1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_LAN_TX_RX_H_ 5 #define _ICE_LAN_TX_RX_H_ 6 7 union ice_32byte_rx_desc { 8 struct { 9 __le64 pkt_addr; /* Packet buffer address */ 10 __le64 hdr_addr; /* Header buffer address */ 11 /* bit 0 of hdr_addr is DD bit */ 12 __le64 rsvd1; 13 __le64 rsvd2; 14 } read; 15 struct { 16 struct { 17 struct { 18 __le16 mirroring_status; 19 __le16 l2tag1; 20 } lo_dword; 21 union { 22 __le32 rss; /* RSS Hash */ 23 __le32 fd_id; /* Flow Director filter ID */ 24 } hi_dword; 25 } qword0; 26 struct { 27 /* status/error/PTYPE/length */ 28 __le64 status_error_len; 29 } qword1; 30 struct { 31 __le16 ext_status; /* extended status */ 32 __le16 rsvd; 33 __le16 l2tag2_1; 34 __le16 l2tag2_2; 35 } qword2; 36 struct { 37 __le32 reserved; 38 __le32 fd_id; 39 } qword3; 40 } wb; /* writeback */ 41 }; 42 43 struct ice_fltr_desc { 44 __le64 qidx_compq_space_stat; 45 __le64 dtype_cmd_vsi_fdid; 46 }; 47 48 #define ICE_FXD_FLTR_QW0_QINDEX_S 0 49 #define ICE_FXD_FLTR_QW0_QINDEX_M (0x7FFULL << ICE_FXD_FLTR_QW0_QINDEX_S) 50 #define ICE_FXD_FLTR_QW0_COMP_Q_S 11 51 #define ICE_FXD_FLTR_QW0_COMP_Q_M BIT_ULL(ICE_FXD_FLTR_QW0_COMP_Q_S) 52 #define ICE_FXD_FLTR_QW0_COMP_Q_ZERO 0x0ULL 53 54 #define ICE_FXD_FLTR_QW0_COMP_REPORT_S 12 55 #define ICE_FXD_FLTR_QW0_COMP_REPORT_M \ 56 (0x3ULL << ICE_FXD_FLTR_QW0_COMP_REPORT_S) 57 #define ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL 0x1ULL 58 59 #define ICE_FXD_FLTR_QW0_FD_SPACE_S 14 60 #define ICE_FXD_FLTR_QW0_FD_SPACE_M (0x3ULL << ICE_FXD_FLTR_QW0_FD_SPACE_S) 61 #define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST 0x2ULL 62 63 #define ICE_FXD_FLTR_QW0_STAT_CNT_S 16 64 #define ICE_FXD_FLTR_QW0_STAT_CNT_M \ 65 (0x1FFFULL << ICE_FXD_FLTR_QW0_STAT_CNT_S) 66 #define ICE_FXD_FLTR_QW0_STAT_ENA_S 29 67 #define ICE_FXD_FLTR_QW0_STAT_ENA_M (0x3ULL << ICE_FXD_FLTR_QW0_STAT_ENA_S) 68 #define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS 0x1ULL 69 70 #define ICE_FXD_FLTR_QW0_EVICT_ENA_S 31 71 #define ICE_FXD_FLTR_QW0_EVICT_ENA_M BIT_ULL(ICE_FXD_FLTR_QW0_EVICT_ENA_S) 72 #define ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE 0x0ULL 73 #define ICE_FXD_FLTR_QW0_EVICT_ENA_TRUE 0x1ULL 74 75 #define ICE_FXD_FLTR_QW0_TO_Q_S 32 76 #define ICE_FXD_FLTR_QW0_TO_Q_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_S) 77 #define ICE_FXD_FLTR_QW0_TO_Q_EQUALS_QINDEX 0x0ULL 78 79 #define ICE_FXD_FLTR_QW0_TO_Q_PRI_S 35 80 #define ICE_FXD_FLTR_QW0_TO_Q_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_PRI_S) 81 #define ICE_FXD_FLTR_QW0_TO_Q_PRIO1 0x1ULL 82 83 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_S 38 84 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_M \ 85 (0x3ULL << ICE_FXD_FLTR_QW0_DPU_RECIPE_S) 86 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_DFLT 0x0ULL 87 88 #define ICE_FXD_FLTR_QW0_DROP_S 40 89 #define ICE_FXD_FLTR_QW0_DROP_M BIT_ULL(ICE_FXD_FLTR_QW0_DROP_S) 90 #define ICE_FXD_FLTR_QW0_DROP_NO 0x0ULL 91 #define ICE_FXD_FLTR_QW0_DROP_YES 0x1ULL 92 93 #define ICE_FXD_FLTR_QW0_FLEX_PRI_S 41 94 #define ICE_FXD_FLTR_QW0_FLEX_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_FLEX_PRI_S) 95 #define ICE_FXD_FLTR_QW0_FLEX_PRI_NONE 0x0ULL 96 97 #define ICE_FXD_FLTR_QW0_FLEX_MDID_S 44 98 #define ICE_FXD_FLTR_QW0_FLEX_MDID_M (0xFULL << ICE_FXD_FLTR_QW0_FLEX_MDID_S) 99 #define ICE_FXD_FLTR_QW0_FLEX_MDID0 0x0ULL 100 101 #define ICE_FXD_FLTR_QW0_FLEX_VAL_S 48 102 #define ICE_FXD_FLTR_QW0_FLEX_VAL_M \ 103 (0xFFFFULL << ICE_FXD_FLTR_QW0_FLEX_VAL_S) 104 #define ICE_FXD_FLTR_QW0_FLEX_VAL0 0x0ULL 105 106 #define ICE_FXD_FLTR_QW1_DTYPE_S 0 107 #define ICE_FXD_FLTR_QW1_DTYPE_M (0xFULL << ICE_FXD_FLTR_QW1_DTYPE_S) 108 #define ICE_FXD_FLTR_QW1_PCMD_S 4 109 #define ICE_FXD_FLTR_QW1_PCMD_M BIT_ULL(ICE_FXD_FLTR_QW1_PCMD_S) 110 #define ICE_FXD_FLTR_QW1_PCMD_ADD 0x0ULL 111 #define ICE_FXD_FLTR_QW1_PCMD_REMOVE 0x1ULL 112 113 #define ICE_FXD_FLTR_QW1_PROF_PRI_S 5 114 #define ICE_FXD_FLTR_QW1_PROF_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_PROF_PRI_S) 115 #define ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO 0x0ULL 116 117 #define ICE_FXD_FLTR_QW1_PROF_S 8 118 #define ICE_FXD_FLTR_QW1_PROF_M (0x3FULL << ICE_FXD_FLTR_QW1_PROF_S) 119 #define ICE_FXD_FLTR_QW1_PROF_ZERO 0x0ULL 120 121 #define ICE_FXD_FLTR_QW1_FD_VSI_S 14 122 #define ICE_FXD_FLTR_QW1_FD_VSI_M (0x3FFULL << ICE_FXD_FLTR_QW1_FD_VSI_S) 123 #define ICE_FXD_FLTR_QW1_SWAP_S 24 124 #define ICE_FXD_FLTR_QW1_SWAP_M BIT_ULL(ICE_FXD_FLTR_QW1_SWAP_S) 125 #define ICE_FXD_FLTR_QW1_SWAP_NOT_SET 0x0ULL 126 #define ICE_FXD_FLTR_QW1_SWAP_SET 0x1ULL 127 128 #define ICE_FXD_FLTR_QW1_FDID_PRI_S 25 129 #define ICE_FXD_FLTR_QW1_FDID_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S) 130 #define ICE_FXD_FLTR_QW1_FDID_PRI_ONE 0x1ULL 131 132 #define ICE_FXD_FLTR_QW1_FDID_MDID_S 28 133 #define ICE_FXD_FLTR_QW1_FDID_MDID_M (0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S) 134 #define ICE_FXD_FLTR_QW1_FDID_MDID_FD 0x05ULL 135 136 #define ICE_FXD_FLTR_QW1_FDID_S 32 137 #define ICE_FXD_FLTR_QW1_FDID_M \ 138 (0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S) 139 #define ICE_FXD_FLTR_QW1_FDID_ZERO 0x0ULL 140 141 struct ice_rx_ptype_decoded { 142 u32 ptype:10; 143 u32 known:1; 144 u32 outer_ip:1; 145 u32 outer_ip_ver:2; 146 u32 outer_frag:1; 147 u32 tunnel_type:3; 148 u32 tunnel_end_prot:2; 149 u32 tunnel_end_frag:1; 150 u32 inner_prot:4; 151 u32 payload_layer:3; 152 }; 153 154 enum ice_rx_ptype_outer_ip { 155 ICE_RX_PTYPE_OUTER_L2 = 0, 156 ICE_RX_PTYPE_OUTER_IP = 1, 157 }; 158 159 enum ice_rx_ptype_outer_ip_ver { 160 ICE_RX_PTYPE_OUTER_NONE = 0, 161 ICE_RX_PTYPE_OUTER_IPV4 = 1, 162 ICE_RX_PTYPE_OUTER_IPV6 = 2, 163 }; 164 165 enum ice_rx_ptype_outer_fragmented { 166 ICE_RX_PTYPE_NOT_FRAG = 0, 167 ICE_RX_PTYPE_FRAG = 1, 168 }; 169 170 enum ice_rx_ptype_tunnel_type { 171 ICE_RX_PTYPE_TUNNEL_NONE = 0, 172 ICE_RX_PTYPE_TUNNEL_IP_IP = 1, 173 ICE_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 174 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 175 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 176 }; 177 178 enum ice_rx_ptype_tunnel_end_prot { 179 ICE_RX_PTYPE_TUNNEL_END_NONE = 0, 180 ICE_RX_PTYPE_TUNNEL_END_IPV4 = 1, 181 ICE_RX_PTYPE_TUNNEL_END_IPV6 = 2, 182 }; 183 184 enum ice_rx_ptype_inner_prot { 185 ICE_RX_PTYPE_INNER_PROT_NONE = 0, 186 ICE_RX_PTYPE_INNER_PROT_UDP = 1, 187 ICE_RX_PTYPE_INNER_PROT_TCP = 2, 188 ICE_RX_PTYPE_INNER_PROT_SCTP = 3, 189 ICE_RX_PTYPE_INNER_PROT_ICMP = 4, 190 ICE_RX_PTYPE_INNER_PROT_TIMESYNC = 5, 191 }; 192 193 enum ice_rx_ptype_payload_layer { 194 ICE_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 195 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 196 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 197 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 198 }; 199 200 /* Rx Flex Descriptor 201 * This descriptor is used instead of the legacy version descriptor when 202 * ice_rlan_ctx.adv_desc is set 203 */ 204 union ice_32b_rx_flex_desc { 205 struct { 206 __le64 pkt_addr; /* Packet buffer address */ 207 __le64 hdr_addr; /* Header buffer address */ 208 /* bit 0 of hdr_addr is DD bit */ 209 __le64 rsvd1; 210 __le64 rsvd2; 211 } read; 212 struct { 213 /* Qword 0 */ 214 u8 rxdid; /* descriptor builder profile ID */ 215 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */ 216 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */ 217 __le16 pkt_len; /* [15:14] are reserved */ 218 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */ 219 /* sph=[11:11] */ 220 /* ff1/ext=[15:12] */ 221 222 /* Qword 1 */ 223 __le16 status_error0; 224 __le16 l2tag1; 225 __le16 flex_meta0; 226 __le16 flex_meta1; 227 228 /* Qword 2 */ 229 __le16 status_error1; 230 u8 flex_flags2; 231 u8 time_stamp_low; 232 __le16 l2tag2_1st; 233 __le16 l2tag2_2nd; 234 235 /* Qword 3 */ 236 __le16 flex_meta2; 237 __le16 flex_meta3; 238 union { 239 struct { 240 __le16 flex_meta4; 241 __le16 flex_meta5; 242 } flex; 243 __le32 ts_high; 244 } flex_ts; 245 } wb; /* writeback */ 246 }; 247 248 /* Rx Flex Descriptor NIC Profile 249 * This descriptor corresponds to RxDID 2 which contains 250 * metadata fields for RSS, flow ID and timestamp info 251 */ 252 struct ice_32b_rx_flex_desc_nic { 253 /* Qword 0 */ 254 u8 rxdid; 255 u8 mir_id_umb_cast; 256 __le16 ptype_flexi_flags0; 257 __le16 pkt_len; 258 __le16 hdr_len_sph_flex_flags1; 259 260 /* Qword 1 */ 261 __le16 status_error0; 262 __le16 l2tag1; 263 __le32 rss_hash; 264 265 /* Qword 2 */ 266 __le16 status_error1; 267 u8 flexi_flags2; 268 u8 ts_low; 269 __le16 l2tag2_1st; 270 __le16 l2tag2_2nd; 271 272 /* Qword 3 */ 273 __le32 flow_id; 274 union { 275 struct { 276 __le16 vlan_id; 277 __le16 flow_id_ipv6; 278 } flex; 279 __le32 ts_high; 280 } flex_ts; 281 }; 282 283 /* Receive Flex Descriptor profile IDs: There are a total 284 * of 64 profiles where profile IDs 0/1 are for legacy; and 285 * profiles 2-63 are flex profiles that can be programmed 286 * with a specific metadata (profile 7 reserved for HW) 287 */ 288 enum ice_rxdid { 289 ICE_RXDID_LEGACY_0 = 0, 290 ICE_RXDID_LEGACY_1 = 1, 291 ICE_RXDID_FLEX_NIC = 2, 292 ICE_RXDID_FLEX_NIC_2 = 6, 293 ICE_RXDID_HW = 7, 294 ICE_RXDID_LAST = 63, 295 }; 296 297 /* Receive Flex Descriptor Rx opcode values */ 298 #define ICE_RX_OPC_MDID 0x01 299 300 /* Receive Descriptor MDID values that access packet flags */ 301 enum ice_flex_mdid_pkt_flags { 302 ICE_RX_MDID_PKT_FLAGS_15_0 = 20, 303 ICE_RX_MDID_PKT_FLAGS_31_16, 304 ICE_RX_MDID_PKT_FLAGS_47_32, 305 ICE_RX_MDID_PKT_FLAGS_63_48, 306 }; 307 308 /* Receive Descriptor MDID values */ 309 enum ice_flex_rx_mdid { 310 ICE_RX_MDID_FLOW_ID_LOWER = 5, 311 ICE_RX_MDID_FLOW_ID_HIGH, 312 ICE_RX_MDID_SRC_VSI = 19, 313 ICE_RX_MDID_HASH_LOW = 56, 314 ICE_RX_MDID_HASH_HIGH, 315 }; 316 317 /* Rx/Tx Flag64 packet flag bits */ 318 enum ice_flg64_bits { 319 ICE_FLG_PKT_DSI = 0, 320 ICE_FLG_EVLAN_x8100 = 14, 321 ICE_FLG_EVLAN_x9100, 322 ICE_FLG_VLAN_x8100, 323 ICE_FLG_TNL_MAC = 22, 324 ICE_FLG_TNL_VLAN, 325 ICE_FLG_PKT_FRG, 326 ICE_FLG_FIN = 32, 327 ICE_FLG_SYN, 328 ICE_FLG_RST, 329 ICE_FLG_TNL0 = 38, 330 ICE_FLG_TNL1, 331 ICE_FLG_TNL2, 332 ICE_FLG_UDP_GRE, 333 ICE_FLG_RSVD = 63 334 }; 335 336 /* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */ 337 #define ICE_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */ 338 339 /* for ice_32byte_rx_flex_desc.pkt_length member */ 340 #define ICE_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */ 341 342 enum ice_rx_flex_desc_status_error_0_bits { 343 /* Note: These are predefined bit offsets */ 344 ICE_RX_FLEX_DESC_STATUS0_DD_S = 0, 345 ICE_RX_FLEX_DESC_STATUS0_EOF_S, 346 ICE_RX_FLEX_DESC_STATUS0_HBO_S, 347 ICE_RX_FLEX_DESC_STATUS0_L3L4P_S, 348 ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S, 349 ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S, 350 ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S, 351 ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S, 352 ICE_RX_FLEX_DESC_STATUS0_LPBK_S, 353 ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S, 354 ICE_RX_FLEX_DESC_STATUS0_RXE_S, 355 ICE_RX_FLEX_DESC_STATUS0_CRCP_S, 356 ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S, 357 ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S, 358 ICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S, 359 ICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S, 360 ICE_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */ 361 }; 362 363 enum ice_rx_flex_desc_status_error_1_bits { 364 /* Note: These are predefined bit offsets */ 365 ICE_RX_FLEX_DESC_STATUS1_NAT_S = 4, 366 ICE_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */ 367 }; 368 369 #define ICE_RXQ_CTX_SIZE_DWORDS 8 370 #define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32)) 371 #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22 372 #define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS 5 373 #define GLTCLAN_CQ_CNTX(i, CQ) (GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800)) 374 375 /* RLAN Rx queue context data 376 * 377 * The sizes of the variables may be larger than needed due to crossing byte 378 * boundaries. If we do not have the width of the variable set to the correct 379 * size then we could end up shifting bits off the top of the variable when the 380 * variable is at the top of a byte and crosses over into the next byte. 381 */ 382 struct ice_rlan_ctx { 383 u16 head; 384 u16 cpuid; /* bigger than needed, see above for reason */ 385 #define ICE_RLAN_BASE_S 7 386 u64 base; 387 u16 qlen; 388 #define ICE_RLAN_CTX_DBUF_S 7 389 u16 dbuf; /* bigger than needed, see above for reason */ 390 #define ICE_RLAN_CTX_HBUF_S 6 391 u16 hbuf; /* bigger than needed, see above for reason */ 392 u8 dtype; 393 u8 dsize; 394 u8 crcstrip; 395 u8 l2tsel; 396 u8 hsplit_0; 397 u8 hsplit_1; 398 u8 showiv; 399 u32 rxmax; /* bigger than needed, see above for reason */ 400 u8 tphrdesc_ena; 401 u8 tphwdesc_ena; 402 u8 tphdata_ena; 403 u8 tphhead_ena; 404 u16 lrxqthresh; /* bigger than needed, see above for reason */ 405 u8 prefena; /* NOTE: normally must be set to 1 at init */ 406 }; 407 408 struct ice_ctx_ele { 409 u16 offset; 410 u16 size_of; 411 u16 width; 412 u16 lsb; 413 }; 414 415 #define ICE_CTX_STORE(_struct, _ele, _width, _lsb) { \ 416 .offset = offsetof(struct _struct, _ele), \ 417 .size_of = sizeof_field(struct _struct, _ele), \ 418 .width = _width, \ 419 .lsb = _lsb, \ 420 } 421 422 /* for hsplit_0 field of Rx RLAN context */ 423 enum ice_rlan_ctx_rx_hsplit_0 { 424 ICE_RLAN_RX_HSPLIT_0_NO_SPLIT = 0, 425 ICE_RLAN_RX_HSPLIT_0_SPLIT_L2 = 1, 426 ICE_RLAN_RX_HSPLIT_0_SPLIT_IP = 2, 427 ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP = 4, 428 ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP = 8, 429 }; 430 431 /* for hsplit_1 field of Rx RLAN context */ 432 enum ice_rlan_ctx_rx_hsplit_1 { 433 ICE_RLAN_RX_HSPLIT_1_NO_SPLIT = 0, 434 ICE_RLAN_RX_HSPLIT_1_SPLIT_L2 = 1, 435 ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS = 2, 436 }; 437 438 /* Tx Descriptor */ 439 struct ice_tx_desc { 440 __le64 buf_addr; /* Address of descriptor's data buf */ 441 __le64 cmd_type_offset_bsz; 442 }; 443 444 enum ice_tx_desc_dtype_value { 445 ICE_TX_DESC_DTYPE_DATA = 0x0, 446 ICE_TX_DESC_DTYPE_CTX = 0x1, 447 ICE_TX_DESC_DTYPE_FLTR_PROG = 0x8, 448 /* DESC_DONE - HW has completed write-back of descriptor */ 449 ICE_TX_DESC_DTYPE_DESC_DONE = 0xF, 450 }; 451 452 #define ICE_TXD_QW1_CMD_S 4 453 #define ICE_TXD_QW1_CMD_M (0xFFFUL << ICE_TXD_QW1_CMD_S) 454 455 enum ice_tx_desc_cmd_bits { 456 ICE_TX_DESC_CMD_EOP = 0x0001, 457 ICE_TX_DESC_CMD_RS = 0x0002, 458 ICE_TX_DESC_CMD_IL2TAG1 = 0x0008, 459 ICE_TX_DESC_CMD_DUMMY = 0x0010, 460 ICE_TX_DESC_CMD_IIPT_IPV6 = 0x0020, 461 ICE_TX_DESC_CMD_IIPT_IPV4 = 0x0040, 462 ICE_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, 463 ICE_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, 464 ICE_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, 465 ICE_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, 466 ICE_TX_DESC_CMD_RE = 0x0400, 467 }; 468 469 #define ICE_TXD_QW1_OFFSET_S 16 470 #define ICE_TXD_QW1_OFFSET_M (0x3FFFFULL << ICE_TXD_QW1_OFFSET_S) 471 472 enum ice_tx_desc_len_fields { 473 /* Note: These are predefined bit offsets */ 474 ICE_TX_DESC_LEN_MACLEN_S = 0, /* 7 BITS */ 475 ICE_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */ 476 ICE_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */ 477 }; 478 479 #define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S) 480 #define ICE_TXD_QW1_IPLEN_M (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S) 481 #define ICE_TXD_QW1_L4LEN_M (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S) 482 483 /* Tx descriptor field limits in bytes */ 484 #define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \ 485 ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD) 486 #define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \ 487 ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD) 488 #define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \ 489 ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD) 490 491 #define ICE_TXD_QW1_TX_BUF_SZ_S 34 492 #define ICE_TXD_QW1_L2TAG1_S 48 493 494 /* Context descriptors */ 495 struct ice_tx_ctx_desc { 496 __le32 tunneling_params; 497 __le16 l2tag2; 498 __le16 rsvd; 499 __le64 qw1; 500 }; 501 502 #define ICE_TXD_CTX_QW1_CMD_S 4 503 #define ICE_TXD_CTX_QW1_CMD_M (0x7FUL << ICE_TXD_CTX_QW1_CMD_S) 504 505 #define ICE_TXD_CTX_QW1_TSO_LEN_S 30 506 #define ICE_TXD_CTX_QW1_TSO_LEN_M \ 507 (0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S) 508 509 #define ICE_TXD_CTX_QW1_MSS_S 50 510 511 enum ice_tx_ctx_desc_cmd_bits { 512 ICE_TX_CTX_DESC_TSO = 0x01, 513 ICE_TX_CTX_DESC_TSYN = 0x02, 514 ICE_TX_CTX_DESC_IL2TAG2 = 0x04, 515 ICE_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 516 ICE_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 517 ICE_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 518 ICE_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 519 ICE_TX_CTX_DESC_SWTCH_VSI = 0x30, 520 ICE_TX_CTX_DESC_RESERVED = 0x40 521 }; 522 523 enum ice_tx_ctx_desc_eipt_offload { 524 ICE_TX_CTX_EIPT_NONE = 0x0, 525 ICE_TX_CTX_EIPT_IPV6 = 0x1, 526 ICE_TX_CTX_EIPT_IPV4_NO_CSUM = 0x2, 527 ICE_TX_CTX_EIPT_IPV4 = 0x3 528 }; 529 530 #define ICE_TXD_CTX_QW0_EIPLEN_S 2 531 532 #define ICE_TXD_CTX_QW0_L4TUNT_S 9 533 534 #define ICE_TXD_CTX_UDP_TUNNELING BIT_ULL(ICE_TXD_CTX_QW0_L4TUNT_S) 535 #define ICE_TXD_CTX_GRE_TUNNELING (0x2ULL << ICE_TXD_CTX_QW0_L4TUNT_S) 536 537 #define ICE_TXD_CTX_QW0_NATLEN_S 12 538 539 #define ICE_TXD_CTX_QW0_L4T_CS_S 23 540 #define ICE_TXD_CTX_QW0_L4T_CS_M BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S) 541 542 #define ICE_LAN_TXQ_MAX_QGRPS 127 543 #define ICE_LAN_TXQ_MAX_QDIS 1023 544 545 /* Tx queue context data 546 * 547 * The sizes of the variables may be larger than needed due to crossing byte 548 * boundaries. If we do not have the width of the variable set to the correct 549 * size then we could end up shifting bits off the top of the variable when the 550 * variable is at the top of a byte and crosses over into the next byte. 551 */ 552 struct ice_tlan_ctx { 553 #define ICE_TLAN_CTX_BASE_S 7 554 u64 base; /* base is defined in 128-byte units */ 555 u8 port_num; 556 u16 cgd_num; /* bigger than needed, see above for reason */ 557 u8 pf_num; 558 u16 vmvf_num; 559 u8 vmvf_type; 560 #define ICE_TLAN_CTX_VMVF_TYPE_VF 0 561 #define ICE_TLAN_CTX_VMVF_TYPE_VMQ 1 562 #define ICE_TLAN_CTX_VMVF_TYPE_PF 2 563 u16 src_vsi; 564 u8 tsyn_ena; 565 u8 internal_usage_flag; 566 u8 alt_vlan; 567 u16 cpuid; /* bigger than needed, see above for reason */ 568 u8 wb_mode; 569 u8 tphrd_desc; 570 u8 tphrd; 571 u8 tphwr_desc; 572 u16 cmpq_id; 573 u16 qnum_in_func; 574 u8 itr_notification_mode; 575 u8 adjust_prof_id; 576 u32 qlen; /* bigger than needed, see above for reason */ 577 u8 quanta_prof_idx; 578 u8 tso_ena; 579 u16 tso_qnum; 580 u8 legacy_int; 581 u8 drop_ena; 582 u8 cache_prof_idx; 583 u8 pkt_shaper_prof_idx; 584 u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */ 585 }; 586 587 /* macro to make the table lines short */ 588 #define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 589 { PTYPE, \ 590 1, \ 591 ICE_RX_PTYPE_OUTER_##OUTER_IP, \ 592 ICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 593 ICE_RX_PTYPE_##OUTER_FRAG, \ 594 ICE_RX_PTYPE_TUNNEL_##T, \ 595 ICE_RX_PTYPE_TUNNEL_END_##TE, \ 596 ICE_RX_PTYPE_##TEF, \ 597 ICE_RX_PTYPE_INNER_PROT_##I, \ 598 ICE_RX_PTYPE_PAYLOAD_LAYER_##PL } 599 600 #define ICE_PTT_UNUSED_ENTRY(PTYPE) { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 601 602 /* shorter macros makes the table fit but are terse */ 603 #define ICE_RX_PTYPE_NOF ICE_RX_PTYPE_NOT_FRAG 604 #define ICE_RX_PTYPE_FRG ICE_RX_PTYPE_FRAG 605 606 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 607 static const struct ice_rx_ptype_decoded ice_ptype_lkup[] = { 608 /* L2 Packet types */ 609 ICE_PTT_UNUSED_ENTRY(0), 610 ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 611 ICE_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 612 ICE_PTT_UNUSED_ENTRY(3), 613 ICE_PTT_UNUSED_ENTRY(4), 614 ICE_PTT_UNUSED_ENTRY(5), 615 ICE_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 616 ICE_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 617 ICE_PTT_UNUSED_ENTRY(8), 618 ICE_PTT_UNUSED_ENTRY(9), 619 ICE_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 620 ICE_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 621 ICE_PTT_UNUSED_ENTRY(12), 622 ICE_PTT_UNUSED_ENTRY(13), 623 ICE_PTT_UNUSED_ENTRY(14), 624 ICE_PTT_UNUSED_ENTRY(15), 625 ICE_PTT_UNUSED_ENTRY(16), 626 ICE_PTT_UNUSED_ENTRY(17), 627 ICE_PTT_UNUSED_ENTRY(18), 628 ICE_PTT_UNUSED_ENTRY(19), 629 ICE_PTT_UNUSED_ENTRY(20), 630 ICE_PTT_UNUSED_ENTRY(21), 631 632 /* Non Tunneled IPv4 */ 633 ICE_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 634 ICE_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 635 ICE_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 636 ICE_PTT_UNUSED_ENTRY(25), 637 ICE_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 638 ICE_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 639 ICE_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 640 641 /* IPv4 --> IPv4 */ 642 ICE_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 643 ICE_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 644 ICE_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 645 ICE_PTT_UNUSED_ENTRY(32), 646 ICE_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 647 ICE_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 648 ICE_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 649 650 /* IPv4 --> IPv6 */ 651 ICE_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 652 ICE_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 653 ICE_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 654 ICE_PTT_UNUSED_ENTRY(39), 655 ICE_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 656 ICE_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 657 ICE_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 658 659 /* IPv4 --> GRE/NAT */ 660 ICE_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 661 662 /* IPv4 --> GRE/NAT --> IPv4 */ 663 ICE_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 664 ICE_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 665 ICE_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 666 ICE_PTT_UNUSED_ENTRY(47), 667 ICE_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 668 ICE_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 669 ICE_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 670 671 /* IPv4 --> GRE/NAT --> IPv6 */ 672 ICE_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 673 ICE_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 674 ICE_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 675 ICE_PTT_UNUSED_ENTRY(54), 676 ICE_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 677 ICE_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 678 ICE_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 679 680 /* IPv4 --> GRE/NAT --> MAC */ 681 ICE_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 682 683 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 684 ICE_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 685 ICE_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 686 ICE_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 687 ICE_PTT_UNUSED_ENTRY(62), 688 ICE_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 689 ICE_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 690 ICE_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 691 692 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 693 ICE_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 694 ICE_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 695 ICE_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 696 ICE_PTT_UNUSED_ENTRY(69), 697 ICE_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 698 ICE_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 699 ICE_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 700 701 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 702 ICE_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 703 704 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 705 ICE_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 706 ICE_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 707 ICE_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 708 ICE_PTT_UNUSED_ENTRY(77), 709 ICE_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 710 ICE_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 711 ICE_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 712 713 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 714 ICE_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 715 ICE_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 716 ICE_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 717 ICE_PTT_UNUSED_ENTRY(84), 718 ICE_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 719 ICE_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 720 ICE_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 721 722 /* Non Tunneled IPv6 */ 723 ICE_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 724 ICE_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 725 ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3), 726 ICE_PTT_UNUSED_ENTRY(91), 727 ICE_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 728 ICE_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 729 ICE_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 730 731 /* IPv6 --> IPv4 */ 732 ICE_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 733 ICE_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 734 ICE_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 735 ICE_PTT_UNUSED_ENTRY(98), 736 ICE_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 737 ICE_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 738 ICE_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 739 740 /* IPv6 --> IPv6 */ 741 ICE_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 742 ICE_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 743 ICE_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 744 ICE_PTT_UNUSED_ENTRY(105), 745 ICE_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 746 ICE_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 747 ICE_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 748 749 /* IPv6 --> GRE/NAT */ 750 ICE_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 751 752 /* IPv6 --> GRE/NAT -> IPv4 */ 753 ICE_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 754 ICE_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 755 ICE_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 756 ICE_PTT_UNUSED_ENTRY(113), 757 ICE_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 758 ICE_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 759 ICE_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 760 761 /* IPv6 --> GRE/NAT -> IPv6 */ 762 ICE_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 763 ICE_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 764 ICE_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 765 ICE_PTT_UNUSED_ENTRY(120), 766 ICE_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 767 ICE_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 768 ICE_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 769 770 /* IPv6 --> GRE/NAT -> MAC */ 771 ICE_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 772 773 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 774 ICE_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 775 ICE_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 776 ICE_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 777 ICE_PTT_UNUSED_ENTRY(128), 778 ICE_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 779 ICE_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 780 ICE_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 781 782 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 783 ICE_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 784 ICE_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 785 ICE_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 786 ICE_PTT_UNUSED_ENTRY(135), 787 ICE_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 788 ICE_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 789 ICE_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 790 791 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 792 ICE_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 793 794 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 795 ICE_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 796 ICE_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 797 ICE_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 798 ICE_PTT_UNUSED_ENTRY(143), 799 ICE_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 800 ICE_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 801 ICE_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 802 803 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 804 ICE_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 805 ICE_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 806 ICE_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 807 ICE_PTT_UNUSED_ENTRY(150), 808 ICE_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 809 ICE_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 810 ICE_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 811 812 /* unused entries */ 813 ICE_PTT_UNUSED_ENTRY(154), 814 ICE_PTT_UNUSED_ENTRY(155), 815 ICE_PTT_UNUSED_ENTRY(156), 816 ICE_PTT_UNUSED_ENTRY(157), 817 ICE_PTT_UNUSED_ENTRY(158), 818 ICE_PTT_UNUSED_ENTRY(159), 819 820 ICE_PTT_UNUSED_ENTRY(160), 821 ICE_PTT_UNUSED_ENTRY(161), 822 ICE_PTT_UNUSED_ENTRY(162), 823 ICE_PTT_UNUSED_ENTRY(163), 824 ICE_PTT_UNUSED_ENTRY(164), 825 ICE_PTT_UNUSED_ENTRY(165), 826 ICE_PTT_UNUSED_ENTRY(166), 827 ICE_PTT_UNUSED_ENTRY(167), 828 ICE_PTT_UNUSED_ENTRY(168), 829 ICE_PTT_UNUSED_ENTRY(169), 830 831 ICE_PTT_UNUSED_ENTRY(170), 832 ICE_PTT_UNUSED_ENTRY(171), 833 ICE_PTT_UNUSED_ENTRY(172), 834 ICE_PTT_UNUSED_ENTRY(173), 835 ICE_PTT_UNUSED_ENTRY(174), 836 ICE_PTT_UNUSED_ENTRY(175), 837 ICE_PTT_UNUSED_ENTRY(176), 838 ICE_PTT_UNUSED_ENTRY(177), 839 ICE_PTT_UNUSED_ENTRY(178), 840 ICE_PTT_UNUSED_ENTRY(179), 841 842 ICE_PTT_UNUSED_ENTRY(180), 843 ICE_PTT_UNUSED_ENTRY(181), 844 ICE_PTT_UNUSED_ENTRY(182), 845 ICE_PTT_UNUSED_ENTRY(183), 846 ICE_PTT_UNUSED_ENTRY(184), 847 ICE_PTT_UNUSED_ENTRY(185), 848 ICE_PTT_UNUSED_ENTRY(186), 849 ICE_PTT_UNUSED_ENTRY(187), 850 ICE_PTT_UNUSED_ENTRY(188), 851 ICE_PTT_UNUSED_ENTRY(189), 852 853 ICE_PTT_UNUSED_ENTRY(190), 854 ICE_PTT_UNUSED_ENTRY(191), 855 ICE_PTT_UNUSED_ENTRY(192), 856 ICE_PTT_UNUSED_ENTRY(193), 857 ICE_PTT_UNUSED_ENTRY(194), 858 ICE_PTT_UNUSED_ENTRY(195), 859 ICE_PTT_UNUSED_ENTRY(196), 860 ICE_PTT_UNUSED_ENTRY(197), 861 ICE_PTT_UNUSED_ENTRY(198), 862 ICE_PTT_UNUSED_ENTRY(199), 863 864 ICE_PTT_UNUSED_ENTRY(200), 865 ICE_PTT_UNUSED_ENTRY(201), 866 ICE_PTT_UNUSED_ENTRY(202), 867 ICE_PTT_UNUSED_ENTRY(203), 868 ICE_PTT_UNUSED_ENTRY(204), 869 ICE_PTT_UNUSED_ENTRY(205), 870 ICE_PTT_UNUSED_ENTRY(206), 871 ICE_PTT_UNUSED_ENTRY(207), 872 ICE_PTT_UNUSED_ENTRY(208), 873 ICE_PTT_UNUSED_ENTRY(209), 874 875 ICE_PTT_UNUSED_ENTRY(210), 876 ICE_PTT_UNUSED_ENTRY(211), 877 ICE_PTT_UNUSED_ENTRY(212), 878 ICE_PTT_UNUSED_ENTRY(213), 879 ICE_PTT_UNUSED_ENTRY(214), 880 ICE_PTT_UNUSED_ENTRY(215), 881 ICE_PTT_UNUSED_ENTRY(216), 882 ICE_PTT_UNUSED_ENTRY(217), 883 ICE_PTT_UNUSED_ENTRY(218), 884 ICE_PTT_UNUSED_ENTRY(219), 885 886 ICE_PTT_UNUSED_ENTRY(220), 887 ICE_PTT_UNUSED_ENTRY(221), 888 ICE_PTT_UNUSED_ENTRY(222), 889 ICE_PTT_UNUSED_ENTRY(223), 890 ICE_PTT_UNUSED_ENTRY(224), 891 ICE_PTT_UNUSED_ENTRY(225), 892 ICE_PTT_UNUSED_ENTRY(226), 893 ICE_PTT_UNUSED_ENTRY(227), 894 ICE_PTT_UNUSED_ENTRY(228), 895 ICE_PTT_UNUSED_ENTRY(229), 896 897 ICE_PTT_UNUSED_ENTRY(230), 898 ICE_PTT_UNUSED_ENTRY(231), 899 ICE_PTT_UNUSED_ENTRY(232), 900 ICE_PTT_UNUSED_ENTRY(233), 901 ICE_PTT_UNUSED_ENTRY(234), 902 ICE_PTT_UNUSED_ENTRY(235), 903 ICE_PTT_UNUSED_ENTRY(236), 904 ICE_PTT_UNUSED_ENTRY(237), 905 ICE_PTT_UNUSED_ENTRY(238), 906 ICE_PTT_UNUSED_ENTRY(239), 907 908 ICE_PTT_UNUSED_ENTRY(240), 909 ICE_PTT_UNUSED_ENTRY(241), 910 ICE_PTT_UNUSED_ENTRY(242), 911 ICE_PTT_UNUSED_ENTRY(243), 912 ICE_PTT_UNUSED_ENTRY(244), 913 ICE_PTT_UNUSED_ENTRY(245), 914 ICE_PTT_UNUSED_ENTRY(246), 915 ICE_PTT_UNUSED_ENTRY(247), 916 ICE_PTT_UNUSED_ENTRY(248), 917 ICE_PTT_UNUSED_ENTRY(249), 918 919 ICE_PTT_UNUSED_ENTRY(250), 920 ICE_PTT_UNUSED_ENTRY(251), 921 ICE_PTT_UNUSED_ENTRY(252), 922 ICE_PTT_UNUSED_ENTRY(253), 923 ICE_PTT_UNUSED_ENTRY(254), 924 ICE_PTT_UNUSED_ENTRY(255), 925 }; 926 927 static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype) 928 { 929 return ice_ptype_lkup[ptype]; 930 } 931 932 #define ICE_LINK_SPEED_UNKNOWN 0 933 #define ICE_LINK_SPEED_10MBPS 10 934 #define ICE_LINK_SPEED_100MBPS 100 935 #define ICE_LINK_SPEED_1000MBPS 1000 936 #define ICE_LINK_SPEED_2500MBPS 2500 937 #define ICE_LINK_SPEED_5000MBPS 5000 938 #define ICE_LINK_SPEED_10000MBPS 10000 939 #define ICE_LINK_SPEED_20000MBPS 20000 940 #define ICE_LINK_SPEED_25000MBPS 25000 941 #define ICE_LINK_SPEED_40000MBPS 40000 942 #define ICE_LINK_SPEED_50000MBPS 50000 943 #define ICE_LINK_SPEED_100000MBPS 100000 944 945 #endif /* _ICE_LAN_TX_RX_H_ */ 946