1cdedef59SAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 2cdedef59SAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 3cdedef59SAnirudh Venkataramanan 4cdedef59SAnirudh Venkataramanan #ifndef _ICE_LAN_TX_RX_H_ 5cdedef59SAnirudh Venkataramanan #define _ICE_LAN_TX_RX_H_ 6cdedef59SAnirudh Venkataramanan 7cdedef59SAnirudh Venkataramanan union ice_32byte_rx_desc { 8cdedef59SAnirudh Venkataramanan struct { 9cdedef59SAnirudh Venkataramanan __le64 pkt_addr; /* Packet buffer address */ 10cdedef59SAnirudh Venkataramanan __le64 hdr_addr; /* Header buffer address */ 11cdedef59SAnirudh Venkataramanan /* bit 0 of hdr_addr is DD bit */ 12cdedef59SAnirudh Venkataramanan __le64 rsvd1; 13cdedef59SAnirudh Venkataramanan __le64 rsvd2; 14cdedef59SAnirudh Venkataramanan } read; 15cdedef59SAnirudh Venkataramanan struct { 16cdedef59SAnirudh Venkataramanan struct { 17cdedef59SAnirudh Venkataramanan struct { 18cdedef59SAnirudh Venkataramanan __le16 mirroring_status; 19cdedef59SAnirudh Venkataramanan __le16 l2tag1; 20cdedef59SAnirudh Venkataramanan } lo_dword; 21cdedef59SAnirudh Venkataramanan union { 22cdedef59SAnirudh Venkataramanan __le32 rss; /* RSS Hash */ 23cdedef59SAnirudh Venkataramanan __le32 fd_id; /* Flow Director filter id */ 24cdedef59SAnirudh Venkataramanan } hi_dword; 25cdedef59SAnirudh Venkataramanan } qword0; 26cdedef59SAnirudh Venkataramanan struct { 27cdedef59SAnirudh Venkataramanan /* status/error/PTYPE/length */ 28cdedef59SAnirudh Venkataramanan __le64 status_error_len; 29cdedef59SAnirudh Venkataramanan } qword1; 30cdedef59SAnirudh Venkataramanan struct { 31cdedef59SAnirudh Venkataramanan __le16 ext_status; /* extended status */ 32cdedef59SAnirudh Venkataramanan __le16 rsvd; 33cdedef59SAnirudh Venkataramanan __le16 l2tag2_1; 34cdedef59SAnirudh Venkataramanan __le16 l2tag2_2; 35cdedef59SAnirudh Venkataramanan } qword2; 36cdedef59SAnirudh Venkataramanan struct { 37cdedef59SAnirudh Venkataramanan __le32 reserved; 38cdedef59SAnirudh Venkataramanan __le32 fd_id; 39cdedef59SAnirudh Venkataramanan } qword3; 40cdedef59SAnirudh Venkataramanan } wb; /* writeback */ 41cdedef59SAnirudh Venkataramanan }; 42cdedef59SAnirudh Venkataramanan 43d76a60baSAnirudh Venkataramanan struct ice_rx_ptype_decoded { 44d76a60baSAnirudh Venkataramanan u32 ptype:10; 45d76a60baSAnirudh Venkataramanan u32 known:1; 46d76a60baSAnirudh Venkataramanan u32 outer_ip:1; 47d76a60baSAnirudh Venkataramanan u32 outer_ip_ver:2; 48d76a60baSAnirudh Venkataramanan u32 outer_frag:1; 49d76a60baSAnirudh Venkataramanan u32 tunnel_type:3; 50d76a60baSAnirudh Venkataramanan u32 tunnel_end_prot:2; 51d76a60baSAnirudh Venkataramanan u32 tunnel_end_frag:1; 52d76a60baSAnirudh Venkataramanan u32 inner_prot:4; 53d76a60baSAnirudh Venkataramanan u32 payload_layer:3; 54d76a60baSAnirudh Venkataramanan }; 55d76a60baSAnirudh Venkataramanan 56d76a60baSAnirudh Venkataramanan enum ice_rx_ptype_outer_ip { 57d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_OUTER_L2 = 0, 58d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_OUTER_IP = 1, 59d76a60baSAnirudh Venkataramanan }; 60d76a60baSAnirudh Venkataramanan 61d76a60baSAnirudh Venkataramanan enum ice_rx_ptype_outer_ip_ver { 62d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_OUTER_NONE = 0, 63d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_OUTER_IPV4 = 1, 64d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_OUTER_IPV6 = 2, 65d76a60baSAnirudh Venkataramanan }; 66d76a60baSAnirudh Venkataramanan 67d76a60baSAnirudh Venkataramanan enum ice_rx_ptype_outer_fragmented { 68d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_NOT_FRAG = 0, 69d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_FRAG = 1, 70d76a60baSAnirudh Venkataramanan }; 71d76a60baSAnirudh Venkataramanan 72d76a60baSAnirudh Venkataramanan enum ice_rx_ptype_tunnel_type { 73d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_TUNNEL_NONE = 0, 74d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_TUNNEL_IP_IP = 1, 75d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 76d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 77d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 78d76a60baSAnirudh Venkataramanan }; 79d76a60baSAnirudh Venkataramanan 80d76a60baSAnirudh Venkataramanan enum ice_rx_ptype_tunnel_end_prot { 81d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_TUNNEL_END_NONE = 0, 82d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_TUNNEL_END_IPV4 = 1, 83d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_TUNNEL_END_IPV6 = 2, 84d76a60baSAnirudh Venkataramanan }; 85d76a60baSAnirudh Venkataramanan 86d76a60baSAnirudh Venkataramanan enum ice_rx_ptype_inner_prot { 87d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_INNER_PROT_NONE = 0, 88d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_INNER_PROT_UDP = 1, 89d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_INNER_PROT_TCP = 2, 90d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_INNER_PROT_SCTP = 3, 91d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_INNER_PROT_ICMP = 4, 92d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_INNER_PROT_TIMESYNC = 5, 93d76a60baSAnirudh Venkataramanan }; 94d76a60baSAnirudh Venkataramanan 95d76a60baSAnirudh Venkataramanan enum ice_rx_ptype_payload_layer { 96d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 97d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 98d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 99d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 100d76a60baSAnirudh Venkataramanan }; 101d76a60baSAnirudh Venkataramanan 102cdedef59SAnirudh Venkataramanan /* RX Flex Descriptor 103cdedef59SAnirudh Venkataramanan * This descriptor is used instead of the legacy version descriptor when 104cdedef59SAnirudh Venkataramanan * ice_rlan_ctx.adv_desc is set 105cdedef59SAnirudh Venkataramanan */ 106cdedef59SAnirudh Venkataramanan union ice_32b_rx_flex_desc { 107cdedef59SAnirudh Venkataramanan struct { 108cdedef59SAnirudh Venkataramanan __le64 pkt_addr; /* Packet buffer address */ 109cdedef59SAnirudh Venkataramanan __le64 hdr_addr; /* Header buffer address */ 110cdedef59SAnirudh Venkataramanan /* bit 0 of hdr_addr is DD bit */ 111cdedef59SAnirudh Venkataramanan __le64 rsvd1; 112cdedef59SAnirudh Venkataramanan __le64 rsvd2; 113cdedef59SAnirudh Venkataramanan } read; 114cdedef59SAnirudh Venkataramanan struct { 115cdedef59SAnirudh Venkataramanan /* Qword 0 */ 116cdedef59SAnirudh Venkataramanan u8 rxdid; /* descriptor builder profile id */ 117cdedef59SAnirudh Venkataramanan u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */ 118cdedef59SAnirudh Venkataramanan __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */ 119cdedef59SAnirudh Venkataramanan __le16 pkt_len; /* [15:14] are reserved */ 120cdedef59SAnirudh Venkataramanan __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */ 121cdedef59SAnirudh Venkataramanan /* sph=[11:11] */ 122cdedef59SAnirudh Venkataramanan /* ff1/ext=[15:12] */ 123cdedef59SAnirudh Venkataramanan 124cdedef59SAnirudh Venkataramanan /* Qword 1 */ 125cdedef59SAnirudh Venkataramanan __le16 status_error0; 126cdedef59SAnirudh Venkataramanan __le16 l2tag1; 127cdedef59SAnirudh Venkataramanan __le16 flex_meta0; 128cdedef59SAnirudh Venkataramanan __le16 flex_meta1; 129cdedef59SAnirudh Venkataramanan 130cdedef59SAnirudh Venkataramanan /* Qword 2 */ 131cdedef59SAnirudh Venkataramanan __le16 status_error1; 132cdedef59SAnirudh Venkataramanan u8 flex_flags2; 133cdedef59SAnirudh Venkataramanan u8 time_stamp_low; 134cdedef59SAnirudh Venkataramanan __le16 l2tag2_1st; 135cdedef59SAnirudh Venkataramanan __le16 l2tag2_2nd; 136cdedef59SAnirudh Venkataramanan 137cdedef59SAnirudh Venkataramanan /* Qword 3 */ 138cdedef59SAnirudh Venkataramanan __le16 flex_meta2; 139cdedef59SAnirudh Venkataramanan __le16 flex_meta3; 140cdedef59SAnirudh Venkataramanan union { 141cdedef59SAnirudh Venkataramanan struct { 142cdedef59SAnirudh Venkataramanan __le16 flex_meta4; 143cdedef59SAnirudh Venkataramanan __le16 flex_meta5; 144cdedef59SAnirudh Venkataramanan } flex; 145cdedef59SAnirudh Venkataramanan __le32 ts_high; 146cdedef59SAnirudh Venkataramanan } flex_ts; 147cdedef59SAnirudh Venkataramanan } wb; /* writeback */ 148cdedef59SAnirudh Venkataramanan }; 149cdedef59SAnirudh Venkataramanan 150d76a60baSAnirudh Venkataramanan /* Rx Flex Descriptor NIC Profile 151d76a60baSAnirudh Venkataramanan * This descriptor corresponds to RxDID 2 which contains 152d76a60baSAnirudh Venkataramanan * metadata fields for RSS, flow id and timestamp info 153d76a60baSAnirudh Venkataramanan */ 154d76a60baSAnirudh Venkataramanan struct ice_32b_rx_flex_desc_nic { 155d76a60baSAnirudh Venkataramanan /* Qword 0 */ 156d76a60baSAnirudh Venkataramanan u8 rxdid; 157d76a60baSAnirudh Venkataramanan u8 mir_id_umb_cast; 158d76a60baSAnirudh Venkataramanan __le16 ptype_flexi_flags0; 159d76a60baSAnirudh Venkataramanan __le16 pkt_len; 160d76a60baSAnirudh Venkataramanan __le16 hdr_len_sph_flex_flags1; 161d76a60baSAnirudh Venkataramanan 162d76a60baSAnirudh Venkataramanan /* Qword 1 */ 163d76a60baSAnirudh Venkataramanan __le16 status_error0; 164d76a60baSAnirudh Venkataramanan __le16 l2tag1; 165d76a60baSAnirudh Venkataramanan __le32 rss_hash; 166d76a60baSAnirudh Venkataramanan 167d76a60baSAnirudh Venkataramanan /* Qword 2 */ 168d76a60baSAnirudh Venkataramanan __le16 status_error1; 169d76a60baSAnirudh Venkataramanan u8 flexi_flags2; 170d76a60baSAnirudh Venkataramanan u8 ts_low; 171d76a60baSAnirudh Venkataramanan __le16 l2tag2_1st; 172d76a60baSAnirudh Venkataramanan __le16 l2tag2_2nd; 173d76a60baSAnirudh Venkataramanan 174d76a60baSAnirudh Venkataramanan /* Qword 3 */ 175d76a60baSAnirudh Venkataramanan __le32 flow_id; 176d76a60baSAnirudh Venkataramanan union { 177d76a60baSAnirudh Venkataramanan struct { 178d76a60baSAnirudh Venkataramanan __le16 vlan_id; 179d76a60baSAnirudh Venkataramanan __le16 flow_id_ipv6; 180d76a60baSAnirudh Venkataramanan } flex; 181d76a60baSAnirudh Venkataramanan __le32 ts_high; 182d76a60baSAnirudh Venkataramanan } flex_ts; 183d76a60baSAnirudh Venkataramanan }; 184d76a60baSAnirudh Venkataramanan 185cdedef59SAnirudh Venkataramanan /* Receive Flex Descriptor profile IDs: There are a total 186cdedef59SAnirudh Venkataramanan * of 64 profiles where profile IDs 0/1 are for legacy; and 187cdedef59SAnirudh Venkataramanan * profiles 2-63 are flex profiles that can be programmed 188cdedef59SAnirudh Venkataramanan * with a specific metadata (profile 7 reserved for HW) 189cdedef59SAnirudh Venkataramanan */ 190cdedef59SAnirudh Venkataramanan enum ice_rxdid { 191cdedef59SAnirudh Venkataramanan ICE_RXDID_START = 0, 192cdedef59SAnirudh Venkataramanan ICE_RXDID_LEGACY_0 = ICE_RXDID_START, 193cdedef59SAnirudh Venkataramanan ICE_RXDID_LEGACY_1, 194cdedef59SAnirudh Venkataramanan ICE_RXDID_FLX_START, 195cdedef59SAnirudh Venkataramanan ICE_RXDID_FLEX_NIC = ICE_RXDID_FLX_START, 196cdedef59SAnirudh Venkataramanan ICE_RXDID_FLX_LAST = 63, 197cdedef59SAnirudh Venkataramanan ICE_RXDID_LAST = ICE_RXDID_FLX_LAST 198cdedef59SAnirudh Venkataramanan }; 199cdedef59SAnirudh Venkataramanan 200cdedef59SAnirudh Venkataramanan /* Receive Flex Descriptor Rx opcode values */ 201cdedef59SAnirudh Venkataramanan #define ICE_RX_OPC_MDID 0x01 202cdedef59SAnirudh Venkataramanan 203cdedef59SAnirudh Venkataramanan /* Receive Descriptor MDID values */ 204cdedef59SAnirudh Venkataramanan #define ICE_RX_MDID_FLOW_ID_LOWER 5 205cdedef59SAnirudh Venkataramanan #define ICE_RX_MDID_FLOW_ID_HIGH 6 206cdedef59SAnirudh Venkataramanan #define ICE_RX_MDID_HASH_LOW 56 207cdedef59SAnirudh Venkataramanan #define ICE_RX_MDID_HASH_HIGH 57 208cdedef59SAnirudh Venkataramanan 209cdedef59SAnirudh Venkataramanan /* Rx Flag64 packet flag bits */ 210cdedef59SAnirudh Venkataramanan enum ice_rx_flg64_bits { 211cdedef59SAnirudh Venkataramanan ICE_RXFLG_PKT_DSI = 0, 212cdedef59SAnirudh Venkataramanan ICE_RXFLG_EVLAN_x8100 = 15, 213cdedef59SAnirudh Venkataramanan ICE_RXFLG_EVLAN_x9100, 214cdedef59SAnirudh Venkataramanan ICE_RXFLG_VLAN_x8100, 215cdedef59SAnirudh Venkataramanan ICE_RXFLG_TNL_MAC = 22, 216cdedef59SAnirudh Venkataramanan ICE_RXFLG_TNL_VLAN, 217cdedef59SAnirudh Venkataramanan ICE_RXFLG_PKT_FRG, 218cdedef59SAnirudh Venkataramanan ICE_RXFLG_FIN = 32, 219cdedef59SAnirudh Venkataramanan ICE_RXFLG_SYN, 220cdedef59SAnirudh Venkataramanan ICE_RXFLG_RST, 221cdedef59SAnirudh Venkataramanan ICE_RXFLG_TNL0 = 38, 222cdedef59SAnirudh Venkataramanan ICE_RXFLG_TNL1, 223cdedef59SAnirudh Venkataramanan ICE_RXFLG_TNL2, 224cdedef59SAnirudh Venkataramanan ICE_RXFLG_UDP_GRE, 225cdedef59SAnirudh Venkataramanan ICE_RXFLG_RSVD = 63 226cdedef59SAnirudh Venkataramanan }; 227cdedef59SAnirudh Venkataramanan 2282b245cb2SAnirudh Venkataramanan /* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */ 2292b245cb2SAnirudh Venkataramanan #define ICE_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */ 2302b245cb2SAnirudh Venkataramanan 2312b245cb2SAnirudh Venkataramanan /* for ice_32byte_rx_flex_desc.pkt_length member */ 2322b245cb2SAnirudh Venkataramanan #define ICE_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */ 2332b245cb2SAnirudh Venkataramanan 2342b245cb2SAnirudh Venkataramanan enum ice_rx_flex_desc_status_error_0_bits { 2352b245cb2SAnirudh Venkataramanan /* Note: These are predefined bit offsets */ 2362b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_DD_S = 0, 2372b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_EOF_S, 2382b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_HBO_S, 2392b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_L3L4P_S, 2402b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S, 2412b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S, 2422b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S, 2432b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S, 2442b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_LPBK_S, 2452b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S, 2462b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_RXE_S, 2472b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_CRCP_S, 2482b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S, 2492b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S, 2502b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S, 2512b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S, 2522b245cb2SAnirudh Venkataramanan ICE_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */ 2532b245cb2SAnirudh Venkataramanan }; 2542b245cb2SAnirudh Venkataramanan 255cdedef59SAnirudh Venkataramanan #define ICE_RXQ_CTX_SIZE_DWORDS 8 256cdedef59SAnirudh Venkataramanan #define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32)) 257cdedef59SAnirudh Venkataramanan 258cdedef59SAnirudh Venkataramanan /* RLAN Rx queue context data 259cdedef59SAnirudh Venkataramanan * 260cdedef59SAnirudh Venkataramanan * The sizes of the variables may be larger than needed due to crossing byte 261cdedef59SAnirudh Venkataramanan * boundaries. If we do not have the width of the variable set to the correct 262cdedef59SAnirudh Venkataramanan * size then we could end up shifting bits off the top of the variable when the 263cdedef59SAnirudh Venkataramanan * variable is at the top of a byte and crosses over into the next byte. 264cdedef59SAnirudh Venkataramanan */ 265cdedef59SAnirudh Venkataramanan struct ice_rlan_ctx { 266cdedef59SAnirudh Venkataramanan u16 head; 267cdedef59SAnirudh Venkataramanan u16 cpuid; /* bigger than needed, see above for reason */ 268cdedef59SAnirudh Venkataramanan u64 base; 269cdedef59SAnirudh Venkataramanan u16 qlen; 270cdedef59SAnirudh Venkataramanan #define ICE_RLAN_CTX_DBUF_S 7 271cdedef59SAnirudh Venkataramanan u16 dbuf; /* bigger than needed, see above for reason */ 272cdedef59SAnirudh Venkataramanan #define ICE_RLAN_CTX_HBUF_S 6 273cdedef59SAnirudh Venkataramanan u16 hbuf; /* bigger than needed, see above for reason */ 274cdedef59SAnirudh Venkataramanan u8 dtype; 275cdedef59SAnirudh Venkataramanan u8 dsize; 276cdedef59SAnirudh Venkataramanan u8 crcstrip; 277cdedef59SAnirudh Venkataramanan u8 l2tsel; 278cdedef59SAnirudh Venkataramanan u8 hsplit_0; 279cdedef59SAnirudh Venkataramanan u8 hsplit_1; 280cdedef59SAnirudh Venkataramanan u8 showiv; 281cdedef59SAnirudh Venkataramanan u32 rxmax; /* bigger than needed, see above for reason */ 282cdedef59SAnirudh Venkataramanan u8 tphrdesc_ena; 283cdedef59SAnirudh Venkataramanan u8 tphwdesc_ena; 284cdedef59SAnirudh Venkataramanan u8 tphdata_ena; 285cdedef59SAnirudh Venkataramanan u8 tphhead_ena; 286cdedef59SAnirudh Venkataramanan u16 lrxqthresh; /* bigger than needed, see above for reason */ 287cdedef59SAnirudh Venkataramanan }; 288cdedef59SAnirudh Venkataramanan 289cdedef59SAnirudh Venkataramanan struct ice_ctx_ele { 290cdedef59SAnirudh Venkataramanan u16 offset; 291cdedef59SAnirudh Venkataramanan u16 size_of; 292cdedef59SAnirudh Venkataramanan u16 width; 293cdedef59SAnirudh Venkataramanan u16 lsb; 294cdedef59SAnirudh Venkataramanan }; 295cdedef59SAnirudh Venkataramanan 296cdedef59SAnirudh Venkataramanan #define ICE_CTX_STORE(_struct, _ele, _width, _lsb) { \ 297cdedef59SAnirudh Venkataramanan .offset = offsetof(struct _struct, _ele), \ 298cdedef59SAnirudh Venkataramanan .size_of = FIELD_SIZEOF(struct _struct, _ele), \ 299cdedef59SAnirudh Venkataramanan .width = _width, \ 300cdedef59SAnirudh Venkataramanan .lsb = _lsb, \ 301cdedef59SAnirudh Venkataramanan } 302cdedef59SAnirudh Venkataramanan 303cdedef59SAnirudh Venkataramanan /* for hsplit_0 field of Rx RLAN context */ 304cdedef59SAnirudh Venkataramanan enum ice_rlan_ctx_rx_hsplit_0 { 305cdedef59SAnirudh Venkataramanan ICE_RLAN_RX_HSPLIT_0_NO_SPLIT = 0, 306cdedef59SAnirudh Venkataramanan ICE_RLAN_RX_HSPLIT_0_SPLIT_L2 = 1, 307cdedef59SAnirudh Venkataramanan ICE_RLAN_RX_HSPLIT_0_SPLIT_IP = 2, 308cdedef59SAnirudh Venkataramanan ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP = 4, 309cdedef59SAnirudh Venkataramanan ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP = 8, 310cdedef59SAnirudh Venkataramanan }; 311cdedef59SAnirudh Venkataramanan 312cdedef59SAnirudh Venkataramanan /* for hsplit_1 field of Rx RLAN context */ 313cdedef59SAnirudh Venkataramanan enum ice_rlan_ctx_rx_hsplit_1 { 314cdedef59SAnirudh Venkataramanan ICE_RLAN_RX_HSPLIT_1_NO_SPLIT = 0, 315cdedef59SAnirudh Venkataramanan ICE_RLAN_RX_HSPLIT_1_SPLIT_L2 = 1, 316cdedef59SAnirudh Venkataramanan ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS = 2, 317cdedef59SAnirudh Venkataramanan }; 318cdedef59SAnirudh Venkataramanan 319cdedef59SAnirudh Venkataramanan /* TX Descriptor */ 320cdedef59SAnirudh Venkataramanan struct ice_tx_desc { 321cdedef59SAnirudh Venkataramanan __le64 buf_addr; /* Address of descriptor's data buf */ 322cdedef59SAnirudh Venkataramanan __le64 cmd_type_offset_bsz; 323cdedef59SAnirudh Venkataramanan }; 324cdedef59SAnirudh Venkataramanan 3252b245cb2SAnirudh Venkataramanan enum ice_tx_desc_dtype_value { 3262b245cb2SAnirudh Venkataramanan ICE_TX_DESC_DTYPE_DATA = 0x0, 3272b245cb2SAnirudh Venkataramanan ICE_TX_DESC_DTYPE_CTX = 0x1, 3282b245cb2SAnirudh Venkataramanan /* DESC_DONE - HW has completed write-back of descriptor */ 3292b245cb2SAnirudh Venkataramanan ICE_TX_DESC_DTYPE_DESC_DONE = 0xF, 3302b245cb2SAnirudh Venkataramanan }; 3312b245cb2SAnirudh Venkataramanan 3322b245cb2SAnirudh Venkataramanan #define ICE_TXD_QW1_CMD_S 4 3332b245cb2SAnirudh Venkataramanan #define ICE_TXD_QW1_CMD_M (0xFFFUL << ICE_TXD_QW1_CMD_S) 3342b245cb2SAnirudh Venkataramanan 3352b245cb2SAnirudh Venkataramanan enum ice_tx_desc_cmd_bits { 3362b245cb2SAnirudh Venkataramanan ICE_TX_DESC_CMD_EOP = 0x0001, 3372b245cb2SAnirudh Venkataramanan ICE_TX_DESC_CMD_RS = 0x0002, 338d76a60baSAnirudh Venkataramanan ICE_TX_DESC_CMD_IL2TAG1 = 0x0008, 339d76a60baSAnirudh Venkataramanan ICE_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 340d76a60baSAnirudh Venkataramanan ICE_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 341d76a60baSAnirudh Venkataramanan ICE_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 342d76a60baSAnirudh Venkataramanan ICE_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 343d76a60baSAnirudh Venkataramanan ICE_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 3442b245cb2SAnirudh Venkataramanan }; 3452b245cb2SAnirudh Venkataramanan 3462b245cb2SAnirudh Venkataramanan #define ICE_TXD_QW1_OFFSET_S 16 347d76a60baSAnirudh Venkataramanan #define ICE_TXD_QW1_OFFSET_M (0x3FFFFULL << ICE_TXD_QW1_OFFSET_S) 348d76a60baSAnirudh Venkataramanan 349d76a60baSAnirudh Venkataramanan enum ice_tx_desc_len_fields { 350d76a60baSAnirudh Venkataramanan /* Note: These are predefined bit offsets */ 351d76a60baSAnirudh Venkataramanan ICE_TX_DESC_LEN_MACLEN_S = 0, /* 7 BITS */ 352d76a60baSAnirudh Venkataramanan ICE_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */ 353d76a60baSAnirudh Venkataramanan ICE_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */ 354d76a60baSAnirudh Venkataramanan }; 355d76a60baSAnirudh Venkataramanan 356e94d4478SAnirudh Venkataramanan #define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S) 357e94d4478SAnirudh Venkataramanan #define ICE_TXD_QW1_IPLEN_M (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S) 358e94d4478SAnirudh Venkataramanan #define ICE_TXD_QW1_L4LEN_M (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S) 359e94d4478SAnirudh Venkataramanan 360e94d4478SAnirudh Venkataramanan /* Tx descriptor field limits in bytes */ 361e94d4478SAnirudh Venkataramanan #define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \ 362e94d4478SAnirudh Venkataramanan ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD) 363e94d4478SAnirudh Venkataramanan #define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \ 364e94d4478SAnirudh Venkataramanan ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD) 365e94d4478SAnirudh Venkataramanan #define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \ 366e94d4478SAnirudh Venkataramanan ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD) 367e94d4478SAnirudh Venkataramanan 3682b245cb2SAnirudh Venkataramanan #define ICE_TXD_QW1_TX_BUF_SZ_S 34 3692b245cb2SAnirudh Venkataramanan #define ICE_TXD_QW1_L2TAG1_S 48 3702b245cb2SAnirudh Venkataramanan 371d76a60baSAnirudh Venkataramanan /* Context descriptors */ 372d76a60baSAnirudh Venkataramanan struct ice_tx_ctx_desc { 373d76a60baSAnirudh Venkataramanan __le32 tunneling_params; 374d76a60baSAnirudh Venkataramanan __le16 l2tag2; 375d76a60baSAnirudh Venkataramanan __le16 rsvd; 376d76a60baSAnirudh Venkataramanan __le64 qw1; 377d76a60baSAnirudh Venkataramanan }; 378d76a60baSAnirudh Venkataramanan 379d76a60baSAnirudh Venkataramanan #define ICE_TXD_CTX_QW1_CMD_S 4 380d76a60baSAnirudh Venkataramanan #define ICE_TXD_CTX_QW1_CMD_M (0x7FUL << ICE_TXD_CTX_QW1_CMD_S) 381d76a60baSAnirudh Venkataramanan 382d76a60baSAnirudh Venkataramanan #define ICE_TXD_CTX_QW1_TSO_LEN_S 30 383d76a60baSAnirudh Venkataramanan #define ICE_TXD_CTX_QW1_TSO_LEN_M \ 384d76a60baSAnirudh Venkataramanan (0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S) 385d76a60baSAnirudh Venkataramanan 386d76a60baSAnirudh Venkataramanan #define ICE_TXD_CTX_QW1_MSS_S 50 387d76a60baSAnirudh Venkataramanan 388d76a60baSAnirudh Venkataramanan enum ice_tx_ctx_desc_cmd_bits { 389d76a60baSAnirudh Venkataramanan ICE_TX_CTX_DESC_TSO = 0x01, 390d76a60baSAnirudh Venkataramanan ICE_TX_CTX_DESC_TSYN = 0x02, 391d76a60baSAnirudh Venkataramanan ICE_TX_CTX_DESC_IL2TAG2 = 0x04, 392d76a60baSAnirudh Venkataramanan ICE_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 393d76a60baSAnirudh Venkataramanan ICE_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 394d76a60baSAnirudh Venkataramanan ICE_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 395d76a60baSAnirudh Venkataramanan ICE_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 396d76a60baSAnirudh Venkataramanan ICE_TX_CTX_DESC_SWTCH_VSI = 0x30, 397d76a60baSAnirudh Venkataramanan ICE_TX_CTX_DESC_RESERVED = 0x40 398d76a60baSAnirudh Venkataramanan }; 399d76a60baSAnirudh Venkataramanan 400cdedef59SAnirudh Venkataramanan #define ICE_LAN_TXQ_MAX_QGRPS 127 401cdedef59SAnirudh Venkataramanan #define ICE_LAN_TXQ_MAX_QDIS 1023 402cdedef59SAnirudh Venkataramanan 403cdedef59SAnirudh Venkataramanan /* Tx queue context data 404cdedef59SAnirudh Venkataramanan * 405cdedef59SAnirudh Venkataramanan * The sizes of the variables may be larger than needed due to crossing byte 406cdedef59SAnirudh Venkataramanan * boundaries. If we do not have the width of the variable set to the correct 407cdedef59SAnirudh Venkataramanan * size then we could end up shifting bits off the top of the variable when the 408cdedef59SAnirudh Venkataramanan * variable is at the top of a byte and crosses over into the next byte. 409cdedef59SAnirudh Venkataramanan */ 410cdedef59SAnirudh Venkataramanan struct ice_tlan_ctx { 411cdedef59SAnirudh Venkataramanan #define ICE_TLAN_CTX_BASE_S 7 412cdedef59SAnirudh Venkataramanan u64 base; /* base is defined in 128-byte units */ 413cdedef59SAnirudh Venkataramanan u8 port_num; 414cdedef59SAnirudh Venkataramanan u16 cgd_num; /* bigger than needed, see above for reason */ 415cdedef59SAnirudh Venkataramanan u8 pf_num; 416cdedef59SAnirudh Venkataramanan u16 vmvf_num; 417cdedef59SAnirudh Venkataramanan u8 vmvf_type; 418cdedef59SAnirudh Venkataramanan #define ICE_TLAN_CTX_VMVF_TYPE_VMQ 1 419cdedef59SAnirudh Venkataramanan #define ICE_TLAN_CTX_VMVF_TYPE_PF 2 420cdedef59SAnirudh Venkataramanan u16 src_vsi; 421cdedef59SAnirudh Venkataramanan u8 tsyn_ena; 422cdedef59SAnirudh Venkataramanan u8 alt_vlan; 423cdedef59SAnirudh Venkataramanan u16 cpuid; /* bigger than needed, see above for reason */ 424cdedef59SAnirudh Venkataramanan u8 wb_mode; 425cdedef59SAnirudh Venkataramanan u8 tphrd_desc; 426cdedef59SAnirudh Venkataramanan u8 tphrd; 427cdedef59SAnirudh Venkataramanan u8 tphwr_desc; 428cdedef59SAnirudh Venkataramanan u16 cmpq_id; 429cdedef59SAnirudh Venkataramanan u16 qnum_in_func; 430cdedef59SAnirudh Venkataramanan u8 itr_notification_mode; 431cdedef59SAnirudh Venkataramanan u8 adjust_prof_id; 432cdedef59SAnirudh Venkataramanan u32 qlen; /* bigger than needed, see above for reason */ 433cdedef59SAnirudh Venkataramanan u8 quanta_prof_idx; 434cdedef59SAnirudh Venkataramanan u8 tso_ena; 435cdedef59SAnirudh Venkataramanan u16 tso_qnum; 436cdedef59SAnirudh Venkataramanan u8 legacy_int; 437cdedef59SAnirudh Venkataramanan u8 drop_ena; 438cdedef59SAnirudh Venkataramanan u8 cache_prof_idx; 439cdedef59SAnirudh Venkataramanan u8 pkt_shaper_prof_idx; 440cdedef59SAnirudh Venkataramanan u8 int_q_state; /* width not needed - internal do not write */ 441cdedef59SAnirudh Venkataramanan }; 442d76a60baSAnirudh Venkataramanan 443d76a60baSAnirudh Venkataramanan /* macro to make the table lines short */ 444d76a60baSAnirudh Venkataramanan #define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 445d76a60baSAnirudh Venkataramanan { PTYPE, \ 446d76a60baSAnirudh Venkataramanan 1, \ 447d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_OUTER_##OUTER_IP, \ 448d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 449d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_##OUTER_FRAG, \ 450d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_TUNNEL_##T, \ 451d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_TUNNEL_END_##TE, \ 452d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_##TEF, \ 453d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_INNER_PROT_##I, \ 454d76a60baSAnirudh Venkataramanan ICE_RX_PTYPE_PAYLOAD_LAYER_##PL } 455d76a60baSAnirudh Venkataramanan 456d76a60baSAnirudh Venkataramanan #define ICE_PTT_UNUSED_ENTRY(PTYPE) { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 457d76a60baSAnirudh Venkataramanan 458d76a60baSAnirudh Venkataramanan /* shorter macros makes the table fit but are terse */ 459d76a60baSAnirudh Venkataramanan #define ICE_RX_PTYPE_NOF ICE_RX_PTYPE_NOT_FRAG 460d76a60baSAnirudh Venkataramanan 461d76a60baSAnirudh Venkataramanan /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 462d76a60baSAnirudh Venkataramanan static const struct ice_rx_ptype_decoded ice_ptype_lkup[] = { 463d76a60baSAnirudh Venkataramanan /* L2 Packet types */ 464d76a60baSAnirudh Venkataramanan ICE_PTT_UNUSED_ENTRY(0), 465d76a60baSAnirudh Venkataramanan ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 466d76a60baSAnirudh Venkataramanan ICE_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 467d76a60baSAnirudh Venkataramanan }; 468d76a60baSAnirudh Venkataramanan 469d76a60baSAnirudh Venkataramanan static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype) 470d76a60baSAnirudh Venkataramanan { 471d76a60baSAnirudh Venkataramanan return ice_ptype_lkup[ptype]; 472d76a60baSAnirudh Venkataramanan } 473cdedef59SAnirudh Venkataramanan #endif /* _ICE_LAN_TX_RX_H_ */ 474