17ec59eeaSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 27ec59eeaSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 37ec59eeaSAnirudh Venkataramanan 47ec59eeaSAnirudh Venkataramanan #ifndef _ICE_CONTROLQ_H_ 57ec59eeaSAnirudh Venkataramanan #define _ICE_CONTROLQ_H_ 67ec59eeaSAnirudh Venkataramanan 77ec59eeaSAnirudh Venkataramanan #include "ice_adminq_cmd.h" 87ec59eeaSAnirudh Venkataramanan 9f31e4b6fSAnirudh Venkataramanan /* Maximum buffer lengths for all control queue types */ 10f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_MAX_BUF_LEN 4096 1175d2b253SAnirudh Venkataramanan #define ICE_MBXQ_MAX_BUF_LEN 4096 12f31e4b6fSAnirudh Venkataramanan 137ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DESC(R, i) \ 147ec59eeaSAnirudh Venkataramanan (&(((struct ice_aq_desc *)((R).desc_buf.va))[i])) 157ec59eeaSAnirudh Venkataramanan 167ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DESC_UNUSED(R) \ 177ec59eeaSAnirudh Venkataramanan (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 187ec59eeaSAnirudh Venkataramanan (R)->next_to_clean - (R)->next_to_use - 1) 197ec59eeaSAnirudh Venkataramanan 207ec59eeaSAnirudh Venkataramanan /* Defines that help manage the driver vs FW API checks. 217ec59eeaSAnirudh Venkataramanan * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage. 227ec59eeaSAnirudh Venkataramanan */ 237ec59eeaSAnirudh Venkataramanan #define EXP_FW_API_VER_BRANCH 0x00 24ac5a8aefSAnirudh Venkataramanan #define EXP_FW_API_VER_MAJOR 0x01 25ed960c1dSKevin Scott #define EXP_FW_API_VER_MINOR 0x05 267ec59eeaSAnirudh Venkataramanan 277ec59eeaSAnirudh Venkataramanan /* Different control queue types: These are mainly for SW consumption. */ 287ec59eeaSAnirudh Venkataramanan enum ice_ctl_q { 297ec59eeaSAnirudh Venkataramanan ICE_CTL_Q_UNKNOWN = 0, 307ec59eeaSAnirudh Venkataramanan ICE_CTL_Q_ADMIN, 3175d2b253SAnirudh Venkataramanan ICE_CTL_Q_MAILBOX, 327ec59eeaSAnirudh Venkataramanan }; 337ec59eeaSAnirudh Venkataramanan 3488bb432aSMitch Williams /* Control Queue timeout settings - max delay 250ms */ 3588bb432aSMitch Williams #define ICE_CTL_Q_SQ_CMD_TIMEOUT 2500 /* Count 2500 times */ 3688bb432aSMitch Williams #define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */ 37b5c7f857SEvan Swanson #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */ 38b5c7f857SEvan Swanson #define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */ 397ec59eeaSAnirudh Venkataramanan 407ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring { 412f2da36eSAnirudh Venkataramanan void *dma_head; /* Virtual address to DMA head */ 427ec59eeaSAnirudh Venkataramanan struct ice_dma_mem desc_buf; /* descriptor ring memory */ 437ec59eeaSAnirudh Venkataramanan void *cmd_buf; /* command buffer memory */ 447ec59eeaSAnirudh Venkataramanan 457ec59eeaSAnirudh Venkataramanan union { 467ec59eeaSAnirudh Venkataramanan struct ice_dma_mem *sq_bi; 477ec59eeaSAnirudh Venkataramanan struct ice_dma_mem *rq_bi; 487ec59eeaSAnirudh Venkataramanan } r; 497ec59eeaSAnirudh Venkataramanan 507ec59eeaSAnirudh Venkataramanan u16 count; /* Number of descriptors */ 517ec59eeaSAnirudh Venkataramanan 527ec59eeaSAnirudh Venkataramanan /* used for interrupt processing */ 537ec59eeaSAnirudh Venkataramanan u16 next_to_use; 547ec59eeaSAnirudh Venkataramanan u16 next_to_clean; 557ec59eeaSAnirudh Venkataramanan 567ec59eeaSAnirudh Venkataramanan /* used for queue tracking */ 577ec59eeaSAnirudh Venkataramanan u32 head; 587ec59eeaSAnirudh Venkataramanan u32 tail; 597ec59eeaSAnirudh Venkataramanan u32 len; 607ec59eeaSAnirudh Venkataramanan u32 bah; 617ec59eeaSAnirudh Venkataramanan u32 bal; 627ec59eeaSAnirudh Venkataramanan u32 len_mask; 637ec59eeaSAnirudh Venkataramanan u32 len_ena_mask; 64b5c7f857SEvan Swanson u32 len_crit_mask; 657ec59eeaSAnirudh Venkataramanan u32 head_mask; 667ec59eeaSAnirudh Venkataramanan }; 677ec59eeaSAnirudh Venkataramanan 687ec59eeaSAnirudh Venkataramanan /* sq transaction details */ 697ec59eeaSAnirudh Venkataramanan struct ice_sq_cd { 707ec59eeaSAnirudh Venkataramanan struct ice_aq_desc *wb_desc; 717ec59eeaSAnirudh Venkataramanan }; 727ec59eeaSAnirudh Venkataramanan 737ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i])) 747ec59eeaSAnirudh Venkataramanan 75940b61afSAnirudh Venkataramanan /* rq event information */ 76940b61afSAnirudh Venkataramanan struct ice_rq_event_info { 77940b61afSAnirudh Venkataramanan struct ice_aq_desc desc; 78940b61afSAnirudh Venkataramanan u16 msg_len; 79940b61afSAnirudh Venkataramanan u16 buf_len; 80940b61afSAnirudh Venkataramanan u8 *msg_buf; 81940b61afSAnirudh Venkataramanan }; 82940b61afSAnirudh Venkataramanan 837ec59eeaSAnirudh Venkataramanan /* Control Queue information */ 847ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_info { 857ec59eeaSAnirudh Venkataramanan enum ice_ctl_q qtype; 8606905270SJesse Brandeburg enum ice_aq_err rq_last_status; /* last status on receive queue */ 877ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring rq; /* receive queue */ 887ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring sq; /* send queue */ 897ec59eeaSAnirudh Venkataramanan u32 sq_cmd_timeout; /* send queue cmd write back timeout */ 907ec59eeaSAnirudh Venkataramanan u16 num_rq_entries; /* receive queue depth */ 917ec59eeaSAnirudh Venkataramanan u16 num_sq_entries; /* send queue depth */ 927ec59eeaSAnirudh Venkataramanan u16 rq_buf_size; /* receive queue buffer size */ 937ec59eeaSAnirudh Venkataramanan u16 sq_buf_size; /* send queue buffer size */ 9406905270SJesse Brandeburg enum ice_aq_err sq_last_status; /* last status on send queue */ 957ec59eeaSAnirudh Venkataramanan struct mutex sq_lock; /* Send queue lock */ 967ec59eeaSAnirudh Venkataramanan struct mutex rq_lock; /* Receive queue lock */ 977ec59eeaSAnirudh Venkataramanan }; 987ec59eeaSAnirudh Venkataramanan 997ec59eeaSAnirudh Venkataramanan #endif /* _ICE_CONTROLQ_H_ */ 100