17ec59eeaSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 27ec59eeaSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 37ec59eeaSAnirudh Venkataramanan 47ec59eeaSAnirudh Venkataramanan #ifndef _ICE_CONTROLQ_H_ 57ec59eeaSAnirudh Venkataramanan #define _ICE_CONTROLQ_H_ 67ec59eeaSAnirudh Venkataramanan 77ec59eeaSAnirudh Venkataramanan #include "ice_adminq_cmd.h" 87ec59eeaSAnirudh Venkataramanan 9f31e4b6fSAnirudh Venkataramanan /* Maximum buffer lengths for all control queue types */ 10f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_MAX_BUF_LEN 4096 1175d2b253SAnirudh Venkataramanan #define ICE_MBXQ_MAX_BUF_LEN 4096 12*8f5ee3c4SJacob Keller #define ICE_SBQ_MAX_BUF_LEN 512 13f31e4b6fSAnirudh Venkataramanan 147ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DESC(R, i) \ 157ec59eeaSAnirudh Venkataramanan (&(((struct ice_aq_desc *)((R).desc_buf.va))[i])) 167ec59eeaSAnirudh Venkataramanan 177ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DESC_UNUSED(R) \ 180c3e94c2SBruce Allan ((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 190c3e94c2SBruce Allan (R)->next_to_clean - (R)->next_to_use - 1)) 207ec59eeaSAnirudh Venkataramanan 217ec59eeaSAnirudh Venkataramanan /* Defines that help manage the driver vs FW API checks. 227ec59eeaSAnirudh Venkataramanan * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage. 237ec59eeaSAnirudh Venkataramanan */ 247ec59eeaSAnirudh Venkataramanan #define EXP_FW_API_VER_BRANCH 0x00 25ac5a8aefSAnirudh Venkataramanan #define EXP_FW_API_VER_MAJOR 0x01 26ed960c1dSKevin Scott #define EXP_FW_API_VER_MINOR 0x05 277ec59eeaSAnirudh Venkataramanan 287ec59eeaSAnirudh Venkataramanan /* Different control queue types: These are mainly for SW consumption. */ 297ec59eeaSAnirudh Venkataramanan enum ice_ctl_q { 307ec59eeaSAnirudh Venkataramanan ICE_CTL_Q_UNKNOWN = 0, 317ec59eeaSAnirudh Venkataramanan ICE_CTL_Q_ADMIN, 3275d2b253SAnirudh Venkataramanan ICE_CTL_Q_MAILBOX, 33*8f5ee3c4SJacob Keller ICE_CTL_Q_SB, 347ec59eeaSAnirudh Venkataramanan }; 357ec59eeaSAnirudh Venkataramanan 36f88c529aSFabio Pricoco /* Control Queue timeout settings - max delay 1s */ 37f88c529aSFabio Pricoco #define ICE_CTL_Q_SQ_CMD_TIMEOUT 10000 /* Count 10000 times */ 3888bb432aSMitch Williams #define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */ 39b5c7f857SEvan Swanson #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */ 40b5c7f857SEvan Swanson #define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */ 417ec59eeaSAnirudh Venkataramanan 427ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring { 432f2da36eSAnirudh Venkataramanan void *dma_head; /* Virtual address to DMA head */ 447ec59eeaSAnirudh Venkataramanan struct ice_dma_mem desc_buf; /* descriptor ring memory */ 457ec59eeaSAnirudh Venkataramanan void *cmd_buf; /* command buffer memory */ 467ec59eeaSAnirudh Venkataramanan 477ec59eeaSAnirudh Venkataramanan union { 487ec59eeaSAnirudh Venkataramanan struct ice_dma_mem *sq_bi; 497ec59eeaSAnirudh Venkataramanan struct ice_dma_mem *rq_bi; 507ec59eeaSAnirudh Venkataramanan } r; 517ec59eeaSAnirudh Venkataramanan 527ec59eeaSAnirudh Venkataramanan u16 count; /* Number of descriptors */ 537ec59eeaSAnirudh Venkataramanan 547ec59eeaSAnirudh Venkataramanan /* used for interrupt processing */ 557ec59eeaSAnirudh Venkataramanan u16 next_to_use; 567ec59eeaSAnirudh Venkataramanan u16 next_to_clean; 577ec59eeaSAnirudh Venkataramanan 587ec59eeaSAnirudh Venkataramanan /* used for queue tracking */ 597ec59eeaSAnirudh Venkataramanan u32 head; 607ec59eeaSAnirudh Venkataramanan u32 tail; 617ec59eeaSAnirudh Venkataramanan u32 len; 627ec59eeaSAnirudh Venkataramanan u32 bah; 637ec59eeaSAnirudh Venkataramanan u32 bal; 647ec59eeaSAnirudh Venkataramanan u32 len_mask; 657ec59eeaSAnirudh Venkataramanan u32 len_ena_mask; 66b5c7f857SEvan Swanson u32 len_crit_mask; 677ec59eeaSAnirudh Venkataramanan u32 head_mask; 687ec59eeaSAnirudh Venkataramanan }; 697ec59eeaSAnirudh Venkataramanan 707ec59eeaSAnirudh Venkataramanan /* sq transaction details */ 717ec59eeaSAnirudh Venkataramanan struct ice_sq_cd { 727ec59eeaSAnirudh Venkataramanan struct ice_aq_desc *wb_desc; 737ec59eeaSAnirudh Venkataramanan }; 747ec59eeaSAnirudh Venkataramanan 757ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i])) 767ec59eeaSAnirudh Venkataramanan 77940b61afSAnirudh Venkataramanan /* rq event information */ 78940b61afSAnirudh Venkataramanan struct ice_rq_event_info { 79940b61afSAnirudh Venkataramanan struct ice_aq_desc desc; 80940b61afSAnirudh Venkataramanan u16 msg_len; 81940b61afSAnirudh Venkataramanan u16 buf_len; 82940b61afSAnirudh Venkataramanan u8 *msg_buf; 83940b61afSAnirudh Venkataramanan }; 84940b61afSAnirudh Venkataramanan 857ec59eeaSAnirudh Venkataramanan /* Control Queue information */ 867ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_info { 877ec59eeaSAnirudh Venkataramanan enum ice_ctl_q qtype; 887ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring rq; /* receive queue */ 897ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring sq; /* send queue */ 907ec59eeaSAnirudh Venkataramanan u32 sq_cmd_timeout; /* send queue cmd write back timeout */ 917ec59eeaSAnirudh Venkataramanan u16 num_rq_entries; /* receive queue depth */ 927ec59eeaSAnirudh Venkataramanan u16 num_sq_entries; /* send queue depth */ 937ec59eeaSAnirudh Venkataramanan u16 rq_buf_size; /* receive queue buffer size */ 947ec59eeaSAnirudh Venkataramanan u16 sq_buf_size; /* send queue buffer size */ 9506905270SJesse Brandeburg enum ice_aq_err sq_last_status; /* last status on send queue */ 967ec59eeaSAnirudh Venkataramanan struct mutex sq_lock; /* Send queue lock */ 977ec59eeaSAnirudh Venkataramanan struct mutex rq_lock; /* Receive queue lock */ 987ec59eeaSAnirudh Venkataramanan }; 997ec59eeaSAnirudh Venkataramanan 1007ec59eeaSAnirudh Venkataramanan #endif /* _ICE_CONTROLQ_H_ */ 101