17ec59eeaSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 27ec59eeaSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 37ec59eeaSAnirudh Venkataramanan 47ec59eeaSAnirudh Venkataramanan #ifndef _ICE_CONTROLQ_H_ 57ec59eeaSAnirudh Venkataramanan #define _ICE_CONTROLQ_H_ 67ec59eeaSAnirudh Venkataramanan 77ec59eeaSAnirudh Venkataramanan #include "ice_adminq_cmd.h" 87ec59eeaSAnirudh Venkataramanan 97ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DESC(R, i) \ 107ec59eeaSAnirudh Venkataramanan (&(((struct ice_aq_desc *)((R).desc_buf.va))[i])) 117ec59eeaSAnirudh Venkataramanan 127ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DESC_UNUSED(R) \ 137ec59eeaSAnirudh Venkataramanan (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 147ec59eeaSAnirudh Venkataramanan (R)->next_to_clean - (R)->next_to_use - 1) 157ec59eeaSAnirudh Venkataramanan 167ec59eeaSAnirudh Venkataramanan /* Defines that help manage the driver vs FW API checks. 177ec59eeaSAnirudh Venkataramanan * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage. 187ec59eeaSAnirudh Venkataramanan * 197ec59eeaSAnirudh Venkataramanan */ 207ec59eeaSAnirudh Venkataramanan #define EXP_FW_API_VER_BRANCH 0x00 217ec59eeaSAnirudh Venkataramanan #define EXP_FW_API_VER_MAJOR 0x00 227ec59eeaSAnirudh Venkataramanan #define EXP_FW_API_VER_MINOR 0x01 237ec59eeaSAnirudh Venkataramanan 247ec59eeaSAnirudh Venkataramanan /* Different control queue types: These are mainly for SW consumption. */ 257ec59eeaSAnirudh Venkataramanan enum ice_ctl_q { 267ec59eeaSAnirudh Venkataramanan ICE_CTL_Q_UNKNOWN = 0, 277ec59eeaSAnirudh Venkataramanan ICE_CTL_Q_ADMIN, 287ec59eeaSAnirudh Venkataramanan }; 297ec59eeaSAnirudh Venkataramanan 307ec59eeaSAnirudh Venkataramanan /* Control Queue default settings */ 317ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_SQ_CMD_TIMEOUT 250 /* msecs */ 327ec59eeaSAnirudh Venkataramanan 337ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring { 347ec59eeaSAnirudh Venkataramanan void *dma_head; /* Virtual address to dma head */ 357ec59eeaSAnirudh Venkataramanan struct ice_dma_mem desc_buf; /* descriptor ring memory */ 367ec59eeaSAnirudh Venkataramanan void *cmd_buf; /* command buffer memory */ 377ec59eeaSAnirudh Venkataramanan 387ec59eeaSAnirudh Venkataramanan union { 397ec59eeaSAnirudh Venkataramanan struct ice_dma_mem *sq_bi; 407ec59eeaSAnirudh Venkataramanan struct ice_dma_mem *rq_bi; 417ec59eeaSAnirudh Venkataramanan } r; 427ec59eeaSAnirudh Venkataramanan 437ec59eeaSAnirudh Venkataramanan u16 count; /* Number of descriptors */ 447ec59eeaSAnirudh Venkataramanan 457ec59eeaSAnirudh Venkataramanan /* used for interrupt processing */ 467ec59eeaSAnirudh Venkataramanan u16 next_to_use; 477ec59eeaSAnirudh Venkataramanan u16 next_to_clean; 487ec59eeaSAnirudh Venkataramanan 497ec59eeaSAnirudh Venkataramanan /* used for queue tracking */ 507ec59eeaSAnirudh Venkataramanan u32 head; 517ec59eeaSAnirudh Venkataramanan u32 tail; 527ec59eeaSAnirudh Venkataramanan u32 len; 537ec59eeaSAnirudh Venkataramanan u32 bah; 547ec59eeaSAnirudh Venkataramanan u32 bal; 557ec59eeaSAnirudh Venkataramanan u32 len_mask; 567ec59eeaSAnirudh Venkataramanan u32 len_ena_mask; 577ec59eeaSAnirudh Venkataramanan u32 head_mask; 587ec59eeaSAnirudh Venkataramanan }; 597ec59eeaSAnirudh Venkataramanan 607ec59eeaSAnirudh Venkataramanan /* sq transaction details */ 617ec59eeaSAnirudh Venkataramanan struct ice_sq_cd { 627ec59eeaSAnirudh Venkataramanan struct ice_aq_desc *wb_desc; 637ec59eeaSAnirudh Venkataramanan }; 647ec59eeaSAnirudh Venkataramanan 657ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i])) 667ec59eeaSAnirudh Venkataramanan 677ec59eeaSAnirudh Venkataramanan /* Control Queue information */ 687ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_info { 697ec59eeaSAnirudh Venkataramanan enum ice_ctl_q qtype; 707ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring rq; /* receive queue */ 717ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring sq; /* send queue */ 727ec59eeaSAnirudh Venkataramanan u32 sq_cmd_timeout; /* send queue cmd write back timeout */ 737ec59eeaSAnirudh Venkataramanan u16 num_rq_entries; /* receive queue depth */ 747ec59eeaSAnirudh Venkataramanan u16 num_sq_entries; /* send queue depth */ 757ec59eeaSAnirudh Venkataramanan u16 rq_buf_size; /* receive queue buffer size */ 767ec59eeaSAnirudh Venkataramanan u16 sq_buf_size; /* send queue buffer size */ 777ec59eeaSAnirudh Venkataramanan struct mutex sq_lock; /* Send queue lock */ 787ec59eeaSAnirudh Venkataramanan struct mutex rq_lock; /* Receive queue lock */ 797ec59eeaSAnirudh Venkataramanan enum ice_aq_err sq_last_status; /* last status on send queue */ 807ec59eeaSAnirudh Venkataramanan enum ice_aq_err rq_last_status; /* last status on receive queue */ 817ec59eeaSAnirudh Venkataramanan }; 827ec59eeaSAnirudh Venkataramanan 837ec59eeaSAnirudh Venkataramanan #endif /* _ICE_CONTROLQ_H_ */ 84