17ec59eeaSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 27ec59eeaSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 37ec59eeaSAnirudh Venkataramanan 47ec59eeaSAnirudh Venkataramanan #ifndef _ICE_CONTROLQ_H_ 57ec59eeaSAnirudh Venkataramanan #define _ICE_CONTROLQ_H_ 67ec59eeaSAnirudh Venkataramanan 77ec59eeaSAnirudh Venkataramanan #include "ice_adminq_cmd.h" 87ec59eeaSAnirudh Venkataramanan 9f31e4b6fSAnirudh Venkataramanan /* Maximum buffer lengths for all control queue types */ 10f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_MAX_BUF_LEN 4096 1175d2b253SAnirudh Venkataramanan #define ICE_MBXQ_MAX_BUF_LEN 4096 12f31e4b6fSAnirudh Venkataramanan 137ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DESC(R, i) \ 147ec59eeaSAnirudh Venkataramanan (&(((struct ice_aq_desc *)((R).desc_buf.va))[i])) 157ec59eeaSAnirudh Venkataramanan 167ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DESC_UNUSED(R) \ 177ec59eeaSAnirudh Venkataramanan (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 187ec59eeaSAnirudh Venkataramanan (R)->next_to_clean - (R)->next_to_use - 1) 197ec59eeaSAnirudh Venkataramanan 207ec59eeaSAnirudh Venkataramanan /* Defines that help manage the driver vs FW API checks. 217ec59eeaSAnirudh Venkataramanan * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage. 227ec59eeaSAnirudh Venkataramanan */ 237ec59eeaSAnirudh Venkataramanan #define EXP_FW_API_VER_BRANCH 0x00 24ac5a8aefSAnirudh Venkataramanan #define EXP_FW_API_VER_MAJOR 0x01 25ac5a8aefSAnirudh Venkataramanan #define EXP_FW_API_VER_MINOR 0x03 267ec59eeaSAnirudh Venkataramanan 277ec59eeaSAnirudh Venkataramanan /* Different control queue types: These are mainly for SW consumption. */ 287ec59eeaSAnirudh Venkataramanan enum ice_ctl_q { 297ec59eeaSAnirudh Venkataramanan ICE_CTL_Q_UNKNOWN = 0, 307ec59eeaSAnirudh Venkataramanan ICE_CTL_Q_ADMIN, 3175d2b253SAnirudh Venkataramanan ICE_CTL_Q_MAILBOX, 327ec59eeaSAnirudh Venkataramanan }; 337ec59eeaSAnirudh Venkataramanan 347ec59eeaSAnirudh Venkataramanan /* Control Queue default settings */ 357ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_SQ_CMD_TIMEOUT 250 /* msecs */ 367ec59eeaSAnirudh Venkataramanan 377ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring { 382f2da36eSAnirudh Venkataramanan void *dma_head; /* Virtual address to DMA head */ 397ec59eeaSAnirudh Venkataramanan struct ice_dma_mem desc_buf; /* descriptor ring memory */ 407ec59eeaSAnirudh Venkataramanan void *cmd_buf; /* command buffer memory */ 417ec59eeaSAnirudh Venkataramanan 427ec59eeaSAnirudh Venkataramanan union { 437ec59eeaSAnirudh Venkataramanan struct ice_dma_mem *sq_bi; 447ec59eeaSAnirudh Venkataramanan struct ice_dma_mem *rq_bi; 457ec59eeaSAnirudh Venkataramanan } r; 467ec59eeaSAnirudh Venkataramanan 477ec59eeaSAnirudh Venkataramanan u16 count; /* Number of descriptors */ 487ec59eeaSAnirudh Venkataramanan 497ec59eeaSAnirudh Venkataramanan /* used for interrupt processing */ 507ec59eeaSAnirudh Venkataramanan u16 next_to_use; 517ec59eeaSAnirudh Venkataramanan u16 next_to_clean; 527ec59eeaSAnirudh Venkataramanan 537ec59eeaSAnirudh Venkataramanan /* used for queue tracking */ 547ec59eeaSAnirudh Venkataramanan u32 head; 557ec59eeaSAnirudh Venkataramanan u32 tail; 567ec59eeaSAnirudh Venkataramanan u32 len; 577ec59eeaSAnirudh Venkataramanan u32 bah; 587ec59eeaSAnirudh Venkataramanan u32 bal; 597ec59eeaSAnirudh Venkataramanan u32 len_mask; 607ec59eeaSAnirudh Venkataramanan u32 len_ena_mask; 617ec59eeaSAnirudh Venkataramanan u32 head_mask; 627ec59eeaSAnirudh Venkataramanan }; 637ec59eeaSAnirudh Venkataramanan 647ec59eeaSAnirudh Venkataramanan /* sq transaction details */ 657ec59eeaSAnirudh Venkataramanan struct ice_sq_cd { 667ec59eeaSAnirudh Venkataramanan struct ice_aq_desc *wb_desc; 677ec59eeaSAnirudh Venkataramanan }; 687ec59eeaSAnirudh Venkataramanan 697ec59eeaSAnirudh Venkataramanan #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i])) 707ec59eeaSAnirudh Venkataramanan 71940b61afSAnirudh Venkataramanan /* rq event information */ 72940b61afSAnirudh Venkataramanan struct ice_rq_event_info { 73940b61afSAnirudh Venkataramanan struct ice_aq_desc desc; 74940b61afSAnirudh Venkataramanan u16 msg_len; 75940b61afSAnirudh Venkataramanan u16 buf_len; 76940b61afSAnirudh Venkataramanan u8 *msg_buf; 77940b61afSAnirudh Venkataramanan }; 78940b61afSAnirudh Venkataramanan 797ec59eeaSAnirudh Venkataramanan /* Control Queue information */ 807ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_info { 817ec59eeaSAnirudh Venkataramanan enum ice_ctl_q qtype; 8206905270SJesse Brandeburg enum ice_aq_err rq_last_status; /* last status on receive queue */ 837ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring rq; /* receive queue */ 847ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_ring sq; /* send queue */ 857ec59eeaSAnirudh Venkataramanan u32 sq_cmd_timeout; /* send queue cmd write back timeout */ 867ec59eeaSAnirudh Venkataramanan u16 num_rq_entries; /* receive queue depth */ 877ec59eeaSAnirudh Venkataramanan u16 num_sq_entries; /* send queue depth */ 887ec59eeaSAnirudh Venkataramanan u16 rq_buf_size; /* receive queue buffer size */ 897ec59eeaSAnirudh Venkataramanan u16 sq_buf_size; /* send queue buffer size */ 9006905270SJesse Brandeburg enum ice_aq_err sq_last_status; /* last status on send queue */ 917ec59eeaSAnirudh Venkataramanan struct mutex sq_lock; /* Send queue lock */ 927ec59eeaSAnirudh Venkataramanan struct mutex rq_lock; /* Receive queue lock */ 937ec59eeaSAnirudh Venkataramanan }; 947ec59eeaSAnirudh Venkataramanan 957ec59eeaSAnirudh Venkataramanan #endif /* _ICE_CONTROLQ_H_ */ 96