1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 9 #define ICE_PF_RESET_WAIT_COUNT 300 10 11 static const char * const ice_link_mode_str_low[] = { 12 [0] = "100BASE_TX", 13 [1] = "100M_SGMII", 14 [2] = "1000BASE_T", 15 [3] = "1000BASE_SX", 16 [4] = "1000BASE_LX", 17 [5] = "1000BASE_KX", 18 [6] = "1G_SGMII", 19 [7] = "2500BASE_T", 20 [8] = "2500BASE_X", 21 [9] = "2500BASE_KX", 22 [10] = "5GBASE_T", 23 [11] = "5GBASE_KR", 24 [12] = "10GBASE_T", 25 [13] = "10G_SFI_DA", 26 [14] = "10GBASE_SR", 27 [15] = "10GBASE_LR", 28 [16] = "10GBASE_KR_CR1", 29 [17] = "10G_SFI_AOC_ACC", 30 [18] = "10G_SFI_C2C", 31 [19] = "25GBASE_T", 32 [20] = "25GBASE_CR", 33 [21] = "25GBASE_CR_S", 34 [22] = "25GBASE_CR1", 35 [23] = "25GBASE_SR", 36 [24] = "25GBASE_LR", 37 [25] = "25GBASE_KR", 38 [26] = "25GBASE_KR_S", 39 [27] = "25GBASE_KR1", 40 [28] = "25G_AUI_AOC_ACC", 41 [29] = "25G_AUI_C2C", 42 [30] = "40GBASE_CR4", 43 [31] = "40GBASE_SR4", 44 [32] = "40GBASE_LR4", 45 [33] = "40GBASE_KR4", 46 [34] = "40G_XLAUI_AOC_ACC", 47 [35] = "40G_XLAUI", 48 [36] = "50GBASE_CR2", 49 [37] = "50GBASE_SR2", 50 [38] = "50GBASE_LR2", 51 [39] = "50GBASE_KR2", 52 [40] = "50G_LAUI2_AOC_ACC", 53 [41] = "50G_LAUI2", 54 [42] = "50G_AUI2_AOC_ACC", 55 [43] = "50G_AUI2", 56 [44] = "50GBASE_CP", 57 [45] = "50GBASE_SR", 58 [46] = "50GBASE_FR", 59 [47] = "50GBASE_LR", 60 [48] = "50GBASE_KR_PAM4", 61 [49] = "50G_AUI1_AOC_ACC", 62 [50] = "50G_AUI1", 63 [51] = "100GBASE_CR4", 64 [52] = "100GBASE_SR4", 65 [53] = "100GBASE_LR4", 66 [54] = "100GBASE_KR4", 67 [55] = "100G_CAUI4_AOC_ACC", 68 [56] = "100G_CAUI4", 69 [57] = "100G_AUI4_AOC_ACC", 70 [58] = "100G_AUI4", 71 [59] = "100GBASE_CR_PAM4", 72 [60] = "100GBASE_KR_PAM4", 73 [61] = "100GBASE_CP2", 74 [62] = "100GBASE_SR2", 75 [63] = "100GBASE_DR", 76 }; 77 78 static const char * const ice_link_mode_str_high[] = { 79 [0] = "100GBASE_KR2_PAM4", 80 [1] = "100G_CAUI2_AOC_ACC", 81 [2] = "100G_CAUI2", 82 [3] = "100G_AUI2_AOC_ACC", 83 [4] = "100G_AUI2", 84 }; 85 86 /** 87 * ice_dump_phy_type - helper function to dump phy_type 88 * @hw: pointer to the HW structure 89 * @low: 64 bit value for phy_type_low 90 * @high: 64 bit value for phy_type_high 91 * @prefix: prefix string to differentiate multiple dumps 92 */ 93 static void 94 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 95 { 96 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 97 98 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 99 if (low & BIT_ULL(i)) 100 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 101 prefix, i, ice_link_mode_str_low[i]); 102 } 103 104 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 105 106 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 107 if (high & BIT_ULL(i)) 108 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 109 prefix, i, ice_link_mode_str_high[i]); 110 } 111 } 112 113 /** 114 * ice_set_mac_type - Sets MAC type 115 * @hw: pointer to the HW structure 116 * 117 * This function sets the MAC type of the adapter based on the 118 * vendor ID and device ID stored in the HW structure. 119 */ 120 static int ice_set_mac_type(struct ice_hw *hw) 121 { 122 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 123 return -ENODEV; 124 125 switch (hw->device_id) { 126 case ICE_DEV_ID_E810C_BACKPLANE: 127 case ICE_DEV_ID_E810C_QSFP: 128 case ICE_DEV_ID_E810C_SFP: 129 case ICE_DEV_ID_E810_XXV_BACKPLANE: 130 case ICE_DEV_ID_E810_XXV_QSFP: 131 case ICE_DEV_ID_E810_XXV_SFP: 132 hw->mac_type = ICE_MAC_E810; 133 break; 134 case ICE_DEV_ID_E823C_10G_BASE_T: 135 case ICE_DEV_ID_E823C_BACKPLANE: 136 case ICE_DEV_ID_E823C_QSFP: 137 case ICE_DEV_ID_E823C_SFP: 138 case ICE_DEV_ID_E823C_SGMII: 139 case ICE_DEV_ID_E822C_10G_BASE_T: 140 case ICE_DEV_ID_E822C_BACKPLANE: 141 case ICE_DEV_ID_E822C_QSFP: 142 case ICE_DEV_ID_E822C_SFP: 143 case ICE_DEV_ID_E822C_SGMII: 144 case ICE_DEV_ID_E822L_10G_BASE_T: 145 case ICE_DEV_ID_E822L_BACKPLANE: 146 case ICE_DEV_ID_E822L_SFP: 147 case ICE_DEV_ID_E822L_SGMII: 148 case ICE_DEV_ID_E823L_10G_BASE_T: 149 case ICE_DEV_ID_E823L_1GBE: 150 case ICE_DEV_ID_E823L_BACKPLANE: 151 case ICE_DEV_ID_E823L_QSFP: 152 case ICE_DEV_ID_E823L_SFP: 153 hw->mac_type = ICE_MAC_GENERIC; 154 break; 155 default: 156 hw->mac_type = ICE_MAC_UNKNOWN; 157 break; 158 } 159 160 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 161 return 0; 162 } 163 164 /** 165 * ice_is_e810 166 * @hw: pointer to the hardware structure 167 * 168 * returns true if the device is E810 based, false if not. 169 */ 170 bool ice_is_e810(struct ice_hw *hw) 171 { 172 return hw->mac_type == ICE_MAC_E810; 173 } 174 175 /** 176 * ice_is_e810t 177 * @hw: pointer to the hardware structure 178 * 179 * returns true if the device is E810T based, false if not. 180 */ 181 bool ice_is_e810t(struct ice_hw *hw) 182 { 183 switch (hw->device_id) { 184 case ICE_DEV_ID_E810C_SFP: 185 if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T || 186 hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2) 187 return true; 188 break; 189 default: 190 break; 191 } 192 193 return false; 194 } 195 196 /** 197 * ice_clear_pf_cfg - Clear PF configuration 198 * @hw: pointer to the hardware structure 199 * 200 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 201 * configuration, flow director filters, etc.). 202 */ 203 int ice_clear_pf_cfg(struct ice_hw *hw) 204 { 205 struct ice_aq_desc desc; 206 207 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 208 209 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 210 } 211 212 /** 213 * ice_aq_manage_mac_read - manage MAC address read command 214 * @hw: pointer to the HW struct 215 * @buf: a virtual buffer to hold the manage MAC read response 216 * @buf_size: Size of the virtual buffer 217 * @cd: pointer to command details structure or NULL 218 * 219 * This function is used to return per PF station MAC address (0x0107). 220 * NOTE: Upon successful completion of this command, MAC address information 221 * is returned in user specified buffer. Please interpret user specified 222 * buffer as "manage_mac_read" response. 223 * Response such as various MAC addresses are stored in HW struct (port.mac) 224 * ice_discover_dev_caps is expected to be called before this function is 225 * called. 226 */ 227 static int 228 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 229 struct ice_sq_cd *cd) 230 { 231 struct ice_aqc_manage_mac_read_resp *resp; 232 struct ice_aqc_manage_mac_read *cmd; 233 struct ice_aq_desc desc; 234 int status; 235 u16 flags; 236 u8 i; 237 238 cmd = &desc.params.mac_read; 239 240 if (buf_size < sizeof(*resp)) 241 return -EINVAL; 242 243 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 244 245 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 246 if (status) 247 return status; 248 249 resp = buf; 250 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 251 252 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 253 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 254 return -EIO; 255 } 256 257 /* A single port can report up to two (LAN and WoL) addresses */ 258 for (i = 0; i < cmd->num_addr; i++) 259 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 260 ether_addr_copy(hw->port_info->mac.lan_addr, 261 resp[i].mac_addr); 262 ether_addr_copy(hw->port_info->mac.perm_addr, 263 resp[i].mac_addr); 264 break; 265 } 266 267 return 0; 268 } 269 270 /** 271 * ice_aq_get_phy_caps - returns PHY capabilities 272 * @pi: port information structure 273 * @qual_mods: report qualified modules 274 * @report_mode: report mode capabilities 275 * @pcaps: structure for PHY capabilities to be filled 276 * @cd: pointer to command details structure or NULL 277 * 278 * Returns the various PHY capabilities supported on the Port (0x0600) 279 */ 280 int 281 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 282 struct ice_aqc_get_phy_caps_data *pcaps, 283 struct ice_sq_cd *cd) 284 { 285 struct ice_aqc_get_phy_caps *cmd; 286 u16 pcaps_size = sizeof(*pcaps); 287 struct ice_aq_desc desc; 288 const char *prefix; 289 struct ice_hw *hw; 290 int status; 291 292 cmd = &desc.params.get_phy; 293 294 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 295 return -EINVAL; 296 hw = pi->hw; 297 298 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 299 !ice_fw_supports_report_dflt_cfg(hw)) 300 return -EINVAL; 301 302 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 303 304 if (qual_mods) 305 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 306 307 cmd->param0 |= cpu_to_le16(report_mode); 308 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 309 310 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 311 312 switch (report_mode) { 313 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 314 prefix = "phy_caps_media"; 315 break; 316 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 317 prefix = "phy_caps_no_media"; 318 break; 319 case ICE_AQC_REPORT_ACTIVE_CFG: 320 prefix = "phy_caps_active"; 321 break; 322 case ICE_AQC_REPORT_DFLT_CFG: 323 prefix = "phy_caps_default"; 324 break; 325 default: 326 prefix = "phy_caps_invalid"; 327 } 328 329 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 330 le64_to_cpu(pcaps->phy_type_high), prefix); 331 332 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 333 prefix, report_mode); 334 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 335 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 336 pcaps->low_power_ctrl_an); 337 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 338 pcaps->eee_cap); 339 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 340 pcaps->eeer_value); 341 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 342 pcaps->link_fec_options); 343 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 344 prefix, pcaps->module_compliance_enforcement); 345 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 346 prefix, pcaps->extended_compliance_code); 347 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 348 pcaps->module_type[0]); 349 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 350 pcaps->module_type[1]); 351 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 352 pcaps->module_type[2]); 353 354 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 355 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 356 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 357 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 358 sizeof(pi->phy.link_info.module_type)); 359 } 360 361 return status; 362 } 363 364 /** 365 * ice_aq_get_link_topo_handle - get link topology node return status 366 * @pi: port information structure 367 * @node_type: requested node type 368 * @cd: pointer to command details structure or NULL 369 * 370 * Get link topology node return status for specified node type (0x06E0) 371 * 372 * Node type cage can be used to determine if cage is present. If AQC 373 * returns error (ENOENT), then no cage present. If no cage present, then 374 * connection type is backplane or BASE-T. 375 */ 376 static int 377 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 378 struct ice_sq_cd *cd) 379 { 380 struct ice_aqc_get_link_topo *cmd; 381 struct ice_aq_desc desc; 382 383 cmd = &desc.params.get_link_topo; 384 385 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 386 387 cmd->addr.topo_params.node_type_ctx = 388 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 389 ICE_AQC_LINK_TOPO_NODE_CTX_S); 390 391 /* set node type */ 392 cmd->addr.topo_params.node_type_ctx |= 393 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 394 395 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 396 } 397 398 /** 399 * ice_is_media_cage_present 400 * @pi: port information structure 401 * 402 * Returns true if media cage is present, else false. If no cage, then 403 * media type is backplane or BASE-T. 404 */ 405 static bool ice_is_media_cage_present(struct ice_port_info *pi) 406 { 407 /* Node type cage can be used to determine if cage is present. If AQC 408 * returns error (ENOENT), then no cage present. If no cage present then 409 * connection type is backplane or BASE-T. 410 */ 411 return !ice_aq_get_link_topo_handle(pi, 412 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 413 NULL); 414 } 415 416 /** 417 * ice_get_media_type - Gets media type 418 * @pi: port information structure 419 */ 420 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 421 { 422 struct ice_link_status *hw_link_info; 423 424 if (!pi) 425 return ICE_MEDIA_UNKNOWN; 426 427 hw_link_info = &pi->phy.link_info; 428 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 429 /* If more than one media type is selected, report unknown */ 430 return ICE_MEDIA_UNKNOWN; 431 432 if (hw_link_info->phy_type_low) { 433 /* 1G SGMII is a special case where some DA cable PHYs 434 * may show this as an option when it really shouldn't 435 * be since SGMII is meant to be between a MAC and a PHY 436 * in a backplane. Try to detect this case and handle it 437 */ 438 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 439 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 440 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 441 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 442 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 443 return ICE_MEDIA_DA; 444 445 switch (hw_link_info->phy_type_low) { 446 case ICE_PHY_TYPE_LOW_1000BASE_SX: 447 case ICE_PHY_TYPE_LOW_1000BASE_LX: 448 case ICE_PHY_TYPE_LOW_10GBASE_SR: 449 case ICE_PHY_TYPE_LOW_10GBASE_LR: 450 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 451 case ICE_PHY_TYPE_LOW_25GBASE_SR: 452 case ICE_PHY_TYPE_LOW_25GBASE_LR: 453 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 454 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 455 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 456 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 457 case ICE_PHY_TYPE_LOW_50GBASE_SR: 458 case ICE_PHY_TYPE_LOW_50GBASE_FR: 459 case ICE_PHY_TYPE_LOW_50GBASE_LR: 460 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 461 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 462 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 463 case ICE_PHY_TYPE_LOW_100GBASE_DR: 464 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 465 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 466 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 467 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 468 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 469 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 470 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 471 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 472 return ICE_MEDIA_FIBER; 473 case ICE_PHY_TYPE_LOW_100BASE_TX: 474 case ICE_PHY_TYPE_LOW_1000BASE_T: 475 case ICE_PHY_TYPE_LOW_2500BASE_T: 476 case ICE_PHY_TYPE_LOW_5GBASE_T: 477 case ICE_PHY_TYPE_LOW_10GBASE_T: 478 case ICE_PHY_TYPE_LOW_25GBASE_T: 479 return ICE_MEDIA_BASET; 480 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 481 case ICE_PHY_TYPE_LOW_25GBASE_CR: 482 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 483 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 484 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 485 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 486 case ICE_PHY_TYPE_LOW_50GBASE_CP: 487 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 488 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 489 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 490 return ICE_MEDIA_DA; 491 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 492 case ICE_PHY_TYPE_LOW_40G_XLAUI: 493 case ICE_PHY_TYPE_LOW_50G_LAUI2: 494 case ICE_PHY_TYPE_LOW_50G_AUI2: 495 case ICE_PHY_TYPE_LOW_50G_AUI1: 496 case ICE_PHY_TYPE_LOW_100G_AUI4: 497 case ICE_PHY_TYPE_LOW_100G_CAUI4: 498 if (ice_is_media_cage_present(pi)) 499 return ICE_MEDIA_DA; 500 fallthrough; 501 case ICE_PHY_TYPE_LOW_1000BASE_KX: 502 case ICE_PHY_TYPE_LOW_2500BASE_KX: 503 case ICE_PHY_TYPE_LOW_2500BASE_X: 504 case ICE_PHY_TYPE_LOW_5GBASE_KR: 505 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 506 case ICE_PHY_TYPE_LOW_25GBASE_KR: 507 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 508 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 509 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 510 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 511 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 512 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 513 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 514 return ICE_MEDIA_BACKPLANE; 515 } 516 } else { 517 switch (hw_link_info->phy_type_high) { 518 case ICE_PHY_TYPE_HIGH_100G_AUI2: 519 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 520 if (ice_is_media_cage_present(pi)) 521 return ICE_MEDIA_DA; 522 fallthrough; 523 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 524 return ICE_MEDIA_BACKPLANE; 525 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 526 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 527 return ICE_MEDIA_FIBER; 528 } 529 } 530 return ICE_MEDIA_UNKNOWN; 531 } 532 533 /** 534 * ice_aq_get_link_info 535 * @pi: port information structure 536 * @ena_lse: enable/disable LinkStatusEvent reporting 537 * @link: pointer to link status structure - optional 538 * @cd: pointer to command details structure or NULL 539 * 540 * Get Link Status (0x607). Returns the link status of the adapter. 541 */ 542 int 543 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 544 struct ice_link_status *link, struct ice_sq_cd *cd) 545 { 546 struct ice_aqc_get_link_status_data link_data = { 0 }; 547 struct ice_aqc_get_link_status *resp; 548 struct ice_link_status *li_old, *li; 549 enum ice_media_type *hw_media_type; 550 struct ice_fc_info *hw_fc_info; 551 bool tx_pause, rx_pause; 552 struct ice_aq_desc desc; 553 struct ice_hw *hw; 554 u16 cmd_flags; 555 int status; 556 557 if (!pi) 558 return -EINVAL; 559 hw = pi->hw; 560 li_old = &pi->phy.link_info_old; 561 hw_media_type = &pi->phy.media_type; 562 li = &pi->phy.link_info; 563 hw_fc_info = &pi->fc; 564 565 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 566 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 567 resp = &desc.params.get_link_status; 568 resp->cmd_flags = cpu_to_le16(cmd_flags); 569 resp->lport_num = pi->lport; 570 571 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 572 573 if (status) 574 return status; 575 576 /* save off old link status information */ 577 *li_old = *li; 578 579 /* update current link status information */ 580 li->link_speed = le16_to_cpu(link_data.link_speed); 581 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 582 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 583 *hw_media_type = ice_get_media_type(pi); 584 li->link_info = link_data.link_info; 585 li->link_cfg_err = link_data.link_cfg_err; 586 li->an_info = link_data.an_info; 587 li->ext_info = link_data.ext_info; 588 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 589 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 590 li->topo_media_conflict = link_data.topo_media_conflict; 591 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 592 ICE_AQ_CFG_PACING_TYPE_M); 593 594 /* update fc info */ 595 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 596 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 597 if (tx_pause && rx_pause) 598 hw_fc_info->current_mode = ICE_FC_FULL; 599 else if (tx_pause) 600 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 601 else if (rx_pause) 602 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 603 else 604 hw_fc_info->current_mode = ICE_FC_NONE; 605 606 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 607 608 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 609 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 610 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 611 (unsigned long long)li->phy_type_low); 612 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 613 (unsigned long long)li->phy_type_high); 614 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 615 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 616 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 617 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 618 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 619 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 620 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 621 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 622 li->max_frame_size); 623 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 624 625 /* save link status information */ 626 if (link) 627 *link = *li; 628 629 /* flag cleared so calling functions don't call AQ again */ 630 pi->phy.get_link_info = false; 631 632 return 0; 633 } 634 635 /** 636 * ice_fill_tx_timer_and_fc_thresh 637 * @hw: pointer to the HW struct 638 * @cmd: pointer to MAC cfg structure 639 * 640 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 641 * descriptor 642 */ 643 static void 644 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 645 struct ice_aqc_set_mac_cfg *cmd) 646 { 647 u16 fc_thres_val, tx_timer_val; 648 u32 val; 649 650 /* We read back the transmit timer and FC threshold value of 651 * LFC. Thus, we will use index = 652 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 653 * 654 * Also, because we are operating on transmit timer and FC 655 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 656 */ 657 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 658 659 /* Retrieve the transmit timer */ 660 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 661 tx_timer_val = val & 662 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 663 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val); 664 665 /* Retrieve the FC threshold */ 666 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 667 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 668 669 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val); 670 } 671 672 /** 673 * ice_aq_set_mac_cfg 674 * @hw: pointer to the HW struct 675 * @max_frame_size: Maximum Frame Size to be supported 676 * @cd: pointer to command details structure or NULL 677 * 678 * Set MAC configuration (0x0603) 679 */ 680 int 681 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 682 { 683 struct ice_aqc_set_mac_cfg *cmd; 684 struct ice_aq_desc desc; 685 686 cmd = &desc.params.set_mac_cfg; 687 688 if (max_frame_size == 0) 689 return -EINVAL; 690 691 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 692 693 cmd->max_frame_size = cpu_to_le16(max_frame_size); 694 695 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 696 697 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 698 } 699 700 /** 701 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 702 * @hw: pointer to the HW struct 703 */ 704 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 705 { 706 struct ice_switch_info *sw; 707 int status; 708 709 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 710 sizeof(*hw->switch_info), GFP_KERNEL); 711 sw = hw->switch_info; 712 713 if (!sw) 714 return -ENOMEM; 715 716 INIT_LIST_HEAD(&sw->vsi_list_map_head); 717 sw->prof_res_bm_init = 0; 718 719 status = ice_init_def_sw_recp(hw); 720 if (status) { 721 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 722 return status; 723 } 724 return 0; 725 } 726 727 /** 728 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 729 * @hw: pointer to the HW struct 730 */ 731 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 732 { 733 struct ice_switch_info *sw = hw->switch_info; 734 struct ice_vsi_list_map_info *v_pos_map; 735 struct ice_vsi_list_map_info *v_tmp_map; 736 struct ice_sw_recipe *recps; 737 u8 i; 738 739 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 740 list_entry) { 741 list_del(&v_pos_map->list_entry); 742 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 743 } 744 recps = sw->recp_list; 745 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 746 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 747 748 recps[i].root_rid = i; 749 list_for_each_entry_safe(rg_entry, tmprg_entry, 750 &recps[i].rg_list, l_entry) { 751 list_del(&rg_entry->l_entry); 752 devm_kfree(ice_hw_to_dev(hw), rg_entry); 753 } 754 755 if (recps[i].adv_rule) { 756 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 757 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 758 759 mutex_destroy(&recps[i].filt_rule_lock); 760 list_for_each_entry_safe(lst_itr, tmp_entry, 761 &recps[i].filt_rules, 762 list_entry) { 763 list_del(&lst_itr->list_entry); 764 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 765 devm_kfree(ice_hw_to_dev(hw), lst_itr); 766 } 767 } else { 768 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 769 770 mutex_destroy(&recps[i].filt_rule_lock); 771 list_for_each_entry_safe(lst_itr, tmp_entry, 772 &recps[i].filt_rules, 773 list_entry) { 774 list_del(&lst_itr->list_entry); 775 devm_kfree(ice_hw_to_dev(hw), lst_itr); 776 } 777 } 778 if (recps[i].root_buf) 779 devm_kfree(ice_hw_to_dev(hw), recps[i].root_buf); 780 } 781 ice_rm_all_sw_replay_rule_info(hw); 782 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 783 devm_kfree(ice_hw_to_dev(hw), sw); 784 } 785 786 /** 787 * ice_get_fw_log_cfg - get FW logging configuration 788 * @hw: pointer to the HW struct 789 */ 790 static int ice_get_fw_log_cfg(struct ice_hw *hw) 791 { 792 struct ice_aq_desc desc; 793 __le16 *config; 794 int status; 795 u16 size; 796 797 size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX; 798 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL); 799 if (!config) 800 return -ENOMEM; 801 802 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 803 804 status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 805 if (!status) { 806 u16 i; 807 808 /* Save FW logging information into the HW structure */ 809 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 810 u16 v, m, flgs; 811 812 v = le16_to_cpu(config[i]); 813 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 814 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 815 816 if (m < ICE_AQC_FW_LOG_ID_MAX) 817 hw->fw_log.evnts[m].cur = flgs; 818 } 819 } 820 821 devm_kfree(ice_hw_to_dev(hw), config); 822 823 return status; 824 } 825 826 /** 827 * ice_cfg_fw_log - configure FW logging 828 * @hw: pointer to the HW struct 829 * @enable: enable certain FW logging events if true, disable all if false 830 * 831 * This function enables/disables the FW logging via Rx CQ events and a UART 832 * port based on predetermined configurations. FW logging via the Rx CQ can be 833 * enabled/disabled for individual PF's. However, FW logging via the UART can 834 * only be enabled/disabled for all PFs on the same device. 835 * 836 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 837 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 838 * before initializing the device. 839 * 840 * When re/configuring FW logging, callers need to update the "cfg" elements of 841 * the hw->fw_log.evnts array with the desired logging event configurations for 842 * modules of interest. When disabling FW logging completely, the callers can 843 * just pass false in the "enable" parameter. On completion, the function will 844 * update the "cur" element of the hw->fw_log.evnts array with the resulting 845 * logging event configurations of the modules that are being re/configured. FW 846 * logging modules that are not part of a reconfiguration operation retain their 847 * previous states. 848 * 849 * Before resetting the device, it is recommended that the driver disables FW 850 * logging before shutting down the control queue. When disabling FW logging 851 * ("enable" = false), the latest configurations of FW logging events stored in 852 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 853 * a device reset. 854 * 855 * When enabling FW logging to emit log messages via the Rx CQ during the 856 * device's initialization phase, a mechanism alternative to interrupt handlers 857 * needs to be used to extract FW log messages from the Rx CQ periodically and 858 * to prevent the Rx CQ from being full and stalling other types of control 859 * messages from FW to SW. Interrupts are typically disabled during the device's 860 * initialization phase. 861 */ 862 static int ice_cfg_fw_log(struct ice_hw *hw, bool enable) 863 { 864 struct ice_aqc_fw_logging *cmd; 865 u16 i, chgs = 0, len = 0; 866 struct ice_aq_desc desc; 867 __le16 *data = NULL; 868 u8 actv_evnts = 0; 869 void *buf = NULL; 870 int status = 0; 871 872 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 873 return 0; 874 875 /* Disable FW logging only when the control queue is still responsive */ 876 if (!enable && 877 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 878 return 0; 879 880 /* Get current FW log settings */ 881 status = ice_get_fw_log_cfg(hw); 882 if (status) 883 return status; 884 885 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 886 cmd = &desc.params.fw_logging; 887 888 /* Indicate which controls are valid */ 889 if (hw->fw_log.cq_en) 890 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 891 892 if (hw->fw_log.uart_en) 893 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 894 895 if (enable) { 896 /* Fill in an array of entries with FW logging modules and 897 * logging events being reconfigured. 898 */ 899 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 900 u16 val; 901 902 /* Keep track of enabled event types */ 903 actv_evnts |= hw->fw_log.evnts[i].cfg; 904 905 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 906 continue; 907 908 if (!data) { 909 data = devm_kcalloc(ice_hw_to_dev(hw), 910 ICE_AQC_FW_LOG_ID_MAX, 911 sizeof(*data), 912 GFP_KERNEL); 913 if (!data) 914 return -ENOMEM; 915 } 916 917 val = i << ICE_AQC_FW_LOG_ID_S; 918 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 919 data[chgs++] = cpu_to_le16(val); 920 } 921 922 /* Only enable FW logging if at least one module is specified. 923 * If FW logging is currently enabled but all modules are not 924 * enabled to emit log messages, disable FW logging altogether. 925 */ 926 if (actv_evnts) { 927 /* Leave if there is effectively no change */ 928 if (!chgs) 929 goto out; 930 931 if (hw->fw_log.cq_en) 932 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 933 934 if (hw->fw_log.uart_en) 935 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 936 937 buf = data; 938 len = sizeof(*data) * chgs; 939 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 940 } 941 } 942 943 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 944 if (!status) { 945 /* Update the current configuration to reflect events enabled. 946 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 947 * logging mode is enabled for the device. They do not reflect 948 * actual modules being enabled to emit log messages. So, their 949 * values remain unchanged even when all modules are disabled. 950 */ 951 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 952 953 hw->fw_log.actv_evnts = actv_evnts; 954 for (i = 0; i < cnt; i++) { 955 u16 v, m; 956 957 if (!enable) { 958 /* When disabling all FW logging events as part 959 * of device's de-initialization, the original 960 * configurations are retained, and can be used 961 * to reconfigure FW logging later if the device 962 * is re-initialized. 963 */ 964 hw->fw_log.evnts[i].cur = 0; 965 continue; 966 } 967 968 v = le16_to_cpu(data[i]); 969 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 970 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 971 } 972 } 973 974 out: 975 if (data) 976 devm_kfree(ice_hw_to_dev(hw), data); 977 978 return status; 979 } 980 981 /** 982 * ice_output_fw_log 983 * @hw: pointer to the HW struct 984 * @desc: pointer to the AQ message descriptor 985 * @buf: pointer to the buffer accompanying the AQ message 986 * 987 * Formats a FW Log message and outputs it via the standard driver logs. 988 */ 989 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 990 { 991 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 992 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 993 le16_to_cpu(desc->datalen)); 994 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 995 } 996 997 /** 998 * ice_get_itr_intrl_gran 999 * @hw: pointer to the HW struct 1000 * 1001 * Determines the ITR/INTRL granularities based on the maximum aggregate 1002 * bandwidth according to the device's configuration during power-on. 1003 */ 1004 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 1005 { 1006 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 1007 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 1008 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 1009 1010 switch (max_agg_bw) { 1011 case ICE_MAX_AGG_BW_200G: 1012 case ICE_MAX_AGG_BW_100G: 1013 case ICE_MAX_AGG_BW_50G: 1014 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 1015 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 1016 break; 1017 case ICE_MAX_AGG_BW_25G: 1018 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 1019 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 1020 break; 1021 } 1022 } 1023 1024 /** 1025 * ice_init_hw - main hardware initialization routine 1026 * @hw: pointer to the hardware structure 1027 */ 1028 int ice_init_hw(struct ice_hw *hw) 1029 { 1030 struct ice_aqc_get_phy_caps_data *pcaps; 1031 u16 mac_buf_len; 1032 void *mac_buf; 1033 int status; 1034 1035 /* Set MAC type based on DeviceID */ 1036 status = ice_set_mac_type(hw); 1037 if (status) 1038 return status; 1039 1040 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 1041 PF_FUNC_RID_FUNC_NUM_M) >> 1042 PF_FUNC_RID_FUNC_NUM_S; 1043 1044 status = ice_reset(hw, ICE_RESET_PFR); 1045 if (status) 1046 return status; 1047 1048 ice_get_itr_intrl_gran(hw); 1049 1050 status = ice_create_all_ctrlq(hw); 1051 if (status) 1052 goto err_unroll_cqinit; 1053 1054 /* Enable FW logging. Not fatal if this fails. */ 1055 status = ice_cfg_fw_log(hw, true); 1056 if (status) 1057 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 1058 1059 status = ice_clear_pf_cfg(hw); 1060 if (status) 1061 goto err_unroll_cqinit; 1062 1063 /* Set bit to enable Flow Director filters */ 1064 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1065 INIT_LIST_HEAD(&hw->fdir_list_head); 1066 1067 ice_clear_pxe_mode(hw); 1068 1069 status = ice_init_nvm(hw); 1070 if (status) 1071 goto err_unroll_cqinit; 1072 1073 status = ice_get_caps(hw); 1074 if (status) 1075 goto err_unroll_cqinit; 1076 1077 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1078 sizeof(*hw->port_info), GFP_KERNEL); 1079 if (!hw->port_info) { 1080 status = -ENOMEM; 1081 goto err_unroll_cqinit; 1082 } 1083 1084 /* set the back pointer to HW */ 1085 hw->port_info->hw = hw; 1086 1087 /* Initialize port_info struct with switch configuration data */ 1088 status = ice_get_initial_sw_cfg(hw); 1089 if (status) 1090 goto err_unroll_alloc; 1091 1092 hw->evb_veb = true; 1093 1094 /* Query the allocated resources for Tx scheduler */ 1095 status = ice_sched_query_res_alloc(hw); 1096 if (status) { 1097 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1098 goto err_unroll_alloc; 1099 } 1100 ice_sched_get_psm_clk_freq(hw); 1101 1102 /* Initialize port_info struct with scheduler data */ 1103 status = ice_sched_init_port(hw->port_info); 1104 if (status) 1105 goto err_unroll_sched; 1106 1107 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 1108 if (!pcaps) { 1109 status = -ENOMEM; 1110 goto err_unroll_sched; 1111 } 1112 1113 /* Initialize port_info struct with PHY capabilities */ 1114 status = ice_aq_get_phy_caps(hw->port_info, false, 1115 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1116 NULL); 1117 devm_kfree(ice_hw_to_dev(hw), pcaps); 1118 if (status) 1119 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1120 status); 1121 1122 /* Initialize port_info struct with link information */ 1123 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1124 if (status) 1125 goto err_unroll_sched; 1126 1127 /* need a valid SW entry point to build a Tx tree */ 1128 if (!hw->sw_entry_point_layer) { 1129 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1130 status = -EIO; 1131 goto err_unroll_sched; 1132 } 1133 INIT_LIST_HEAD(&hw->agg_list); 1134 /* Initialize max burst size */ 1135 if (!hw->max_burst_size) 1136 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1137 1138 status = ice_init_fltr_mgmt_struct(hw); 1139 if (status) 1140 goto err_unroll_sched; 1141 1142 /* Get MAC information */ 1143 /* A single port can report up to two (LAN and WoL) addresses */ 1144 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 1145 sizeof(struct ice_aqc_manage_mac_read_resp), 1146 GFP_KERNEL); 1147 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1148 1149 if (!mac_buf) { 1150 status = -ENOMEM; 1151 goto err_unroll_fltr_mgmt_struct; 1152 } 1153 1154 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1155 devm_kfree(ice_hw_to_dev(hw), mac_buf); 1156 1157 if (status) 1158 goto err_unroll_fltr_mgmt_struct; 1159 /* enable jumbo frame support at MAC level */ 1160 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1161 if (status) 1162 goto err_unroll_fltr_mgmt_struct; 1163 /* Obtain counter base index which would be used by flow director */ 1164 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1165 if (status) 1166 goto err_unroll_fltr_mgmt_struct; 1167 status = ice_init_hw_tbls(hw); 1168 if (status) 1169 goto err_unroll_fltr_mgmt_struct; 1170 mutex_init(&hw->tnl_lock); 1171 return 0; 1172 1173 err_unroll_fltr_mgmt_struct: 1174 ice_cleanup_fltr_mgmt_struct(hw); 1175 err_unroll_sched: 1176 ice_sched_cleanup_all(hw); 1177 err_unroll_alloc: 1178 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1179 err_unroll_cqinit: 1180 ice_destroy_all_ctrlq(hw); 1181 return status; 1182 } 1183 1184 /** 1185 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1186 * @hw: pointer to the hardware structure 1187 * 1188 * This should be called only during nominal operation, not as a result of 1189 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1190 * applicable initializations if it fails for any reason. 1191 */ 1192 void ice_deinit_hw(struct ice_hw *hw) 1193 { 1194 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1195 ice_cleanup_fltr_mgmt_struct(hw); 1196 1197 ice_sched_cleanup_all(hw); 1198 ice_sched_clear_agg(hw); 1199 ice_free_seg(hw); 1200 ice_free_hw_tbls(hw); 1201 mutex_destroy(&hw->tnl_lock); 1202 1203 if (hw->port_info) { 1204 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1205 hw->port_info = NULL; 1206 } 1207 1208 /* Attempt to disable FW logging before shutting down control queues */ 1209 ice_cfg_fw_log(hw, false); 1210 ice_destroy_all_ctrlq(hw); 1211 1212 /* Clear VSI contexts if not already cleared */ 1213 ice_clear_all_vsi_ctx(hw); 1214 } 1215 1216 /** 1217 * ice_check_reset - Check to see if a global reset is complete 1218 * @hw: pointer to the hardware structure 1219 */ 1220 int ice_check_reset(struct ice_hw *hw) 1221 { 1222 u32 cnt, reg = 0, grst_timeout, uld_mask; 1223 1224 /* Poll for Device Active state in case a recent CORER, GLOBR, 1225 * or EMPR has occurred. The grst delay value is in 100ms units. 1226 * Add 1sec for outstanding AQ commands that can take a long time. 1227 */ 1228 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1229 GLGEN_RSTCTL_GRSTDEL_S) + 10; 1230 1231 for (cnt = 0; cnt < grst_timeout; cnt++) { 1232 mdelay(100); 1233 reg = rd32(hw, GLGEN_RSTAT); 1234 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1235 break; 1236 } 1237 1238 if (cnt == grst_timeout) { 1239 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1240 return -EIO; 1241 } 1242 1243 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1244 GLNVM_ULD_PCIER_DONE_1_M |\ 1245 GLNVM_ULD_CORER_DONE_M |\ 1246 GLNVM_ULD_GLOBR_DONE_M |\ 1247 GLNVM_ULD_POR_DONE_M |\ 1248 GLNVM_ULD_POR_DONE_1_M |\ 1249 GLNVM_ULD_PCIER_DONE_2_M) 1250 1251 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1252 GLNVM_ULD_PE_DONE_M : 0); 1253 1254 /* Device is Active; check Global Reset processes are done */ 1255 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1256 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1257 if (reg == uld_mask) { 1258 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1259 break; 1260 } 1261 mdelay(10); 1262 } 1263 1264 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1265 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1266 reg); 1267 return -EIO; 1268 } 1269 1270 return 0; 1271 } 1272 1273 /** 1274 * ice_pf_reset - Reset the PF 1275 * @hw: pointer to the hardware structure 1276 * 1277 * If a global reset has been triggered, this function checks 1278 * for its completion and then issues the PF reset 1279 */ 1280 static int ice_pf_reset(struct ice_hw *hw) 1281 { 1282 u32 cnt, reg; 1283 1284 /* If at function entry a global reset was already in progress, i.e. 1285 * state is not 'device active' or any of the reset done bits are not 1286 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1287 * global reset is done. 1288 */ 1289 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1290 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1291 /* poll on global reset currently in progress until done */ 1292 if (ice_check_reset(hw)) 1293 return -EIO; 1294 1295 return 0; 1296 } 1297 1298 /* Reset the PF */ 1299 reg = rd32(hw, PFGEN_CTRL); 1300 1301 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1302 1303 /* Wait for the PFR to complete. The wait time is the global config lock 1304 * timeout plus the PFR timeout which will account for a possible reset 1305 * that is occurring during a download package operation. 1306 */ 1307 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1308 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1309 reg = rd32(hw, PFGEN_CTRL); 1310 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1311 break; 1312 1313 mdelay(1); 1314 } 1315 1316 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1317 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1318 return -EIO; 1319 } 1320 1321 return 0; 1322 } 1323 1324 /** 1325 * ice_reset - Perform different types of reset 1326 * @hw: pointer to the hardware structure 1327 * @req: reset request 1328 * 1329 * This function triggers a reset as specified by the req parameter. 1330 * 1331 * Note: 1332 * If anything other than a PF reset is triggered, PXE mode is restored. 1333 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1334 * interface has been restored in the rebuild flow. 1335 */ 1336 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1337 { 1338 u32 val = 0; 1339 1340 switch (req) { 1341 case ICE_RESET_PFR: 1342 return ice_pf_reset(hw); 1343 case ICE_RESET_CORER: 1344 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1345 val = GLGEN_RTRIG_CORER_M; 1346 break; 1347 case ICE_RESET_GLOBR: 1348 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1349 val = GLGEN_RTRIG_GLOBR_M; 1350 break; 1351 default: 1352 return -EINVAL; 1353 } 1354 1355 val |= rd32(hw, GLGEN_RTRIG); 1356 wr32(hw, GLGEN_RTRIG, val); 1357 ice_flush(hw); 1358 1359 /* wait for the FW to be ready */ 1360 return ice_check_reset(hw); 1361 } 1362 1363 /** 1364 * ice_copy_rxq_ctx_to_hw 1365 * @hw: pointer to the hardware structure 1366 * @ice_rxq_ctx: pointer to the rxq context 1367 * @rxq_index: the index of the Rx queue 1368 * 1369 * Copies rxq context from dense structure to HW register space 1370 */ 1371 static int 1372 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1373 { 1374 u8 i; 1375 1376 if (!ice_rxq_ctx) 1377 return -EINVAL; 1378 1379 if (rxq_index > QRX_CTRL_MAX_INDEX) 1380 return -EINVAL; 1381 1382 /* Copy each dword separately to HW */ 1383 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1384 wr32(hw, QRX_CONTEXT(i, rxq_index), 1385 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1386 1387 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1388 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1389 } 1390 1391 return 0; 1392 } 1393 1394 /* LAN Rx Queue Context */ 1395 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1396 /* Field Width LSB */ 1397 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1398 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1399 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1400 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1401 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1402 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1403 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1404 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1405 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1406 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1407 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1408 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1409 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1410 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1411 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1412 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1413 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1414 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1415 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1416 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1417 { 0 } 1418 }; 1419 1420 /** 1421 * ice_write_rxq_ctx 1422 * @hw: pointer to the hardware structure 1423 * @rlan_ctx: pointer to the rxq context 1424 * @rxq_index: the index of the Rx queue 1425 * 1426 * Converts rxq context from sparse to dense structure and then writes 1427 * it to HW register space and enables the hardware to prefetch descriptors 1428 * instead of only fetching them on demand 1429 */ 1430 int 1431 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1432 u32 rxq_index) 1433 { 1434 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1435 1436 if (!rlan_ctx) 1437 return -EINVAL; 1438 1439 rlan_ctx->prefena = 1; 1440 1441 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1442 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1443 } 1444 1445 /* LAN Tx Queue Context */ 1446 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1447 /* Field Width LSB */ 1448 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1449 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1450 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1451 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1452 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1453 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1454 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1455 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1456 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1457 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1458 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1459 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1460 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1461 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1462 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1463 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1464 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1465 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1466 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1467 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1468 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1469 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1470 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1471 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1472 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1473 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1474 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1475 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1476 { 0 } 1477 }; 1478 1479 /* Sideband Queue command wrappers */ 1480 1481 /** 1482 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1483 * @hw: pointer to the HW struct 1484 * @desc: descriptor describing the command 1485 * @buf: buffer to use for indirect commands (NULL for direct commands) 1486 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1487 * @cd: pointer to command details structure 1488 */ 1489 static int 1490 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1491 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1492 { 1493 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1494 (struct ice_aq_desc *)desc, buf, buf_size, cd); 1495 } 1496 1497 /** 1498 * ice_sbq_rw_reg - Fill Sideband Queue command 1499 * @hw: pointer to the HW struct 1500 * @in: message info to be filled in descriptor 1501 */ 1502 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in) 1503 { 1504 struct ice_sbq_cmd_desc desc = {0}; 1505 struct ice_sbq_msg_req msg = {0}; 1506 u16 msg_len; 1507 int status; 1508 1509 msg_len = sizeof(msg); 1510 1511 msg.dest_dev = in->dest_dev; 1512 msg.opcode = in->opcode; 1513 msg.flags = ICE_SBQ_MSG_FLAGS; 1514 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1515 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1516 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1517 1518 if (in->opcode) 1519 msg.data = cpu_to_le32(in->data); 1520 else 1521 /* data read comes back in completion, so shorten the struct by 1522 * sizeof(msg.data) 1523 */ 1524 msg_len -= sizeof(msg.data); 1525 1526 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 1527 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1528 desc.param0.cmd_len = cpu_to_le16(msg_len); 1529 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1530 if (!status && !in->opcode) 1531 in->data = le32_to_cpu 1532 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1533 return status; 1534 } 1535 1536 /* FW Admin Queue command wrappers */ 1537 1538 /* Software lock/mutex that is meant to be held while the Global Config Lock 1539 * in firmware is acquired by the software to prevent most (but not all) types 1540 * of AQ commands from being sent to FW 1541 */ 1542 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1543 1544 /** 1545 * ice_should_retry_sq_send_cmd 1546 * @opcode: AQ opcode 1547 * 1548 * Decide if we should retry the send command routine for the ATQ, depending 1549 * on the opcode. 1550 */ 1551 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1552 { 1553 switch (opcode) { 1554 case ice_aqc_opc_get_link_topo: 1555 case ice_aqc_opc_lldp_stop: 1556 case ice_aqc_opc_lldp_start: 1557 case ice_aqc_opc_lldp_filter_ctrl: 1558 return true; 1559 } 1560 1561 return false; 1562 } 1563 1564 /** 1565 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1566 * @hw: pointer to the HW struct 1567 * @cq: pointer to the specific Control queue 1568 * @desc: prefilled descriptor describing the command 1569 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1570 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1571 * @cd: pointer to command details structure 1572 * 1573 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1574 * Queue if the EBUSY AQ error is returned. 1575 */ 1576 static int 1577 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1578 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1579 struct ice_sq_cd *cd) 1580 { 1581 struct ice_aq_desc desc_cpy; 1582 bool is_cmd_for_retry; 1583 u8 *buf_cpy = NULL; 1584 u8 idx = 0; 1585 u16 opcode; 1586 int status; 1587 1588 opcode = le16_to_cpu(desc->opcode); 1589 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1590 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1591 1592 if (is_cmd_for_retry) { 1593 if (buf) { 1594 buf_cpy = kzalloc(buf_size, GFP_KERNEL); 1595 if (!buf_cpy) 1596 return -ENOMEM; 1597 } 1598 1599 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1600 } 1601 1602 do { 1603 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1604 1605 if (!is_cmd_for_retry || !status || 1606 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1607 break; 1608 1609 if (buf_cpy) 1610 memcpy(buf, buf_cpy, buf_size); 1611 1612 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1613 1614 mdelay(ICE_SQ_SEND_DELAY_TIME_MS); 1615 1616 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1617 1618 kfree(buf_cpy); 1619 1620 return status; 1621 } 1622 1623 /** 1624 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1625 * @hw: pointer to the HW struct 1626 * @desc: descriptor describing the command 1627 * @buf: buffer to use for indirect commands (NULL for direct commands) 1628 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1629 * @cd: pointer to command details structure 1630 * 1631 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1632 */ 1633 int 1634 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1635 u16 buf_size, struct ice_sq_cd *cd) 1636 { 1637 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1638 bool lock_acquired = false; 1639 int status; 1640 1641 /* When a package download is in process (i.e. when the firmware's 1642 * Global Configuration Lock resource is held), only the Download 1643 * Package, Get Version, Get Package Info List, Upload Section, 1644 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1645 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1646 * Recipes to Profile Association, and Release Resource (with resource 1647 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1648 * must block until the package download completes and the Global Config 1649 * Lock is released. See also ice_acquire_global_cfg_lock(). 1650 */ 1651 switch (le16_to_cpu(desc->opcode)) { 1652 case ice_aqc_opc_download_pkg: 1653 case ice_aqc_opc_get_pkg_info_list: 1654 case ice_aqc_opc_get_ver: 1655 case ice_aqc_opc_upload_section: 1656 case ice_aqc_opc_update_pkg: 1657 case ice_aqc_opc_set_port_params: 1658 case ice_aqc_opc_get_vlan_mode_parameters: 1659 case ice_aqc_opc_set_vlan_mode_parameters: 1660 case ice_aqc_opc_add_recipe: 1661 case ice_aqc_opc_recipe_to_profile: 1662 case ice_aqc_opc_get_recipe: 1663 case ice_aqc_opc_get_recipe_to_profile: 1664 break; 1665 case ice_aqc_opc_release_res: 1666 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1667 break; 1668 fallthrough; 1669 default: 1670 mutex_lock(&ice_global_cfg_lock_sw); 1671 lock_acquired = true; 1672 break; 1673 } 1674 1675 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1676 if (lock_acquired) 1677 mutex_unlock(&ice_global_cfg_lock_sw); 1678 1679 return status; 1680 } 1681 1682 /** 1683 * ice_aq_get_fw_ver 1684 * @hw: pointer to the HW struct 1685 * @cd: pointer to command details structure or NULL 1686 * 1687 * Get the firmware version (0x0001) from the admin queue commands 1688 */ 1689 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1690 { 1691 struct ice_aqc_get_ver *resp; 1692 struct ice_aq_desc desc; 1693 int status; 1694 1695 resp = &desc.params.get_ver; 1696 1697 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1698 1699 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1700 1701 if (!status) { 1702 hw->fw_branch = resp->fw_branch; 1703 hw->fw_maj_ver = resp->fw_major; 1704 hw->fw_min_ver = resp->fw_minor; 1705 hw->fw_patch = resp->fw_patch; 1706 hw->fw_build = le32_to_cpu(resp->fw_build); 1707 hw->api_branch = resp->api_branch; 1708 hw->api_maj_ver = resp->api_major; 1709 hw->api_min_ver = resp->api_minor; 1710 hw->api_patch = resp->api_patch; 1711 } 1712 1713 return status; 1714 } 1715 1716 /** 1717 * ice_aq_send_driver_ver 1718 * @hw: pointer to the HW struct 1719 * @dv: driver's major, minor version 1720 * @cd: pointer to command details structure or NULL 1721 * 1722 * Send the driver version (0x0002) to the firmware 1723 */ 1724 int 1725 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1726 struct ice_sq_cd *cd) 1727 { 1728 struct ice_aqc_driver_ver *cmd; 1729 struct ice_aq_desc desc; 1730 u16 len; 1731 1732 cmd = &desc.params.driver_ver; 1733 1734 if (!dv) 1735 return -EINVAL; 1736 1737 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1738 1739 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1740 cmd->major_ver = dv->major_ver; 1741 cmd->minor_ver = dv->minor_ver; 1742 cmd->build_ver = dv->build_ver; 1743 cmd->subbuild_ver = dv->subbuild_ver; 1744 1745 len = 0; 1746 while (len < sizeof(dv->driver_string) && 1747 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1748 len++; 1749 1750 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1751 } 1752 1753 /** 1754 * ice_aq_q_shutdown 1755 * @hw: pointer to the HW struct 1756 * @unloading: is the driver unloading itself 1757 * 1758 * Tell the Firmware that we're shutting down the AdminQ and whether 1759 * or not the driver is unloading as well (0x0003). 1760 */ 1761 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1762 { 1763 struct ice_aqc_q_shutdown *cmd; 1764 struct ice_aq_desc desc; 1765 1766 cmd = &desc.params.q_shutdown; 1767 1768 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1769 1770 if (unloading) 1771 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1772 1773 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1774 } 1775 1776 /** 1777 * ice_aq_req_res 1778 * @hw: pointer to the HW struct 1779 * @res: resource ID 1780 * @access: access type 1781 * @sdp_number: resource number 1782 * @timeout: the maximum time in ms that the driver may hold the resource 1783 * @cd: pointer to command details structure or NULL 1784 * 1785 * Requests common resource using the admin queue commands (0x0008). 1786 * When attempting to acquire the Global Config Lock, the driver can 1787 * learn of three states: 1788 * 1) 0 - acquired lock, and can perform download package 1789 * 2) -EIO - did not get lock, driver should fail to load 1790 * 3) -EALREADY - did not get lock, but another driver has 1791 * successfully downloaded the package; the driver does 1792 * not have to download the package and can continue 1793 * loading 1794 * 1795 * Note that if the caller is in an acquire lock, perform action, release lock 1796 * phase of operation, it is possible that the FW may detect a timeout and issue 1797 * a CORER. In this case, the driver will receive a CORER interrupt and will 1798 * have to determine its cause. The calling thread that is handling this flow 1799 * will likely get an error propagated back to it indicating the Download 1800 * Package, Update Package or the Release Resource AQ commands timed out. 1801 */ 1802 static int 1803 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1804 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1805 struct ice_sq_cd *cd) 1806 { 1807 struct ice_aqc_req_res *cmd_resp; 1808 struct ice_aq_desc desc; 1809 int status; 1810 1811 cmd_resp = &desc.params.res_owner; 1812 1813 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1814 1815 cmd_resp->res_id = cpu_to_le16(res); 1816 cmd_resp->access_type = cpu_to_le16(access); 1817 cmd_resp->res_number = cpu_to_le32(sdp_number); 1818 cmd_resp->timeout = cpu_to_le32(*timeout); 1819 *timeout = 0; 1820 1821 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1822 1823 /* The completion specifies the maximum time in ms that the driver 1824 * may hold the resource in the Timeout field. 1825 */ 1826 1827 /* Global config lock response utilizes an additional status field. 1828 * 1829 * If the Global config lock resource is held by some other driver, the 1830 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1831 * and the timeout field indicates the maximum time the current owner 1832 * of the resource has to free it. 1833 */ 1834 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1835 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1836 *timeout = le32_to_cpu(cmd_resp->timeout); 1837 return 0; 1838 } else if (le16_to_cpu(cmd_resp->status) == 1839 ICE_AQ_RES_GLBL_IN_PROG) { 1840 *timeout = le32_to_cpu(cmd_resp->timeout); 1841 return -EIO; 1842 } else if (le16_to_cpu(cmd_resp->status) == 1843 ICE_AQ_RES_GLBL_DONE) { 1844 return -EALREADY; 1845 } 1846 1847 /* invalid FW response, force a timeout immediately */ 1848 *timeout = 0; 1849 return -EIO; 1850 } 1851 1852 /* If the resource is held by some other driver, the command completes 1853 * with a busy return value and the timeout field indicates the maximum 1854 * time the current owner of the resource has to free it. 1855 */ 1856 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1857 *timeout = le32_to_cpu(cmd_resp->timeout); 1858 1859 return status; 1860 } 1861 1862 /** 1863 * ice_aq_release_res 1864 * @hw: pointer to the HW struct 1865 * @res: resource ID 1866 * @sdp_number: resource number 1867 * @cd: pointer to command details structure or NULL 1868 * 1869 * release common resource using the admin queue commands (0x0009) 1870 */ 1871 static int 1872 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1873 struct ice_sq_cd *cd) 1874 { 1875 struct ice_aqc_req_res *cmd; 1876 struct ice_aq_desc desc; 1877 1878 cmd = &desc.params.res_owner; 1879 1880 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1881 1882 cmd->res_id = cpu_to_le16(res); 1883 cmd->res_number = cpu_to_le32(sdp_number); 1884 1885 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1886 } 1887 1888 /** 1889 * ice_acquire_res 1890 * @hw: pointer to the HW structure 1891 * @res: resource ID 1892 * @access: access type (read or write) 1893 * @timeout: timeout in milliseconds 1894 * 1895 * This function will attempt to acquire the ownership of a resource. 1896 */ 1897 int 1898 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1899 enum ice_aq_res_access_type access, u32 timeout) 1900 { 1901 #define ICE_RES_POLLING_DELAY_MS 10 1902 u32 delay = ICE_RES_POLLING_DELAY_MS; 1903 u32 time_left = timeout; 1904 int status; 1905 1906 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1907 1908 /* A return code of -EALREADY means that another driver has 1909 * previously acquired the resource and performed any necessary updates; 1910 * in this case the caller does not obtain the resource and has no 1911 * further work to do. 1912 */ 1913 if (status == -EALREADY) 1914 goto ice_acquire_res_exit; 1915 1916 if (status) 1917 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1918 1919 /* If necessary, poll until the current lock owner timeouts */ 1920 timeout = time_left; 1921 while (status && timeout && time_left) { 1922 mdelay(delay); 1923 timeout = (timeout > delay) ? timeout - delay : 0; 1924 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1925 1926 if (status == -EALREADY) 1927 /* lock free, but no work to do */ 1928 break; 1929 1930 if (!status) 1931 /* lock acquired */ 1932 break; 1933 } 1934 if (status && status != -EALREADY) 1935 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1936 1937 ice_acquire_res_exit: 1938 if (status == -EALREADY) { 1939 if (access == ICE_RES_WRITE) 1940 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1941 else 1942 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 1943 } 1944 return status; 1945 } 1946 1947 /** 1948 * ice_release_res 1949 * @hw: pointer to the HW structure 1950 * @res: resource ID 1951 * 1952 * This function will release a resource using the proper Admin Command. 1953 */ 1954 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1955 { 1956 u32 total_delay = 0; 1957 int status; 1958 1959 status = ice_aq_release_res(hw, res, 0, NULL); 1960 1961 /* there are some rare cases when trying to release the resource 1962 * results in an admin queue timeout, so handle them correctly 1963 */ 1964 while ((status == -EIO) && (total_delay < hw->adminq.sq_cmd_timeout)) { 1965 mdelay(1); 1966 status = ice_aq_release_res(hw, res, 0, NULL); 1967 total_delay++; 1968 } 1969 } 1970 1971 /** 1972 * ice_aq_alloc_free_res - command to allocate/free resources 1973 * @hw: pointer to the HW struct 1974 * @num_entries: number of resource entries in buffer 1975 * @buf: Indirect buffer to hold data parameters and response 1976 * @buf_size: size of buffer for indirect commands 1977 * @opc: pass in the command opcode 1978 * @cd: pointer to command details structure or NULL 1979 * 1980 * Helper function to allocate/free resources using the admin queue commands 1981 */ 1982 int 1983 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1984 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1985 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1986 { 1987 struct ice_aqc_alloc_free_res_cmd *cmd; 1988 struct ice_aq_desc desc; 1989 1990 cmd = &desc.params.sw_res_ctrl; 1991 1992 if (!buf) 1993 return -EINVAL; 1994 1995 if (buf_size < flex_array_size(buf, elem, num_entries)) 1996 return -EINVAL; 1997 1998 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1999 2000 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2001 2002 cmd->num_entries = cpu_to_le16(num_entries); 2003 2004 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2005 } 2006 2007 /** 2008 * ice_alloc_hw_res - allocate resource 2009 * @hw: pointer to the HW struct 2010 * @type: type of resource 2011 * @num: number of resources to allocate 2012 * @btm: allocate from bottom 2013 * @res: pointer to array that will receive the resources 2014 */ 2015 int 2016 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2017 { 2018 struct ice_aqc_alloc_free_res_elem *buf; 2019 u16 buf_len; 2020 int status; 2021 2022 buf_len = struct_size(buf, elem, num); 2023 buf = kzalloc(buf_len, GFP_KERNEL); 2024 if (!buf) 2025 return -ENOMEM; 2026 2027 /* Prepare buffer to allocate resource. */ 2028 buf->num_elems = cpu_to_le16(num); 2029 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2030 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2031 if (btm) 2032 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2033 2034 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 2035 ice_aqc_opc_alloc_res, NULL); 2036 if (status) 2037 goto ice_alloc_res_exit; 2038 2039 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2040 2041 ice_alloc_res_exit: 2042 kfree(buf); 2043 return status; 2044 } 2045 2046 /** 2047 * ice_free_hw_res - free allocated HW resource 2048 * @hw: pointer to the HW struct 2049 * @type: type of resource to free 2050 * @num: number of resources 2051 * @res: pointer to array that contains the resources to free 2052 */ 2053 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2054 { 2055 struct ice_aqc_alloc_free_res_elem *buf; 2056 u16 buf_len; 2057 int status; 2058 2059 buf_len = struct_size(buf, elem, num); 2060 buf = kzalloc(buf_len, GFP_KERNEL); 2061 if (!buf) 2062 return -ENOMEM; 2063 2064 /* Prepare buffer to free resource. */ 2065 buf->num_elems = cpu_to_le16(num); 2066 buf->res_type = cpu_to_le16(type); 2067 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2068 2069 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 2070 ice_aqc_opc_free_res, NULL); 2071 if (status) 2072 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2073 2074 kfree(buf); 2075 return status; 2076 } 2077 2078 /** 2079 * ice_get_num_per_func - determine number of resources per PF 2080 * @hw: pointer to the HW structure 2081 * @max: value to be evenly split between each PF 2082 * 2083 * Determine the number of valid functions by going through the bitmap returned 2084 * from parsing capabilities and use this to calculate the number of resources 2085 * per PF based on the max value passed in. 2086 */ 2087 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2088 { 2089 u8 funcs; 2090 2091 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2092 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2093 ICE_CAPS_VALID_FUNCS_M); 2094 2095 if (!funcs) 2096 return 0; 2097 2098 return max / funcs; 2099 } 2100 2101 /** 2102 * ice_parse_common_caps - parse common device/function capabilities 2103 * @hw: pointer to the HW struct 2104 * @caps: pointer to common capabilities structure 2105 * @elem: the capability element to parse 2106 * @prefix: message prefix for tracing capabilities 2107 * 2108 * Given a capability element, extract relevant details into the common 2109 * capability structure. 2110 * 2111 * Returns: true if the capability matches one of the common capability ids, 2112 * false otherwise. 2113 */ 2114 static bool 2115 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2116 struct ice_aqc_list_caps_elem *elem, const char *prefix) 2117 { 2118 u32 logical_id = le32_to_cpu(elem->logical_id); 2119 u32 phys_id = le32_to_cpu(elem->phys_id); 2120 u32 number = le32_to_cpu(elem->number); 2121 u16 cap = le16_to_cpu(elem->cap); 2122 bool found = true; 2123 2124 switch (cap) { 2125 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2126 caps->valid_functions = number; 2127 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2128 caps->valid_functions); 2129 break; 2130 case ICE_AQC_CAPS_SRIOV: 2131 caps->sr_iov_1_1 = (number == 1); 2132 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2133 caps->sr_iov_1_1); 2134 break; 2135 case ICE_AQC_CAPS_DCB: 2136 caps->dcb = (number == 1); 2137 caps->active_tc_bitmap = logical_id; 2138 caps->maxtc = phys_id; 2139 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2140 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2141 caps->active_tc_bitmap); 2142 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2143 break; 2144 case ICE_AQC_CAPS_RSS: 2145 caps->rss_table_size = number; 2146 caps->rss_table_entry_width = logical_id; 2147 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2148 caps->rss_table_size); 2149 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2150 caps->rss_table_entry_width); 2151 break; 2152 case ICE_AQC_CAPS_RXQS: 2153 caps->num_rxq = number; 2154 caps->rxq_first_id = phys_id; 2155 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2156 caps->num_rxq); 2157 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2158 caps->rxq_first_id); 2159 break; 2160 case ICE_AQC_CAPS_TXQS: 2161 caps->num_txq = number; 2162 caps->txq_first_id = phys_id; 2163 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2164 caps->num_txq); 2165 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2166 caps->txq_first_id); 2167 break; 2168 case ICE_AQC_CAPS_MSIX: 2169 caps->num_msix_vectors = number; 2170 caps->msix_vector_first_id = phys_id; 2171 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2172 caps->num_msix_vectors); 2173 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2174 caps->msix_vector_first_id); 2175 break; 2176 case ICE_AQC_CAPS_PENDING_NVM_VER: 2177 caps->nvm_update_pending_nvm = true; 2178 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2179 break; 2180 case ICE_AQC_CAPS_PENDING_OROM_VER: 2181 caps->nvm_update_pending_orom = true; 2182 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2183 break; 2184 case ICE_AQC_CAPS_PENDING_NET_VER: 2185 caps->nvm_update_pending_netlist = true; 2186 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2187 break; 2188 case ICE_AQC_CAPS_NVM_MGMT: 2189 caps->nvm_unified_update = 2190 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2191 true : false; 2192 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2193 caps->nvm_unified_update); 2194 break; 2195 case ICE_AQC_CAPS_RDMA: 2196 caps->rdma = (number == 1); 2197 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2198 break; 2199 case ICE_AQC_CAPS_MAX_MTU: 2200 caps->max_mtu = number; 2201 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2202 prefix, caps->max_mtu); 2203 break; 2204 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2205 caps->pcie_reset_avoidance = (number > 0); 2206 ice_debug(hw, ICE_DBG_INIT, 2207 "%s: pcie_reset_avoidance = %d\n", prefix, 2208 caps->pcie_reset_avoidance); 2209 break; 2210 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2211 caps->reset_restrict_support = (number == 1); 2212 ice_debug(hw, ICE_DBG_INIT, 2213 "%s: reset_restrict_support = %d\n", prefix, 2214 caps->reset_restrict_support); 2215 break; 2216 default: 2217 /* Not one of the recognized common capabilities */ 2218 found = false; 2219 } 2220 2221 return found; 2222 } 2223 2224 /** 2225 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2226 * @hw: pointer to the HW structure 2227 * @caps: pointer to capabilities structure to fix 2228 * 2229 * Re-calculate the capabilities that are dependent on the number of physical 2230 * ports; i.e. some features are not supported or function differently on 2231 * devices with more than 4 ports. 2232 */ 2233 static void 2234 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2235 { 2236 /* This assumes device capabilities are always scanned before function 2237 * capabilities during the initialization flow. 2238 */ 2239 if (hw->dev_caps.num_funcs > 4) { 2240 /* Max 4 TCs per port */ 2241 caps->maxtc = 4; 2242 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2243 caps->maxtc); 2244 if (caps->rdma) { 2245 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2246 caps->rdma = 0; 2247 } 2248 2249 /* print message only when processing device capabilities 2250 * during initialization. 2251 */ 2252 if (caps == &hw->dev_caps.common_cap) 2253 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2254 } 2255 } 2256 2257 /** 2258 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2259 * @hw: pointer to the HW struct 2260 * @func_p: pointer to function capabilities structure 2261 * @cap: pointer to the capability element to parse 2262 * 2263 * Extract function capabilities for ICE_AQC_CAPS_VF. 2264 */ 2265 static void 2266 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2267 struct ice_aqc_list_caps_elem *cap) 2268 { 2269 u32 logical_id = le32_to_cpu(cap->logical_id); 2270 u32 number = le32_to_cpu(cap->number); 2271 2272 func_p->num_allocd_vfs = number; 2273 func_p->vf_base_id = logical_id; 2274 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2275 func_p->num_allocd_vfs); 2276 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2277 func_p->vf_base_id); 2278 } 2279 2280 /** 2281 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2282 * @hw: pointer to the HW struct 2283 * @func_p: pointer to function capabilities structure 2284 * @cap: pointer to the capability element to parse 2285 * 2286 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2287 */ 2288 static void 2289 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2290 struct ice_aqc_list_caps_elem *cap) 2291 { 2292 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2293 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2294 le32_to_cpu(cap->number)); 2295 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2296 func_p->guar_num_vsi); 2297 } 2298 2299 /** 2300 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2301 * @hw: pointer to the HW struct 2302 * @func_p: pointer to function capabilities structure 2303 * @cap: pointer to the capability element to parse 2304 * 2305 * Extract function capabilities for ICE_AQC_CAPS_1588. 2306 */ 2307 static void 2308 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2309 struct ice_aqc_list_caps_elem *cap) 2310 { 2311 struct ice_ts_func_info *info = &func_p->ts_func_info; 2312 u32 number = le32_to_cpu(cap->number); 2313 2314 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2315 func_p->common_cap.ieee_1588 = info->ena; 2316 2317 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2318 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2319 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2320 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2321 2322 info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S; 2323 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2324 2325 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { 2326 info->time_ref = (enum ice_time_ref_freq)info->clk_freq; 2327 } else { 2328 /* Unknown clock frequency, so assume a (probably incorrect) 2329 * default to avoid out-of-bounds look ups of frequency 2330 * related information. 2331 */ 2332 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2333 info->clk_freq); 2334 info->time_ref = ICE_TIME_REF_FREQ_25_000; 2335 } 2336 2337 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2338 func_p->common_cap.ieee_1588); 2339 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2340 info->src_tmr_owned); 2341 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2342 info->tmr_ena); 2343 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2344 info->tmr_index_owned); 2345 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2346 info->tmr_index_assoc); 2347 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2348 info->clk_freq); 2349 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2350 info->clk_src); 2351 } 2352 2353 /** 2354 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2355 * @hw: pointer to the HW struct 2356 * @func_p: pointer to function capabilities structure 2357 * 2358 * Extract function capabilities for ICE_AQC_CAPS_FD. 2359 */ 2360 static void 2361 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2362 { 2363 u32 reg_val, val; 2364 2365 reg_val = rd32(hw, GLQF_FD_SIZE); 2366 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2367 GLQF_FD_SIZE_FD_GSIZE_S; 2368 func_p->fd_fltr_guar = 2369 ice_get_num_per_func(hw, val); 2370 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2371 GLQF_FD_SIZE_FD_BSIZE_S; 2372 func_p->fd_fltr_best_effort = val; 2373 2374 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2375 func_p->fd_fltr_guar); 2376 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2377 func_p->fd_fltr_best_effort); 2378 } 2379 2380 /** 2381 * ice_parse_func_caps - Parse function capabilities 2382 * @hw: pointer to the HW struct 2383 * @func_p: pointer to function capabilities structure 2384 * @buf: buffer containing the function capability records 2385 * @cap_count: the number of capabilities 2386 * 2387 * Helper function to parse function (0x000A) capabilities list. For 2388 * capabilities shared between device and function, this relies on 2389 * ice_parse_common_caps. 2390 * 2391 * Loop through the list of provided capabilities and extract the relevant 2392 * data into the function capabilities structured. 2393 */ 2394 static void 2395 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2396 void *buf, u32 cap_count) 2397 { 2398 struct ice_aqc_list_caps_elem *cap_resp; 2399 u32 i; 2400 2401 cap_resp = buf; 2402 2403 memset(func_p, 0, sizeof(*func_p)); 2404 2405 for (i = 0; i < cap_count; i++) { 2406 u16 cap = le16_to_cpu(cap_resp[i].cap); 2407 bool found; 2408 2409 found = ice_parse_common_caps(hw, &func_p->common_cap, 2410 &cap_resp[i], "func caps"); 2411 2412 switch (cap) { 2413 case ICE_AQC_CAPS_VF: 2414 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2415 break; 2416 case ICE_AQC_CAPS_VSI: 2417 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2418 break; 2419 case ICE_AQC_CAPS_1588: 2420 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2421 break; 2422 case ICE_AQC_CAPS_FD: 2423 ice_parse_fdir_func_caps(hw, func_p); 2424 break; 2425 default: 2426 /* Don't list common capabilities as unknown */ 2427 if (!found) 2428 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2429 i, cap); 2430 break; 2431 } 2432 } 2433 2434 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2435 } 2436 2437 /** 2438 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2439 * @hw: pointer to the HW struct 2440 * @dev_p: pointer to device capabilities structure 2441 * @cap: capability element to parse 2442 * 2443 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2444 */ 2445 static void 2446 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2447 struct ice_aqc_list_caps_elem *cap) 2448 { 2449 u32 number = le32_to_cpu(cap->number); 2450 2451 dev_p->num_funcs = hweight32(number); 2452 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2453 dev_p->num_funcs); 2454 } 2455 2456 /** 2457 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2458 * @hw: pointer to the HW struct 2459 * @dev_p: pointer to device capabilities structure 2460 * @cap: capability element to parse 2461 * 2462 * Parse ICE_AQC_CAPS_VF for device capabilities. 2463 */ 2464 static void 2465 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2466 struct ice_aqc_list_caps_elem *cap) 2467 { 2468 u32 number = le32_to_cpu(cap->number); 2469 2470 dev_p->num_vfs_exposed = number; 2471 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2472 dev_p->num_vfs_exposed); 2473 } 2474 2475 /** 2476 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2477 * @hw: pointer to the HW struct 2478 * @dev_p: pointer to device capabilities structure 2479 * @cap: capability element to parse 2480 * 2481 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2482 */ 2483 static void 2484 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2485 struct ice_aqc_list_caps_elem *cap) 2486 { 2487 u32 number = le32_to_cpu(cap->number); 2488 2489 dev_p->num_vsi_allocd_to_host = number; 2490 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2491 dev_p->num_vsi_allocd_to_host); 2492 } 2493 2494 /** 2495 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2496 * @hw: pointer to the HW struct 2497 * @dev_p: pointer to device capabilities structure 2498 * @cap: capability element to parse 2499 * 2500 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2501 */ 2502 static void 2503 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2504 struct ice_aqc_list_caps_elem *cap) 2505 { 2506 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2507 u32 logical_id = le32_to_cpu(cap->logical_id); 2508 u32 phys_id = le32_to_cpu(cap->phys_id); 2509 u32 number = le32_to_cpu(cap->number); 2510 2511 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2512 dev_p->common_cap.ieee_1588 = info->ena; 2513 2514 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2515 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2516 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2517 2518 info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S; 2519 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2520 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2521 2522 info->ena_ports = logical_id; 2523 info->tmr_own_map = phys_id; 2524 2525 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2526 dev_p->common_cap.ieee_1588); 2527 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2528 info->tmr0_owner); 2529 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2530 info->tmr0_owned); 2531 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2532 info->tmr0_ena); 2533 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2534 info->tmr1_owner); 2535 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2536 info->tmr1_owned); 2537 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2538 info->tmr1_ena); 2539 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2540 info->ena_ports); 2541 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2542 info->tmr_own_map); 2543 } 2544 2545 /** 2546 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2547 * @hw: pointer to the HW struct 2548 * @dev_p: pointer to device capabilities structure 2549 * @cap: capability element to parse 2550 * 2551 * Parse ICE_AQC_CAPS_FD for device capabilities. 2552 */ 2553 static void 2554 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2555 struct ice_aqc_list_caps_elem *cap) 2556 { 2557 u32 number = le32_to_cpu(cap->number); 2558 2559 dev_p->num_flow_director_fltr = number; 2560 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2561 dev_p->num_flow_director_fltr); 2562 } 2563 2564 /** 2565 * ice_parse_dev_caps - Parse device capabilities 2566 * @hw: pointer to the HW struct 2567 * @dev_p: pointer to device capabilities structure 2568 * @buf: buffer containing the device capability records 2569 * @cap_count: the number of capabilities 2570 * 2571 * Helper device to parse device (0x000B) capabilities list. For 2572 * capabilities shared between device and function, this relies on 2573 * ice_parse_common_caps. 2574 * 2575 * Loop through the list of provided capabilities and extract the relevant 2576 * data into the device capabilities structured. 2577 */ 2578 static void 2579 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2580 void *buf, u32 cap_count) 2581 { 2582 struct ice_aqc_list_caps_elem *cap_resp; 2583 u32 i; 2584 2585 cap_resp = buf; 2586 2587 memset(dev_p, 0, sizeof(*dev_p)); 2588 2589 for (i = 0; i < cap_count; i++) { 2590 u16 cap = le16_to_cpu(cap_resp[i].cap); 2591 bool found; 2592 2593 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2594 &cap_resp[i], "dev caps"); 2595 2596 switch (cap) { 2597 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2598 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2599 break; 2600 case ICE_AQC_CAPS_VF: 2601 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2602 break; 2603 case ICE_AQC_CAPS_VSI: 2604 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2605 break; 2606 case ICE_AQC_CAPS_1588: 2607 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2608 break; 2609 case ICE_AQC_CAPS_FD: 2610 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2611 break; 2612 default: 2613 /* Don't list common capabilities as unknown */ 2614 if (!found) 2615 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2616 i, cap); 2617 break; 2618 } 2619 } 2620 2621 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2622 } 2623 2624 /** 2625 * ice_aq_list_caps - query function/device capabilities 2626 * @hw: pointer to the HW struct 2627 * @buf: a buffer to hold the capabilities 2628 * @buf_size: size of the buffer 2629 * @cap_count: if not NULL, set to the number of capabilities reported 2630 * @opc: capabilities type to discover, device or function 2631 * @cd: pointer to command details structure or NULL 2632 * 2633 * Get the function (0x000A) or device (0x000B) capabilities description from 2634 * firmware and store it in the buffer. 2635 * 2636 * If the cap_count pointer is not NULL, then it is set to the number of 2637 * capabilities firmware will report. Note that if the buffer size is too 2638 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2639 * cap_count will still be updated in this case. It is recommended that the 2640 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2641 * firmware could return) to avoid this. 2642 */ 2643 int 2644 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2645 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2646 { 2647 struct ice_aqc_list_caps *cmd; 2648 struct ice_aq_desc desc; 2649 int status; 2650 2651 cmd = &desc.params.get_cap; 2652 2653 if (opc != ice_aqc_opc_list_func_caps && 2654 opc != ice_aqc_opc_list_dev_caps) 2655 return -EINVAL; 2656 2657 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2658 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2659 2660 if (cap_count) 2661 *cap_count = le32_to_cpu(cmd->count); 2662 2663 return status; 2664 } 2665 2666 /** 2667 * ice_discover_dev_caps - Read and extract device capabilities 2668 * @hw: pointer to the hardware structure 2669 * @dev_caps: pointer to device capabilities structure 2670 * 2671 * Read the device capabilities and extract them into the dev_caps structure 2672 * for later use. 2673 */ 2674 int 2675 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2676 { 2677 u32 cap_count = 0; 2678 void *cbuf; 2679 int status; 2680 2681 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2682 if (!cbuf) 2683 return -ENOMEM; 2684 2685 /* Although the driver doesn't know the number of capabilities the 2686 * device will return, we can simply send a 4KB buffer, the maximum 2687 * possible size that firmware can return. 2688 */ 2689 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2690 2691 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2692 ice_aqc_opc_list_dev_caps, NULL); 2693 if (!status) 2694 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2695 kfree(cbuf); 2696 2697 return status; 2698 } 2699 2700 /** 2701 * ice_discover_func_caps - Read and extract function capabilities 2702 * @hw: pointer to the hardware structure 2703 * @func_caps: pointer to function capabilities structure 2704 * 2705 * Read the function capabilities and extract them into the func_caps structure 2706 * for later use. 2707 */ 2708 static int 2709 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2710 { 2711 u32 cap_count = 0; 2712 void *cbuf; 2713 int status; 2714 2715 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2716 if (!cbuf) 2717 return -ENOMEM; 2718 2719 /* Although the driver doesn't know the number of capabilities the 2720 * device will return, we can simply send a 4KB buffer, the maximum 2721 * possible size that firmware can return. 2722 */ 2723 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2724 2725 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2726 ice_aqc_opc_list_func_caps, NULL); 2727 if (!status) 2728 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2729 kfree(cbuf); 2730 2731 return status; 2732 } 2733 2734 /** 2735 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2736 * @hw: pointer to the hardware structure 2737 */ 2738 void ice_set_safe_mode_caps(struct ice_hw *hw) 2739 { 2740 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2741 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2742 struct ice_hw_common_caps cached_caps; 2743 u32 num_funcs; 2744 2745 /* cache some func_caps values that should be restored after memset */ 2746 cached_caps = func_caps->common_cap; 2747 2748 /* unset func capabilities */ 2749 memset(func_caps, 0, sizeof(*func_caps)); 2750 2751 #define ICE_RESTORE_FUNC_CAP(name) \ 2752 func_caps->common_cap.name = cached_caps.name 2753 2754 /* restore cached values */ 2755 ICE_RESTORE_FUNC_CAP(valid_functions); 2756 ICE_RESTORE_FUNC_CAP(txq_first_id); 2757 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2758 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2759 ICE_RESTORE_FUNC_CAP(max_mtu); 2760 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2761 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2762 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2763 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2764 2765 /* one Tx and one Rx queue in safe mode */ 2766 func_caps->common_cap.num_rxq = 1; 2767 func_caps->common_cap.num_txq = 1; 2768 2769 /* two MSIX vectors, one for traffic and one for misc causes */ 2770 func_caps->common_cap.num_msix_vectors = 2; 2771 func_caps->guar_num_vsi = 1; 2772 2773 /* cache some dev_caps values that should be restored after memset */ 2774 cached_caps = dev_caps->common_cap; 2775 num_funcs = dev_caps->num_funcs; 2776 2777 /* unset dev capabilities */ 2778 memset(dev_caps, 0, sizeof(*dev_caps)); 2779 2780 #define ICE_RESTORE_DEV_CAP(name) \ 2781 dev_caps->common_cap.name = cached_caps.name 2782 2783 /* restore cached values */ 2784 ICE_RESTORE_DEV_CAP(valid_functions); 2785 ICE_RESTORE_DEV_CAP(txq_first_id); 2786 ICE_RESTORE_DEV_CAP(rxq_first_id); 2787 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2788 ICE_RESTORE_DEV_CAP(max_mtu); 2789 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2790 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 2791 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 2792 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 2793 dev_caps->num_funcs = num_funcs; 2794 2795 /* one Tx and one Rx queue per function in safe mode */ 2796 dev_caps->common_cap.num_rxq = num_funcs; 2797 dev_caps->common_cap.num_txq = num_funcs; 2798 2799 /* two MSIX vectors per function */ 2800 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2801 } 2802 2803 /** 2804 * ice_get_caps - get info about the HW 2805 * @hw: pointer to the hardware structure 2806 */ 2807 int ice_get_caps(struct ice_hw *hw) 2808 { 2809 int status; 2810 2811 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2812 if (status) 2813 return status; 2814 2815 return ice_discover_func_caps(hw, &hw->func_caps); 2816 } 2817 2818 /** 2819 * ice_aq_manage_mac_write - manage MAC address write command 2820 * @hw: pointer to the HW struct 2821 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2822 * @flags: flags to control write behavior 2823 * @cd: pointer to command details structure or NULL 2824 * 2825 * This function is used to write MAC address to the NVM (0x0108). 2826 */ 2827 int 2828 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2829 struct ice_sq_cd *cd) 2830 { 2831 struct ice_aqc_manage_mac_write *cmd; 2832 struct ice_aq_desc desc; 2833 2834 cmd = &desc.params.mac_write; 2835 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2836 2837 cmd->flags = flags; 2838 ether_addr_copy(cmd->mac_addr, mac_addr); 2839 2840 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2841 } 2842 2843 /** 2844 * ice_aq_clear_pxe_mode 2845 * @hw: pointer to the HW struct 2846 * 2847 * Tell the firmware that the driver is taking over from PXE (0x0110). 2848 */ 2849 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 2850 { 2851 struct ice_aq_desc desc; 2852 2853 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2854 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2855 2856 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2857 } 2858 2859 /** 2860 * ice_clear_pxe_mode - clear pxe operations mode 2861 * @hw: pointer to the HW struct 2862 * 2863 * Make sure all PXE mode settings are cleared, including things 2864 * like descriptor fetch/write-back mode. 2865 */ 2866 void ice_clear_pxe_mode(struct ice_hw *hw) 2867 { 2868 if (ice_check_sq_alive(hw, &hw->adminq)) 2869 ice_aq_clear_pxe_mode(hw); 2870 } 2871 2872 /** 2873 * ice_aq_set_port_params - set physical port parameters. 2874 * @pi: pointer to the port info struct 2875 * @double_vlan: if set double VLAN is enabled 2876 * @cd: pointer to command details structure or NULL 2877 * 2878 * Set Physical port parameters (0x0203) 2879 */ 2880 int 2881 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 2882 struct ice_sq_cd *cd) 2883 2884 { 2885 struct ice_aqc_set_port_params *cmd; 2886 struct ice_hw *hw = pi->hw; 2887 struct ice_aq_desc desc; 2888 u16 cmd_flags = 0; 2889 2890 cmd = &desc.params.set_port_params; 2891 2892 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 2893 if (double_vlan) 2894 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 2895 cmd->cmd_flags = cpu_to_le16(cmd_flags); 2896 2897 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2898 } 2899 2900 /** 2901 * ice_is_100m_speed_supported 2902 * @hw: pointer to the HW struct 2903 * 2904 * returns true if 100M speeds are supported by the device, 2905 * false otherwise. 2906 */ 2907 bool ice_is_100m_speed_supported(struct ice_hw *hw) 2908 { 2909 switch (hw->device_id) { 2910 case ICE_DEV_ID_E822C_SGMII: 2911 case ICE_DEV_ID_E822L_SGMII: 2912 case ICE_DEV_ID_E823L_1GBE: 2913 case ICE_DEV_ID_E823C_SGMII: 2914 return true; 2915 default: 2916 return false; 2917 } 2918 } 2919 2920 /** 2921 * ice_get_link_speed_based_on_phy_type - returns link speed 2922 * @phy_type_low: lower part of phy_type 2923 * @phy_type_high: higher part of phy_type 2924 * 2925 * This helper function will convert an entry in PHY type structure 2926 * [phy_type_low, phy_type_high] to its corresponding link speed. 2927 * Note: In the structure of [phy_type_low, phy_type_high], there should 2928 * be one bit set, as this function will convert one PHY type to its 2929 * speed. 2930 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2931 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2932 */ 2933 static u16 2934 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2935 { 2936 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2937 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2938 2939 switch (phy_type_low) { 2940 case ICE_PHY_TYPE_LOW_100BASE_TX: 2941 case ICE_PHY_TYPE_LOW_100M_SGMII: 2942 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2943 break; 2944 case ICE_PHY_TYPE_LOW_1000BASE_T: 2945 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2946 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2947 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2948 case ICE_PHY_TYPE_LOW_1G_SGMII: 2949 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2950 break; 2951 case ICE_PHY_TYPE_LOW_2500BASE_T: 2952 case ICE_PHY_TYPE_LOW_2500BASE_X: 2953 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2954 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2955 break; 2956 case ICE_PHY_TYPE_LOW_5GBASE_T: 2957 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2958 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2959 break; 2960 case ICE_PHY_TYPE_LOW_10GBASE_T: 2961 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2962 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2963 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2964 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2965 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2966 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2967 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2968 break; 2969 case ICE_PHY_TYPE_LOW_25GBASE_T: 2970 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2971 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2972 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2973 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2974 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2975 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2976 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2977 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2978 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2979 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2980 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2981 break; 2982 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2983 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2984 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2985 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2986 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2987 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2988 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2989 break; 2990 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2991 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2992 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2993 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2994 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2995 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2996 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2997 case ICE_PHY_TYPE_LOW_50G_AUI2: 2998 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2999 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3000 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3001 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3002 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3003 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3004 case ICE_PHY_TYPE_LOW_50G_AUI1: 3005 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3006 break; 3007 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3008 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3009 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3010 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3011 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3012 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3013 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3014 case ICE_PHY_TYPE_LOW_100G_AUI4: 3015 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3016 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3017 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3018 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3019 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3020 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3021 break; 3022 default: 3023 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3024 break; 3025 } 3026 3027 switch (phy_type_high) { 3028 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3029 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3030 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3031 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3032 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3033 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3034 break; 3035 default: 3036 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3037 break; 3038 } 3039 3040 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3041 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3042 return ICE_AQ_LINK_SPEED_UNKNOWN; 3043 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3044 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3045 return ICE_AQ_LINK_SPEED_UNKNOWN; 3046 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3047 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3048 return speed_phy_type_low; 3049 else 3050 return speed_phy_type_high; 3051 } 3052 3053 /** 3054 * ice_update_phy_type 3055 * @phy_type_low: pointer to the lower part of phy_type 3056 * @phy_type_high: pointer to the higher part of phy_type 3057 * @link_speeds_bitmap: targeted link speeds bitmap 3058 * 3059 * Note: For the link_speeds_bitmap structure, you can check it at 3060 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3061 * link_speeds_bitmap include multiple speeds. 3062 * 3063 * Each entry in this [phy_type_low, phy_type_high] structure will 3064 * present a certain link speed. This helper function will turn on bits 3065 * in [phy_type_low, phy_type_high] structure based on the value of 3066 * link_speeds_bitmap input parameter. 3067 */ 3068 void 3069 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3070 u16 link_speeds_bitmap) 3071 { 3072 u64 pt_high; 3073 u64 pt_low; 3074 int index; 3075 u16 speed; 3076 3077 /* We first check with low part of phy_type */ 3078 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3079 pt_low = BIT_ULL(index); 3080 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3081 3082 if (link_speeds_bitmap & speed) 3083 *phy_type_low |= BIT_ULL(index); 3084 } 3085 3086 /* We then check with high part of phy_type */ 3087 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3088 pt_high = BIT_ULL(index); 3089 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3090 3091 if (link_speeds_bitmap & speed) 3092 *phy_type_high |= BIT_ULL(index); 3093 } 3094 } 3095 3096 /** 3097 * ice_aq_set_phy_cfg 3098 * @hw: pointer to the HW struct 3099 * @pi: port info structure of the interested logical port 3100 * @cfg: structure with PHY configuration data to be set 3101 * @cd: pointer to command details structure or NULL 3102 * 3103 * Set the various PHY configuration parameters supported on the Port. 3104 * One or more of the Set PHY config parameters may be ignored in an MFP 3105 * mode as the PF may not have the privilege to set some of the PHY Config 3106 * parameters. This status will be indicated by the command response (0x0601). 3107 */ 3108 int 3109 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3110 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3111 { 3112 struct ice_aq_desc desc; 3113 int status; 3114 3115 if (!cfg) 3116 return -EINVAL; 3117 3118 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3119 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3120 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3121 cfg->caps); 3122 3123 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3124 } 3125 3126 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3127 desc.params.set_phy.lport_num = pi->lport; 3128 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3129 3130 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3131 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3132 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3133 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3134 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3135 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3136 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3137 cfg->low_power_ctrl_an); 3138 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3139 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3140 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3141 cfg->link_fec_opt); 3142 3143 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3144 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3145 status = 0; 3146 3147 if (!status) 3148 pi->phy.curr_user_phy_cfg = *cfg; 3149 3150 return status; 3151 } 3152 3153 /** 3154 * ice_update_link_info - update status of the HW network link 3155 * @pi: port info structure of the interested logical port 3156 */ 3157 int ice_update_link_info(struct ice_port_info *pi) 3158 { 3159 struct ice_link_status *li; 3160 int status; 3161 3162 if (!pi) 3163 return -EINVAL; 3164 3165 li = &pi->phy.link_info; 3166 3167 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3168 if (status) 3169 return status; 3170 3171 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3172 struct ice_aqc_get_phy_caps_data *pcaps; 3173 struct ice_hw *hw; 3174 3175 hw = pi->hw; 3176 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 3177 GFP_KERNEL); 3178 if (!pcaps) 3179 return -ENOMEM; 3180 3181 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3182 pcaps, NULL); 3183 3184 devm_kfree(ice_hw_to_dev(hw), pcaps); 3185 } 3186 3187 return status; 3188 } 3189 3190 /** 3191 * ice_cache_phy_user_req 3192 * @pi: port information structure 3193 * @cache_data: PHY logging data 3194 * @cache_mode: PHY logging mode 3195 * 3196 * Log the user request on (FC, FEC, SPEED) for later use. 3197 */ 3198 static void 3199 ice_cache_phy_user_req(struct ice_port_info *pi, 3200 struct ice_phy_cache_mode_data cache_data, 3201 enum ice_phy_cache_mode cache_mode) 3202 { 3203 if (!pi) 3204 return; 3205 3206 switch (cache_mode) { 3207 case ICE_FC_MODE: 3208 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3209 break; 3210 case ICE_SPEED_MODE: 3211 pi->phy.curr_user_speed_req = 3212 cache_data.data.curr_user_speed_req; 3213 break; 3214 case ICE_FEC_MODE: 3215 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3216 break; 3217 default: 3218 break; 3219 } 3220 } 3221 3222 /** 3223 * ice_caps_to_fc_mode 3224 * @caps: PHY capabilities 3225 * 3226 * Convert PHY FC capabilities to ice FC mode 3227 */ 3228 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3229 { 3230 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3231 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3232 return ICE_FC_FULL; 3233 3234 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3235 return ICE_FC_TX_PAUSE; 3236 3237 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3238 return ICE_FC_RX_PAUSE; 3239 3240 return ICE_FC_NONE; 3241 } 3242 3243 /** 3244 * ice_caps_to_fec_mode 3245 * @caps: PHY capabilities 3246 * @fec_options: Link FEC options 3247 * 3248 * Convert PHY FEC capabilities to ice FEC mode 3249 */ 3250 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3251 { 3252 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3253 return ICE_FEC_AUTO; 3254 3255 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3256 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3257 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3258 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3259 return ICE_FEC_BASER; 3260 3261 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3262 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3263 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3264 return ICE_FEC_RS; 3265 3266 return ICE_FEC_NONE; 3267 } 3268 3269 /** 3270 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3271 * @pi: port information structure 3272 * @cfg: PHY configuration data to set FC mode 3273 * @req_mode: FC mode to configure 3274 */ 3275 int 3276 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3277 enum ice_fc_mode req_mode) 3278 { 3279 struct ice_phy_cache_mode_data cache_data; 3280 u8 pause_mask = 0x0; 3281 3282 if (!pi || !cfg) 3283 return -EINVAL; 3284 3285 switch (req_mode) { 3286 case ICE_FC_FULL: 3287 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3288 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3289 break; 3290 case ICE_FC_RX_PAUSE: 3291 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3292 break; 3293 case ICE_FC_TX_PAUSE: 3294 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3295 break; 3296 default: 3297 break; 3298 } 3299 3300 /* clear the old pause settings */ 3301 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3302 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3303 3304 /* set the new capabilities */ 3305 cfg->caps |= pause_mask; 3306 3307 /* Cache user FC request */ 3308 cache_data.data.curr_user_fc_req = req_mode; 3309 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3310 3311 return 0; 3312 } 3313 3314 /** 3315 * ice_set_fc 3316 * @pi: port information structure 3317 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3318 * @ena_auto_link_update: enable automatic link update 3319 * 3320 * Set the requested flow control mode. 3321 */ 3322 int 3323 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3324 { 3325 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3326 struct ice_aqc_get_phy_caps_data *pcaps; 3327 struct ice_hw *hw; 3328 int status; 3329 3330 if (!pi || !aq_failures) 3331 return -EINVAL; 3332 3333 *aq_failures = 0; 3334 hw = pi->hw; 3335 3336 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 3337 if (!pcaps) 3338 return -ENOMEM; 3339 3340 /* Get the current PHY config */ 3341 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3342 pcaps, NULL); 3343 if (status) { 3344 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3345 goto out; 3346 } 3347 3348 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3349 3350 /* Configure the set PHY data */ 3351 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3352 if (status) 3353 goto out; 3354 3355 /* If the capabilities have changed, then set the new config */ 3356 if (cfg.caps != pcaps->caps) { 3357 int retry_count, retry_max = 10; 3358 3359 /* Auto restart link so settings take effect */ 3360 if (ena_auto_link_update) 3361 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3362 3363 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3364 if (status) { 3365 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3366 goto out; 3367 } 3368 3369 /* Update the link info 3370 * It sometimes takes a really long time for link to 3371 * come back from the atomic reset. Thus, we wait a 3372 * little bit. 3373 */ 3374 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3375 status = ice_update_link_info(pi); 3376 3377 if (!status) 3378 break; 3379 3380 mdelay(100); 3381 } 3382 3383 if (status) 3384 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3385 } 3386 3387 out: 3388 devm_kfree(ice_hw_to_dev(hw), pcaps); 3389 return status; 3390 } 3391 3392 /** 3393 * ice_phy_caps_equals_cfg 3394 * @phy_caps: PHY capabilities 3395 * @phy_cfg: PHY configuration 3396 * 3397 * Helper function to determine if PHY capabilities matches PHY 3398 * configuration 3399 */ 3400 bool 3401 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3402 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3403 { 3404 u8 caps_mask, cfg_mask; 3405 3406 if (!phy_caps || !phy_cfg) 3407 return false; 3408 3409 /* These bits are not common between capabilities and configuration. 3410 * Do not use them to determine equality. 3411 */ 3412 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3413 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3414 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3415 3416 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3417 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3418 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3419 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3420 phy_caps->eee_cap != phy_cfg->eee_cap || 3421 phy_caps->eeer_value != phy_cfg->eeer_value || 3422 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3423 return false; 3424 3425 return true; 3426 } 3427 3428 /** 3429 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3430 * @pi: port information structure 3431 * @caps: PHY ability structure to copy date from 3432 * @cfg: PHY configuration structure to copy data to 3433 * 3434 * Helper function to copy AQC PHY get ability data to PHY set configuration 3435 * data structure 3436 */ 3437 void 3438 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3439 struct ice_aqc_get_phy_caps_data *caps, 3440 struct ice_aqc_set_phy_cfg_data *cfg) 3441 { 3442 if (!pi || !caps || !cfg) 3443 return; 3444 3445 memset(cfg, 0, sizeof(*cfg)); 3446 cfg->phy_type_low = caps->phy_type_low; 3447 cfg->phy_type_high = caps->phy_type_high; 3448 cfg->caps = caps->caps; 3449 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3450 cfg->eee_cap = caps->eee_cap; 3451 cfg->eeer_value = caps->eeer_value; 3452 cfg->link_fec_opt = caps->link_fec_options; 3453 cfg->module_compliance_enforcement = 3454 caps->module_compliance_enforcement; 3455 } 3456 3457 /** 3458 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3459 * @pi: port information structure 3460 * @cfg: PHY configuration data to set FEC mode 3461 * @fec: FEC mode to configure 3462 */ 3463 int 3464 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3465 enum ice_fec_mode fec) 3466 { 3467 struct ice_aqc_get_phy_caps_data *pcaps; 3468 struct ice_hw *hw; 3469 int status; 3470 3471 if (!pi || !cfg) 3472 return -EINVAL; 3473 3474 hw = pi->hw; 3475 3476 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3477 if (!pcaps) 3478 return -ENOMEM; 3479 3480 status = ice_aq_get_phy_caps(pi, false, 3481 (ice_fw_supports_report_dflt_cfg(hw) ? 3482 ICE_AQC_REPORT_DFLT_CFG : 3483 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3484 if (status) 3485 goto out; 3486 3487 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3488 cfg->link_fec_opt = pcaps->link_fec_options; 3489 3490 switch (fec) { 3491 case ICE_FEC_BASER: 3492 /* Clear RS bits, and AND BASE-R ability 3493 * bits and OR request bits. 3494 */ 3495 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3496 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3497 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3498 ICE_AQC_PHY_FEC_25G_KR_REQ; 3499 break; 3500 case ICE_FEC_RS: 3501 /* Clear BASE-R bits, and AND RS ability 3502 * bits and OR request bits. 3503 */ 3504 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3505 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3506 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3507 break; 3508 case ICE_FEC_NONE: 3509 /* Clear all FEC option bits. */ 3510 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3511 break; 3512 case ICE_FEC_AUTO: 3513 /* AND auto FEC bit, and all caps bits. */ 3514 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3515 cfg->link_fec_opt |= pcaps->link_fec_options; 3516 break; 3517 default: 3518 status = -EINVAL; 3519 break; 3520 } 3521 3522 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 3523 !ice_fw_supports_report_dflt_cfg(hw)) { 3524 struct ice_link_default_override_tlv tlv = { 0 }; 3525 3526 status = ice_get_link_default_override(&tlv, pi); 3527 if (status) 3528 goto out; 3529 3530 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3531 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3532 cfg->link_fec_opt = tlv.fec_options; 3533 } 3534 3535 out: 3536 kfree(pcaps); 3537 3538 return status; 3539 } 3540 3541 /** 3542 * ice_get_link_status - get status of the HW network link 3543 * @pi: port information structure 3544 * @link_up: pointer to bool (true/false = linkup/linkdown) 3545 * 3546 * Variable link_up is true if link is up, false if link is down. 3547 * The variable link_up is invalid if status is non zero. As a 3548 * result of this call, link status reporting becomes enabled 3549 */ 3550 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3551 { 3552 struct ice_phy_info *phy_info; 3553 int status = 0; 3554 3555 if (!pi || !link_up) 3556 return -EINVAL; 3557 3558 phy_info = &pi->phy; 3559 3560 if (phy_info->get_link_info) { 3561 status = ice_update_link_info(pi); 3562 3563 if (status) 3564 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3565 status); 3566 } 3567 3568 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3569 3570 return status; 3571 } 3572 3573 /** 3574 * ice_aq_set_link_restart_an 3575 * @pi: pointer to the port information structure 3576 * @ena_link: if true: enable link, if false: disable link 3577 * @cd: pointer to command details structure or NULL 3578 * 3579 * Sets up the link and restarts the Auto-Negotiation over the link. 3580 */ 3581 int 3582 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3583 struct ice_sq_cd *cd) 3584 { 3585 struct ice_aqc_restart_an *cmd; 3586 struct ice_aq_desc desc; 3587 3588 cmd = &desc.params.restart_an; 3589 3590 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3591 3592 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3593 cmd->lport_num = pi->lport; 3594 if (ena_link) 3595 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3596 else 3597 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3598 3599 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3600 } 3601 3602 /** 3603 * ice_aq_set_event_mask 3604 * @hw: pointer to the HW struct 3605 * @port_num: port number of the physical function 3606 * @mask: event mask to be set 3607 * @cd: pointer to command details structure or NULL 3608 * 3609 * Set event mask (0x0613) 3610 */ 3611 int 3612 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3613 struct ice_sq_cd *cd) 3614 { 3615 struct ice_aqc_set_event_mask *cmd; 3616 struct ice_aq_desc desc; 3617 3618 cmd = &desc.params.set_event_mask; 3619 3620 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3621 3622 cmd->lport_num = port_num; 3623 3624 cmd->event_mask = cpu_to_le16(mask); 3625 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3626 } 3627 3628 /** 3629 * ice_aq_set_mac_loopback 3630 * @hw: pointer to the HW struct 3631 * @ena_lpbk: Enable or Disable loopback 3632 * @cd: pointer to command details structure or NULL 3633 * 3634 * Enable/disable loopback on a given port 3635 */ 3636 int 3637 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3638 { 3639 struct ice_aqc_set_mac_lb *cmd; 3640 struct ice_aq_desc desc; 3641 3642 cmd = &desc.params.set_mac_lb; 3643 3644 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3645 if (ena_lpbk) 3646 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3647 3648 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3649 } 3650 3651 /** 3652 * ice_aq_set_port_id_led 3653 * @pi: pointer to the port information 3654 * @is_orig_mode: is this LED set to original mode (by the net-list) 3655 * @cd: pointer to command details structure or NULL 3656 * 3657 * Set LED value for the given port (0x06e9) 3658 */ 3659 int 3660 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3661 struct ice_sq_cd *cd) 3662 { 3663 struct ice_aqc_set_port_id_led *cmd; 3664 struct ice_hw *hw = pi->hw; 3665 struct ice_aq_desc desc; 3666 3667 cmd = &desc.params.set_port_id_led; 3668 3669 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3670 3671 if (is_orig_mode) 3672 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3673 else 3674 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3675 3676 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3677 } 3678 3679 /** 3680 * ice_aq_get_port_options 3681 * @hw: pointer to the HW struct 3682 * @options: buffer for the resultant port options 3683 * @option_count: input - size of the buffer in port options structures, 3684 * output - number of returned port options 3685 * @lport: logical port to call the command with (optional) 3686 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3687 * when PF owns more than 1 port it must be true 3688 * @active_option_idx: index of active port option in returned buffer 3689 * @active_option_valid: active option in returned buffer is valid 3690 * @pending_option_idx: index of pending port option in returned buffer 3691 * @pending_option_valid: pending option in returned buffer is valid 3692 * 3693 * Calls Get Port Options AQC (0x06ea) and verifies result. 3694 */ 3695 int 3696 ice_aq_get_port_options(struct ice_hw *hw, 3697 struct ice_aqc_get_port_options_elem *options, 3698 u8 *option_count, u8 lport, bool lport_valid, 3699 u8 *active_option_idx, bool *active_option_valid, 3700 u8 *pending_option_idx, bool *pending_option_valid) 3701 { 3702 struct ice_aqc_get_port_options *cmd; 3703 struct ice_aq_desc desc; 3704 int status; 3705 u8 i; 3706 3707 /* options buffer shall be able to hold max returned options */ 3708 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 3709 return -EINVAL; 3710 3711 cmd = &desc.params.get_port_options; 3712 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 3713 3714 if (lport_valid) 3715 cmd->lport_num = lport; 3716 cmd->lport_num_valid = lport_valid; 3717 3718 status = ice_aq_send_cmd(hw, &desc, options, 3719 *option_count * sizeof(*options), NULL); 3720 if (status) 3721 return status; 3722 3723 /* verify direct FW response & set output parameters */ 3724 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 3725 cmd->port_options_count); 3726 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 3727 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 3728 cmd->port_options); 3729 if (*active_option_valid) { 3730 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 3731 cmd->port_options); 3732 if (*active_option_idx > (*option_count - 1)) 3733 return -EIO; 3734 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 3735 *active_option_idx); 3736 } 3737 3738 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 3739 cmd->pending_port_option_status); 3740 if (*pending_option_valid) { 3741 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 3742 cmd->pending_port_option_status); 3743 if (*pending_option_idx > (*option_count - 1)) 3744 return -EIO; 3745 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 3746 *pending_option_idx); 3747 } 3748 3749 /* mask output options fields */ 3750 for (i = 0; i < *option_count; i++) { 3751 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 3752 options[i].pmd); 3753 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 3754 options[i].max_lane_speed); 3755 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 3756 options[i].pmd, options[i].max_lane_speed); 3757 } 3758 3759 return 0; 3760 } 3761 3762 /** 3763 * ice_aq_set_port_option 3764 * @hw: pointer to the HW struct 3765 * @lport: logical port to call the command with 3766 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3767 * when PF owns more than 1 port it must be true 3768 * @new_option: new port option to be written 3769 * 3770 * Calls Set Port Options AQC (0x06eb). 3771 */ 3772 int 3773 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 3774 u8 new_option) 3775 { 3776 struct ice_aqc_set_port_option *cmd; 3777 struct ice_aq_desc desc; 3778 3779 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 3780 return -EINVAL; 3781 3782 cmd = &desc.params.set_port_option; 3783 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 3784 3785 if (lport_valid) 3786 cmd->lport_num = lport; 3787 3788 cmd->lport_num_valid = lport_valid; 3789 cmd->selected_port_option = new_option; 3790 3791 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3792 } 3793 3794 /** 3795 * ice_aq_sff_eeprom 3796 * @hw: pointer to the HW struct 3797 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3798 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3799 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3800 * @page: QSFP page 3801 * @set_page: set or ignore the page 3802 * @data: pointer to data buffer to be read/written to the I2C device. 3803 * @length: 1-16 for read, 1 for write. 3804 * @write: 0 read, 1 for write. 3805 * @cd: pointer to command details structure or NULL 3806 * 3807 * Read/Write SFF EEPROM (0x06EE) 3808 */ 3809 int 3810 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3811 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3812 bool write, struct ice_sq_cd *cd) 3813 { 3814 struct ice_aqc_sff_eeprom *cmd; 3815 struct ice_aq_desc desc; 3816 int status; 3817 3818 if (!data || (mem_addr & 0xff00)) 3819 return -EINVAL; 3820 3821 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3822 cmd = &desc.params.read_write_sff_param; 3823 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 3824 cmd->lport_num = (u8)(lport & 0xff); 3825 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3826 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 3827 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3828 ((set_page << 3829 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3830 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3831 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3832 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3833 if (write) 3834 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 3835 3836 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3837 return status; 3838 } 3839 3840 /** 3841 * __ice_aq_get_set_rss_lut 3842 * @hw: pointer to the hardware structure 3843 * @params: RSS LUT parameters 3844 * @set: set true to set the table, false to get the table 3845 * 3846 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3847 */ 3848 static int 3849 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 3850 { 3851 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 3852 struct ice_aqc_get_set_rss_lut *cmd_resp; 3853 struct ice_aq_desc desc; 3854 int status; 3855 u8 *lut; 3856 3857 if (!params) 3858 return -EINVAL; 3859 3860 vsi_handle = params->vsi_handle; 3861 lut = params->lut; 3862 3863 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3864 return -EINVAL; 3865 3866 lut_size = params->lut_size; 3867 lut_type = params->lut_type; 3868 glob_lut_idx = params->global_lut_id; 3869 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 3870 3871 cmd_resp = &desc.params.get_set_rss_lut; 3872 3873 if (set) { 3874 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3875 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3876 } else { 3877 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3878 } 3879 3880 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3881 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3882 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3883 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3884 3885 switch (lut_type) { 3886 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3887 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3888 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3889 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3890 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3891 break; 3892 default: 3893 status = -EINVAL; 3894 goto ice_aq_get_set_rss_lut_exit; 3895 } 3896 3897 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3898 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3899 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3900 3901 if (!set) 3902 goto ice_aq_get_set_rss_lut_send; 3903 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3904 if (!set) 3905 goto ice_aq_get_set_rss_lut_send; 3906 } else { 3907 goto ice_aq_get_set_rss_lut_send; 3908 } 3909 3910 /* LUT size is only valid for Global and PF table types */ 3911 switch (lut_size) { 3912 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3913 break; 3914 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3915 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3916 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3917 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3918 break; 3919 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3920 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3921 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3922 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3923 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3924 break; 3925 } 3926 fallthrough; 3927 default: 3928 status = -EINVAL; 3929 goto ice_aq_get_set_rss_lut_exit; 3930 } 3931 3932 ice_aq_get_set_rss_lut_send: 3933 cmd_resp->flags = cpu_to_le16(flags); 3934 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3935 3936 ice_aq_get_set_rss_lut_exit: 3937 return status; 3938 } 3939 3940 /** 3941 * ice_aq_get_rss_lut 3942 * @hw: pointer to the hardware structure 3943 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 3944 * 3945 * get the RSS lookup table, PF or VSI type 3946 */ 3947 int 3948 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 3949 { 3950 return __ice_aq_get_set_rss_lut(hw, get_params, false); 3951 } 3952 3953 /** 3954 * ice_aq_set_rss_lut 3955 * @hw: pointer to the hardware structure 3956 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 3957 * 3958 * set the RSS lookup table, PF or VSI type 3959 */ 3960 int 3961 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 3962 { 3963 return __ice_aq_get_set_rss_lut(hw, set_params, true); 3964 } 3965 3966 /** 3967 * __ice_aq_get_set_rss_key 3968 * @hw: pointer to the HW struct 3969 * @vsi_id: VSI FW index 3970 * @key: pointer to key info struct 3971 * @set: set true to set the key, false to get the key 3972 * 3973 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3974 */ 3975 static int 3976 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3977 struct ice_aqc_get_set_rss_keys *key, bool set) 3978 { 3979 struct ice_aqc_get_set_rss_key *cmd_resp; 3980 u16 key_size = sizeof(*key); 3981 struct ice_aq_desc desc; 3982 3983 cmd_resp = &desc.params.get_set_rss_key; 3984 3985 if (set) { 3986 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3987 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3988 } else { 3989 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3990 } 3991 3992 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3993 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3994 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3995 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3996 3997 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3998 } 3999 4000 /** 4001 * ice_aq_get_rss_key 4002 * @hw: pointer to the HW struct 4003 * @vsi_handle: software VSI handle 4004 * @key: pointer to key info struct 4005 * 4006 * get the RSS key per VSI 4007 */ 4008 int 4009 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4010 struct ice_aqc_get_set_rss_keys *key) 4011 { 4012 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4013 return -EINVAL; 4014 4015 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4016 key, false); 4017 } 4018 4019 /** 4020 * ice_aq_set_rss_key 4021 * @hw: pointer to the HW struct 4022 * @vsi_handle: software VSI handle 4023 * @keys: pointer to key info struct 4024 * 4025 * set the RSS key per VSI 4026 */ 4027 int 4028 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4029 struct ice_aqc_get_set_rss_keys *keys) 4030 { 4031 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4032 return -EINVAL; 4033 4034 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4035 keys, true); 4036 } 4037 4038 /** 4039 * ice_aq_add_lan_txq 4040 * @hw: pointer to the hardware structure 4041 * @num_qgrps: Number of added queue groups 4042 * @qg_list: list of queue groups to be added 4043 * @buf_size: size of buffer for indirect command 4044 * @cd: pointer to command details structure or NULL 4045 * 4046 * Add Tx LAN queue (0x0C30) 4047 * 4048 * NOTE: 4049 * Prior to calling add Tx LAN queue: 4050 * Initialize the following as part of the Tx queue context: 4051 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4052 * Cache profile and Packet shaper profile. 4053 * 4054 * After add Tx LAN queue AQ command is completed: 4055 * Interrupts should be associated with specific queues, 4056 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4057 * flow. 4058 */ 4059 static int 4060 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4061 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4062 struct ice_sq_cd *cd) 4063 { 4064 struct ice_aqc_add_tx_qgrp *list; 4065 struct ice_aqc_add_txqs *cmd; 4066 struct ice_aq_desc desc; 4067 u16 i, sum_size = 0; 4068 4069 cmd = &desc.params.add_txqs; 4070 4071 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4072 4073 if (!qg_list) 4074 return -EINVAL; 4075 4076 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4077 return -EINVAL; 4078 4079 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4080 sum_size += struct_size(list, txqs, list->num_txqs); 4081 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4082 list->num_txqs); 4083 } 4084 4085 if (buf_size != sum_size) 4086 return -EINVAL; 4087 4088 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4089 4090 cmd->num_qgrps = num_qgrps; 4091 4092 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4093 } 4094 4095 /** 4096 * ice_aq_dis_lan_txq 4097 * @hw: pointer to the hardware structure 4098 * @num_qgrps: number of groups in the list 4099 * @qg_list: the list of groups to disable 4100 * @buf_size: the total size of the qg_list buffer in bytes 4101 * @rst_src: if called due to reset, specifies the reset source 4102 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4103 * @cd: pointer to command details structure or NULL 4104 * 4105 * Disable LAN Tx queue (0x0C31) 4106 */ 4107 static int 4108 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4109 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4110 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4111 struct ice_sq_cd *cd) 4112 { 4113 struct ice_aqc_dis_txq_item *item; 4114 struct ice_aqc_dis_txqs *cmd; 4115 struct ice_aq_desc desc; 4116 u16 i, sz = 0; 4117 int status; 4118 4119 cmd = &desc.params.dis_txqs; 4120 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4121 4122 /* qg_list can be NULL only in VM/VF reset flow */ 4123 if (!qg_list && !rst_src) 4124 return -EINVAL; 4125 4126 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4127 return -EINVAL; 4128 4129 cmd->num_entries = num_qgrps; 4130 4131 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 4132 ICE_AQC_Q_DIS_TIMEOUT_M); 4133 4134 switch (rst_src) { 4135 case ICE_VM_RESET: 4136 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4137 cmd->vmvf_and_timeout |= 4138 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 4139 break; 4140 case ICE_VF_RESET: 4141 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4142 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4143 cmd->vmvf_and_timeout |= 4144 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 4145 ICE_AQC_Q_DIS_VMVF_NUM_M); 4146 break; 4147 case ICE_NO_RESET: 4148 default: 4149 break; 4150 } 4151 4152 /* flush pipe on time out */ 4153 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4154 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4155 if (!qg_list) 4156 goto do_aq; 4157 4158 /* set RD bit to indicate that command buffer is provided by the driver 4159 * and it needs to be read by the firmware 4160 */ 4161 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4162 4163 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4164 u16 item_size = struct_size(item, q_id, item->num_qs); 4165 4166 /* If the num of queues is even, add 2 bytes of padding */ 4167 if ((item->num_qs % 2) == 0) 4168 item_size += 2; 4169 4170 sz += item_size; 4171 4172 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4173 } 4174 4175 if (buf_size != sz) 4176 return -EINVAL; 4177 4178 do_aq: 4179 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4180 if (status) { 4181 if (!qg_list) 4182 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4183 vmvf_num, hw->adminq.sq_last_status); 4184 else 4185 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4186 le16_to_cpu(qg_list[0].q_id[0]), 4187 hw->adminq.sq_last_status); 4188 } 4189 return status; 4190 } 4191 4192 /** 4193 * ice_aq_add_rdma_qsets 4194 * @hw: pointer to the hardware structure 4195 * @num_qset_grps: Number of RDMA Qset groups 4196 * @qset_list: list of Qset groups to be added 4197 * @buf_size: size of buffer for indirect command 4198 * @cd: pointer to command details structure or NULL 4199 * 4200 * Add Tx RDMA Qsets (0x0C33) 4201 */ 4202 static int 4203 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4204 struct ice_aqc_add_rdma_qset_data *qset_list, 4205 u16 buf_size, struct ice_sq_cd *cd) 4206 { 4207 struct ice_aqc_add_rdma_qset_data *list; 4208 struct ice_aqc_add_rdma_qset *cmd; 4209 struct ice_aq_desc desc; 4210 u16 i, sum_size = 0; 4211 4212 cmd = &desc.params.add_rdma_qset; 4213 4214 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4215 4216 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4217 return -EINVAL; 4218 4219 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4220 u16 num_qsets = le16_to_cpu(list->num_qsets); 4221 4222 sum_size += struct_size(list, rdma_qsets, num_qsets); 4223 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4224 num_qsets); 4225 } 4226 4227 if (buf_size != sum_size) 4228 return -EINVAL; 4229 4230 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4231 4232 cmd->num_qset_grps = num_qset_grps; 4233 4234 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4235 } 4236 4237 /* End of FW Admin Queue command wrappers */ 4238 4239 /** 4240 * ice_write_byte - write a byte to a packed context structure 4241 * @src_ctx: the context structure to read from 4242 * @dest_ctx: the context to be written to 4243 * @ce_info: a description of the struct to be filled 4244 */ 4245 static void 4246 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4247 { 4248 u8 src_byte, dest_byte, mask; 4249 u8 *from, *dest; 4250 u16 shift_width; 4251 4252 /* copy from the next struct field */ 4253 from = src_ctx + ce_info->offset; 4254 4255 /* prepare the bits and mask */ 4256 shift_width = ce_info->lsb % 8; 4257 mask = (u8)(BIT(ce_info->width) - 1); 4258 4259 src_byte = *from; 4260 src_byte &= mask; 4261 4262 /* shift to correct alignment */ 4263 mask <<= shift_width; 4264 src_byte <<= shift_width; 4265 4266 /* get the current bits from the target bit string */ 4267 dest = dest_ctx + (ce_info->lsb / 8); 4268 4269 memcpy(&dest_byte, dest, sizeof(dest_byte)); 4270 4271 dest_byte &= ~mask; /* get the bits not changing */ 4272 dest_byte |= src_byte; /* add in the new bits */ 4273 4274 /* put it all back */ 4275 memcpy(dest, &dest_byte, sizeof(dest_byte)); 4276 } 4277 4278 /** 4279 * ice_write_word - write a word to a packed context structure 4280 * @src_ctx: the context structure to read from 4281 * @dest_ctx: the context to be written to 4282 * @ce_info: a description of the struct to be filled 4283 */ 4284 static void 4285 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4286 { 4287 u16 src_word, mask; 4288 __le16 dest_word; 4289 u8 *from, *dest; 4290 u16 shift_width; 4291 4292 /* copy from the next struct field */ 4293 from = src_ctx + ce_info->offset; 4294 4295 /* prepare the bits and mask */ 4296 shift_width = ce_info->lsb % 8; 4297 mask = BIT(ce_info->width) - 1; 4298 4299 /* don't swizzle the bits until after the mask because the mask bits 4300 * will be in a different bit position on big endian machines 4301 */ 4302 src_word = *(u16 *)from; 4303 src_word &= mask; 4304 4305 /* shift to correct alignment */ 4306 mask <<= shift_width; 4307 src_word <<= shift_width; 4308 4309 /* get the current bits from the target bit string */ 4310 dest = dest_ctx + (ce_info->lsb / 8); 4311 4312 memcpy(&dest_word, dest, sizeof(dest_word)); 4313 4314 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 4315 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 4316 4317 /* put it all back */ 4318 memcpy(dest, &dest_word, sizeof(dest_word)); 4319 } 4320 4321 /** 4322 * ice_write_dword - write a dword to a packed context structure 4323 * @src_ctx: the context structure to read from 4324 * @dest_ctx: the context to be written to 4325 * @ce_info: a description of the struct to be filled 4326 */ 4327 static void 4328 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4329 { 4330 u32 src_dword, mask; 4331 __le32 dest_dword; 4332 u8 *from, *dest; 4333 u16 shift_width; 4334 4335 /* copy from the next struct field */ 4336 from = src_ctx + ce_info->offset; 4337 4338 /* prepare the bits and mask */ 4339 shift_width = ce_info->lsb % 8; 4340 4341 /* if the field width is exactly 32 on an x86 machine, then the shift 4342 * operation will not work because the SHL instructions count is masked 4343 * to 5 bits so the shift will do nothing 4344 */ 4345 if (ce_info->width < 32) 4346 mask = BIT(ce_info->width) - 1; 4347 else 4348 mask = (u32)~0; 4349 4350 /* don't swizzle the bits until after the mask because the mask bits 4351 * will be in a different bit position on big endian machines 4352 */ 4353 src_dword = *(u32 *)from; 4354 src_dword &= mask; 4355 4356 /* shift to correct alignment */ 4357 mask <<= shift_width; 4358 src_dword <<= shift_width; 4359 4360 /* get the current bits from the target bit string */ 4361 dest = dest_ctx + (ce_info->lsb / 8); 4362 4363 memcpy(&dest_dword, dest, sizeof(dest_dword)); 4364 4365 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 4366 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 4367 4368 /* put it all back */ 4369 memcpy(dest, &dest_dword, sizeof(dest_dword)); 4370 } 4371 4372 /** 4373 * ice_write_qword - write a qword to a packed context structure 4374 * @src_ctx: the context structure to read from 4375 * @dest_ctx: the context to be written to 4376 * @ce_info: a description of the struct to be filled 4377 */ 4378 static void 4379 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4380 { 4381 u64 src_qword, mask; 4382 __le64 dest_qword; 4383 u8 *from, *dest; 4384 u16 shift_width; 4385 4386 /* copy from the next struct field */ 4387 from = src_ctx + ce_info->offset; 4388 4389 /* prepare the bits and mask */ 4390 shift_width = ce_info->lsb % 8; 4391 4392 /* if the field width is exactly 64 on an x86 machine, then the shift 4393 * operation will not work because the SHL instructions count is masked 4394 * to 6 bits so the shift will do nothing 4395 */ 4396 if (ce_info->width < 64) 4397 mask = BIT_ULL(ce_info->width) - 1; 4398 else 4399 mask = (u64)~0; 4400 4401 /* don't swizzle the bits until after the mask because the mask bits 4402 * will be in a different bit position on big endian machines 4403 */ 4404 src_qword = *(u64 *)from; 4405 src_qword &= mask; 4406 4407 /* shift to correct alignment */ 4408 mask <<= shift_width; 4409 src_qword <<= shift_width; 4410 4411 /* get the current bits from the target bit string */ 4412 dest = dest_ctx + (ce_info->lsb / 8); 4413 4414 memcpy(&dest_qword, dest, sizeof(dest_qword)); 4415 4416 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 4417 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 4418 4419 /* put it all back */ 4420 memcpy(dest, &dest_qword, sizeof(dest_qword)); 4421 } 4422 4423 /** 4424 * ice_set_ctx - set context bits in packed structure 4425 * @hw: pointer to the hardware structure 4426 * @src_ctx: pointer to a generic non-packed context structure 4427 * @dest_ctx: pointer to memory for the packed structure 4428 * @ce_info: a description of the structure to be transformed 4429 */ 4430 int 4431 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 4432 const struct ice_ctx_ele *ce_info) 4433 { 4434 int f; 4435 4436 for (f = 0; ce_info[f].width; f++) { 4437 /* We have to deal with each element of the FW response 4438 * using the correct size so that we are correct regardless 4439 * of the endianness of the machine. 4440 */ 4441 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 4442 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 4443 f, ce_info[f].width, ce_info[f].size_of); 4444 continue; 4445 } 4446 switch (ce_info[f].size_of) { 4447 case sizeof(u8): 4448 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 4449 break; 4450 case sizeof(u16): 4451 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 4452 break; 4453 case sizeof(u32): 4454 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 4455 break; 4456 case sizeof(u64): 4457 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 4458 break; 4459 default: 4460 return -EINVAL; 4461 } 4462 } 4463 4464 return 0; 4465 } 4466 4467 /** 4468 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4469 * @hw: pointer to the HW struct 4470 * @vsi_handle: software VSI handle 4471 * @tc: TC number 4472 * @q_handle: software queue handle 4473 */ 4474 struct ice_q_ctx * 4475 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4476 { 4477 struct ice_vsi_ctx *vsi; 4478 struct ice_q_ctx *q_ctx; 4479 4480 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4481 if (!vsi) 4482 return NULL; 4483 if (q_handle >= vsi->num_lan_q_entries[tc]) 4484 return NULL; 4485 if (!vsi->lan_q_ctx[tc]) 4486 return NULL; 4487 q_ctx = vsi->lan_q_ctx[tc]; 4488 return &q_ctx[q_handle]; 4489 } 4490 4491 /** 4492 * ice_ena_vsi_txq 4493 * @pi: port information structure 4494 * @vsi_handle: software VSI handle 4495 * @tc: TC number 4496 * @q_handle: software queue handle 4497 * @num_qgrps: Number of added queue groups 4498 * @buf: list of queue groups to be added 4499 * @buf_size: size of buffer for indirect command 4500 * @cd: pointer to command details structure or NULL 4501 * 4502 * This function adds one LAN queue 4503 */ 4504 int 4505 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4506 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4507 struct ice_sq_cd *cd) 4508 { 4509 struct ice_aqc_txsched_elem_data node = { 0 }; 4510 struct ice_sched_node *parent; 4511 struct ice_q_ctx *q_ctx; 4512 struct ice_hw *hw; 4513 int status; 4514 4515 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4516 return -EIO; 4517 4518 if (num_qgrps > 1 || buf->num_txqs > 1) 4519 return -ENOSPC; 4520 4521 hw = pi->hw; 4522 4523 if (!ice_is_vsi_valid(hw, vsi_handle)) 4524 return -EINVAL; 4525 4526 mutex_lock(&pi->sched_lock); 4527 4528 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4529 if (!q_ctx) { 4530 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4531 q_handle); 4532 status = -EINVAL; 4533 goto ena_txq_exit; 4534 } 4535 4536 /* find a parent node */ 4537 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4538 ICE_SCHED_NODE_OWNER_LAN); 4539 if (!parent) { 4540 status = -EINVAL; 4541 goto ena_txq_exit; 4542 } 4543 4544 buf->parent_teid = parent->info.node_teid; 4545 node.parent_teid = parent->info.node_teid; 4546 /* Mark that the values in the "generic" section as valid. The default 4547 * value in the "generic" section is zero. This means that : 4548 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4549 * - 0 priority among siblings, indicated by Bit 1-3. 4550 * - WFQ, indicated by Bit 4. 4551 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4552 * Bit 5-6. 4553 * - Bit 7 is reserved. 4554 * Without setting the generic section as valid in valid_sections, the 4555 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4556 */ 4557 buf->txqs[0].info.valid_sections = 4558 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4559 ICE_AQC_ELEM_VALID_EIR; 4560 buf->txqs[0].info.generic = 0; 4561 buf->txqs[0].info.cir_bw.bw_profile_idx = 4562 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4563 buf->txqs[0].info.cir_bw.bw_alloc = 4564 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4565 buf->txqs[0].info.eir_bw.bw_profile_idx = 4566 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4567 buf->txqs[0].info.eir_bw.bw_alloc = 4568 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4569 4570 /* add the LAN queue */ 4571 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4572 if (status) { 4573 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4574 le16_to_cpu(buf->txqs[0].txq_id), 4575 hw->adminq.sq_last_status); 4576 goto ena_txq_exit; 4577 } 4578 4579 node.node_teid = buf->txqs[0].q_teid; 4580 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4581 q_ctx->q_handle = q_handle; 4582 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4583 4584 /* add a leaf node into scheduler tree queue layer */ 4585 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 4586 if (!status) 4587 status = ice_sched_replay_q_bw(pi, q_ctx); 4588 4589 ena_txq_exit: 4590 mutex_unlock(&pi->sched_lock); 4591 return status; 4592 } 4593 4594 /** 4595 * ice_dis_vsi_txq 4596 * @pi: port information structure 4597 * @vsi_handle: software VSI handle 4598 * @tc: TC number 4599 * @num_queues: number of queues 4600 * @q_handles: pointer to software queue handle array 4601 * @q_ids: pointer to the q_id array 4602 * @q_teids: pointer to queue node teids 4603 * @rst_src: if called due to reset, specifies the reset source 4604 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4605 * @cd: pointer to command details structure or NULL 4606 * 4607 * This function removes queues and their corresponding nodes in SW DB 4608 */ 4609 int 4610 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4611 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4612 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4613 struct ice_sq_cd *cd) 4614 { 4615 struct ice_aqc_dis_txq_item *qg_list; 4616 struct ice_q_ctx *q_ctx; 4617 int status = -ENOENT; 4618 struct ice_hw *hw; 4619 u16 i, buf_size; 4620 4621 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4622 return -EIO; 4623 4624 hw = pi->hw; 4625 4626 if (!num_queues) { 4627 /* if queue is disabled already yet the disable queue command 4628 * has to be sent to complete the VF reset, then call 4629 * ice_aq_dis_lan_txq without any queue information 4630 */ 4631 if (rst_src) 4632 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4633 vmvf_num, NULL); 4634 return -EIO; 4635 } 4636 4637 buf_size = struct_size(qg_list, q_id, 1); 4638 qg_list = kzalloc(buf_size, GFP_KERNEL); 4639 if (!qg_list) 4640 return -ENOMEM; 4641 4642 mutex_lock(&pi->sched_lock); 4643 4644 for (i = 0; i < num_queues; i++) { 4645 struct ice_sched_node *node; 4646 4647 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4648 if (!node) 4649 continue; 4650 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4651 if (!q_ctx) { 4652 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4653 q_handles[i]); 4654 continue; 4655 } 4656 if (q_ctx->q_handle != q_handles[i]) { 4657 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4658 q_ctx->q_handle, q_handles[i]); 4659 continue; 4660 } 4661 qg_list->parent_teid = node->info.parent_teid; 4662 qg_list->num_qs = 1; 4663 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4664 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4665 vmvf_num, cd); 4666 4667 if (status) 4668 break; 4669 ice_free_sched_node(pi, node); 4670 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4671 } 4672 mutex_unlock(&pi->sched_lock); 4673 kfree(qg_list); 4674 return status; 4675 } 4676 4677 /** 4678 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4679 * @pi: port information structure 4680 * @vsi_handle: software VSI handle 4681 * @tc_bitmap: TC bitmap 4682 * @maxqs: max queues array per TC 4683 * @owner: LAN or RDMA 4684 * 4685 * This function adds/updates the VSI queues per TC. 4686 */ 4687 static int 4688 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4689 u16 *maxqs, u8 owner) 4690 { 4691 int status = 0; 4692 u8 i; 4693 4694 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4695 return -EIO; 4696 4697 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4698 return -EINVAL; 4699 4700 mutex_lock(&pi->sched_lock); 4701 4702 ice_for_each_traffic_class(i) { 4703 /* configuration is possible only if TC node is present */ 4704 if (!ice_sched_get_tc_node(pi, i)) 4705 continue; 4706 4707 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4708 ice_is_tc_ena(tc_bitmap, i)); 4709 if (status) 4710 break; 4711 } 4712 4713 mutex_unlock(&pi->sched_lock); 4714 return status; 4715 } 4716 4717 /** 4718 * ice_cfg_vsi_lan - configure VSI LAN queues 4719 * @pi: port information structure 4720 * @vsi_handle: software VSI handle 4721 * @tc_bitmap: TC bitmap 4722 * @max_lanqs: max LAN queues array per TC 4723 * 4724 * This function adds/updates the VSI LAN queues per TC. 4725 */ 4726 int 4727 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4728 u16 *max_lanqs) 4729 { 4730 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4731 ICE_SCHED_NODE_OWNER_LAN); 4732 } 4733 4734 /** 4735 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 4736 * @pi: port information structure 4737 * @vsi_handle: software VSI handle 4738 * @tc_bitmap: TC bitmap 4739 * @max_rdmaqs: max RDMA queues array per TC 4740 * 4741 * This function adds/updates the VSI RDMA queues per TC. 4742 */ 4743 int 4744 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4745 u16 *max_rdmaqs) 4746 { 4747 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 4748 ICE_SCHED_NODE_OWNER_RDMA); 4749 } 4750 4751 /** 4752 * ice_ena_vsi_rdma_qset 4753 * @pi: port information structure 4754 * @vsi_handle: software VSI handle 4755 * @tc: TC number 4756 * @rdma_qset: pointer to RDMA Qset 4757 * @num_qsets: number of RDMA Qsets 4758 * @qset_teid: pointer to Qset node TEIDs 4759 * 4760 * This function adds RDMA Qset 4761 */ 4762 int 4763 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4764 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 4765 { 4766 struct ice_aqc_txsched_elem_data node = { 0 }; 4767 struct ice_aqc_add_rdma_qset_data *buf; 4768 struct ice_sched_node *parent; 4769 struct ice_hw *hw; 4770 u16 i, buf_size; 4771 int ret; 4772 4773 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4774 return -EIO; 4775 hw = pi->hw; 4776 4777 if (!ice_is_vsi_valid(hw, vsi_handle)) 4778 return -EINVAL; 4779 4780 buf_size = struct_size(buf, rdma_qsets, num_qsets); 4781 buf = kzalloc(buf_size, GFP_KERNEL); 4782 if (!buf) 4783 return -ENOMEM; 4784 mutex_lock(&pi->sched_lock); 4785 4786 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4787 ICE_SCHED_NODE_OWNER_RDMA); 4788 if (!parent) { 4789 ret = -EINVAL; 4790 goto rdma_error_exit; 4791 } 4792 buf->parent_teid = parent->info.node_teid; 4793 node.parent_teid = parent->info.node_teid; 4794 4795 buf->num_qsets = cpu_to_le16(num_qsets); 4796 for (i = 0; i < num_qsets; i++) { 4797 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 4798 buf->rdma_qsets[i].info.valid_sections = 4799 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4800 ICE_AQC_ELEM_VALID_EIR; 4801 buf->rdma_qsets[i].info.generic = 0; 4802 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 4803 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4804 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 4805 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4806 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 4807 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4808 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 4809 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4810 } 4811 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 4812 if (ret) { 4813 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 4814 goto rdma_error_exit; 4815 } 4816 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4817 for (i = 0; i < num_qsets; i++) { 4818 node.node_teid = buf->rdma_qsets[i].qset_teid; 4819 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 4820 &node); 4821 if (ret) 4822 break; 4823 qset_teid[i] = le32_to_cpu(node.node_teid); 4824 } 4825 rdma_error_exit: 4826 mutex_unlock(&pi->sched_lock); 4827 kfree(buf); 4828 return ret; 4829 } 4830 4831 /** 4832 * ice_dis_vsi_rdma_qset - free RDMA resources 4833 * @pi: port_info struct 4834 * @count: number of RDMA Qsets to free 4835 * @qset_teid: TEID of Qset node 4836 * @q_id: list of queue IDs being disabled 4837 */ 4838 int 4839 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 4840 u16 *q_id) 4841 { 4842 struct ice_aqc_dis_txq_item *qg_list; 4843 struct ice_hw *hw; 4844 int status = 0; 4845 u16 qg_size; 4846 int i; 4847 4848 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4849 return -EIO; 4850 4851 hw = pi->hw; 4852 4853 qg_size = struct_size(qg_list, q_id, 1); 4854 qg_list = kzalloc(qg_size, GFP_KERNEL); 4855 if (!qg_list) 4856 return -ENOMEM; 4857 4858 mutex_lock(&pi->sched_lock); 4859 4860 for (i = 0; i < count; i++) { 4861 struct ice_sched_node *node; 4862 4863 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 4864 if (!node) 4865 continue; 4866 4867 qg_list->parent_teid = node->info.parent_teid; 4868 qg_list->num_qs = 1; 4869 qg_list->q_id[0] = 4870 cpu_to_le16(q_id[i] | 4871 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 4872 4873 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 4874 ICE_NO_RESET, 0, NULL); 4875 if (status) 4876 break; 4877 4878 ice_free_sched_node(pi, node); 4879 } 4880 4881 mutex_unlock(&pi->sched_lock); 4882 kfree(qg_list); 4883 return status; 4884 } 4885 4886 /** 4887 * ice_replay_pre_init - replay pre initialization 4888 * @hw: pointer to the HW struct 4889 * 4890 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4891 */ 4892 static int ice_replay_pre_init(struct ice_hw *hw) 4893 { 4894 struct ice_switch_info *sw = hw->switch_info; 4895 u8 i; 4896 4897 /* Delete old entries from replay filter list head if there is any */ 4898 ice_rm_all_sw_replay_rule_info(hw); 4899 /* In start of replay, move entries into replay_rules list, it 4900 * will allow adding rules entries back to filt_rules list, 4901 * which is operational list. 4902 */ 4903 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 4904 list_replace_init(&sw->recp_list[i].filt_rules, 4905 &sw->recp_list[i].filt_replay_rules); 4906 ice_sched_replay_agg_vsi_preinit(hw); 4907 4908 return 0; 4909 } 4910 4911 /** 4912 * ice_replay_vsi - replay VSI configuration 4913 * @hw: pointer to the HW struct 4914 * @vsi_handle: driver VSI handle 4915 * 4916 * Restore all VSI configuration after reset. It is required to call this 4917 * function with main VSI first. 4918 */ 4919 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4920 { 4921 int status; 4922 4923 if (!ice_is_vsi_valid(hw, vsi_handle)) 4924 return -EINVAL; 4925 4926 /* Replay pre-initialization if there is any */ 4927 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 4928 status = ice_replay_pre_init(hw); 4929 if (status) 4930 return status; 4931 } 4932 /* Replay per VSI all RSS configurations */ 4933 status = ice_replay_rss_cfg(hw, vsi_handle); 4934 if (status) 4935 return status; 4936 /* Replay per VSI all filters */ 4937 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 4938 if (!status) 4939 status = ice_replay_vsi_agg(hw, vsi_handle); 4940 return status; 4941 } 4942 4943 /** 4944 * ice_replay_post - post replay configuration cleanup 4945 * @hw: pointer to the HW struct 4946 * 4947 * Post replay cleanup. 4948 */ 4949 void ice_replay_post(struct ice_hw *hw) 4950 { 4951 /* Delete old entries from replay filter list head */ 4952 ice_rm_all_sw_replay_rule_info(hw); 4953 ice_sched_replay_agg(hw); 4954 } 4955 4956 /** 4957 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4958 * @hw: ptr to the hardware info 4959 * @reg: offset of 64 bit HW register to read from 4960 * @prev_stat_loaded: bool to specify if previous stats are loaded 4961 * @prev_stat: ptr to previous loaded stat value 4962 * @cur_stat: ptr to current stat value 4963 */ 4964 void 4965 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4966 u64 *prev_stat, u64 *cur_stat) 4967 { 4968 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4969 4970 /* device stats are not reset at PFR, they likely will not be zeroed 4971 * when the driver starts. Thus, save the value from the first read 4972 * without adding to the statistic value so that we report stats which 4973 * count up from zero. 4974 */ 4975 if (!prev_stat_loaded) { 4976 *prev_stat = new_data; 4977 return; 4978 } 4979 4980 /* Calculate the difference between the new and old values, and then 4981 * add it to the software stat value. 4982 */ 4983 if (new_data >= *prev_stat) 4984 *cur_stat += new_data - *prev_stat; 4985 else 4986 /* to manage the potential roll-over */ 4987 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4988 4989 /* Update the previously stored value to prepare for next read */ 4990 *prev_stat = new_data; 4991 } 4992 4993 /** 4994 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4995 * @hw: ptr to the hardware info 4996 * @reg: offset of HW register to read from 4997 * @prev_stat_loaded: bool to specify if previous stats are loaded 4998 * @prev_stat: ptr to previous loaded stat value 4999 * @cur_stat: ptr to current stat value 5000 */ 5001 void 5002 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5003 u64 *prev_stat, u64 *cur_stat) 5004 { 5005 u32 new_data; 5006 5007 new_data = rd32(hw, reg); 5008 5009 /* device stats are not reset at PFR, they likely will not be zeroed 5010 * when the driver starts. Thus, save the value from the first read 5011 * without adding to the statistic value so that we report stats which 5012 * count up from zero. 5013 */ 5014 if (!prev_stat_loaded) { 5015 *prev_stat = new_data; 5016 return; 5017 } 5018 5019 /* Calculate the difference between the new and old values, and then 5020 * add it to the software stat value. 5021 */ 5022 if (new_data >= *prev_stat) 5023 *cur_stat += new_data - *prev_stat; 5024 else 5025 /* to manage the potential roll-over */ 5026 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5027 5028 /* Update the previously stored value to prepare for next read */ 5029 *prev_stat = new_data; 5030 } 5031 5032 /** 5033 * ice_sched_query_elem - query element information from HW 5034 * @hw: pointer to the HW struct 5035 * @node_teid: node TEID to be queried 5036 * @buf: buffer to element information 5037 * 5038 * This function queries HW element information 5039 */ 5040 int 5041 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5042 struct ice_aqc_txsched_elem_data *buf) 5043 { 5044 u16 buf_size, num_elem_ret = 0; 5045 int status; 5046 5047 buf_size = sizeof(*buf); 5048 memset(buf, 0, buf_size); 5049 buf->node_teid = cpu_to_le32(node_teid); 5050 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5051 NULL); 5052 if (status || num_elem_ret != 1) 5053 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5054 return status; 5055 } 5056 5057 /** 5058 * ice_aq_read_i2c 5059 * @hw: pointer to the hw struct 5060 * @topo_addr: topology address for a device to communicate with 5061 * @bus_addr: 7-bit I2C bus address 5062 * @addr: I2C memory address (I2C offset) with up to 16 bits 5063 * @params: I2C parameters: bit [7] - Repeated start, 5064 * bits [6:5] data offset size, 5065 * bit [4] - I2C address type, 5066 * bits [3:0] - data size to read (0-16 bytes) 5067 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5068 * @cd: pointer to command details structure or NULL 5069 * 5070 * Read I2C (0x06E2) 5071 */ 5072 int 5073 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5074 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5075 struct ice_sq_cd *cd) 5076 { 5077 struct ice_aq_desc desc = { 0 }; 5078 struct ice_aqc_i2c *cmd; 5079 u8 data_size; 5080 int status; 5081 5082 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5083 cmd = &desc.params.read_write_i2c; 5084 5085 if (!data) 5086 return -EINVAL; 5087 5088 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5089 5090 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5091 cmd->topo_addr = topo_addr; 5092 cmd->i2c_params = params; 5093 cmd->i2c_addr = addr; 5094 5095 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5096 if (!status) { 5097 struct ice_aqc_read_i2c_resp *resp; 5098 u8 i; 5099 5100 resp = &desc.params.read_i2c_resp; 5101 for (i = 0; i < data_size; i++) { 5102 *data = resp->i2c_data[i]; 5103 data++; 5104 } 5105 } 5106 5107 return status; 5108 } 5109 5110 /** 5111 * ice_aq_write_i2c 5112 * @hw: pointer to the hw struct 5113 * @topo_addr: topology address for a device to communicate with 5114 * @bus_addr: 7-bit I2C bus address 5115 * @addr: I2C memory address (I2C offset) with up to 16 bits 5116 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5117 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5118 * @cd: pointer to command details structure or NULL 5119 * 5120 * Write I2C (0x06E3) 5121 * 5122 * * Return: 5123 * * 0 - Successful write to the i2c device 5124 * * -EINVAL - Data size greater than 4 bytes 5125 * * -EIO - FW error 5126 */ 5127 int 5128 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5129 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5130 struct ice_sq_cd *cd) 5131 { 5132 struct ice_aq_desc desc = { 0 }; 5133 struct ice_aqc_i2c *cmd; 5134 u8 data_size; 5135 5136 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5137 cmd = &desc.params.read_write_i2c; 5138 5139 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5140 5141 /* data_size limited to 4 */ 5142 if (data_size > 4) 5143 return -EINVAL; 5144 5145 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5146 cmd->topo_addr = topo_addr; 5147 cmd->i2c_params = params; 5148 cmd->i2c_addr = addr; 5149 5150 memcpy(cmd->i2c_data, data, data_size); 5151 5152 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5153 } 5154 5155 /** 5156 * ice_aq_set_driver_param - Set driver parameter to share via firmware 5157 * @hw: pointer to the HW struct 5158 * @idx: parameter index to set 5159 * @value: the value to set the parameter to 5160 * @cd: pointer to command details structure or NULL 5161 * 5162 * Set the value of one of the software defined parameters. All PFs connected 5163 * to this device can read the value using ice_aq_get_driver_param. 5164 * 5165 * Note that firmware provides no synchronization or locking, and will not 5166 * save the parameter value during a device reset. It is expected that 5167 * a single PF will write the parameter value, while all other PFs will only 5168 * read it. 5169 */ 5170 int 5171 ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx, 5172 u32 value, struct ice_sq_cd *cd) 5173 { 5174 struct ice_aqc_driver_shared_params *cmd; 5175 struct ice_aq_desc desc; 5176 5177 if (idx >= ICE_AQC_DRIVER_PARAM_MAX) 5178 return -EIO; 5179 5180 cmd = &desc.params.drv_shared_params; 5181 5182 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params); 5183 5184 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_SET; 5185 cmd->param_indx = idx; 5186 cmd->param_val = cpu_to_le32(value); 5187 5188 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5189 } 5190 5191 /** 5192 * ice_aq_get_driver_param - Get driver parameter shared via firmware 5193 * @hw: pointer to the HW struct 5194 * @idx: parameter index to set 5195 * @value: storage to return the shared parameter 5196 * @cd: pointer to command details structure or NULL 5197 * 5198 * Get the value of one of the software defined parameters. 5199 * 5200 * Note that firmware provides no synchronization or locking. It is expected 5201 * that only a single PF will write a given parameter. 5202 */ 5203 int 5204 ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx, 5205 u32 *value, struct ice_sq_cd *cd) 5206 { 5207 struct ice_aqc_driver_shared_params *cmd; 5208 struct ice_aq_desc desc; 5209 int status; 5210 5211 if (idx >= ICE_AQC_DRIVER_PARAM_MAX) 5212 return -EIO; 5213 5214 cmd = &desc.params.drv_shared_params; 5215 5216 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params); 5217 5218 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_GET; 5219 cmd->param_indx = idx; 5220 5221 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5222 if (status) 5223 return status; 5224 5225 *value = le32_to_cpu(cmd->param_val); 5226 5227 return 0; 5228 } 5229 5230 /** 5231 * ice_aq_set_gpio 5232 * @hw: pointer to the hw struct 5233 * @gpio_ctrl_handle: GPIO controller node handle 5234 * @pin_idx: IO Number of the GPIO that needs to be set 5235 * @value: SW provide IO value to set in the LSB 5236 * @cd: pointer to command details structure or NULL 5237 * 5238 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 5239 */ 5240 int 5241 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 5242 struct ice_sq_cd *cd) 5243 { 5244 struct ice_aqc_gpio *cmd; 5245 struct ice_aq_desc desc; 5246 5247 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 5248 cmd = &desc.params.read_write_gpio; 5249 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5250 cmd->gpio_num = pin_idx; 5251 cmd->gpio_val = value ? 1 : 0; 5252 5253 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5254 } 5255 5256 /** 5257 * ice_aq_get_gpio 5258 * @hw: pointer to the hw struct 5259 * @gpio_ctrl_handle: GPIO controller node handle 5260 * @pin_idx: IO Number of the GPIO that needs to be set 5261 * @value: IO value read 5262 * @cd: pointer to command details structure or NULL 5263 * 5264 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 5265 * the topology 5266 */ 5267 int 5268 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 5269 bool *value, struct ice_sq_cd *cd) 5270 { 5271 struct ice_aqc_gpio *cmd; 5272 struct ice_aq_desc desc; 5273 int status; 5274 5275 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 5276 cmd = &desc.params.read_write_gpio; 5277 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5278 cmd->gpio_num = pin_idx; 5279 5280 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5281 if (status) 5282 return status; 5283 5284 *value = !!cmd->gpio_val; 5285 return 0; 5286 } 5287 5288 /** 5289 * ice_fw_supports_link_override 5290 * @hw: pointer to the hardware structure 5291 * 5292 * Checks if the firmware supports link override 5293 */ 5294 bool ice_fw_supports_link_override(struct ice_hw *hw) 5295 { 5296 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 5297 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 5298 return true; 5299 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 5300 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 5301 return true; 5302 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 5303 return true; 5304 } 5305 5306 return false; 5307 } 5308 5309 /** 5310 * ice_get_link_default_override 5311 * @ldo: pointer to the link default override struct 5312 * @pi: pointer to the port info struct 5313 * 5314 * Gets the link default override for a port 5315 */ 5316 int 5317 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 5318 struct ice_port_info *pi) 5319 { 5320 u16 i, tlv, tlv_len, tlv_start, buf, offset; 5321 struct ice_hw *hw = pi->hw; 5322 int status; 5323 5324 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 5325 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 5326 if (status) { 5327 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 5328 return status; 5329 } 5330 5331 /* Each port has its own config; calculate for our port */ 5332 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 5333 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 5334 5335 /* link options first */ 5336 status = ice_read_sr_word(hw, tlv_start, &buf); 5337 if (status) { 5338 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5339 return status; 5340 } 5341 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 5342 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 5343 ICE_LINK_OVERRIDE_PHY_CFG_S; 5344 5345 /* link PHY config */ 5346 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 5347 status = ice_read_sr_word(hw, offset, &buf); 5348 if (status) { 5349 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 5350 return status; 5351 } 5352 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 5353 5354 /* PHY types low */ 5355 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 5356 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5357 status = ice_read_sr_word(hw, (offset + i), &buf); 5358 if (status) { 5359 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5360 return status; 5361 } 5362 /* shift 16 bits at a time to fill 64 bits */ 5363 ldo->phy_type_low |= ((u64)buf << (i * 16)); 5364 } 5365 5366 /* PHY types high */ 5367 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 5368 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 5369 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5370 status = ice_read_sr_word(hw, (offset + i), &buf); 5371 if (status) { 5372 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5373 return status; 5374 } 5375 /* shift 16 bits at a time to fill 64 bits */ 5376 ldo->phy_type_high |= ((u64)buf << (i * 16)); 5377 } 5378 5379 return status; 5380 } 5381 5382 /** 5383 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 5384 * @caps: get PHY capability data 5385 */ 5386 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 5387 { 5388 if (caps->caps & ICE_AQC_PHY_AN_MODE || 5389 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 5390 ICE_AQC_PHY_AN_EN_CLAUSE73 | 5391 ICE_AQC_PHY_AN_EN_CLAUSE37)) 5392 return true; 5393 5394 return false; 5395 } 5396 5397 /** 5398 * ice_aq_set_lldp_mib - Set the LLDP MIB 5399 * @hw: pointer to the HW struct 5400 * @mib_type: Local, Remote or both Local and Remote MIBs 5401 * @buf: pointer to the caller-supplied buffer to store the MIB block 5402 * @buf_size: size of the buffer (in bytes) 5403 * @cd: pointer to command details structure or NULL 5404 * 5405 * Set the LLDP MIB. (0x0A08) 5406 */ 5407 int 5408 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 5409 struct ice_sq_cd *cd) 5410 { 5411 struct ice_aqc_lldp_set_local_mib *cmd; 5412 struct ice_aq_desc desc; 5413 5414 cmd = &desc.params.lldp_set_mib; 5415 5416 if (buf_size == 0 || !buf) 5417 return -EINVAL; 5418 5419 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5420 5421 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 5422 desc.datalen = cpu_to_le16(buf_size); 5423 5424 cmd->type = mib_type; 5425 cmd->length = cpu_to_le16(buf_size); 5426 5427 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5428 } 5429 5430 /** 5431 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5432 * @hw: pointer to HW struct 5433 */ 5434 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 5435 { 5436 if (hw->mac_type != ICE_MAC_E810) 5437 return false; 5438 5439 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) { 5440 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN) 5441 return true; 5442 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN && 5443 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH) 5444 return true; 5445 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) { 5446 return true; 5447 } 5448 return false; 5449 } 5450 5451 /** 5452 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 5453 * @hw: pointer to HW struct 5454 * @vsi_num: absolute HW index for VSI 5455 * @add: boolean for if adding or removing a filter 5456 */ 5457 int 5458 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 5459 { 5460 struct ice_aqc_lldp_filter_ctrl *cmd; 5461 struct ice_aq_desc desc; 5462 5463 cmd = &desc.params.lldp_filter_ctrl; 5464 5465 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 5466 5467 if (add) 5468 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 5469 else 5470 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 5471 5472 cmd->vsi_num = cpu_to_le16(vsi_num); 5473 5474 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5475 } 5476 5477 /** 5478 * ice_fw_supports_report_dflt_cfg 5479 * @hw: pointer to the hardware structure 5480 * 5481 * Checks if the firmware supports report default configuration 5482 */ 5483 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 5484 { 5485 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5486 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN) 5487 return true; 5488 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN && 5489 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH) 5490 return true; 5491 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5492 return true; 5493 } 5494 return false; 5495 } 5496