1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 8 #define ICE_PF_RESET_WAIT_COUNT 200 9 10 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \ 11 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \ 12 ((ICE_RX_OPC_MDID << \ 13 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \ 14 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \ 15 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \ 16 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M)) 17 18 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \ 19 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \ 20 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \ 21 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \ 22 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \ 23 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \ 24 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \ 25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \ 26 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \ 27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M)) 28 29 /** 30 * ice_set_mac_type - Sets MAC type 31 * @hw: pointer to the HW structure 32 * 33 * This function sets the MAC type of the adapter based on the 34 * vendor ID and device ID stored in the HW structure. 35 */ 36 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 37 { 38 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 39 return ICE_ERR_DEVICE_NOT_SUPPORTED; 40 41 hw->mac_type = ICE_MAC_GENERIC; 42 return 0; 43 } 44 45 /** 46 * ice_dev_onetime_setup - Temporary HW/FW workarounds 47 * @hw: pointer to the HW structure 48 * 49 * This function provides temporary workarounds for certain issues 50 * that are expected to be fixed in the HW/FW. 51 */ 52 void ice_dev_onetime_setup(struct ice_hw *hw) 53 { 54 #define MBX_PF_VT_PFALLOC 0x00231E80 55 /* set VFs per PF */ 56 wr32(hw, MBX_PF_VT_PFALLOC, rd32(hw, PF_VT_PFALLOC_HIF)); 57 } 58 59 /** 60 * ice_clear_pf_cfg - Clear PF configuration 61 * @hw: pointer to the hardware structure 62 * 63 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 64 * configuration, flow director filters, etc.). 65 */ 66 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 67 { 68 struct ice_aq_desc desc; 69 70 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 71 72 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 73 } 74 75 /** 76 * ice_aq_manage_mac_read - manage MAC address read command 77 * @hw: pointer to the HW struct 78 * @buf: a virtual buffer to hold the manage MAC read response 79 * @buf_size: Size of the virtual buffer 80 * @cd: pointer to command details structure or NULL 81 * 82 * This function is used to return per PF station MAC address (0x0107). 83 * NOTE: Upon successful completion of this command, MAC address information 84 * is returned in user specified buffer. Please interpret user specified 85 * buffer as "manage_mac_read" response. 86 * Response such as various MAC addresses are stored in HW struct (port.mac) 87 * ice_aq_discover_caps is expected to be called before this function is called. 88 */ 89 static enum ice_status 90 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 91 struct ice_sq_cd *cd) 92 { 93 struct ice_aqc_manage_mac_read_resp *resp; 94 struct ice_aqc_manage_mac_read *cmd; 95 struct ice_aq_desc desc; 96 enum ice_status status; 97 u16 flags; 98 u8 i; 99 100 cmd = &desc.params.mac_read; 101 102 if (buf_size < sizeof(*resp)) 103 return ICE_ERR_BUF_TOO_SHORT; 104 105 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 106 107 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 108 if (status) 109 return status; 110 111 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 112 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 113 114 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 115 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 116 return ICE_ERR_CFG; 117 } 118 119 /* A single port can report up to two (LAN and WoL) addresses */ 120 for (i = 0; i < cmd->num_addr; i++) 121 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 122 ether_addr_copy(hw->port_info->mac.lan_addr, 123 resp[i].mac_addr); 124 ether_addr_copy(hw->port_info->mac.perm_addr, 125 resp[i].mac_addr); 126 break; 127 } 128 129 return 0; 130 } 131 132 /** 133 * ice_aq_get_phy_caps - returns PHY capabilities 134 * @pi: port information structure 135 * @qual_mods: report qualified modules 136 * @report_mode: report mode capabilities 137 * @pcaps: structure for PHY capabilities to be filled 138 * @cd: pointer to command details structure or NULL 139 * 140 * Returns the various PHY capabilities supported on the Port (0x0600) 141 */ 142 enum ice_status 143 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 144 struct ice_aqc_get_phy_caps_data *pcaps, 145 struct ice_sq_cd *cd) 146 { 147 struct ice_aqc_get_phy_caps *cmd; 148 u16 pcaps_size = sizeof(*pcaps); 149 struct ice_aq_desc desc; 150 enum ice_status status; 151 152 cmd = &desc.params.get_phy; 153 154 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 155 return ICE_ERR_PARAM; 156 157 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 158 159 if (qual_mods) 160 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 161 162 cmd->param0 |= cpu_to_le16(report_mode); 163 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd); 164 165 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) { 166 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 167 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 168 } 169 170 return status; 171 } 172 173 /** 174 * ice_get_media_type - Gets media type 175 * @pi: port information structure 176 */ 177 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 178 { 179 struct ice_link_status *hw_link_info; 180 181 if (!pi) 182 return ICE_MEDIA_UNKNOWN; 183 184 hw_link_info = &pi->phy.link_info; 185 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 186 /* If more than one media type is selected, report unknown */ 187 return ICE_MEDIA_UNKNOWN; 188 189 if (hw_link_info->phy_type_low) { 190 switch (hw_link_info->phy_type_low) { 191 case ICE_PHY_TYPE_LOW_1000BASE_SX: 192 case ICE_PHY_TYPE_LOW_1000BASE_LX: 193 case ICE_PHY_TYPE_LOW_10GBASE_SR: 194 case ICE_PHY_TYPE_LOW_10GBASE_LR: 195 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 196 case ICE_PHY_TYPE_LOW_25GBASE_SR: 197 case ICE_PHY_TYPE_LOW_25GBASE_LR: 198 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 199 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 200 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 201 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 202 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 203 case ICE_PHY_TYPE_LOW_50GBASE_SR: 204 case ICE_PHY_TYPE_LOW_50GBASE_FR: 205 case ICE_PHY_TYPE_LOW_50GBASE_LR: 206 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 207 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 208 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 209 case ICE_PHY_TYPE_LOW_100GBASE_DR: 210 return ICE_MEDIA_FIBER; 211 case ICE_PHY_TYPE_LOW_100BASE_TX: 212 case ICE_PHY_TYPE_LOW_1000BASE_T: 213 case ICE_PHY_TYPE_LOW_2500BASE_T: 214 case ICE_PHY_TYPE_LOW_5GBASE_T: 215 case ICE_PHY_TYPE_LOW_10GBASE_T: 216 case ICE_PHY_TYPE_LOW_25GBASE_T: 217 return ICE_MEDIA_BASET; 218 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 219 case ICE_PHY_TYPE_LOW_25GBASE_CR: 220 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 221 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 222 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 223 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 224 case ICE_PHY_TYPE_LOW_50GBASE_CP: 225 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 226 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 227 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 228 return ICE_MEDIA_DA; 229 case ICE_PHY_TYPE_LOW_1000BASE_KX: 230 case ICE_PHY_TYPE_LOW_2500BASE_KX: 231 case ICE_PHY_TYPE_LOW_2500BASE_X: 232 case ICE_PHY_TYPE_LOW_5GBASE_KR: 233 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 234 case ICE_PHY_TYPE_LOW_25GBASE_KR: 235 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 236 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 237 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 238 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 239 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 240 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 241 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 242 return ICE_MEDIA_BACKPLANE; 243 } 244 } else { 245 switch (hw_link_info->phy_type_high) { 246 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 247 return ICE_MEDIA_BACKPLANE; 248 } 249 } 250 return ICE_MEDIA_UNKNOWN; 251 } 252 253 /** 254 * ice_aq_get_link_info 255 * @pi: port information structure 256 * @ena_lse: enable/disable LinkStatusEvent reporting 257 * @link: pointer to link status structure - optional 258 * @cd: pointer to command details structure or NULL 259 * 260 * Get Link Status (0x607). Returns the link status of the adapter. 261 */ 262 enum ice_status 263 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 264 struct ice_link_status *link, struct ice_sq_cd *cd) 265 { 266 struct ice_aqc_get_link_status_data link_data = { 0 }; 267 struct ice_aqc_get_link_status *resp; 268 struct ice_link_status *li_old, *li; 269 enum ice_media_type *hw_media_type; 270 struct ice_fc_info *hw_fc_info; 271 bool tx_pause, rx_pause; 272 struct ice_aq_desc desc; 273 enum ice_status status; 274 struct ice_hw *hw; 275 u16 cmd_flags; 276 277 if (!pi) 278 return ICE_ERR_PARAM; 279 hw = pi->hw; 280 li_old = &pi->phy.link_info_old; 281 hw_media_type = &pi->phy.media_type; 282 li = &pi->phy.link_info; 283 hw_fc_info = &pi->fc; 284 285 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 286 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 287 resp = &desc.params.get_link_status; 288 resp->cmd_flags = cpu_to_le16(cmd_flags); 289 resp->lport_num = pi->lport; 290 291 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 292 293 if (status) 294 return status; 295 296 /* save off old link status information */ 297 *li_old = *li; 298 299 /* update current link status information */ 300 li->link_speed = le16_to_cpu(link_data.link_speed); 301 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 302 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 303 *hw_media_type = ice_get_media_type(pi); 304 li->link_info = link_data.link_info; 305 li->an_info = link_data.an_info; 306 li->ext_info = link_data.ext_info; 307 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 308 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 309 li->topo_media_conflict = link_data.topo_media_conflict; 310 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 311 ICE_AQ_CFG_PACING_TYPE_M); 312 313 /* update fc info */ 314 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 315 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 316 if (tx_pause && rx_pause) 317 hw_fc_info->current_mode = ICE_FC_FULL; 318 else if (tx_pause) 319 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 320 else if (rx_pause) 321 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 322 else 323 hw_fc_info->current_mode = ICE_FC_NONE; 324 325 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 326 327 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed); 328 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n", 329 (unsigned long long)li->phy_type_low); 330 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n", 331 (unsigned long long)li->phy_type_high); 332 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type); 333 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info); 334 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info); 335 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info); 336 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena); 337 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size); 338 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing); 339 340 /* save link status information */ 341 if (link) 342 *link = *li; 343 344 /* flag cleared so calling functions don't call AQ again */ 345 pi->phy.get_link_info = false; 346 347 return 0; 348 } 349 350 /** 351 * ice_init_flex_flags 352 * @hw: pointer to the hardware structure 353 * @prof_id: Rx Descriptor Builder profile ID 354 * 355 * Function to initialize Rx flex flags 356 */ 357 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id) 358 { 359 u8 idx = 0; 360 361 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout: 362 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE 363 * flexiflags1[3:0] - Not used for flag programming 364 * flexiflags2[7:0] - Tunnel and VLAN types 365 * 2 invalid fields in last index 366 */ 367 switch (prof_id) { 368 /* Rx flex flags are currently programmed for the NIC profiles only. 369 * Different flag bit programming configurations can be added per 370 * profile as needed. 371 */ 372 case ICE_RXDID_FLEX_NIC: 373 case ICE_RXDID_FLEX_NIC_2: 374 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG, 375 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI, 376 ICE_FLG_FIN, idx++); 377 /* flex flag 1 is not used for flexi-flag programming, skipping 378 * these four FLG64 bits. 379 */ 380 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST, 381 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++); 382 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI, 383 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100, 384 ICE_FLG_EVLAN_x9100, idx++); 385 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100, 386 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC, 387 ICE_FLG_TNL0, idx++); 388 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2, 389 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx); 390 break; 391 392 default: 393 ice_debug(hw, ICE_DBG_INIT, 394 "Flag programming for profile ID %d not supported\n", 395 prof_id); 396 } 397 } 398 399 /** 400 * ice_init_flex_flds 401 * @hw: pointer to the hardware structure 402 * @prof_id: Rx Descriptor Builder profile ID 403 * 404 * Function to initialize flex descriptors 405 */ 406 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id) 407 { 408 enum ice_flex_rx_mdid mdid; 409 410 switch (prof_id) { 411 case ICE_RXDID_FLEX_NIC: 412 case ICE_RXDID_FLEX_NIC_2: 413 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_LOW, 0); 414 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_HIGH, 1); 415 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_FLOW_ID_LOWER, 2); 416 417 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ? 418 ICE_RX_MDID_SRC_VSI : ICE_RX_MDID_FLOW_ID_HIGH; 419 420 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3); 421 422 ice_init_flex_flags(hw, prof_id); 423 break; 424 425 default: 426 ice_debug(hw, ICE_DBG_INIT, 427 "Field init for profile ID %d not supported\n", 428 prof_id); 429 } 430 } 431 432 /** 433 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 434 * @hw: pointer to the HW struct 435 */ 436 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 437 { 438 struct ice_switch_info *sw; 439 440 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 441 sizeof(*hw->switch_info), GFP_KERNEL); 442 sw = hw->switch_info; 443 444 if (!sw) 445 return ICE_ERR_NO_MEMORY; 446 447 INIT_LIST_HEAD(&sw->vsi_list_map_head); 448 449 return ice_init_def_sw_recp(hw); 450 } 451 452 /** 453 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 454 * @hw: pointer to the HW struct 455 */ 456 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 457 { 458 struct ice_switch_info *sw = hw->switch_info; 459 struct ice_vsi_list_map_info *v_pos_map; 460 struct ice_vsi_list_map_info *v_tmp_map; 461 struct ice_sw_recipe *recps; 462 u8 i; 463 464 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 465 list_entry) { 466 list_del(&v_pos_map->list_entry); 467 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 468 } 469 recps = hw->switch_info->recp_list; 470 for (i = 0; i < ICE_SW_LKUP_LAST; i++) { 471 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 472 473 recps[i].root_rid = i; 474 mutex_destroy(&recps[i].filt_rule_lock); 475 list_for_each_entry_safe(lst_itr, tmp_entry, 476 &recps[i].filt_rules, list_entry) { 477 list_del(&lst_itr->list_entry); 478 devm_kfree(ice_hw_to_dev(hw), lst_itr); 479 } 480 } 481 ice_rm_all_sw_replay_rule_info(hw); 482 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 483 devm_kfree(ice_hw_to_dev(hw), sw); 484 } 485 486 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \ 487 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry))) 488 #define ICE_FW_LOG_DESC_SIZE_MAX \ 489 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX) 490 491 /** 492 * ice_get_fw_log_cfg - get FW logging configuration 493 * @hw: pointer to the HW struct 494 */ 495 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw) 496 { 497 struct ice_aqc_fw_logging_data *config; 498 struct ice_aq_desc desc; 499 enum ice_status status; 500 u16 size; 501 502 size = ICE_FW_LOG_DESC_SIZE_MAX; 503 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL); 504 if (!config) 505 return ICE_ERR_NO_MEMORY; 506 507 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 508 509 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_BUF); 510 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 511 512 status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 513 if (!status) { 514 u16 i; 515 516 /* Save FW logging information into the HW structure */ 517 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 518 u16 v, m, flgs; 519 520 v = le16_to_cpu(config->entry[i]); 521 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 522 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 523 524 if (m < ICE_AQC_FW_LOG_ID_MAX) 525 hw->fw_log.evnts[m].cur = flgs; 526 } 527 } 528 529 devm_kfree(ice_hw_to_dev(hw), config); 530 531 return status; 532 } 533 534 /** 535 * ice_cfg_fw_log - configure FW logging 536 * @hw: pointer to the HW struct 537 * @enable: enable certain FW logging events if true, disable all if false 538 * 539 * This function enables/disables the FW logging via Rx CQ events and a UART 540 * port based on predetermined configurations. FW logging via the Rx CQ can be 541 * enabled/disabled for individual PF's. However, FW logging via the UART can 542 * only be enabled/disabled for all PFs on the same device. 543 * 544 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 545 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 546 * before initializing the device. 547 * 548 * When re/configuring FW logging, callers need to update the "cfg" elements of 549 * the hw->fw_log.evnts array with the desired logging event configurations for 550 * modules of interest. When disabling FW logging completely, the callers can 551 * just pass false in the "enable" parameter. On completion, the function will 552 * update the "cur" element of the hw->fw_log.evnts array with the resulting 553 * logging event configurations of the modules that are being re/configured. FW 554 * logging modules that are not part of a reconfiguration operation retain their 555 * previous states. 556 * 557 * Before resetting the device, it is recommended that the driver disables FW 558 * logging before shutting down the control queue. When disabling FW logging 559 * ("enable" = false), the latest configurations of FW logging events stored in 560 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 561 * a device reset. 562 * 563 * When enabling FW logging to emit log messages via the Rx CQ during the 564 * device's initialization phase, a mechanism alternative to interrupt handlers 565 * needs to be used to extract FW log messages from the Rx CQ periodically and 566 * to prevent the Rx CQ from being full and stalling other types of control 567 * messages from FW to SW. Interrupts are typically disabled during the device's 568 * initialization phase. 569 */ 570 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable) 571 { 572 struct ice_aqc_fw_logging_data *data = NULL; 573 struct ice_aqc_fw_logging *cmd; 574 enum ice_status status = 0; 575 u16 i, chgs = 0, len = 0; 576 struct ice_aq_desc desc; 577 u8 actv_evnts = 0; 578 void *buf = NULL; 579 580 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 581 return 0; 582 583 /* Disable FW logging only when the control queue is still responsive */ 584 if (!enable && 585 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 586 return 0; 587 588 /* Get current FW log settings */ 589 status = ice_get_fw_log_cfg(hw); 590 if (status) 591 return status; 592 593 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 594 cmd = &desc.params.fw_logging; 595 596 /* Indicate which controls are valid */ 597 if (hw->fw_log.cq_en) 598 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 599 600 if (hw->fw_log.uart_en) 601 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 602 603 if (enable) { 604 /* Fill in an array of entries with FW logging modules and 605 * logging events being reconfigured. 606 */ 607 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 608 u16 val; 609 610 /* Keep track of enabled event types */ 611 actv_evnts |= hw->fw_log.evnts[i].cfg; 612 613 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 614 continue; 615 616 if (!data) { 617 data = devm_kzalloc(ice_hw_to_dev(hw), 618 ICE_FW_LOG_DESC_SIZE_MAX, 619 GFP_KERNEL); 620 if (!data) 621 return ICE_ERR_NO_MEMORY; 622 } 623 624 val = i << ICE_AQC_FW_LOG_ID_S; 625 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 626 data->entry[chgs++] = cpu_to_le16(val); 627 } 628 629 /* Only enable FW logging if at least one module is specified. 630 * If FW logging is currently enabled but all modules are not 631 * enabled to emit log messages, disable FW logging altogether. 632 */ 633 if (actv_evnts) { 634 /* Leave if there is effectively no change */ 635 if (!chgs) 636 goto out; 637 638 if (hw->fw_log.cq_en) 639 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 640 641 if (hw->fw_log.uart_en) 642 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 643 644 buf = data; 645 len = ICE_FW_LOG_DESC_SIZE(chgs); 646 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 647 } 648 } 649 650 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 651 if (!status) { 652 /* Update the current configuration to reflect events enabled. 653 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 654 * logging mode is enabled for the device. They do not reflect 655 * actual modules being enabled to emit log messages. So, their 656 * values remain unchanged even when all modules are disabled. 657 */ 658 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 659 660 hw->fw_log.actv_evnts = actv_evnts; 661 for (i = 0; i < cnt; i++) { 662 u16 v, m; 663 664 if (!enable) { 665 /* When disabling all FW logging events as part 666 * of device's de-initialization, the original 667 * configurations are retained, and can be used 668 * to reconfigure FW logging later if the device 669 * is re-initialized. 670 */ 671 hw->fw_log.evnts[i].cur = 0; 672 continue; 673 } 674 675 v = le16_to_cpu(data->entry[i]); 676 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 677 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 678 } 679 } 680 681 out: 682 if (data) 683 devm_kfree(ice_hw_to_dev(hw), data); 684 685 return status; 686 } 687 688 /** 689 * ice_output_fw_log 690 * @hw: pointer to the HW struct 691 * @desc: pointer to the AQ message descriptor 692 * @buf: pointer to the buffer accompanying the AQ message 693 * 694 * Formats a FW Log message and outputs it via the standard driver logs. 695 */ 696 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 697 { 698 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 699 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 700 le16_to_cpu(desc->datalen)); 701 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 702 } 703 704 /** 705 * ice_get_itr_intrl_gran - determine int/intrl granularity 706 * @hw: pointer to the HW struct 707 * 708 * Determines the ITR/intrl granularities based on the maximum aggregate 709 * bandwidth according to the device's configuration during power-on. 710 */ 711 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 712 { 713 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 714 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 715 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 716 717 switch (max_agg_bw) { 718 case ICE_MAX_AGG_BW_200G: 719 case ICE_MAX_AGG_BW_100G: 720 case ICE_MAX_AGG_BW_50G: 721 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 722 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 723 break; 724 case ICE_MAX_AGG_BW_25G: 725 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 726 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 727 break; 728 } 729 } 730 731 /** 732 * ice_init_hw - main hardware initialization routine 733 * @hw: pointer to the hardware structure 734 */ 735 enum ice_status ice_init_hw(struct ice_hw *hw) 736 { 737 struct ice_aqc_get_phy_caps_data *pcaps; 738 enum ice_status status; 739 u16 mac_buf_len; 740 void *mac_buf; 741 742 /* Set MAC type based on DeviceID */ 743 status = ice_set_mac_type(hw); 744 if (status) 745 return status; 746 747 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 748 PF_FUNC_RID_FUNC_NUM_M) >> 749 PF_FUNC_RID_FUNC_NUM_S; 750 751 status = ice_reset(hw, ICE_RESET_PFR); 752 if (status) 753 return status; 754 755 ice_get_itr_intrl_gran(hw); 756 757 status = ice_create_all_ctrlq(hw); 758 if (status) 759 goto err_unroll_cqinit; 760 761 /* Enable FW logging. Not fatal if this fails. */ 762 status = ice_cfg_fw_log(hw, true); 763 if (status) 764 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 765 766 status = ice_clear_pf_cfg(hw); 767 if (status) 768 goto err_unroll_cqinit; 769 770 ice_clear_pxe_mode(hw); 771 772 status = ice_init_nvm(hw); 773 if (status) 774 goto err_unroll_cqinit; 775 776 status = ice_get_caps(hw); 777 if (status) 778 goto err_unroll_cqinit; 779 780 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 781 sizeof(*hw->port_info), GFP_KERNEL); 782 if (!hw->port_info) { 783 status = ICE_ERR_NO_MEMORY; 784 goto err_unroll_cqinit; 785 } 786 787 /* set the back pointer to HW */ 788 hw->port_info->hw = hw; 789 790 /* Initialize port_info struct with switch configuration data */ 791 status = ice_get_initial_sw_cfg(hw); 792 if (status) 793 goto err_unroll_alloc; 794 795 hw->evb_veb = true; 796 797 /* Query the allocated resources for Tx scheduler */ 798 status = ice_sched_query_res_alloc(hw); 799 if (status) { 800 ice_debug(hw, ICE_DBG_SCHED, 801 "Failed to get scheduler allocated resources\n"); 802 goto err_unroll_alloc; 803 } 804 805 /* Initialize port_info struct with scheduler data */ 806 status = ice_sched_init_port(hw->port_info); 807 if (status) 808 goto err_unroll_sched; 809 810 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 811 if (!pcaps) { 812 status = ICE_ERR_NO_MEMORY; 813 goto err_unroll_sched; 814 } 815 816 /* Initialize port_info struct with PHY capabilities */ 817 status = ice_aq_get_phy_caps(hw->port_info, false, 818 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); 819 devm_kfree(ice_hw_to_dev(hw), pcaps); 820 if (status) 821 goto err_unroll_sched; 822 823 /* Initialize port_info struct with link information */ 824 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 825 if (status) 826 goto err_unroll_sched; 827 828 /* need a valid SW entry point to build a Tx tree */ 829 if (!hw->sw_entry_point_layer) { 830 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 831 status = ICE_ERR_CFG; 832 goto err_unroll_sched; 833 } 834 INIT_LIST_HEAD(&hw->agg_list); 835 836 status = ice_init_fltr_mgmt_struct(hw); 837 if (status) 838 goto err_unroll_sched; 839 840 ice_dev_onetime_setup(hw); 841 842 /* Get MAC information */ 843 /* A single port can report up to two (LAN and WoL) addresses */ 844 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 845 sizeof(struct ice_aqc_manage_mac_read_resp), 846 GFP_KERNEL); 847 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 848 849 if (!mac_buf) { 850 status = ICE_ERR_NO_MEMORY; 851 goto err_unroll_fltr_mgmt_struct; 852 } 853 854 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 855 devm_kfree(ice_hw_to_dev(hw), mac_buf); 856 857 if (status) 858 goto err_unroll_fltr_mgmt_struct; 859 860 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC); 861 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2); 862 863 return 0; 864 865 err_unroll_fltr_mgmt_struct: 866 ice_cleanup_fltr_mgmt_struct(hw); 867 err_unroll_sched: 868 ice_sched_cleanup_all(hw); 869 err_unroll_alloc: 870 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 871 err_unroll_cqinit: 872 ice_destroy_all_ctrlq(hw); 873 return status; 874 } 875 876 /** 877 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 878 * @hw: pointer to the hardware structure 879 * 880 * This should be called only during nominal operation, not as a result of 881 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 882 * applicable initializations if it fails for any reason. 883 */ 884 void ice_deinit_hw(struct ice_hw *hw) 885 { 886 ice_cleanup_fltr_mgmt_struct(hw); 887 888 ice_sched_cleanup_all(hw); 889 ice_sched_clear_agg(hw); 890 891 if (hw->port_info) { 892 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 893 hw->port_info = NULL; 894 } 895 896 /* Attempt to disable FW logging before shutting down control queues */ 897 ice_cfg_fw_log(hw, false); 898 ice_destroy_all_ctrlq(hw); 899 900 /* Clear VSI contexts if not already cleared */ 901 ice_clear_all_vsi_ctx(hw); 902 } 903 904 /** 905 * ice_check_reset - Check to see if a global reset is complete 906 * @hw: pointer to the hardware structure 907 */ 908 enum ice_status ice_check_reset(struct ice_hw *hw) 909 { 910 u32 cnt, reg = 0, grst_delay; 911 912 /* Poll for Device Active state in case a recent CORER, GLOBR, 913 * or EMPR has occurred. The grst delay value is in 100ms units. 914 * Add 1sec for outstanding AQ commands that can take a long time. 915 */ 916 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 917 GLGEN_RSTCTL_GRSTDEL_S) + 10; 918 919 for (cnt = 0; cnt < grst_delay; cnt++) { 920 mdelay(100); 921 reg = rd32(hw, GLGEN_RSTAT); 922 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 923 break; 924 } 925 926 if (cnt == grst_delay) { 927 ice_debug(hw, ICE_DBG_INIT, 928 "Global reset polling failed to complete.\n"); 929 return ICE_ERR_RESET_FAILED; 930 } 931 932 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \ 933 GLNVM_ULD_GLOBR_DONE_M) 934 935 /* Device is Active; check Global Reset processes are done */ 936 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 937 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK; 938 if (reg == ICE_RESET_DONE_MASK) { 939 ice_debug(hw, ICE_DBG_INIT, 940 "Global reset processes done. %d\n", cnt); 941 break; 942 } 943 mdelay(10); 944 } 945 946 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 947 ice_debug(hw, ICE_DBG_INIT, 948 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 949 reg); 950 return ICE_ERR_RESET_FAILED; 951 } 952 953 return 0; 954 } 955 956 /** 957 * ice_pf_reset - Reset the PF 958 * @hw: pointer to the hardware structure 959 * 960 * If a global reset has been triggered, this function checks 961 * for its completion and then issues the PF reset 962 */ 963 static enum ice_status ice_pf_reset(struct ice_hw *hw) 964 { 965 u32 cnt, reg; 966 967 /* If at function entry a global reset was already in progress, i.e. 968 * state is not 'device active' or any of the reset done bits are not 969 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 970 * global reset is done. 971 */ 972 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 973 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 974 /* poll on global reset currently in progress until done */ 975 if (ice_check_reset(hw)) 976 return ICE_ERR_RESET_FAILED; 977 978 return 0; 979 } 980 981 /* Reset the PF */ 982 reg = rd32(hw, PFGEN_CTRL); 983 984 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 985 986 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 987 reg = rd32(hw, PFGEN_CTRL); 988 if (!(reg & PFGEN_CTRL_PFSWR_M)) 989 break; 990 991 mdelay(1); 992 } 993 994 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 995 ice_debug(hw, ICE_DBG_INIT, 996 "PF reset polling failed to complete.\n"); 997 return ICE_ERR_RESET_FAILED; 998 } 999 1000 return 0; 1001 } 1002 1003 /** 1004 * ice_reset - Perform different types of reset 1005 * @hw: pointer to the hardware structure 1006 * @req: reset request 1007 * 1008 * This function triggers a reset as specified by the req parameter. 1009 * 1010 * Note: 1011 * If anything other than a PF reset is triggered, PXE mode is restored. 1012 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1013 * interface has been restored in the rebuild flow. 1014 */ 1015 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1016 { 1017 u32 val = 0; 1018 1019 switch (req) { 1020 case ICE_RESET_PFR: 1021 return ice_pf_reset(hw); 1022 case ICE_RESET_CORER: 1023 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1024 val = GLGEN_RTRIG_CORER_M; 1025 break; 1026 case ICE_RESET_GLOBR: 1027 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1028 val = GLGEN_RTRIG_GLOBR_M; 1029 break; 1030 default: 1031 return ICE_ERR_PARAM; 1032 } 1033 1034 val |= rd32(hw, GLGEN_RTRIG); 1035 wr32(hw, GLGEN_RTRIG, val); 1036 ice_flush(hw); 1037 1038 /* wait for the FW to be ready */ 1039 return ice_check_reset(hw); 1040 } 1041 1042 /** 1043 * ice_copy_rxq_ctx_to_hw 1044 * @hw: pointer to the hardware structure 1045 * @ice_rxq_ctx: pointer to the rxq context 1046 * @rxq_index: the index of the Rx queue 1047 * 1048 * Copies rxq context from dense structure to HW register space 1049 */ 1050 static enum ice_status 1051 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1052 { 1053 u8 i; 1054 1055 if (!ice_rxq_ctx) 1056 return ICE_ERR_BAD_PTR; 1057 1058 if (rxq_index > QRX_CTRL_MAX_INDEX) 1059 return ICE_ERR_PARAM; 1060 1061 /* Copy each dword separately to HW */ 1062 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1063 wr32(hw, QRX_CONTEXT(i, rxq_index), 1064 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1065 1066 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1067 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1068 } 1069 1070 return 0; 1071 } 1072 1073 /* LAN Rx Queue Context */ 1074 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1075 /* Field Width LSB */ 1076 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1077 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1078 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1079 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1080 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1081 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1082 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1083 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1084 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1085 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1086 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1087 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1088 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1089 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1090 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1091 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1092 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1093 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1094 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1095 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1096 { 0 } 1097 }; 1098 1099 /** 1100 * ice_write_rxq_ctx 1101 * @hw: pointer to the hardware structure 1102 * @rlan_ctx: pointer to the rxq context 1103 * @rxq_index: the index of the Rx queue 1104 * 1105 * Converts rxq context from sparse to dense structure and then writes 1106 * it to HW register space and enables the hardware to prefetch descriptors 1107 * instead of only fetching them on demand 1108 */ 1109 enum ice_status 1110 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1111 u32 rxq_index) 1112 { 1113 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1114 1115 if (!rlan_ctx) 1116 return ICE_ERR_BAD_PTR; 1117 1118 rlan_ctx->prefena = 1; 1119 1120 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1121 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1122 } 1123 1124 /* LAN Tx Queue Context */ 1125 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1126 /* Field Width LSB */ 1127 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1128 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1129 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1130 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1131 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1132 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1133 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1134 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1135 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1136 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1137 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1138 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1139 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1140 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1141 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1142 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1143 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1144 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1145 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1146 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1147 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1148 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1149 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1150 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1151 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1152 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1153 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1154 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1155 { 0 } 1156 }; 1157 1158 /** 1159 * ice_debug_cq 1160 * @hw: pointer to the hardware structure 1161 * @mask: debug mask 1162 * @desc: pointer to control queue descriptor 1163 * @buf: pointer to command buffer 1164 * @buf_len: max length of buf 1165 * 1166 * Dumps debug log about control command with descriptor contents. 1167 */ 1168 void 1169 ice_debug_cq(struct ice_hw *hw, u32 __maybe_unused mask, void *desc, void *buf, 1170 u16 buf_len) 1171 { 1172 struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc; 1173 u16 len; 1174 1175 #ifndef CONFIG_DYNAMIC_DEBUG 1176 if (!(mask & hw->debug_mask)) 1177 return; 1178 #endif 1179 1180 if (!desc) 1181 return; 1182 1183 len = le16_to_cpu(cq_desc->datalen); 1184 1185 ice_debug(hw, mask, 1186 "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 1187 le16_to_cpu(cq_desc->opcode), 1188 le16_to_cpu(cq_desc->flags), 1189 le16_to_cpu(cq_desc->datalen), le16_to_cpu(cq_desc->retval)); 1190 ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 1191 le32_to_cpu(cq_desc->cookie_high), 1192 le32_to_cpu(cq_desc->cookie_low)); 1193 ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 1194 le32_to_cpu(cq_desc->params.generic.param0), 1195 le32_to_cpu(cq_desc->params.generic.param1)); 1196 ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 1197 le32_to_cpu(cq_desc->params.generic.addr_high), 1198 le32_to_cpu(cq_desc->params.generic.addr_low)); 1199 if (buf && cq_desc->datalen != 0) { 1200 ice_debug(hw, mask, "Buffer:\n"); 1201 if (buf_len < len) 1202 len = buf_len; 1203 1204 ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len); 1205 } 1206 } 1207 1208 /* FW Admin Queue command wrappers */ 1209 1210 /** 1211 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1212 * @hw: pointer to the HW struct 1213 * @desc: descriptor describing the command 1214 * @buf: buffer to use for indirect commands (NULL for direct commands) 1215 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1216 * @cd: pointer to command details structure 1217 * 1218 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1219 */ 1220 enum ice_status 1221 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1222 u16 buf_size, struct ice_sq_cd *cd) 1223 { 1224 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); 1225 } 1226 1227 /** 1228 * ice_aq_get_fw_ver 1229 * @hw: pointer to the HW struct 1230 * @cd: pointer to command details structure or NULL 1231 * 1232 * Get the firmware version (0x0001) from the admin queue commands 1233 */ 1234 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1235 { 1236 struct ice_aqc_get_ver *resp; 1237 struct ice_aq_desc desc; 1238 enum ice_status status; 1239 1240 resp = &desc.params.get_ver; 1241 1242 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1243 1244 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1245 1246 if (!status) { 1247 hw->fw_branch = resp->fw_branch; 1248 hw->fw_maj_ver = resp->fw_major; 1249 hw->fw_min_ver = resp->fw_minor; 1250 hw->fw_patch = resp->fw_patch; 1251 hw->fw_build = le32_to_cpu(resp->fw_build); 1252 hw->api_branch = resp->api_branch; 1253 hw->api_maj_ver = resp->api_major; 1254 hw->api_min_ver = resp->api_minor; 1255 hw->api_patch = resp->api_patch; 1256 } 1257 1258 return status; 1259 } 1260 1261 /** 1262 * ice_aq_q_shutdown 1263 * @hw: pointer to the HW struct 1264 * @unloading: is the driver unloading itself 1265 * 1266 * Tell the Firmware that we're shutting down the AdminQ and whether 1267 * or not the driver is unloading as well (0x0003). 1268 */ 1269 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1270 { 1271 struct ice_aqc_q_shutdown *cmd; 1272 struct ice_aq_desc desc; 1273 1274 cmd = &desc.params.q_shutdown; 1275 1276 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1277 1278 if (unloading) 1279 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1280 1281 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1282 } 1283 1284 /** 1285 * ice_aq_req_res 1286 * @hw: pointer to the HW struct 1287 * @res: resource ID 1288 * @access: access type 1289 * @sdp_number: resource number 1290 * @timeout: the maximum time in ms that the driver may hold the resource 1291 * @cd: pointer to command details structure or NULL 1292 * 1293 * Requests common resource using the admin queue commands (0x0008). 1294 * When attempting to acquire the Global Config Lock, the driver can 1295 * learn of three states: 1296 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1297 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1298 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1299 * successfully downloaded the package; the driver does 1300 * not have to download the package and can continue 1301 * loading 1302 * 1303 * Note that if the caller is in an acquire lock, perform action, release lock 1304 * phase of operation, it is possible that the FW may detect a timeout and issue 1305 * a CORER. In this case, the driver will receive a CORER interrupt and will 1306 * have to determine its cause. The calling thread that is handling this flow 1307 * will likely get an error propagated back to it indicating the Download 1308 * Package, Update Package or the Release Resource AQ commands timed out. 1309 */ 1310 static enum ice_status 1311 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1312 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1313 struct ice_sq_cd *cd) 1314 { 1315 struct ice_aqc_req_res *cmd_resp; 1316 struct ice_aq_desc desc; 1317 enum ice_status status; 1318 1319 cmd_resp = &desc.params.res_owner; 1320 1321 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1322 1323 cmd_resp->res_id = cpu_to_le16(res); 1324 cmd_resp->access_type = cpu_to_le16(access); 1325 cmd_resp->res_number = cpu_to_le32(sdp_number); 1326 cmd_resp->timeout = cpu_to_le32(*timeout); 1327 *timeout = 0; 1328 1329 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1330 1331 /* The completion specifies the maximum time in ms that the driver 1332 * may hold the resource in the Timeout field. 1333 */ 1334 1335 /* Global config lock response utilizes an additional status field. 1336 * 1337 * If the Global config lock resource is held by some other driver, the 1338 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1339 * and the timeout field indicates the maximum time the current owner 1340 * of the resource has to free it. 1341 */ 1342 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1343 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1344 *timeout = le32_to_cpu(cmd_resp->timeout); 1345 return 0; 1346 } else if (le16_to_cpu(cmd_resp->status) == 1347 ICE_AQ_RES_GLBL_IN_PROG) { 1348 *timeout = le32_to_cpu(cmd_resp->timeout); 1349 return ICE_ERR_AQ_ERROR; 1350 } else if (le16_to_cpu(cmd_resp->status) == 1351 ICE_AQ_RES_GLBL_DONE) { 1352 return ICE_ERR_AQ_NO_WORK; 1353 } 1354 1355 /* invalid FW response, force a timeout immediately */ 1356 *timeout = 0; 1357 return ICE_ERR_AQ_ERROR; 1358 } 1359 1360 /* If the resource is held by some other driver, the command completes 1361 * with a busy return value and the timeout field indicates the maximum 1362 * time the current owner of the resource has to free it. 1363 */ 1364 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1365 *timeout = le32_to_cpu(cmd_resp->timeout); 1366 1367 return status; 1368 } 1369 1370 /** 1371 * ice_aq_release_res 1372 * @hw: pointer to the HW struct 1373 * @res: resource ID 1374 * @sdp_number: resource number 1375 * @cd: pointer to command details structure or NULL 1376 * 1377 * release common resource using the admin queue commands (0x0009) 1378 */ 1379 static enum ice_status 1380 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1381 struct ice_sq_cd *cd) 1382 { 1383 struct ice_aqc_req_res *cmd; 1384 struct ice_aq_desc desc; 1385 1386 cmd = &desc.params.res_owner; 1387 1388 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1389 1390 cmd->res_id = cpu_to_le16(res); 1391 cmd->res_number = cpu_to_le32(sdp_number); 1392 1393 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1394 } 1395 1396 /** 1397 * ice_acquire_res 1398 * @hw: pointer to the HW structure 1399 * @res: resource ID 1400 * @access: access type (read or write) 1401 * @timeout: timeout in milliseconds 1402 * 1403 * This function will attempt to acquire the ownership of a resource. 1404 */ 1405 enum ice_status 1406 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1407 enum ice_aq_res_access_type access, u32 timeout) 1408 { 1409 #define ICE_RES_POLLING_DELAY_MS 10 1410 u32 delay = ICE_RES_POLLING_DELAY_MS; 1411 u32 time_left = timeout; 1412 enum ice_status status; 1413 1414 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1415 1416 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1417 * previously acquired the resource and performed any necessary updates; 1418 * in this case the caller does not obtain the resource and has no 1419 * further work to do. 1420 */ 1421 if (status == ICE_ERR_AQ_NO_WORK) 1422 goto ice_acquire_res_exit; 1423 1424 if (status) 1425 ice_debug(hw, ICE_DBG_RES, 1426 "resource %d acquire type %d failed.\n", res, access); 1427 1428 /* If necessary, poll until the current lock owner timeouts */ 1429 timeout = time_left; 1430 while (status && timeout && time_left) { 1431 mdelay(delay); 1432 timeout = (timeout > delay) ? timeout - delay : 0; 1433 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1434 1435 if (status == ICE_ERR_AQ_NO_WORK) 1436 /* lock free, but no work to do */ 1437 break; 1438 1439 if (!status) 1440 /* lock acquired */ 1441 break; 1442 } 1443 if (status && status != ICE_ERR_AQ_NO_WORK) 1444 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1445 1446 ice_acquire_res_exit: 1447 if (status == ICE_ERR_AQ_NO_WORK) { 1448 if (access == ICE_RES_WRITE) 1449 ice_debug(hw, ICE_DBG_RES, 1450 "resource indicates no work to do.\n"); 1451 else 1452 ice_debug(hw, ICE_DBG_RES, 1453 "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1454 } 1455 return status; 1456 } 1457 1458 /** 1459 * ice_release_res 1460 * @hw: pointer to the HW structure 1461 * @res: resource ID 1462 * 1463 * This function will release a resource using the proper Admin Command. 1464 */ 1465 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1466 { 1467 enum ice_status status; 1468 u32 total_delay = 0; 1469 1470 status = ice_aq_release_res(hw, res, 0, NULL); 1471 1472 /* there are some rare cases when trying to release the resource 1473 * results in an admin queue timeout, so handle them correctly 1474 */ 1475 while ((status == ICE_ERR_AQ_TIMEOUT) && 1476 (total_delay < hw->adminq.sq_cmd_timeout)) { 1477 mdelay(1); 1478 status = ice_aq_release_res(hw, res, 0, NULL); 1479 total_delay++; 1480 } 1481 } 1482 1483 /** 1484 * ice_get_num_per_func - determine number of resources per PF 1485 * @hw: pointer to the HW structure 1486 * @max: value to be evenly split between each PF 1487 * 1488 * Determine the number of valid functions by going through the bitmap returned 1489 * from parsing capabilities and use this to calculate the number of resources 1490 * per PF based on the max value passed in. 1491 */ 1492 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1493 { 1494 u8 funcs; 1495 1496 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1497 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 1498 ICE_CAPS_VALID_FUNCS_M); 1499 1500 if (!funcs) 1501 return 0; 1502 1503 return max / funcs; 1504 } 1505 1506 /** 1507 * ice_parse_caps - parse function/device capabilities 1508 * @hw: pointer to the HW struct 1509 * @buf: pointer to a buffer containing function/device capability records 1510 * @cap_count: number of capability records in the list 1511 * @opc: type of capabilities list to parse 1512 * 1513 * Helper function to parse function(0x000a)/device(0x000b) capabilities list. 1514 */ 1515 static void 1516 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, 1517 enum ice_adminq_opc opc) 1518 { 1519 struct ice_aqc_list_caps_elem *cap_resp; 1520 struct ice_hw_func_caps *func_p = NULL; 1521 struct ice_hw_dev_caps *dev_p = NULL; 1522 struct ice_hw_common_caps *caps; 1523 char const *prefix; 1524 u32 i; 1525 1526 if (!buf) 1527 return; 1528 1529 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 1530 1531 if (opc == ice_aqc_opc_list_dev_caps) { 1532 dev_p = &hw->dev_caps; 1533 caps = &dev_p->common_cap; 1534 prefix = "dev cap"; 1535 } else if (opc == ice_aqc_opc_list_func_caps) { 1536 func_p = &hw->func_caps; 1537 caps = &func_p->common_cap; 1538 prefix = "func cap"; 1539 } else { 1540 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n"); 1541 return; 1542 } 1543 1544 for (i = 0; caps && i < cap_count; i++, cap_resp++) { 1545 u32 logical_id = le32_to_cpu(cap_resp->logical_id); 1546 u32 phys_id = le32_to_cpu(cap_resp->phys_id); 1547 u32 number = le32_to_cpu(cap_resp->number); 1548 u16 cap = le16_to_cpu(cap_resp->cap); 1549 1550 switch (cap) { 1551 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1552 caps->valid_functions = number; 1553 ice_debug(hw, ICE_DBG_INIT, 1554 "%s: valid_functions (bitmap) = %d\n", prefix, 1555 caps->valid_functions); 1556 break; 1557 case ICE_AQC_CAPS_SRIOV: 1558 caps->sr_iov_1_1 = (number == 1); 1559 ice_debug(hw, ICE_DBG_INIT, 1560 "%s: sr_iov_1_1 = %d\n", prefix, 1561 caps->sr_iov_1_1); 1562 break; 1563 case ICE_AQC_CAPS_VF: 1564 if (dev_p) { 1565 dev_p->num_vfs_exposed = number; 1566 ice_debug(hw, ICE_DBG_INIT, 1567 "%s: num_vfs_exposed = %d\n", prefix, 1568 dev_p->num_vfs_exposed); 1569 } else if (func_p) { 1570 func_p->num_allocd_vfs = number; 1571 func_p->vf_base_id = logical_id; 1572 ice_debug(hw, ICE_DBG_INIT, 1573 "%s: num_allocd_vfs = %d\n", prefix, 1574 func_p->num_allocd_vfs); 1575 ice_debug(hw, ICE_DBG_INIT, 1576 "%s: vf_base_id = %d\n", prefix, 1577 func_p->vf_base_id); 1578 } 1579 break; 1580 case ICE_AQC_CAPS_VSI: 1581 if (dev_p) { 1582 dev_p->num_vsi_allocd_to_host = number; 1583 ice_debug(hw, ICE_DBG_INIT, 1584 "%s: num_vsi_allocd_to_host = %d\n", 1585 prefix, 1586 dev_p->num_vsi_allocd_to_host); 1587 } else if (func_p) { 1588 func_p->guar_num_vsi = 1589 ice_get_num_per_func(hw, ICE_MAX_VSI); 1590 ice_debug(hw, ICE_DBG_INIT, 1591 "%s: guar_num_vsi (fw) = %d\n", 1592 prefix, number); 1593 ice_debug(hw, ICE_DBG_INIT, 1594 "%s: guar_num_vsi = %d\n", 1595 prefix, func_p->guar_num_vsi); 1596 } 1597 break; 1598 case ICE_AQC_CAPS_DCB: 1599 caps->dcb = (number == 1); 1600 caps->active_tc_bitmap = logical_id; 1601 caps->maxtc = phys_id; 1602 ice_debug(hw, ICE_DBG_INIT, 1603 "%s: dcb = %d\n", prefix, caps->dcb); 1604 ice_debug(hw, ICE_DBG_INIT, 1605 "%s: active_tc_bitmap = %d\n", prefix, 1606 caps->active_tc_bitmap); 1607 ice_debug(hw, ICE_DBG_INIT, 1608 "%s: maxtc = %d\n", prefix, caps->maxtc); 1609 break; 1610 case ICE_AQC_CAPS_RSS: 1611 caps->rss_table_size = number; 1612 caps->rss_table_entry_width = logical_id; 1613 ice_debug(hw, ICE_DBG_INIT, 1614 "%s: rss_table_size = %d\n", prefix, 1615 caps->rss_table_size); 1616 ice_debug(hw, ICE_DBG_INIT, 1617 "%s: rss_table_entry_width = %d\n", prefix, 1618 caps->rss_table_entry_width); 1619 break; 1620 case ICE_AQC_CAPS_RXQS: 1621 caps->num_rxq = number; 1622 caps->rxq_first_id = phys_id; 1623 ice_debug(hw, ICE_DBG_INIT, 1624 "%s: num_rxq = %d\n", prefix, 1625 caps->num_rxq); 1626 ice_debug(hw, ICE_DBG_INIT, 1627 "%s: rxq_first_id = %d\n", prefix, 1628 caps->rxq_first_id); 1629 break; 1630 case ICE_AQC_CAPS_TXQS: 1631 caps->num_txq = number; 1632 caps->txq_first_id = phys_id; 1633 ice_debug(hw, ICE_DBG_INIT, 1634 "%s: num_txq = %d\n", prefix, 1635 caps->num_txq); 1636 ice_debug(hw, ICE_DBG_INIT, 1637 "%s: txq_first_id = %d\n", prefix, 1638 caps->txq_first_id); 1639 break; 1640 case ICE_AQC_CAPS_MSIX: 1641 caps->num_msix_vectors = number; 1642 caps->msix_vector_first_id = phys_id; 1643 ice_debug(hw, ICE_DBG_INIT, 1644 "%s: num_msix_vectors = %d\n", prefix, 1645 caps->num_msix_vectors); 1646 ice_debug(hw, ICE_DBG_INIT, 1647 "%s: msix_vector_first_id = %d\n", prefix, 1648 caps->msix_vector_first_id); 1649 break; 1650 case ICE_AQC_CAPS_MAX_MTU: 1651 caps->max_mtu = number; 1652 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 1653 prefix, caps->max_mtu); 1654 break; 1655 default: 1656 ice_debug(hw, ICE_DBG_INIT, 1657 "%s: unknown capability[%d]: 0x%x\n", prefix, 1658 i, cap); 1659 break; 1660 } 1661 } 1662 } 1663 1664 /** 1665 * ice_aq_discover_caps - query function/device capabilities 1666 * @hw: pointer to the HW struct 1667 * @buf: a virtual buffer to hold the capabilities 1668 * @buf_size: Size of the virtual buffer 1669 * @cap_count: cap count needed if AQ err==ENOMEM 1670 * @opc: capabilities type to discover - pass in the command opcode 1671 * @cd: pointer to command details structure or NULL 1672 * 1673 * Get the function(0x000a)/device(0x000b) capabilities description from 1674 * the firmware. 1675 */ 1676 static enum ice_status 1677 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 1678 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1679 { 1680 struct ice_aqc_list_caps *cmd; 1681 struct ice_aq_desc desc; 1682 enum ice_status status; 1683 1684 cmd = &desc.params.get_cap; 1685 1686 if (opc != ice_aqc_opc_list_func_caps && 1687 opc != ice_aqc_opc_list_dev_caps) 1688 return ICE_ERR_PARAM; 1689 1690 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1691 1692 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1693 if (!status) 1694 ice_parse_caps(hw, buf, le32_to_cpu(cmd->count), opc); 1695 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM) 1696 *cap_count = le32_to_cpu(cmd->count); 1697 return status; 1698 } 1699 1700 /** 1701 * ice_discover_caps - get info about the HW 1702 * @hw: pointer to the hardware structure 1703 * @opc: capabilities type to discover - pass in the command opcode 1704 */ 1705 static enum ice_status 1706 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc) 1707 { 1708 enum ice_status status; 1709 u32 cap_count; 1710 u16 cbuf_len; 1711 u8 retries; 1712 1713 /* The driver doesn't know how many capabilities the device will return 1714 * so the buffer size required isn't known ahead of time. The driver 1715 * starts with cbuf_len and if this turns out to be insufficient, the 1716 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs. 1717 * The driver then allocates the buffer based on the count and retries 1718 * the operation. So it follows that the retry count is 2. 1719 */ 1720 #define ICE_GET_CAP_BUF_COUNT 40 1721 #define ICE_GET_CAP_RETRY_COUNT 2 1722 1723 cap_count = ICE_GET_CAP_BUF_COUNT; 1724 retries = ICE_GET_CAP_RETRY_COUNT; 1725 1726 do { 1727 void *cbuf; 1728 1729 cbuf_len = (u16)(cap_count * 1730 sizeof(struct ice_aqc_list_caps_elem)); 1731 cbuf = devm_kzalloc(ice_hw_to_dev(hw), cbuf_len, GFP_KERNEL); 1732 if (!cbuf) 1733 return ICE_ERR_NO_MEMORY; 1734 1735 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count, 1736 opc, NULL); 1737 devm_kfree(ice_hw_to_dev(hw), cbuf); 1738 1739 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM) 1740 break; 1741 1742 /* If ENOMEM is returned, try again with bigger buffer */ 1743 } while (--retries); 1744 1745 return status; 1746 } 1747 1748 /** 1749 * ice_get_caps - get info about the HW 1750 * @hw: pointer to the hardware structure 1751 */ 1752 enum ice_status ice_get_caps(struct ice_hw *hw) 1753 { 1754 enum ice_status status; 1755 1756 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps); 1757 if (!status) 1758 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps); 1759 1760 return status; 1761 } 1762 1763 /** 1764 * ice_aq_manage_mac_write - manage MAC address write command 1765 * @hw: pointer to the HW struct 1766 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 1767 * @flags: flags to control write behavior 1768 * @cd: pointer to command details structure or NULL 1769 * 1770 * This function is used to write MAC address to the NVM (0x0108). 1771 */ 1772 enum ice_status 1773 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 1774 struct ice_sq_cd *cd) 1775 { 1776 struct ice_aqc_manage_mac_write *cmd; 1777 struct ice_aq_desc desc; 1778 1779 cmd = &desc.params.mac_write; 1780 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 1781 1782 cmd->flags = flags; 1783 1784 /* Prep values for flags, sah, sal */ 1785 cmd->sah = htons(*((const u16 *)mac_addr)); 1786 cmd->sal = htonl(*((const u32 *)(mac_addr + 2))); 1787 1788 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1789 } 1790 1791 /** 1792 * ice_aq_clear_pxe_mode 1793 * @hw: pointer to the HW struct 1794 * 1795 * Tell the firmware that the driver is taking over from PXE (0x0110). 1796 */ 1797 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 1798 { 1799 struct ice_aq_desc desc; 1800 1801 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 1802 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 1803 1804 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1805 } 1806 1807 /** 1808 * ice_clear_pxe_mode - clear pxe operations mode 1809 * @hw: pointer to the HW struct 1810 * 1811 * Make sure all PXE mode settings are cleared, including things 1812 * like descriptor fetch/write-back mode. 1813 */ 1814 void ice_clear_pxe_mode(struct ice_hw *hw) 1815 { 1816 if (ice_check_sq_alive(hw, &hw->adminq)) 1817 ice_aq_clear_pxe_mode(hw); 1818 } 1819 1820 /** 1821 * ice_get_link_speed_based_on_phy_type - returns link speed 1822 * @phy_type_low: lower part of phy_type 1823 * @phy_type_high: higher part of phy_type 1824 * 1825 * This helper function will convert an entry in PHY type structure 1826 * [phy_type_low, phy_type_high] to its corresponding link speed. 1827 * Note: In the structure of [phy_type_low, phy_type_high], there should 1828 * be one bit set, as this function will convert one PHY type to its 1829 * speed. 1830 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 1831 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 1832 */ 1833 static u16 1834 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 1835 { 1836 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 1837 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 1838 1839 switch (phy_type_low) { 1840 case ICE_PHY_TYPE_LOW_100BASE_TX: 1841 case ICE_PHY_TYPE_LOW_100M_SGMII: 1842 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 1843 break; 1844 case ICE_PHY_TYPE_LOW_1000BASE_T: 1845 case ICE_PHY_TYPE_LOW_1000BASE_SX: 1846 case ICE_PHY_TYPE_LOW_1000BASE_LX: 1847 case ICE_PHY_TYPE_LOW_1000BASE_KX: 1848 case ICE_PHY_TYPE_LOW_1G_SGMII: 1849 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 1850 break; 1851 case ICE_PHY_TYPE_LOW_2500BASE_T: 1852 case ICE_PHY_TYPE_LOW_2500BASE_X: 1853 case ICE_PHY_TYPE_LOW_2500BASE_KX: 1854 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 1855 break; 1856 case ICE_PHY_TYPE_LOW_5GBASE_T: 1857 case ICE_PHY_TYPE_LOW_5GBASE_KR: 1858 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 1859 break; 1860 case ICE_PHY_TYPE_LOW_10GBASE_T: 1861 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 1862 case ICE_PHY_TYPE_LOW_10GBASE_SR: 1863 case ICE_PHY_TYPE_LOW_10GBASE_LR: 1864 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 1865 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 1866 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 1867 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 1868 break; 1869 case ICE_PHY_TYPE_LOW_25GBASE_T: 1870 case ICE_PHY_TYPE_LOW_25GBASE_CR: 1871 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 1872 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 1873 case ICE_PHY_TYPE_LOW_25GBASE_SR: 1874 case ICE_PHY_TYPE_LOW_25GBASE_LR: 1875 case ICE_PHY_TYPE_LOW_25GBASE_KR: 1876 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 1877 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 1878 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 1879 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 1880 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 1881 break; 1882 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 1883 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 1884 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 1885 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 1886 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 1887 case ICE_PHY_TYPE_LOW_40G_XLAUI: 1888 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 1889 break; 1890 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 1891 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 1892 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 1893 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 1894 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 1895 case ICE_PHY_TYPE_LOW_50G_LAUI2: 1896 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 1897 case ICE_PHY_TYPE_LOW_50G_AUI2: 1898 case ICE_PHY_TYPE_LOW_50GBASE_CP: 1899 case ICE_PHY_TYPE_LOW_50GBASE_SR: 1900 case ICE_PHY_TYPE_LOW_50GBASE_FR: 1901 case ICE_PHY_TYPE_LOW_50GBASE_LR: 1902 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 1903 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 1904 case ICE_PHY_TYPE_LOW_50G_AUI1: 1905 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 1906 break; 1907 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 1908 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 1909 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 1910 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 1911 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 1912 case ICE_PHY_TYPE_LOW_100G_CAUI4: 1913 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 1914 case ICE_PHY_TYPE_LOW_100G_AUI4: 1915 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 1916 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 1917 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 1918 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 1919 case ICE_PHY_TYPE_LOW_100GBASE_DR: 1920 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 1921 break; 1922 default: 1923 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 1924 break; 1925 } 1926 1927 switch (phy_type_high) { 1928 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 1929 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 1930 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 1931 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 1932 case ICE_PHY_TYPE_HIGH_100G_AUI2: 1933 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 1934 break; 1935 default: 1936 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 1937 break; 1938 } 1939 1940 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 1941 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 1942 return ICE_AQ_LINK_SPEED_UNKNOWN; 1943 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 1944 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 1945 return ICE_AQ_LINK_SPEED_UNKNOWN; 1946 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 1947 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 1948 return speed_phy_type_low; 1949 else 1950 return speed_phy_type_high; 1951 } 1952 1953 /** 1954 * ice_update_phy_type 1955 * @phy_type_low: pointer to the lower part of phy_type 1956 * @phy_type_high: pointer to the higher part of phy_type 1957 * @link_speeds_bitmap: targeted link speeds bitmap 1958 * 1959 * Note: For the link_speeds_bitmap structure, you can check it at 1960 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 1961 * link_speeds_bitmap include multiple speeds. 1962 * 1963 * Each entry in this [phy_type_low, phy_type_high] structure will 1964 * present a certain link speed. This helper function will turn on bits 1965 * in [phy_type_low, phy_type_high] structure based on the value of 1966 * link_speeds_bitmap input parameter. 1967 */ 1968 void 1969 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 1970 u16 link_speeds_bitmap) 1971 { 1972 u64 pt_high; 1973 u64 pt_low; 1974 int index; 1975 u16 speed; 1976 1977 /* We first check with low part of phy_type */ 1978 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 1979 pt_low = BIT_ULL(index); 1980 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 1981 1982 if (link_speeds_bitmap & speed) 1983 *phy_type_low |= BIT_ULL(index); 1984 } 1985 1986 /* We then check with high part of phy_type */ 1987 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 1988 pt_high = BIT_ULL(index); 1989 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 1990 1991 if (link_speeds_bitmap & speed) 1992 *phy_type_high |= BIT_ULL(index); 1993 } 1994 } 1995 1996 /** 1997 * ice_aq_set_phy_cfg 1998 * @hw: pointer to the HW struct 1999 * @lport: logical port number 2000 * @cfg: structure with PHY configuration data to be set 2001 * @cd: pointer to command details structure or NULL 2002 * 2003 * Set the various PHY configuration parameters supported on the Port. 2004 * One or more of the Set PHY config parameters may be ignored in an MFP 2005 * mode as the PF may not have the privilege to set some of the PHY Config 2006 * parameters. This status will be indicated by the command response (0x0601). 2007 */ 2008 enum ice_status 2009 ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport, 2010 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2011 { 2012 struct ice_aq_desc desc; 2013 2014 if (!cfg) 2015 return ICE_ERR_PARAM; 2016 2017 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2018 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2019 ice_debug(hw, ICE_DBG_PHY, 2020 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2021 cfg->caps); 2022 2023 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2024 } 2025 2026 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2027 desc.params.set_phy.lport_num = lport; 2028 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2029 2030 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n", 2031 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 2032 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n", 2033 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 2034 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps); 2035 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n", 2036 cfg->low_power_ctrl); 2037 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap); 2038 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value); 2039 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt); 2040 2041 return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2042 } 2043 2044 /** 2045 * ice_update_link_info - update status of the HW network link 2046 * @pi: port info structure of the interested logical port 2047 */ 2048 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2049 { 2050 struct ice_link_status *li; 2051 enum ice_status status; 2052 2053 if (!pi) 2054 return ICE_ERR_PARAM; 2055 2056 li = &pi->phy.link_info; 2057 2058 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2059 if (status) 2060 return status; 2061 2062 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2063 struct ice_aqc_get_phy_caps_data *pcaps; 2064 struct ice_hw *hw; 2065 2066 hw = pi->hw; 2067 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 2068 GFP_KERNEL); 2069 if (!pcaps) 2070 return ICE_ERR_NO_MEMORY; 2071 2072 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, 2073 pcaps, NULL); 2074 if (!status) 2075 memcpy(li->module_type, &pcaps->module_type, 2076 sizeof(li->module_type)); 2077 2078 devm_kfree(ice_hw_to_dev(hw), pcaps); 2079 } 2080 2081 return status; 2082 } 2083 2084 /** 2085 * ice_set_fc 2086 * @pi: port information structure 2087 * @aq_failures: pointer to status code, specific to ice_set_fc routine 2088 * @ena_auto_link_update: enable automatic link update 2089 * 2090 * Set the requested flow control mode. 2091 */ 2092 enum ice_status 2093 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2094 { 2095 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2096 struct ice_aqc_get_phy_caps_data *pcaps; 2097 enum ice_status status; 2098 u8 pause_mask = 0x0; 2099 struct ice_hw *hw; 2100 2101 if (!pi) 2102 return ICE_ERR_PARAM; 2103 hw = pi->hw; 2104 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE; 2105 2106 switch (pi->fc.req_mode) { 2107 case ICE_FC_FULL: 2108 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2109 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2110 break; 2111 case ICE_FC_RX_PAUSE: 2112 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2113 break; 2114 case ICE_FC_TX_PAUSE: 2115 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2116 break; 2117 default: 2118 break; 2119 } 2120 2121 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 2122 if (!pcaps) 2123 return ICE_ERR_NO_MEMORY; 2124 2125 /* Get the current PHY config */ 2126 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 2127 NULL); 2128 if (status) { 2129 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2130 goto out; 2131 } 2132 2133 /* clear the old pause settings */ 2134 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2135 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2136 2137 /* set the new capabilities */ 2138 cfg.caps |= pause_mask; 2139 2140 /* If the capabilities have changed, then set the new config */ 2141 if (cfg.caps != pcaps->caps) { 2142 int retry_count, retry_max = 10; 2143 2144 /* Auto restart link so settings take effect */ 2145 if (ena_auto_link_update) 2146 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2147 /* Copy over all the old settings */ 2148 cfg.phy_type_high = pcaps->phy_type_high; 2149 cfg.phy_type_low = pcaps->phy_type_low; 2150 cfg.low_power_ctrl = pcaps->low_power_ctrl; 2151 cfg.eee_cap = pcaps->eee_cap; 2152 cfg.eeer_value = pcaps->eeer_value; 2153 cfg.link_fec_opt = pcaps->link_fec_options; 2154 2155 status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL); 2156 if (status) { 2157 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 2158 goto out; 2159 } 2160 2161 /* Update the link info 2162 * It sometimes takes a really long time for link to 2163 * come back from the atomic reset. Thus, we wait a 2164 * little bit. 2165 */ 2166 for (retry_count = 0; retry_count < retry_max; retry_count++) { 2167 status = ice_update_link_info(pi); 2168 2169 if (!status) 2170 break; 2171 2172 mdelay(100); 2173 } 2174 2175 if (status) 2176 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 2177 } 2178 2179 out: 2180 devm_kfree(ice_hw_to_dev(hw), pcaps); 2181 return status; 2182 } 2183 2184 /** 2185 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 2186 * @caps: PHY ability structure to copy date from 2187 * @cfg: PHY configuration structure to copy data to 2188 * 2189 * Helper function to copy AQC PHY get ability data to PHY set configuration 2190 * data structure 2191 */ 2192 void 2193 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps, 2194 struct ice_aqc_set_phy_cfg_data *cfg) 2195 { 2196 if (!caps || !cfg) 2197 return; 2198 2199 cfg->phy_type_low = caps->phy_type_low; 2200 cfg->phy_type_high = caps->phy_type_high; 2201 cfg->caps = caps->caps; 2202 cfg->low_power_ctrl = caps->low_power_ctrl; 2203 cfg->eee_cap = caps->eee_cap; 2204 cfg->eeer_value = caps->eeer_value; 2205 cfg->link_fec_opt = caps->link_fec_options; 2206 } 2207 2208 /** 2209 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 2210 * @cfg: PHY configuration data to set FEC mode 2211 * @fec: FEC mode to configure 2212 * 2213 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC 2214 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps 2215 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling. 2216 */ 2217 void 2218 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec) 2219 { 2220 switch (fec) { 2221 case ICE_FEC_BASER: 2222 /* Clear RS bits, and AND BASE-R ability 2223 * bits and OR request bits. 2224 */ 2225 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2226 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 2227 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2228 ICE_AQC_PHY_FEC_25G_KR_REQ; 2229 break; 2230 case ICE_FEC_RS: 2231 /* Clear BASE-R bits, and AND RS ability 2232 * bits and OR request bits. 2233 */ 2234 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 2235 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2236 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 2237 break; 2238 case ICE_FEC_NONE: 2239 /* Clear all FEC option bits. */ 2240 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 2241 break; 2242 case ICE_FEC_AUTO: 2243 /* AND auto FEC bit, and all caps bits. */ 2244 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 2245 break; 2246 } 2247 } 2248 2249 /** 2250 * ice_get_link_status - get status of the HW network link 2251 * @pi: port information structure 2252 * @link_up: pointer to bool (true/false = linkup/linkdown) 2253 * 2254 * Variable link_up is true if link is up, false if link is down. 2255 * The variable link_up is invalid if status is non zero. As a 2256 * result of this call, link status reporting becomes enabled 2257 */ 2258 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 2259 { 2260 struct ice_phy_info *phy_info; 2261 enum ice_status status = 0; 2262 2263 if (!pi || !link_up) 2264 return ICE_ERR_PARAM; 2265 2266 phy_info = &pi->phy; 2267 2268 if (phy_info->get_link_info) { 2269 status = ice_update_link_info(pi); 2270 2271 if (status) 2272 ice_debug(pi->hw, ICE_DBG_LINK, 2273 "get link status error, status = %d\n", 2274 status); 2275 } 2276 2277 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 2278 2279 return status; 2280 } 2281 2282 /** 2283 * ice_aq_set_link_restart_an 2284 * @pi: pointer to the port information structure 2285 * @ena_link: if true: enable link, if false: disable link 2286 * @cd: pointer to command details structure or NULL 2287 * 2288 * Sets up the link and restarts the Auto-Negotiation over the link. 2289 */ 2290 enum ice_status 2291 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 2292 struct ice_sq_cd *cd) 2293 { 2294 struct ice_aqc_restart_an *cmd; 2295 struct ice_aq_desc desc; 2296 2297 cmd = &desc.params.restart_an; 2298 2299 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 2300 2301 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 2302 cmd->lport_num = pi->lport; 2303 if (ena_link) 2304 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 2305 else 2306 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 2307 2308 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 2309 } 2310 2311 /** 2312 * ice_aq_set_event_mask 2313 * @hw: pointer to the HW struct 2314 * @port_num: port number of the physical function 2315 * @mask: event mask to be set 2316 * @cd: pointer to command details structure or NULL 2317 * 2318 * Set event mask (0x0613) 2319 */ 2320 enum ice_status 2321 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 2322 struct ice_sq_cd *cd) 2323 { 2324 struct ice_aqc_set_event_mask *cmd; 2325 struct ice_aq_desc desc; 2326 2327 cmd = &desc.params.set_event_mask; 2328 2329 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 2330 2331 cmd->lport_num = port_num; 2332 2333 cmd->event_mask = cpu_to_le16(mask); 2334 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2335 } 2336 2337 /** 2338 * ice_aq_set_mac_loopback 2339 * @hw: pointer to the HW struct 2340 * @ena_lpbk: Enable or Disable loopback 2341 * @cd: pointer to command details structure or NULL 2342 * 2343 * Enable/disable loopback on a given port 2344 */ 2345 enum ice_status 2346 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 2347 { 2348 struct ice_aqc_set_mac_lb *cmd; 2349 struct ice_aq_desc desc; 2350 2351 cmd = &desc.params.set_mac_lb; 2352 2353 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 2354 if (ena_lpbk) 2355 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 2356 2357 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2358 } 2359 2360 /** 2361 * ice_aq_set_port_id_led 2362 * @pi: pointer to the port information 2363 * @is_orig_mode: is this LED set to original mode (by the net-list) 2364 * @cd: pointer to command details structure or NULL 2365 * 2366 * Set LED value for the given port (0x06e9) 2367 */ 2368 enum ice_status 2369 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 2370 struct ice_sq_cd *cd) 2371 { 2372 struct ice_aqc_set_port_id_led *cmd; 2373 struct ice_hw *hw = pi->hw; 2374 struct ice_aq_desc desc; 2375 2376 cmd = &desc.params.set_port_id_led; 2377 2378 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 2379 2380 if (is_orig_mode) 2381 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 2382 else 2383 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 2384 2385 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2386 } 2387 2388 /** 2389 * __ice_aq_get_set_rss_lut 2390 * @hw: pointer to the hardware structure 2391 * @vsi_id: VSI FW index 2392 * @lut_type: LUT table type 2393 * @lut: pointer to the LUT buffer provided by the caller 2394 * @lut_size: size of the LUT buffer 2395 * @glob_lut_idx: global LUT index 2396 * @set: set true to set the table, false to get the table 2397 * 2398 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 2399 */ 2400 static enum ice_status 2401 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 2402 u16 lut_size, u8 glob_lut_idx, bool set) 2403 { 2404 struct ice_aqc_get_set_rss_lut *cmd_resp; 2405 struct ice_aq_desc desc; 2406 enum ice_status status; 2407 u16 flags = 0; 2408 2409 cmd_resp = &desc.params.get_set_rss_lut; 2410 2411 if (set) { 2412 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 2413 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2414 } else { 2415 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 2416 } 2417 2418 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 2419 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 2420 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 2421 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 2422 2423 switch (lut_type) { 2424 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 2425 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 2426 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 2427 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 2428 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 2429 break; 2430 default: 2431 status = ICE_ERR_PARAM; 2432 goto ice_aq_get_set_rss_lut_exit; 2433 } 2434 2435 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 2436 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 2437 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 2438 2439 if (!set) 2440 goto ice_aq_get_set_rss_lut_send; 2441 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 2442 if (!set) 2443 goto ice_aq_get_set_rss_lut_send; 2444 } else { 2445 goto ice_aq_get_set_rss_lut_send; 2446 } 2447 2448 /* LUT size is only valid for Global and PF table types */ 2449 switch (lut_size) { 2450 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 2451 break; 2452 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 2453 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 2454 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 2455 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 2456 break; 2457 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 2458 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 2459 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 2460 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 2461 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 2462 break; 2463 } 2464 /* fall-through */ 2465 default: 2466 status = ICE_ERR_PARAM; 2467 goto ice_aq_get_set_rss_lut_exit; 2468 } 2469 2470 ice_aq_get_set_rss_lut_send: 2471 cmd_resp->flags = cpu_to_le16(flags); 2472 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 2473 2474 ice_aq_get_set_rss_lut_exit: 2475 return status; 2476 } 2477 2478 /** 2479 * ice_aq_get_rss_lut 2480 * @hw: pointer to the hardware structure 2481 * @vsi_handle: software VSI handle 2482 * @lut_type: LUT table type 2483 * @lut: pointer to the LUT buffer provided by the caller 2484 * @lut_size: size of the LUT buffer 2485 * 2486 * get the RSS lookup table, PF or VSI type 2487 */ 2488 enum ice_status 2489 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 2490 u8 *lut, u16 lut_size) 2491 { 2492 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 2493 return ICE_ERR_PARAM; 2494 2495 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2496 lut_type, lut, lut_size, 0, false); 2497 } 2498 2499 /** 2500 * ice_aq_set_rss_lut 2501 * @hw: pointer to the hardware structure 2502 * @vsi_handle: software VSI handle 2503 * @lut_type: LUT table type 2504 * @lut: pointer to the LUT buffer provided by the caller 2505 * @lut_size: size of the LUT buffer 2506 * 2507 * set the RSS lookup table, PF or VSI type 2508 */ 2509 enum ice_status 2510 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 2511 u8 *lut, u16 lut_size) 2512 { 2513 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 2514 return ICE_ERR_PARAM; 2515 2516 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2517 lut_type, lut, lut_size, 0, true); 2518 } 2519 2520 /** 2521 * __ice_aq_get_set_rss_key 2522 * @hw: pointer to the HW struct 2523 * @vsi_id: VSI FW index 2524 * @key: pointer to key info struct 2525 * @set: set true to set the key, false to get the key 2526 * 2527 * get (0x0B04) or set (0x0B02) the RSS key per VSI 2528 */ 2529 static enum 2530 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 2531 struct ice_aqc_get_set_rss_keys *key, 2532 bool set) 2533 { 2534 struct ice_aqc_get_set_rss_key *cmd_resp; 2535 u16 key_size = sizeof(*key); 2536 struct ice_aq_desc desc; 2537 2538 cmd_resp = &desc.params.get_set_rss_key; 2539 2540 if (set) { 2541 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 2542 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2543 } else { 2544 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 2545 } 2546 2547 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 2548 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 2549 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 2550 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 2551 2552 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 2553 } 2554 2555 /** 2556 * ice_aq_get_rss_key 2557 * @hw: pointer to the HW struct 2558 * @vsi_handle: software VSI handle 2559 * @key: pointer to key info struct 2560 * 2561 * get the RSS key per VSI 2562 */ 2563 enum ice_status 2564 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 2565 struct ice_aqc_get_set_rss_keys *key) 2566 { 2567 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 2568 return ICE_ERR_PARAM; 2569 2570 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2571 key, false); 2572 } 2573 2574 /** 2575 * ice_aq_set_rss_key 2576 * @hw: pointer to the HW struct 2577 * @vsi_handle: software VSI handle 2578 * @keys: pointer to key info struct 2579 * 2580 * set the RSS key per VSI 2581 */ 2582 enum ice_status 2583 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 2584 struct ice_aqc_get_set_rss_keys *keys) 2585 { 2586 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 2587 return ICE_ERR_PARAM; 2588 2589 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2590 keys, true); 2591 } 2592 2593 /** 2594 * ice_aq_add_lan_txq 2595 * @hw: pointer to the hardware structure 2596 * @num_qgrps: Number of added queue groups 2597 * @qg_list: list of queue groups to be added 2598 * @buf_size: size of buffer for indirect command 2599 * @cd: pointer to command details structure or NULL 2600 * 2601 * Add Tx LAN queue (0x0C30) 2602 * 2603 * NOTE: 2604 * Prior to calling add Tx LAN queue: 2605 * Initialize the following as part of the Tx queue context: 2606 * Completion queue ID if the queue uses Completion queue, Quanta profile, 2607 * Cache profile and Packet shaper profile. 2608 * 2609 * After add Tx LAN queue AQ command is completed: 2610 * Interrupts should be associated with specific queues, 2611 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 2612 * flow. 2613 */ 2614 static enum ice_status 2615 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 2616 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 2617 struct ice_sq_cd *cd) 2618 { 2619 u16 i, sum_header_size, sum_q_size = 0; 2620 struct ice_aqc_add_tx_qgrp *list; 2621 struct ice_aqc_add_txqs *cmd; 2622 struct ice_aq_desc desc; 2623 2624 cmd = &desc.params.add_txqs; 2625 2626 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 2627 2628 if (!qg_list) 2629 return ICE_ERR_PARAM; 2630 2631 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 2632 return ICE_ERR_PARAM; 2633 2634 sum_header_size = num_qgrps * 2635 (sizeof(*qg_list) - sizeof(*qg_list->txqs)); 2636 2637 list = qg_list; 2638 for (i = 0; i < num_qgrps; i++) { 2639 struct ice_aqc_add_txqs_perq *q = list->txqs; 2640 2641 sum_q_size += list->num_txqs * sizeof(*q); 2642 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs); 2643 } 2644 2645 if (buf_size != (sum_header_size + sum_q_size)) 2646 return ICE_ERR_PARAM; 2647 2648 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2649 2650 cmd->num_qgrps = num_qgrps; 2651 2652 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 2653 } 2654 2655 /** 2656 * ice_aq_dis_lan_txq 2657 * @hw: pointer to the hardware structure 2658 * @num_qgrps: number of groups in the list 2659 * @qg_list: the list of groups to disable 2660 * @buf_size: the total size of the qg_list buffer in bytes 2661 * @rst_src: if called due to reset, specifies the reset source 2662 * @vmvf_num: the relative VM or VF number that is undergoing the reset 2663 * @cd: pointer to command details structure or NULL 2664 * 2665 * Disable LAN Tx queue (0x0C31) 2666 */ 2667 static enum ice_status 2668 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 2669 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 2670 enum ice_disq_rst_src rst_src, u16 vmvf_num, 2671 struct ice_sq_cd *cd) 2672 { 2673 struct ice_aqc_dis_txqs *cmd; 2674 struct ice_aq_desc desc; 2675 enum ice_status status; 2676 u16 i, sz = 0; 2677 2678 cmd = &desc.params.dis_txqs; 2679 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 2680 2681 /* qg_list can be NULL only in VM/VF reset flow */ 2682 if (!qg_list && !rst_src) 2683 return ICE_ERR_PARAM; 2684 2685 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 2686 return ICE_ERR_PARAM; 2687 2688 cmd->num_entries = num_qgrps; 2689 2690 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 2691 ICE_AQC_Q_DIS_TIMEOUT_M); 2692 2693 switch (rst_src) { 2694 case ICE_VM_RESET: 2695 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 2696 cmd->vmvf_and_timeout |= 2697 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 2698 break; 2699 case ICE_VF_RESET: 2700 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 2701 /* In this case, FW expects vmvf_num to be absolute VF ID */ 2702 cmd->vmvf_and_timeout |= 2703 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 2704 ICE_AQC_Q_DIS_VMVF_NUM_M); 2705 break; 2706 case ICE_NO_RESET: 2707 default: 2708 break; 2709 } 2710 2711 /* flush pipe on time out */ 2712 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 2713 /* If no queue group info, we are in a reset flow. Issue the AQ */ 2714 if (!qg_list) 2715 goto do_aq; 2716 2717 /* set RD bit to indicate that command buffer is provided by the driver 2718 * and it needs to be read by the firmware 2719 */ 2720 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2721 2722 for (i = 0; i < num_qgrps; ++i) { 2723 /* Calculate the size taken up by the queue IDs in this group */ 2724 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id); 2725 2726 /* Add the size of the group header */ 2727 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id); 2728 2729 /* If the num of queues is even, add 2 bytes of padding */ 2730 if ((qg_list[i].num_qs % 2) == 0) 2731 sz += 2; 2732 } 2733 2734 if (buf_size != sz) 2735 return ICE_ERR_PARAM; 2736 2737 do_aq: 2738 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 2739 if (status) { 2740 if (!qg_list) 2741 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 2742 vmvf_num, hw->adminq.sq_last_status); 2743 else 2744 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 2745 le16_to_cpu(qg_list[0].q_id[0]), 2746 hw->adminq.sq_last_status); 2747 } 2748 return status; 2749 } 2750 2751 /* End of FW Admin Queue command wrappers */ 2752 2753 /** 2754 * ice_write_byte - write a byte to a packed context structure 2755 * @src_ctx: the context structure to read from 2756 * @dest_ctx: the context to be written to 2757 * @ce_info: a description of the struct to be filled 2758 */ 2759 static void 2760 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2761 { 2762 u8 src_byte, dest_byte, mask; 2763 u8 *from, *dest; 2764 u16 shift_width; 2765 2766 /* copy from the next struct field */ 2767 from = src_ctx + ce_info->offset; 2768 2769 /* prepare the bits and mask */ 2770 shift_width = ce_info->lsb % 8; 2771 mask = (u8)(BIT(ce_info->width) - 1); 2772 2773 src_byte = *from; 2774 src_byte &= mask; 2775 2776 /* shift to correct alignment */ 2777 mask <<= shift_width; 2778 src_byte <<= shift_width; 2779 2780 /* get the current bits from the target bit string */ 2781 dest = dest_ctx + (ce_info->lsb / 8); 2782 2783 memcpy(&dest_byte, dest, sizeof(dest_byte)); 2784 2785 dest_byte &= ~mask; /* get the bits not changing */ 2786 dest_byte |= src_byte; /* add in the new bits */ 2787 2788 /* put it all back */ 2789 memcpy(dest, &dest_byte, sizeof(dest_byte)); 2790 } 2791 2792 /** 2793 * ice_write_word - write a word to a packed context structure 2794 * @src_ctx: the context structure to read from 2795 * @dest_ctx: the context to be written to 2796 * @ce_info: a description of the struct to be filled 2797 */ 2798 static void 2799 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2800 { 2801 u16 src_word, mask; 2802 __le16 dest_word; 2803 u8 *from, *dest; 2804 u16 shift_width; 2805 2806 /* copy from the next struct field */ 2807 from = src_ctx + ce_info->offset; 2808 2809 /* prepare the bits and mask */ 2810 shift_width = ce_info->lsb % 8; 2811 mask = BIT(ce_info->width) - 1; 2812 2813 /* don't swizzle the bits until after the mask because the mask bits 2814 * will be in a different bit position on big endian machines 2815 */ 2816 src_word = *(u16 *)from; 2817 src_word &= mask; 2818 2819 /* shift to correct alignment */ 2820 mask <<= shift_width; 2821 src_word <<= shift_width; 2822 2823 /* get the current bits from the target bit string */ 2824 dest = dest_ctx + (ce_info->lsb / 8); 2825 2826 memcpy(&dest_word, dest, sizeof(dest_word)); 2827 2828 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 2829 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 2830 2831 /* put it all back */ 2832 memcpy(dest, &dest_word, sizeof(dest_word)); 2833 } 2834 2835 /** 2836 * ice_write_dword - write a dword to a packed context structure 2837 * @src_ctx: the context structure to read from 2838 * @dest_ctx: the context to be written to 2839 * @ce_info: a description of the struct to be filled 2840 */ 2841 static void 2842 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2843 { 2844 u32 src_dword, mask; 2845 __le32 dest_dword; 2846 u8 *from, *dest; 2847 u16 shift_width; 2848 2849 /* copy from the next struct field */ 2850 from = src_ctx + ce_info->offset; 2851 2852 /* prepare the bits and mask */ 2853 shift_width = ce_info->lsb % 8; 2854 2855 /* if the field width is exactly 32 on an x86 machine, then the shift 2856 * operation will not work because the SHL instructions count is masked 2857 * to 5 bits so the shift will do nothing 2858 */ 2859 if (ce_info->width < 32) 2860 mask = BIT(ce_info->width) - 1; 2861 else 2862 mask = (u32)~0; 2863 2864 /* don't swizzle the bits until after the mask because the mask bits 2865 * will be in a different bit position on big endian machines 2866 */ 2867 src_dword = *(u32 *)from; 2868 src_dword &= mask; 2869 2870 /* shift to correct alignment */ 2871 mask <<= shift_width; 2872 src_dword <<= shift_width; 2873 2874 /* get the current bits from the target bit string */ 2875 dest = dest_ctx + (ce_info->lsb / 8); 2876 2877 memcpy(&dest_dword, dest, sizeof(dest_dword)); 2878 2879 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 2880 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 2881 2882 /* put it all back */ 2883 memcpy(dest, &dest_dword, sizeof(dest_dword)); 2884 } 2885 2886 /** 2887 * ice_write_qword - write a qword to a packed context structure 2888 * @src_ctx: the context structure to read from 2889 * @dest_ctx: the context to be written to 2890 * @ce_info: a description of the struct to be filled 2891 */ 2892 static void 2893 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2894 { 2895 u64 src_qword, mask; 2896 __le64 dest_qword; 2897 u8 *from, *dest; 2898 u16 shift_width; 2899 2900 /* copy from the next struct field */ 2901 from = src_ctx + ce_info->offset; 2902 2903 /* prepare the bits and mask */ 2904 shift_width = ce_info->lsb % 8; 2905 2906 /* if the field width is exactly 64 on an x86 machine, then the shift 2907 * operation will not work because the SHL instructions count is masked 2908 * to 6 bits so the shift will do nothing 2909 */ 2910 if (ce_info->width < 64) 2911 mask = BIT_ULL(ce_info->width) - 1; 2912 else 2913 mask = (u64)~0; 2914 2915 /* don't swizzle the bits until after the mask because the mask bits 2916 * will be in a different bit position on big endian machines 2917 */ 2918 src_qword = *(u64 *)from; 2919 src_qword &= mask; 2920 2921 /* shift to correct alignment */ 2922 mask <<= shift_width; 2923 src_qword <<= shift_width; 2924 2925 /* get the current bits from the target bit string */ 2926 dest = dest_ctx + (ce_info->lsb / 8); 2927 2928 memcpy(&dest_qword, dest, sizeof(dest_qword)); 2929 2930 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 2931 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 2932 2933 /* put it all back */ 2934 memcpy(dest, &dest_qword, sizeof(dest_qword)); 2935 } 2936 2937 /** 2938 * ice_set_ctx - set context bits in packed structure 2939 * @src_ctx: pointer to a generic non-packed context structure 2940 * @dest_ctx: pointer to memory for the packed structure 2941 * @ce_info: a description of the structure to be transformed 2942 */ 2943 enum ice_status 2944 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2945 { 2946 int f; 2947 2948 for (f = 0; ce_info[f].width; f++) { 2949 /* We have to deal with each element of the FW response 2950 * using the correct size so that we are correct regardless 2951 * of the endianness of the machine. 2952 */ 2953 switch (ce_info[f].size_of) { 2954 case sizeof(u8): 2955 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 2956 break; 2957 case sizeof(u16): 2958 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 2959 break; 2960 case sizeof(u32): 2961 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 2962 break; 2963 case sizeof(u64): 2964 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 2965 break; 2966 default: 2967 return ICE_ERR_INVAL_SIZE; 2968 } 2969 } 2970 2971 return 0; 2972 } 2973 2974 /** 2975 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 2976 * @hw: pointer to the HW struct 2977 * @vsi_handle: software VSI handle 2978 * @tc: TC number 2979 * @q_handle: software queue handle 2980 */ 2981 static struct ice_q_ctx * 2982 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 2983 { 2984 struct ice_vsi_ctx *vsi; 2985 struct ice_q_ctx *q_ctx; 2986 2987 vsi = ice_get_vsi_ctx(hw, vsi_handle); 2988 if (!vsi) 2989 return NULL; 2990 if (q_handle >= vsi->num_lan_q_entries[tc]) 2991 return NULL; 2992 if (!vsi->lan_q_ctx[tc]) 2993 return NULL; 2994 q_ctx = vsi->lan_q_ctx[tc]; 2995 return &q_ctx[q_handle]; 2996 } 2997 2998 /** 2999 * ice_ena_vsi_txq 3000 * @pi: port information structure 3001 * @vsi_handle: software VSI handle 3002 * @tc: TC number 3003 * @q_handle: software queue handle 3004 * @num_qgrps: Number of added queue groups 3005 * @buf: list of queue groups to be added 3006 * @buf_size: size of buffer for indirect command 3007 * @cd: pointer to command details structure or NULL 3008 * 3009 * This function adds one LAN queue 3010 */ 3011 enum ice_status 3012 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 3013 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 3014 struct ice_sq_cd *cd) 3015 { 3016 struct ice_aqc_txsched_elem_data node = { 0 }; 3017 struct ice_sched_node *parent; 3018 struct ice_q_ctx *q_ctx; 3019 enum ice_status status; 3020 struct ice_hw *hw; 3021 3022 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3023 return ICE_ERR_CFG; 3024 3025 if (num_qgrps > 1 || buf->num_txqs > 1) 3026 return ICE_ERR_MAX_LIMIT; 3027 3028 hw = pi->hw; 3029 3030 if (!ice_is_vsi_valid(hw, vsi_handle)) 3031 return ICE_ERR_PARAM; 3032 3033 mutex_lock(&pi->sched_lock); 3034 3035 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 3036 if (!q_ctx) { 3037 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 3038 q_handle); 3039 status = ICE_ERR_PARAM; 3040 goto ena_txq_exit; 3041 } 3042 3043 /* find a parent node */ 3044 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 3045 ICE_SCHED_NODE_OWNER_LAN); 3046 if (!parent) { 3047 status = ICE_ERR_PARAM; 3048 goto ena_txq_exit; 3049 } 3050 3051 buf->parent_teid = parent->info.node_teid; 3052 node.parent_teid = parent->info.node_teid; 3053 /* Mark that the values in the "generic" section as valid. The default 3054 * value in the "generic" section is zero. This means that : 3055 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 3056 * - 0 priority among siblings, indicated by Bit 1-3. 3057 * - WFQ, indicated by Bit 4. 3058 * - 0 Adjustment value is used in PSM credit update flow, indicated by 3059 * Bit 5-6. 3060 * - Bit 7 is reserved. 3061 * Without setting the generic section as valid in valid_sections, the 3062 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 3063 */ 3064 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC; 3065 3066 /* add the LAN queue */ 3067 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 3068 if (status) { 3069 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 3070 le16_to_cpu(buf->txqs[0].txq_id), 3071 hw->adminq.sq_last_status); 3072 goto ena_txq_exit; 3073 } 3074 3075 node.node_teid = buf->txqs[0].q_teid; 3076 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 3077 q_ctx->q_handle = q_handle; 3078 3079 /* add a leaf node into schduler tree queue layer */ 3080 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 3081 3082 ena_txq_exit: 3083 mutex_unlock(&pi->sched_lock); 3084 return status; 3085 } 3086 3087 /** 3088 * ice_dis_vsi_txq 3089 * @pi: port information structure 3090 * @vsi_handle: software VSI handle 3091 * @tc: TC number 3092 * @num_queues: number of queues 3093 * @q_handles: pointer to software queue handle array 3094 * @q_ids: pointer to the q_id array 3095 * @q_teids: pointer to queue node teids 3096 * @rst_src: if called due to reset, specifies the reset source 3097 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3098 * @cd: pointer to command details structure or NULL 3099 * 3100 * This function removes queues and their corresponding nodes in SW DB 3101 */ 3102 enum ice_status 3103 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 3104 u16 *q_handles, u16 *q_ids, u32 *q_teids, 3105 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3106 struct ice_sq_cd *cd) 3107 { 3108 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 3109 struct ice_aqc_dis_txq_item qg_list; 3110 struct ice_q_ctx *q_ctx; 3111 u16 i; 3112 3113 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3114 return ICE_ERR_CFG; 3115 3116 if (!num_queues) { 3117 /* if queue is disabled already yet the disable queue command 3118 * has to be sent to complete the VF reset, then call 3119 * ice_aq_dis_lan_txq without any queue information 3120 */ 3121 if (rst_src) 3122 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src, 3123 vmvf_num, NULL); 3124 return ICE_ERR_CFG; 3125 } 3126 3127 mutex_lock(&pi->sched_lock); 3128 3129 for (i = 0; i < num_queues; i++) { 3130 struct ice_sched_node *node; 3131 3132 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 3133 if (!node) 3134 continue; 3135 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]); 3136 if (!q_ctx) { 3137 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 3138 q_handles[i]); 3139 continue; 3140 } 3141 if (q_ctx->q_handle != q_handles[i]) { 3142 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 3143 q_ctx->q_handle, q_handles[i]); 3144 continue; 3145 } 3146 qg_list.parent_teid = node->info.parent_teid; 3147 qg_list.num_qs = 1; 3148 qg_list.q_id[0] = cpu_to_le16(q_ids[i]); 3149 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list, 3150 sizeof(qg_list), rst_src, vmvf_num, 3151 cd); 3152 3153 if (status) 3154 break; 3155 ice_free_sched_node(pi, node); 3156 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 3157 } 3158 mutex_unlock(&pi->sched_lock); 3159 return status; 3160 } 3161 3162 /** 3163 * ice_cfg_vsi_qs - configure the new/existing VSI queues 3164 * @pi: port information structure 3165 * @vsi_handle: software VSI handle 3166 * @tc_bitmap: TC bitmap 3167 * @maxqs: max queues array per TC 3168 * @owner: LAN or RDMA 3169 * 3170 * This function adds/updates the VSI queues per TC. 3171 */ 3172 static enum ice_status 3173 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 3174 u16 *maxqs, u8 owner) 3175 { 3176 enum ice_status status = 0; 3177 u8 i; 3178 3179 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3180 return ICE_ERR_CFG; 3181 3182 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3183 return ICE_ERR_PARAM; 3184 3185 mutex_lock(&pi->sched_lock); 3186 3187 ice_for_each_traffic_class(i) { 3188 /* configuration is possible only if TC node is present */ 3189 if (!ice_sched_get_tc_node(pi, i)) 3190 continue; 3191 3192 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 3193 ice_is_tc_ena(tc_bitmap, i)); 3194 if (status) 3195 break; 3196 } 3197 3198 mutex_unlock(&pi->sched_lock); 3199 return status; 3200 } 3201 3202 /** 3203 * ice_cfg_vsi_lan - configure VSI LAN queues 3204 * @pi: port information structure 3205 * @vsi_handle: software VSI handle 3206 * @tc_bitmap: TC bitmap 3207 * @max_lanqs: max LAN queues array per TC 3208 * 3209 * This function adds/updates the VSI LAN queues per TC. 3210 */ 3211 enum ice_status 3212 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 3213 u16 *max_lanqs) 3214 { 3215 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 3216 ICE_SCHED_NODE_OWNER_LAN); 3217 } 3218 3219 /** 3220 * ice_replay_pre_init - replay pre initialization 3221 * @hw: pointer to the HW struct 3222 * 3223 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 3224 */ 3225 static enum ice_status ice_replay_pre_init(struct ice_hw *hw) 3226 { 3227 struct ice_switch_info *sw = hw->switch_info; 3228 u8 i; 3229 3230 /* Delete old entries from replay filter list head if there is any */ 3231 ice_rm_all_sw_replay_rule_info(hw); 3232 /* In start of replay, move entries into replay_rules list, it 3233 * will allow adding rules entries back to filt_rules list, 3234 * which is operational list. 3235 */ 3236 for (i = 0; i < ICE_SW_LKUP_LAST; i++) 3237 list_replace_init(&sw->recp_list[i].filt_rules, 3238 &sw->recp_list[i].filt_replay_rules); 3239 3240 return 0; 3241 } 3242 3243 /** 3244 * ice_replay_vsi - replay VSI configuration 3245 * @hw: pointer to the HW struct 3246 * @vsi_handle: driver VSI handle 3247 * 3248 * Restore all VSI configuration after reset. It is required to call this 3249 * function with main VSI first. 3250 */ 3251 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 3252 { 3253 enum ice_status status; 3254 3255 if (!ice_is_vsi_valid(hw, vsi_handle)) 3256 return ICE_ERR_PARAM; 3257 3258 /* Replay pre-initialization if there is any */ 3259 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 3260 status = ice_replay_pre_init(hw); 3261 if (status) 3262 return status; 3263 } 3264 3265 /* Replay per VSI all filters */ 3266 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 3267 return status; 3268 } 3269 3270 /** 3271 * ice_replay_post - post replay configuration cleanup 3272 * @hw: pointer to the HW struct 3273 * 3274 * Post replay cleanup. 3275 */ 3276 void ice_replay_post(struct ice_hw *hw) 3277 { 3278 /* Delete old entries from replay filter list head */ 3279 ice_rm_all_sw_replay_rule_info(hw); 3280 } 3281 3282 /** 3283 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 3284 * @hw: ptr to the hardware info 3285 * @reg: offset of 64 bit HW register to read from 3286 * @prev_stat_loaded: bool to specify if previous stats are loaded 3287 * @prev_stat: ptr to previous loaded stat value 3288 * @cur_stat: ptr to current stat value 3289 */ 3290 void 3291 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 3292 u64 *prev_stat, u64 *cur_stat) 3293 { 3294 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 3295 3296 /* device stats are not reset at PFR, they likely will not be zeroed 3297 * when the driver starts. Thus, save the value from the first read 3298 * without adding to the statistic value so that we report stats which 3299 * count up from zero. 3300 */ 3301 if (!prev_stat_loaded) { 3302 *prev_stat = new_data; 3303 return; 3304 } 3305 3306 /* Calculate the difference between the new and old values, and then 3307 * add it to the software stat value. 3308 */ 3309 if (new_data >= *prev_stat) 3310 *cur_stat += new_data - *prev_stat; 3311 else 3312 /* to manage the potential roll-over */ 3313 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 3314 3315 /* Update the previously stored value to prepare for next read */ 3316 *prev_stat = new_data; 3317 } 3318 3319 /** 3320 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 3321 * @hw: ptr to the hardware info 3322 * @reg: offset of HW register to read from 3323 * @prev_stat_loaded: bool to specify if previous stats are loaded 3324 * @prev_stat: ptr to previous loaded stat value 3325 * @cur_stat: ptr to current stat value 3326 */ 3327 void 3328 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 3329 u64 *prev_stat, u64 *cur_stat) 3330 { 3331 u32 new_data; 3332 3333 new_data = rd32(hw, reg); 3334 3335 /* device stats are not reset at PFR, they likely will not be zeroed 3336 * when the driver starts. Thus, save the value from the first read 3337 * without adding to the statistic value so that we report stats which 3338 * count up from zero. 3339 */ 3340 if (!prev_stat_loaded) { 3341 *prev_stat = new_data; 3342 return; 3343 } 3344 3345 /* Calculate the difference between the new and old values, and then 3346 * add it to the software stat value. 3347 */ 3348 if (new_data >= *prev_stat) 3349 *cur_stat += new_data - *prev_stat; 3350 else 3351 /* to manage the potential roll-over */ 3352 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 3353 3354 /* Update the previously stored value to prepare for next read */ 3355 *prev_stat = new_data; 3356 } 3357 3358 /** 3359 * ice_sched_query_elem - query element information from HW 3360 * @hw: pointer to the HW struct 3361 * @node_teid: node TEID to be queried 3362 * @buf: buffer to element information 3363 * 3364 * This function queries HW element information 3365 */ 3366 enum ice_status 3367 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 3368 struct ice_aqc_get_elem *buf) 3369 { 3370 u16 buf_size, num_elem_ret = 0; 3371 enum ice_status status; 3372 3373 buf_size = sizeof(*buf); 3374 memset(buf, 0, buf_size); 3375 buf->generic[0].node_teid = cpu_to_le32(node_teid); 3376 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 3377 NULL); 3378 if (status || num_elem_ret != 1) 3379 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 3380 return status; 3381 } 3382