1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 9 #define ICE_PF_RESET_WAIT_COUNT 300 10 11 static const char * const ice_link_mode_str_low[] = { 12 [0] = "100BASE_TX", 13 [1] = "100M_SGMII", 14 [2] = "1000BASE_T", 15 [3] = "1000BASE_SX", 16 [4] = "1000BASE_LX", 17 [5] = "1000BASE_KX", 18 [6] = "1G_SGMII", 19 [7] = "2500BASE_T", 20 [8] = "2500BASE_X", 21 [9] = "2500BASE_KX", 22 [10] = "5GBASE_T", 23 [11] = "5GBASE_KR", 24 [12] = "10GBASE_T", 25 [13] = "10G_SFI_DA", 26 [14] = "10GBASE_SR", 27 [15] = "10GBASE_LR", 28 [16] = "10GBASE_KR_CR1", 29 [17] = "10G_SFI_AOC_ACC", 30 [18] = "10G_SFI_C2C", 31 [19] = "25GBASE_T", 32 [20] = "25GBASE_CR", 33 [21] = "25GBASE_CR_S", 34 [22] = "25GBASE_CR1", 35 [23] = "25GBASE_SR", 36 [24] = "25GBASE_LR", 37 [25] = "25GBASE_KR", 38 [26] = "25GBASE_KR_S", 39 [27] = "25GBASE_KR1", 40 [28] = "25G_AUI_AOC_ACC", 41 [29] = "25G_AUI_C2C", 42 [30] = "40GBASE_CR4", 43 [31] = "40GBASE_SR4", 44 [32] = "40GBASE_LR4", 45 [33] = "40GBASE_KR4", 46 [34] = "40G_XLAUI_AOC_ACC", 47 [35] = "40G_XLAUI", 48 [36] = "50GBASE_CR2", 49 [37] = "50GBASE_SR2", 50 [38] = "50GBASE_LR2", 51 [39] = "50GBASE_KR2", 52 [40] = "50G_LAUI2_AOC_ACC", 53 [41] = "50G_LAUI2", 54 [42] = "50G_AUI2_AOC_ACC", 55 [43] = "50G_AUI2", 56 [44] = "50GBASE_CP", 57 [45] = "50GBASE_SR", 58 [46] = "50GBASE_FR", 59 [47] = "50GBASE_LR", 60 [48] = "50GBASE_KR_PAM4", 61 [49] = "50G_AUI1_AOC_ACC", 62 [50] = "50G_AUI1", 63 [51] = "100GBASE_CR4", 64 [52] = "100GBASE_SR4", 65 [53] = "100GBASE_LR4", 66 [54] = "100GBASE_KR4", 67 [55] = "100G_CAUI4_AOC_ACC", 68 [56] = "100G_CAUI4", 69 [57] = "100G_AUI4_AOC_ACC", 70 [58] = "100G_AUI4", 71 [59] = "100GBASE_CR_PAM4", 72 [60] = "100GBASE_KR_PAM4", 73 [61] = "100GBASE_CP2", 74 [62] = "100GBASE_SR2", 75 [63] = "100GBASE_DR", 76 }; 77 78 static const char * const ice_link_mode_str_high[] = { 79 [0] = "100GBASE_KR2_PAM4", 80 [1] = "100G_CAUI2_AOC_ACC", 81 [2] = "100G_CAUI2", 82 [3] = "100G_AUI2_AOC_ACC", 83 [4] = "100G_AUI2", 84 }; 85 86 /** 87 * ice_dump_phy_type - helper function to dump phy_type 88 * @hw: pointer to the HW structure 89 * @low: 64 bit value for phy_type_low 90 * @high: 64 bit value for phy_type_high 91 * @prefix: prefix string to differentiate multiple dumps 92 */ 93 static void 94 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 95 { 96 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 97 98 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 99 if (low & BIT_ULL(i)) 100 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 101 prefix, i, ice_link_mode_str_low[i]); 102 } 103 104 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 105 106 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 107 if (high & BIT_ULL(i)) 108 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 109 prefix, i, ice_link_mode_str_high[i]); 110 } 111 } 112 113 /** 114 * ice_set_mac_type - Sets MAC type 115 * @hw: pointer to the HW structure 116 * 117 * This function sets the MAC type of the adapter based on the 118 * vendor ID and device ID stored in the HW structure. 119 */ 120 static int ice_set_mac_type(struct ice_hw *hw) 121 { 122 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 123 return -ENODEV; 124 125 switch (hw->device_id) { 126 case ICE_DEV_ID_E810C_BACKPLANE: 127 case ICE_DEV_ID_E810C_QSFP: 128 case ICE_DEV_ID_E810C_SFP: 129 case ICE_DEV_ID_E810_XXV_BACKPLANE: 130 case ICE_DEV_ID_E810_XXV_QSFP: 131 case ICE_DEV_ID_E810_XXV_SFP: 132 hw->mac_type = ICE_MAC_E810; 133 break; 134 case ICE_DEV_ID_E823C_10G_BASE_T: 135 case ICE_DEV_ID_E823C_BACKPLANE: 136 case ICE_DEV_ID_E823C_QSFP: 137 case ICE_DEV_ID_E823C_SFP: 138 case ICE_DEV_ID_E823C_SGMII: 139 case ICE_DEV_ID_E822C_10G_BASE_T: 140 case ICE_DEV_ID_E822C_BACKPLANE: 141 case ICE_DEV_ID_E822C_QSFP: 142 case ICE_DEV_ID_E822C_SFP: 143 case ICE_DEV_ID_E822C_SGMII: 144 case ICE_DEV_ID_E822L_10G_BASE_T: 145 case ICE_DEV_ID_E822L_BACKPLANE: 146 case ICE_DEV_ID_E822L_SFP: 147 case ICE_DEV_ID_E822L_SGMII: 148 case ICE_DEV_ID_E823L_10G_BASE_T: 149 case ICE_DEV_ID_E823L_1GBE: 150 case ICE_DEV_ID_E823L_BACKPLANE: 151 case ICE_DEV_ID_E823L_QSFP: 152 case ICE_DEV_ID_E823L_SFP: 153 hw->mac_type = ICE_MAC_GENERIC; 154 break; 155 default: 156 hw->mac_type = ICE_MAC_UNKNOWN; 157 break; 158 } 159 160 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 161 return 0; 162 } 163 164 /** 165 * ice_is_e810 166 * @hw: pointer to the hardware structure 167 * 168 * returns true if the device is E810 based, false if not. 169 */ 170 bool ice_is_e810(struct ice_hw *hw) 171 { 172 return hw->mac_type == ICE_MAC_E810; 173 } 174 175 /** 176 * ice_is_e810t 177 * @hw: pointer to the hardware structure 178 * 179 * returns true if the device is E810T based, false if not. 180 */ 181 bool ice_is_e810t(struct ice_hw *hw) 182 { 183 switch (hw->device_id) { 184 case ICE_DEV_ID_E810C_SFP: 185 switch (hw->subsystem_device_id) { 186 case ICE_SUBDEV_ID_E810T: 187 case ICE_SUBDEV_ID_E810T2: 188 case ICE_SUBDEV_ID_E810T3: 189 case ICE_SUBDEV_ID_E810T4: 190 case ICE_SUBDEV_ID_E810T6: 191 case ICE_SUBDEV_ID_E810T7: 192 return true; 193 } 194 break; 195 case ICE_DEV_ID_E810C_QSFP: 196 switch (hw->subsystem_device_id) { 197 case ICE_SUBDEV_ID_E810T2: 198 case ICE_SUBDEV_ID_E810T3: 199 case ICE_SUBDEV_ID_E810T5: 200 return true; 201 } 202 break; 203 default: 204 break; 205 } 206 207 return false; 208 } 209 210 /** 211 * ice_is_e823 212 * @hw: pointer to the hardware structure 213 * 214 * returns true if the device is E823-L or E823-C based, false if not. 215 */ 216 bool ice_is_e823(struct ice_hw *hw) 217 { 218 switch (hw->device_id) { 219 case ICE_DEV_ID_E823L_BACKPLANE: 220 case ICE_DEV_ID_E823L_SFP: 221 case ICE_DEV_ID_E823L_10G_BASE_T: 222 case ICE_DEV_ID_E823L_1GBE: 223 case ICE_DEV_ID_E823L_QSFP: 224 case ICE_DEV_ID_E823C_BACKPLANE: 225 case ICE_DEV_ID_E823C_QSFP: 226 case ICE_DEV_ID_E823C_SFP: 227 case ICE_DEV_ID_E823C_10G_BASE_T: 228 case ICE_DEV_ID_E823C_SGMII: 229 return true; 230 default: 231 return false; 232 } 233 } 234 235 /** 236 * ice_clear_pf_cfg - Clear PF configuration 237 * @hw: pointer to the hardware structure 238 * 239 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 240 * configuration, flow director filters, etc.). 241 */ 242 int ice_clear_pf_cfg(struct ice_hw *hw) 243 { 244 struct ice_aq_desc desc; 245 246 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 247 248 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 249 } 250 251 /** 252 * ice_aq_manage_mac_read - manage MAC address read command 253 * @hw: pointer to the HW struct 254 * @buf: a virtual buffer to hold the manage MAC read response 255 * @buf_size: Size of the virtual buffer 256 * @cd: pointer to command details structure or NULL 257 * 258 * This function is used to return per PF station MAC address (0x0107). 259 * NOTE: Upon successful completion of this command, MAC address information 260 * is returned in user specified buffer. Please interpret user specified 261 * buffer as "manage_mac_read" response. 262 * Response such as various MAC addresses are stored in HW struct (port.mac) 263 * ice_discover_dev_caps is expected to be called before this function is 264 * called. 265 */ 266 static int 267 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 268 struct ice_sq_cd *cd) 269 { 270 struct ice_aqc_manage_mac_read_resp *resp; 271 struct ice_aqc_manage_mac_read *cmd; 272 struct ice_aq_desc desc; 273 int status; 274 u16 flags; 275 u8 i; 276 277 cmd = &desc.params.mac_read; 278 279 if (buf_size < sizeof(*resp)) 280 return -EINVAL; 281 282 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 283 284 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 285 if (status) 286 return status; 287 288 resp = buf; 289 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 290 291 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 292 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 293 return -EIO; 294 } 295 296 /* A single port can report up to two (LAN and WoL) addresses */ 297 for (i = 0; i < cmd->num_addr; i++) 298 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 299 ether_addr_copy(hw->port_info->mac.lan_addr, 300 resp[i].mac_addr); 301 ether_addr_copy(hw->port_info->mac.perm_addr, 302 resp[i].mac_addr); 303 break; 304 } 305 306 return 0; 307 } 308 309 /** 310 * ice_aq_get_phy_caps - returns PHY capabilities 311 * @pi: port information structure 312 * @qual_mods: report qualified modules 313 * @report_mode: report mode capabilities 314 * @pcaps: structure for PHY capabilities to be filled 315 * @cd: pointer to command details structure or NULL 316 * 317 * Returns the various PHY capabilities supported on the Port (0x0600) 318 */ 319 int 320 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 321 struct ice_aqc_get_phy_caps_data *pcaps, 322 struct ice_sq_cd *cd) 323 { 324 struct ice_aqc_get_phy_caps *cmd; 325 u16 pcaps_size = sizeof(*pcaps); 326 struct ice_aq_desc desc; 327 const char *prefix; 328 struct ice_hw *hw; 329 int status; 330 331 cmd = &desc.params.get_phy; 332 333 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 334 return -EINVAL; 335 hw = pi->hw; 336 337 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 338 !ice_fw_supports_report_dflt_cfg(hw)) 339 return -EINVAL; 340 341 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 342 343 if (qual_mods) 344 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 345 346 cmd->param0 |= cpu_to_le16(report_mode); 347 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 348 349 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 350 351 switch (report_mode) { 352 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 353 prefix = "phy_caps_media"; 354 break; 355 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 356 prefix = "phy_caps_no_media"; 357 break; 358 case ICE_AQC_REPORT_ACTIVE_CFG: 359 prefix = "phy_caps_active"; 360 break; 361 case ICE_AQC_REPORT_DFLT_CFG: 362 prefix = "phy_caps_default"; 363 break; 364 default: 365 prefix = "phy_caps_invalid"; 366 } 367 368 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 369 le64_to_cpu(pcaps->phy_type_high), prefix); 370 371 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 372 prefix, report_mode); 373 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 374 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 375 pcaps->low_power_ctrl_an); 376 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 377 pcaps->eee_cap); 378 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 379 pcaps->eeer_value); 380 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 381 pcaps->link_fec_options); 382 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 383 prefix, pcaps->module_compliance_enforcement); 384 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 385 prefix, pcaps->extended_compliance_code); 386 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 387 pcaps->module_type[0]); 388 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 389 pcaps->module_type[1]); 390 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 391 pcaps->module_type[2]); 392 393 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 394 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 395 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 396 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 397 sizeof(pi->phy.link_info.module_type)); 398 } 399 400 return status; 401 } 402 403 /** 404 * ice_aq_get_link_topo_handle - get link topology node return status 405 * @pi: port information structure 406 * @node_type: requested node type 407 * @cd: pointer to command details structure or NULL 408 * 409 * Get link topology node return status for specified node type (0x06E0) 410 * 411 * Node type cage can be used to determine if cage is present. If AQC 412 * returns error (ENOENT), then no cage present. If no cage present, then 413 * connection type is backplane or BASE-T. 414 */ 415 static int 416 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 417 struct ice_sq_cd *cd) 418 { 419 struct ice_aqc_get_link_topo *cmd; 420 struct ice_aq_desc desc; 421 422 cmd = &desc.params.get_link_topo; 423 424 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 425 426 cmd->addr.topo_params.node_type_ctx = 427 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 428 ICE_AQC_LINK_TOPO_NODE_CTX_S); 429 430 /* set node type */ 431 cmd->addr.topo_params.node_type_ctx |= 432 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 433 434 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 435 } 436 437 /** 438 * ice_is_media_cage_present 439 * @pi: port information structure 440 * 441 * Returns true if media cage is present, else false. If no cage, then 442 * media type is backplane or BASE-T. 443 */ 444 static bool ice_is_media_cage_present(struct ice_port_info *pi) 445 { 446 /* Node type cage can be used to determine if cage is present. If AQC 447 * returns error (ENOENT), then no cage present. If no cage present then 448 * connection type is backplane or BASE-T. 449 */ 450 return !ice_aq_get_link_topo_handle(pi, 451 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 452 NULL); 453 } 454 455 /** 456 * ice_get_media_type - Gets media type 457 * @pi: port information structure 458 */ 459 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 460 { 461 struct ice_link_status *hw_link_info; 462 463 if (!pi) 464 return ICE_MEDIA_UNKNOWN; 465 466 hw_link_info = &pi->phy.link_info; 467 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 468 /* If more than one media type is selected, report unknown */ 469 return ICE_MEDIA_UNKNOWN; 470 471 if (hw_link_info->phy_type_low) { 472 /* 1G SGMII is a special case where some DA cable PHYs 473 * may show this as an option when it really shouldn't 474 * be since SGMII is meant to be between a MAC and a PHY 475 * in a backplane. Try to detect this case and handle it 476 */ 477 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 478 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 479 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 480 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 481 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 482 return ICE_MEDIA_DA; 483 484 switch (hw_link_info->phy_type_low) { 485 case ICE_PHY_TYPE_LOW_1000BASE_SX: 486 case ICE_PHY_TYPE_LOW_1000BASE_LX: 487 case ICE_PHY_TYPE_LOW_10GBASE_SR: 488 case ICE_PHY_TYPE_LOW_10GBASE_LR: 489 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 490 case ICE_PHY_TYPE_LOW_25GBASE_SR: 491 case ICE_PHY_TYPE_LOW_25GBASE_LR: 492 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 493 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 494 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 495 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 496 case ICE_PHY_TYPE_LOW_50GBASE_SR: 497 case ICE_PHY_TYPE_LOW_50GBASE_FR: 498 case ICE_PHY_TYPE_LOW_50GBASE_LR: 499 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 500 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 501 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 502 case ICE_PHY_TYPE_LOW_100GBASE_DR: 503 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 504 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 505 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 506 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 507 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 508 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 509 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 510 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 511 return ICE_MEDIA_FIBER; 512 case ICE_PHY_TYPE_LOW_100BASE_TX: 513 case ICE_PHY_TYPE_LOW_1000BASE_T: 514 case ICE_PHY_TYPE_LOW_2500BASE_T: 515 case ICE_PHY_TYPE_LOW_5GBASE_T: 516 case ICE_PHY_TYPE_LOW_10GBASE_T: 517 case ICE_PHY_TYPE_LOW_25GBASE_T: 518 return ICE_MEDIA_BASET; 519 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 520 case ICE_PHY_TYPE_LOW_25GBASE_CR: 521 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 522 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 523 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 524 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 525 case ICE_PHY_TYPE_LOW_50GBASE_CP: 526 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 527 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 528 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 529 return ICE_MEDIA_DA; 530 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 531 case ICE_PHY_TYPE_LOW_40G_XLAUI: 532 case ICE_PHY_TYPE_LOW_50G_LAUI2: 533 case ICE_PHY_TYPE_LOW_50G_AUI2: 534 case ICE_PHY_TYPE_LOW_50G_AUI1: 535 case ICE_PHY_TYPE_LOW_100G_AUI4: 536 case ICE_PHY_TYPE_LOW_100G_CAUI4: 537 if (ice_is_media_cage_present(pi)) 538 return ICE_MEDIA_DA; 539 fallthrough; 540 case ICE_PHY_TYPE_LOW_1000BASE_KX: 541 case ICE_PHY_TYPE_LOW_2500BASE_KX: 542 case ICE_PHY_TYPE_LOW_2500BASE_X: 543 case ICE_PHY_TYPE_LOW_5GBASE_KR: 544 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 545 case ICE_PHY_TYPE_LOW_25GBASE_KR: 546 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 547 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 548 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 549 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 550 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 551 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 552 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 553 return ICE_MEDIA_BACKPLANE; 554 } 555 } else { 556 switch (hw_link_info->phy_type_high) { 557 case ICE_PHY_TYPE_HIGH_100G_AUI2: 558 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 559 if (ice_is_media_cage_present(pi)) 560 return ICE_MEDIA_DA; 561 fallthrough; 562 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 563 return ICE_MEDIA_BACKPLANE; 564 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 565 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 566 return ICE_MEDIA_FIBER; 567 } 568 } 569 return ICE_MEDIA_UNKNOWN; 570 } 571 572 /** 573 * ice_aq_get_link_info 574 * @pi: port information structure 575 * @ena_lse: enable/disable LinkStatusEvent reporting 576 * @link: pointer to link status structure - optional 577 * @cd: pointer to command details structure or NULL 578 * 579 * Get Link Status (0x607). Returns the link status of the adapter. 580 */ 581 int 582 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 583 struct ice_link_status *link, struct ice_sq_cd *cd) 584 { 585 struct ice_aqc_get_link_status_data link_data = { 0 }; 586 struct ice_aqc_get_link_status *resp; 587 struct ice_link_status *li_old, *li; 588 enum ice_media_type *hw_media_type; 589 struct ice_fc_info *hw_fc_info; 590 bool tx_pause, rx_pause; 591 struct ice_aq_desc desc; 592 struct ice_hw *hw; 593 u16 cmd_flags; 594 int status; 595 596 if (!pi) 597 return -EINVAL; 598 hw = pi->hw; 599 li_old = &pi->phy.link_info_old; 600 hw_media_type = &pi->phy.media_type; 601 li = &pi->phy.link_info; 602 hw_fc_info = &pi->fc; 603 604 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 605 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 606 resp = &desc.params.get_link_status; 607 resp->cmd_flags = cpu_to_le16(cmd_flags); 608 resp->lport_num = pi->lport; 609 610 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 611 612 if (status) 613 return status; 614 615 /* save off old link status information */ 616 *li_old = *li; 617 618 /* update current link status information */ 619 li->link_speed = le16_to_cpu(link_data.link_speed); 620 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 621 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 622 *hw_media_type = ice_get_media_type(pi); 623 li->link_info = link_data.link_info; 624 li->link_cfg_err = link_data.link_cfg_err; 625 li->an_info = link_data.an_info; 626 li->ext_info = link_data.ext_info; 627 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 628 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 629 li->topo_media_conflict = link_data.topo_media_conflict; 630 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 631 ICE_AQ_CFG_PACING_TYPE_M); 632 633 /* update fc info */ 634 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 635 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 636 if (tx_pause && rx_pause) 637 hw_fc_info->current_mode = ICE_FC_FULL; 638 else if (tx_pause) 639 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 640 else if (rx_pause) 641 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 642 else 643 hw_fc_info->current_mode = ICE_FC_NONE; 644 645 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 646 647 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 648 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 649 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 650 (unsigned long long)li->phy_type_low); 651 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 652 (unsigned long long)li->phy_type_high); 653 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 654 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 655 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 656 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 657 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 658 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 659 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 660 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 661 li->max_frame_size); 662 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 663 664 /* save link status information */ 665 if (link) 666 *link = *li; 667 668 /* flag cleared so calling functions don't call AQ again */ 669 pi->phy.get_link_info = false; 670 671 return 0; 672 } 673 674 /** 675 * ice_fill_tx_timer_and_fc_thresh 676 * @hw: pointer to the HW struct 677 * @cmd: pointer to MAC cfg structure 678 * 679 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 680 * descriptor 681 */ 682 static void 683 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 684 struct ice_aqc_set_mac_cfg *cmd) 685 { 686 u16 fc_thres_val, tx_timer_val; 687 u32 val; 688 689 /* We read back the transmit timer and FC threshold value of 690 * LFC. Thus, we will use index = 691 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 692 * 693 * Also, because we are operating on transmit timer and FC 694 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 695 */ 696 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 697 698 /* Retrieve the transmit timer */ 699 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 700 tx_timer_val = val & 701 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 702 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val); 703 704 /* Retrieve the FC threshold */ 705 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 706 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 707 708 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val); 709 } 710 711 /** 712 * ice_aq_set_mac_cfg 713 * @hw: pointer to the HW struct 714 * @max_frame_size: Maximum Frame Size to be supported 715 * @cd: pointer to command details structure or NULL 716 * 717 * Set MAC configuration (0x0603) 718 */ 719 int 720 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 721 { 722 struct ice_aqc_set_mac_cfg *cmd; 723 struct ice_aq_desc desc; 724 725 cmd = &desc.params.set_mac_cfg; 726 727 if (max_frame_size == 0) 728 return -EINVAL; 729 730 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 731 732 cmd->max_frame_size = cpu_to_le16(max_frame_size); 733 734 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 735 736 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 737 } 738 739 /** 740 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 741 * @hw: pointer to the HW struct 742 */ 743 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 744 { 745 struct ice_switch_info *sw; 746 int status; 747 748 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 749 sizeof(*hw->switch_info), GFP_KERNEL); 750 sw = hw->switch_info; 751 752 if (!sw) 753 return -ENOMEM; 754 755 INIT_LIST_HEAD(&sw->vsi_list_map_head); 756 sw->prof_res_bm_init = 0; 757 758 status = ice_init_def_sw_recp(hw); 759 if (status) { 760 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 761 return status; 762 } 763 return 0; 764 } 765 766 /** 767 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 768 * @hw: pointer to the HW struct 769 */ 770 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 771 { 772 struct ice_switch_info *sw = hw->switch_info; 773 struct ice_vsi_list_map_info *v_pos_map; 774 struct ice_vsi_list_map_info *v_tmp_map; 775 struct ice_sw_recipe *recps; 776 u8 i; 777 778 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 779 list_entry) { 780 list_del(&v_pos_map->list_entry); 781 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 782 } 783 recps = sw->recp_list; 784 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 785 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 786 787 recps[i].root_rid = i; 788 list_for_each_entry_safe(rg_entry, tmprg_entry, 789 &recps[i].rg_list, l_entry) { 790 list_del(&rg_entry->l_entry); 791 devm_kfree(ice_hw_to_dev(hw), rg_entry); 792 } 793 794 if (recps[i].adv_rule) { 795 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 796 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 797 798 mutex_destroy(&recps[i].filt_rule_lock); 799 list_for_each_entry_safe(lst_itr, tmp_entry, 800 &recps[i].filt_rules, 801 list_entry) { 802 list_del(&lst_itr->list_entry); 803 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 804 devm_kfree(ice_hw_to_dev(hw), lst_itr); 805 } 806 } else { 807 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 808 809 mutex_destroy(&recps[i].filt_rule_lock); 810 list_for_each_entry_safe(lst_itr, tmp_entry, 811 &recps[i].filt_rules, 812 list_entry) { 813 list_del(&lst_itr->list_entry); 814 devm_kfree(ice_hw_to_dev(hw), lst_itr); 815 } 816 } 817 if (recps[i].root_buf) 818 devm_kfree(ice_hw_to_dev(hw), recps[i].root_buf); 819 } 820 ice_rm_all_sw_replay_rule_info(hw); 821 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 822 devm_kfree(ice_hw_to_dev(hw), sw); 823 } 824 825 /** 826 * ice_get_fw_log_cfg - get FW logging configuration 827 * @hw: pointer to the HW struct 828 */ 829 static int ice_get_fw_log_cfg(struct ice_hw *hw) 830 { 831 struct ice_aq_desc desc; 832 __le16 *config; 833 int status; 834 u16 size; 835 836 size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX; 837 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL); 838 if (!config) 839 return -ENOMEM; 840 841 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 842 843 status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 844 if (!status) { 845 u16 i; 846 847 /* Save FW logging information into the HW structure */ 848 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 849 u16 v, m, flgs; 850 851 v = le16_to_cpu(config[i]); 852 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 853 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 854 855 if (m < ICE_AQC_FW_LOG_ID_MAX) 856 hw->fw_log.evnts[m].cur = flgs; 857 } 858 } 859 860 devm_kfree(ice_hw_to_dev(hw), config); 861 862 return status; 863 } 864 865 /** 866 * ice_cfg_fw_log - configure FW logging 867 * @hw: pointer to the HW struct 868 * @enable: enable certain FW logging events if true, disable all if false 869 * 870 * This function enables/disables the FW logging via Rx CQ events and a UART 871 * port based on predetermined configurations. FW logging via the Rx CQ can be 872 * enabled/disabled for individual PF's. However, FW logging via the UART can 873 * only be enabled/disabled for all PFs on the same device. 874 * 875 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 876 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 877 * before initializing the device. 878 * 879 * When re/configuring FW logging, callers need to update the "cfg" elements of 880 * the hw->fw_log.evnts array with the desired logging event configurations for 881 * modules of interest. When disabling FW logging completely, the callers can 882 * just pass false in the "enable" parameter. On completion, the function will 883 * update the "cur" element of the hw->fw_log.evnts array with the resulting 884 * logging event configurations of the modules that are being re/configured. FW 885 * logging modules that are not part of a reconfiguration operation retain their 886 * previous states. 887 * 888 * Before resetting the device, it is recommended that the driver disables FW 889 * logging before shutting down the control queue. When disabling FW logging 890 * ("enable" = false), the latest configurations of FW logging events stored in 891 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 892 * a device reset. 893 * 894 * When enabling FW logging to emit log messages via the Rx CQ during the 895 * device's initialization phase, a mechanism alternative to interrupt handlers 896 * needs to be used to extract FW log messages from the Rx CQ periodically and 897 * to prevent the Rx CQ from being full and stalling other types of control 898 * messages from FW to SW. Interrupts are typically disabled during the device's 899 * initialization phase. 900 */ 901 static int ice_cfg_fw_log(struct ice_hw *hw, bool enable) 902 { 903 struct ice_aqc_fw_logging *cmd; 904 u16 i, chgs = 0, len = 0; 905 struct ice_aq_desc desc; 906 __le16 *data = NULL; 907 u8 actv_evnts = 0; 908 void *buf = NULL; 909 int status = 0; 910 911 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 912 return 0; 913 914 /* Disable FW logging only when the control queue is still responsive */ 915 if (!enable && 916 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 917 return 0; 918 919 /* Get current FW log settings */ 920 status = ice_get_fw_log_cfg(hw); 921 if (status) 922 return status; 923 924 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 925 cmd = &desc.params.fw_logging; 926 927 /* Indicate which controls are valid */ 928 if (hw->fw_log.cq_en) 929 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 930 931 if (hw->fw_log.uart_en) 932 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 933 934 if (enable) { 935 /* Fill in an array of entries with FW logging modules and 936 * logging events being reconfigured. 937 */ 938 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 939 u16 val; 940 941 /* Keep track of enabled event types */ 942 actv_evnts |= hw->fw_log.evnts[i].cfg; 943 944 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 945 continue; 946 947 if (!data) { 948 data = devm_kcalloc(ice_hw_to_dev(hw), 949 ICE_AQC_FW_LOG_ID_MAX, 950 sizeof(*data), 951 GFP_KERNEL); 952 if (!data) 953 return -ENOMEM; 954 } 955 956 val = i << ICE_AQC_FW_LOG_ID_S; 957 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 958 data[chgs++] = cpu_to_le16(val); 959 } 960 961 /* Only enable FW logging if at least one module is specified. 962 * If FW logging is currently enabled but all modules are not 963 * enabled to emit log messages, disable FW logging altogether. 964 */ 965 if (actv_evnts) { 966 /* Leave if there is effectively no change */ 967 if (!chgs) 968 goto out; 969 970 if (hw->fw_log.cq_en) 971 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 972 973 if (hw->fw_log.uart_en) 974 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 975 976 buf = data; 977 len = sizeof(*data) * chgs; 978 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 979 } 980 } 981 982 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 983 if (!status) { 984 /* Update the current configuration to reflect events enabled. 985 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 986 * logging mode is enabled for the device. They do not reflect 987 * actual modules being enabled to emit log messages. So, their 988 * values remain unchanged even when all modules are disabled. 989 */ 990 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 991 992 hw->fw_log.actv_evnts = actv_evnts; 993 for (i = 0; i < cnt; i++) { 994 u16 v, m; 995 996 if (!enable) { 997 /* When disabling all FW logging events as part 998 * of device's de-initialization, the original 999 * configurations are retained, and can be used 1000 * to reconfigure FW logging later if the device 1001 * is re-initialized. 1002 */ 1003 hw->fw_log.evnts[i].cur = 0; 1004 continue; 1005 } 1006 1007 v = le16_to_cpu(data[i]); 1008 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 1009 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 1010 } 1011 } 1012 1013 out: 1014 if (data) 1015 devm_kfree(ice_hw_to_dev(hw), data); 1016 1017 return status; 1018 } 1019 1020 /** 1021 * ice_output_fw_log 1022 * @hw: pointer to the HW struct 1023 * @desc: pointer to the AQ message descriptor 1024 * @buf: pointer to the buffer accompanying the AQ message 1025 * 1026 * Formats a FW Log message and outputs it via the standard driver logs. 1027 */ 1028 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 1029 { 1030 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 1031 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 1032 le16_to_cpu(desc->datalen)); 1033 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 1034 } 1035 1036 /** 1037 * ice_get_itr_intrl_gran 1038 * @hw: pointer to the HW struct 1039 * 1040 * Determines the ITR/INTRL granularities based on the maximum aggregate 1041 * bandwidth according to the device's configuration during power-on. 1042 */ 1043 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 1044 { 1045 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 1046 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 1047 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 1048 1049 switch (max_agg_bw) { 1050 case ICE_MAX_AGG_BW_200G: 1051 case ICE_MAX_AGG_BW_100G: 1052 case ICE_MAX_AGG_BW_50G: 1053 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 1054 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 1055 break; 1056 case ICE_MAX_AGG_BW_25G: 1057 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 1058 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 1059 break; 1060 } 1061 } 1062 1063 /** 1064 * ice_init_hw - main hardware initialization routine 1065 * @hw: pointer to the hardware structure 1066 */ 1067 int ice_init_hw(struct ice_hw *hw) 1068 { 1069 struct ice_aqc_get_phy_caps_data *pcaps; 1070 u16 mac_buf_len; 1071 void *mac_buf; 1072 int status; 1073 1074 /* Set MAC type based on DeviceID */ 1075 status = ice_set_mac_type(hw); 1076 if (status) 1077 return status; 1078 1079 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 1080 PF_FUNC_RID_FUNC_NUM_M) >> 1081 PF_FUNC_RID_FUNC_NUM_S; 1082 1083 status = ice_reset(hw, ICE_RESET_PFR); 1084 if (status) 1085 return status; 1086 1087 ice_get_itr_intrl_gran(hw); 1088 1089 status = ice_create_all_ctrlq(hw); 1090 if (status) 1091 goto err_unroll_cqinit; 1092 1093 /* Enable FW logging. Not fatal if this fails. */ 1094 status = ice_cfg_fw_log(hw, true); 1095 if (status) 1096 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 1097 1098 status = ice_clear_pf_cfg(hw); 1099 if (status) 1100 goto err_unroll_cqinit; 1101 1102 /* Set bit to enable Flow Director filters */ 1103 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1104 INIT_LIST_HEAD(&hw->fdir_list_head); 1105 1106 ice_clear_pxe_mode(hw); 1107 1108 status = ice_init_nvm(hw); 1109 if (status) 1110 goto err_unroll_cqinit; 1111 1112 status = ice_get_caps(hw); 1113 if (status) 1114 goto err_unroll_cqinit; 1115 1116 if (!hw->port_info) 1117 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1118 sizeof(*hw->port_info), 1119 GFP_KERNEL); 1120 if (!hw->port_info) { 1121 status = -ENOMEM; 1122 goto err_unroll_cqinit; 1123 } 1124 1125 /* set the back pointer to HW */ 1126 hw->port_info->hw = hw; 1127 1128 /* Initialize port_info struct with switch configuration data */ 1129 status = ice_get_initial_sw_cfg(hw); 1130 if (status) 1131 goto err_unroll_alloc; 1132 1133 hw->evb_veb = true; 1134 1135 /* init xarray for identifying scheduling nodes uniquely */ 1136 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); 1137 1138 /* Query the allocated resources for Tx scheduler */ 1139 status = ice_sched_query_res_alloc(hw); 1140 if (status) { 1141 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1142 goto err_unroll_alloc; 1143 } 1144 ice_sched_get_psm_clk_freq(hw); 1145 1146 /* Initialize port_info struct with scheduler data */ 1147 status = ice_sched_init_port(hw->port_info); 1148 if (status) 1149 goto err_unroll_sched; 1150 1151 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 1152 if (!pcaps) { 1153 status = -ENOMEM; 1154 goto err_unroll_sched; 1155 } 1156 1157 /* Initialize port_info struct with PHY capabilities */ 1158 status = ice_aq_get_phy_caps(hw->port_info, false, 1159 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1160 NULL); 1161 devm_kfree(ice_hw_to_dev(hw), pcaps); 1162 if (status) 1163 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1164 status); 1165 1166 /* Initialize port_info struct with link information */ 1167 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1168 if (status) 1169 goto err_unroll_sched; 1170 1171 /* need a valid SW entry point to build a Tx tree */ 1172 if (!hw->sw_entry_point_layer) { 1173 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1174 status = -EIO; 1175 goto err_unroll_sched; 1176 } 1177 INIT_LIST_HEAD(&hw->agg_list); 1178 /* Initialize max burst size */ 1179 if (!hw->max_burst_size) 1180 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1181 1182 status = ice_init_fltr_mgmt_struct(hw); 1183 if (status) 1184 goto err_unroll_sched; 1185 1186 /* Get MAC information */ 1187 /* A single port can report up to two (LAN and WoL) addresses */ 1188 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 1189 sizeof(struct ice_aqc_manage_mac_read_resp), 1190 GFP_KERNEL); 1191 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1192 1193 if (!mac_buf) { 1194 status = -ENOMEM; 1195 goto err_unroll_fltr_mgmt_struct; 1196 } 1197 1198 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1199 devm_kfree(ice_hw_to_dev(hw), mac_buf); 1200 1201 if (status) 1202 goto err_unroll_fltr_mgmt_struct; 1203 /* enable jumbo frame support at MAC level */ 1204 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1205 if (status) 1206 goto err_unroll_fltr_mgmt_struct; 1207 /* Obtain counter base index which would be used by flow director */ 1208 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1209 if (status) 1210 goto err_unroll_fltr_mgmt_struct; 1211 status = ice_init_hw_tbls(hw); 1212 if (status) 1213 goto err_unroll_fltr_mgmt_struct; 1214 mutex_init(&hw->tnl_lock); 1215 return 0; 1216 1217 err_unroll_fltr_mgmt_struct: 1218 ice_cleanup_fltr_mgmt_struct(hw); 1219 err_unroll_sched: 1220 ice_sched_cleanup_all(hw); 1221 err_unroll_alloc: 1222 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1223 err_unroll_cqinit: 1224 ice_destroy_all_ctrlq(hw); 1225 return status; 1226 } 1227 1228 /** 1229 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1230 * @hw: pointer to the hardware structure 1231 * 1232 * This should be called only during nominal operation, not as a result of 1233 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1234 * applicable initializations if it fails for any reason. 1235 */ 1236 void ice_deinit_hw(struct ice_hw *hw) 1237 { 1238 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1239 ice_cleanup_fltr_mgmt_struct(hw); 1240 1241 ice_sched_cleanup_all(hw); 1242 ice_sched_clear_agg(hw); 1243 ice_free_seg(hw); 1244 ice_free_hw_tbls(hw); 1245 mutex_destroy(&hw->tnl_lock); 1246 1247 /* Attempt to disable FW logging before shutting down control queues */ 1248 ice_cfg_fw_log(hw, false); 1249 ice_destroy_all_ctrlq(hw); 1250 1251 /* Clear VSI contexts if not already cleared */ 1252 ice_clear_all_vsi_ctx(hw); 1253 } 1254 1255 /** 1256 * ice_check_reset - Check to see if a global reset is complete 1257 * @hw: pointer to the hardware structure 1258 */ 1259 int ice_check_reset(struct ice_hw *hw) 1260 { 1261 u32 cnt, reg = 0, grst_timeout, uld_mask; 1262 1263 /* Poll for Device Active state in case a recent CORER, GLOBR, 1264 * or EMPR has occurred. The grst delay value is in 100ms units. 1265 * Add 1sec for outstanding AQ commands that can take a long time. 1266 */ 1267 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1268 GLGEN_RSTCTL_GRSTDEL_S) + 10; 1269 1270 for (cnt = 0; cnt < grst_timeout; cnt++) { 1271 mdelay(100); 1272 reg = rd32(hw, GLGEN_RSTAT); 1273 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1274 break; 1275 } 1276 1277 if (cnt == grst_timeout) { 1278 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1279 return -EIO; 1280 } 1281 1282 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1283 GLNVM_ULD_PCIER_DONE_1_M |\ 1284 GLNVM_ULD_CORER_DONE_M |\ 1285 GLNVM_ULD_GLOBR_DONE_M |\ 1286 GLNVM_ULD_POR_DONE_M |\ 1287 GLNVM_ULD_POR_DONE_1_M |\ 1288 GLNVM_ULD_PCIER_DONE_2_M) 1289 1290 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1291 GLNVM_ULD_PE_DONE_M : 0); 1292 1293 /* Device is Active; check Global Reset processes are done */ 1294 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1295 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1296 if (reg == uld_mask) { 1297 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1298 break; 1299 } 1300 mdelay(10); 1301 } 1302 1303 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1304 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1305 reg); 1306 return -EIO; 1307 } 1308 1309 return 0; 1310 } 1311 1312 /** 1313 * ice_pf_reset - Reset the PF 1314 * @hw: pointer to the hardware structure 1315 * 1316 * If a global reset has been triggered, this function checks 1317 * for its completion and then issues the PF reset 1318 */ 1319 static int ice_pf_reset(struct ice_hw *hw) 1320 { 1321 u32 cnt, reg; 1322 1323 /* If at function entry a global reset was already in progress, i.e. 1324 * state is not 'device active' or any of the reset done bits are not 1325 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1326 * global reset is done. 1327 */ 1328 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1329 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1330 /* poll on global reset currently in progress until done */ 1331 if (ice_check_reset(hw)) 1332 return -EIO; 1333 1334 return 0; 1335 } 1336 1337 /* Reset the PF */ 1338 reg = rd32(hw, PFGEN_CTRL); 1339 1340 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1341 1342 /* Wait for the PFR to complete. The wait time is the global config lock 1343 * timeout plus the PFR timeout which will account for a possible reset 1344 * that is occurring during a download package operation. 1345 */ 1346 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1347 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1348 reg = rd32(hw, PFGEN_CTRL); 1349 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1350 break; 1351 1352 mdelay(1); 1353 } 1354 1355 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1356 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1357 return -EIO; 1358 } 1359 1360 return 0; 1361 } 1362 1363 /** 1364 * ice_reset - Perform different types of reset 1365 * @hw: pointer to the hardware structure 1366 * @req: reset request 1367 * 1368 * This function triggers a reset as specified by the req parameter. 1369 * 1370 * Note: 1371 * If anything other than a PF reset is triggered, PXE mode is restored. 1372 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1373 * interface has been restored in the rebuild flow. 1374 */ 1375 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1376 { 1377 u32 val = 0; 1378 1379 switch (req) { 1380 case ICE_RESET_PFR: 1381 return ice_pf_reset(hw); 1382 case ICE_RESET_CORER: 1383 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1384 val = GLGEN_RTRIG_CORER_M; 1385 break; 1386 case ICE_RESET_GLOBR: 1387 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1388 val = GLGEN_RTRIG_GLOBR_M; 1389 break; 1390 default: 1391 return -EINVAL; 1392 } 1393 1394 val |= rd32(hw, GLGEN_RTRIG); 1395 wr32(hw, GLGEN_RTRIG, val); 1396 ice_flush(hw); 1397 1398 /* wait for the FW to be ready */ 1399 return ice_check_reset(hw); 1400 } 1401 1402 /** 1403 * ice_copy_rxq_ctx_to_hw 1404 * @hw: pointer to the hardware structure 1405 * @ice_rxq_ctx: pointer to the rxq context 1406 * @rxq_index: the index of the Rx queue 1407 * 1408 * Copies rxq context from dense structure to HW register space 1409 */ 1410 static int 1411 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1412 { 1413 u8 i; 1414 1415 if (!ice_rxq_ctx) 1416 return -EINVAL; 1417 1418 if (rxq_index > QRX_CTRL_MAX_INDEX) 1419 return -EINVAL; 1420 1421 /* Copy each dword separately to HW */ 1422 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1423 wr32(hw, QRX_CONTEXT(i, rxq_index), 1424 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1425 1426 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1427 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1428 } 1429 1430 return 0; 1431 } 1432 1433 /* LAN Rx Queue Context */ 1434 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1435 /* Field Width LSB */ 1436 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1437 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1438 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1439 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1440 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1441 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1442 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1443 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1444 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1445 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1446 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1447 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1448 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1449 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1450 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1451 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1452 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1453 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1454 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1455 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1456 { 0 } 1457 }; 1458 1459 /** 1460 * ice_write_rxq_ctx 1461 * @hw: pointer to the hardware structure 1462 * @rlan_ctx: pointer to the rxq context 1463 * @rxq_index: the index of the Rx queue 1464 * 1465 * Converts rxq context from sparse to dense structure and then writes 1466 * it to HW register space and enables the hardware to prefetch descriptors 1467 * instead of only fetching them on demand 1468 */ 1469 int 1470 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1471 u32 rxq_index) 1472 { 1473 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1474 1475 if (!rlan_ctx) 1476 return -EINVAL; 1477 1478 rlan_ctx->prefena = 1; 1479 1480 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1481 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1482 } 1483 1484 /* LAN Tx Queue Context */ 1485 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1486 /* Field Width LSB */ 1487 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1488 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1489 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1490 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1491 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1492 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1493 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1494 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1495 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1496 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1497 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1498 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1499 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1500 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1501 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1502 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1503 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1504 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1505 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1506 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1507 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1508 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1509 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1510 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1511 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1512 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1513 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1514 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1515 { 0 } 1516 }; 1517 1518 /* Sideband Queue command wrappers */ 1519 1520 /** 1521 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1522 * @hw: pointer to the HW struct 1523 * @desc: descriptor describing the command 1524 * @buf: buffer to use for indirect commands (NULL for direct commands) 1525 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1526 * @cd: pointer to command details structure 1527 */ 1528 static int 1529 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1530 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1531 { 1532 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1533 (struct ice_aq_desc *)desc, buf, buf_size, cd); 1534 } 1535 1536 /** 1537 * ice_sbq_rw_reg - Fill Sideband Queue command 1538 * @hw: pointer to the HW struct 1539 * @in: message info to be filled in descriptor 1540 */ 1541 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in) 1542 { 1543 struct ice_sbq_cmd_desc desc = {0}; 1544 struct ice_sbq_msg_req msg = {0}; 1545 u16 msg_len; 1546 int status; 1547 1548 msg_len = sizeof(msg); 1549 1550 msg.dest_dev = in->dest_dev; 1551 msg.opcode = in->opcode; 1552 msg.flags = ICE_SBQ_MSG_FLAGS; 1553 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1554 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1555 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1556 1557 if (in->opcode) 1558 msg.data = cpu_to_le32(in->data); 1559 else 1560 /* data read comes back in completion, so shorten the struct by 1561 * sizeof(msg.data) 1562 */ 1563 msg_len -= sizeof(msg.data); 1564 1565 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 1566 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1567 desc.param0.cmd_len = cpu_to_le16(msg_len); 1568 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1569 if (!status && !in->opcode) 1570 in->data = le32_to_cpu 1571 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1572 return status; 1573 } 1574 1575 /* FW Admin Queue command wrappers */ 1576 1577 /* Software lock/mutex that is meant to be held while the Global Config Lock 1578 * in firmware is acquired by the software to prevent most (but not all) types 1579 * of AQ commands from being sent to FW 1580 */ 1581 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1582 1583 /** 1584 * ice_should_retry_sq_send_cmd 1585 * @opcode: AQ opcode 1586 * 1587 * Decide if we should retry the send command routine for the ATQ, depending 1588 * on the opcode. 1589 */ 1590 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1591 { 1592 switch (opcode) { 1593 case ice_aqc_opc_get_link_topo: 1594 case ice_aqc_opc_lldp_stop: 1595 case ice_aqc_opc_lldp_start: 1596 case ice_aqc_opc_lldp_filter_ctrl: 1597 return true; 1598 } 1599 1600 return false; 1601 } 1602 1603 /** 1604 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1605 * @hw: pointer to the HW struct 1606 * @cq: pointer to the specific Control queue 1607 * @desc: prefilled descriptor describing the command 1608 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1609 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1610 * @cd: pointer to command details structure 1611 * 1612 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1613 * Queue if the EBUSY AQ error is returned. 1614 */ 1615 static int 1616 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1617 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1618 struct ice_sq_cd *cd) 1619 { 1620 struct ice_aq_desc desc_cpy; 1621 bool is_cmd_for_retry; 1622 u8 *buf_cpy = NULL; 1623 u8 idx = 0; 1624 u16 opcode; 1625 int status; 1626 1627 opcode = le16_to_cpu(desc->opcode); 1628 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1629 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1630 1631 if (is_cmd_for_retry) { 1632 if (buf) { 1633 buf_cpy = kzalloc(buf_size, GFP_KERNEL); 1634 if (!buf_cpy) 1635 return -ENOMEM; 1636 } 1637 1638 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1639 } 1640 1641 do { 1642 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1643 1644 if (!is_cmd_for_retry || !status || 1645 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1646 break; 1647 1648 if (buf_cpy) 1649 memcpy(buf, buf_cpy, buf_size); 1650 1651 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1652 1653 mdelay(ICE_SQ_SEND_DELAY_TIME_MS); 1654 1655 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1656 1657 kfree(buf_cpy); 1658 1659 return status; 1660 } 1661 1662 /** 1663 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1664 * @hw: pointer to the HW struct 1665 * @desc: descriptor describing the command 1666 * @buf: buffer to use for indirect commands (NULL for direct commands) 1667 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1668 * @cd: pointer to command details structure 1669 * 1670 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1671 */ 1672 int 1673 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1674 u16 buf_size, struct ice_sq_cd *cd) 1675 { 1676 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1677 bool lock_acquired = false; 1678 int status; 1679 1680 /* When a package download is in process (i.e. when the firmware's 1681 * Global Configuration Lock resource is held), only the Download 1682 * Package, Get Version, Get Package Info List, Upload Section, 1683 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1684 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1685 * Recipes to Profile Association, and Release Resource (with resource 1686 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1687 * must block until the package download completes and the Global Config 1688 * Lock is released. See also ice_acquire_global_cfg_lock(). 1689 */ 1690 switch (le16_to_cpu(desc->opcode)) { 1691 case ice_aqc_opc_download_pkg: 1692 case ice_aqc_opc_get_pkg_info_list: 1693 case ice_aqc_opc_get_ver: 1694 case ice_aqc_opc_upload_section: 1695 case ice_aqc_opc_update_pkg: 1696 case ice_aqc_opc_set_port_params: 1697 case ice_aqc_opc_get_vlan_mode_parameters: 1698 case ice_aqc_opc_set_vlan_mode_parameters: 1699 case ice_aqc_opc_add_recipe: 1700 case ice_aqc_opc_recipe_to_profile: 1701 case ice_aqc_opc_get_recipe: 1702 case ice_aqc_opc_get_recipe_to_profile: 1703 break; 1704 case ice_aqc_opc_release_res: 1705 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1706 break; 1707 fallthrough; 1708 default: 1709 mutex_lock(&ice_global_cfg_lock_sw); 1710 lock_acquired = true; 1711 break; 1712 } 1713 1714 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1715 if (lock_acquired) 1716 mutex_unlock(&ice_global_cfg_lock_sw); 1717 1718 return status; 1719 } 1720 1721 /** 1722 * ice_aq_get_fw_ver 1723 * @hw: pointer to the HW struct 1724 * @cd: pointer to command details structure or NULL 1725 * 1726 * Get the firmware version (0x0001) from the admin queue commands 1727 */ 1728 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1729 { 1730 struct ice_aqc_get_ver *resp; 1731 struct ice_aq_desc desc; 1732 int status; 1733 1734 resp = &desc.params.get_ver; 1735 1736 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1737 1738 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1739 1740 if (!status) { 1741 hw->fw_branch = resp->fw_branch; 1742 hw->fw_maj_ver = resp->fw_major; 1743 hw->fw_min_ver = resp->fw_minor; 1744 hw->fw_patch = resp->fw_patch; 1745 hw->fw_build = le32_to_cpu(resp->fw_build); 1746 hw->api_branch = resp->api_branch; 1747 hw->api_maj_ver = resp->api_major; 1748 hw->api_min_ver = resp->api_minor; 1749 hw->api_patch = resp->api_patch; 1750 } 1751 1752 return status; 1753 } 1754 1755 /** 1756 * ice_aq_send_driver_ver 1757 * @hw: pointer to the HW struct 1758 * @dv: driver's major, minor version 1759 * @cd: pointer to command details structure or NULL 1760 * 1761 * Send the driver version (0x0002) to the firmware 1762 */ 1763 int 1764 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1765 struct ice_sq_cd *cd) 1766 { 1767 struct ice_aqc_driver_ver *cmd; 1768 struct ice_aq_desc desc; 1769 u16 len; 1770 1771 cmd = &desc.params.driver_ver; 1772 1773 if (!dv) 1774 return -EINVAL; 1775 1776 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1777 1778 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1779 cmd->major_ver = dv->major_ver; 1780 cmd->minor_ver = dv->minor_ver; 1781 cmd->build_ver = dv->build_ver; 1782 cmd->subbuild_ver = dv->subbuild_ver; 1783 1784 len = 0; 1785 while (len < sizeof(dv->driver_string) && 1786 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1787 len++; 1788 1789 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1790 } 1791 1792 /** 1793 * ice_aq_q_shutdown 1794 * @hw: pointer to the HW struct 1795 * @unloading: is the driver unloading itself 1796 * 1797 * Tell the Firmware that we're shutting down the AdminQ and whether 1798 * or not the driver is unloading as well (0x0003). 1799 */ 1800 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1801 { 1802 struct ice_aqc_q_shutdown *cmd; 1803 struct ice_aq_desc desc; 1804 1805 cmd = &desc.params.q_shutdown; 1806 1807 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1808 1809 if (unloading) 1810 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1811 1812 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1813 } 1814 1815 /** 1816 * ice_aq_req_res 1817 * @hw: pointer to the HW struct 1818 * @res: resource ID 1819 * @access: access type 1820 * @sdp_number: resource number 1821 * @timeout: the maximum time in ms that the driver may hold the resource 1822 * @cd: pointer to command details structure or NULL 1823 * 1824 * Requests common resource using the admin queue commands (0x0008). 1825 * When attempting to acquire the Global Config Lock, the driver can 1826 * learn of three states: 1827 * 1) 0 - acquired lock, and can perform download package 1828 * 2) -EIO - did not get lock, driver should fail to load 1829 * 3) -EALREADY - did not get lock, but another driver has 1830 * successfully downloaded the package; the driver does 1831 * not have to download the package and can continue 1832 * loading 1833 * 1834 * Note that if the caller is in an acquire lock, perform action, release lock 1835 * phase of operation, it is possible that the FW may detect a timeout and issue 1836 * a CORER. In this case, the driver will receive a CORER interrupt and will 1837 * have to determine its cause. The calling thread that is handling this flow 1838 * will likely get an error propagated back to it indicating the Download 1839 * Package, Update Package or the Release Resource AQ commands timed out. 1840 */ 1841 static int 1842 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1843 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1844 struct ice_sq_cd *cd) 1845 { 1846 struct ice_aqc_req_res *cmd_resp; 1847 struct ice_aq_desc desc; 1848 int status; 1849 1850 cmd_resp = &desc.params.res_owner; 1851 1852 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1853 1854 cmd_resp->res_id = cpu_to_le16(res); 1855 cmd_resp->access_type = cpu_to_le16(access); 1856 cmd_resp->res_number = cpu_to_le32(sdp_number); 1857 cmd_resp->timeout = cpu_to_le32(*timeout); 1858 *timeout = 0; 1859 1860 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1861 1862 /* The completion specifies the maximum time in ms that the driver 1863 * may hold the resource in the Timeout field. 1864 */ 1865 1866 /* Global config lock response utilizes an additional status field. 1867 * 1868 * If the Global config lock resource is held by some other driver, the 1869 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1870 * and the timeout field indicates the maximum time the current owner 1871 * of the resource has to free it. 1872 */ 1873 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1874 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1875 *timeout = le32_to_cpu(cmd_resp->timeout); 1876 return 0; 1877 } else if (le16_to_cpu(cmd_resp->status) == 1878 ICE_AQ_RES_GLBL_IN_PROG) { 1879 *timeout = le32_to_cpu(cmd_resp->timeout); 1880 return -EIO; 1881 } else if (le16_to_cpu(cmd_resp->status) == 1882 ICE_AQ_RES_GLBL_DONE) { 1883 return -EALREADY; 1884 } 1885 1886 /* invalid FW response, force a timeout immediately */ 1887 *timeout = 0; 1888 return -EIO; 1889 } 1890 1891 /* If the resource is held by some other driver, the command completes 1892 * with a busy return value and the timeout field indicates the maximum 1893 * time the current owner of the resource has to free it. 1894 */ 1895 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1896 *timeout = le32_to_cpu(cmd_resp->timeout); 1897 1898 return status; 1899 } 1900 1901 /** 1902 * ice_aq_release_res 1903 * @hw: pointer to the HW struct 1904 * @res: resource ID 1905 * @sdp_number: resource number 1906 * @cd: pointer to command details structure or NULL 1907 * 1908 * release common resource using the admin queue commands (0x0009) 1909 */ 1910 static int 1911 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1912 struct ice_sq_cd *cd) 1913 { 1914 struct ice_aqc_req_res *cmd; 1915 struct ice_aq_desc desc; 1916 1917 cmd = &desc.params.res_owner; 1918 1919 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1920 1921 cmd->res_id = cpu_to_le16(res); 1922 cmd->res_number = cpu_to_le32(sdp_number); 1923 1924 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1925 } 1926 1927 /** 1928 * ice_acquire_res 1929 * @hw: pointer to the HW structure 1930 * @res: resource ID 1931 * @access: access type (read or write) 1932 * @timeout: timeout in milliseconds 1933 * 1934 * This function will attempt to acquire the ownership of a resource. 1935 */ 1936 int 1937 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1938 enum ice_aq_res_access_type access, u32 timeout) 1939 { 1940 #define ICE_RES_POLLING_DELAY_MS 10 1941 u32 delay = ICE_RES_POLLING_DELAY_MS; 1942 u32 time_left = timeout; 1943 int status; 1944 1945 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1946 1947 /* A return code of -EALREADY means that another driver has 1948 * previously acquired the resource and performed any necessary updates; 1949 * in this case the caller does not obtain the resource and has no 1950 * further work to do. 1951 */ 1952 if (status == -EALREADY) 1953 goto ice_acquire_res_exit; 1954 1955 if (status) 1956 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1957 1958 /* If necessary, poll until the current lock owner timeouts */ 1959 timeout = time_left; 1960 while (status && timeout && time_left) { 1961 mdelay(delay); 1962 timeout = (timeout > delay) ? timeout - delay : 0; 1963 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1964 1965 if (status == -EALREADY) 1966 /* lock free, but no work to do */ 1967 break; 1968 1969 if (!status) 1970 /* lock acquired */ 1971 break; 1972 } 1973 if (status && status != -EALREADY) 1974 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1975 1976 ice_acquire_res_exit: 1977 if (status == -EALREADY) { 1978 if (access == ICE_RES_WRITE) 1979 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1980 else 1981 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 1982 } 1983 return status; 1984 } 1985 1986 /** 1987 * ice_release_res 1988 * @hw: pointer to the HW structure 1989 * @res: resource ID 1990 * 1991 * This function will release a resource using the proper Admin Command. 1992 */ 1993 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1994 { 1995 u32 total_delay = 0; 1996 int status; 1997 1998 status = ice_aq_release_res(hw, res, 0, NULL); 1999 2000 /* there are some rare cases when trying to release the resource 2001 * results in an admin queue timeout, so handle them correctly 2002 */ 2003 while ((status == -EIO) && (total_delay < hw->adminq.sq_cmd_timeout)) { 2004 mdelay(1); 2005 status = ice_aq_release_res(hw, res, 0, NULL); 2006 total_delay++; 2007 } 2008 } 2009 2010 /** 2011 * ice_aq_alloc_free_res - command to allocate/free resources 2012 * @hw: pointer to the HW struct 2013 * @num_entries: number of resource entries in buffer 2014 * @buf: Indirect buffer to hold data parameters and response 2015 * @buf_size: size of buffer for indirect commands 2016 * @opc: pass in the command opcode 2017 * @cd: pointer to command details structure or NULL 2018 * 2019 * Helper function to allocate/free resources using the admin queue commands 2020 */ 2021 int 2022 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 2023 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 2024 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2025 { 2026 struct ice_aqc_alloc_free_res_cmd *cmd; 2027 struct ice_aq_desc desc; 2028 2029 cmd = &desc.params.sw_res_ctrl; 2030 2031 if (!buf) 2032 return -EINVAL; 2033 2034 if (buf_size < flex_array_size(buf, elem, num_entries)) 2035 return -EINVAL; 2036 2037 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2038 2039 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2040 2041 cmd->num_entries = cpu_to_le16(num_entries); 2042 2043 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2044 } 2045 2046 /** 2047 * ice_alloc_hw_res - allocate resource 2048 * @hw: pointer to the HW struct 2049 * @type: type of resource 2050 * @num: number of resources to allocate 2051 * @btm: allocate from bottom 2052 * @res: pointer to array that will receive the resources 2053 */ 2054 int 2055 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2056 { 2057 struct ice_aqc_alloc_free_res_elem *buf; 2058 u16 buf_len; 2059 int status; 2060 2061 buf_len = struct_size(buf, elem, num); 2062 buf = kzalloc(buf_len, GFP_KERNEL); 2063 if (!buf) 2064 return -ENOMEM; 2065 2066 /* Prepare buffer to allocate resource. */ 2067 buf->num_elems = cpu_to_le16(num); 2068 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2069 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2070 if (btm) 2071 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2072 2073 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 2074 ice_aqc_opc_alloc_res, NULL); 2075 if (status) 2076 goto ice_alloc_res_exit; 2077 2078 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2079 2080 ice_alloc_res_exit: 2081 kfree(buf); 2082 return status; 2083 } 2084 2085 /** 2086 * ice_free_hw_res - free allocated HW resource 2087 * @hw: pointer to the HW struct 2088 * @type: type of resource to free 2089 * @num: number of resources 2090 * @res: pointer to array that contains the resources to free 2091 */ 2092 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2093 { 2094 struct ice_aqc_alloc_free_res_elem *buf; 2095 u16 buf_len; 2096 int status; 2097 2098 buf_len = struct_size(buf, elem, num); 2099 buf = kzalloc(buf_len, GFP_KERNEL); 2100 if (!buf) 2101 return -ENOMEM; 2102 2103 /* Prepare buffer to free resource. */ 2104 buf->num_elems = cpu_to_le16(num); 2105 buf->res_type = cpu_to_le16(type); 2106 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2107 2108 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 2109 ice_aqc_opc_free_res, NULL); 2110 if (status) 2111 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2112 2113 kfree(buf); 2114 return status; 2115 } 2116 2117 /** 2118 * ice_get_num_per_func - determine number of resources per PF 2119 * @hw: pointer to the HW structure 2120 * @max: value to be evenly split between each PF 2121 * 2122 * Determine the number of valid functions by going through the bitmap returned 2123 * from parsing capabilities and use this to calculate the number of resources 2124 * per PF based on the max value passed in. 2125 */ 2126 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2127 { 2128 u8 funcs; 2129 2130 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2131 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2132 ICE_CAPS_VALID_FUNCS_M); 2133 2134 if (!funcs) 2135 return 0; 2136 2137 return max / funcs; 2138 } 2139 2140 /** 2141 * ice_parse_common_caps - parse common device/function capabilities 2142 * @hw: pointer to the HW struct 2143 * @caps: pointer to common capabilities structure 2144 * @elem: the capability element to parse 2145 * @prefix: message prefix for tracing capabilities 2146 * 2147 * Given a capability element, extract relevant details into the common 2148 * capability structure. 2149 * 2150 * Returns: true if the capability matches one of the common capability ids, 2151 * false otherwise. 2152 */ 2153 static bool 2154 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2155 struct ice_aqc_list_caps_elem *elem, const char *prefix) 2156 { 2157 u32 logical_id = le32_to_cpu(elem->logical_id); 2158 u32 phys_id = le32_to_cpu(elem->phys_id); 2159 u32 number = le32_to_cpu(elem->number); 2160 u16 cap = le16_to_cpu(elem->cap); 2161 bool found = true; 2162 2163 switch (cap) { 2164 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2165 caps->valid_functions = number; 2166 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2167 caps->valid_functions); 2168 break; 2169 case ICE_AQC_CAPS_SRIOV: 2170 caps->sr_iov_1_1 = (number == 1); 2171 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2172 caps->sr_iov_1_1); 2173 break; 2174 case ICE_AQC_CAPS_DCB: 2175 caps->dcb = (number == 1); 2176 caps->active_tc_bitmap = logical_id; 2177 caps->maxtc = phys_id; 2178 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2179 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2180 caps->active_tc_bitmap); 2181 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2182 break; 2183 case ICE_AQC_CAPS_RSS: 2184 caps->rss_table_size = number; 2185 caps->rss_table_entry_width = logical_id; 2186 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2187 caps->rss_table_size); 2188 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2189 caps->rss_table_entry_width); 2190 break; 2191 case ICE_AQC_CAPS_RXQS: 2192 caps->num_rxq = number; 2193 caps->rxq_first_id = phys_id; 2194 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2195 caps->num_rxq); 2196 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2197 caps->rxq_first_id); 2198 break; 2199 case ICE_AQC_CAPS_TXQS: 2200 caps->num_txq = number; 2201 caps->txq_first_id = phys_id; 2202 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2203 caps->num_txq); 2204 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2205 caps->txq_first_id); 2206 break; 2207 case ICE_AQC_CAPS_MSIX: 2208 caps->num_msix_vectors = number; 2209 caps->msix_vector_first_id = phys_id; 2210 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2211 caps->num_msix_vectors); 2212 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2213 caps->msix_vector_first_id); 2214 break; 2215 case ICE_AQC_CAPS_PENDING_NVM_VER: 2216 caps->nvm_update_pending_nvm = true; 2217 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2218 break; 2219 case ICE_AQC_CAPS_PENDING_OROM_VER: 2220 caps->nvm_update_pending_orom = true; 2221 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2222 break; 2223 case ICE_AQC_CAPS_PENDING_NET_VER: 2224 caps->nvm_update_pending_netlist = true; 2225 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2226 break; 2227 case ICE_AQC_CAPS_NVM_MGMT: 2228 caps->nvm_unified_update = 2229 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2230 true : false; 2231 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2232 caps->nvm_unified_update); 2233 break; 2234 case ICE_AQC_CAPS_RDMA: 2235 caps->rdma = (number == 1); 2236 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2237 break; 2238 case ICE_AQC_CAPS_MAX_MTU: 2239 caps->max_mtu = number; 2240 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2241 prefix, caps->max_mtu); 2242 break; 2243 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2244 caps->pcie_reset_avoidance = (number > 0); 2245 ice_debug(hw, ICE_DBG_INIT, 2246 "%s: pcie_reset_avoidance = %d\n", prefix, 2247 caps->pcie_reset_avoidance); 2248 break; 2249 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2250 caps->reset_restrict_support = (number == 1); 2251 ice_debug(hw, ICE_DBG_INIT, 2252 "%s: reset_restrict_support = %d\n", prefix, 2253 caps->reset_restrict_support); 2254 break; 2255 default: 2256 /* Not one of the recognized common capabilities */ 2257 found = false; 2258 } 2259 2260 return found; 2261 } 2262 2263 /** 2264 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2265 * @hw: pointer to the HW structure 2266 * @caps: pointer to capabilities structure to fix 2267 * 2268 * Re-calculate the capabilities that are dependent on the number of physical 2269 * ports; i.e. some features are not supported or function differently on 2270 * devices with more than 4 ports. 2271 */ 2272 static void 2273 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2274 { 2275 /* This assumes device capabilities are always scanned before function 2276 * capabilities during the initialization flow. 2277 */ 2278 if (hw->dev_caps.num_funcs > 4) { 2279 /* Max 4 TCs per port */ 2280 caps->maxtc = 4; 2281 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2282 caps->maxtc); 2283 if (caps->rdma) { 2284 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2285 caps->rdma = 0; 2286 } 2287 2288 /* print message only when processing device capabilities 2289 * during initialization. 2290 */ 2291 if (caps == &hw->dev_caps.common_cap) 2292 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2293 } 2294 } 2295 2296 /** 2297 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2298 * @hw: pointer to the HW struct 2299 * @func_p: pointer to function capabilities structure 2300 * @cap: pointer to the capability element to parse 2301 * 2302 * Extract function capabilities for ICE_AQC_CAPS_VF. 2303 */ 2304 static void 2305 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2306 struct ice_aqc_list_caps_elem *cap) 2307 { 2308 u32 logical_id = le32_to_cpu(cap->logical_id); 2309 u32 number = le32_to_cpu(cap->number); 2310 2311 func_p->num_allocd_vfs = number; 2312 func_p->vf_base_id = logical_id; 2313 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2314 func_p->num_allocd_vfs); 2315 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2316 func_p->vf_base_id); 2317 } 2318 2319 /** 2320 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2321 * @hw: pointer to the HW struct 2322 * @func_p: pointer to function capabilities structure 2323 * @cap: pointer to the capability element to parse 2324 * 2325 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2326 */ 2327 static void 2328 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2329 struct ice_aqc_list_caps_elem *cap) 2330 { 2331 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2332 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2333 le32_to_cpu(cap->number)); 2334 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2335 func_p->guar_num_vsi); 2336 } 2337 2338 /** 2339 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2340 * @hw: pointer to the HW struct 2341 * @func_p: pointer to function capabilities structure 2342 * @cap: pointer to the capability element to parse 2343 * 2344 * Extract function capabilities for ICE_AQC_CAPS_1588. 2345 */ 2346 static void 2347 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2348 struct ice_aqc_list_caps_elem *cap) 2349 { 2350 struct ice_ts_func_info *info = &func_p->ts_func_info; 2351 u32 number = le32_to_cpu(cap->number); 2352 2353 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2354 func_p->common_cap.ieee_1588 = info->ena; 2355 2356 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2357 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2358 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2359 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2360 2361 info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S; 2362 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2363 2364 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { 2365 info->time_ref = (enum ice_time_ref_freq)info->clk_freq; 2366 } else { 2367 /* Unknown clock frequency, so assume a (probably incorrect) 2368 * default to avoid out-of-bounds look ups of frequency 2369 * related information. 2370 */ 2371 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2372 info->clk_freq); 2373 info->time_ref = ICE_TIME_REF_FREQ_25_000; 2374 } 2375 2376 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2377 func_p->common_cap.ieee_1588); 2378 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2379 info->src_tmr_owned); 2380 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2381 info->tmr_ena); 2382 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2383 info->tmr_index_owned); 2384 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2385 info->tmr_index_assoc); 2386 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2387 info->clk_freq); 2388 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2389 info->clk_src); 2390 } 2391 2392 /** 2393 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2394 * @hw: pointer to the HW struct 2395 * @func_p: pointer to function capabilities structure 2396 * 2397 * Extract function capabilities for ICE_AQC_CAPS_FD. 2398 */ 2399 static void 2400 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2401 { 2402 u32 reg_val, val; 2403 2404 reg_val = rd32(hw, GLQF_FD_SIZE); 2405 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2406 GLQF_FD_SIZE_FD_GSIZE_S; 2407 func_p->fd_fltr_guar = 2408 ice_get_num_per_func(hw, val); 2409 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2410 GLQF_FD_SIZE_FD_BSIZE_S; 2411 func_p->fd_fltr_best_effort = val; 2412 2413 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2414 func_p->fd_fltr_guar); 2415 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2416 func_p->fd_fltr_best_effort); 2417 } 2418 2419 /** 2420 * ice_parse_func_caps - Parse function capabilities 2421 * @hw: pointer to the HW struct 2422 * @func_p: pointer to function capabilities structure 2423 * @buf: buffer containing the function capability records 2424 * @cap_count: the number of capabilities 2425 * 2426 * Helper function to parse function (0x000A) capabilities list. For 2427 * capabilities shared between device and function, this relies on 2428 * ice_parse_common_caps. 2429 * 2430 * Loop through the list of provided capabilities and extract the relevant 2431 * data into the function capabilities structured. 2432 */ 2433 static void 2434 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2435 void *buf, u32 cap_count) 2436 { 2437 struct ice_aqc_list_caps_elem *cap_resp; 2438 u32 i; 2439 2440 cap_resp = buf; 2441 2442 memset(func_p, 0, sizeof(*func_p)); 2443 2444 for (i = 0; i < cap_count; i++) { 2445 u16 cap = le16_to_cpu(cap_resp[i].cap); 2446 bool found; 2447 2448 found = ice_parse_common_caps(hw, &func_p->common_cap, 2449 &cap_resp[i], "func caps"); 2450 2451 switch (cap) { 2452 case ICE_AQC_CAPS_VF: 2453 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2454 break; 2455 case ICE_AQC_CAPS_VSI: 2456 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2457 break; 2458 case ICE_AQC_CAPS_1588: 2459 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2460 break; 2461 case ICE_AQC_CAPS_FD: 2462 ice_parse_fdir_func_caps(hw, func_p); 2463 break; 2464 default: 2465 /* Don't list common capabilities as unknown */ 2466 if (!found) 2467 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2468 i, cap); 2469 break; 2470 } 2471 } 2472 2473 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2474 } 2475 2476 /** 2477 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2478 * @hw: pointer to the HW struct 2479 * @dev_p: pointer to device capabilities structure 2480 * @cap: capability element to parse 2481 * 2482 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2483 */ 2484 static void 2485 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2486 struct ice_aqc_list_caps_elem *cap) 2487 { 2488 u32 number = le32_to_cpu(cap->number); 2489 2490 dev_p->num_funcs = hweight32(number); 2491 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2492 dev_p->num_funcs); 2493 } 2494 2495 /** 2496 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2497 * @hw: pointer to the HW struct 2498 * @dev_p: pointer to device capabilities structure 2499 * @cap: capability element to parse 2500 * 2501 * Parse ICE_AQC_CAPS_VF for device capabilities. 2502 */ 2503 static void 2504 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2505 struct ice_aqc_list_caps_elem *cap) 2506 { 2507 u32 number = le32_to_cpu(cap->number); 2508 2509 dev_p->num_vfs_exposed = number; 2510 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2511 dev_p->num_vfs_exposed); 2512 } 2513 2514 /** 2515 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2516 * @hw: pointer to the HW struct 2517 * @dev_p: pointer to device capabilities structure 2518 * @cap: capability element to parse 2519 * 2520 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2521 */ 2522 static void 2523 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2524 struct ice_aqc_list_caps_elem *cap) 2525 { 2526 u32 number = le32_to_cpu(cap->number); 2527 2528 dev_p->num_vsi_allocd_to_host = number; 2529 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2530 dev_p->num_vsi_allocd_to_host); 2531 } 2532 2533 /** 2534 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2535 * @hw: pointer to the HW struct 2536 * @dev_p: pointer to device capabilities structure 2537 * @cap: capability element to parse 2538 * 2539 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2540 */ 2541 static void 2542 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2543 struct ice_aqc_list_caps_elem *cap) 2544 { 2545 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2546 u32 logical_id = le32_to_cpu(cap->logical_id); 2547 u32 phys_id = le32_to_cpu(cap->phys_id); 2548 u32 number = le32_to_cpu(cap->number); 2549 2550 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2551 dev_p->common_cap.ieee_1588 = info->ena; 2552 2553 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2554 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2555 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2556 2557 info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S; 2558 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2559 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2560 2561 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2562 2563 info->ena_ports = logical_id; 2564 info->tmr_own_map = phys_id; 2565 2566 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2567 dev_p->common_cap.ieee_1588); 2568 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2569 info->tmr0_owner); 2570 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2571 info->tmr0_owned); 2572 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2573 info->tmr0_ena); 2574 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2575 info->tmr1_owner); 2576 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2577 info->tmr1_owned); 2578 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2579 info->tmr1_ena); 2580 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2581 info->ts_ll_read); 2582 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2583 info->ena_ports); 2584 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2585 info->tmr_own_map); 2586 } 2587 2588 /** 2589 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2590 * @hw: pointer to the HW struct 2591 * @dev_p: pointer to device capabilities structure 2592 * @cap: capability element to parse 2593 * 2594 * Parse ICE_AQC_CAPS_FD for device capabilities. 2595 */ 2596 static void 2597 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2598 struct ice_aqc_list_caps_elem *cap) 2599 { 2600 u32 number = le32_to_cpu(cap->number); 2601 2602 dev_p->num_flow_director_fltr = number; 2603 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2604 dev_p->num_flow_director_fltr); 2605 } 2606 2607 /** 2608 * ice_parse_dev_caps - Parse device capabilities 2609 * @hw: pointer to the HW struct 2610 * @dev_p: pointer to device capabilities structure 2611 * @buf: buffer containing the device capability records 2612 * @cap_count: the number of capabilities 2613 * 2614 * Helper device to parse device (0x000B) capabilities list. For 2615 * capabilities shared between device and function, this relies on 2616 * ice_parse_common_caps. 2617 * 2618 * Loop through the list of provided capabilities and extract the relevant 2619 * data into the device capabilities structured. 2620 */ 2621 static void 2622 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2623 void *buf, u32 cap_count) 2624 { 2625 struct ice_aqc_list_caps_elem *cap_resp; 2626 u32 i; 2627 2628 cap_resp = buf; 2629 2630 memset(dev_p, 0, sizeof(*dev_p)); 2631 2632 for (i = 0; i < cap_count; i++) { 2633 u16 cap = le16_to_cpu(cap_resp[i].cap); 2634 bool found; 2635 2636 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2637 &cap_resp[i], "dev caps"); 2638 2639 switch (cap) { 2640 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2641 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2642 break; 2643 case ICE_AQC_CAPS_VF: 2644 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2645 break; 2646 case ICE_AQC_CAPS_VSI: 2647 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2648 break; 2649 case ICE_AQC_CAPS_1588: 2650 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2651 break; 2652 case ICE_AQC_CAPS_FD: 2653 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2654 break; 2655 default: 2656 /* Don't list common capabilities as unknown */ 2657 if (!found) 2658 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2659 i, cap); 2660 break; 2661 } 2662 } 2663 2664 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2665 } 2666 2667 /** 2668 * ice_aq_list_caps - query function/device capabilities 2669 * @hw: pointer to the HW struct 2670 * @buf: a buffer to hold the capabilities 2671 * @buf_size: size of the buffer 2672 * @cap_count: if not NULL, set to the number of capabilities reported 2673 * @opc: capabilities type to discover, device or function 2674 * @cd: pointer to command details structure or NULL 2675 * 2676 * Get the function (0x000A) or device (0x000B) capabilities description from 2677 * firmware and store it in the buffer. 2678 * 2679 * If the cap_count pointer is not NULL, then it is set to the number of 2680 * capabilities firmware will report. Note that if the buffer size is too 2681 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2682 * cap_count will still be updated in this case. It is recommended that the 2683 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2684 * firmware could return) to avoid this. 2685 */ 2686 int 2687 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2688 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2689 { 2690 struct ice_aqc_list_caps *cmd; 2691 struct ice_aq_desc desc; 2692 int status; 2693 2694 cmd = &desc.params.get_cap; 2695 2696 if (opc != ice_aqc_opc_list_func_caps && 2697 opc != ice_aqc_opc_list_dev_caps) 2698 return -EINVAL; 2699 2700 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2701 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2702 2703 if (cap_count) 2704 *cap_count = le32_to_cpu(cmd->count); 2705 2706 return status; 2707 } 2708 2709 /** 2710 * ice_discover_dev_caps - Read and extract device capabilities 2711 * @hw: pointer to the hardware structure 2712 * @dev_caps: pointer to device capabilities structure 2713 * 2714 * Read the device capabilities and extract them into the dev_caps structure 2715 * for later use. 2716 */ 2717 int 2718 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2719 { 2720 u32 cap_count = 0; 2721 void *cbuf; 2722 int status; 2723 2724 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2725 if (!cbuf) 2726 return -ENOMEM; 2727 2728 /* Although the driver doesn't know the number of capabilities the 2729 * device will return, we can simply send a 4KB buffer, the maximum 2730 * possible size that firmware can return. 2731 */ 2732 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2733 2734 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2735 ice_aqc_opc_list_dev_caps, NULL); 2736 if (!status) 2737 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2738 kfree(cbuf); 2739 2740 return status; 2741 } 2742 2743 /** 2744 * ice_discover_func_caps - Read and extract function capabilities 2745 * @hw: pointer to the hardware structure 2746 * @func_caps: pointer to function capabilities structure 2747 * 2748 * Read the function capabilities and extract them into the func_caps structure 2749 * for later use. 2750 */ 2751 static int 2752 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2753 { 2754 u32 cap_count = 0; 2755 void *cbuf; 2756 int status; 2757 2758 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2759 if (!cbuf) 2760 return -ENOMEM; 2761 2762 /* Although the driver doesn't know the number of capabilities the 2763 * device will return, we can simply send a 4KB buffer, the maximum 2764 * possible size that firmware can return. 2765 */ 2766 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2767 2768 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2769 ice_aqc_opc_list_func_caps, NULL); 2770 if (!status) 2771 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2772 kfree(cbuf); 2773 2774 return status; 2775 } 2776 2777 /** 2778 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2779 * @hw: pointer to the hardware structure 2780 */ 2781 void ice_set_safe_mode_caps(struct ice_hw *hw) 2782 { 2783 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2784 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2785 struct ice_hw_common_caps cached_caps; 2786 u32 num_funcs; 2787 2788 /* cache some func_caps values that should be restored after memset */ 2789 cached_caps = func_caps->common_cap; 2790 2791 /* unset func capabilities */ 2792 memset(func_caps, 0, sizeof(*func_caps)); 2793 2794 #define ICE_RESTORE_FUNC_CAP(name) \ 2795 func_caps->common_cap.name = cached_caps.name 2796 2797 /* restore cached values */ 2798 ICE_RESTORE_FUNC_CAP(valid_functions); 2799 ICE_RESTORE_FUNC_CAP(txq_first_id); 2800 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2801 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2802 ICE_RESTORE_FUNC_CAP(max_mtu); 2803 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2804 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2805 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2806 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2807 2808 /* one Tx and one Rx queue in safe mode */ 2809 func_caps->common_cap.num_rxq = 1; 2810 func_caps->common_cap.num_txq = 1; 2811 2812 /* two MSIX vectors, one for traffic and one for misc causes */ 2813 func_caps->common_cap.num_msix_vectors = 2; 2814 func_caps->guar_num_vsi = 1; 2815 2816 /* cache some dev_caps values that should be restored after memset */ 2817 cached_caps = dev_caps->common_cap; 2818 num_funcs = dev_caps->num_funcs; 2819 2820 /* unset dev capabilities */ 2821 memset(dev_caps, 0, sizeof(*dev_caps)); 2822 2823 #define ICE_RESTORE_DEV_CAP(name) \ 2824 dev_caps->common_cap.name = cached_caps.name 2825 2826 /* restore cached values */ 2827 ICE_RESTORE_DEV_CAP(valid_functions); 2828 ICE_RESTORE_DEV_CAP(txq_first_id); 2829 ICE_RESTORE_DEV_CAP(rxq_first_id); 2830 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2831 ICE_RESTORE_DEV_CAP(max_mtu); 2832 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2833 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 2834 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 2835 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 2836 dev_caps->num_funcs = num_funcs; 2837 2838 /* one Tx and one Rx queue per function in safe mode */ 2839 dev_caps->common_cap.num_rxq = num_funcs; 2840 dev_caps->common_cap.num_txq = num_funcs; 2841 2842 /* two MSIX vectors per function */ 2843 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2844 } 2845 2846 /** 2847 * ice_get_caps - get info about the HW 2848 * @hw: pointer to the hardware structure 2849 */ 2850 int ice_get_caps(struct ice_hw *hw) 2851 { 2852 int status; 2853 2854 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2855 if (status) 2856 return status; 2857 2858 return ice_discover_func_caps(hw, &hw->func_caps); 2859 } 2860 2861 /** 2862 * ice_aq_manage_mac_write - manage MAC address write command 2863 * @hw: pointer to the HW struct 2864 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2865 * @flags: flags to control write behavior 2866 * @cd: pointer to command details structure or NULL 2867 * 2868 * This function is used to write MAC address to the NVM (0x0108). 2869 */ 2870 int 2871 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2872 struct ice_sq_cd *cd) 2873 { 2874 struct ice_aqc_manage_mac_write *cmd; 2875 struct ice_aq_desc desc; 2876 2877 cmd = &desc.params.mac_write; 2878 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2879 2880 cmd->flags = flags; 2881 ether_addr_copy(cmd->mac_addr, mac_addr); 2882 2883 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2884 } 2885 2886 /** 2887 * ice_aq_clear_pxe_mode 2888 * @hw: pointer to the HW struct 2889 * 2890 * Tell the firmware that the driver is taking over from PXE (0x0110). 2891 */ 2892 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 2893 { 2894 struct ice_aq_desc desc; 2895 2896 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2897 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2898 2899 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2900 } 2901 2902 /** 2903 * ice_clear_pxe_mode - clear pxe operations mode 2904 * @hw: pointer to the HW struct 2905 * 2906 * Make sure all PXE mode settings are cleared, including things 2907 * like descriptor fetch/write-back mode. 2908 */ 2909 void ice_clear_pxe_mode(struct ice_hw *hw) 2910 { 2911 if (ice_check_sq_alive(hw, &hw->adminq)) 2912 ice_aq_clear_pxe_mode(hw); 2913 } 2914 2915 /** 2916 * ice_aq_set_port_params - set physical port parameters. 2917 * @pi: pointer to the port info struct 2918 * @double_vlan: if set double VLAN is enabled 2919 * @cd: pointer to command details structure or NULL 2920 * 2921 * Set Physical port parameters (0x0203) 2922 */ 2923 int 2924 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 2925 struct ice_sq_cd *cd) 2926 2927 { 2928 struct ice_aqc_set_port_params *cmd; 2929 struct ice_hw *hw = pi->hw; 2930 struct ice_aq_desc desc; 2931 u16 cmd_flags = 0; 2932 2933 cmd = &desc.params.set_port_params; 2934 2935 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 2936 if (double_vlan) 2937 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 2938 cmd->cmd_flags = cpu_to_le16(cmd_flags); 2939 2940 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2941 } 2942 2943 /** 2944 * ice_is_100m_speed_supported 2945 * @hw: pointer to the HW struct 2946 * 2947 * returns true if 100M speeds are supported by the device, 2948 * false otherwise. 2949 */ 2950 bool ice_is_100m_speed_supported(struct ice_hw *hw) 2951 { 2952 switch (hw->device_id) { 2953 case ICE_DEV_ID_E822C_SGMII: 2954 case ICE_DEV_ID_E822L_SGMII: 2955 case ICE_DEV_ID_E823L_1GBE: 2956 case ICE_DEV_ID_E823C_SGMII: 2957 return true; 2958 default: 2959 return false; 2960 } 2961 } 2962 2963 /** 2964 * ice_get_link_speed_based_on_phy_type - returns link speed 2965 * @phy_type_low: lower part of phy_type 2966 * @phy_type_high: higher part of phy_type 2967 * 2968 * This helper function will convert an entry in PHY type structure 2969 * [phy_type_low, phy_type_high] to its corresponding link speed. 2970 * Note: In the structure of [phy_type_low, phy_type_high], there should 2971 * be one bit set, as this function will convert one PHY type to its 2972 * speed. 2973 * If no bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 2974 * If more than one bit gets set, ICE_AQ_LINK_SPEED_UNKNOWN will be returned 2975 */ 2976 static u16 2977 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2978 { 2979 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2980 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2981 2982 switch (phy_type_low) { 2983 case ICE_PHY_TYPE_LOW_100BASE_TX: 2984 case ICE_PHY_TYPE_LOW_100M_SGMII: 2985 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2986 break; 2987 case ICE_PHY_TYPE_LOW_1000BASE_T: 2988 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2989 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2990 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2991 case ICE_PHY_TYPE_LOW_1G_SGMII: 2992 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2993 break; 2994 case ICE_PHY_TYPE_LOW_2500BASE_T: 2995 case ICE_PHY_TYPE_LOW_2500BASE_X: 2996 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2997 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2998 break; 2999 case ICE_PHY_TYPE_LOW_5GBASE_T: 3000 case ICE_PHY_TYPE_LOW_5GBASE_KR: 3001 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 3002 break; 3003 case ICE_PHY_TYPE_LOW_10GBASE_T: 3004 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 3005 case ICE_PHY_TYPE_LOW_10GBASE_SR: 3006 case ICE_PHY_TYPE_LOW_10GBASE_LR: 3007 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 3008 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3009 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 3010 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 3011 break; 3012 case ICE_PHY_TYPE_LOW_25GBASE_T: 3013 case ICE_PHY_TYPE_LOW_25GBASE_CR: 3014 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 3015 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 3016 case ICE_PHY_TYPE_LOW_25GBASE_SR: 3017 case ICE_PHY_TYPE_LOW_25GBASE_LR: 3018 case ICE_PHY_TYPE_LOW_25GBASE_KR: 3019 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 3020 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 3021 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3022 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3023 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 3024 break; 3025 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3026 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3027 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3028 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3029 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3030 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3031 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3032 break; 3033 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3034 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3035 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3036 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3037 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3038 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3039 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3040 case ICE_PHY_TYPE_LOW_50G_AUI2: 3041 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3042 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3043 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3044 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3045 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3046 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3047 case ICE_PHY_TYPE_LOW_50G_AUI1: 3048 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3049 break; 3050 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3051 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3052 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3053 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3054 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3055 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3056 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3057 case ICE_PHY_TYPE_LOW_100G_AUI4: 3058 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3059 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3060 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3061 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3062 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3063 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3064 break; 3065 default: 3066 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3067 break; 3068 } 3069 3070 switch (phy_type_high) { 3071 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3072 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3073 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3074 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3075 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3076 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3077 break; 3078 default: 3079 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3080 break; 3081 } 3082 3083 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3084 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3085 return ICE_AQ_LINK_SPEED_UNKNOWN; 3086 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3087 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3088 return ICE_AQ_LINK_SPEED_UNKNOWN; 3089 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3090 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3091 return speed_phy_type_low; 3092 else 3093 return speed_phy_type_high; 3094 } 3095 3096 /** 3097 * ice_update_phy_type 3098 * @phy_type_low: pointer to the lower part of phy_type 3099 * @phy_type_high: pointer to the higher part of phy_type 3100 * @link_speeds_bitmap: targeted link speeds bitmap 3101 * 3102 * Note: For the link_speeds_bitmap structure, you can check it at 3103 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3104 * link_speeds_bitmap include multiple speeds. 3105 * 3106 * Each entry in this [phy_type_low, phy_type_high] structure will 3107 * present a certain link speed. This helper function will turn on bits 3108 * in [phy_type_low, phy_type_high] structure based on the value of 3109 * link_speeds_bitmap input parameter. 3110 */ 3111 void 3112 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3113 u16 link_speeds_bitmap) 3114 { 3115 u64 pt_high; 3116 u64 pt_low; 3117 int index; 3118 u16 speed; 3119 3120 /* We first check with low part of phy_type */ 3121 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3122 pt_low = BIT_ULL(index); 3123 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3124 3125 if (link_speeds_bitmap & speed) 3126 *phy_type_low |= BIT_ULL(index); 3127 } 3128 3129 /* We then check with high part of phy_type */ 3130 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3131 pt_high = BIT_ULL(index); 3132 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3133 3134 if (link_speeds_bitmap & speed) 3135 *phy_type_high |= BIT_ULL(index); 3136 } 3137 } 3138 3139 /** 3140 * ice_aq_set_phy_cfg 3141 * @hw: pointer to the HW struct 3142 * @pi: port info structure of the interested logical port 3143 * @cfg: structure with PHY configuration data to be set 3144 * @cd: pointer to command details structure or NULL 3145 * 3146 * Set the various PHY configuration parameters supported on the Port. 3147 * One or more of the Set PHY config parameters may be ignored in an MFP 3148 * mode as the PF may not have the privilege to set some of the PHY Config 3149 * parameters. This status will be indicated by the command response (0x0601). 3150 */ 3151 int 3152 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3153 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3154 { 3155 struct ice_aq_desc desc; 3156 int status; 3157 3158 if (!cfg) 3159 return -EINVAL; 3160 3161 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3162 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3163 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3164 cfg->caps); 3165 3166 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3167 } 3168 3169 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3170 desc.params.set_phy.lport_num = pi->lport; 3171 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3172 3173 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3174 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3175 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3176 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3177 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3178 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3179 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3180 cfg->low_power_ctrl_an); 3181 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3182 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3183 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3184 cfg->link_fec_opt); 3185 3186 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3187 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3188 status = 0; 3189 3190 if (!status) 3191 pi->phy.curr_user_phy_cfg = *cfg; 3192 3193 return status; 3194 } 3195 3196 /** 3197 * ice_update_link_info - update status of the HW network link 3198 * @pi: port info structure of the interested logical port 3199 */ 3200 int ice_update_link_info(struct ice_port_info *pi) 3201 { 3202 struct ice_link_status *li; 3203 int status; 3204 3205 if (!pi) 3206 return -EINVAL; 3207 3208 li = &pi->phy.link_info; 3209 3210 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3211 if (status) 3212 return status; 3213 3214 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3215 struct ice_aqc_get_phy_caps_data *pcaps; 3216 struct ice_hw *hw; 3217 3218 hw = pi->hw; 3219 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 3220 GFP_KERNEL); 3221 if (!pcaps) 3222 return -ENOMEM; 3223 3224 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3225 pcaps, NULL); 3226 3227 devm_kfree(ice_hw_to_dev(hw), pcaps); 3228 } 3229 3230 return status; 3231 } 3232 3233 /** 3234 * ice_cache_phy_user_req 3235 * @pi: port information structure 3236 * @cache_data: PHY logging data 3237 * @cache_mode: PHY logging mode 3238 * 3239 * Log the user request on (FC, FEC, SPEED) for later use. 3240 */ 3241 static void 3242 ice_cache_phy_user_req(struct ice_port_info *pi, 3243 struct ice_phy_cache_mode_data cache_data, 3244 enum ice_phy_cache_mode cache_mode) 3245 { 3246 if (!pi) 3247 return; 3248 3249 switch (cache_mode) { 3250 case ICE_FC_MODE: 3251 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3252 break; 3253 case ICE_SPEED_MODE: 3254 pi->phy.curr_user_speed_req = 3255 cache_data.data.curr_user_speed_req; 3256 break; 3257 case ICE_FEC_MODE: 3258 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3259 break; 3260 default: 3261 break; 3262 } 3263 } 3264 3265 /** 3266 * ice_caps_to_fc_mode 3267 * @caps: PHY capabilities 3268 * 3269 * Convert PHY FC capabilities to ice FC mode 3270 */ 3271 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3272 { 3273 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3274 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3275 return ICE_FC_FULL; 3276 3277 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3278 return ICE_FC_TX_PAUSE; 3279 3280 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3281 return ICE_FC_RX_PAUSE; 3282 3283 return ICE_FC_NONE; 3284 } 3285 3286 /** 3287 * ice_caps_to_fec_mode 3288 * @caps: PHY capabilities 3289 * @fec_options: Link FEC options 3290 * 3291 * Convert PHY FEC capabilities to ice FEC mode 3292 */ 3293 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3294 { 3295 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3296 return ICE_FEC_AUTO; 3297 3298 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3299 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3300 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3301 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3302 return ICE_FEC_BASER; 3303 3304 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3305 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3306 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3307 return ICE_FEC_RS; 3308 3309 return ICE_FEC_NONE; 3310 } 3311 3312 /** 3313 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3314 * @pi: port information structure 3315 * @cfg: PHY configuration data to set FC mode 3316 * @req_mode: FC mode to configure 3317 */ 3318 int 3319 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3320 enum ice_fc_mode req_mode) 3321 { 3322 struct ice_phy_cache_mode_data cache_data; 3323 u8 pause_mask = 0x0; 3324 3325 if (!pi || !cfg) 3326 return -EINVAL; 3327 3328 switch (req_mode) { 3329 case ICE_FC_FULL: 3330 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3331 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3332 break; 3333 case ICE_FC_RX_PAUSE: 3334 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3335 break; 3336 case ICE_FC_TX_PAUSE: 3337 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3338 break; 3339 default: 3340 break; 3341 } 3342 3343 /* clear the old pause settings */ 3344 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3345 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3346 3347 /* set the new capabilities */ 3348 cfg->caps |= pause_mask; 3349 3350 /* Cache user FC request */ 3351 cache_data.data.curr_user_fc_req = req_mode; 3352 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3353 3354 return 0; 3355 } 3356 3357 /** 3358 * ice_set_fc 3359 * @pi: port information structure 3360 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3361 * @ena_auto_link_update: enable automatic link update 3362 * 3363 * Set the requested flow control mode. 3364 */ 3365 int 3366 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3367 { 3368 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3369 struct ice_aqc_get_phy_caps_data *pcaps; 3370 struct ice_hw *hw; 3371 int status; 3372 3373 if (!pi || !aq_failures) 3374 return -EINVAL; 3375 3376 *aq_failures = 0; 3377 hw = pi->hw; 3378 3379 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 3380 if (!pcaps) 3381 return -ENOMEM; 3382 3383 /* Get the current PHY config */ 3384 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3385 pcaps, NULL); 3386 if (status) { 3387 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3388 goto out; 3389 } 3390 3391 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3392 3393 /* Configure the set PHY data */ 3394 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3395 if (status) 3396 goto out; 3397 3398 /* If the capabilities have changed, then set the new config */ 3399 if (cfg.caps != pcaps->caps) { 3400 int retry_count, retry_max = 10; 3401 3402 /* Auto restart link so settings take effect */ 3403 if (ena_auto_link_update) 3404 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3405 3406 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3407 if (status) { 3408 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3409 goto out; 3410 } 3411 3412 /* Update the link info 3413 * It sometimes takes a really long time for link to 3414 * come back from the atomic reset. Thus, we wait a 3415 * little bit. 3416 */ 3417 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3418 status = ice_update_link_info(pi); 3419 3420 if (!status) 3421 break; 3422 3423 mdelay(100); 3424 } 3425 3426 if (status) 3427 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3428 } 3429 3430 out: 3431 devm_kfree(ice_hw_to_dev(hw), pcaps); 3432 return status; 3433 } 3434 3435 /** 3436 * ice_phy_caps_equals_cfg 3437 * @phy_caps: PHY capabilities 3438 * @phy_cfg: PHY configuration 3439 * 3440 * Helper function to determine if PHY capabilities matches PHY 3441 * configuration 3442 */ 3443 bool 3444 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3445 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3446 { 3447 u8 caps_mask, cfg_mask; 3448 3449 if (!phy_caps || !phy_cfg) 3450 return false; 3451 3452 /* These bits are not common between capabilities and configuration. 3453 * Do not use them to determine equality. 3454 */ 3455 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3456 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3457 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3458 3459 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3460 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3461 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3462 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3463 phy_caps->eee_cap != phy_cfg->eee_cap || 3464 phy_caps->eeer_value != phy_cfg->eeer_value || 3465 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3466 return false; 3467 3468 return true; 3469 } 3470 3471 /** 3472 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3473 * @pi: port information structure 3474 * @caps: PHY ability structure to copy date from 3475 * @cfg: PHY configuration structure to copy data to 3476 * 3477 * Helper function to copy AQC PHY get ability data to PHY set configuration 3478 * data structure 3479 */ 3480 void 3481 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3482 struct ice_aqc_get_phy_caps_data *caps, 3483 struct ice_aqc_set_phy_cfg_data *cfg) 3484 { 3485 if (!pi || !caps || !cfg) 3486 return; 3487 3488 memset(cfg, 0, sizeof(*cfg)); 3489 cfg->phy_type_low = caps->phy_type_low; 3490 cfg->phy_type_high = caps->phy_type_high; 3491 cfg->caps = caps->caps; 3492 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3493 cfg->eee_cap = caps->eee_cap; 3494 cfg->eeer_value = caps->eeer_value; 3495 cfg->link_fec_opt = caps->link_fec_options; 3496 cfg->module_compliance_enforcement = 3497 caps->module_compliance_enforcement; 3498 } 3499 3500 /** 3501 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3502 * @pi: port information structure 3503 * @cfg: PHY configuration data to set FEC mode 3504 * @fec: FEC mode to configure 3505 */ 3506 int 3507 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3508 enum ice_fec_mode fec) 3509 { 3510 struct ice_aqc_get_phy_caps_data *pcaps; 3511 struct ice_hw *hw; 3512 int status; 3513 3514 if (!pi || !cfg) 3515 return -EINVAL; 3516 3517 hw = pi->hw; 3518 3519 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3520 if (!pcaps) 3521 return -ENOMEM; 3522 3523 status = ice_aq_get_phy_caps(pi, false, 3524 (ice_fw_supports_report_dflt_cfg(hw) ? 3525 ICE_AQC_REPORT_DFLT_CFG : 3526 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3527 if (status) 3528 goto out; 3529 3530 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3531 cfg->link_fec_opt = pcaps->link_fec_options; 3532 3533 switch (fec) { 3534 case ICE_FEC_BASER: 3535 /* Clear RS bits, and AND BASE-R ability 3536 * bits and OR request bits. 3537 */ 3538 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3539 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3540 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3541 ICE_AQC_PHY_FEC_25G_KR_REQ; 3542 break; 3543 case ICE_FEC_RS: 3544 /* Clear BASE-R bits, and AND RS ability 3545 * bits and OR request bits. 3546 */ 3547 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3548 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3549 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3550 break; 3551 case ICE_FEC_NONE: 3552 /* Clear all FEC option bits. */ 3553 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3554 break; 3555 case ICE_FEC_AUTO: 3556 /* AND auto FEC bit, and all caps bits. */ 3557 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3558 cfg->link_fec_opt |= pcaps->link_fec_options; 3559 break; 3560 default: 3561 status = -EINVAL; 3562 break; 3563 } 3564 3565 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 3566 !ice_fw_supports_report_dflt_cfg(hw)) { 3567 struct ice_link_default_override_tlv tlv = { 0 }; 3568 3569 status = ice_get_link_default_override(&tlv, pi); 3570 if (status) 3571 goto out; 3572 3573 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3574 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3575 cfg->link_fec_opt = tlv.fec_options; 3576 } 3577 3578 out: 3579 kfree(pcaps); 3580 3581 return status; 3582 } 3583 3584 /** 3585 * ice_get_link_status - get status of the HW network link 3586 * @pi: port information structure 3587 * @link_up: pointer to bool (true/false = linkup/linkdown) 3588 * 3589 * Variable link_up is true if link is up, false if link is down. 3590 * The variable link_up is invalid if status is non zero. As a 3591 * result of this call, link status reporting becomes enabled 3592 */ 3593 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3594 { 3595 struct ice_phy_info *phy_info; 3596 int status = 0; 3597 3598 if (!pi || !link_up) 3599 return -EINVAL; 3600 3601 phy_info = &pi->phy; 3602 3603 if (phy_info->get_link_info) { 3604 status = ice_update_link_info(pi); 3605 3606 if (status) 3607 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3608 status); 3609 } 3610 3611 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3612 3613 return status; 3614 } 3615 3616 /** 3617 * ice_aq_set_link_restart_an 3618 * @pi: pointer to the port information structure 3619 * @ena_link: if true: enable link, if false: disable link 3620 * @cd: pointer to command details structure or NULL 3621 * 3622 * Sets up the link and restarts the Auto-Negotiation over the link. 3623 */ 3624 int 3625 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3626 struct ice_sq_cd *cd) 3627 { 3628 struct ice_aqc_restart_an *cmd; 3629 struct ice_aq_desc desc; 3630 3631 cmd = &desc.params.restart_an; 3632 3633 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3634 3635 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3636 cmd->lport_num = pi->lport; 3637 if (ena_link) 3638 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3639 else 3640 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3641 3642 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3643 } 3644 3645 /** 3646 * ice_aq_set_event_mask 3647 * @hw: pointer to the HW struct 3648 * @port_num: port number of the physical function 3649 * @mask: event mask to be set 3650 * @cd: pointer to command details structure or NULL 3651 * 3652 * Set event mask (0x0613) 3653 */ 3654 int 3655 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3656 struct ice_sq_cd *cd) 3657 { 3658 struct ice_aqc_set_event_mask *cmd; 3659 struct ice_aq_desc desc; 3660 3661 cmd = &desc.params.set_event_mask; 3662 3663 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3664 3665 cmd->lport_num = port_num; 3666 3667 cmd->event_mask = cpu_to_le16(mask); 3668 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3669 } 3670 3671 /** 3672 * ice_aq_set_mac_loopback 3673 * @hw: pointer to the HW struct 3674 * @ena_lpbk: Enable or Disable loopback 3675 * @cd: pointer to command details structure or NULL 3676 * 3677 * Enable/disable loopback on a given port 3678 */ 3679 int 3680 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3681 { 3682 struct ice_aqc_set_mac_lb *cmd; 3683 struct ice_aq_desc desc; 3684 3685 cmd = &desc.params.set_mac_lb; 3686 3687 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3688 if (ena_lpbk) 3689 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3690 3691 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3692 } 3693 3694 /** 3695 * ice_aq_set_port_id_led 3696 * @pi: pointer to the port information 3697 * @is_orig_mode: is this LED set to original mode (by the net-list) 3698 * @cd: pointer to command details structure or NULL 3699 * 3700 * Set LED value for the given port (0x06e9) 3701 */ 3702 int 3703 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3704 struct ice_sq_cd *cd) 3705 { 3706 struct ice_aqc_set_port_id_led *cmd; 3707 struct ice_hw *hw = pi->hw; 3708 struct ice_aq_desc desc; 3709 3710 cmd = &desc.params.set_port_id_led; 3711 3712 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3713 3714 if (is_orig_mode) 3715 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3716 else 3717 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3718 3719 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3720 } 3721 3722 /** 3723 * ice_aq_get_port_options 3724 * @hw: pointer to the HW struct 3725 * @options: buffer for the resultant port options 3726 * @option_count: input - size of the buffer in port options structures, 3727 * output - number of returned port options 3728 * @lport: logical port to call the command with (optional) 3729 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3730 * when PF owns more than 1 port it must be true 3731 * @active_option_idx: index of active port option in returned buffer 3732 * @active_option_valid: active option in returned buffer is valid 3733 * @pending_option_idx: index of pending port option in returned buffer 3734 * @pending_option_valid: pending option in returned buffer is valid 3735 * 3736 * Calls Get Port Options AQC (0x06ea) and verifies result. 3737 */ 3738 int 3739 ice_aq_get_port_options(struct ice_hw *hw, 3740 struct ice_aqc_get_port_options_elem *options, 3741 u8 *option_count, u8 lport, bool lport_valid, 3742 u8 *active_option_idx, bool *active_option_valid, 3743 u8 *pending_option_idx, bool *pending_option_valid) 3744 { 3745 struct ice_aqc_get_port_options *cmd; 3746 struct ice_aq_desc desc; 3747 int status; 3748 u8 i; 3749 3750 /* options buffer shall be able to hold max returned options */ 3751 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 3752 return -EINVAL; 3753 3754 cmd = &desc.params.get_port_options; 3755 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 3756 3757 if (lport_valid) 3758 cmd->lport_num = lport; 3759 cmd->lport_num_valid = lport_valid; 3760 3761 status = ice_aq_send_cmd(hw, &desc, options, 3762 *option_count * sizeof(*options), NULL); 3763 if (status) 3764 return status; 3765 3766 /* verify direct FW response & set output parameters */ 3767 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 3768 cmd->port_options_count); 3769 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 3770 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 3771 cmd->port_options); 3772 if (*active_option_valid) { 3773 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 3774 cmd->port_options); 3775 if (*active_option_idx > (*option_count - 1)) 3776 return -EIO; 3777 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 3778 *active_option_idx); 3779 } 3780 3781 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 3782 cmd->pending_port_option_status); 3783 if (*pending_option_valid) { 3784 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 3785 cmd->pending_port_option_status); 3786 if (*pending_option_idx > (*option_count - 1)) 3787 return -EIO; 3788 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 3789 *pending_option_idx); 3790 } 3791 3792 /* mask output options fields */ 3793 for (i = 0; i < *option_count; i++) { 3794 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 3795 options[i].pmd); 3796 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 3797 options[i].max_lane_speed); 3798 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 3799 options[i].pmd, options[i].max_lane_speed); 3800 } 3801 3802 return 0; 3803 } 3804 3805 /** 3806 * ice_aq_set_port_option 3807 * @hw: pointer to the HW struct 3808 * @lport: logical port to call the command with 3809 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3810 * when PF owns more than 1 port it must be true 3811 * @new_option: new port option to be written 3812 * 3813 * Calls Set Port Options AQC (0x06eb). 3814 */ 3815 int 3816 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 3817 u8 new_option) 3818 { 3819 struct ice_aqc_set_port_option *cmd; 3820 struct ice_aq_desc desc; 3821 3822 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 3823 return -EINVAL; 3824 3825 cmd = &desc.params.set_port_option; 3826 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 3827 3828 if (lport_valid) 3829 cmd->lport_num = lport; 3830 3831 cmd->lport_num_valid = lport_valid; 3832 cmd->selected_port_option = new_option; 3833 3834 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3835 } 3836 3837 /** 3838 * ice_aq_sff_eeprom 3839 * @hw: pointer to the HW struct 3840 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3841 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3842 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3843 * @page: QSFP page 3844 * @set_page: set or ignore the page 3845 * @data: pointer to data buffer to be read/written to the I2C device. 3846 * @length: 1-16 for read, 1 for write. 3847 * @write: 0 read, 1 for write. 3848 * @cd: pointer to command details structure or NULL 3849 * 3850 * Read/Write SFF EEPROM (0x06EE) 3851 */ 3852 int 3853 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3854 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3855 bool write, struct ice_sq_cd *cd) 3856 { 3857 struct ice_aqc_sff_eeprom *cmd; 3858 struct ice_aq_desc desc; 3859 int status; 3860 3861 if (!data || (mem_addr & 0xff00)) 3862 return -EINVAL; 3863 3864 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3865 cmd = &desc.params.read_write_sff_param; 3866 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 3867 cmd->lport_num = (u8)(lport & 0xff); 3868 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3869 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 3870 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3871 ((set_page << 3872 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3873 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3874 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3875 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3876 if (write) 3877 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 3878 3879 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3880 return status; 3881 } 3882 3883 /** 3884 * __ice_aq_get_set_rss_lut 3885 * @hw: pointer to the hardware structure 3886 * @params: RSS LUT parameters 3887 * @set: set true to set the table, false to get the table 3888 * 3889 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3890 */ 3891 static int 3892 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 3893 { 3894 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 3895 struct ice_aqc_get_set_rss_lut *cmd_resp; 3896 struct ice_aq_desc desc; 3897 int status; 3898 u8 *lut; 3899 3900 if (!params) 3901 return -EINVAL; 3902 3903 vsi_handle = params->vsi_handle; 3904 lut = params->lut; 3905 3906 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3907 return -EINVAL; 3908 3909 lut_size = params->lut_size; 3910 lut_type = params->lut_type; 3911 glob_lut_idx = params->global_lut_id; 3912 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 3913 3914 cmd_resp = &desc.params.get_set_rss_lut; 3915 3916 if (set) { 3917 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3918 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3919 } else { 3920 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3921 } 3922 3923 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3924 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3925 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3926 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3927 3928 switch (lut_type) { 3929 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3930 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3931 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3932 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3933 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3934 break; 3935 default: 3936 status = -EINVAL; 3937 goto ice_aq_get_set_rss_lut_exit; 3938 } 3939 3940 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3941 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3942 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3943 3944 if (!set) 3945 goto ice_aq_get_set_rss_lut_send; 3946 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3947 if (!set) 3948 goto ice_aq_get_set_rss_lut_send; 3949 } else { 3950 goto ice_aq_get_set_rss_lut_send; 3951 } 3952 3953 /* LUT size is only valid for Global and PF table types */ 3954 switch (lut_size) { 3955 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3956 break; 3957 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3958 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3959 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3960 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3961 break; 3962 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3963 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3964 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3965 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3966 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3967 break; 3968 } 3969 fallthrough; 3970 default: 3971 status = -EINVAL; 3972 goto ice_aq_get_set_rss_lut_exit; 3973 } 3974 3975 ice_aq_get_set_rss_lut_send: 3976 cmd_resp->flags = cpu_to_le16(flags); 3977 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3978 3979 ice_aq_get_set_rss_lut_exit: 3980 return status; 3981 } 3982 3983 /** 3984 * ice_aq_get_rss_lut 3985 * @hw: pointer to the hardware structure 3986 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 3987 * 3988 * get the RSS lookup table, PF or VSI type 3989 */ 3990 int 3991 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 3992 { 3993 return __ice_aq_get_set_rss_lut(hw, get_params, false); 3994 } 3995 3996 /** 3997 * ice_aq_set_rss_lut 3998 * @hw: pointer to the hardware structure 3999 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 4000 * 4001 * set the RSS lookup table, PF or VSI type 4002 */ 4003 int 4004 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 4005 { 4006 return __ice_aq_get_set_rss_lut(hw, set_params, true); 4007 } 4008 4009 /** 4010 * __ice_aq_get_set_rss_key 4011 * @hw: pointer to the HW struct 4012 * @vsi_id: VSI FW index 4013 * @key: pointer to key info struct 4014 * @set: set true to set the key, false to get the key 4015 * 4016 * get (0x0B04) or set (0x0B02) the RSS key per VSI 4017 */ 4018 static int 4019 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 4020 struct ice_aqc_get_set_rss_keys *key, bool set) 4021 { 4022 struct ice_aqc_get_set_rss_key *cmd_resp; 4023 u16 key_size = sizeof(*key); 4024 struct ice_aq_desc desc; 4025 4026 cmd_resp = &desc.params.get_set_rss_key; 4027 4028 if (set) { 4029 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4030 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4031 } else { 4032 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4033 } 4034 4035 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 4036 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 4037 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 4038 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 4039 4040 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4041 } 4042 4043 /** 4044 * ice_aq_get_rss_key 4045 * @hw: pointer to the HW struct 4046 * @vsi_handle: software VSI handle 4047 * @key: pointer to key info struct 4048 * 4049 * get the RSS key per VSI 4050 */ 4051 int 4052 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4053 struct ice_aqc_get_set_rss_keys *key) 4054 { 4055 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4056 return -EINVAL; 4057 4058 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4059 key, false); 4060 } 4061 4062 /** 4063 * ice_aq_set_rss_key 4064 * @hw: pointer to the HW struct 4065 * @vsi_handle: software VSI handle 4066 * @keys: pointer to key info struct 4067 * 4068 * set the RSS key per VSI 4069 */ 4070 int 4071 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4072 struct ice_aqc_get_set_rss_keys *keys) 4073 { 4074 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4075 return -EINVAL; 4076 4077 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4078 keys, true); 4079 } 4080 4081 /** 4082 * ice_aq_add_lan_txq 4083 * @hw: pointer to the hardware structure 4084 * @num_qgrps: Number of added queue groups 4085 * @qg_list: list of queue groups to be added 4086 * @buf_size: size of buffer for indirect command 4087 * @cd: pointer to command details structure or NULL 4088 * 4089 * Add Tx LAN queue (0x0C30) 4090 * 4091 * NOTE: 4092 * Prior to calling add Tx LAN queue: 4093 * Initialize the following as part of the Tx queue context: 4094 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4095 * Cache profile and Packet shaper profile. 4096 * 4097 * After add Tx LAN queue AQ command is completed: 4098 * Interrupts should be associated with specific queues, 4099 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4100 * flow. 4101 */ 4102 static int 4103 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4104 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4105 struct ice_sq_cd *cd) 4106 { 4107 struct ice_aqc_add_tx_qgrp *list; 4108 struct ice_aqc_add_txqs *cmd; 4109 struct ice_aq_desc desc; 4110 u16 i, sum_size = 0; 4111 4112 cmd = &desc.params.add_txqs; 4113 4114 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4115 4116 if (!qg_list) 4117 return -EINVAL; 4118 4119 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4120 return -EINVAL; 4121 4122 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4123 sum_size += struct_size(list, txqs, list->num_txqs); 4124 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4125 list->num_txqs); 4126 } 4127 4128 if (buf_size != sum_size) 4129 return -EINVAL; 4130 4131 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4132 4133 cmd->num_qgrps = num_qgrps; 4134 4135 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4136 } 4137 4138 /** 4139 * ice_aq_dis_lan_txq 4140 * @hw: pointer to the hardware structure 4141 * @num_qgrps: number of groups in the list 4142 * @qg_list: the list of groups to disable 4143 * @buf_size: the total size of the qg_list buffer in bytes 4144 * @rst_src: if called due to reset, specifies the reset source 4145 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4146 * @cd: pointer to command details structure or NULL 4147 * 4148 * Disable LAN Tx queue (0x0C31) 4149 */ 4150 static int 4151 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4152 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4153 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4154 struct ice_sq_cd *cd) 4155 { 4156 struct ice_aqc_dis_txq_item *item; 4157 struct ice_aqc_dis_txqs *cmd; 4158 struct ice_aq_desc desc; 4159 u16 i, sz = 0; 4160 int status; 4161 4162 cmd = &desc.params.dis_txqs; 4163 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4164 4165 /* qg_list can be NULL only in VM/VF reset flow */ 4166 if (!qg_list && !rst_src) 4167 return -EINVAL; 4168 4169 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4170 return -EINVAL; 4171 4172 cmd->num_entries = num_qgrps; 4173 4174 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 4175 ICE_AQC_Q_DIS_TIMEOUT_M); 4176 4177 switch (rst_src) { 4178 case ICE_VM_RESET: 4179 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4180 cmd->vmvf_and_timeout |= 4181 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 4182 break; 4183 case ICE_VF_RESET: 4184 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4185 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4186 cmd->vmvf_and_timeout |= 4187 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 4188 ICE_AQC_Q_DIS_VMVF_NUM_M); 4189 break; 4190 case ICE_NO_RESET: 4191 default: 4192 break; 4193 } 4194 4195 /* flush pipe on time out */ 4196 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4197 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4198 if (!qg_list) 4199 goto do_aq; 4200 4201 /* set RD bit to indicate that command buffer is provided by the driver 4202 * and it needs to be read by the firmware 4203 */ 4204 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4205 4206 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4207 u16 item_size = struct_size(item, q_id, item->num_qs); 4208 4209 /* If the num of queues is even, add 2 bytes of padding */ 4210 if ((item->num_qs % 2) == 0) 4211 item_size += 2; 4212 4213 sz += item_size; 4214 4215 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4216 } 4217 4218 if (buf_size != sz) 4219 return -EINVAL; 4220 4221 do_aq: 4222 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4223 if (status) { 4224 if (!qg_list) 4225 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4226 vmvf_num, hw->adminq.sq_last_status); 4227 else 4228 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4229 le16_to_cpu(qg_list[0].q_id[0]), 4230 hw->adminq.sq_last_status); 4231 } 4232 return status; 4233 } 4234 4235 /** 4236 * ice_aq_add_rdma_qsets 4237 * @hw: pointer to the hardware structure 4238 * @num_qset_grps: Number of RDMA Qset groups 4239 * @qset_list: list of Qset groups to be added 4240 * @buf_size: size of buffer for indirect command 4241 * @cd: pointer to command details structure or NULL 4242 * 4243 * Add Tx RDMA Qsets (0x0C33) 4244 */ 4245 static int 4246 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4247 struct ice_aqc_add_rdma_qset_data *qset_list, 4248 u16 buf_size, struct ice_sq_cd *cd) 4249 { 4250 struct ice_aqc_add_rdma_qset_data *list; 4251 struct ice_aqc_add_rdma_qset *cmd; 4252 struct ice_aq_desc desc; 4253 u16 i, sum_size = 0; 4254 4255 cmd = &desc.params.add_rdma_qset; 4256 4257 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4258 4259 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4260 return -EINVAL; 4261 4262 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4263 u16 num_qsets = le16_to_cpu(list->num_qsets); 4264 4265 sum_size += struct_size(list, rdma_qsets, num_qsets); 4266 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4267 num_qsets); 4268 } 4269 4270 if (buf_size != sum_size) 4271 return -EINVAL; 4272 4273 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4274 4275 cmd->num_qset_grps = num_qset_grps; 4276 4277 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4278 } 4279 4280 /* End of FW Admin Queue command wrappers */ 4281 4282 /** 4283 * ice_write_byte - write a byte to a packed context structure 4284 * @src_ctx: the context structure to read from 4285 * @dest_ctx: the context to be written to 4286 * @ce_info: a description of the struct to be filled 4287 */ 4288 static void 4289 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4290 { 4291 u8 src_byte, dest_byte, mask; 4292 u8 *from, *dest; 4293 u16 shift_width; 4294 4295 /* copy from the next struct field */ 4296 from = src_ctx + ce_info->offset; 4297 4298 /* prepare the bits and mask */ 4299 shift_width = ce_info->lsb % 8; 4300 mask = (u8)(BIT(ce_info->width) - 1); 4301 4302 src_byte = *from; 4303 src_byte &= mask; 4304 4305 /* shift to correct alignment */ 4306 mask <<= shift_width; 4307 src_byte <<= shift_width; 4308 4309 /* get the current bits from the target bit string */ 4310 dest = dest_ctx + (ce_info->lsb / 8); 4311 4312 memcpy(&dest_byte, dest, sizeof(dest_byte)); 4313 4314 dest_byte &= ~mask; /* get the bits not changing */ 4315 dest_byte |= src_byte; /* add in the new bits */ 4316 4317 /* put it all back */ 4318 memcpy(dest, &dest_byte, sizeof(dest_byte)); 4319 } 4320 4321 /** 4322 * ice_write_word - write a word to a packed context structure 4323 * @src_ctx: the context structure to read from 4324 * @dest_ctx: the context to be written to 4325 * @ce_info: a description of the struct to be filled 4326 */ 4327 static void 4328 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4329 { 4330 u16 src_word, mask; 4331 __le16 dest_word; 4332 u8 *from, *dest; 4333 u16 shift_width; 4334 4335 /* copy from the next struct field */ 4336 from = src_ctx + ce_info->offset; 4337 4338 /* prepare the bits and mask */ 4339 shift_width = ce_info->lsb % 8; 4340 mask = BIT(ce_info->width) - 1; 4341 4342 /* don't swizzle the bits until after the mask because the mask bits 4343 * will be in a different bit position on big endian machines 4344 */ 4345 src_word = *(u16 *)from; 4346 src_word &= mask; 4347 4348 /* shift to correct alignment */ 4349 mask <<= shift_width; 4350 src_word <<= shift_width; 4351 4352 /* get the current bits from the target bit string */ 4353 dest = dest_ctx + (ce_info->lsb / 8); 4354 4355 memcpy(&dest_word, dest, sizeof(dest_word)); 4356 4357 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 4358 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 4359 4360 /* put it all back */ 4361 memcpy(dest, &dest_word, sizeof(dest_word)); 4362 } 4363 4364 /** 4365 * ice_write_dword - write a dword to a packed context structure 4366 * @src_ctx: the context structure to read from 4367 * @dest_ctx: the context to be written to 4368 * @ce_info: a description of the struct to be filled 4369 */ 4370 static void 4371 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4372 { 4373 u32 src_dword, mask; 4374 __le32 dest_dword; 4375 u8 *from, *dest; 4376 u16 shift_width; 4377 4378 /* copy from the next struct field */ 4379 from = src_ctx + ce_info->offset; 4380 4381 /* prepare the bits and mask */ 4382 shift_width = ce_info->lsb % 8; 4383 4384 /* if the field width is exactly 32 on an x86 machine, then the shift 4385 * operation will not work because the SHL instructions count is masked 4386 * to 5 bits so the shift will do nothing 4387 */ 4388 if (ce_info->width < 32) 4389 mask = BIT(ce_info->width) - 1; 4390 else 4391 mask = (u32)~0; 4392 4393 /* don't swizzle the bits until after the mask because the mask bits 4394 * will be in a different bit position on big endian machines 4395 */ 4396 src_dword = *(u32 *)from; 4397 src_dword &= mask; 4398 4399 /* shift to correct alignment */ 4400 mask <<= shift_width; 4401 src_dword <<= shift_width; 4402 4403 /* get the current bits from the target bit string */ 4404 dest = dest_ctx + (ce_info->lsb / 8); 4405 4406 memcpy(&dest_dword, dest, sizeof(dest_dword)); 4407 4408 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 4409 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 4410 4411 /* put it all back */ 4412 memcpy(dest, &dest_dword, sizeof(dest_dword)); 4413 } 4414 4415 /** 4416 * ice_write_qword - write a qword to a packed context structure 4417 * @src_ctx: the context structure to read from 4418 * @dest_ctx: the context to be written to 4419 * @ce_info: a description of the struct to be filled 4420 */ 4421 static void 4422 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4423 { 4424 u64 src_qword, mask; 4425 __le64 dest_qword; 4426 u8 *from, *dest; 4427 u16 shift_width; 4428 4429 /* copy from the next struct field */ 4430 from = src_ctx + ce_info->offset; 4431 4432 /* prepare the bits and mask */ 4433 shift_width = ce_info->lsb % 8; 4434 4435 /* if the field width is exactly 64 on an x86 machine, then the shift 4436 * operation will not work because the SHL instructions count is masked 4437 * to 6 bits so the shift will do nothing 4438 */ 4439 if (ce_info->width < 64) 4440 mask = BIT_ULL(ce_info->width) - 1; 4441 else 4442 mask = (u64)~0; 4443 4444 /* don't swizzle the bits until after the mask because the mask bits 4445 * will be in a different bit position on big endian machines 4446 */ 4447 src_qword = *(u64 *)from; 4448 src_qword &= mask; 4449 4450 /* shift to correct alignment */ 4451 mask <<= shift_width; 4452 src_qword <<= shift_width; 4453 4454 /* get the current bits from the target bit string */ 4455 dest = dest_ctx + (ce_info->lsb / 8); 4456 4457 memcpy(&dest_qword, dest, sizeof(dest_qword)); 4458 4459 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 4460 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 4461 4462 /* put it all back */ 4463 memcpy(dest, &dest_qword, sizeof(dest_qword)); 4464 } 4465 4466 /** 4467 * ice_set_ctx - set context bits in packed structure 4468 * @hw: pointer to the hardware structure 4469 * @src_ctx: pointer to a generic non-packed context structure 4470 * @dest_ctx: pointer to memory for the packed structure 4471 * @ce_info: a description of the structure to be transformed 4472 */ 4473 int 4474 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 4475 const struct ice_ctx_ele *ce_info) 4476 { 4477 int f; 4478 4479 for (f = 0; ce_info[f].width; f++) { 4480 /* We have to deal with each element of the FW response 4481 * using the correct size so that we are correct regardless 4482 * of the endianness of the machine. 4483 */ 4484 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 4485 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 4486 f, ce_info[f].width, ce_info[f].size_of); 4487 continue; 4488 } 4489 switch (ce_info[f].size_of) { 4490 case sizeof(u8): 4491 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 4492 break; 4493 case sizeof(u16): 4494 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 4495 break; 4496 case sizeof(u32): 4497 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 4498 break; 4499 case sizeof(u64): 4500 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 4501 break; 4502 default: 4503 return -EINVAL; 4504 } 4505 } 4506 4507 return 0; 4508 } 4509 4510 /** 4511 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4512 * @hw: pointer to the HW struct 4513 * @vsi_handle: software VSI handle 4514 * @tc: TC number 4515 * @q_handle: software queue handle 4516 */ 4517 struct ice_q_ctx * 4518 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4519 { 4520 struct ice_vsi_ctx *vsi; 4521 struct ice_q_ctx *q_ctx; 4522 4523 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4524 if (!vsi) 4525 return NULL; 4526 if (q_handle >= vsi->num_lan_q_entries[tc]) 4527 return NULL; 4528 if (!vsi->lan_q_ctx[tc]) 4529 return NULL; 4530 q_ctx = vsi->lan_q_ctx[tc]; 4531 return &q_ctx[q_handle]; 4532 } 4533 4534 /** 4535 * ice_ena_vsi_txq 4536 * @pi: port information structure 4537 * @vsi_handle: software VSI handle 4538 * @tc: TC number 4539 * @q_handle: software queue handle 4540 * @num_qgrps: Number of added queue groups 4541 * @buf: list of queue groups to be added 4542 * @buf_size: size of buffer for indirect command 4543 * @cd: pointer to command details structure or NULL 4544 * 4545 * This function adds one LAN queue 4546 */ 4547 int 4548 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4549 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4550 struct ice_sq_cd *cd) 4551 { 4552 struct ice_aqc_txsched_elem_data node = { 0 }; 4553 struct ice_sched_node *parent; 4554 struct ice_q_ctx *q_ctx; 4555 struct ice_hw *hw; 4556 int status; 4557 4558 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4559 return -EIO; 4560 4561 if (num_qgrps > 1 || buf->num_txqs > 1) 4562 return -ENOSPC; 4563 4564 hw = pi->hw; 4565 4566 if (!ice_is_vsi_valid(hw, vsi_handle)) 4567 return -EINVAL; 4568 4569 mutex_lock(&pi->sched_lock); 4570 4571 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4572 if (!q_ctx) { 4573 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4574 q_handle); 4575 status = -EINVAL; 4576 goto ena_txq_exit; 4577 } 4578 4579 /* find a parent node */ 4580 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4581 ICE_SCHED_NODE_OWNER_LAN); 4582 if (!parent) { 4583 status = -EINVAL; 4584 goto ena_txq_exit; 4585 } 4586 4587 buf->parent_teid = parent->info.node_teid; 4588 node.parent_teid = parent->info.node_teid; 4589 /* Mark that the values in the "generic" section as valid. The default 4590 * value in the "generic" section is zero. This means that : 4591 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4592 * - 0 priority among siblings, indicated by Bit 1-3. 4593 * - WFQ, indicated by Bit 4. 4594 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4595 * Bit 5-6. 4596 * - Bit 7 is reserved. 4597 * Without setting the generic section as valid in valid_sections, the 4598 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4599 */ 4600 buf->txqs[0].info.valid_sections = 4601 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4602 ICE_AQC_ELEM_VALID_EIR; 4603 buf->txqs[0].info.generic = 0; 4604 buf->txqs[0].info.cir_bw.bw_profile_idx = 4605 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4606 buf->txqs[0].info.cir_bw.bw_alloc = 4607 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4608 buf->txqs[0].info.eir_bw.bw_profile_idx = 4609 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4610 buf->txqs[0].info.eir_bw.bw_alloc = 4611 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4612 4613 /* add the LAN queue */ 4614 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4615 if (status) { 4616 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4617 le16_to_cpu(buf->txqs[0].txq_id), 4618 hw->adminq.sq_last_status); 4619 goto ena_txq_exit; 4620 } 4621 4622 node.node_teid = buf->txqs[0].q_teid; 4623 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4624 q_ctx->q_handle = q_handle; 4625 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4626 4627 /* add a leaf node into scheduler tree queue layer */ 4628 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); 4629 if (!status) 4630 status = ice_sched_replay_q_bw(pi, q_ctx); 4631 4632 ena_txq_exit: 4633 mutex_unlock(&pi->sched_lock); 4634 return status; 4635 } 4636 4637 /** 4638 * ice_dis_vsi_txq 4639 * @pi: port information structure 4640 * @vsi_handle: software VSI handle 4641 * @tc: TC number 4642 * @num_queues: number of queues 4643 * @q_handles: pointer to software queue handle array 4644 * @q_ids: pointer to the q_id array 4645 * @q_teids: pointer to queue node teids 4646 * @rst_src: if called due to reset, specifies the reset source 4647 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4648 * @cd: pointer to command details structure or NULL 4649 * 4650 * This function removes queues and their corresponding nodes in SW DB 4651 */ 4652 int 4653 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4654 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4655 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4656 struct ice_sq_cd *cd) 4657 { 4658 struct ice_aqc_dis_txq_item *qg_list; 4659 struct ice_q_ctx *q_ctx; 4660 int status = -ENOENT; 4661 struct ice_hw *hw; 4662 u16 i, buf_size; 4663 4664 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4665 return -EIO; 4666 4667 hw = pi->hw; 4668 4669 if (!num_queues) { 4670 /* if queue is disabled already yet the disable queue command 4671 * has to be sent to complete the VF reset, then call 4672 * ice_aq_dis_lan_txq without any queue information 4673 */ 4674 if (rst_src) 4675 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4676 vmvf_num, NULL); 4677 return -EIO; 4678 } 4679 4680 buf_size = struct_size(qg_list, q_id, 1); 4681 qg_list = kzalloc(buf_size, GFP_KERNEL); 4682 if (!qg_list) 4683 return -ENOMEM; 4684 4685 mutex_lock(&pi->sched_lock); 4686 4687 for (i = 0; i < num_queues; i++) { 4688 struct ice_sched_node *node; 4689 4690 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4691 if (!node) 4692 continue; 4693 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4694 if (!q_ctx) { 4695 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4696 q_handles[i]); 4697 continue; 4698 } 4699 if (q_ctx->q_handle != q_handles[i]) { 4700 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4701 q_ctx->q_handle, q_handles[i]); 4702 continue; 4703 } 4704 qg_list->parent_teid = node->info.parent_teid; 4705 qg_list->num_qs = 1; 4706 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4707 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4708 vmvf_num, cd); 4709 4710 if (status) 4711 break; 4712 ice_free_sched_node(pi, node); 4713 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4714 } 4715 mutex_unlock(&pi->sched_lock); 4716 kfree(qg_list); 4717 return status; 4718 } 4719 4720 /** 4721 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4722 * @pi: port information structure 4723 * @vsi_handle: software VSI handle 4724 * @tc_bitmap: TC bitmap 4725 * @maxqs: max queues array per TC 4726 * @owner: LAN or RDMA 4727 * 4728 * This function adds/updates the VSI queues per TC. 4729 */ 4730 static int 4731 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4732 u16 *maxqs, u8 owner) 4733 { 4734 int status = 0; 4735 u8 i; 4736 4737 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4738 return -EIO; 4739 4740 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4741 return -EINVAL; 4742 4743 mutex_lock(&pi->sched_lock); 4744 4745 ice_for_each_traffic_class(i) { 4746 /* configuration is possible only if TC node is present */ 4747 if (!ice_sched_get_tc_node(pi, i)) 4748 continue; 4749 4750 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4751 ice_is_tc_ena(tc_bitmap, i)); 4752 if (status) 4753 break; 4754 } 4755 4756 mutex_unlock(&pi->sched_lock); 4757 return status; 4758 } 4759 4760 /** 4761 * ice_cfg_vsi_lan - configure VSI LAN queues 4762 * @pi: port information structure 4763 * @vsi_handle: software VSI handle 4764 * @tc_bitmap: TC bitmap 4765 * @max_lanqs: max LAN queues array per TC 4766 * 4767 * This function adds/updates the VSI LAN queues per TC. 4768 */ 4769 int 4770 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4771 u16 *max_lanqs) 4772 { 4773 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4774 ICE_SCHED_NODE_OWNER_LAN); 4775 } 4776 4777 /** 4778 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 4779 * @pi: port information structure 4780 * @vsi_handle: software VSI handle 4781 * @tc_bitmap: TC bitmap 4782 * @max_rdmaqs: max RDMA queues array per TC 4783 * 4784 * This function adds/updates the VSI RDMA queues per TC. 4785 */ 4786 int 4787 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4788 u16 *max_rdmaqs) 4789 { 4790 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 4791 ICE_SCHED_NODE_OWNER_RDMA); 4792 } 4793 4794 /** 4795 * ice_ena_vsi_rdma_qset 4796 * @pi: port information structure 4797 * @vsi_handle: software VSI handle 4798 * @tc: TC number 4799 * @rdma_qset: pointer to RDMA Qset 4800 * @num_qsets: number of RDMA Qsets 4801 * @qset_teid: pointer to Qset node TEIDs 4802 * 4803 * This function adds RDMA Qset 4804 */ 4805 int 4806 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4807 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 4808 { 4809 struct ice_aqc_txsched_elem_data node = { 0 }; 4810 struct ice_aqc_add_rdma_qset_data *buf; 4811 struct ice_sched_node *parent; 4812 struct ice_hw *hw; 4813 u16 i, buf_size; 4814 int ret; 4815 4816 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4817 return -EIO; 4818 hw = pi->hw; 4819 4820 if (!ice_is_vsi_valid(hw, vsi_handle)) 4821 return -EINVAL; 4822 4823 buf_size = struct_size(buf, rdma_qsets, num_qsets); 4824 buf = kzalloc(buf_size, GFP_KERNEL); 4825 if (!buf) 4826 return -ENOMEM; 4827 mutex_lock(&pi->sched_lock); 4828 4829 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4830 ICE_SCHED_NODE_OWNER_RDMA); 4831 if (!parent) { 4832 ret = -EINVAL; 4833 goto rdma_error_exit; 4834 } 4835 buf->parent_teid = parent->info.node_teid; 4836 node.parent_teid = parent->info.node_teid; 4837 4838 buf->num_qsets = cpu_to_le16(num_qsets); 4839 for (i = 0; i < num_qsets; i++) { 4840 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 4841 buf->rdma_qsets[i].info.valid_sections = 4842 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4843 ICE_AQC_ELEM_VALID_EIR; 4844 buf->rdma_qsets[i].info.generic = 0; 4845 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 4846 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4847 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 4848 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4849 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 4850 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4851 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 4852 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4853 } 4854 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 4855 if (ret) { 4856 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 4857 goto rdma_error_exit; 4858 } 4859 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4860 for (i = 0; i < num_qsets; i++) { 4861 node.node_teid = buf->rdma_qsets[i].qset_teid; 4862 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 4863 &node, NULL); 4864 if (ret) 4865 break; 4866 qset_teid[i] = le32_to_cpu(node.node_teid); 4867 } 4868 rdma_error_exit: 4869 mutex_unlock(&pi->sched_lock); 4870 kfree(buf); 4871 return ret; 4872 } 4873 4874 /** 4875 * ice_dis_vsi_rdma_qset - free RDMA resources 4876 * @pi: port_info struct 4877 * @count: number of RDMA Qsets to free 4878 * @qset_teid: TEID of Qset node 4879 * @q_id: list of queue IDs being disabled 4880 */ 4881 int 4882 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 4883 u16 *q_id) 4884 { 4885 struct ice_aqc_dis_txq_item *qg_list; 4886 struct ice_hw *hw; 4887 int status = 0; 4888 u16 qg_size; 4889 int i; 4890 4891 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4892 return -EIO; 4893 4894 hw = pi->hw; 4895 4896 qg_size = struct_size(qg_list, q_id, 1); 4897 qg_list = kzalloc(qg_size, GFP_KERNEL); 4898 if (!qg_list) 4899 return -ENOMEM; 4900 4901 mutex_lock(&pi->sched_lock); 4902 4903 for (i = 0; i < count; i++) { 4904 struct ice_sched_node *node; 4905 4906 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 4907 if (!node) 4908 continue; 4909 4910 qg_list->parent_teid = node->info.parent_teid; 4911 qg_list->num_qs = 1; 4912 qg_list->q_id[0] = 4913 cpu_to_le16(q_id[i] | 4914 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 4915 4916 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 4917 ICE_NO_RESET, 0, NULL); 4918 if (status) 4919 break; 4920 4921 ice_free_sched_node(pi, node); 4922 } 4923 4924 mutex_unlock(&pi->sched_lock); 4925 kfree(qg_list); 4926 return status; 4927 } 4928 4929 /** 4930 * ice_replay_pre_init - replay pre initialization 4931 * @hw: pointer to the HW struct 4932 * 4933 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4934 */ 4935 static int ice_replay_pre_init(struct ice_hw *hw) 4936 { 4937 struct ice_switch_info *sw = hw->switch_info; 4938 u8 i; 4939 4940 /* Delete old entries from replay filter list head if there is any */ 4941 ice_rm_all_sw_replay_rule_info(hw); 4942 /* In start of replay, move entries into replay_rules list, it 4943 * will allow adding rules entries back to filt_rules list, 4944 * which is operational list. 4945 */ 4946 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 4947 list_replace_init(&sw->recp_list[i].filt_rules, 4948 &sw->recp_list[i].filt_replay_rules); 4949 ice_sched_replay_agg_vsi_preinit(hw); 4950 4951 return 0; 4952 } 4953 4954 /** 4955 * ice_replay_vsi - replay VSI configuration 4956 * @hw: pointer to the HW struct 4957 * @vsi_handle: driver VSI handle 4958 * 4959 * Restore all VSI configuration after reset. It is required to call this 4960 * function with main VSI first. 4961 */ 4962 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4963 { 4964 int status; 4965 4966 if (!ice_is_vsi_valid(hw, vsi_handle)) 4967 return -EINVAL; 4968 4969 /* Replay pre-initialization if there is any */ 4970 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 4971 status = ice_replay_pre_init(hw); 4972 if (status) 4973 return status; 4974 } 4975 /* Replay per VSI all RSS configurations */ 4976 status = ice_replay_rss_cfg(hw, vsi_handle); 4977 if (status) 4978 return status; 4979 /* Replay per VSI all filters */ 4980 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 4981 if (!status) 4982 status = ice_replay_vsi_agg(hw, vsi_handle); 4983 return status; 4984 } 4985 4986 /** 4987 * ice_replay_post - post replay configuration cleanup 4988 * @hw: pointer to the HW struct 4989 * 4990 * Post replay cleanup. 4991 */ 4992 void ice_replay_post(struct ice_hw *hw) 4993 { 4994 /* Delete old entries from replay filter list head */ 4995 ice_rm_all_sw_replay_rule_info(hw); 4996 ice_sched_replay_agg(hw); 4997 } 4998 4999 /** 5000 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 5001 * @hw: ptr to the hardware info 5002 * @reg: offset of 64 bit HW register to read from 5003 * @prev_stat_loaded: bool to specify if previous stats are loaded 5004 * @prev_stat: ptr to previous loaded stat value 5005 * @cur_stat: ptr to current stat value 5006 */ 5007 void 5008 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5009 u64 *prev_stat, u64 *cur_stat) 5010 { 5011 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 5012 5013 /* device stats are not reset at PFR, they likely will not be zeroed 5014 * when the driver starts. Thus, save the value from the first read 5015 * without adding to the statistic value so that we report stats which 5016 * count up from zero. 5017 */ 5018 if (!prev_stat_loaded) { 5019 *prev_stat = new_data; 5020 return; 5021 } 5022 5023 /* Calculate the difference between the new and old values, and then 5024 * add it to the software stat value. 5025 */ 5026 if (new_data >= *prev_stat) 5027 *cur_stat += new_data - *prev_stat; 5028 else 5029 /* to manage the potential roll-over */ 5030 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5031 5032 /* Update the previously stored value to prepare for next read */ 5033 *prev_stat = new_data; 5034 } 5035 5036 /** 5037 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5038 * @hw: ptr to the hardware info 5039 * @reg: offset of HW register to read from 5040 * @prev_stat_loaded: bool to specify if previous stats are loaded 5041 * @prev_stat: ptr to previous loaded stat value 5042 * @cur_stat: ptr to current stat value 5043 */ 5044 void 5045 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5046 u64 *prev_stat, u64 *cur_stat) 5047 { 5048 u32 new_data; 5049 5050 new_data = rd32(hw, reg); 5051 5052 /* device stats are not reset at PFR, they likely will not be zeroed 5053 * when the driver starts. Thus, save the value from the first read 5054 * without adding to the statistic value so that we report stats which 5055 * count up from zero. 5056 */ 5057 if (!prev_stat_loaded) { 5058 *prev_stat = new_data; 5059 return; 5060 } 5061 5062 /* Calculate the difference between the new and old values, and then 5063 * add it to the software stat value. 5064 */ 5065 if (new_data >= *prev_stat) 5066 *cur_stat += new_data - *prev_stat; 5067 else 5068 /* to manage the potential roll-over */ 5069 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5070 5071 /* Update the previously stored value to prepare for next read */ 5072 *prev_stat = new_data; 5073 } 5074 5075 /** 5076 * ice_sched_query_elem - query element information from HW 5077 * @hw: pointer to the HW struct 5078 * @node_teid: node TEID to be queried 5079 * @buf: buffer to element information 5080 * 5081 * This function queries HW element information 5082 */ 5083 int 5084 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5085 struct ice_aqc_txsched_elem_data *buf) 5086 { 5087 u16 buf_size, num_elem_ret = 0; 5088 int status; 5089 5090 buf_size = sizeof(*buf); 5091 memset(buf, 0, buf_size); 5092 buf->node_teid = cpu_to_le32(node_teid); 5093 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5094 NULL); 5095 if (status || num_elem_ret != 1) 5096 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5097 return status; 5098 } 5099 5100 /** 5101 * ice_aq_read_i2c 5102 * @hw: pointer to the hw struct 5103 * @topo_addr: topology address for a device to communicate with 5104 * @bus_addr: 7-bit I2C bus address 5105 * @addr: I2C memory address (I2C offset) with up to 16 bits 5106 * @params: I2C parameters: bit [7] - Repeated start, 5107 * bits [6:5] data offset size, 5108 * bit [4] - I2C address type, 5109 * bits [3:0] - data size to read (0-16 bytes) 5110 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5111 * @cd: pointer to command details structure or NULL 5112 * 5113 * Read I2C (0x06E2) 5114 */ 5115 int 5116 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5117 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5118 struct ice_sq_cd *cd) 5119 { 5120 struct ice_aq_desc desc = { 0 }; 5121 struct ice_aqc_i2c *cmd; 5122 u8 data_size; 5123 int status; 5124 5125 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5126 cmd = &desc.params.read_write_i2c; 5127 5128 if (!data) 5129 return -EINVAL; 5130 5131 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5132 5133 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5134 cmd->topo_addr = topo_addr; 5135 cmd->i2c_params = params; 5136 cmd->i2c_addr = addr; 5137 5138 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5139 if (!status) { 5140 struct ice_aqc_read_i2c_resp *resp; 5141 u8 i; 5142 5143 resp = &desc.params.read_i2c_resp; 5144 for (i = 0; i < data_size; i++) { 5145 *data = resp->i2c_data[i]; 5146 data++; 5147 } 5148 } 5149 5150 return status; 5151 } 5152 5153 /** 5154 * ice_aq_write_i2c 5155 * @hw: pointer to the hw struct 5156 * @topo_addr: topology address for a device to communicate with 5157 * @bus_addr: 7-bit I2C bus address 5158 * @addr: I2C memory address (I2C offset) with up to 16 bits 5159 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5160 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5161 * @cd: pointer to command details structure or NULL 5162 * 5163 * Write I2C (0x06E3) 5164 * 5165 * * Return: 5166 * * 0 - Successful write to the i2c device 5167 * * -EINVAL - Data size greater than 4 bytes 5168 * * -EIO - FW error 5169 */ 5170 int 5171 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5172 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5173 struct ice_sq_cd *cd) 5174 { 5175 struct ice_aq_desc desc = { 0 }; 5176 struct ice_aqc_i2c *cmd; 5177 u8 data_size; 5178 5179 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5180 cmd = &desc.params.read_write_i2c; 5181 5182 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5183 5184 /* data_size limited to 4 */ 5185 if (data_size > 4) 5186 return -EINVAL; 5187 5188 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5189 cmd->topo_addr = topo_addr; 5190 cmd->i2c_params = params; 5191 cmd->i2c_addr = addr; 5192 5193 memcpy(cmd->i2c_data, data, data_size); 5194 5195 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5196 } 5197 5198 /** 5199 * ice_aq_set_driver_param - Set driver parameter to share via firmware 5200 * @hw: pointer to the HW struct 5201 * @idx: parameter index to set 5202 * @value: the value to set the parameter to 5203 * @cd: pointer to command details structure or NULL 5204 * 5205 * Set the value of one of the software defined parameters. All PFs connected 5206 * to this device can read the value using ice_aq_get_driver_param. 5207 * 5208 * Note that firmware provides no synchronization or locking, and will not 5209 * save the parameter value during a device reset. It is expected that 5210 * a single PF will write the parameter value, while all other PFs will only 5211 * read it. 5212 */ 5213 int 5214 ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx, 5215 u32 value, struct ice_sq_cd *cd) 5216 { 5217 struct ice_aqc_driver_shared_params *cmd; 5218 struct ice_aq_desc desc; 5219 5220 if (idx >= ICE_AQC_DRIVER_PARAM_MAX) 5221 return -EIO; 5222 5223 cmd = &desc.params.drv_shared_params; 5224 5225 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params); 5226 5227 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_SET; 5228 cmd->param_indx = idx; 5229 cmd->param_val = cpu_to_le32(value); 5230 5231 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5232 } 5233 5234 /** 5235 * ice_aq_get_driver_param - Get driver parameter shared via firmware 5236 * @hw: pointer to the HW struct 5237 * @idx: parameter index to set 5238 * @value: storage to return the shared parameter 5239 * @cd: pointer to command details structure or NULL 5240 * 5241 * Get the value of one of the software defined parameters. 5242 * 5243 * Note that firmware provides no synchronization or locking. It is expected 5244 * that only a single PF will write a given parameter. 5245 */ 5246 int 5247 ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx, 5248 u32 *value, struct ice_sq_cd *cd) 5249 { 5250 struct ice_aqc_driver_shared_params *cmd; 5251 struct ice_aq_desc desc; 5252 int status; 5253 5254 if (idx >= ICE_AQC_DRIVER_PARAM_MAX) 5255 return -EIO; 5256 5257 cmd = &desc.params.drv_shared_params; 5258 5259 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params); 5260 5261 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_GET; 5262 cmd->param_indx = idx; 5263 5264 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5265 if (status) 5266 return status; 5267 5268 *value = le32_to_cpu(cmd->param_val); 5269 5270 return 0; 5271 } 5272 5273 /** 5274 * ice_aq_set_gpio 5275 * @hw: pointer to the hw struct 5276 * @gpio_ctrl_handle: GPIO controller node handle 5277 * @pin_idx: IO Number of the GPIO that needs to be set 5278 * @value: SW provide IO value to set in the LSB 5279 * @cd: pointer to command details structure or NULL 5280 * 5281 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 5282 */ 5283 int 5284 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 5285 struct ice_sq_cd *cd) 5286 { 5287 struct ice_aqc_gpio *cmd; 5288 struct ice_aq_desc desc; 5289 5290 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 5291 cmd = &desc.params.read_write_gpio; 5292 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5293 cmd->gpio_num = pin_idx; 5294 cmd->gpio_val = value ? 1 : 0; 5295 5296 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5297 } 5298 5299 /** 5300 * ice_aq_get_gpio 5301 * @hw: pointer to the hw struct 5302 * @gpio_ctrl_handle: GPIO controller node handle 5303 * @pin_idx: IO Number of the GPIO that needs to be set 5304 * @value: IO value read 5305 * @cd: pointer to command details structure or NULL 5306 * 5307 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 5308 * the topology 5309 */ 5310 int 5311 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 5312 bool *value, struct ice_sq_cd *cd) 5313 { 5314 struct ice_aqc_gpio *cmd; 5315 struct ice_aq_desc desc; 5316 int status; 5317 5318 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 5319 cmd = &desc.params.read_write_gpio; 5320 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5321 cmd->gpio_num = pin_idx; 5322 5323 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5324 if (status) 5325 return status; 5326 5327 *value = !!cmd->gpio_val; 5328 return 0; 5329 } 5330 5331 /** 5332 * ice_is_fw_api_min_ver 5333 * @hw: pointer to the hardware structure 5334 * @maj: major version 5335 * @min: minor version 5336 * @patch: patch version 5337 * 5338 * Checks if the firmware API is minimum version 5339 */ 5340 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 5341 { 5342 if (hw->api_maj_ver == maj) { 5343 if (hw->api_min_ver > min) 5344 return true; 5345 if (hw->api_min_ver == min && hw->api_patch >= patch) 5346 return true; 5347 } else if (hw->api_maj_ver > maj) { 5348 return true; 5349 } 5350 5351 return false; 5352 } 5353 5354 /** 5355 * ice_fw_supports_link_override 5356 * @hw: pointer to the hardware structure 5357 * 5358 * Checks if the firmware supports link override 5359 */ 5360 bool ice_fw_supports_link_override(struct ice_hw *hw) 5361 { 5362 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 5363 ICE_FW_API_LINK_OVERRIDE_MIN, 5364 ICE_FW_API_LINK_OVERRIDE_PATCH); 5365 } 5366 5367 /** 5368 * ice_get_link_default_override 5369 * @ldo: pointer to the link default override struct 5370 * @pi: pointer to the port info struct 5371 * 5372 * Gets the link default override for a port 5373 */ 5374 int 5375 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 5376 struct ice_port_info *pi) 5377 { 5378 u16 i, tlv, tlv_len, tlv_start, buf, offset; 5379 struct ice_hw *hw = pi->hw; 5380 int status; 5381 5382 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 5383 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 5384 if (status) { 5385 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 5386 return status; 5387 } 5388 5389 /* Each port has its own config; calculate for our port */ 5390 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 5391 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 5392 5393 /* link options first */ 5394 status = ice_read_sr_word(hw, tlv_start, &buf); 5395 if (status) { 5396 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5397 return status; 5398 } 5399 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 5400 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 5401 ICE_LINK_OVERRIDE_PHY_CFG_S; 5402 5403 /* link PHY config */ 5404 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 5405 status = ice_read_sr_word(hw, offset, &buf); 5406 if (status) { 5407 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 5408 return status; 5409 } 5410 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 5411 5412 /* PHY types low */ 5413 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 5414 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5415 status = ice_read_sr_word(hw, (offset + i), &buf); 5416 if (status) { 5417 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5418 return status; 5419 } 5420 /* shift 16 bits at a time to fill 64 bits */ 5421 ldo->phy_type_low |= ((u64)buf << (i * 16)); 5422 } 5423 5424 /* PHY types high */ 5425 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 5426 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 5427 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5428 status = ice_read_sr_word(hw, (offset + i), &buf); 5429 if (status) { 5430 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5431 return status; 5432 } 5433 /* shift 16 bits at a time to fill 64 bits */ 5434 ldo->phy_type_high |= ((u64)buf << (i * 16)); 5435 } 5436 5437 return status; 5438 } 5439 5440 /** 5441 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 5442 * @caps: get PHY capability data 5443 */ 5444 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 5445 { 5446 if (caps->caps & ICE_AQC_PHY_AN_MODE || 5447 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 5448 ICE_AQC_PHY_AN_EN_CLAUSE73 | 5449 ICE_AQC_PHY_AN_EN_CLAUSE37)) 5450 return true; 5451 5452 return false; 5453 } 5454 5455 /** 5456 * ice_aq_set_lldp_mib - Set the LLDP MIB 5457 * @hw: pointer to the HW struct 5458 * @mib_type: Local, Remote or both Local and Remote MIBs 5459 * @buf: pointer to the caller-supplied buffer to store the MIB block 5460 * @buf_size: size of the buffer (in bytes) 5461 * @cd: pointer to command details structure or NULL 5462 * 5463 * Set the LLDP MIB. (0x0A08) 5464 */ 5465 int 5466 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 5467 struct ice_sq_cd *cd) 5468 { 5469 struct ice_aqc_lldp_set_local_mib *cmd; 5470 struct ice_aq_desc desc; 5471 5472 cmd = &desc.params.lldp_set_mib; 5473 5474 if (buf_size == 0 || !buf) 5475 return -EINVAL; 5476 5477 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5478 5479 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 5480 desc.datalen = cpu_to_le16(buf_size); 5481 5482 cmd->type = mib_type; 5483 cmd->length = cpu_to_le16(buf_size); 5484 5485 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5486 } 5487 5488 /** 5489 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5490 * @hw: pointer to HW struct 5491 */ 5492 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 5493 { 5494 if (hw->mac_type != ICE_MAC_E810) 5495 return false; 5496 5497 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 5498 ICE_FW_API_LLDP_FLTR_MIN, 5499 ICE_FW_API_LLDP_FLTR_PATCH); 5500 } 5501 5502 /** 5503 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 5504 * @hw: pointer to HW struct 5505 * @vsi_num: absolute HW index for VSI 5506 * @add: boolean for if adding or removing a filter 5507 */ 5508 int 5509 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 5510 { 5511 struct ice_aqc_lldp_filter_ctrl *cmd; 5512 struct ice_aq_desc desc; 5513 5514 cmd = &desc.params.lldp_filter_ctrl; 5515 5516 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 5517 5518 if (add) 5519 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 5520 else 5521 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 5522 5523 cmd->vsi_num = cpu_to_le16(vsi_num); 5524 5525 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5526 } 5527 5528 /** 5529 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request 5530 * @hw: pointer to HW struct 5531 */ 5532 int ice_lldp_execute_pending_mib(struct ice_hw *hw) 5533 { 5534 struct ice_aq_desc desc; 5535 5536 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_execute_pending_mib); 5537 5538 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5539 } 5540 5541 /** 5542 * ice_fw_supports_report_dflt_cfg 5543 * @hw: pointer to the hardware structure 5544 * 5545 * Checks if the firmware supports report default configuration 5546 */ 5547 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 5548 { 5549 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 5550 ICE_FW_API_REPORT_DFLT_CFG_MIN, 5551 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 5552 } 5553 5554 /* each of the indexes into the following array match the speed of a return 5555 * value from the list of AQ returned speeds like the range: 5556 * ICE_AQ_LINK_SPEED_10MB .. ICE_AQ_LINK_SPEED_100GB excluding 5557 * ICE_AQ_LINK_SPEED_UNKNOWN which is BIT(15) and maps to BIT(14) in this 5558 * array. The array is defined as 15 elements long because the link_speed 5559 * returned by the firmware is a 16 bit * value, but is indexed 5560 * by [fls(speed) - 1] 5561 */ 5562 static const u32 ice_aq_to_link_speed[] = { 5563 SPEED_10, /* BIT(0) */ 5564 SPEED_100, 5565 SPEED_1000, 5566 SPEED_2500, 5567 SPEED_5000, 5568 SPEED_10000, 5569 SPEED_20000, 5570 SPEED_25000, 5571 SPEED_40000, 5572 SPEED_50000, 5573 SPEED_100000, /* BIT(10) */ 5574 }; 5575 5576 /** 5577 * ice_get_link_speed - get integer speed from table 5578 * @index: array index from fls(aq speed) - 1 5579 * 5580 * Returns: u32 value containing integer speed 5581 */ 5582 u32 ice_get_link_speed(u16 index) 5583 { 5584 if (index >= ARRAY_SIZE(ice_aq_to_link_speed)) 5585 return 0; 5586 5587 return ice_aq_to_link_speed[index]; 5588 } 5589