1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 9 #define ICE_PF_RESET_WAIT_COUNT 300 10 11 static const char * const ice_link_mode_str_low[] = { 12 [0] = "100BASE_TX", 13 [1] = "100M_SGMII", 14 [2] = "1000BASE_T", 15 [3] = "1000BASE_SX", 16 [4] = "1000BASE_LX", 17 [5] = "1000BASE_KX", 18 [6] = "1G_SGMII", 19 [7] = "2500BASE_T", 20 [8] = "2500BASE_X", 21 [9] = "2500BASE_KX", 22 [10] = "5GBASE_T", 23 [11] = "5GBASE_KR", 24 [12] = "10GBASE_T", 25 [13] = "10G_SFI_DA", 26 [14] = "10GBASE_SR", 27 [15] = "10GBASE_LR", 28 [16] = "10GBASE_KR_CR1", 29 [17] = "10G_SFI_AOC_ACC", 30 [18] = "10G_SFI_C2C", 31 [19] = "25GBASE_T", 32 [20] = "25GBASE_CR", 33 [21] = "25GBASE_CR_S", 34 [22] = "25GBASE_CR1", 35 [23] = "25GBASE_SR", 36 [24] = "25GBASE_LR", 37 [25] = "25GBASE_KR", 38 [26] = "25GBASE_KR_S", 39 [27] = "25GBASE_KR1", 40 [28] = "25G_AUI_AOC_ACC", 41 [29] = "25G_AUI_C2C", 42 [30] = "40GBASE_CR4", 43 [31] = "40GBASE_SR4", 44 [32] = "40GBASE_LR4", 45 [33] = "40GBASE_KR4", 46 [34] = "40G_XLAUI_AOC_ACC", 47 [35] = "40G_XLAUI", 48 [36] = "50GBASE_CR2", 49 [37] = "50GBASE_SR2", 50 [38] = "50GBASE_LR2", 51 [39] = "50GBASE_KR2", 52 [40] = "50G_LAUI2_AOC_ACC", 53 [41] = "50G_LAUI2", 54 [42] = "50G_AUI2_AOC_ACC", 55 [43] = "50G_AUI2", 56 [44] = "50GBASE_CP", 57 [45] = "50GBASE_SR", 58 [46] = "50GBASE_FR", 59 [47] = "50GBASE_LR", 60 [48] = "50GBASE_KR_PAM4", 61 [49] = "50G_AUI1_AOC_ACC", 62 [50] = "50G_AUI1", 63 [51] = "100GBASE_CR4", 64 [52] = "100GBASE_SR4", 65 [53] = "100GBASE_LR4", 66 [54] = "100GBASE_KR4", 67 [55] = "100G_CAUI4_AOC_ACC", 68 [56] = "100G_CAUI4", 69 [57] = "100G_AUI4_AOC_ACC", 70 [58] = "100G_AUI4", 71 [59] = "100GBASE_CR_PAM4", 72 [60] = "100GBASE_KR_PAM4", 73 [61] = "100GBASE_CP2", 74 [62] = "100GBASE_SR2", 75 [63] = "100GBASE_DR", 76 }; 77 78 static const char * const ice_link_mode_str_high[] = { 79 [0] = "100GBASE_KR2_PAM4", 80 [1] = "100G_CAUI2_AOC_ACC", 81 [2] = "100G_CAUI2", 82 [3] = "100G_AUI2_AOC_ACC", 83 [4] = "100G_AUI2", 84 }; 85 86 /** 87 * ice_dump_phy_type - helper function to dump phy_type 88 * @hw: pointer to the HW structure 89 * @low: 64 bit value for phy_type_low 90 * @high: 64 bit value for phy_type_high 91 * @prefix: prefix string to differentiate multiple dumps 92 */ 93 static void 94 ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix) 95 { 96 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, low); 97 98 for (u32 i = 0; i < BITS_PER_TYPE(typeof(low)); i++) { 99 if (low & BIT_ULL(i)) 100 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 101 prefix, i, ice_link_mode_str_low[i]); 102 } 103 104 ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, high); 105 106 for (u32 i = 0; i < BITS_PER_TYPE(typeof(high)); i++) { 107 if (high & BIT_ULL(i)) 108 ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", 109 prefix, i, ice_link_mode_str_high[i]); 110 } 111 } 112 113 /** 114 * ice_set_mac_type - Sets MAC type 115 * @hw: pointer to the HW structure 116 * 117 * This function sets the MAC type of the adapter based on the 118 * vendor ID and device ID stored in the HW structure. 119 */ 120 static int ice_set_mac_type(struct ice_hw *hw) 121 { 122 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 123 return -ENODEV; 124 125 switch (hw->device_id) { 126 case ICE_DEV_ID_E810C_BACKPLANE: 127 case ICE_DEV_ID_E810C_QSFP: 128 case ICE_DEV_ID_E810C_SFP: 129 case ICE_DEV_ID_E810_XXV_BACKPLANE: 130 case ICE_DEV_ID_E810_XXV_QSFP: 131 case ICE_DEV_ID_E810_XXV_SFP: 132 hw->mac_type = ICE_MAC_E810; 133 break; 134 case ICE_DEV_ID_E823C_10G_BASE_T: 135 case ICE_DEV_ID_E823C_BACKPLANE: 136 case ICE_DEV_ID_E823C_QSFP: 137 case ICE_DEV_ID_E823C_SFP: 138 case ICE_DEV_ID_E823C_SGMII: 139 case ICE_DEV_ID_E822C_10G_BASE_T: 140 case ICE_DEV_ID_E822C_BACKPLANE: 141 case ICE_DEV_ID_E822C_QSFP: 142 case ICE_DEV_ID_E822C_SFP: 143 case ICE_DEV_ID_E822C_SGMII: 144 case ICE_DEV_ID_E822L_10G_BASE_T: 145 case ICE_DEV_ID_E822L_BACKPLANE: 146 case ICE_DEV_ID_E822L_SFP: 147 case ICE_DEV_ID_E822L_SGMII: 148 case ICE_DEV_ID_E823L_10G_BASE_T: 149 case ICE_DEV_ID_E823L_1GBE: 150 case ICE_DEV_ID_E823L_BACKPLANE: 151 case ICE_DEV_ID_E823L_QSFP: 152 case ICE_DEV_ID_E823L_SFP: 153 hw->mac_type = ICE_MAC_GENERIC; 154 break; 155 default: 156 hw->mac_type = ICE_MAC_UNKNOWN; 157 break; 158 } 159 160 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 161 return 0; 162 } 163 164 /** 165 * ice_is_e810 166 * @hw: pointer to the hardware structure 167 * 168 * returns true if the device is E810 based, false if not. 169 */ 170 bool ice_is_e810(struct ice_hw *hw) 171 { 172 return hw->mac_type == ICE_MAC_E810; 173 } 174 175 /** 176 * ice_is_e810t 177 * @hw: pointer to the hardware structure 178 * 179 * returns true if the device is E810T based, false if not. 180 */ 181 bool ice_is_e810t(struct ice_hw *hw) 182 { 183 switch (hw->device_id) { 184 case ICE_DEV_ID_E810C_SFP: 185 switch (hw->subsystem_device_id) { 186 case ICE_SUBDEV_ID_E810T: 187 case ICE_SUBDEV_ID_E810T2: 188 case ICE_SUBDEV_ID_E810T3: 189 case ICE_SUBDEV_ID_E810T4: 190 case ICE_SUBDEV_ID_E810T6: 191 case ICE_SUBDEV_ID_E810T7: 192 return true; 193 } 194 break; 195 case ICE_DEV_ID_E810C_QSFP: 196 switch (hw->subsystem_device_id) { 197 case ICE_SUBDEV_ID_E810T2: 198 case ICE_SUBDEV_ID_E810T3: 199 case ICE_SUBDEV_ID_E810T5: 200 return true; 201 } 202 break; 203 default: 204 break; 205 } 206 207 return false; 208 } 209 210 /** 211 * ice_clear_pf_cfg - Clear PF configuration 212 * @hw: pointer to the hardware structure 213 * 214 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 215 * configuration, flow director filters, etc.). 216 */ 217 int ice_clear_pf_cfg(struct ice_hw *hw) 218 { 219 struct ice_aq_desc desc; 220 221 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 222 223 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 224 } 225 226 /** 227 * ice_aq_manage_mac_read - manage MAC address read command 228 * @hw: pointer to the HW struct 229 * @buf: a virtual buffer to hold the manage MAC read response 230 * @buf_size: Size of the virtual buffer 231 * @cd: pointer to command details structure or NULL 232 * 233 * This function is used to return per PF station MAC address (0x0107). 234 * NOTE: Upon successful completion of this command, MAC address information 235 * is returned in user specified buffer. Please interpret user specified 236 * buffer as "manage_mac_read" response. 237 * Response such as various MAC addresses are stored in HW struct (port.mac) 238 * ice_discover_dev_caps is expected to be called before this function is 239 * called. 240 */ 241 static int 242 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 243 struct ice_sq_cd *cd) 244 { 245 struct ice_aqc_manage_mac_read_resp *resp; 246 struct ice_aqc_manage_mac_read *cmd; 247 struct ice_aq_desc desc; 248 int status; 249 u16 flags; 250 u8 i; 251 252 cmd = &desc.params.mac_read; 253 254 if (buf_size < sizeof(*resp)) 255 return -EINVAL; 256 257 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 258 259 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 260 if (status) 261 return status; 262 263 resp = buf; 264 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 265 266 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 267 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 268 return -EIO; 269 } 270 271 /* A single port can report up to two (LAN and WoL) addresses */ 272 for (i = 0; i < cmd->num_addr; i++) 273 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 274 ether_addr_copy(hw->port_info->mac.lan_addr, 275 resp[i].mac_addr); 276 ether_addr_copy(hw->port_info->mac.perm_addr, 277 resp[i].mac_addr); 278 break; 279 } 280 281 return 0; 282 } 283 284 /** 285 * ice_aq_get_phy_caps - returns PHY capabilities 286 * @pi: port information structure 287 * @qual_mods: report qualified modules 288 * @report_mode: report mode capabilities 289 * @pcaps: structure for PHY capabilities to be filled 290 * @cd: pointer to command details structure or NULL 291 * 292 * Returns the various PHY capabilities supported on the Port (0x0600) 293 */ 294 int 295 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 296 struct ice_aqc_get_phy_caps_data *pcaps, 297 struct ice_sq_cd *cd) 298 { 299 struct ice_aqc_get_phy_caps *cmd; 300 u16 pcaps_size = sizeof(*pcaps); 301 struct ice_aq_desc desc; 302 const char *prefix; 303 struct ice_hw *hw; 304 int status; 305 306 cmd = &desc.params.get_phy; 307 308 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 309 return -EINVAL; 310 hw = pi->hw; 311 312 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 313 !ice_fw_supports_report_dflt_cfg(hw)) 314 return -EINVAL; 315 316 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 317 318 if (qual_mods) 319 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 320 321 cmd->param0 |= cpu_to_le16(report_mode); 322 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 323 324 ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); 325 326 switch (report_mode) { 327 case ICE_AQC_REPORT_TOPO_CAP_MEDIA: 328 prefix = "phy_caps_media"; 329 break; 330 case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA: 331 prefix = "phy_caps_no_media"; 332 break; 333 case ICE_AQC_REPORT_ACTIVE_CFG: 334 prefix = "phy_caps_active"; 335 break; 336 case ICE_AQC_REPORT_DFLT_CFG: 337 prefix = "phy_caps_default"; 338 break; 339 default: 340 prefix = "phy_caps_invalid"; 341 } 342 343 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), 344 le64_to_cpu(pcaps->phy_type_high), prefix); 345 346 ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", 347 prefix, report_mode); 348 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); 349 ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, 350 pcaps->low_power_ctrl_an); 351 ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, 352 pcaps->eee_cap); 353 ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, 354 pcaps->eeer_value); 355 ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, 356 pcaps->link_fec_options); 357 ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", 358 prefix, pcaps->module_compliance_enforcement); 359 ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", 360 prefix, pcaps->extended_compliance_code); 361 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, 362 pcaps->module_type[0]); 363 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, 364 pcaps->module_type[1]); 365 ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, 366 pcaps->module_type[2]); 367 368 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 369 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 370 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 371 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 372 sizeof(pi->phy.link_info.module_type)); 373 } 374 375 return status; 376 } 377 378 /** 379 * ice_aq_get_link_topo_handle - get link topology node return status 380 * @pi: port information structure 381 * @node_type: requested node type 382 * @cd: pointer to command details structure or NULL 383 * 384 * Get link topology node return status for specified node type (0x06E0) 385 * 386 * Node type cage can be used to determine if cage is present. If AQC 387 * returns error (ENOENT), then no cage present. If no cage present, then 388 * connection type is backplane or BASE-T. 389 */ 390 static int 391 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 392 struct ice_sq_cd *cd) 393 { 394 struct ice_aqc_get_link_topo *cmd; 395 struct ice_aq_desc desc; 396 397 cmd = &desc.params.get_link_topo; 398 399 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 400 401 cmd->addr.topo_params.node_type_ctx = 402 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 403 ICE_AQC_LINK_TOPO_NODE_CTX_S); 404 405 /* set node type */ 406 cmd->addr.topo_params.node_type_ctx |= 407 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 408 409 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 410 } 411 412 /** 413 * ice_is_media_cage_present 414 * @pi: port information structure 415 * 416 * Returns true if media cage is present, else false. If no cage, then 417 * media type is backplane or BASE-T. 418 */ 419 static bool ice_is_media_cage_present(struct ice_port_info *pi) 420 { 421 /* Node type cage can be used to determine if cage is present. If AQC 422 * returns error (ENOENT), then no cage present. If no cage present then 423 * connection type is backplane or BASE-T. 424 */ 425 return !ice_aq_get_link_topo_handle(pi, 426 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 427 NULL); 428 } 429 430 /** 431 * ice_get_media_type - Gets media type 432 * @pi: port information structure 433 */ 434 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 435 { 436 struct ice_link_status *hw_link_info; 437 438 if (!pi) 439 return ICE_MEDIA_UNKNOWN; 440 441 hw_link_info = &pi->phy.link_info; 442 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 443 /* If more than one media type is selected, report unknown */ 444 return ICE_MEDIA_UNKNOWN; 445 446 if (hw_link_info->phy_type_low) { 447 /* 1G SGMII is a special case where some DA cable PHYs 448 * may show this as an option when it really shouldn't 449 * be since SGMII is meant to be between a MAC and a PHY 450 * in a backplane. Try to detect this case and handle it 451 */ 452 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 453 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 454 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 455 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 456 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 457 return ICE_MEDIA_DA; 458 459 switch (hw_link_info->phy_type_low) { 460 case ICE_PHY_TYPE_LOW_1000BASE_SX: 461 case ICE_PHY_TYPE_LOW_1000BASE_LX: 462 case ICE_PHY_TYPE_LOW_10GBASE_SR: 463 case ICE_PHY_TYPE_LOW_10GBASE_LR: 464 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 465 case ICE_PHY_TYPE_LOW_25GBASE_SR: 466 case ICE_PHY_TYPE_LOW_25GBASE_LR: 467 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 468 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 469 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 470 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 471 case ICE_PHY_TYPE_LOW_50GBASE_SR: 472 case ICE_PHY_TYPE_LOW_50GBASE_FR: 473 case ICE_PHY_TYPE_LOW_50GBASE_LR: 474 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 475 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 476 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 477 case ICE_PHY_TYPE_LOW_100GBASE_DR: 478 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 479 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 480 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 481 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 482 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 483 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 484 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 485 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 486 return ICE_MEDIA_FIBER; 487 case ICE_PHY_TYPE_LOW_100BASE_TX: 488 case ICE_PHY_TYPE_LOW_1000BASE_T: 489 case ICE_PHY_TYPE_LOW_2500BASE_T: 490 case ICE_PHY_TYPE_LOW_5GBASE_T: 491 case ICE_PHY_TYPE_LOW_10GBASE_T: 492 case ICE_PHY_TYPE_LOW_25GBASE_T: 493 return ICE_MEDIA_BASET; 494 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 495 case ICE_PHY_TYPE_LOW_25GBASE_CR: 496 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 497 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 498 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 499 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 500 case ICE_PHY_TYPE_LOW_50GBASE_CP: 501 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 502 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 503 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 504 return ICE_MEDIA_DA; 505 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 506 case ICE_PHY_TYPE_LOW_40G_XLAUI: 507 case ICE_PHY_TYPE_LOW_50G_LAUI2: 508 case ICE_PHY_TYPE_LOW_50G_AUI2: 509 case ICE_PHY_TYPE_LOW_50G_AUI1: 510 case ICE_PHY_TYPE_LOW_100G_AUI4: 511 case ICE_PHY_TYPE_LOW_100G_CAUI4: 512 if (ice_is_media_cage_present(pi)) 513 return ICE_MEDIA_DA; 514 fallthrough; 515 case ICE_PHY_TYPE_LOW_1000BASE_KX: 516 case ICE_PHY_TYPE_LOW_2500BASE_KX: 517 case ICE_PHY_TYPE_LOW_2500BASE_X: 518 case ICE_PHY_TYPE_LOW_5GBASE_KR: 519 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 520 case ICE_PHY_TYPE_LOW_25GBASE_KR: 521 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 522 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 523 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 524 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 525 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 526 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 527 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 528 return ICE_MEDIA_BACKPLANE; 529 } 530 } else { 531 switch (hw_link_info->phy_type_high) { 532 case ICE_PHY_TYPE_HIGH_100G_AUI2: 533 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 534 if (ice_is_media_cage_present(pi)) 535 return ICE_MEDIA_DA; 536 fallthrough; 537 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 538 return ICE_MEDIA_BACKPLANE; 539 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 540 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 541 return ICE_MEDIA_FIBER; 542 } 543 } 544 return ICE_MEDIA_UNKNOWN; 545 } 546 547 /** 548 * ice_aq_get_link_info 549 * @pi: port information structure 550 * @ena_lse: enable/disable LinkStatusEvent reporting 551 * @link: pointer to link status structure - optional 552 * @cd: pointer to command details structure or NULL 553 * 554 * Get Link Status (0x607). Returns the link status of the adapter. 555 */ 556 int 557 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 558 struct ice_link_status *link, struct ice_sq_cd *cd) 559 { 560 struct ice_aqc_get_link_status_data link_data = { 0 }; 561 struct ice_aqc_get_link_status *resp; 562 struct ice_link_status *li_old, *li; 563 enum ice_media_type *hw_media_type; 564 struct ice_fc_info *hw_fc_info; 565 bool tx_pause, rx_pause; 566 struct ice_aq_desc desc; 567 struct ice_hw *hw; 568 u16 cmd_flags; 569 int status; 570 571 if (!pi) 572 return -EINVAL; 573 hw = pi->hw; 574 li_old = &pi->phy.link_info_old; 575 hw_media_type = &pi->phy.media_type; 576 li = &pi->phy.link_info; 577 hw_fc_info = &pi->fc; 578 579 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 580 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 581 resp = &desc.params.get_link_status; 582 resp->cmd_flags = cpu_to_le16(cmd_flags); 583 resp->lport_num = pi->lport; 584 585 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 586 587 if (status) 588 return status; 589 590 /* save off old link status information */ 591 *li_old = *li; 592 593 /* update current link status information */ 594 li->link_speed = le16_to_cpu(link_data.link_speed); 595 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 596 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 597 *hw_media_type = ice_get_media_type(pi); 598 li->link_info = link_data.link_info; 599 li->link_cfg_err = link_data.link_cfg_err; 600 li->an_info = link_data.an_info; 601 li->ext_info = link_data.ext_info; 602 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 603 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 604 li->topo_media_conflict = link_data.topo_media_conflict; 605 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 606 ICE_AQ_CFG_PACING_TYPE_M); 607 608 /* update fc info */ 609 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 610 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 611 if (tx_pause && rx_pause) 612 hw_fc_info->current_mode = ICE_FC_FULL; 613 else if (tx_pause) 614 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 615 else if (rx_pause) 616 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 617 else 618 hw_fc_info->current_mode = ICE_FC_NONE; 619 620 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 621 622 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 623 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 624 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 625 (unsigned long long)li->phy_type_low); 626 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 627 (unsigned long long)li->phy_type_high); 628 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 629 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 630 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 631 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 632 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 633 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 634 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 635 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 636 li->max_frame_size); 637 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 638 639 /* save link status information */ 640 if (link) 641 *link = *li; 642 643 /* flag cleared so calling functions don't call AQ again */ 644 pi->phy.get_link_info = false; 645 646 return 0; 647 } 648 649 /** 650 * ice_fill_tx_timer_and_fc_thresh 651 * @hw: pointer to the HW struct 652 * @cmd: pointer to MAC cfg structure 653 * 654 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 655 * descriptor 656 */ 657 static void 658 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 659 struct ice_aqc_set_mac_cfg *cmd) 660 { 661 u16 fc_thres_val, tx_timer_val; 662 u32 val; 663 664 /* We read back the transmit timer and FC threshold value of 665 * LFC. Thus, we will use index = 666 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 667 * 668 * Also, because we are operating on transmit timer and FC 669 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 670 */ 671 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 672 673 /* Retrieve the transmit timer */ 674 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 675 tx_timer_val = val & 676 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 677 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val); 678 679 /* Retrieve the FC threshold */ 680 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 681 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 682 683 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val); 684 } 685 686 /** 687 * ice_aq_set_mac_cfg 688 * @hw: pointer to the HW struct 689 * @max_frame_size: Maximum Frame Size to be supported 690 * @cd: pointer to command details structure or NULL 691 * 692 * Set MAC configuration (0x0603) 693 */ 694 int 695 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 696 { 697 struct ice_aqc_set_mac_cfg *cmd; 698 struct ice_aq_desc desc; 699 700 cmd = &desc.params.set_mac_cfg; 701 702 if (max_frame_size == 0) 703 return -EINVAL; 704 705 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 706 707 cmd->max_frame_size = cpu_to_le16(max_frame_size); 708 709 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 710 711 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 712 } 713 714 /** 715 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 716 * @hw: pointer to the HW struct 717 */ 718 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 719 { 720 struct ice_switch_info *sw; 721 int status; 722 723 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 724 sizeof(*hw->switch_info), GFP_KERNEL); 725 sw = hw->switch_info; 726 727 if (!sw) 728 return -ENOMEM; 729 730 INIT_LIST_HEAD(&sw->vsi_list_map_head); 731 sw->prof_res_bm_init = 0; 732 733 status = ice_init_def_sw_recp(hw); 734 if (status) { 735 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 736 return status; 737 } 738 return 0; 739 } 740 741 /** 742 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 743 * @hw: pointer to the HW struct 744 */ 745 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 746 { 747 struct ice_switch_info *sw = hw->switch_info; 748 struct ice_vsi_list_map_info *v_pos_map; 749 struct ice_vsi_list_map_info *v_tmp_map; 750 struct ice_sw_recipe *recps; 751 u8 i; 752 753 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 754 list_entry) { 755 list_del(&v_pos_map->list_entry); 756 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 757 } 758 recps = sw->recp_list; 759 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 760 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 761 762 recps[i].root_rid = i; 763 list_for_each_entry_safe(rg_entry, tmprg_entry, 764 &recps[i].rg_list, l_entry) { 765 list_del(&rg_entry->l_entry); 766 devm_kfree(ice_hw_to_dev(hw), rg_entry); 767 } 768 769 if (recps[i].adv_rule) { 770 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 771 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 772 773 mutex_destroy(&recps[i].filt_rule_lock); 774 list_for_each_entry_safe(lst_itr, tmp_entry, 775 &recps[i].filt_rules, 776 list_entry) { 777 list_del(&lst_itr->list_entry); 778 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 779 devm_kfree(ice_hw_to_dev(hw), lst_itr); 780 } 781 } else { 782 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 783 784 mutex_destroy(&recps[i].filt_rule_lock); 785 list_for_each_entry_safe(lst_itr, tmp_entry, 786 &recps[i].filt_rules, 787 list_entry) { 788 list_del(&lst_itr->list_entry); 789 devm_kfree(ice_hw_to_dev(hw), lst_itr); 790 } 791 } 792 if (recps[i].root_buf) 793 devm_kfree(ice_hw_to_dev(hw), recps[i].root_buf); 794 } 795 ice_rm_all_sw_replay_rule_info(hw); 796 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 797 devm_kfree(ice_hw_to_dev(hw), sw); 798 } 799 800 /** 801 * ice_get_fw_log_cfg - get FW logging configuration 802 * @hw: pointer to the HW struct 803 */ 804 static int ice_get_fw_log_cfg(struct ice_hw *hw) 805 { 806 struct ice_aq_desc desc; 807 __le16 *config; 808 int status; 809 u16 size; 810 811 size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX; 812 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL); 813 if (!config) 814 return -ENOMEM; 815 816 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 817 818 status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 819 if (!status) { 820 u16 i; 821 822 /* Save FW logging information into the HW structure */ 823 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 824 u16 v, m, flgs; 825 826 v = le16_to_cpu(config[i]); 827 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 828 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 829 830 if (m < ICE_AQC_FW_LOG_ID_MAX) 831 hw->fw_log.evnts[m].cur = flgs; 832 } 833 } 834 835 devm_kfree(ice_hw_to_dev(hw), config); 836 837 return status; 838 } 839 840 /** 841 * ice_cfg_fw_log - configure FW logging 842 * @hw: pointer to the HW struct 843 * @enable: enable certain FW logging events if true, disable all if false 844 * 845 * This function enables/disables the FW logging via Rx CQ events and a UART 846 * port based on predetermined configurations. FW logging via the Rx CQ can be 847 * enabled/disabled for individual PF's. However, FW logging via the UART can 848 * only be enabled/disabled for all PFs on the same device. 849 * 850 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 851 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 852 * before initializing the device. 853 * 854 * When re/configuring FW logging, callers need to update the "cfg" elements of 855 * the hw->fw_log.evnts array with the desired logging event configurations for 856 * modules of interest. When disabling FW logging completely, the callers can 857 * just pass false in the "enable" parameter. On completion, the function will 858 * update the "cur" element of the hw->fw_log.evnts array with the resulting 859 * logging event configurations of the modules that are being re/configured. FW 860 * logging modules that are not part of a reconfiguration operation retain their 861 * previous states. 862 * 863 * Before resetting the device, it is recommended that the driver disables FW 864 * logging before shutting down the control queue. When disabling FW logging 865 * ("enable" = false), the latest configurations of FW logging events stored in 866 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 867 * a device reset. 868 * 869 * When enabling FW logging to emit log messages via the Rx CQ during the 870 * device's initialization phase, a mechanism alternative to interrupt handlers 871 * needs to be used to extract FW log messages from the Rx CQ periodically and 872 * to prevent the Rx CQ from being full and stalling other types of control 873 * messages from FW to SW. Interrupts are typically disabled during the device's 874 * initialization phase. 875 */ 876 static int ice_cfg_fw_log(struct ice_hw *hw, bool enable) 877 { 878 struct ice_aqc_fw_logging *cmd; 879 u16 i, chgs = 0, len = 0; 880 struct ice_aq_desc desc; 881 __le16 *data = NULL; 882 u8 actv_evnts = 0; 883 void *buf = NULL; 884 int status = 0; 885 886 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 887 return 0; 888 889 /* Disable FW logging only when the control queue is still responsive */ 890 if (!enable && 891 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 892 return 0; 893 894 /* Get current FW log settings */ 895 status = ice_get_fw_log_cfg(hw); 896 if (status) 897 return status; 898 899 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 900 cmd = &desc.params.fw_logging; 901 902 /* Indicate which controls are valid */ 903 if (hw->fw_log.cq_en) 904 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 905 906 if (hw->fw_log.uart_en) 907 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 908 909 if (enable) { 910 /* Fill in an array of entries with FW logging modules and 911 * logging events being reconfigured. 912 */ 913 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 914 u16 val; 915 916 /* Keep track of enabled event types */ 917 actv_evnts |= hw->fw_log.evnts[i].cfg; 918 919 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 920 continue; 921 922 if (!data) { 923 data = devm_kcalloc(ice_hw_to_dev(hw), 924 ICE_AQC_FW_LOG_ID_MAX, 925 sizeof(*data), 926 GFP_KERNEL); 927 if (!data) 928 return -ENOMEM; 929 } 930 931 val = i << ICE_AQC_FW_LOG_ID_S; 932 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 933 data[chgs++] = cpu_to_le16(val); 934 } 935 936 /* Only enable FW logging if at least one module is specified. 937 * If FW logging is currently enabled but all modules are not 938 * enabled to emit log messages, disable FW logging altogether. 939 */ 940 if (actv_evnts) { 941 /* Leave if there is effectively no change */ 942 if (!chgs) 943 goto out; 944 945 if (hw->fw_log.cq_en) 946 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 947 948 if (hw->fw_log.uart_en) 949 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 950 951 buf = data; 952 len = sizeof(*data) * chgs; 953 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 954 } 955 } 956 957 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 958 if (!status) { 959 /* Update the current configuration to reflect events enabled. 960 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 961 * logging mode is enabled for the device. They do not reflect 962 * actual modules being enabled to emit log messages. So, their 963 * values remain unchanged even when all modules are disabled. 964 */ 965 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 966 967 hw->fw_log.actv_evnts = actv_evnts; 968 for (i = 0; i < cnt; i++) { 969 u16 v, m; 970 971 if (!enable) { 972 /* When disabling all FW logging events as part 973 * of device's de-initialization, the original 974 * configurations are retained, and can be used 975 * to reconfigure FW logging later if the device 976 * is re-initialized. 977 */ 978 hw->fw_log.evnts[i].cur = 0; 979 continue; 980 } 981 982 v = le16_to_cpu(data[i]); 983 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 984 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 985 } 986 } 987 988 out: 989 if (data) 990 devm_kfree(ice_hw_to_dev(hw), data); 991 992 return status; 993 } 994 995 /** 996 * ice_output_fw_log 997 * @hw: pointer to the HW struct 998 * @desc: pointer to the AQ message descriptor 999 * @buf: pointer to the buffer accompanying the AQ message 1000 * 1001 * Formats a FW Log message and outputs it via the standard driver logs. 1002 */ 1003 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 1004 { 1005 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 1006 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 1007 le16_to_cpu(desc->datalen)); 1008 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 1009 } 1010 1011 /** 1012 * ice_get_itr_intrl_gran 1013 * @hw: pointer to the HW struct 1014 * 1015 * Determines the ITR/INTRL granularities based on the maximum aggregate 1016 * bandwidth according to the device's configuration during power-on. 1017 */ 1018 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 1019 { 1020 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 1021 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 1022 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 1023 1024 switch (max_agg_bw) { 1025 case ICE_MAX_AGG_BW_200G: 1026 case ICE_MAX_AGG_BW_100G: 1027 case ICE_MAX_AGG_BW_50G: 1028 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 1029 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 1030 break; 1031 case ICE_MAX_AGG_BW_25G: 1032 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 1033 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 1034 break; 1035 } 1036 } 1037 1038 /** 1039 * ice_init_hw - main hardware initialization routine 1040 * @hw: pointer to the hardware structure 1041 */ 1042 int ice_init_hw(struct ice_hw *hw) 1043 { 1044 struct ice_aqc_get_phy_caps_data *pcaps; 1045 u16 mac_buf_len; 1046 void *mac_buf; 1047 int status; 1048 1049 /* Set MAC type based on DeviceID */ 1050 status = ice_set_mac_type(hw); 1051 if (status) 1052 return status; 1053 1054 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 1055 PF_FUNC_RID_FUNC_NUM_M) >> 1056 PF_FUNC_RID_FUNC_NUM_S; 1057 1058 status = ice_reset(hw, ICE_RESET_PFR); 1059 if (status) 1060 return status; 1061 1062 ice_get_itr_intrl_gran(hw); 1063 1064 status = ice_create_all_ctrlq(hw); 1065 if (status) 1066 goto err_unroll_cqinit; 1067 1068 /* Enable FW logging. Not fatal if this fails. */ 1069 status = ice_cfg_fw_log(hw, true); 1070 if (status) 1071 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 1072 1073 status = ice_clear_pf_cfg(hw); 1074 if (status) 1075 goto err_unroll_cqinit; 1076 1077 /* Set bit to enable Flow Director filters */ 1078 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 1079 INIT_LIST_HEAD(&hw->fdir_list_head); 1080 1081 ice_clear_pxe_mode(hw); 1082 1083 status = ice_init_nvm(hw); 1084 if (status) 1085 goto err_unroll_cqinit; 1086 1087 status = ice_get_caps(hw); 1088 if (status) 1089 goto err_unroll_cqinit; 1090 1091 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 1092 sizeof(*hw->port_info), GFP_KERNEL); 1093 if (!hw->port_info) { 1094 status = -ENOMEM; 1095 goto err_unroll_cqinit; 1096 } 1097 1098 /* set the back pointer to HW */ 1099 hw->port_info->hw = hw; 1100 1101 /* Initialize port_info struct with switch configuration data */ 1102 status = ice_get_initial_sw_cfg(hw); 1103 if (status) 1104 goto err_unroll_alloc; 1105 1106 hw->evb_veb = true; 1107 1108 /* Query the allocated resources for Tx scheduler */ 1109 status = ice_sched_query_res_alloc(hw); 1110 if (status) { 1111 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 1112 goto err_unroll_alloc; 1113 } 1114 ice_sched_get_psm_clk_freq(hw); 1115 1116 /* Initialize port_info struct with scheduler data */ 1117 status = ice_sched_init_port(hw->port_info); 1118 if (status) 1119 goto err_unroll_sched; 1120 1121 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 1122 if (!pcaps) { 1123 status = -ENOMEM; 1124 goto err_unroll_sched; 1125 } 1126 1127 /* Initialize port_info struct with PHY capabilities */ 1128 status = ice_aq_get_phy_caps(hw->port_info, false, 1129 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 1130 NULL); 1131 devm_kfree(ice_hw_to_dev(hw), pcaps); 1132 if (status) 1133 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 1134 status); 1135 1136 /* Initialize port_info struct with link information */ 1137 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1138 if (status) 1139 goto err_unroll_sched; 1140 1141 /* need a valid SW entry point to build a Tx tree */ 1142 if (!hw->sw_entry_point_layer) { 1143 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1144 status = -EIO; 1145 goto err_unroll_sched; 1146 } 1147 INIT_LIST_HEAD(&hw->agg_list); 1148 /* Initialize max burst size */ 1149 if (!hw->max_burst_size) 1150 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1151 1152 status = ice_init_fltr_mgmt_struct(hw); 1153 if (status) 1154 goto err_unroll_sched; 1155 1156 /* Get MAC information */ 1157 /* A single port can report up to two (LAN and WoL) addresses */ 1158 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 1159 sizeof(struct ice_aqc_manage_mac_read_resp), 1160 GFP_KERNEL); 1161 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1162 1163 if (!mac_buf) { 1164 status = -ENOMEM; 1165 goto err_unroll_fltr_mgmt_struct; 1166 } 1167 1168 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1169 devm_kfree(ice_hw_to_dev(hw), mac_buf); 1170 1171 if (status) 1172 goto err_unroll_fltr_mgmt_struct; 1173 /* enable jumbo frame support at MAC level */ 1174 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1175 if (status) 1176 goto err_unroll_fltr_mgmt_struct; 1177 /* Obtain counter base index which would be used by flow director */ 1178 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1179 if (status) 1180 goto err_unroll_fltr_mgmt_struct; 1181 status = ice_init_hw_tbls(hw); 1182 if (status) 1183 goto err_unroll_fltr_mgmt_struct; 1184 mutex_init(&hw->tnl_lock); 1185 return 0; 1186 1187 err_unroll_fltr_mgmt_struct: 1188 ice_cleanup_fltr_mgmt_struct(hw); 1189 err_unroll_sched: 1190 ice_sched_cleanup_all(hw); 1191 err_unroll_alloc: 1192 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1193 err_unroll_cqinit: 1194 ice_destroy_all_ctrlq(hw); 1195 return status; 1196 } 1197 1198 /** 1199 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1200 * @hw: pointer to the hardware structure 1201 * 1202 * This should be called only during nominal operation, not as a result of 1203 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1204 * applicable initializations if it fails for any reason. 1205 */ 1206 void ice_deinit_hw(struct ice_hw *hw) 1207 { 1208 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1209 ice_cleanup_fltr_mgmt_struct(hw); 1210 1211 ice_sched_cleanup_all(hw); 1212 ice_sched_clear_agg(hw); 1213 ice_free_seg(hw); 1214 ice_free_hw_tbls(hw); 1215 mutex_destroy(&hw->tnl_lock); 1216 1217 if (hw->port_info) { 1218 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1219 hw->port_info = NULL; 1220 } 1221 1222 /* Attempt to disable FW logging before shutting down control queues */ 1223 ice_cfg_fw_log(hw, false); 1224 ice_destroy_all_ctrlq(hw); 1225 1226 /* Clear VSI contexts if not already cleared */ 1227 ice_clear_all_vsi_ctx(hw); 1228 } 1229 1230 /** 1231 * ice_check_reset - Check to see if a global reset is complete 1232 * @hw: pointer to the hardware structure 1233 */ 1234 int ice_check_reset(struct ice_hw *hw) 1235 { 1236 u32 cnt, reg = 0, grst_timeout, uld_mask; 1237 1238 /* Poll for Device Active state in case a recent CORER, GLOBR, 1239 * or EMPR has occurred. The grst delay value is in 100ms units. 1240 * Add 1sec for outstanding AQ commands that can take a long time. 1241 */ 1242 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1243 GLGEN_RSTCTL_GRSTDEL_S) + 10; 1244 1245 for (cnt = 0; cnt < grst_timeout; cnt++) { 1246 mdelay(100); 1247 reg = rd32(hw, GLGEN_RSTAT); 1248 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1249 break; 1250 } 1251 1252 if (cnt == grst_timeout) { 1253 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1254 return -EIO; 1255 } 1256 1257 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1258 GLNVM_ULD_PCIER_DONE_1_M |\ 1259 GLNVM_ULD_CORER_DONE_M |\ 1260 GLNVM_ULD_GLOBR_DONE_M |\ 1261 GLNVM_ULD_POR_DONE_M |\ 1262 GLNVM_ULD_POR_DONE_1_M |\ 1263 GLNVM_ULD_PCIER_DONE_2_M) 1264 1265 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1266 GLNVM_ULD_PE_DONE_M : 0); 1267 1268 /* Device is Active; check Global Reset processes are done */ 1269 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1270 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1271 if (reg == uld_mask) { 1272 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1273 break; 1274 } 1275 mdelay(10); 1276 } 1277 1278 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1279 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1280 reg); 1281 return -EIO; 1282 } 1283 1284 return 0; 1285 } 1286 1287 /** 1288 * ice_pf_reset - Reset the PF 1289 * @hw: pointer to the hardware structure 1290 * 1291 * If a global reset has been triggered, this function checks 1292 * for its completion and then issues the PF reset 1293 */ 1294 static int ice_pf_reset(struct ice_hw *hw) 1295 { 1296 u32 cnt, reg; 1297 1298 /* If at function entry a global reset was already in progress, i.e. 1299 * state is not 'device active' or any of the reset done bits are not 1300 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1301 * global reset is done. 1302 */ 1303 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1304 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1305 /* poll on global reset currently in progress until done */ 1306 if (ice_check_reset(hw)) 1307 return -EIO; 1308 1309 return 0; 1310 } 1311 1312 /* Reset the PF */ 1313 reg = rd32(hw, PFGEN_CTRL); 1314 1315 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1316 1317 /* Wait for the PFR to complete. The wait time is the global config lock 1318 * timeout plus the PFR timeout which will account for a possible reset 1319 * that is occurring during a download package operation. 1320 */ 1321 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1322 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1323 reg = rd32(hw, PFGEN_CTRL); 1324 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1325 break; 1326 1327 mdelay(1); 1328 } 1329 1330 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1331 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1332 return -EIO; 1333 } 1334 1335 return 0; 1336 } 1337 1338 /** 1339 * ice_reset - Perform different types of reset 1340 * @hw: pointer to the hardware structure 1341 * @req: reset request 1342 * 1343 * This function triggers a reset as specified by the req parameter. 1344 * 1345 * Note: 1346 * If anything other than a PF reset is triggered, PXE mode is restored. 1347 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1348 * interface has been restored in the rebuild flow. 1349 */ 1350 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1351 { 1352 u32 val = 0; 1353 1354 switch (req) { 1355 case ICE_RESET_PFR: 1356 return ice_pf_reset(hw); 1357 case ICE_RESET_CORER: 1358 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1359 val = GLGEN_RTRIG_CORER_M; 1360 break; 1361 case ICE_RESET_GLOBR: 1362 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1363 val = GLGEN_RTRIG_GLOBR_M; 1364 break; 1365 default: 1366 return -EINVAL; 1367 } 1368 1369 val |= rd32(hw, GLGEN_RTRIG); 1370 wr32(hw, GLGEN_RTRIG, val); 1371 ice_flush(hw); 1372 1373 /* wait for the FW to be ready */ 1374 return ice_check_reset(hw); 1375 } 1376 1377 /** 1378 * ice_copy_rxq_ctx_to_hw 1379 * @hw: pointer to the hardware structure 1380 * @ice_rxq_ctx: pointer to the rxq context 1381 * @rxq_index: the index of the Rx queue 1382 * 1383 * Copies rxq context from dense structure to HW register space 1384 */ 1385 static int 1386 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1387 { 1388 u8 i; 1389 1390 if (!ice_rxq_ctx) 1391 return -EINVAL; 1392 1393 if (rxq_index > QRX_CTRL_MAX_INDEX) 1394 return -EINVAL; 1395 1396 /* Copy each dword separately to HW */ 1397 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1398 wr32(hw, QRX_CONTEXT(i, rxq_index), 1399 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1400 1401 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1402 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1403 } 1404 1405 return 0; 1406 } 1407 1408 /* LAN Rx Queue Context */ 1409 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1410 /* Field Width LSB */ 1411 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1412 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1413 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1414 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1415 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1416 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1417 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1418 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1419 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1420 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1421 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1422 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1423 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1424 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1425 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1426 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1427 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1428 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1429 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1430 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1431 { 0 } 1432 }; 1433 1434 /** 1435 * ice_write_rxq_ctx 1436 * @hw: pointer to the hardware structure 1437 * @rlan_ctx: pointer to the rxq context 1438 * @rxq_index: the index of the Rx queue 1439 * 1440 * Converts rxq context from sparse to dense structure and then writes 1441 * it to HW register space and enables the hardware to prefetch descriptors 1442 * instead of only fetching them on demand 1443 */ 1444 int 1445 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1446 u32 rxq_index) 1447 { 1448 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1449 1450 if (!rlan_ctx) 1451 return -EINVAL; 1452 1453 rlan_ctx->prefena = 1; 1454 1455 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1456 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1457 } 1458 1459 /* LAN Tx Queue Context */ 1460 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1461 /* Field Width LSB */ 1462 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1463 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1464 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1465 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1466 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1467 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1468 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1469 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1470 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1471 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1472 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1473 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1474 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1475 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1476 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1477 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1478 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1479 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1480 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1481 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1482 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1483 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1484 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1485 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1486 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1487 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1488 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1489 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1490 { 0 } 1491 }; 1492 1493 /* Sideband Queue command wrappers */ 1494 1495 /** 1496 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1497 * @hw: pointer to the HW struct 1498 * @desc: descriptor describing the command 1499 * @buf: buffer to use for indirect commands (NULL for direct commands) 1500 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1501 * @cd: pointer to command details structure 1502 */ 1503 static int 1504 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1505 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1506 { 1507 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1508 (struct ice_aq_desc *)desc, buf, buf_size, cd); 1509 } 1510 1511 /** 1512 * ice_sbq_rw_reg - Fill Sideband Queue command 1513 * @hw: pointer to the HW struct 1514 * @in: message info to be filled in descriptor 1515 */ 1516 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in) 1517 { 1518 struct ice_sbq_cmd_desc desc = {0}; 1519 struct ice_sbq_msg_req msg = {0}; 1520 u16 msg_len; 1521 int status; 1522 1523 msg_len = sizeof(msg); 1524 1525 msg.dest_dev = in->dest_dev; 1526 msg.opcode = in->opcode; 1527 msg.flags = ICE_SBQ_MSG_FLAGS; 1528 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1529 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1530 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1531 1532 if (in->opcode) 1533 msg.data = cpu_to_le32(in->data); 1534 else 1535 /* data read comes back in completion, so shorten the struct by 1536 * sizeof(msg.data) 1537 */ 1538 msg_len -= sizeof(msg.data); 1539 1540 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 1541 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1542 desc.param0.cmd_len = cpu_to_le16(msg_len); 1543 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1544 if (!status && !in->opcode) 1545 in->data = le32_to_cpu 1546 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1547 return status; 1548 } 1549 1550 /* FW Admin Queue command wrappers */ 1551 1552 /* Software lock/mutex that is meant to be held while the Global Config Lock 1553 * in firmware is acquired by the software to prevent most (but not all) types 1554 * of AQ commands from being sent to FW 1555 */ 1556 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1557 1558 /** 1559 * ice_should_retry_sq_send_cmd 1560 * @opcode: AQ opcode 1561 * 1562 * Decide if we should retry the send command routine for the ATQ, depending 1563 * on the opcode. 1564 */ 1565 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1566 { 1567 switch (opcode) { 1568 case ice_aqc_opc_get_link_topo: 1569 case ice_aqc_opc_lldp_stop: 1570 case ice_aqc_opc_lldp_start: 1571 case ice_aqc_opc_lldp_filter_ctrl: 1572 return true; 1573 } 1574 1575 return false; 1576 } 1577 1578 /** 1579 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1580 * @hw: pointer to the HW struct 1581 * @cq: pointer to the specific Control queue 1582 * @desc: prefilled descriptor describing the command 1583 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1584 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1585 * @cd: pointer to command details structure 1586 * 1587 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1588 * Queue if the EBUSY AQ error is returned. 1589 */ 1590 static int 1591 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1592 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1593 struct ice_sq_cd *cd) 1594 { 1595 struct ice_aq_desc desc_cpy; 1596 bool is_cmd_for_retry; 1597 u8 *buf_cpy = NULL; 1598 u8 idx = 0; 1599 u16 opcode; 1600 int status; 1601 1602 opcode = le16_to_cpu(desc->opcode); 1603 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1604 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1605 1606 if (is_cmd_for_retry) { 1607 if (buf) { 1608 buf_cpy = kzalloc(buf_size, GFP_KERNEL); 1609 if (!buf_cpy) 1610 return -ENOMEM; 1611 } 1612 1613 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1614 } 1615 1616 do { 1617 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1618 1619 if (!is_cmd_for_retry || !status || 1620 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1621 break; 1622 1623 if (buf_cpy) 1624 memcpy(buf, buf_cpy, buf_size); 1625 1626 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1627 1628 mdelay(ICE_SQ_SEND_DELAY_TIME_MS); 1629 1630 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1631 1632 kfree(buf_cpy); 1633 1634 return status; 1635 } 1636 1637 /** 1638 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1639 * @hw: pointer to the HW struct 1640 * @desc: descriptor describing the command 1641 * @buf: buffer to use for indirect commands (NULL for direct commands) 1642 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1643 * @cd: pointer to command details structure 1644 * 1645 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1646 */ 1647 int 1648 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1649 u16 buf_size, struct ice_sq_cd *cd) 1650 { 1651 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1652 bool lock_acquired = false; 1653 int status; 1654 1655 /* When a package download is in process (i.e. when the firmware's 1656 * Global Configuration Lock resource is held), only the Download 1657 * Package, Get Version, Get Package Info List, Upload Section, 1658 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1659 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1660 * Recipes to Profile Association, and Release Resource (with resource 1661 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1662 * must block until the package download completes and the Global Config 1663 * Lock is released. See also ice_acquire_global_cfg_lock(). 1664 */ 1665 switch (le16_to_cpu(desc->opcode)) { 1666 case ice_aqc_opc_download_pkg: 1667 case ice_aqc_opc_get_pkg_info_list: 1668 case ice_aqc_opc_get_ver: 1669 case ice_aqc_opc_upload_section: 1670 case ice_aqc_opc_update_pkg: 1671 case ice_aqc_opc_set_port_params: 1672 case ice_aqc_opc_get_vlan_mode_parameters: 1673 case ice_aqc_opc_set_vlan_mode_parameters: 1674 case ice_aqc_opc_add_recipe: 1675 case ice_aqc_opc_recipe_to_profile: 1676 case ice_aqc_opc_get_recipe: 1677 case ice_aqc_opc_get_recipe_to_profile: 1678 break; 1679 case ice_aqc_opc_release_res: 1680 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1681 break; 1682 fallthrough; 1683 default: 1684 mutex_lock(&ice_global_cfg_lock_sw); 1685 lock_acquired = true; 1686 break; 1687 } 1688 1689 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1690 if (lock_acquired) 1691 mutex_unlock(&ice_global_cfg_lock_sw); 1692 1693 return status; 1694 } 1695 1696 /** 1697 * ice_aq_get_fw_ver 1698 * @hw: pointer to the HW struct 1699 * @cd: pointer to command details structure or NULL 1700 * 1701 * Get the firmware version (0x0001) from the admin queue commands 1702 */ 1703 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1704 { 1705 struct ice_aqc_get_ver *resp; 1706 struct ice_aq_desc desc; 1707 int status; 1708 1709 resp = &desc.params.get_ver; 1710 1711 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1712 1713 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1714 1715 if (!status) { 1716 hw->fw_branch = resp->fw_branch; 1717 hw->fw_maj_ver = resp->fw_major; 1718 hw->fw_min_ver = resp->fw_minor; 1719 hw->fw_patch = resp->fw_patch; 1720 hw->fw_build = le32_to_cpu(resp->fw_build); 1721 hw->api_branch = resp->api_branch; 1722 hw->api_maj_ver = resp->api_major; 1723 hw->api_min_ver = resp->api_minor; 1724 hw->api_patch = resp->api_patch; 1725 } 1726 1727 return status; 1728 } 1729 1730 /** 1731 * ice_aq_send_driver_ver 1732 * @hw: pointer to the HW struct 1733 * @dv: driver's major, minor version 1734 * @cd: pointer to command details structure or NULL 1735 * 1736 * Send the driver version (0x0002) to the firmware 1737 */ 1738 int 1739 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1740 struct ice_sq_cd *cd) 1741 { 1742 struct ice_aqc_driver_ver *cmd; 1743 struct ice_aq_desc desc; 1744 u16 len; 1745 1746 cmd = &desc.params.driver_ver; 1747 1748 if (!dv) 1749 return -EINVAL; 1750 1751 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1752 1753 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1754 cmd->major_ver = dv->major_ver; 1755 cmd->minor_ver = dv->minor_ver; 1756 cmd->build_ver = dv->build_ver; 1757 cmd->subbuild_ver = dv->subbuild_ver; 1758 1759 len = 0; 1760 while (len < sizeof(dv->driver_string) && 1761 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1762 len++; 1763 1764 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1765 } 1766 1767 /** 1768 * ice_aq_q_shutdown 1769 * @hw: pointer to the HW struct 1770 * @unloading: is the driver unloading itself 1771 * 1772 * Tell the Firmware that we're shutting down the AdminQ and whether 1773 * or not the driver is unloading as well (0x0003). 1774 */ 1775 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1776 { 1777 struct ice_aqc_q_shutdown *cmd; 1778 struct ice_aq_desc desc; 1779 1780 cmd = &desc.params.q_shutdown; 1781 1782 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1783 1784 if (unloading) 1785 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1786 1787 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1788 } 1789 1790 /** 1791 * ice_aq_req_res 1792 * @hw: pointer to the HW struct 1793 * @res: resource ID 1794 * @access: access type 1795 * @sdp_number: resource number 1796 * @timeout: the maximum time in ms that the driver may hold the resource 1797 * @cd: pointer to command details structure or NULL 1798 * 1799 * Requests common resource using the admin queue commands (0x0008). 1800 * When attempting to acquire the Global Config Lock, the driver can 1801 * learn of three states: 1802 * 1) 0 - acquired lock, and can perform download package 1803 * 2) -EIO - did not get lock, driver should fail to load 1804 * 3) -EALREADY - did not get lock, but another driver has 1805 * successfully downloaded the package; the driver does 1806 * not have to download the package and can continue 1807 * loading 1808 * 1809 * Note that if the caller is in an acquire lock, perform action, release lock 1810 * phase of operation, it is possible that the FW may detect a timeout and issue 1811 * a CORER. In this case, the driver will receive a CORER interrupt and will 1812 * have to determine its cause. The calling thread that is handling this flow 1813 * will likely get an error propagated back to it indicating the Download 1814 * Package, Update Package or the Release Resource AQ commands timed out. 1815 */ 1816 static int 1817 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1818 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1819 struct ice_sq_cd *cd) 1820 { 1821 struct ice_aqc_req_res *cmd_resp; 1822 struct ice_aq_desc desc; 1823 int status; 1824 1825 cmd_resp = &desc.params.res_owner; 1826 1827 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1828 1829 cmd_resp->res_id = cpu_to_le16(res); 1830 cmd_resp->access_type = cpu_to_le16(access); 1831 cmd_resp->res_number = cpu_to_le32(sdp_number); 1832 cmd_resp->timeout = cpu_to_le32(*timeout); 1833 *timeout = 0; 1834 1835 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1836 1837 /* The completion specifies the maximum time in ms that the driver 1838 * may hold the resource in the Timeout field. 1839 */ 1840 1841 /* Global config lock response utilizes an additional status field. 1842 * 1843 * If the Global config lock resource is held by some other driver, the 1844 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1845 * and the timeout field indicates the maximum time the current owner 1846 * of the resource has to free it. 1847 */ 1848 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1849 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1850 *timeout = le32_to_cpu(cmd_resp->timeout); 1851 return 0; 1852 } else if (le16_to_cpu(cmd_resp->status) == 1853 ICE_AQ_RES_GLBL_IN_PROG) { 1854 *timeout = le32_to_cpu(cmd_resp->timeout); 1855 return -EIO; 1856 } else if (le16_to_cpu(cmd_resp->status) == 1857 ICE_AQ_RES_GLBL_DONE) { 1858 return -EALREADY; 1859 } 1860 1861 /* invalid FW response, force a timeout immediately */ 1862 *timeout = 0; 1863 return -EIO; 1864 } 1865 1866 /* If the resource is held by some other driver, the command completes 1867 * with a busy return value and the timeout field indicates the maximum 1868 * time the current owner of the resource has to free it. 1869 */ 1870 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1871 *timeout = le32_to_cpu(cmd_resp->timeout); 1872 1873 return status; 1874 } 1875 1876 /** 1877 * ice_aq_release_res 1878 * @hw: pointer to the HW struct 1879 * @res: resource ID 1880 * @sdp_number: resource number 1881 * @cd: pointer to command details structure or NULL 1882 * 1883 * release common resource using the admin queue commands (0x0009) 1884 */ 1885 static int 1886 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1887 struct ice_sq_cd *cd) 1888 { 1889 struct ice_aqc_req_res *cmd; 1890 struct ice_aq_desc desc; 1891 1892 cmd = &desc.params.res_owner; 1893 1894 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1895 1896 cmd->res_id = cpu_to_le16(res); 1897 cmd->res_number = cpu_to_le32(sdp_number); 1898 1899 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1900 } 1901 1902 /** 1903 * ice_acquire_res 1904 * @hw: pointer to the HW structure 1905 * @res: resource ID 1906 * @access: access type (read or write) 1907 * @timeout: timeout in milliseconds 1908 * 1909 * This function will attempt to acquire the ownership of a resource. 1910 */ 1911 int 1912 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1913 enum ice_aq_res_access_type access, u32 timeout) 1914 { 1915 #define ICE_RES_POLLING_DELAY_MS 10 1916 u32 delay = ICE_RES_POLLING_DELAY_MS; 1917 u32 time_left = timeout; 1918 int status; 1919 1920 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1921 1922 /* A return code of -EALREADY means that another driver has 1923 * previously acquired the resource and performed any necessary updates; 1924 * in this case the caller does not obtain the resource and has no 1925 * further work to do. 1926 */ 1927 if (status == -EALREADY) 1928 goto ice_acquire_res_exit; 1929 1930 if (status) 1931 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1932 1933 /* If necessary, poll until the current lock owner timeouts */ 1934 timeout = time_left; 1935 while (status && timeout && time_left) { 1936 mdelay(delay); 1937 timeout = (timeout > delay) ? timeout - delay : 0; 1938 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1939 1940 if (status == -EALREADY) 1941 /* lock free, but no work to do */ 1942 break; 1943 1944 if (!status) 1945 /* lock acquired */ 1946 break; 1947 } 1948 if (status && status != -EALREADY) 1949 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1950 1951 ice_acquire_res_exit: 1952 if (status == -EALREADY) { 1953 if (access == ICE_RES_WRITE) 1954 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1955 else 1956 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 1957 } 1958 return status; 1959 } 1960 1961 /** 1962 * ice_release_res 1963 * @hw: pointer to the HW structure 1964 * @res: resource ID 1965 * 1966 * This function will release a resource using the proper Admin Command. 1967 */ 1968 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1969 { 1970 u32 total_delay = 0; 1971 int status; 1972 1973 status = ice_aq_release_res(hw, res, 0, NULL); 1974 1975 /* there are some rare cases when trying to release the resource 1976 * results in an admin queue timeout, so handle them correctly 1977 */ 1978 while ((status == -EIO) && (total_delay < hw->adminq.sq_cmd_timeout)) { 1979 mdelay(1); 1980 status = ice_aq_release_res(hw, res, 0, NULL); 1981 total_delay++; 1982 } 1983 } 1984 1985 /** 1986 * ice_aq_alloc_free_res - command to allocate/free resources 1987 * @hw: pointer to the HW struct 1988 * @num_entries: number of resource entries in buffer 1989 * @buf: Indirect buffer to hold data parameters and response 1990 * @buf_size: size of buffer for indirect commands 1991 * @opc: pass in the command opcode 1992 * @cd: pointer to command details structure or NULL 1993 * 1994 * Helper function to allocate/free resources using the admin queue commands 1995 */ 1996 int 1997 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1998 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1999 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2000 { 2001 struct ice_aqc_alloc_free_res_cmd *cmd; 2002 struct ice_aq_desc desc; 2003 2004 cmd = &desc.params.sw_res_ctrl; 2005 2006 if (!buf) 2007 return -EINVAL; 2008 2009 if (buf_size < flex_array_size(buf, elem, num_entries)) 2010 return -EINVAL; 2011 2012 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2013 2014 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2015 2016 cmd->num_entries = cpu_to_le16(num_entries); 2017 2018 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2019 } 2020 2021 /** 2022 * ice_alloc_hw_res - allocate resource 2023 * @hw: pointer to the HW struct 2024 * @type: type of resource 2025 * @num: number of resources to allocate 2026 * @btm: allocate from bottom 2027 * @res: pointer to array that will receive the resources 2028 */ 2029 int 2030 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 2031 { 2032 struct ice_aqc_alloc_free_res_elem *buf; 2033 u16 buf_len; 2034 int status; 2035 2036 buf_len = struct_size(buf, elem, num); 2037 buf = kzalloc(buf_len, GFP_KERNEL); 2038 if (!buf) 2039 return -ENOMEM; 2040 2041 /* Prepare buffer to allocate resource. */ 2042 buf->num_elems = cpu_to_le16(num); 2043 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 2044 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 2045 if (btm) 2046 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 2047 2048 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 2049 ice_aqc_opc_alloc_res, NULL); 2050 if (status) 2051 goto ice_alloc_res_exit; 2052 2053 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 2054 2055 ice_alloc_res_exit: 2056 kfree(buf); 2057 return status; 2058 } 2059 2060 /** 2061 * ice_free_hw_res - free allocated HW resource 2062 * @hw: pointer to the HW struct 2063 * @type: type of resource to free 2064 * @num: number of resources 2065 * @res: pointer to array that contains the resources to free 2066 */ 2067 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 2068 { 2069 struct ice_aqc_alloc_free_res_elem *buf; 2070 u16 buf_len; 2071 int status; 2072 2073 buf_len = struct_size(buf, elem, num); 2074 buf = kzalloc(buf_len, GFP_KERNEL); 2075 if (!buf) 2076 return -ENOMEM; 2077 2078 /* Prepare buffer to free resource. */ 2079 buf->num_elems = cpu_to_le16(num); 2080 buf->res_type = cpu_to_le16(type); 2081 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 2082 2083 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 2084 ice_aqc_opc_free_res, NULL); 2085 if (status) 2086 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 2087 2088 kfree(buf); 2089 return status; 2090 } 2091 2092 /** 2093 * ice_get_num_per_func - determine number of resources per PF 2094 * @hw: pointer to the HW structure 2095 * @max: value to be evenly split between each PF 2096 * 2097 * Determine the number of valid functions by going through the bitmap returned 2098 * from parsing capabilities and use this to calculate the number of resources 2099 * per PF based on the max value passed in. 2100 */ 2101 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 2102 { 2103 u8 funcs; 2104 2105 #define ICE_CAPS_VALID_FUNCS_M 0xFF 2106 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 2107 ICE_CAPS_VALID_FUNCS_M); 2108 2109 if (!funcs) 2110 return 0; 2111 2112 return max / funcs; 2113 } 2114 2115 /** 2116 * ice_parse_common_caps - parse common device/function capabilities 2117 * @hw: pointer to the HW struct 2118 * @caps: pointer to common capabilities structure 2119 * @elem: the capability element to parse 2120 * @prefix: message prefix for tracing capabilities 2121 * 2122 * Given a capability element, extract relevant details into the common 2123 * capability structure. 2124 * 2125 * Returns: true if the capability matches one of the common capability ids, 2126 * false otherwise. 2127 */ 2128 static bool 2129 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 2130 struct ice_aqc_list_caps_elem *elem, const char *prefix) 2131 { 2132 u32 logical_id = le32_to_cpu(elem->logical_id); 2133 u32 phys_id = le32_to_cpu(elem->phys_id); 2134 u32 number = le32_to_cpu(elem->number); 2135 u16 cap = le16_to_cpu(elem->cap); 2136 bool found = true; 2137 2138 switch (cap) { 2139 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2140 caps->valid_functions = number; 2141 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2142 caps->valid_functions); 2143 break; 2144 case ICE_AQC_CAPS_SRIOV: 2145 caps->sr_iov_1_1 = (number == 1); 2146 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2147 caps->sr_iov_1_1); 2148 break; 2149 case ICE_AQC_CAPS_DCB: 2150 caps->dcb = (number == 1); 2151 caps->active_tc_bitmap = logical_id; 2152 caps->maxtc = phys_id; 2153 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2154 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2155 caps->active_tc_bitmap); 2156 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2157 break; 2158 case ICE_AQC_CAPS_RSS: 2159 caps->rss_table_size = number; 2160 caps->rss_table_entry_width = logical_id; 2161 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2162 caps->rss_table_size); 2163 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2164 caps->rss_table_entry_width); 2165 break; 2166 case ICE_AQC_CAPS_RXQS: 2167 caps->num_rxq = number; 2168 caps->rxq_first_id = phys_id; 2169 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2170 caps->num_rxq); 2171 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2172 caps->rxq_first_id); 2173 break; 2174 case ICE_AQC_CAPS_TXQS: 2175 caps->num_txq = number; 2176 caps->txq_first_id = phys_id; 2177 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2178 caps->num_txq); 2179 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2180 caps->txq_first_id); 2181 break; 2182 case ICE_AQC_CAPS_MSIX: 2183 caps->num_msix_vectors = number; 2184 caps->msix_vector_first_id = phys_id; 2185 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2186 caps->num_msix_vectors); 2187 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2188 caps->msix_vector_first_id); 2189 break; 2190 case ICE_AQC_CAPS_PENDING_NVM_VER: 2191 caps->nvm_update_pending_nvm = true; 2192 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2193 break; 2194 case ICE_AQC_CAPS_PENDING_OROM_VER: 2195 caps->nvm_update_pending_orom = true; 2196 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2197 break; 2198 case ICE_AQC_CAPS_PENDING_NET_VER: 2199 caps->nvm_update_pending_netlist = true; 2200 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2201 break; 2202 case ICE_AQC_CAPS_NVM_MGMT: 2203 caps->nvm_unified_update = 2204 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2205 true : false; 2206 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2207 caps->nvm_unified_update); 2208 break; 2209 case ICE_AQC_CAPS_RDMA: 2210 caps->rdma = (number == 1); 2211 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2212 break; 2213 case ICE_AQC_CAPS_MAX_MTU: 2214 caps->max_mtu = number; 2215 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2216 prefix, caps->max_mtu); 2217 break; 2218 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2219 caps->pcie_reset_avoidance = (number > 0); 2220 ice_debug(hw, ICE_DBG_INIT, 2221 "%s: pcie_reset_avoidance = %d\n", prefix, 2222 caps->pcie_reset_avoidance); 2223 break; 2224 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2225 caps->reset_restrict_support = (number == 1); 2226 ice_debug(hw, ICE_DBG_INIT, 2227 "%s: reset_restrict_support = %d\n", prefix, 2228 caps->reset_restrict_support); 2229 break; 2230 default: 2231 /* Not one of the recognized common capabilities */ 2232 found = false; 2233 } 2234 2235 return found; 2236 } 2237 2238 /** 2239 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2240 * @hw: pointer to the HW structure 2241 * @caps: pointer to capabilities structure to fix 2242 * 2243 * Re-calculate the capabilities that are dependent on the number of physical 2244 * ports; i.e. some features are not supported or function differently on 2245 * devices with more than 4 ports. 2246 */ 2247 static void 2248 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2249 { 2250 /* This assumes device capabilities are always scanned before function 2251 * capabilities during the initialization flow. 2252 */ 2253 if (hw->dev_caps.num_funcs > 4) { 2254 /* Max 4 TCs per port */ 2255 caps->maxtc = 4; 2256 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2257 caps->maxtc); 2258 if (caps->rdma) { 2259 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2260 caps->rdma = 0; 2261 } 2262 2263 /* print message only when processing device capabilities 2264 * during initialization. 2265 */ 2266 if (caps == &hw->dev_caps.common_cap) 2267 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2268 } 2269 } 2270 2271 /** 2272 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2273 * @hw: pointer to the HW struct 2274 * @func_p: pointer to function capabilities structure 2275 * @cap: pointer to the capability element to parse 2276 * 2277 * Extract function capabilities for ICE_AQC_CAPS_VF. 2278 */ 2279 static void 2280 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2281 struct ice_aqc_list_caps_elem *cap) 2282 { 2283 u32 logical_id = le32_to_cpu(cap->logical_id); 2284 u32 number = le32_to_cpu(cap->number); 2285 2286 func_p->num_allocd_vfs = number; 2287 func_p->vf_base_id = logical_id; 2288 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2289 func_p->num_allocd_vfs); 2290 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2291 func_p->vf_base_id); 2292 } 2293 2294 /** 2295 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2296 * @hw: pointer to the HW struct 2297 * @func_p: pointer to function capabilities structure 2298 * @cap: pointer to the capability element to parse 2299 * 2300 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2301 */ 2302 static void 2303 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2304 struct ice_aqc_list_caps_elem *cap) 2305 { 2306 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2307 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2308 le32_to_cpu(cap->number)); 2309 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2310 func_p->guar_num_vsi); 2311 } 2312 2313 /** 2314 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2315 * @hw: pointer to the HW struct 2316 * @func_p: pointer to function capabilities structure 2317 * @cap: pointer to the capability element to parse 2318 * 2319 * Extract function capabilities for ICE_AQC_CAPS_1588. 2320 */ 2321 static void 2322 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2323 struct ice_aqc_list_caps_elem *cap) 2324 { 2325 struct ice_ts_func_info *info = &func_p->ts_func_info; 2326 u32 number = le32_to_cpu(cap->number); 2327 2328 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2329 func_p->common_cap.ieee_1588 = info->ena; 2330 2331 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2332 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2333 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2334 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2335 2336 info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S; 2337 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2338 2339 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { 2340 info->time_ref = (enum ice_time_ref_freq)info->clk_freq; 2341 } else { 2342 /* Unknown clock frequency, so assume a (probably incorrect) 2343 * default to avoid out-of-bounds look ups of frequency 2344 * related information. 2345 */ 2346 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2347 info->clk_freq); 2348 info->time_ref = ICE_TIME_REF_FREQ_25_000; 2349 } 2350 2351 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2352 func_p->common_cap.ieee_1588); 2353 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2354 info->src_tmr_owned); 2355 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2356 info->tmr_ena); 2357 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2358 info->tmr_index_owned); 2359 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2360 info->tmr_index_assoc); 2361 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2362 info->clk_freq); 2363 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2364 info->clk_src); 2365 } 2366 2367 /** 2368 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2369 * @hw: pointer to the HW struct 2370 * @func_p: pointer to function capabilities structure 2371 * 2372 * Extract function capabilities for ICE_AQC_CAPS_FD. 2373 */ 2374 static void 2375 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2376 { 2377 u32 reg_val, val; 2378 2379 reg_val = rd32(hw, GLQF_FD_SIZE); 2380 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2381 GLQF_FD_SIZE_FD_GSIZE_S; 2382 func_p->fd_fltr_guar = 2383 ice_get_num_per_func(hw, val); 2384 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2385 GLQF_FD_SIZE_FD_BSIZE_S; 2386 func_p->fd_fltr_best_effort = val; 2387 2388 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2389 func_p->fd_fltr_guar); 2390 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2391 func_p->fd_fltr_best_effort); 2392 } 2393 2394 /** 2395 * ice_parse_func_caps - Parse function capabilities 2396 * @hw: pointer to the HW struct 2397 * @func_p: pointer to function capabilities structure 2398 * @buf: buffer containing the function capability records 2399 * @cap_count: the number of capabilities 2400 * 2401 * Helper function to parse function (0x000A) capabilities list. For 2402 * capabilities shared between device and function, this relies on 2403 * ice_parse_common_caps. 2404 * 2405 * Loop through the list of provided capabilities and extract the relevant 2406 * data into the function capabilities structured. 2407 */ 2408 static void 2409 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2410 void *buf, u32 cap_count) 2411 { 2412 struct ice_aqc_list_caps_elem *cap_resp; 2413 u32 i; 2414 2415 cap_resp = buf; 2416 2417 memset(func_p, 0, sizeof(*func_p)); 2418 2419 for (i = 0; i < cap_count; i++) { 2420 u16 cap = le16_to_cpu(cap_resp[i].cap); 2421 bool found; 2422 2423 found = ice_parse_common_caps(hw, &func_p->common_cap, 2424 &cap_resp[i], "func caps"); 2425 2426 switch (cap) { 2427 case ICE_AQC_CAPS_VF: 2428 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2429 break; 2430 case ICE_AQC_CAPS_VSI: 2431 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2432 break; 2433 case ICE_AQC_CAPS_1588: 2434 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2435 break; 2436 case ICE_AQC_CAPS_FD: 2437 ice_parse_fdir_func_caps(hw, func_p); 2438 break; 2439 default: 2440 /* Don't list common capabilities as unknown */ 2441 if (!found) 2442 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2443 i, cap); 2444 break; 2445 } 2446 } 2447 2448 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2449 } 2450 2451 /** 2452 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2453 * @hw: pointer to the HW struct 2454 * @dev_p: pointer to device capabilities structure 2455 * @cap: capability element to parse 2456 * 2457 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2458 */ 2459 static void 2460 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2461 struct ice_aqc_list_caps_elem *cap) 2462 { 2463 u32 number = le32_to_cpu(cap->number); 2464 2465 dev_p->num_funcs = hweight32(number); 2466 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2467 dev_p->num_funcs); 2468 } 2469 2470 /** 2471 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2472 * @hw: pointer to the HW struct 2473 * @dev_p: pointer to device capabilities structure 2474 * @cap: capability element to parse 2475 * 2476 * Parse ICE_AQC_CAPS_VF for device capabilities. 2477 */ 2478 static void 2479 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2480 struct ice_aqc_list_caps_elem *cap) 2481 { 2482 u32 number = le32_to_cpu(cap->number); 2483 2484 dev_p->num_vfs_exposed = number; 2485 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2486 dev_p->num_vfs_exposed); 2487 } 2488 2489 /** 2490 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2491 * @hw: pointer to the HW struct 2492 * @dev_p: pointer to device capabilities structure 2493 * @cap: capability element to parse 2494 * 2495 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2496 */ 2497 static void 2498 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2499 struct ice_aqc_list_caps_elem *cap) 2500 { 2501 u32 number = le32_to_cpu(cap->number); 2502 2503 dev_p->num_vsi_allocd_to_host = number; 2504 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2505 dev_p->num_vsi_allocd_to_host); 2506 } 2507 2508 /** 2509 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2510 * @hw: pointer to the HW struct 2511 * @dev_p: pointer to device capabilities structure 2512 * @cap: capability element to parse 2513 * 2514 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2515 */ 2516 static void 2517 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2518 struct ice_aqc_list_caps_elem *cap) 2519 { 2520 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2521 u32 logical_id = le32_to_cpu(cap->logical_id); 2522 u32 phys_id = le32_to_cpu(cap->phys_id); 2523 u32 number = le32_to_cpu(cap->number); 2524 2525 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2526 dev_p->common_cap.ieee_1588 = info->ena; 2527 2528 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2529 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2530 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2531 2532 info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S; 2533 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2534 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2535 2536 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); 2537 2538 info->ena_ports = logical_id; 2539 info->tmr_own_map = phys_id; 2540 2541 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2542 dev_p->common_cap.ieee_1588); 2543 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2544 info->tmr0_owner); 2545 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2546 info->tmr0_owned); 2547 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2548 info->tmr0_ena); 2549 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2550 info->tmr1_owner); 2551 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2552 info->tmr1_owned); 2553 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2554 info->tmr1_ena); 2555 ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n", 2556 info->ts_ll_read); 2557 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2558 info->ena_ports); 2559 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2560 info->tmr_own_map); 2561 } 2562 2563 /** 2564 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2565 * @hw: pointer to the HW struct 2566 * @dev_p: pointer to device capabilities structure 2567 * @cap: capability element to parse 2568 * 2569 * Parse ICE_AQC_CAPS_FD for device capabilities. 2570 */ 2571 static void 2572 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2573 struct ice_aqc_list_caps_elem *cap) 2574 { 2575 u32 number = le32_to_cpu(cap->number); 2576 2577 dev_p->num_flow_director_fltr = number; 2578 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2579 dev_p->num_flow_director_fltr); 2580 } 2581 2582 /** 2583 * ice_parse_dev_caps - Parse device capabilities 2584 * @hw: pointer to the HW struct 2585 * @dev_p: pointer to device capabilities structure 2586 * @buf: buffer containing the device capability records 2587 * @cap_count: the number of capabilities 2588 * 2589 * Helper device to parse device (0x000B) capabilities list. For 2590 * capabilities shared between device and function, this relies on 2591 * ice_parse_common_caps. 2592 * 2593 * Loop through the list of provided capabilities and extract the relevant 2594 * data into the device capabilities structured. 2595 */ 2596 static void 2597 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2598 void *buf, u32 cap_count) 2599 { 2600 struct ice_aqc_list_caps_elem *cap_resp; 2601 u32 i; 2602 2603 cap_resp = buf; 2604 2605 memset(dev_p, 0, sizeof(*dev_p)); 2606 2607 for (i = 0; i < cap_count; i++) { 2608 u16 cap = le16_to_cpu(cap_resp[i].cap); 2609 bool found; 2610 2611 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2612 &cap_resp[i], "dev caps"); 2613 2614 switch (cap) { 2615 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2616 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2617 break; 2618 case ICE_AQC_CAPS_VF: 2619 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2620 break; 2621 case ICE_AQC_CAPS_VSI: 2622 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2623 break; 2624 case ICE_AQC_CAPS_1588: 2625 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2626 break; 2627 case ICE_AQC_CAPS_FD: 2628 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2629 break; 2630 default: 2631 /* Don't list common capabilities as unknown */ 2632 if (!found) 2633 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2634 i, cap); 2635 break; 2636 } 2637 } 2638 2639 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2640 } 2641 2642 /** 2643 * ice_aq_list_caps - query function/device capabilities 2644 * @hw: pointer to the HW struct 2645 * @buf: a buffer to hold the capabilities 2646 * @buf_size: size of the buffer 2647 * @cap_count: if not NULL, set to the number of capabilities reported 2648 * @opc: capabilities type to discover, device or function 2649 * @cd: pointer to command details structure or NULL 2650 * 2651 * Get the function (0x000A) or device (0x000B) capabilities description from 2652 * firmware and store it in the buffer. 2653 * 2654 * If the cap_count pointer is not NULL, then it is set to the number of 2655 * capabilities firmware will report. Note that if the buffer size is too 2656 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2657 * cap_count will still be updated in this case. It is recommended that the 2658 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2659 * firmware could return) to avoid this. 2660 */ 2661 int 2662 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2663 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2664 { 2665 struct ice_aqc_list_caps *cmd; 2666 struct ice_aq_desc desc; 2667 int status; 2668 2669 cmd = &desc.params.get_cap; 2670 2671 if (opc != ice_aqc_opc_list_func_caps && 2672 opc != ice_aqc_opc_list_dev_caps) 2673 return -EINVAL; 2674 2675 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2676 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2677 2678 if (cap_count) 2679 *cap_count = le32_to_cpu(cmd->count); 2680 2681 return status; 2682 } 2683 2684 /** 2685 * ice_discover_dev_caps - Read and extract device capabilities 2686 * @hw: pointer to the hardware structure 2687 * @dev_caps: pointer to device capabilities structure 2688 * 2689 * Read the device capabilities and extract them into the dev_caps structure 2690 * for later use. 2691 */ 2692 int 2693 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2694 { 2695 u32 cap_count = 0; 2696 void *cbuf; 2697 int status; 2698 2699 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2700 if (!cbuf) 2701 return -ENOMEM; 2702 2703 /* Although the driver doesn't know the number of capabilities the 2704 * device will return, we can simply send a 4KB buffer, the maximum 2705 * possible size that firmware can return. 2706 */ 2707 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2708 2709 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2710 ice_aqc_opc_list_dev_caps, NULL); 2711 if (!status) 2712 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2713 kfree(cbuf); 2714 2715 return status; 2716 } 2717 2718 /** 2719 * ice_discover_func_caps - Read and extract function capabilities 2720 * @hw: pointer to the hardware structure 2721 * @func_caps: pointer to function capabilities structure 2722 * 2723 * Read the function capabilities and extract them into the func_caps structure 2724 * for later use. 2725 */ 2726 static int 2727 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2728 { 2729 u32 cap_count = 0; 2730 void *cbuf; 2731 int status; 2732 2733 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2734 if (!cbuf) 2735 return -ENOMEM; 2736 2737 /* Although the driver doesn't know the number of capabilities the 2738 * device will return, we can simply send a 4KB buffer, the maximum 2739 * possible size that firmware can return. 2740 */ 2741 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2742 2743 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2744 ice_aqc_opc_list_func_caps, NULL); 2745 if (!status) 2746 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2747 kfree(cbuf); 2748 2749 return status; 2750 } 2751 2752 /** 2753 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2754 * @hw: pointer to the hardware structure 2755 */ 2756 void ice_set_safe_mode_caps(struct ice_hw *hw) 2757 { 2758 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2759 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2760 struct ice_hw_common_caps cached_caps; 2761 u32 num_funcs; 2762 2763 /* cache some func_caps values that should be restored after memset */ 2764 cached_caps = func_caps->common_cap; 2765 2766 /* unset func capabilities */ 2767 memset(func_caps, 0, sizeof(*func_caps)); 2768 2769 #define ICE_RESTORE_FUNC_CAP(name) \ 2770 func_caps->common_cap.name = cached_caps.name 2771 2772 /* restore cached values */ 2773 ICE_RESTORE_FUNC_CAP(valid_functions); 2774 ICE_RESTORE_FUNC_CAP(txq_first_id); 2775 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2776 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2777 ICE_RESTORE_FUNC_CAP(max_mtu); 2778 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2779 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2780 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2781 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2782 2783 /* one Tx and one Rx queue in safe mode */ 2784 func_caps->common_cap.num_rxq = 1; 2785 func_caps->common_cap.num_txq = 1; 2786 2787 /* two MSIX vectors, one for traffic and one for misc causes */ 2788 func_caps->common_cap.num_msix_vectors = 2; 2789 func_caps->guar_num_vsi = 1; 2790 2791 /* cache some dev_caps values that should be restored after memset */ 2792 cached_caps = dev_caps->common_cap; 2793 num_funcs = dev_caps->num_funcs; 2794 2795 /* unset dev capabilities */ 2796 memset(dev_caps, 0, sizeof(*dev_caps)); 2797 2798 #define ICE_RESTORE_DEV_CAP(name) \ 2799 dev_caps->common_cap.name = cached_caps.name 2800 2801 /* restore cached values */ 2802 ICE_RESTORE_DEV_CAP(valid_functions); 2803 ICE_RESTORE_DEV_CAP(txq_first_id); 2804 ICE_RESTORE_DEV_CAP(rxq_first_id); 2805 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2806 ICE_RESTORE_DEV_CAP(max_mtu); 2807 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2808 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 2809 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 2810 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 2811 dev_caps->num_funcs = num_funcs; 2812 2813 /* one Tx and one Rx queue per function in safe mode */ 2814 dev_caps->common_cap.num_rxq = num_funcs; 2815 dev_caps->common_cap.num_txq = num_funcs; 2816 2817 /* two MSIX vectors per function */ 2818 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2819 } 2820 2821 /** 2822 * ice_get_caps - get info about the HW 2823 * @hw: pointer to the hardware structure 2824 */ 2825 int ice_get_caps(struct ice_hw *hw) 2826 { 2827 int status; 2828 2829 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2830 if (status) 2831 return status; 2832 2833 return ice_discover_func_caps(hw, &hw->func_caps); 2834 } 2835 2836 /** 2837 * ice_aq_manage_mac_write - manage MAC address write command 2838 * @hw: pointer to the HW struct 2839 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2840 * @flags: flags to control write behavior 2841 * @cd: pointer to command details structure or NULL 2842 * 2843 * This function is used to write MAC address to the NVM (0x0108). 2844 */ 2845 int 2846 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2847 struct ice_sq_cd *cd) 2848 { 2849 struct ice_aqc_manage_mac_write *cmd; 2850 struct ice_aq_desc desc; 2851 2852 cmd = &desc.params.mac_write; 2853 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2854 2855 cmd->flags = flags; 2856 ether_addr_copy(cmd->mac_addr, mac_addr); 2857 2858 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2859 } 2860 2861 /** 2862 * ice_aq_clear_pxe_mode 2863 * @hw: pointer to the HW struct 2864 * 2865 * Tell the firmware that the driver is taking over from PXE (0x0110). 2866 */ 2867 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 2868 { 2869 struct ice_aq_desc desc; 2870 2871 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2872 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2873 2874 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2875 } 2876 2877 /** 2878 * ice_clear_pxe_mode - clear pxe operations mode 2879 * @hw: pointer to the HW struct 2880 * 2881 * Make sure all PXE mode settings are cleared, including things 2882 * like descriptor fetch/write-back mode. 2883 */ 2884 void ice_clear_pxe_mode(struct ice_hw *hw) 2885 { 2886 if (ice_check_sq_alive(hw, &hw->adminq)) 2887 ice_aq_clear_pxe_mode(hw); 2888 } 2889 2890 /** 2891 * ice_aq_set_port_params - set physical port parameters. 2892 * @pi: pointer to the port info struct 2893 * @double_vlan: if set double VLAN is enabled 2894 * @cd: pointer to command details structure or NULL 2895 * 2896 * Set Physical port parameters (0x0203) 2897 */ 2898 int 2899 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 2900 struct ice_sq_cd *cd) 2901 2902 { 2903 struct ice_aqc_set_port_params *cmd; 2904 struct ice_hw *hw = pi->hw; 2905 struct ice_aq_desc desc; 2906 u16 cmd_flags = 0; 2907 2908 cmd = &desc.params.set_port_params; 2909 2910 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 2911 if (double_vlan) 2912 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 2913 cmd->cmd_flags = cpu_to_le16(cmd_flags); 2914 2915 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2916 } 2917 2918 /** 2919 * ice_is_100m_speed_supported 2920 * @hw: pointer to the HW struct 2921 * 2922 * returns true if 100M speeds are supported by the device, 2923 * false otherwise. 2924 */ 2925 bool ice_is_100m_speed_supported(struct ice_hw *hw) 2926 { 2927 switch (hw->device_id) { 2928 case ICE_DEV_ID_E822C_SGMII: 2929 case ICE_DEV_ID_E822L_SGMII: 2930 case ICE_DEV_ID_E823L_1GBE: 2931 case ICE_DEV_ID_E823C_SGMII: 2932 return true; 2933 default: 2934 return false; 2935 } 2936 } 2937 2938 /** 2939 * ice_get_link_speed_based_on_phy_type - returns link speed 2940 * @phy_type_low: lower part of phy_type 2941 * @phy_type_high: higher part of phy_type 2942 * 2943 * This helper function will convert an entry in PHY type structure 2944 * [phy_type_low, phy_type_high] to its corresponding link speed. 2945 * Note: In the structure of [phy_type_low, phy_type_high], there should 2946 * be one bit set, as this function will convert one PHY type to its 2947 * speed. 2948 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2949 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2950 */ 2951 static u16 2952 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2953 { 2954 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2955 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2956 2957 switch (phy_type_low) { 2958 case ICE_PHY_TYPE_LOW_100BASE_TX: 2959 case ICE_PHY_TYPE_LOW_100M_SGMII: 2960 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2961 break; 2962 case ICE_PHY_TYPE_LOW_1000BASE_T: 2963 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2964 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2965 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2966 case ICE_PHY_TYPE_LOW_1G_SGMII: 2967 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2968 break; 2969 case ICE_PHY_TYPE_LOW_2500BASE_T: 2970 case ICE_PHY_TYPE_LOW_2500BASE_X: 2971 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2972 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2973 break; 2974 case ICE_PHY_TYPE_LOW_5GBASE_T: 2975 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2976 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2977 break; 2978 case ICE_PHY_TYPE_LOW_10GBASE_T: 2979 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2980 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2981 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2982 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2983 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2984 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2985 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2986 break; 2987 case ICE_PHY_TYPE_LOW_25GBASE_T: 2988 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2989 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2990 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2991 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2992 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2993 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2994 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2995 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2996 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2997 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2998 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2999 break; 3000 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 3001 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 3002 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 3003 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 3004 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3005 case ICE_PHY_TYPE_LOW_40G_XLAUI: 3006 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 3007 break; 3008 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 3009 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 3010 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 3011 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 3012 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3013 case ICE_PHY_TYPE_LOW_50G_LAUI2: 3014 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3015 case ICE_PHY_TYPE_LOW_50G_AUI2: 3016 case ICE_PHY_TYPE_LOW_50GBASE_CP: 3017 case ICE_PHY_TYPE_LOW_50GBASE_SR: 3018 case ICE_PHY_TYPE_LOW_50GBASE_FR: 3019 case ICE_PHY_TYPE_LOW_50GBASE_LR: 3020 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 3021 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3022 case ICE_PHY_TYPE_LOW_50G_AUI1: 3023 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 3024 break; 3025 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 3026 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 3027 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 3028 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 3029 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3030 case ICE_PHY_TYPE_LOW_100G_CAUI4: 3031 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3032 case ICE_PHY_TYPE_LOW_100G_AUI4: 3033 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 3034 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 3035 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 3036 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 3037 case ICE_PHY_TYPE_LOW_100GBASE_DR: 3038 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 3039 break; 3040 default: 3041 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 3042 break; 3043 } 3044 3045 switch (phy_type_high) { 3046 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 3047 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 3048 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3049 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 3050 case ICE_PHY_TYPE_HIGH_100G_AUI2: 3051 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 3052 break; 3053 default: 3054 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 3055 break; 3056 } 3057 3058 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 3059 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3060 return ICE_AQ_LINK_SPEED_UNKNOWN; 3061 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3062 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 3063 return ICE_AQ_LINK_SPEED_UNKNOWN; 3064 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 3065 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 3066 return speed_phy_type_low; 3067 else 3068 return speed_phy_type_high; 3069 } 3070 3071 /** 3072 * ice_update_phy_type 3073 * @phy_type_low: pointer to the lower part of phy_type 3074 * @phy_type_high: pointer to the higher part of phy_type 3075 * @link_speeds_bitmap: targeted link speeds bitmap 3076 * 3077 * Note: For the link_speeds_bitmap structure, you can check it at 3078 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 3079 * link_speeds_bitmap include multiple speeds. 3080 * 3081 * Each entry in this [phy_type_low, phy_type_high] structure will 3082 * present a certain link speed. This helper function will turn on bits 3083 * in [phy_type_low, phy_type_high] structure based on the value of 3084 * link_speeds_bitmap input parameter. 3085 */ 3086 void 3087 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 3088 u16 link_speeds_bitmap) 3089 { 3090 u64 pt_high; 3091 u64 pt_low; 3092 int index; 3093 u16 speed; 3094 3095 /* We first check with low part of phy_type */ 3096 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 3097 pt_low = BIT_ULL(index); 3098 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 3099 3100 if (link_speeds_bitmap & speed) 3101 *phy_type_low |= BIT_ULL(index); 3102 } 3103 3104 /* We then check with high part of phy_type */ 3105 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 3106 pt_high = BIT_ULL(index); 3107 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 3108 3109 if (link_speeds_bitmap & speed) 3110 *phy_type_high |= BIT_ULL(index); 3111 } 3112 } 3113 3114 /** 3115 * ice_aq_set_phy_cfg 3116 * @hw: pointer to the HW struct 3117 * @pi: port info structure of the interested logical port 3118 * @cfg: structure with PHY configuration data to be set 3119 * @cd: pointer to command details structure or NULL 3120 * 3121 * Set the various PHY configuration parameters supported on the Port. 3122 * One or more of the Set PHY config parameters may be ignored in an MFP 3123 * mode as the PF may not have the privilege to set some of the PHY Config 3124 * parameters. This status will be indicated by the command response (0x0601). 3125 */ 3126 int 3127 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 3128 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 3129 { 3130 struct ice_aq_desc desc; 3131 int status; 3132 3133 if (!cfg) 3134 return -EINVAL; 3135 3136 /* Ensure that only valid bits of cfg->caps can be turned on. */ 3137 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 3138 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 3139 cfg->caps); 3140 3141 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3142 } 3143 3144 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3145 desc.params.set_phy.lport_num = pi->lport; 3146 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3147 3148 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3149 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3150 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3151 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3152 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3153 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3154 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3155 cfg->low_power_ctrl_an); 3156 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3157 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3158 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3159 cfg->link_fec_opt); 3160 3161 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3162 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3163 status = 0; 3164 3165 if (!status) 3166 pi->phy.curr_user_phy_cfg = *cfg; 3167 3168 return status; 3169 } 3170 3171 /** 3172 * ice_update_link_info - update status of the HW network link 3173 * @pi: port info structure of the interested logical port 3174 */ 3175 int ice_update_link_info(struct ice_port_info *pi) 3176 { 3177 struct ice_link_status *li; 3178 int status; 3179 3180 if (!pi) 3181 return -EINVAL; 3182 3183 li = &pi->phy.link_info; 3184 3185 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3186 if (status) 3187 return status; 3188 3189 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3190 struct ice_aqc_get_phy_caps_data *pcaps; 3191 struct ice_hw *hw; 3192 3193 hw = pi->hw; 3194 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 3195 GFP_KERNEL); 3196 if (!pcaps) 3197 return -ENOMEM; 3198 3199 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3200 pcaps, NULL); 3201 3202 devm_kfree(ice_hw_to_dev(hw), pcaps); 3203 } 3204 3205 return status; 3206 } 3207 3208 /** 3209 * ice_cache_phy_user_req 3210 * @pi: port information structure 3211 * @cache_data: PHY logging data 3212 * @cache_mode: PHY logging mode 3213 * 3214 * Log the user request on (FC, FEC, SPEED) for later use. 3215 */ 3216 static void 3217 ice_cache_phy_user_req(struct ice_port_info *pi, 3218 struct ice_phy_cache_mode_data cache_data, 3219 enum ice_phy_cache_mode cache_mode) 3220 { 3221 if (!pi) 3222 return; 3223 3224 switch (cache_mode) { 3225 case ICE_FC_MODE: 3226 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3227 break; 3228 case ICE_SPEED_MODE: 3229 pi->phy.curr_user_speed_req = 3230 cache_data.data.curr_user_speed_req; 3231 break; 3232 case ICE_FEC_MODE: 3233 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3234 break; 3235 default: 3236 break; 3237 } 3238 } 3239 3240 /** 3241 * ice_caps_to_fc_mode 3242 * @caps: PHY capabilities 3243 * 3244 * Convert PHY FC capabilities to ice FC mode 3245 */ 3246 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3247 { 3248 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3249 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3250 return ICE_FC_FULL; 3251 3252 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3253 return ICE_FC_TX_PAUSE; 3254 3255 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3256 return ICE_FC_RX_PAUSE; 3257 3258 return ICE_FC_NONE; 3259 } 3260 3261 /** 3262 * ice_caps_to_fec_mode 3263 * @caps: PHY capabilities 3264 * @fec_options: Link FEC options 3265 * 3266 * Convert PHY FEC capabilities to ice FEC mode 3267 */ 3268 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3269 { 3270 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3271 return ICE_FEC_AUTO; 3272 3273 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3274 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3275 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3276 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3277 return ICE_FEC_BASER; 3278 3279 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3280 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3281 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3282 return ICE_FEC_RS; 3283 3284 return ICE_FEC_NONE; 3285 } 3286 3287 /** 3288 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3289 * @pi: port information structure 3290 * @cfg: PHY configuration data to set FC mode 3291 * @req_mode: FC mode to configure 3292 */ 3293 int 3294 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3295 enum ice_fc_mode req_mode) 3296 { 3297 struct ice_phy_cache_mode_data cache_data; 3298 u8 pause_mask = 0x0; 3299 3300 if (!pi || !cfg) 3301 return -EINVAL; 3302 3303 switch (req_mode) { 3304 case ICE_FC_FULL: 3305 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3306 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3307 break; 3308 case ICE_FC_RX_PAUSE: 3309 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3310 break; 3311 case ICE_FC_TX_PAUSE: 3312 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3313 break; 3314 default: 3315 break; 3316 } 3317 3318 /* clear the old pause settings */ 3319 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3320 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3321 3322 /* set the new capabilities */ 3323 cfg->caps |= pause_mask; 3324 3325 /* Cache user FC request */ 3326 cache_data.data.curr_user_fc_req = req_mode; 3327 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3328 3329 return 0; 3330 } 3331 3332 /** 3333 * ice_set_fc 3334 * @pi: port information structure 3335 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3336 * @ena_auto_link_update: enable automatic link update 3337 * 3338 * Set the requested flow control mode. 3339 */ 3340 int 3341 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3342 { 3343 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3344 struct ice_aqc_get_phy_caps_data *pcaps; 3345 struct ice_hw *hw; 3346 int status; 3347 3348 if (!pi || !aq_failures) 3349 return -EINVAL; 3350 3351 *aq_failures = 0; 3352 hw = pi->hw; 3353 3354 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 3355 if (!pcaps) 3356 return -ENOMEM; 3357 3358 /* Get the current PHY config */ 3359 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3360 pcaps, NULL); 3361 if (status) { 3362 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3363 goto out; 3364 } 3365 3366 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3367 3368 /* Configure the set PHY data */ 3369 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3370 if (status) 3371 goto out; 3372 3373 /* If the capabilities have changed, then set the new config */ 3374 if (cfg.caps != pcaps->caps) { 3375 int retry_count, retry_max = 10; 3376 3377 /* Auto restart link so settings take effect */ 3378 if (ena_auto_link_update) 3379 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3380 3381 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3382 if (status) { 3383 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3384 goto out; 3385 } 3386 3387 /* Update the link info 3388 * It sometimes takes a really long time for link to 3389 * come back from the atomic reset. Thus, we wait a 3390 * little bit. 3391 */ 3392 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3393 status = ice_update_link_info(pi); 3394 3395 if (!status) 3396 break; 3397 3398 mdelay(100); 3399 } 3400 3401 if (status) 3402 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3403 } 3404 3405 out: 3406 devm_kfree(ice_hw_to_dev(hw), pcaps); 3407 return status; 3408 } 3409 3410 /** 3411 * ice_phy_caps_equals_cfg 3412 * @phy_caps: PHY capabilities 3413 * @phy_cfg: PHY configuration 3414 * 3415 * Helper function to determine if PHY capabilities matches PHY 3416 * configuration 3417 */ 3418 bool 3419 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3420 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3421 { 3422 u8 caps_mask, cfg_mask; 3423 3424 if (!phy_caps || !phy_cfg) 3425 return false; 3426 3427 /* These bits are not common between capabilities and configuration. 3428 * Do not use them to determine equality. 3429 */ 3430 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3431 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3432 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3433 3434 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3435 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3436 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3437 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3438 phy_caps->eee_cap != phy_cfg->eee_cap || 3439 phy_caps->eeer_value != phy_cfg->eeer_value || 3440 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3441 return false; 3442 3443 return true; 3444 } 3445 3446 /** 3447 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3448 * @pi: port information structure 3449 * @caps: PHY ability structure to copy date from 3450 * @cfg: PHY configuration structure to copy data to 3451 * 3452 * Helper function to copy AQC PHY get ability data to PHY set configuration 3453 * data structure 3454 */ 3455 void 3456 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3457 struct ice_aqc_get_phy_caps_data *caps, 3458 struct ice_aqc_set_phy_cfg_data *cfg) 3459 { 3460 if (!pi || !caps || !cfg) 3461 return; 3462 3463 memset(cfg, 0, sizeof(*cfg)); 3464 cfg->phy_type_low = caps->phy_type_low; 3465 cfg->phy_type_high = caps->phy_type_high; 3466 cfg->caps = caps->caps; 3467 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3468 cfg->eee_cap = caps->eee_cap; 3469 cfg->eeer_value = caps->eeer_value; 3470 cfg->link_fec_opt = caps->link_fec_options; 3471 cfg->module_compliance_enforcement = 3472 caps->module_compliance_enforcement; 3473 } 3474 3475 /** 3476 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3477 * @pi: port information structure 3478 * @cfg: PHY configuration data to set FEC mode 3479 * @fec: FEC mode to configure 3480 */ 3481 int 3482 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3483 enum ice_fec_mode fec) 3484 { 3485 struct ice_aqc_get_phy_caps_data *pcaps; 3486 struct ice_hw *hw; 3487 int status; 3488 3489 if (!pi || !cfg) 3490 return -EINVAL; 3491 3492 hw = pi->hw; 3493 3494 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3495 if (!pcaps) 3496 return -ENOMEM; 3497 3498 status = ice_aq_get_phy_caps(pi, false, 3499 (ice_fw_supports_report_dflt_cfg(hw) ? 3500 ICE_AQC_REPORT_DFLT_CFG : 3501 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3502 if (status) 3503 goto out; 3504 3505 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3506 cfg->link_fec_opt = pcaps->link_fec_options; 3507 3508 switch (fec) { 3509 case ICE_FEC_BASER: 3510 /* Clear RS bits, and AND BASE-R ability 3511 * bits and OR request bits. 3512 */ 3513 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3514 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3515 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3516 ICE_AQC_PHY_FEC_25G_KR_REQ; 3517 break; 3518 case ICE_FEC_RS: 3519 /* Clear BASE-R bits, and AND RS ability 3520 * bits and OR request bits. 3521 */ 3522 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3523 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3524 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3525 break; 3526 case ICE_FEC_NONE: 3527 /* Clear all FEC option bits. */ 3528 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3529 break; 3530 case ICE_FEC_AUTO: 3531 /* AND auto FEC bit, and all caps bits. */ 3532 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3533 cfg->link_fec_opt |= pcaps->link_fec_options; 3534 break; 3535 default: 3536 status = -EINVAL; 3537 break; 3538 } 3539 3540 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 3541 !ice_fw_supports_report_dflt_cfg(hw)) { 3542 struct ice_link_default_override_tlv tlv = { 0 }; 3543 3544 status = ice_get_link_default_override(&tlv, pi); 3545 if (status) 3546 goto out; 3547 3548 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3549 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3550 cfg->link_fec_opt = tlv.fec_options; 3551 } 3552 3553 out: 3554 kfree(pcaps); 3555 3556 return status; 3557 } 3558 3559 /** 3560 * ice_get_link_status - get status of the HW network link 3561 * @pi: port information structure 3562 * @link_up: pointer to bool (true/false = linkup/linkdown) 3563 * 3564 * Variable link_up is true if link is up, false if link is down. 3565 * The variable link_up is invalid if status is non zero. As a 3566 * result of this call, link status reporting becomes enabled 3567 */ 3568 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3569 { 3570 struct ice_phy_info *phy_info; 3571 int status = 0; 3572 3573 if (!pi || !link_up) 3574 return -EINVAL; 3575 3576 phy_info = &pi->phy; 3577 3578 if (phy_info->get_link_info) { 3579 status = ice_update_link_info(pi); 3580 3581 if (status) 3582 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3583 status); 3584 } 3585 3586 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3587 3588 return status; 3589 } 3590 3591 /** 3592 * ice_aq_set_link_restart_an 3593 * @pi: pointer to the port information structure 3594 * @ena_link: if true: enable link, if false: disable link 3595 * @cd: pointer to command details structure or NULL 3596 * 3597 * Sets up the link and restarts the Auto-Negotiation over the link. 3598 */ 3599 int 3600 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3601 struct ice_sq_cd *cd) 3602 { 3603 struct ice_aqc_restart_an *cmd; 3604 struct ice_aq_desc desc; 3605 3606 cmd = &desc.params.restart_an; 3607 3608 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3609 3610 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3611 cmd->lport_num = pi->lport; 3612 if (ena_link) 3613 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3614 else 3615 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3616 3617 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3618 } 3619 3620 /** 3621 * ice_aq_set_event_mask 3622 * @hw: pointer to the HW struct 3623 * @port_num: port number of the physical function 3624 * @mask: event mask to be set 3625 * @cd: pointer to command details structure or NULL 3626 * 3627 * Set event mask (0x0613) 3628 */ 3629 int 3630 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3631 struct ice_sq_cd *cd) 3632 { 3633 struct ice_aqc_set_event_mask *cmd; 3634 struct ice_aq_desc desc; 3635 3636 cmd = &desc.params.set_event_mask; 3637 3638 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3639 3640 cmd->lport_num = port_num; 3641 3642 cmd->event_mask = cpu_to_le16(mask); 3643 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3644 } 3645 3646 /** 3647 * ice_aq_set_mac_loopback 3648 * @hw: pointer to the HW struct 3649 * @ena_lpbk: Enable or Disable loopback 3650 * @cd: pointer to command details structure or NULL 3651 * 3652 * Enable/disable loopback on a given port 3653 */ 3654 int 3655 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3656 { 3657 struct ice_aqc_set_mac_lb *cmd; 3658 struct ice_aq_desc desc; 3659 3660 cmd = &desc.params.set_mac_lb; 3661 3662 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3663 if (ena_lpbk) 3664 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3665 3666 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3667 } 3668 3669 /** 3670 * ice_aq_set_port_id_led 3671 * @pi: pointer to the port information 3672 * @is_orig_mode: is this LED set to original mode (by the net-list) 3673 * @cd: pointer to command details structure or NULL 3674 * 3675 * Set LED value for the given port (0x06e9) 3676 */ 3677 int 3678 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3679 struct ice_sq_cd *cd) 3680 { 3681 struct ice_aqc_set_port_id_led *cmd; 3682 struct ice_hw *hw = pi->hw; 3683 struct ice_aq_desc desc; 3684 3685 cmd = &desc.params.set_port_id_led; 3686 3687 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3688 3689 if (is_orig_mode) 3690 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3691 else 3692 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3693 3694 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3695 } 3696 3697 /** 3698 * ice_aq_get_port_options 3699 * @hw: pointer to the HW struct 3700 * @options: buffer for the resultant port options 3701 * @option_count: input - size of the buffer in port options structures, 3702 * output - number of returned port options 3703 * @lport: logical port to call the command with (optional) 3704 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3705 * when PF owns more than 1 port it must be true 3706 * @active_option_idx: index of active port option in returned buffer 3707 * @active_option_valid: active option in returned buffer is valid 3708 * @pending_option_idx: index of pending port option in returned buffer 3709 * @pending_option_valid: pending option in returned buffer is valid 3710 * 3711 * Calls Get Port Options AQC (0x06ea) and verifies result. 3712 */ 3713 int 3714 ice_aq_get_port_options(struct ice_hw *hw, 3715 struct ice_aqc_get_port_options_elem *options, 3716 u8 *option_count, u8 lport, bool lport_valid, 3717 u8 *active_option_idx, bool *active_option_valid, 3718 u8 *pending_option_idx, bool *pending_option_valid) 3719 { 3720 struct ice_aqc_get_port_options *cmd; 3721 struct ice_aq_desc desc; 3722 int status; 3723 u8 i; 3724 3725 /* options buffer shall be able to hold max returned options */ 3726 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 3727 return -EINVAL; 3728 3729 cmd = &desc.params.get_port_options; 3730 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 3731 3732 if (lport_valid) 3733 cmd->lport_num = lport; 3734 cmd->lport_num_valid = lport_valid; 3735 3736 status = ice_aq_send_cmd(hw, &desc, options, 3737 *option_count * sizeof(*options), NULL); 3738 if (status) 3739 return status; 3740 3741 /* verify direct FW response & set output parameters */ 3742 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 3743 cmd->port_options_count); 3744 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 3745 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 3746 cmd->port_options); 3747 if (*active_option_valid) { 3748 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 3749 cmd->port_options); 3750 if (*active_option_idx > (*option_count - 1)) 3751 return -EIO; 3752 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 3753 *active_option_idx); 3754 } 3755 3756 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 3757 cmd->pending_port_option_status); 3758 if (*pending_option_valid) { 3759 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 3760 cmd->pending_port_option_status); 3761 if (*pending_option_idx > (*option_count - 1)) 3762 return -EIO; 3763 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 3764 *pending_option_idx); 3765 } 3766 3767 /* mask output options fields */ 3768 for (i = 0; i < *option_count; i++) { 3769 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 3770 options[i].pmd); 3771 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 3772 options[i].max_lane_speed); 3773 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 3774 options[i].pmd, options[i].max_lane_speed); 3775 } 3776 3777 return 0; 3778 } 3779 3780 /** 3781 * ice_aq_set_port_option 3782 * @hw: pointer to the HW struct 3783 * @lport: logical port to call the command with 3784 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3785 * when PF owns more than 1 port it must be true 3786 * @new_option: new port option to be written 3787 * 3788 * Calls Set Port Options AQC (0x06eb). 3789 */ 3790 int 3791 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 3792 u8 new_option) 3793 { 3794 struct ice_aqc_set_port_option *cmd; 3795 struct ice_aq_desc desc; 3796 3797 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 3798 return -EINVAL; 3799 3800 cmd = &desc.params.set_port_option; 3801 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 3802 3803 if (lport_valid) 3804 cmd->lport_num = lport; 3805 3806 cmd->lport_num_valid = lport_valid; 3807 cmd->selected_port_option = new_option; 3808 3809 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3810 } 3811 3812 /** 3813 * ice_aq_sff_eeprom 3814 * @hw: pointer to the HW struct 3815 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3816 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3817 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3818 * @page: QSFP page 3819 * @set_page: set or ignore the page 3820 * @data: pointer to data buffer to be read/written to the I2C device. 3821 * @length: 1-16 for read, 1 for write. 3822 * @write: 0 read, 1 for write. 3823 * @cd: pointer to command details structure or NULL 3824 * 3825 * Read/Write SFF EEPROM (0x06EE) 3826 */ 3827 int 3828 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3829 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3830 bool write, struct ice_sq_cd *cd) 3831 { 3832 struct ice_aqc_sff_eeprom *cmd; 3833 struct ice_aq_desc desc; 3834 int status; 3835 3836 if (!data || (mem_addr & 0xff00)) 3837 return -EINVAL; 3838 3839 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3840 cmd = &desc.params.read_write_sff_param; 3841 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 3842 cmd->lport_num = (u8)(lport & 0xff); 3843 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3844 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 3845 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3846 ((set_page << 3847 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3848 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3849 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3850 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3851 if (write) 3852 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 3853 3854 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3855 return status; 3856 } 3857 3858 /** 3859 * __ice_aq_get_set_rss_lut 3860 * @hw: pointer to the hardware structure 3861 * @params: RSS LUT parameters 3862 * @set: set true to set the table, false to get the table 3863 * 3864 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3865 */ 3866 static int 3867 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 3868 { 3869 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 3870 struct ice_aqc_get_set_rss_lut *cmd_resp; 3871 struct ice_aq_desc desc; 3872 int status; 3873 u8 *lut; 3874 3875 if (!params) 3876 return -EINVAL; 3877 3878 vsi_handle = params->vsi_handle; 3879 lut = params->lut; 3880 3881 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3882 return -EINVAL; 3883 3884 lut_size = params->lut_size; 3885 lut_type = params->lut_type; 3886 glob_lut_idx = params->global_lut_id; 3887 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 3888 3889 cmd_resp = &desc.params.get_set_rss_lut; 3890 3891 if (set) { 3892 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3893 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3894 } else { 3895 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3896 } 3897 3898 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3899 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3900 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3901 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3902 3903 switch (lut_type) { 3904 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3905 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3906 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3907 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3908 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3909 break; 3910 default: 3911 status = -EINVAL; 3912 goto ice_aq_get_set_rss_lut_exit; 3913 } 3914 3915 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3916 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3917 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3918 3919 if (!set) 3920 goto ice_aq_get_set_rss_lut_send; 3921 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3922 if (!set) 3923 goto ice_aq_get_set_rss_lut_send; 3924 } else { 3925 goto ice_aq_get_set_rss_lut_send; 3926 } 3927 3928 /* LUT size is only valid for Global and PF table types */ 3929 switch (lut_size) { 3930 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3931 break; 3932 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3933 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3934 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3935 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3936 break; 3937 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3938 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3939 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3940 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3941 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3942 break; 3943 } 3944 fallthrough; 3945 default: 3946 status = -EINVAL; 3947 goto ice_aq_get_set_rss_lut_exit; 3948 } 3949 3950 ice_aq_get_set_rss_lut_send: 3951 cmd_resp->flags = cpu_to_le16(flags); 3952 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3953 3954 ice_aq_get_set_rss_lut_exit: 3955 return status; 3956 } 3957 3958 /** 3959 * ice_aq_get_rss_lut 3960 * @hw: pointer to the hardware structure 3961 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 3962 * 3963 * get the RSS lookup table, PF or VSI type 3964 */ 3965 int 3966 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 3967 { 3968 return __ice_aq_get_set_rss_lut(hw, get_params, false); 3969 } 3970 3971 /** 3972 * ice_aq_set_rss_lut 3973 * @hw: pointer to the hardware structure 3974 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 3975 * 3976 * set the RSS lookup table, PF or VSI type 3977 */ 3978 int 3979 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 3980 { 3981 return __ice_aq_get_set_rss_lut(hw, set_params, true); 3982 } 3983 3984 /** 3985 * __ice_aq_get_set_rss_key 3986 * @hw: pointer to the HW struct 3987 * @vsi_id: VSI FW index 3988 * @key: pointer to key info struct 3989 * @set: set true to set the key, false to get the key 3990 * 3991 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3992 */ 3993 static int 3994 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3995 struct ice_aqc_get_set_rss_keys *key, bool set) 3996 { 3997 struct ice_aqc_get_set_rss_key *cmd_resp; 3998 u16 key_size = sizeof(*key); 3999 struct ice_aq_desc desc; 4000 4001 cmd_resp = &desc.params.get_set_rss_key; 4002 4003 if (set) { 4004 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 4005 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4006 } else { 4007 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 4008 } 4009 4010 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 4011 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 4012 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 4013 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 4014 4015 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 4016 } 4017 4018 /** 4019 * ice_aq_get_rss_key 4020 * @hw: pointer to the HW struct 4021 * @vsi_handle: software VSI handle 4022 * @key: pointer to key info struct 4023 * 4024 * get the RSS key per VSI 4025 */ 4026 int 4027 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 4028 struct ice_aqc_get_set_rss_keys *key) 4029 { 4030 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 4031 return -EINVAL; 4032 4033 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4034 key, false); 4035 } 4036 4037 /** 4038 * ice_aq_set_rss_key 4039 * @hw: pointer to the HW struct 4040 * @vsi_handle: software VSI handle 4041 * @keys: pointer to key info struct 4042 * 4043 * set the RSS key per VSI 4044 */ 4045 int 4046 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 4047 struct ice_aqc_get_set_rss_keys *keys) 4048 { 4049 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 4050 return -EINVAL; 4051 4052 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 4053 keys, true); 4054 } 4055 4056 /** 4057 * ice_aq_add_lan_txq 4058 * @hw: pointer to the hardware structure 4059 * @num_qgrps: Number of added queue groups 4060 * @qg_list: list of queue groups to be added 4061 * @buf_size: size of buffer for indirect command 4062 * @cd: pointer to command details structure or NULL 4063 * 4064 * Add Tx LAN queue (0x0C30) 4065 * 4066 * NOTE: 4067 * Prior to calling add Tx LAN queue: 4068 * Initialize the following as part of the Tx queue context: 4069 * Completion queue ID if the queue uses Completion queue, Quanta profile, 4070 * Cache profile and Packet shaper profile. 4071 * 4072 * After add Tx LAN queue AQ command is completed: 4073 * Interrupts should be associated with specific queues, 4074 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 4075 * flow. 4076 */ 4077 static int 4078 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4079 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 4080 struct ice_sq_cd *cd) 4081 { 4082 struct ice_aqc_add_tx_qgrp *list; 4083 struct ice_aqc_add_txqs *cmd; 4084 struct ice_aq_desc desc; 4085 u16 i, sum_size = 0; 4086 4087 cmd = &desc.params.add_txqs; 4088 4089 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 4090 4091 if (!qg_list) 4092 return -EINVAL; 4093 4094 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4095 return -EINVAL; 4096 4097 for (i = 0, list = qg_list; i < num_qgrps; i++) { 4098 sum_size += struct_size(list, txqs, list->num_txqs); 4099 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 4100 list->num_txqs); 4101 } 4102 4103 if (buf_size != sum_size) 4104 return -EINVAL; 4105 4106 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4107 4108 cmd->num_qgrps = num_qgrps; 4109 4110 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4111 } 4112 4113 /** 4114 * ice_aq_dis_lan_txq 4115 * @hw: pointer to the hardware structure 4116 * @num_qgrps: number of groups in the list 4117 * @qg_list: the list of groups to disable 4118 * @buf_size: the total size of the qg_list buffer in bytes 4119 * @rst_src: if called due to reset, specifies the reset source 4120 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4121 * @cd: pointer to command details structure or NULL 4122 * 4123 * Disable LAN Tx queue (0x0C31) 4124 */ 4125 static int 4126 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 4127 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 4128 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4129 struct ice_sq_cd *cd) 4130 { 4131 struct ice_aqc_dis_txq_item *item; 4132 struct ice_aqc_dis_txqs *cmd; 4133 struct ice_aq_desc desc; 4134 u16 i, sz = 0; 4135 int status; 4136 4137 cmd = &desc.params.dis_txqs; 4138 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 4139 4140 /* qg_list can be NULL only in VM/VF reset flow */ 4141 if (!qg_list && !rst_src) 4142 return -EINVAL; 4143 4144 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4145 return -EINVAL; 4146 4147 cmd->num_entries = num_qgrps; 4148 4149 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 4150 ICE_AQC_Q_DIS_TIMEOUT_M); 4151 4152 switch (rst_src) { 4153 case ICE_VM_RESET: 4154 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4155 cmd->vmvf_and_timeout |= 4156 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 4157 break; 4158 case ICE_VF_RESET: 4159 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4160 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4161 cmd->vmvf_and_timeout |= 4162 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 4163 ICE_AQC_Q_DIS_VMVF_NUM_M); 4164 break; 4165 case ICE_NO_RESET: 4166 default: 4167 break; 4168 } 4169 4170 /* flush pipe on time out */ 4171 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4172 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4173 if (!qg_list) 4174 goto do_aq; 4175 4176 /* set RD bit to indicate that command buffer is provided by the driver 4177 * and it needs to be read by the firmware 4178 */ 4179 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4180 4181 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4182 u16 item_size = struct_size(item, q_id, item->num_qs); 4183 4184 /* If the num of queues is even, add 2 bytes of padding */ 4185 if ((item->num_qs % 2) == 0) 4186 item_size += 2; 4187 4188 sz += item_size; 4189 4190 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4191 } 4192 4193 if (buf_size != sz) 4194 return -EINVAL; 4195 4196 do_aq: 4197 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4198 if (status) { 4199 if (!qg_list) 4200 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4201 vmvf_num, hw->adminq.sq_last_status); 4202 else 4203 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4204 le16_to_cpu(qg_list[0].q_id[0]), 4205 hw->adminq.sq_last_status); 4206 } 4207 return status; 4208 } 4209 4210 /** 4211 * ice_aq_add_rdma_qsets 4212 * @hw: pointer to the hardware structure 4213 * @num_qset_grps: Number of RDMA Qset groups 4214 * @qset_list: list of Qset groups to be added 4215 * @buf_size: size of buffer for indirect command 4216 * @cd: pointer to command details structure or NULL 4217 * 4218 * Add Tx RDMA Qsets (0x0C33) 4219 */ 4220 static int 4221 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4222 struct ice_aqc_add_rdma_qset_data *qset_list, 4223 u16 buf_size, struct ice_sq_cd *cd) 4224 { 4225 struct ice_aqc_add_rdma_qset_data *list; 4226 struct ice_aqc_add_rdma_qset *cmd; 4227 struct ice_aq_desc desc; 4228 u16 i, sum_size = 0; 4229 4230 cmd = &desc.params.add_rdma_qset; 4231 4232 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4233 4234 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4235 return -EINVAL; 4236 4237 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4238 u16 num_qsets = le16_to_cpu(list->num_qsets); 4239 4240 sum_size += struct_size(list, rdma_qsets, num_qsets); 4241 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4242 num_qsets); 4243 } 4244 4245 if (buf_size != sum_size) 4246 return -EINVAL; 4247 4248 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4249 4250 cmd->num_qset_grps = num_qset_grps; 4251 4252 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4253 } 4254 4255 /* End of FW Admin Queue command wrappers */ 4256 4257 /** 4258 * ice_write_byte - write a byte to a packed context structure 4259 * @src_ctx: the context structure to read from 4260 * @dest_ctx: the context to be written to 4261 * @ce_info: a description of the struct to be filled 4262 */ 4263 static void 4264 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4265 { 4266 u8 src_byte, dest_byte, mask; 4267 u8 *from, *dest; 4268 u16 shift_width; 4269 4270 /* copy from the next struct field */ 4271 from = src_ctx + ce_info->offset; 4272 4273 /* prepare the bits and mask */ 4274 shift_width = ce_info->lsb % 8; 4275 mask = (u8)(BIT(ce_info->width) - 1); 4276 4277 src_byte = *from; 4278 src_byte &= mask; 4279 4280 /* shift to correct alignment */ 4281 mask <<= shift_width; 4282 src_byte <<= shift_width; 4283 4284 /* get the current bits from the target bit string */ 4285 dest = dest_ctx + (ce_info->lsb / 8); 4286 4287 memcpy(&dest_byte, dest, sizeof(dest_byte)); 4288 4289 dest_byte &= ~mask; /* get the bits not changing */ 4290 dest_byte |= src_byte; /* add in the new bits */ 4291 4292 /* put it all back */ 4293 memcpy(dest, &dest_byte, sizeof(dest_byte)); 4294 } 4295 4296 /** 4297 * ice_write_word - write a word to a packed context structure 4298 * @src_ctx: the context structure to read from 4299 * @dest_ctx: the context to be written to 4300 * @ce_info: a description of the struct to be filled 4301 */ 4302 static void 4303 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4304 { 4305 u16 src_word, mask; 4306 __le16 dest_word; 4307 u8 *from, *dest; 4308 u16 shift_width; 4309 4310 /* copy from the next struct field */ 4311 from = src_ctx + ce_info->offset; 4312 4313 /* prepare the bits and mask */ 4314 shift_width = ce_info->lsb % 8; 4315 mask = BIT(ce_info->width) - 1; 4316 4317 /* don't swizzle the bits until after the mask because the mask bits 4318 * will be in a different bit position on big endian machines 4319 */ 4320 src_word = *(u16 *)from; 4321 src_word &= mask; 4322 4323 /* shift to correct alignment */ 4324 mask <<= shift_width; 4325 src_word <<= shift_width; 4326 4327 /* get the current bits from the target bit string */ 4328 dest = dest_ctx + (ce_info->lsb / 8); 4329 4330 memcpy(&dest_word, dest, sizeof(dest_word)); 4331 4332 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 4333 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 4334 4335 /* put it all back */ 4336 memcpy(dest, &dest_word, sizeof(dest_word)); 4337 } 4338 4339 /** 4340 * ice_write_dword - write a dword to a packed context structure 4341 * @src_ctx: the context structure to read from 4342 * @dest_ctx: the context to be written to 4343 * @ce_info: a description of the struct to be filled 4344 */ 4345 static void 4346 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4347 { 4348 u32 src_dword, mask; 4349 __le32 dest_dword; 4350 u8 *from, *dest; 4351 u16 shift_width; 4352 4353 /* copy from the next struct field */ 4354 from = src_ctx + ce_info->offset; 4355 4356 /* prepare the bits and mask */ 4357 shift_width = ce_info->lsb % 8; 4358 4359 /* if the field width is exactly 32 on an x86 machine, then the shift 4360 * operation will not work because the SHL instructions count is masked 4361 * to 5 bits so the shift will do nothing 4362 */ 4363 if (ce_info->width < 32) 4364 mask = BIT(ce_info->width) - 1; 4365 else 4366 mask = (u32)~0; 4367 4368 /* don't swizzle the bits until after the mask because the mask bits 4369 * will be in a different bit position on big endian machines 4370 */ 4371 src_dword = *(u32 *)from; 4372 src_dword &= mask; 4373 4374 /* shift to correct alignment */ 4375 mask <<= shift_width; 4376 src_dword <<= shift_width; 4377 4378 /* get the current bits from the target bit string */ 4379 dest = dest_ctx + (ce_info->lsb / 8); 4380 4381 memcpy(&dest_dword, dest, sizeof(dest_dword)); 4382 4383 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 4384 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 4385 4386 /* put it all back */ 4387 memcpy(dest, &dest_dword, sizeof(dest_dword)); 4388 } 4389 4390 /** 4391 * ice_write_qword - write a qword to a packed context structure 4392 * @src_ctx: the context structure to read from 4393 * @dest_ctx: the context to be written to 4394 * @ce_info: a description of the struct to be filled 4395 */ 4396 static void 4397 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4398 { 4399 u64 src_qword, mask; 4400 __le64 dest_qword; 4401 u8 *from, *dest; 4402 u16 shift_width; 4403 4404 /* copy from the next struct field */ 4405 from = src_ctx + ce_info->offset; 4406 4407 /* prepare the bits and mask */ 4408 shift_width = ce_info->lsb % 8; 4409 4410 /* if the field width is exactly 64 on an x86 machine, then the shift 4411 * operation will not work because the SHL instructions count is masked 4412 * to 6 bits so the shift will do nothing 4413 */ 4414 if (ce_info->width < 64) 4415 mask = BIT_ULL(ce_info->width) - 1; 4416 else 4417 mask = (u64)~0; 4418 4419 /* don't swizzle the bits until after the mask because the mask bits 4420 * will be in a different bit position on big endian machines 4421 */ 4422 src_qword = *(u64 *)from; 4423 src_qword &= mask; 4424 4425 /* shift to correct alignment */ 4426 mask <<= shift_width; 4427 src_qword <<= shift_width; 4428 4429 /* get the current bits from the target bit string */ 4430 dest = dest_ctx + (ce_info->lsb / 8); 4431 4432 memcpy(&dest_qword, dest, sizeof(dest_qword)); 4433 4434 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 4435 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 4436 4437 /* put it all back */ 4438 memcpy(dest, &dest_qword, sizeof(dest_qword)); 4439 } 4440 4441 /** 4442 * ice_set_ctx - set context bits in packed structure 4443 * @hw: pointer to the hardware structure 4444 * @src_ctx: pointer to a generic non-packed context structure 4445 * @dest_ctx: pointer to memory for the packed structure 4446 * @ce_info: a description of the structure to be transformed 4447 */ 4448 int 4449 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 4450 const struct ice_ctx_ele *ce_info) 4451 { 4452 int f; 4453 4454 for (f = 0; ce_info[f].width; f++) { 4455 /* We have to deal with each element of the FW response 4456 * using the correct size so that we are correct regardless 4457 * of the endianness of the machine. 4458 */ 4459 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 4460 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 4461 f, ce_info[f].width, ce_info[f].size_of); 4462 continue; 4463 } 4464 switch (ce_info[f].size_of) { 4465 case sizeof(u8): 4466 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 4467 break; 4468 case sizeof(u16): 4469 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 4470 break; 4471 case sizeof(u32): 4472 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 4473 break; 4474 case sizeof(u64): 4475 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 4476 break; 4477 default: 4478 return -EINVAL; 4479 } 4480 } 4481 4482 return 0; 4483 } 4484 4485 /** 4486 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4487 * @hw: pointer to the HW struct 4488 * @vsi_handle: software VSI handle 4489 * @tc: TC number 4490 * @q_handle: software queue handle 4491 */ 4492 struct ice_q_ctx * 4493 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4494 { 4495 struct ice_vsi_ctx *vsi; 4496 struct ice_q_ctx *q_ctx; 4497 4498 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4499 if (!vsi) 4500 return NULL; 4501 if (q_handle >= vsi->num_lan_q_entries[tc]) 4502 return NULL; 4503 if (!vsi->lan_q_ctx[tc]) 4504 return NULL; 4505 q_ctx = vsi->lan_q_ctx[tc]; 4506 return &q_ctx[q_handle]; 4507 } 4508 4509 /** 4510 * ice_ena_vsi_txq 4511 * @pi: port information structure 4512 * @vsi_handle: software VSI handle 4513 * @tc: TC number 4514 * @q_handle: software queue handle 4515 * @num_qgrps: Number of added queue groups 4516 * @buf: list of queue groups to be added 4517 * @buf_size: size of buffer for indirect command 4518 * @cd: pointer to command details structure or NULL 4519 * 4520 * This function adds one LAN queue 4521 */ 4522 int 4523 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4524 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4525 struct ice_sq_cd *cd) 4526 { 4527 struct ice_aqc_txsched_elem_data node = { 0 }; 4528 struct ice_sched_node *parent; 4529 struct ice_q_ctx *q_ctx; 4530 struct ice_hw *hw; 4531 int status; 4532 4533 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4534 return -EIO; 4535 4536 if (num_qgrps > 1 || buf->num_txqs > 1) 4537 return -ENOSPC; 4538 4539 hw = pi->hw; 4540 4541 if (!ice_is_vsi_valid(hw, vsi_handle)) 4542 return -EINVAL; 4543 4544 mutex_lock(&pi->sched_lock); 4545 4546 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4547 if (!q_ctx) { 4548 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4549 q_handle); 4550 status = -EINVAL; 4551 goto ena_txq_exit; 4552 } 4553 4554 /* find a parent node */ 4555 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4556 ICE_SCHED_NODE_OWNER_LAN); 4557 if (!parent) { 4558 status = -EINVAL; 4559 goto ena_txq_exit; 4560 } 4561 4562 buf->parent_teid = parent->info.node_teid; 4563 node.parent_teid = parent->info.node_teid; 4564 /* Mark that the values in the "generic" section as valid. The default 4565 * value in the "generic" section is zero. This means that : 4566 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4567 * - 0 priority among siblings, indicated by Bit 1-3. 4568 * - WFQ, indicated by Bit 4. 4569 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4570 * Bit 5-6. 4571 * - Bit 7 is reserved. 4572 * Without setting the generic section as valid in valid_sections, the 4573 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4574 */ 4575 buf->txqs[0].info.valid_sections = 4576 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4577 ICE_AQC_ELEM_VALID_EIR; 4578 buf->txqs[0].info.generic = 0; 4579 buf->txqs[0].info.cir_bw.bw_profile_idx = 4580 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4581 buf->txqs[0].info.cir_bw.bw_alloc = 4582 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4583 buf->txqs[0].info.eir_bw.bw_profile_idx = 4584 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4585 buf->txqs[0].info.eir_bw.bw_alloc = 4586 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4587 4588 /* add the LAN queue */ 4589 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4590 if (status) { 4591 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4592 le16_to_cpu(buf->txqs[0].txq_id), 4593 hw->adminq.sq_last_status); 4594 goto ena_txq_exit; 4595 } 4596 4597 node.node_teid = buf->txqs[0].q_teid; 4598 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4599 q_ctx->q_handle = q_handle; 4600 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4601 4602 /* add a leaf node into scheduler tree queue layer */ 4603 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 4604 if (!status) 4605 status = ice_sched_replay_q_bw(pi, q_ctx); 4606 4607 ena_txq_exit: 4608 mutex_unlock(&pi->sched_lock); 4609 return status; 4610 } 4611 4612 /** 4613 * ice_dis_vsi_txq 4614 * @pi: port information structure 4615 * @vsi_handle: software VSI handle 4616 * @tc: TC number 4617 * @num_queues: number of queues 4618 * @q_handles: pointer to software queue handle array 4619 * @q_ids: pointer to the q_id array 4620 * @q_teids: pointer to queue node teids 4621 * @rst_src: if called due to reset, specifies the reset source 4622 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4623 * @cd: pointer to command details structure or NULL 4624 * 4625 * This function removes queues and their corresponding nodes in SW DB 4626 */ 4627 int 4628 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4629 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4630 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4631 struct ice_sq_cd *cd) 4632 { 4633 struct ice_aqc_dis_txq_item *qg_list; 4634 struct ice_q_ctx *q_ctx; 4635 int status = -ENOENT; 4636 struct ice_hw *hw; 4637 u16 i, buf_size; 4638 4639 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4640 return -EIO; 4641 4642 hw = pi->hw; 4643 4644 if (!num_queues) { 4645 /* if queue is disabled already yet the disable queue command 4646 * has to be sent to complete the VF reset, then call 4647 * ice_aq_dis_lan_txq without any queue information 4648 */ 4649 if (rst_src) 4650 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4651 vmvf_num, NULL); 4652 return -EIO; 4653 } 4654 4655 buf_size = struct_size(qg_list, q_id, 1); 4656 qg_list = kzalloc(buf_size, GFP_KERNEL); 4657 if (!qg_list) 4658 return -ENOMEM; 4659 4660 mutex_lock(&pi->sched_lock); 4661 4662 for (i = 0; i < num_queues; i++) { 4663 struct ice_sched_node *node; 4664 4665 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4666 if (!node) 4667 continue; 4668 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4669 if (!q_ctx) { 4670 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4671 q_handles[i]); 4672 continue; 4673 } 4674 if (q_ctx->q_handle != q_handles[i]) { 4675 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4676 q_ctx->q_handle, q_handles[i]); 4677 continue; 4678 } 4679 qg_list->parent_teid = node->info.parent_teid; 4680 qg_list->num_qs = 1; 4681 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4682 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4683 vmvf_num, cd); 4684 4685 if (status) 4686 break; 4687 ice_free_sched_node(pi, node); 4688 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4689 } 4690 mutex_unlock(&pi->sched_lock); 4691 kfree(qg_list); 4692 return status; 4693 } 4694 4695 /** 4696 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4697 * @pi: port information structure 4698 * @vsi_handle: software VSI handle 4699 * @tc_bitmap: TC bitmap 4700 * @maxqs: max queues array per TC 4701 * @owner: LAN or RDMA 4702 * 4703 * This function adds/updates the VSI queues per TC. 4704 */ 4705 static int 4706 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4707 u16 *maxqs, u8 owner) 4708 { 4709 int status = 0; 4710 u8 i; 4711 4712 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4713 return -EIO; 4714 4715 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4716 return -EINVAL; 4717 4718 mutex_lock(&pi->sched_lock); 4719 4720 ice_for_each_traffic_class(i) { 4721 /* configuration is possible only if TC node is present */ 4722 if (!ice_sched_get_tc_node(pi, i)) 4723 continue; 4724 4725 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4726 ice_is_tc_ena(tc_bitmap, i)); 4727 if (status) 4728 break; 4729 } 4730 4731 mutex_unlock(&pi->sched_lock); 4732 return status; 4733 } 4734 4735 /** 4736 * ice_cfg_vsi_lan - configure VSI LAN queues 4737 * @pi: port information structure 4738 * @vsi_handle: software VSI handle 4739 * @tc_bitmap: TC bitmap 4740 * @max_lanqs: max LAN queues array per TC 4741 * 4742 * This function adds/updates the VSI LAN queues per TC. 4743 */ 4744 int 4745 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4746 u16 *max_lanqs) 4747 { 4748 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4749 ICE_SCHED_NODE_OWNER_LAN); 4750 } 4751 4752 /** 4753 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 4754 * @pi: port information structure 4755 * @vsi_handle: software VSI handle 4756 * @tc_bitmap: TC bitmap 4757 * @max_rdmaqs: max RDMA queues array per TC 4758 * 4759 * This function adds/updates the VSI RDMA queues per TC. 4760 */ 4761 int 4762 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4763 u16 *max_rdmaqs) 4764 { 4765 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 4766 ICE_SCHED_NODE_OWNER_RDMA); 4767 } 4768 4769 /** 4770 * ice_ena_vsi_rdma_qset 4771 * @pi: port information structure 4772 * @vsi_handle: software VSI handle 4773 * @tc: TC number 4774 * @rdma_qset: pointer to RDMA Qset 4775 * @num_qsets: number of RDMA Qsets 4776 * @qset_teid: pointer to Qset node TEIDs 4777 * 4778 * This function adds RDMA Qset 4779 */ 4780 int 4781 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4782 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 4783 { 4784 struct ice_aqc_txsched_elem_data node = { 0 }; 4785 struct ice_aqc_add_rdma_qset_data *buf; 4786 struct ice_sched_node *parent; 4787 struct ice_hw *hw; 4788 u16 i, buf_size; 4789 int ret; 4790 4791 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4792 return -EIO; 4793 hw = pi->hw; 4794 4795 if (!ice_is_vsi_valid(hw, vsi_handle)) 4796 return -EINVAL; 4797 4798 buf_size = struct_size(buf, rdma_qsets, num_qsets); 4799 buf = kzalloc(buf_size, GFP_KERNEL); 4800 if (!buf) 4801 return -ENOMEM; 4802 mutex_lock(&pi->sched_lock); 4803 4804 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4805 ICE_SCHED_NODE_OWNER_RDMA); 4806 if (!parent) { 4807 ret = -EINVAL; 4808 goto rdma_error_exit; 4809 } 4810 buf->parent_teid = parent->info.node_teid; 4811 node.parent_teid = parent->info.node_teid; 4812 4813 buf->num_qsets = cpu_to_le16(num_qsets); 4814 for (i = 0; i < num_qsets; i++) { 4815 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 4816 buf->rdma_qsets[i].info.valid_sections = 4817 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4818 ICE_AQC_ELEM_VALID_EIR; 4819 buf->rdma_qsets[i].info.generic = 0; 4820 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 4821 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4822 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 4823 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4824 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 4825 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4826 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 4827 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4828 } 4829 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 4830 if (ret) { 4831 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 4832 goto rdma_error_exit; 4833 } 4834 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4835 for (i = 0; i < num_qsets; i++) { 4836 node.node_teid = buf->rdma_qsets[i].qset_teid; 4837 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 4838 &node); 4839 if (ret) 4840 break; 4841 qset_teid[i] = le32_to_cpu(node.node_teid); 4842 } 4843 rdma_error_exit: 4844 mutex_unlock(&pi->sched_lock); 4845 kfree(buf); 4846 return ret; 4847 } 4848 4849 /** 4850 * ice_dis_vsi_rdma_qset - free RDMA resources 4851 * @pi: port_info struct 4852 * @count: number of RDMA Qsets to free 4853 * @qset_teid: TEID of Qset node 4854 * @q_id: list of queue IDs being disabled 4855 */ 4856 int 4857 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 4858 u16 *q_id) 4859 { 4860 struct ice_aqc_dis_txq_item *qg_list; 4861 struct ice_hw *hw; 4862 int status = 0; 4863 u16 qg_size; 4864 int i; 4865 4866 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4867 return -EIO; 4868 4869 hw = pi->hw; 4870 4871 qg_size = struct_size(qg_list, q_id, 1); 4872 qg_list = kzalloc(qg_size, GFP_KERNEL); 4873 if (!qg_list) 4874 return -ENOMEM; 4875 4876 mutex_lock(&pi->sched_lock); 4877 4878 for (i = 0; i < count; i++) { 4879 struct ice_sched_node *node; 4880 4881 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 4882 if (!node) 4883 continue; 4884 4885 qg_list->parent_teid = node->info.parent_teid; 4886 qg_list->num_qs = 1; 4887 qg_list->q_id[0] = 4888 cpu_to_le16(q_id[i] | 4889 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 4890 4891 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 4892 ICE_NO_RESET, 0, NULL); 4893 if (status) 4894 break; 4895 4896 ice_free_sched_node(pi, node); 4897 } 4898 4899 mutex_unlock(&pi->sched_lock); 4900 kfree(qg_list); 4901 return status; 4902 } 4903 4904 /** 4905 * ice_replay_pre_init - replay pre initialization 4906 * @hw: pointer to the HW struct 4907 * 4908 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4909 */ 4910 static int ice_replay_pre_init(struct ice_hw *hw) 4911 { 4912 struct ice_switch_info *sw = hw->switch_info; 4913 u8 i; 4914 4915 /* Delete old entries from replay filter list head if there is any */ 4916 ice_rm_all_sw_replay_rule_info(hw); 4917 /* In start of replay, move entries into replay_rules list, it 4918 * will allow adding rules entries back to filt_rules list, 4919 * which is operational list. 4920 */ 4921 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 4922 list_replace_init(&sw->recp_list[i].filt_rules, 4923 &sw->recp_list[i].filt_replay_rules); 4924 ice_sched_replay_agg_vsi_preinit(hw); 4925 4926 return 0; 4927 } 4928 4929 /** 4930 * ice_replay_vsi - replay VSI configuration 4931 * @hw: pointer to the HW struct 4932 * @vsi_handle: driver VSI handle 4933 * 4934 * Restore all VSI configuration after reset. It is required to call this 4935 * function with main VSI first. 4936 */ 4937 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4938 { 4939 int status; 4940 4941 if (!ice_is_vsi_valid(hw, vsi_handle)) 4942 return -EINVAL; 4943 4944 /* Replay pre-initialization if there is any */ 4945 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 4946 status = ice_replay_pre_init(hw); 4947 if (status) 4948 return status; 4949 } 4950 /* Replay per VSI all RSS configurations */ 4951 status = ice_replay_rss_cfg(hw, vsi_handle); 4952 if (status) 4953 return status; 4954 /* Replay per VSI all filters */ 4955 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 4956 if (!status) 4957 status = ice_replay_vsi_agg(hw, vsi_handle); 4958 return status; 4959 } 4960 4961 /** 4962 * ice_replay_post - post replay configuration cleanup 4963 * @hw: pointer to the HW struct 4964 * 4965 * Post replay cleanup. 4966 */ 4967 void ice_replay_post(struct ice_hw *hw) 4968 { 4969 /* Delete old entries from replay filter list head */ 4970 ice_rm_all_sw_replay_rule_info(hw); 4971 ice_sched_replay_agg(hw); 4972 } 4973 4974 /** 4975 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4976 * @hw: ptr to the hardware info 4977 * @reg: offset of 64 bit HW register to read from 4978 * @prev_stat_loaded: bool to specify if previous stats are loaded 4979 * @prev_stat: ptr to previous loaded stat value 4980 * @cur_stat: ptr to current stat value 4981 */ 4982 void 4983 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4984 u64 *prev_stat, u64 *cur_stat) 4985 { 4986 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4987 4988 /* device stats are not reset at PFR, they likely will not be zeroed 4989 * when the driver starts. Thus, save the value from the first read 4990 * without adding to the statistic value so that we report stats which 4991 * count up from zero. 4992 */ 4993 if (!prev_stat_loaded) { 4994 *prev_stat = new_data; 4995 return; 4996 } 4997 4998 /* Calculate the difference between the new and old values, and then 4999 * add it to the software stat value. 5000 */ 5001 if (new_data >= *prev_stat) 5002 *cur_stat += new_data - *prev_stat; 5003 else 5004 /* to manage the potential roll-over */ 5005 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 5006 5007 /* Update the previously stored value to prepare for next read */ 5008 *prev_stat = new_data; 5009 } 5010 5011 /** 5012 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 5013 * @hw: ptr to the hardware info 5014 * @reg: offset of HW register to read from 5015 * @prev_stat_loaded: bool to specify if previous stats are loaded 5016 * @prev_stat: ptr to previous loaded stat value 5017 * @cur_stat: ptr to current stat value 5018 */ 5019 void 5020 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 5021 u64 *prev_stat, u64 *cur_stat) 5022 { 5023 u32 new_data; 5024 5025 new_data = rd32(hw, reg); 5026 5027 /* device stats are not reset at PFR, they likely will not be zeroed 5028 * when the driver starts. Thus, save the value from the first read 5029 * without adding to the statistic value so that we report stats which 5030 * count up from zero. 5031 */ 5032 if (!prev_stat_loaded) { 5033 *prev_stat = new_data; 5034 return; 5035 } 5036 5037 /* Calculate the difference between the new and old values, and then 5038 * add it to the software stat value. 5039 */ 5040 if (new_data >= *prev_stat) 5041 *cur_stat += new_data - *prev_stat; 5042 else 5043 /* to manage the potential roll-over */ 5044 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 5045 5046 /* Update the previously stored value to prepare for next read */ 5047 *prev_stat = new_data; 5048 } 5049 5050 /** 5051 * ice_sched_query_elem - query element information from HW 5052 * @hw: pointer to the HW struct 5053 * @node_teid: node TEID to be queried 5054 * @buf: buffer to element information 5055 * 5056 * This function queries HW element information 5057 */ 5058 int 5059 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 5060 struct ice_aqc_txsched_elem_data *buf) 5061 { 5062 u16 buf_size, num_elem_ret = 0; 5063 int status; 5064 5065 buf_size = sizeof(*buf); 5066 memset(buf, 0, buf_size); 5067 buf->node_teid = cpu_to_le32(node_teid); 5068 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 5069 NULL); 5070 if (status || num_elem_ret != 1) 5071 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 5072 return status; 5073 } 5074 5075 /** 5076 * ice_aq_read_i2c 5077 * @hw: pointer to the hw struct 5078 * @topo_addr: topology address for a device to communicate with 5079 * @bus_addr: 7-bit I2C bus address 5080 * @addr: I2C memory address (I2C offset) with up to 16 bits 5081 * @params: I2C parameters: bit [7] - Repeated start, 5082 * bits [6:5] data offset size, 5083 * bit [4] - I2C address type, 5084 * bits [3:0] - data size to read (0-16 bytes) 5085 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 5086 * @cd: pointer to command details structure or NULL 5087 * 5088 * Read I2C (0x06E2) 5089 */ 5090 int 5091 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5092 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5093 struct ice_sq_cd *cd) 5094 { 5095 struct ice_aq_desc desc = { 0 }; 5096 struct ice_aqc_i2c *cmd; 5097 u8 data_size; 5098 int status; 5099 5100 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 5101 cmd = &desc.params.read_write_i2c; 5102 5103 if (!data) 5104 return -EINVAL; 5105 5106 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5107 5108 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5109 cmd->topo_addr = topo_addr; 5110 cmd->i2c_params = params; 5111 cmd->i2c_addr = addr; 5112 5113 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5114 if (!status) { 5115 struct ice_aqc_read_i2c_resp *resp; 5116 u8 i; 5117 5118 resp = &desc.params.read_i2c_resp; 5119 for (i = 0; i < data_size; i++) { 5120 *data = resp->i2c_data[i]; 5121 data++; 5122 } 5123 } 5124 5125 return status; 5126 } 5127 5128 /** 5129 * ice_aq_write_i2c 5130 * @hw: pointer to the hw struct 5131 * @topo_addr: topology address for a device to communicate with 5132 * @bus_addr: 7-bit I2C bus address 5133 * @addr: I2C memory address (I2C offset) with up to 16 bits 5134 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 5135 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 5136 * @cd: pointer to command details structure or NULL 5137 * 5138 * Write I2C (0x06E3) 5139 * 5140 * * Return: 5141 * * 0 - Successful write to the i2c device 5142 * * -EINVAL - Data size greater than 4 bytes 5143 * * -EIO - FW error 5144 */ 5145 int 5146 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5147 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5148 struct ice_sq_cd *cd) 5149 { 5150 struct ice_aq_desc desc = { 0 }; 5151 struct ice_aqc_i2c *cmd; 5152 u8 data_size; 5153 5154 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5155 cmd = &desc.params.read_write_i2c; 5156 5157 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5158 5159 /* data_size limited to 4 */ 5160 if (data_size > 4) 5161 return -EINVAL; 5162 5163 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5164 cmd->topo_addr = topo_addr; 5165 cmd->i2c_params = params; 5166 cmd->i2c_addr = addr; 5167 5168 memcpy(cmd->i2c_data, data, data_size); 5169 5170 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5171 } 5172 5173 /** 5174 * ice_aq_set_driver_param - Set driver parameter to share via firmware 5175 * @hw: pointer to the HW struct 5176 * @idx: parameter index to set 5177 * @value: the value to set the parameter to 5178 * @cd: pointer to command details structure or NULL 5179 * 5180 * Set the value of one of the software defined parameters. All PFs connected 5181 * to this device can read the value using ice_aq_get_driver_param. 5182 * 5183 * Note that firmware provides no synchronization or locking, and will not 5184 * save the parameter value during a device reset. It is expected that 5185 * a single PF will write the parameter value, while all other PFs will only 5186 * read it. 5187 */ 5188 int 5189 ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx, 5190 u32 value, struct ice_sq_cd *cd) 5191 { 5192 struct ice_aqc_driver_shared_params *cmd; 5193 struct ice_aq_desc desc; 5194 5195 if (idx >= ICE_AQC_DRIVER_PARAM_MAX) 5196 return -EIO; 5197 5198 cmd = &desc.params.drv_shared_params; 5199 5200 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params); 5201 5202 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_SET; 5203 cmd->param_indx = idx; 5204 cmd->param_val = cpu_to_le32(value); 5205 5206 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5207 } 5208 5209 /** 5210 * ice_aq_get_driver_param - Get driver parameter shared via firmware 5211 * @hw: pointer to the HW struct 5212 * @idx: parameter index to set 5213 * @value: storage to return the shared parameter 5214 * @cd: pointer to command details structure or NULL 5215 * 5216 * Get the value of one of the software defined parameters. 5217 * 5218 * Note that firmware provides no synchronization or locking. It is expected 5219 * that only a single PF will write a given parameter. 5220 */ 5221 int 5222 ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx, 5223 u32 *value, struct ice_sq_cd *cd) 5224 { 5225 struct ice_aqc_driver_shared_params *cmd; 5226 struct ice_aq_desc desc; 5227 int status; 5228 5229 if (idx >= ICE_AQC_DRIVER_PARAM_MAX) 5230 return -EIO; 5231 5232 cmd = &desc.params.drv_shared_params; 5233 5234 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params); 5235 5236 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_GET; 5237 cmd->param_indx = idx; 5238 5239 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5240 if (status) 5241 return status; 5242 5243 *value = le32_to_cpu(cmd->param_val); 5244 5245 return 0; 5246 } 5247 5248 /** 5249 * ice_aq_set_gpio 5250 * @hw: pointer to the hw struct 5251 * @gpio_ctrl_handle: GPIO controller node handle 5252 * @pin_idx: IO Number of the GPIO that needs to be set 5253 * @value: SW provide IO value to set in the LSB 5254 * @cd: pointer to command details structure or NULL 5255 * 5256 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 5257 */ 5258 int 5259 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 5260 struct ice_sq_cd *cd) 5261 { 5262 struct ice_aqc_gpio *cmd; 5263 struct ice_aq_desc desc; 5264 5265 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 5266 cmd = &desc.params.read_write_gpio; 5267 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5268 cmd->gpio_num = pin_idx; 5269 cmd->gpio_val = value ? 1 : 0; 5270 5271 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5272 } 5273 5274 /** 5275 * ice_aq_get_gpio 5276 * @hw: pointer to the hw struct 5277 * @gpio_ctrl_handle: GPIO controller node handle 5278 * @pin_idx: IO Number of the GPIO that needs to be set 5279 * @value: IO value read 5280 * @cd: pointer to command details structure or NULL 5281 * 5282 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 5283 * the topology 5284 */ 5285 int 5286 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 5287 bool *value, struct ice_sq_cd *cd) 5288 { 5289 struct ice_aqc_gpio *cmd; 5290 struct ice_aq_desc desc; 5291 int status; 5292 5293 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 5294 cmd = &desc.params.read_write_gpio; 5295 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5296 cmd->gpio_num = pin_idx; 5297 5298 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5299 if (status) 5300 return status; 5301 5302 *value = !!cmd->gpio_val; 5303 return 0; 5304 } 5305 5306 /** 5307 * ice_is_fw_api_min_ver 5308 * @hw: pointer to the hardware structure 5309 * @maj: major version 5310 * @min: minor version 5311 * @patch: patch version 5312 * 5313 * Checks if the firmware API is minimum version 5314 */ 5315 static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch) 5316 { 5317 if (hw->api_maj_ver == maj) { 5318 if (hw->api_min_ver > min) 5319 return true; 5320 if (hw->api_min_ver == min && hw->api_patch >= patch) 5321 return true; 5322 } else if (hw->api_maj_ver > maj) { 5323 return true; 5324 } 5325 5326 return false; 5327 } 5328 5329 /** 5330 * ice_fw_supports_link_override 5331 * @hw: pointer to the hardware structure 5332 * 5333 * Checks if the firmware supports link override 5334 */ 5335 bool ice_fw_supports_link_override(struct ice_hw *hw) 5336 { 5337 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LINK_OVERRIDE_MAJ, 5338 ICE_FW_API_LINK_OVERRIDE_MIN, 5339 ICE_FW_API_LINK_OVERRIDE_PATCH); 5340 } 5341 5342 /** 5343 * ice_get_link_default_override 5344 * @ldo: pointer to the link default override struct 5345 * @pi: pointer to the port info struct 5346 * 5347 * Gets the link default override for a port 5348 */ 5349 int 5350 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 5351 struct ice_port_info *pi) 5352 { 5353 u16 i, tlv, tlv_len, tlv_start, buf, offset; 5354 struct ice_hw *hw = pi->hw; 5355 int status; 5356 5357 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 5358 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 5359 if (status) { 5360 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 5361 return status; 5362 } 5363 5364 /* Each port has its own config; calculate for our port */ 5365 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 5366 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 5367 5368 /* link options first */ 5369 status = ice_read_sr_word(hw, tlv_start, &buf); 5370 if (status) { 5371 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5372 return status; 5373 } 5374 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 5375 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 5376 ICE_LINK_OVERRIDE_PHY_CFG_S; 5377 5378 /* link PHY config */ 5379 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 5380 status = ice_read_sr_word(hw, offset, &buf); 5381 if (status) { 5382 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 5383 return status; 5384 } 5385 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 5386 5387 /* PHY types low */ 5388 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 5389 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5390 status = ice_read_sr_word(hw, (offset + i), &buf); 5391 if (status) { 5392 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5393 return status; 5394 } 5395 /* shift 16 bits at a time to fill 64 bits */ 5396 ldo->phy_type_low |= ((u64)buf << (i * 16)); 5397 } 5398 5399 /* PHY types high */ 5400 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 5401 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 5402 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5403 status = ice_read_sr_word(hw, (offset + i), &buf); 5404 if (status) { 5405 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5406 return status; 5407 } 5408 /* shift 16 bits at a time to fill 64 bits */ 5409 ldo->phy_type_high |= ((u64)buf << (i * 16)); 5410 } 5411 5412 return status; 5413 } 5414 5415 /** 5416 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 5417 * @caps: get PHY capability data 5418 */ 5419 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 5420 { 5421 if (caps->caps & ICE_AQC_PHY_AN_MODE || 5422 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 5423 ICE_AQC_PHY_AN_EN_CLAUSE73 | 5424 ICE_AQC_PHY_AN_EN_CLAUSE37)) 5425 return true; 5426 5427 return false; 5428 } 5429 5430 /** 5431 * ice_aq_set_lldp_mib - Set the LLDP MIB 5432 * @hw: pointer to the HW struct 5433 * @mib_type: Local, Remote or both Local and Remote MIBs 5434 * @buf: pointer to the caller-supplied buffer to store the MIB block 5435 * @buf_size: size of the buffer (in bytes) 5436 * @cd: pointer to command details structure or NULL 5437 * 5438 * Set the LLDP MIB. (0x0A08) 5439 */ 5440 int 5441 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 5442 struct ice_sq_cd *cd) 5443 { 5444 struct ice_aqc_lldp_set_local_mib *cmd; 5445 struct ice_aq_desc desc; 5446 5447 cmd = &desc.params.lldp_set_mib; 5448 5449 if (buf_size == 0 || !buf) 5450 return -EINVAL; 5451 5452 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5453 5454 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 5455 desc.datalen = cpu_to_le16(buf_size); 5456 5457 cmd->type = mib_type; 5458 cmd->length = cpu_to_le16(buf_size); 5459 5460 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5461 } 5462 5463 /** 5464 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5465 * @hw: pointer to HW struct 5466 */ 5467 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 5468 { 5469 if (hw->mac_type != ICE_MAC_E810) 5470 return false; 5471 5472 return ice_is_fw_api_min_ver(hw, ICE_FW_API_LLDP_FLTR_MAJ, 5473 ICE_FW_API_LLDP_FLTR_MIN, 5474 ICE_FW_API_LLDP_FLTR_PATCH); 5475 } 5476 5477 /** 5478 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 5479 * @hw: pointer to HW struct 5480 * @vsi_num: absolute HW index for VSI 5481 * @add: boolean for if adding or removing a filter 5482 */ 5483 int 5484 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 5485 { 5486 struct ice_aqc_lldp_filter_ctrl *cmd; 5487 struct ice_aq_desc desc; 5488 5489 cmd = &desc.params.lldp_filter_ctrl; 5490 5491 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 5492 5493 if (add) 5494 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 5495 else 5496 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 5497 5498 cmd->vsi_num = cpu_to_le16(vsi_num); 5499 5500 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5501 } 5502 5503 /** 5504 * ice_fw_supports_report_dflt_cfg 5505 * @hw: pointer to the hardware structure 5506 * 5507 * Checks if the firmware supports report default configuration 5508 */ 5509 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 5510 { 5511 return ice_is_fw_api_min_ver(hw, ICE_FW_API_REPORT_DFLT_CFG_MAJ, 5512 ICE_FW_API_REPORT_DFLT_CFG_MIN, 5513 ICE_FW_API_REPORT_DFLT_CFG_PATCH); 5514 } 5515