1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 9 #define ICE_PF_RESET_WAIT_COUNT 300 10 11 /** 12 * ice_set_mac_type - Sets MAC type 13 * @hw: pointer to the HW structure 14 * 15 * This function sets the MAC type of the adapter based on the 16 * vendor ID and device ID stored in the HW structure. 17 */ 18 static int ice_set_mac_type(struct ice_hw *hw) 19 { 20 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 21 return -ENODEV; 22 23 switch (hw->device_id) { 24 case ICE_DEV_ID_E810C_BACKPLANE: 25 case ICE_DEV_ID_E810C_QSFP: 26 case ICE_DEV_ID_E810C_SFP: 27 case ICE_DEV_ID_E810_XXV_BACKPLANE: 28 case ICE_DEV_ID_E810_XXV_QSFP: 29 case ICE_DEV_ID_E810_XXV_SFP: 30 hw->mac_type = ICE_MAC_E810; 31 break; 32 case ICE_DEV_ID_E823C_10G_BASE_T: 33 case ICE_DEV_ID_E823C_BACKPLANE: 34 case ICE_DEV_ID_E823C_QSFP: 35 case ICE_DEV_ID_E823C_SFP: 36 case ICE_DEV_ID_E823C_SGMII: 37 case ICE_DEV_ID_E822C_10G_BASE_T: 38 case ICE_DEV_ID_E822C_BACKPLANE: 39 case ICE_DEV_ID_E822C_QSFP: 40 case ICE_DEV_ID_E822C_SFP: 41 case ICE_DEV_ID_E822C_SGMII: 42 case ICE_DEV_ID_E822L_10G_BASE_T: 43 case ICE_DEV_ID_E822L_BACKPLANE: 44 case ICE_DEV_ID_E822L_SFP: 45 case ICE_DEV_ID_E822L_SGMII: 46 case ICE_DEV_ID_E823L_10G_BASE_T: 47 case ICE_DEV_ID_E823L_1GBE: 48 case ICE_DEV_ID_E823L_BACKPLANE: 49 case ICE_DEV_ID_E823L_QSFP: 50 case ICE_DEV_ID_E823L_SFP: 51 hw->mac_type = ICE_MAC_GENERIC; 52 break; 53 default: 54 hw->mac_type = ICE_MAC_UNKNOWN; 55 break; 56 } 57 58 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 59 return 0; 60 } 61 62 /** 63 * ice_is_e810 64 * @hw: pointer to the hardware structure 65 * 66 * returns true if the device is E810 based, false if not. 67 */ 68 bool ice_is_e810(struct ice_hw *hw) 69 { 70 return hw->mac_type == ICE_MAC_E810; 71 } 72 73 /** 74 * ice_is_e810t 75 * @hw: pointer to the hardware structure 76 * 77 * returns true if the device is E810T based, false if not. 78 */ 79 bool ice_is_e810t(struct ice_hw *hw) 80 { 81 switch (hw->device_id) { 82 case ICE_DEV_ID_E810C_SFP: 83 if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T || 84 hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2) 85 return true; 86 break; 87 default: 88 break; 89 } 90 91 return false; 92 } 93 94 /** 95 * ice_clear_pf_cfg - Clear PF configuration 96 * @hw: pointer to the hardware structure 97 * 98 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 99 * configuration, flow director filters, etc.). 100 */ 101 int ice_clear_pf_cfg(struct ice_hw *hw) 102 { 103 struct ice_aq_desc desc; 104 105 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 106 107 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 108 } 109 110 /** 111 * ice_aq_manage_mac_read - manage MAC address read command 112 * @hw: pointer to the HW struct 113 * @buf: a virtual buffer to hold the manage MAC read response 114 * @buf_size: Size of the virtual buffer 115 * @cd: pointer to command details structure or NULL 116 * 117 * This function is used to return per PF station MAC address (0x0107). 118 * NOTE: Upon successful completion of this command, MAC address information 119 * is returned in user specified buffer. Please interpret user specified 120 * buffer as "manage_mac_read" response. 121 * Response such as various MAC addresses are stored in HW struct (port.mac) 122 * ice_discover_dev_caps is expected to be called before this function is 123 * called. 124 */ 125 static int 126 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 127 struct ice_sq_cd *cd) 128 { 129 struct ice_aqc_manage_mac_read_resp *resp; 130 struct ice_aqc_manage_mac_read *cmd; 131 struct ice_aq_desc desc; 132 int status; 133 u16 flags; 134 u8 i; 135 136 cmd = &desc.params.mac_read; 137 138 if (buf_size < sizeof(*resp)) 139 return -EINVAL; 140 141 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 142 143 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 144 if (status) 145 return status; 146 147 resp = buf; 148 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 149 150 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 151 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 152 return -EIO; 153 } 154 155 /* A single port can report up to two (LAN and WoL) addresses */ 156 for (i = 0; i < cmd->num_addr; i++) 157 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 158 ether_addr_copy(hw->port_info->mac.lan_addr, 159 resp[i].mac_addr); 160 ether_addr_copy(hw->port_info->mac.perm_addr, 161 resp[i].mac_addr); 162 break; 163 } 164 165 return 0; 166 } 167 168 /** 169 * ice_aq_get_phy_caps - returns PHY capabilities 170 * @pi: port information structure 171 * @qual_mods: report qualified modules 172 * @report_mode: report mode capabilities 173 * @pcaps: structure for PHY capabilities to be filled 174 * @cd: pointer to command details structure or NULL 175 * 176 * Returns the various PHY capabilities supported on the Port (0x0600) 177 */ 178 int 179 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 180 struct ice_aqc_get_phy_caps_data *pcaps, 181 struct ice_sq_cd *cd) 182 { 183 struct ice_aqc_get_phy_caps *cmd; 184 u16 pcaps_size = sizeof(*pcaps); 185 struct ice_aq_desc desc; 186 struct ice_hw *hw; 187 int status; 188 189 cmd = &desc.params.get_phy; 190 191 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 192 return -EINVAL; 193 hw = pi->hw; 194 195 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 196 !ice_fw_supports_report_dflt_cfg(hw)) 197 return -EINVAL; 198 199 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 200 201 if (qual_mods) 202 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 203 204 cmd->param0 |= cpu_to_le16(report_mode); 205 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 206 207 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 208 report_mode); 209 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 210 (unsigned long long)le64_to_cpu(pcaps->phy_type_low)); 211 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 212 (unsigned long long)le64_to_cpu(pcaps->phy_type_high)); 213 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 214 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 215 pcaps->low_power_ctrl_an); 216 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 217 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 218 pcaps->eeer_value); 219 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 220 pcaps->link_fec_options); 221 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 222 pcaps->module_compliance_enforcement); 223 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 224 pcaps->extended_compliance_code); 225 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 226 pcaps->module_type[0]); 227 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 228 pcaps->module_type[1]); 229 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 230 pcaps->module_type[2]); 231 232 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 233 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 234 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 235 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 236 sizeof(pi->phy.link_info.module_type)); 237 } 238 239 return status; 240 } 241 242 /** 243 * ice_aq_get_link_topo_handle - get link topology node return status 244 * @pi: port information structure 245 * @node_type: requested node type 246 * @cd: pointer to command details structure or NULL 247 * 248 * Get link topology node return status for specified node type (0x06E0) 249 * 250 * Node type cage can be used to determine if cage is present. If AQC 251 * returns error (ENOENT), then no cage present. If no cage present, then 252 * connection type is backplane or BASE-T. 253 */ 254 static int 255 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 256 struct ice_sq_cd *cd) 257 { 258 struct ice_aqc_get_link_topo *cmd; 259 struct ice_aq_desc desc; 260 261 cmd = &desc.params.get_link_topo; 262 263 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 264 265 cmd->addr.topo_params.node_type_ctx = 266 (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 267 ICE_AQC_LINK_TOPO_NODE_CTX_S); 268 269 /* set node type */ 270 cmd->addr.topo_params.node_type_ctx |= 271 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 272 273 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 274 } 275 276 /** 277 * ice_is_media_cage_present 278 * @pi: port information structure 279 * 280 * Returns true if media cage is present, else false. If no cage, then 281 * media type is backplane or BASE-T. 282 */ 283 static bool ice_is_media_cage_present(struct ice_port_info *pi) 284 { 285 /* Node type cage can be used to determine if cage is present. If AQC 286 * returns error (ENOENT), then no cage present. If no cage present then 287 * connection type is backplane or BASE-T. 288 */ 289 return !ice_aq_get_link_topo_handle(pi, 290 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 291 NULL); 292 } 293 294 /** 295 * ice_get_media_type - Gets media type 296 * @pi: port information structure 297 */ 298 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 299 { 300 struct ice_link_status *hw_link_info; 301 302 if (!pi) 303 return ICE_MEDIA_UNKNOWN; 304 305 hw_link_info = &pi->phy.link_info; 306 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 307 /* If more than one media type is selected, report unknown */ 308 return ICE_MEDIA_UNKNOWN; 309 310 if (hw_link_info->phy_type_low) { 311 /* 1G SGMII is a special case where some DA cable PHYs 312 * may show this as an option when it really shouldn't 313 * be since SGMII is meant to be between a MAC and a PHY 314 * in a backplane. Try to detect this case and handle it 315 */ 316 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 317 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 318 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 319 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 320 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 321 return ICE_MEDIA_DA; 322 323 switch (hw_link_info->phy_type_low) { 324 case ICE_PHY_TYPE_LOW_1000BASE_SX: 325 case ICE_PHY_TYPE_LOW_1000BASE_LX: 326 case ICE_PHY_TYPE_LOW_10GBASE_SR: 327 case ICE_PHY_TYPE_LOW_10GBASE_LR: 328 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 329 case ICE_PHY_TYPE_LOW_25GBASE_SR: 330 case ICE_PHY_TYPE_LOW_25GBASE_LR: 331 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 332 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 333 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 334 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 335 case ICE_PHY_TYPE_LOW_50GBASE_SR: 336 case ICE_PHY_TYPE_LOW_50GBASE_FR: 337 case ICE_PHY_TYPE_LOW_50GBASE_LR: 338 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 339 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 340 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 341 case ICE_PHY_TYPE_LOW_100GBASE_DR: 342 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 343 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 344 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 345 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 346 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 347 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 348 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 349 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 350 return ICE_MEDIA_FIBER; 351 case ICE_PHY_TYPE_LOW_100BASE_TX: 352 case ICE_PHY_TYPE_LOW_1000BASE_T: 353 case ICE_PHY_TYPE_LOW_2500BASE_T: 354 case ICE_PHY_TYPE_LOW_5GBASE_T: 355 case ICE_PHY_TYPE_LOW_10GBASE_T: 356 case ICE_PHY_TYPE_LOW_25GBASE_T: 357 return ICE_MEDIA_BASET; 358 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 359 case ICE_PHY_TYPE_LOW_25GBASE_CR: 360 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 361 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 362 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 363 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 364 case ICE_PHY_TYPE_LOW_50GBASE_CP: 365 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 366 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 367 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 368 return ICE_MEDIA_DA; 369 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 370 case ICE_PHY_TYPE_LOW_40G_XLAUI: 371 case ICE_PHY_TYPE_LOW_50G_LAUI2: 372 case ICE_PHY_TYPE_LOW_50G_AUI2: 373 case ICE_PHY_TYPE_LOW_50G_AUI1: 374 case ICE_PHY_TYPE_LOW_100G_AUI4: 375 case ICE_PHY_TYPE_LOW_100G_CAUI4: 376 if (ice_is_media_cage_present(pi)) 377 return ICE_MEDIA_DA; 378 fallthrough; 379 case ICE_PHY_TYPE_LOW_1000BASE_KX: 380 case ICE_PHY_TYPE_LOW_2500BASE_KX: 381 case ICE_PHY_TYPE_LOW_2500BASE_X: 382 case ICE_PHY_TYPE_LOW_5GBASE_KR: 383 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 384 case ICE_PHY_TYPE_LOW_25GBASE_KR: 385 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 386 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 387 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 388 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 389 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 390 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 391 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 392 return ICE_MEDIA_BACKPLANE; 393 } 394 } else { 395 switch (hw_link_info->phy_type_high) { 396 case ICE_PHY_TYPE_HIGH_100G_AUI2: 397 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 398 if (ice_is_media_cage_present(pi)) 399 return ICE_MEDIA_DA; 400 fallthrough; 401 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 402 return ICE_MEDIA_BACKPLANE; 403 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 404 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 405 return ICE_MEDIA_FIBER; 406 } 407 } 408 return ICE_MEDIA_UNKNOWN; 409 } 410 411 /** 412 * ice_aq_get_link_info 413 * @pi: port information structure 414 * @ena_lse: enable/disable LinkStatusEvent reporting 415 * @link: pointer to link status structure - optional 416 * @cd: pointer to command details structure or NULL 417 * 418 * Get Link Status (0x607). Returns the link status of the adapter. 419 */ 420 int 421 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 422 struct ice_link_status *link, struct ice_sq_cd *cd) 423 { 424 struct ice_aqc_get_link_status_data link_data = { 0 }; 425 struct ice_aqc_get_link_status *resp; 426 struct ice_link_status *li_old, *li; 427 enum ice_media_type *hw_media_type; 428 struct ice_fc_info *hw_fc_info; 429 bool tx_pause, rx_pause; 430 struct ice_aq_desc desc; 431 struct ice_hw *hw; 432 u16 cmd_flags; 433 int status; 434 435 if (!pi) 436 return -EINVAL; 437 hw = pi->hw; 438 li_old = &pi->phy.link_info_old; 439 hw_media_type = &pi->phy.media_type; 440 li = &pi->phy.link_info; 441 hw_fc_info = &pi->fc; 442 443 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 444 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 445 resp = &desc.params.get_link_status; 446 resp->cmd_flags = cpu_to_le16(cmd_flags); 447 resp->lport_num = pi->lport; 448 449 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 450 451 if (status) 452 return status; 453 454 /* save off old link status information */ 455 *li_old = *li; 456 457 /* update current link status information */ 458 li->link_speed = le16_to_cpu(link_data.link_speed); 459 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 460 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 461 *hw_media_type = ice_get_media_type(pi); 462 li->link_info = link_data.link_info; 463 li->link_cfg_err = link_data.link_cfg_err; 464 li->an_info = link_data.an_info; 465 li->ext_info = link_data.ext_info; 466 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 467 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 468 li->topo_media_conflict = link_data.topo_media_conflict; 469 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 470 ICE_AQ_CFG_PACING_TYPE_M); 471 472 /* update fc info */ 473 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 474 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 475 if (tx_pause && rx_pause) 476 hw_fc_info->current_mode = ICE_FC_FULL; 477 else if (tx_pause) 478 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 479 else if (rx_pause) 480 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 481 else 482 hw_fc_info->current_mode = ICE_FC_NONE; 483 484 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 485 486 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 487 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 488 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 489 (unsigned long long)li->phy_type_low); 490 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 491 (unsigned long long)li->phy_type_high); 492 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 493 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 494 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); 495 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 496 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 497 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 498 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 499 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 500 li->max_frame_size); 501 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 502 503 /* save link status information */ 504 if (link) 505 *link = *li; 506 507 /* flag cleared so calling functions don't call AQ again */ 508 pi->phy.get_link_info = false; 509 510 return 0; 511 } 512 513 /** 514 * ice_fill_tx_timer_and_fc_thresh 515 * @hw: pointer to the HW struct 516 * @cmd: pointer to MAC cfg structure 517 * 518 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 519 * descriptor 520 */ 521 static void 522 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 523 struct ice_aqc_set_mac_cfg *cmd) 524 { 525 u16 fc_thres_val, tx_timer_val; 526 u32 val; 527 528 /* We read back the transmit timer and FC threshold value of 529 * LFC. Thus, we will use index = 530 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 531 * 532 * Also, because we are operating on transmit timer and FC 533 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 534 */ 535 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 536 537 /* Retrieve the transmit timer */ 538 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 539 tx_timer_val = val & 540 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 541 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val); 542 543 /* Retrieve the FC threshold */ 544 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 545 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 546 547 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val); 548 } 549 550 /** 551 * ice_aq_set_mac_cfg 552 * @hw: pointer to the HW struct 553 * @max_frame_size: Maximum Frame Size to be supported 554 * @cd: pointer to command details structure or NULL 555 * 556 * Set MAC configuration (0x0603) 557 */ 558 int 559 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 560 { 561 struct ice_aqc_set_mac_cfg *cmd; 562 struct ice_aq_desc desc; 563 564 cmd = &desc.params.set_mac_cfg; 565 566 if (max_frame_size == 0) 567 return -EINVAL; 568 569 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 570 571 cmd->max_frame_size = cpu_to_le16(max_frame_size); 572 573 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 574 575 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 576 } 577 578 /** 579 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 580 * @hw: pointer to the HW struct 581 */ 582 static int ice_init_fltr_mgmt_struct(struct ice_hw *hw) 583 { 584 struct ice_switch_info *sw; 585 int status; 586 587 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 588 sizeof(*hw->switch_info), GFP_KERNEL); 589 sw = hw->switch_info; 590 591 if (!sw) 592 return -ENOMEM; 593 594 INIT_LIST_HEAD(&sw->vsi_list_map_head); 595 sw->prof_res_bm_init = 0; 596 597 status = ice_init_def_sw_recp(hw); 598 if (status) { 599 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 600 return status; 601 } 602 return 0; 603 } 604 605 /** 606 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 607 * @hw: pointer to the HW struct 608 */ 609 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 610 { 611 struct ice_switch_info *sw = hw->switch_info; 612 struct ice_vsi_list_map_info *v_pos_map; 613 struct ice_vsi_list_map_info *v_tmp_map; 614 struct ice_sw_recipe *recps; 615 u8 i; 616 617 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 618 list_entry) { 619 list_del(&v_pos_map->list_entry); 620 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 621 } 622 recps = sw->recp_list; 623 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 624 struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 625 626 recps[i].root_rid = i; 627 list_for_each_entry_safe(rg_entry, tmprg_entry, 628 &recps[i].rg_list, l_entry) { 629 list_del(&rg_entry->l_entry); 630 devm_kfree(ice_hw_to_dev(hw), rg_entry); 631 } 632 633 if (recps[i].adv_rule) { 634 struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 635 struct ice_adv_fltr_mgmt_list_entry *lst_itr; 636 637 mutex_destroy(&recps[i].filt_rule_lock); 638 list_for_each_entry_safe(lst_itr, tmp_entry, 639 &recps[i].filt_rules, 640 list_entry) { 641 list_del(&lst_itr->list_entry); 642 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); 643 devm_kfree(ice_hw_to_dev(hw), lst_itr); 644 } 645 } else { 646 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 647 648 mutex_destroy(&recps[i].filt_rule_lock); 649 list_for_each_entry_safe(lst_itr, tmp_entry, 650 &recps[i].filt_rules, 651 list_entry) { 652 list_del(&lst_itr->list_entry); 653 devm_kfree(ice_hw_to_dev(hw), lst_itr); 654 } 655 } 656 if (recps[i].root_buf) 657 devm_kfree(ice_hw_to_dev(hw), recps[i].root_buf); 658 } 659 ice_rm_all_sw_replay_rule_info(hw); 660 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 661 devm_kfree(ice_hw_to_dev(hw), sw); 662 } 663 664 /** 665 * ice_get_fw_log_cfg - get FW logging configuration 666 * @hw: pointer to the HW struct 667 */ 668 static int ice_get_fw_log_cfg(struct ice_hw *hw) 669 { 670 struct ice_aq_desc desc; 671 __le16 *config; 672 int status; 673 u16 size; 674 675 size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX; 676 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL); 677 if (!config) 678 return -ENOMEM; 679 680 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 681 682 status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 683 if (!status) { 684 u16 i; 685 686 /* Save FW logging information into the HW structure */ 687 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 688 u16 v, m, flgs; 689 690 v = le16_to_cpu(config[i]); 691 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 692 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 693 694 if (m < ICE_AQC_FW_LOG_ID_MAX) 695 hw->fw_log.evnts[m].cur = flgs; 696 } 697 } 698 699 devm_kfree(ice_hw_to_dev(hw), config); 700 701 return status; 702 } 703 704 /** 705 * ice_cfg_fw_log - configure FW logging 706 * @hw: pointer to the HW struct 707 * @enable: enable certain FW logging events if true, disable all if false 708 * 709 * This function enables/disables the FW logging via Rx CQ events and a UART 710 * port based on predetermined configurations. FW logging via the Rx CQ can be 711 * enabled/disabled for individual PF's. However, FW logging via the UART can 712 * only be enabled/disabled for all PFs on the same device. 713 * 714 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 715 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 716 * before initializing the device. 717 * 718 * When re/configuring FW logging, callers need to update the "cfg" elements of 719 * the hw->fw_log.evnts array with the desired logging event configurations for 720 * modules of interest. When disabling FW logging completely, the callers can 721 * just pass false in the "enable" parameter. On completion, the function will 722 * update the "cur" element of the hw->fw_log.evnts array with the resulting 723 * logging event configurations of the modules that are being re/configured. FW 724 * logging modules that are not part of a reconfiguration operation retain their 725 * previous states. 726 * 727 * Before resetting the device, it is recommended that the driver disables FW 728 * logging before shutting down the control queue. When disabling FW logging 729 * ("enable" = false), the latest configurations of FW logging events stored in 730 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 731 * a device reset. 732 * 733 * When enabling FW logging to emit log messages via the Rx CQ during the 734 * device's initialization phase, a mechanism alternative to interrupt handlers 735 * needs to be used to extract FW log messages from the Rx CQ periodically and 736 * to prevent the Rx CQ from being full and stalling other types of control 737 * messages from FW to SW. Interrupts are typically disabled during the device's 738 * initialization phase. 739 */ 740 static int ice_cfg_fw_log(struct ice_hw *hw, bool enable) 741 { 742 struct ice_aqc_fw_logging *cmd; 743 u16 i, chgs = 0, len = 0; 744 struct ice_aq_desc desc; 745 __le16 *data = NULL; 746 u8 actv_evnts = 0; 747 void *buf = NULL; 748 int status = 0; 749 750 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 751 return 0; 752 753 /* Disable FW logging only when the control queue is still responsive */ 754 if (!enable && 755 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 756 return 0; 757 758 /* Get current FW log settings */ 759 status = ice_get_fw_log_cfg(hw); 760 if (status) 761 return status; 762 763 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 764 cmd = &desc.params.fw_logging; 765 766 /* Indicate which controls are valid */ 767 if (hw->fw_log.cq_en) 768 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 769 770 if (hw->fw_log.uart_en) 771 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 772 773 if (enable) { 774 /* Fill in an array of entries with FW logging modules and 775 * logging events being reconfigured. 776 */ 777 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 778 u16 val; 779 780 /* Keep track of enabled event types */ 781 actv_evnts |= hw->fw_log.evnts[i].cfg; 782 783 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 784 continue; 785 786 if (!data) { 787 data = devm_kcalloc(ice_hw_to_dev(hw), 788 ICE_AQC_FW_LOG_ID_MAX, 789 sizeof(*data), 790 GFP_KERNEL); 791 if (!data) 792 return -ENOMEM; 793 } 794 795 val = i << ICE_AQC_FW_LOG_ID_S; 796 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 797 data[chgs++] = cpu_to_le16(val); 798 } 799 800 /* Only enable FW logging if at least one module is specified. 801 * If FW logging is currently enabled but all modules are not 802 * enabled to emit log messages, disable FW logging altogether. 803 */ 804 if (actv_evnts) { 805 /* Leave if there is effectively no change */ 806 if (!chgs) 807 goto out; 808 809 if (hw->fw_log.cq_en) 810 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 811 812 if (hw->fw_log.uart_en) 813 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 814 815 buf = data; 816 len = sizeof(*data) * chgs; 817 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 818 } 819 } 820 821 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 822 if (!status) { 823 /* Update the current configuration to reflect events enabled. 824 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 825 * logging mode is enabled for the device. They do not reflect 826 * actual modules being enabled to emit log messages. So, their 827 * values remain unchanged even when all modules are disabled. 828 */ 829 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 830 831 hw->fw_log.actv_evnts = actv_evnts; 832 for (i = 0; i < cnt; i++) { 833 u16 v, m; 834 835 if (!enable) { 836 /* When disabling all FW logging events as part 837 * of device's de-initialization, the original 838 * configurations are retained, and can be used 839 * to reconfigure FW logging later if the device 840 * is re-initialized. 841 */ 842 hw->fw_log.evnts[i].cur = 0; 843 continue; 844 } 845 846 v = le16_to_cpu(data[i]); 847 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 848 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 849 } 850 } 851 852 out: 853 if (data) 854 devm_kfree(ice_hw_to_dev(hw), data); 855 856 return status; 857 } 858 859 /** 860 * ice_output_fw_log 861 * @hw: pointer to the HW struct 862 * @desc: pointer to the AQ message descriptor 863 * @buf: pointer to the buffer accompanying the AQ message 864 * 865 * Formats a FW Log message and outputs it via the standard driver logs. 866 */ 867 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 868 { 869 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 870 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 871 le16_to_cpu(desc->datalen)); 872 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 873 } 874 875 /** 876 * ice_get_itr_intrl_gran 877 * @hw: pointer to the HW struct 878 * 879 * Determines the ITR/INTRL granularities based on the maximum aggregate 880 * bandwidth according to the device's configuration during power-on. 881 */ 882 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 883 { 884 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 885 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 886 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 887 888 switch (max_agg_bw) { 889 case ICE_MAX_AGG_BW_200G: 890 case ICE_MAX_AGG_BW_100G: 891 case ICE_MAX_AGG_BW_50G: 892 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 893 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 894 break; 895 case ICE_MAX_AGG_BW_25G: 896 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 897 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 898 break; 899 } 900 } 901 902 /** 903 * ice_init_hw - main hardware initialization routine 904 * @hw: pointer to the hardware structure 905 */ 906 int ice_init_hw(struct ice_hw *hw) 907 { 908 struct ice_aqc_get_phy_caps_data *pcaps; 909 u16 mac_buf_len; 910 void *mac_buf; 911 int status; 912 913 /* Set MAC type based on DeviceID */ 914 status = ice_set_mac_type(hw); 915 if (status) 916 return status; 917 918 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 919 PF_FUNC_RID_FUNC_NUM_M) >> 920 PF_FUNC_RID_FUNC_NUM_S; 921 922 status = ice_reset(hw, ICE_RESET_PFR); 923 if (status) 924 return status; 925 926 ice_get_itr_intrl_gran(hw); 927 928 status = ice_create_all_ctrlq(hw); 929 if (status) 930 goto err_unroll_cqinit; 931 932 /* Enable FW logging. Not fatal if this fails. */ 933 status = ice_cfg_fw_log(hw, true); 934 if (status) 935 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 936 937 status = ice_clear_pf_cfg(hw); 938 if (status) 939 goto err_unroll_cqinit; 940 941 /* Set bit to enable Flow Director filters */ 942 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 943 INIT_LIST_HEAD(&hw->fdir_list_head); 944 945 ice_clear_pxe_mode(hw); 946 947 status = ice_init_nvm(hw); 948 if (status) 949 goto err_unroll_cqinit; 950 951 status = ice_get_caps(hw); 952 if (status) 953 goto err_unroll_cqinit; 954 955 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 956 sizeof(*hw->port_info), GFP_KERNEL); 957 if (!hw->port_info) { 958 status = -ENOMEM; 959 goto err_unroll_cqinit; 960 } 961 962 /* set the back pointer to HW */ 963 hw->port_info->hw = hw; 964 965 /* Initialize port_info struct with switch configuration data */ 966 status = ice_get_initial_sw_cfg(hw); 967 if (status) 968 goto err_unroll_alloc; 969 970 hw->evb_veb = true; 971 972 /* Query the allocated resources for Tx scheduler */ 973 status = ice_sched_query_res_alloc(hw); 974 if (status) { 975 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 976 goto err_unroll_alloc; 977 } 978 ice_sched_get_psm_clk_freq(hw); 979 980 /* Initialize port_info struct with scheduler data */ 981 status = ice_sched_init_port(hw->port_info); 982 if (status) 983 goto err_unroll_sched; 984 985 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 986 if (!pcaps) { 987 status = -ENOMEM; 988 goto err_unroll_sched; 989 } 990 991 /* Initialize port_info struct with PHY capabilities */ 992 status = ice_aq_get_phy_caps(hw->port_info, false, 993 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 994 NULL); 995 devm_kfree(ice_hw_to_dev(hw), pcaps); 996 if (status) 997 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 998 status); 999 1000 /* Initialize port_info struct with link information */ 1001 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 1002 if (status) 1003 goto err_unroll_sched; 1004 1005 /* need a valid SW entry point to build a Tx tree */ 1006 if (!hw->sw_entry_point_layer) { 1007 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 1008 status = -EIO; 1009 goto err_unroll_sched; 1010 } 1011 INIT_LIST_HEAD(&hw->agg_list); 1012 /* Initialize max burst size */ 1013 if (!hw->max_burst_size) 1014 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 1015 1016 status = ice_init_fltr_mgmt_struct(hw); 1017 if (status) 1018 goto err_unroll_sched; 1019 1020 /* Get MAC information */ 1021 /* A single port can report up to two (LAN and WoL) addresses */ 1022 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 1023 sizeof(struct ice_aqc_manage_mac_read_resp), 1024 GFP_KERNEL); 1025 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 1026 1027 if (!mac_buf) { 1028 status = -ENOMEM; 1029 goto err_unroll_fltr_mgmt_struct; 1030 } 1031 1032 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 1033 devm_kfree(ice_hw_to_dev(hw), mac_buf); 1034 1035 if (status) 1036 goto err_unroll_fltr_mgmt_struct; 1037 /* enable jumbo frame support at MAC level */ 1038 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 1039 if (status) 1040 goto err_unroll_fltr_mgmt_struct; 1041 /* Obtain counter base index which would be used by flow director */ 1042 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 1043 if (status) 1044 goto err_unroll_fltr_mgmt_struct; 1045 status = ice_init_hw_tbls(hw); 1046 if (status) 1047 goto err_unroll_fltr_mgmt_struct; 1048 mutex_init(&hw->tnl_lock); 1049 return 0; 1050 1051 err_unroll_fltr_mgmt_struct: 1052 ice_cleanup_fltr_mgmt_struct(hw); 1053 err_unroll_sched: 1054 ice_sched_cleanup_all(hw); 1055 err_unroll_alloc: 1056 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1057 err_unroll_cqinit: 1058 ice_destroy_all_ctrlq(hw); 1059 return status; 1060 } 1061 1062 /** 1063 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1064 * @hw: pointer to the hardware structure 1065 * 1066 * This should be called only during nominal operation, not as a result of 1067 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1068 * applicable initializations if it fails for any reason. 1069 */ 1070 void ice_deinit_hw(struct ice_hw *hw) 1071 { 1072 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1073 ice_cleanup_fltr_mgmt_struct(hw); 1074 1075 ice_sched_cleanup_all(hw); 1076 ice_sched_clear_agg(hw); 1077 ice_free_seg(hw); 1078 ice_free_hw_tbls(hw); 1079 mutex_destroy(&hw->tnl_lock); 1080 1081 if (hw->port_info) { 1082 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1083 hw->port_info = NULL; 1084 } 1085 1086 /* Attempt to disable FW logging before shutting down control queues */ 1087 ice_cfg_fw_log(hw, false); 1088 ice_destroy_all_ctrlq(hw); 1089 1090 /* Clear VSI contexts if not already cleared */ 1091 ice_clear_all_vsi_ctx(hw); 1092 } 1093 1094 /** 1095 * ice_check_reset - Check to see if a global reset is complete 1096 * @hw: pointer to the hardware structure 1097 */ 1098 int ice_check_reset(struct ice_hw *hw) 1099 { 1100 u32 cnt, reg = 0, grst_timeout, uld_mask; 1101 1102 /* Poll for Device Active state in case a recent CORER, GLOBR, 1103 * or EMPR has occurred. The grst delay value is in 100ms units. 1104 * Add 1sec for outstanding AQ commands that can take a long time. 1105 */ 1106 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1107 GLGEN_RSTCTL_GRSTDEL_S) + 10; 1108 1109 for (cnt = 0; cnt < grst_timeout; cnt++) { 1110 mdelay(100); 1111 reg = rd32(hw, GLGEN_RSTAT); 1112 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1113 break; 1114 } 1115 1116 if (cnt == grst_timeout) { 1117 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1118 return -EIO; 1119 } 1120 1121 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1122 GLNVM_ULD_PCIER_DONE_1_M |\ 1123 GLNVM_ULD_CORER_DONE_M |\ 1124 GLNVM_ULD_GLOBR_DONE_M |\ 1125 GLNVM_ULD_POR_DONE_M |\ 1126 GLNVM_ULD_POR_DONE_1_M |\ 1127 GLNVM_ULD_PCIER_DONE_2_M) 1128 1129 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1130 GLNVM_ULD_PE_DONE_M : 0); 1131 1132 /* Device is Active; check Global Reset processes are done */ 1133 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1134 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1135 if (reg == uld_mask) { 1136 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1137 break; 1138 } 1139 mdelay(10); 1140 } 1141 1142 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1143 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1144 reg); 1145 return -EIO; 1146 } 1147 1148 return 0; 1149 } 1150 1151 /** 1152 * ice_pf_reset - Reset the PF 1153 * @hw: pointer to the hardware structure 1154 * 1155 * If a global reset has been triggered, this function checks 1156 * for its completion and then issues the PF reset 1157 */ 1158 static int ice_pf_reset(struct ice_hw *hw) 1159 { 1160 u32 cnt, reg; 1161 1162 /* If at function entry a global reset was already in progress, i.e. 1163 * state is not 'device active' or any of the reset done bits are not 1164 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1165 * global reset is done. 1166 */ 1167 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1168 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1169 /* poll on global reset currently in progress until done */ 1170 if (ice_check_reset(hw)) 1171 return -EIO; 1172 1173 return 0; 1174 } 1175 1176 /* Reset the PF */ 1177 reg = rd32(hw, PFGEN_CTRL); 1178 1179 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1180 1181 /* Wait for the PFR to complete. The wait time is the global config lock 1182 * timeout plus the PFR timeout which will account for a possible reset 1183 * that is occurring during a download package operation. 1184 */ 1185 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1186 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1187 reg = rd32(hw, PFGEN_CTRL); 1188 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1189 break; 1190 1191 mdelay(1); 1192 } 1193 1194 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1195 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1196 return -EIO; 1197 } 1198 1199 return 0; 1200 } 1201 1202 /** 1203 * ice_reset - Perform different types of reset 1204 * @hw: pointer to the hardware structure 1205 * @req: reset request 1206 * 1207 * This function triggers a reset as specified by the req parameter. 1208 * 1209 * Note: 1210 * If anything other than a PF reset is triggered, PXE mode is restored. 1211 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1212 * interface has been restored in the rebuild flow. 1213 */ 1214 int ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1215 { 1216 u32 val = 0; 1217 1218 switch (req) { 1219 case ICE_RESET_PFR: 1220 return ice_pf_reset(hw); 1221 case ICE_RESET_CORER: 1222 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1223 val = GLGEN_RTRIG_CORER_M; 1224 break; 1225 case ICE_RESET_GLOBR: 1226 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1227 val = GLGEN_RTRIG_GLOBR_M; 1228 break; 1229 default: 1230 return -EINVAL; 1231 } 1232 1233 val |= rd32(hw, GLGEN_RTRIG); 1234 wr32(hw, GLGEN_RTRIG, val); 1235 ice_flush(hw); 1236 1237 /* wait for the FW to be ready */ 1238 return ice_check_reset(hw); 1239 } 1240 1241 /** 1242 * ice_copy_rxq_ctx_to_hw 1243 * @hw: pointer to the hardware structure 1244 * @ice_rxq_ctx: pointer to the rxq context 1245 * @rxq_index: the index of the Rx queue 1246 * 1247 * Copies rxq context from dense structure to HW register space 1248 */ 1249 static int 1250 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1251 { 1252 u8 i; 1253 1254 if (!ice_rxq_ctx) 1255 return -EINVAL; 1256 1257 if (rxq_index > QRX_CTRL_MAX_INDEX) 1258 return -EINVAL; 1259 1260 /* Copy each dword separately to HW */ 1261 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1262 wr32(hw, QRX_CONTEXT(i, rxq_index), 1263 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1264 1265 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1266 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1267 } 1268 1269 return 0; 1270 } 1271 1272 /* LAN Rx Queue Context */ 1273 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1274 /* Field Width LSB */ 1275 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1276 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1277 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1278 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1279 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1280 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1281 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1282 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1283 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1284 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1285 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1286 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1287 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1288 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1289 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1290 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1291 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1292 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1293 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1294 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1295 { 0 } 1296 }; 1297 1298 /** 1299 * ice_write_rxq_ctx 1300 * @hw: pointer to the hardware structure 1301 * @rlan_ctx: pointer to the rxq context 1302 * @rxq_index: the index of the Rx queue 1303 * 1304 * Converts rxq context from sparse to dense structure and then writes 1305 * it to HW register space and enables the hardware to prefetch descriptors 1306 * instead of only fetching them on demand 1307 */ 1308 int 1309 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1310 u32 rxq_index) 1311 { 1312 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1313 1314 if (!rlan_ctx) 1315 return -EINVAL; 1316 1317 rlan_ctx->prefena = 1; 1318 1319 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1320 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1321 } 1322 1323 /* LAN Tx Queue Context */ 1324 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1325 /* Field Width LSB */ 1326 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1327 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1328 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1329 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1330 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1331 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1332 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1333 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1334 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1335 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1336 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1337 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1338 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1339 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1340 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1341 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1342 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1343 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1344 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1345 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1346 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1347 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1348 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1349 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1350 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1351 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1352 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1353 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1354 { 0 } 1355 }; 1356 1357 /* Sideband Queue command wrappers */ 1358 1359 /** 1360 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue 1361 * @hw: pointer to the HW struct 1362 * @desc: descriptor describing the command 1363 * @buf: buffer to use for indirect commands (NULL for direct commands) 1364 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1365 * @cd: pointer to command details structure 1366 */ 1367 static int 1368 ice_sbq_send_cmd(struct ice_hw *hw, struct ice_sbq_cmd_desc *desc, 1369 void *buf, u16 buf_size, struct ice_sq_cd *cd) 1370 { 1371 return ice_sq_send_cmd(hw, ice_get_sbq(hw), 1372 (struct ice_aq_desc *)desc, buf, buf_size, cd); 1373 } 1374 1375 /** 1376 * ice_sbq_rw_reg - Fill Sideband Queue command 1377 * @hw: pointer to the HW struct 1378 * @in: message info to be filled in descriptor 1379 */ 1380 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in) 1381 { 1382 struct ice_sbq_cmd_desc desc = {0}; 1383 struct ice_sbq_msg_req msg = {0}; 1384 u16 msg_len; 1385 int status; 1386 1387 msg_len = sizeof(msg); 1388 1389 msg.dest_dev = in->dest_dev; 1390 msg.opcode = in->opcode; 1391 msg.flags = ICE_SBQ_MSG_FLAGS; 1392 msg.sbe_fbe = ICE_SBQ_MSG_SBE_FBE; 1393 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); 1394 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); 1395 1396 if (in->opcode) 1397 msg.data = cpu_to_le32(in->data); 1398 else 1399 /* data read comes back in completion, so shorten the struct by 1400 * sizeof(msg.data) 1401 */ 1402 msg_len -= sizeof(msg.data); 1403 1404 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 1405 desc.opcode = cpu_to_le16(ice_sbq_opc_neigh_dev_req); 1406 desc.param0.cmd_len = cpu_to_le16(msg_len); 1407 status = ice_sbq_send_cmd(hw, &desc, &msg, msg_len, NULL); 1408 if (!status && !in->opcode) 1409 in->data = le32_to_cpu 1410 (((struct ice_sbq_msg_cmpl *)&msg)->data); 1411 return status; 1412 } 1413 1414 /* FW Admin Queue command wrappers */ 1415 1416 /* Software lock/mutex that is meant to be held while the Global Config Lock 1417 * in firmware is acquired by the software to prevent most (but not all) types 1418 * of AQ commands from being sent to FW 1419 */ 1420 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1421 1422 /** 1423 * ice_should_retry_sq_send_cmd 1424 * @opcode: AQ opcode 1425 * 1426 * Decide if we should retry the send command routine for the ATQ, depending 1427 * on the opcode. 1428 */ 1429 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1430 { 1431 switch (opcode) { 1432 case ice_aqc_opc_get_link_topo: 1433 case ice_aqc_opc_lldp_stop: 1434 case ice_aqc_opc_lldp_start: 1435 case ice_aqc_opc_lldp_filter_ctrl: 1436 return true; 1437 } 1438 1439 return false; 1440 } 1441 1442 /** 1443 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1444 * @hw: pointer to the HW struct 1445 * @cq: pointer to the specific Control queue 1446 * @desc: prefilled descriptor describing the command 1447 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1448 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1449 * @cd: pointer to command details structure 1450 * 1451 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1452 * Queue if the EBUSY AQ error is returned. 1453 */ 1454 static int 1455 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1456 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1457 struct ice_sq_cd *cd) 1458 { 1459 struct ice_aq_desc desc_cpy; 1460 bool is_cmd_for_retry; 1461 u8 *buf_cpy = NULL; 1462 u8 idx = 0; 1463 u16 opcode; 1464 int status; 1465 1466 opcode = le16_to_cpu(desc->opcode); 1467 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1468 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1469 1470 if (is_cmd_for_retry) { 1471 if (buf) { 1472 buf_cpy = kzalloc(buf_size, GFP_KERNEL); 1473 if (!buf_cpy) 1474 return -ENOMEM; 1475 } 1476 1477 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1478 } 1479 1480 do { 1481 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1482 1483 if (!is_cmd_for_retry || !status || 1484 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1485 break; 1486 1487 if (buf_cpy) 1488 memcpy(buf, buf_cpy, buf_size); 1489 1490 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1491 1492 mdelay(ICE_SQ_SEND_DELAY_TIME_MS); 1493 1494 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1495 1496 kfree(buf_cpy); 1497 1498 return status; 1499 } 1500 1501 /** 1502 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1503 * @hw: pointer to the HW struct 1504 * @desc: descriptor describing the command 1505 * @buf: buffer to use for indirect commands (NULL for direct commands) 1506 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1507 * @cd: pointer to command details structure 1508 * 1509 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1510 */ 1511 int 1512 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1513 u16 buf_size, struct ice_sq_cd *cd) 1514 { 1515 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1516 bool lock_acquired = false; 1517 int status; 1518 1519 /* When a package download is in process (i.e. when the firmware's 1520 * Global Configuration Lock resource is held), only the Download 1521 * Package, Get Version, Get Package Info List, Upload Section, 1522 * Update Package, Set Port Parameters, Get/Set VLAN Mode Parameters, 1523 * Add Recipe, Set Recipes to Profile Association, Get Recipe, and Get 1524 * Recipes to Profile Association, and Release Resource (with resource 1525 * ID set to Global Config Lock) AdminQ commands are allowed; all others 1526 * must block until the package download completes and the Global Config 1527 * Lock is released. See also ice_acquire_global_cfg_lock(). 1528 */ 1529 switch (le16_to_cpu(desc->opcode)) { 1530 case ice_aqc_opc_download_pkg: 1531 case ice_aqc_opc_get_pkg_info_list: 1532 case ice_aqc_opc_get_ver: 1533 case ice_aqc_opc_upload_section: 1534 case ice_aqc_opc_update_pkg: 1535 case ice_aqc_opc_set_port_params: 1536 case ice_aqc_opc_get_vlan_mode_parameters: 1537 case ice_aqc_opc_set_vlan_mode_parameters: 1538 case ice_aqc_opc_add_recipe: 1539 case ice_aqc_opc_recipe_to_profile: 1540 case ice_aqc_opc_get_recipe: 1541 case ice_aqc_opc_get_recipe_to_profile: 1542 break; 1543 case ice_aqc_opc_release_res: 1544 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1545 break; 1546 fallthrough; 1547 default: 1548 mutex_lock(&ice_global_cfg_lock_sw); 1549 lock_acquired = true; 1550 break; 1551 } 1552 1553 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1554 if (lock_acquired) 1555 mutex_unlock(&ice_global_cfg_lock_sw); 1556 1557 return status; 1558 } 1559 1560 /** 1561 * ice_aq_get_fw_ver 1562 * @hw: pointer to the HW struct 1563 * @cd: pointer to command details structure or NULL 1564 * 1565 * Get the firmware version (0x0001) from the admin queue commands 1566 */ 1567 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1568 { 1569 struct ice_aqc_get_ver *resp; 1570 struct ice_aq_desc desc; 1571 int status; 1572 1573 resp = &desc.params.get_ver; 1574 1575 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1576 1577 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1578 1579 if (!status) { 1580 hw->fw_branch = resp->fw_branch; 1581 hw->fw_maj_ver = resp->fw_major; 1582 hw->fw_min_ver = resp->fw_minor; 1583 hw->fw_patch = resp->fw_patch; 1584 hw->fw_build = le32_to_cpu(resp->fw_build); 1585 hw->api_branch = resp->api_branch; 1586 hw->api_maj_ver = resp->api_major; 1587 hw->api_min_ver = resp->api_minor; 1588 hw->api_patch = resp->api_patch; 1589 } 1590 1591 return status; 1592 } 1593 1594 /** 1595 * ice_aq_send_driver_ver 1596 * @hw: pointer to the HW struct 1597 * @dv: driver's major, minor version 1598 * @cd: pointer to command details structure or NULL 1599 * 1600 * Send the driver version (0x0002) to the firmware 1601 */ 1602 int 1603 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1604 struct ice_sq_cd *cd) 1605 { 1606 struct ice_aqc_driver_ver *cmd; 1607 struct ice_aq_desc desc; 1608 u16 len; 1609 1610 cmd = &desc.params.driver_ver; 1611 1612 if (!dv) 1613 return -EINVAL; 1614 1615 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1616 1617 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1618 cmd->major_ver = dv->major_ver; 1619 cmd->minor_ver = dv->minor_ver; 1620 cmd->build_ver = dv->build_ver; 1621 cmd->subbuild_ver = dv->subbuild_ver; 1622 1623 len = 0; 1624 while (len < sizeof(dv->driver_string) && 1625 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1626 len++; 1627 1628 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1629 } 1630 1631 /** 1632 * ice_aq_q_shutdown 1633 * @hw: pointer to the HW struct 1634 * @unloading: is the driver unloading itself 1635 * 1636 * Tell the Firmware that we're shutting down the AdminQ and whether 1637 * or not the driver is unloading as well (0x0003). 1638 */ 1639 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1640 { 1641 struct ice_aqc_q_shutdown *cmd; 1642 struct ice_aq_desc desc; 1643 1644 cmd = &desc.params.q_shutdown; 1645 1646 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1647 1648 if (unloading) 1649 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1650 1651 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1652 } 1653 1654 /** 1655 * ice_aq_req_res 1656 * @hw: pointer to the HW struct 1657 * @res: resource ID 1658 * @access: access type 1659 * @sdp_number: resource number 1660 * @timeout: the maximum time in ms that the driver may hold the resource 1661 * @cd: pointer to command details structure or NULL 1662 * 1663 * Requests common resource using the admin queue commands (0x0008). 1664 * When attempting to acquire the Global Config Lock, the driver can 1665 * learn of three states: 1666 * 1) 0 - acquired lock, and can perform download package 1667 * 2) -EIO - did not get lock, driver should fail to load 1668 * 3) -EALREADY - did not get lock, but another driver has 1669 * successfully downloaded the package; the driver does 1670 * not have to download the package and can continue 1671 * loading 1672 * 1673 * Note that if the caller is in an acquire lock, perform action, release lock 1674 * phase of operation, it is possible that the FW may detect a timeout and issue 1675 * a CORER. In this case, the driver will receive a CORER interrupt and will 1676 * have to determine its cause. The calling thread that is handling this flow 1677 * will likely get an error propagated back to it indicating the Download 1678 * Package, Update Package or the Release Resource AQ commands timed out. 1679 */ 1680 static int 1681 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1682 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1683 struct ice_sq_cd *cd) 1684 { 1685 struct ice_aqc_req_res *cmd_resp; 1686 struct ice_aq_desc desc; 1687 int status; 1688 1689 cmd_resp = &desc.params.res_owner; 1690 1691 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1692 1693 cmd_resp->res_id = cpu_to_le16(res); 1694 cmd_resp->access_type = cpu_to_le16(access); 1695 cmd_resp->res_number = cpu_to_le32(sdp_number); 1696 cmd_resp->timeout = cpu_to_le32(*timeout); 1697 *timeout = 0; 1698 1699 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1700 1701 /* The completion specifies the maximum time in ms that the driver 1702 * may hold the resource in the Timeout field. 1703 */ 1704 1705 /* Global config lock response utilizes an additional status field. 1706 * 1707 * If the Global config lock resource is held by some other driver, the 1708 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1709 * and the timeout field indicates the maximum time the current owner 1710 * of the resource has to free it. 1711 */ 1712 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1713 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1714 *timeout = le32_to_cpu(cmd_resp->timeout); 1715 return 0; 1716 } else if (le16_to_cpu(cmd_resp->status) == 1717 ICE_AQ_RES_GLBL_IN_PROG) { 1718 *timeout = le32_to_cpu(cmd_resp->timeout); 1719 return -EIO; 1720 } else if (le16_to_cpu(cmd_resp->status) == 1721 ICE_AQ_RES_GLBL_DONE) { 1722 return -EALREADY; 1723 } 1724 1725 /* invalid FW response, force a timeout immediately */ 1726 *timeout = 0; 1727 return -EIO; 1728 } 1729 1730 /* If the resource is held by some other driver, the command completes 1731 * with a busy return value and the timeout field indicates the maximum 1732 * time the current owner of the resource has to free it. 1733 */ 1734 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1735 *timeout = le32_to_cpu(cmd_resp->timeout); 1736 1737 return status; 1738 } 1739 1740 /** 1741 * ice_aq_release_res 1742 * @hw: pointer to the HW struct 1743 * @res: resource ID 1744 * @sdp_number: resource number 1745 * @cd: pointer to command details structure or NULL 1746 * 1747 * release common resource using the admin queue commands (0x0009) 1748 */ 1749 static int 1750 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1751 struct ice_sq_cd *cd) 1752 { 1753 struct ice_aqc_req_res *cmd; 1754 struct ice_aq_desc desc; 1755 1756 cmd = &desc.params.res_owner; 1757 1758 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1759 1760 cmd->res_id = cpu_to_le16(res); 1761 cmd->res_number = cpu_to_le32(sdp_number); 1762 1763 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1764 } 1765 1766 /** 1767 * ice_acquire_res 1768 * @hw: pointer to the HW structure 1769 * @res: resource ID 1770 * @access: access type (read or write) 1771 * @timeout: timeout in milliseconds 1772 * 1773 * This function will attempt to acquire the ownership of a resource. 1774 */ 1775 int 1776 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1777 enum ice_aq_res_access_type access, u32 timeout) 1778 { 1779 #define ICE_RES_POLLING_DELAY_MS 10 1780 u32 delay = ICE_RES_POLLING_DELAY_MS; 1781 u32 time_left = timeout; 1782 int status; 1783 1784 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1785 1786 /* A return code of -EALREADY means that another driver has 1787 * previously acquired the resource and performed any necessary updates; 1788 * in this case the caller does not obtain the resource and has no 1789 * further work to do. 1790 */ 1791 if (status == -EALREADY) 1792 goto ice_acquire_res_exit; 1793 1794 if (status) 1795 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1796 1797 /* If necessary, poll until the current lock owner timeouts */ 1798 timeout = time_left; 1799 while (status && timeout && time_left) { 1800 mdelay(delay); 1801 timeout = (timeout > delay) ? timeout - delay : 0; 1802 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1803 1804 if (status == -EALREADY) 1805 /* lock free, but no work to do */ 1806 break; 1807 1808 if (!status) 1809 /* lock acquired */ 1810 break; 1811 } 1812 if (status && status != -EALREADY) 1813 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1814 1815 ice_acquire_res_exit: 1816 if (status == -EALREADY) { 1817 if (access == ICE_RES_WRITE) 1818 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1819 else 1820 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); 1821 } 1822 return status; 1823 } 1824 1825 /** 1826 * ice_release_res 1827 * @hw: pointer to the HW structure 1828 * @res: resource ID 1829 * 1830 * This function will release a resource using the proper Admin Command. 1831 */ 1832 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1833 { 1834 u32 total_delay = 0; 1835 int status; 1836 1837 status = ice_aq_release_res(hw, res, 0, NULL); 1838 1839 /* there are some rare cases when trying to release the resource 1840 * results in an admin queue timeout, so handle them correctly 1841 */ 1842 while ((status == -EIO) && (total_delay < hw->adminq.sq_cmd_timeout)) { 1843 mdelay(1); 1844 status = ice_aq_release_res(hw, res, 0, NULL); 1845 total_delay++; 1846 } 1847 } 1848 1849 /** 1850 * ice_aq_alloc_free_res - command to allocate/free resources 1851 * @hw: pointer to the HW struct 1852 * @num_entries: number of resource entries in buffer 1853 * @buf: Indirect buffer to hold data parameters and response 1854 * @buf_size: size of buffer for indirect commands 1855 * @opc: pass in the command opcode 1856 * @cd: pointer to command details structure or NULL 1857 * 1858 * Helper function to allocate/free resources using the admin queue commands 1859 */ 1860 int 1861 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1862 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1863 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1864 { 1865 struct ice_aqc_alloc_free_res_cmd *cmd; 1866 struct ice_aq_desc desc; 1867 1868 cmd = &desc.params.sw_res_ctrl; 1869 1870 if (!buf) 1871 return -EINVAL; 1872 1873 if (buf_size < flex_array_size(buf, elem, num_entries)) 1874 return -EINVAL; 1875 1876 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1877 1878 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1879 1880 cmd->num_entries = cpu_to_le16(num_entries); 1881 1882 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1883 } 1884 1885 /** 1886 * ice_alloc_hw_res - allocate resource 1887 * @hw: pointer to the HW struct 1888 * @type: type of resource 1889 * @num: number of resources to allocate 1890 * @btm: allocate from bottom 1891 * @res: pointer to array that will receive the resources 1892 */ 1893 int 1894 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1895 { 1896 struct ice_aqc_alloc_free_res_elem *buf; 1897 u16 buf_len; 1898 int status; 1899 1900 buf_len = struct_size(buf, elem, num); 1901 buf = kzalloc(buf_len, GFP_KERNEL); 1902 if (!buf) 1903 return -ENOMEM; 1904 1905 /* Prepare buffer to allocate resource. */ 1906 buf->num_elems = cpu_to_le16(num); 1907 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1908 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1909 if (btm) 1910 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1911 1912 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1913 ice_aqc_opc_alloc_res, NULL); 1914 if (status) 1915 goto ice_alloc_res_exit; 1916 1917 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 1918 1919 ice_alloc_res_exit: 1920 kfree(buf); 1921 return status; 1922 } 1923 1924 /** 1925 * ice_free_hw_res - free allocated HW resource 1926 * @hw: pointer to the HW struct 1927 * @type: type of resource to free 1928 * @num: number of resources 1929 * @res: pointer to array that contains the resources to free 1930 */ 1931 int ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1932 { 1933 struct ice_aqc_alloc_free_res_elem *buf; 1934 u16 buf_len; 1935 int status; 1936 1937 buf_len = struct_size(buf, elem, num); 1938 buf = kzalloc(buf_len, GFP_KERNEL); 1939 if (!buf) 1940 return -ENOMEM; 1941 1942 /* Prepare buffer to free resource. */ 1943 buf->num_elems = cpu_to_le16(num); 1944 buf->res_type = cpu_to_le16(type); 1945 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 1946 1947 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1948 ice_aqc_opc_free_res, NULL); 1949 if (status) 1950 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1951 1952 kfree(buf); 1953 return status; 1954 } 1955 1956 /** 1957 * ice_get_num_per_func - determine number of resources per PF 1958 * @hw: pointer to the HW structure 1959 * @max: value to be evenly split between each PF 1960 * 1961 * Determine the number of valid functions by going through the bitmap returned 1962 * from parsing capabilities and use this to calculate the number of resources 1963 * per PF based on the max value passed in. 1964 */ 1965 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1966 { 1967 u8 funcs; 1968 1969 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1970 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 1971 ICE_CAPS_VALID_FUNCS_M); 1972 1973 if (!funcs) 1974 return 0; 1975 1976 return max / funcs; 1977 } 1978 1979 /** 1980 * ice_parse_common_caps - parse common device/function capabilities 1981 * @hw: pointer to the HW struct 1982 * @caps: pointer to common capabilities structure 1983 * @elem: the capability element to parse 1984 * @prefix: message prefix for tracing capabilities 1985 * 1986 * Given a capability element, extract relevant details into the common 1987 * capability structure. 1988 * 1989 * Returns: true if the capability matches one of the common capability ids, 1990 * false otherwise. 1991 */ 1992 static bool 1993 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1994 struct ice_aqc_list_caps_elem *elem, const char *prefix) 1995 { 1996 u32 logical_id = le32_to_cpu(elem->logical_id); 1997 u32 phys_id = le32_to_cpu(elem->phys_id); 1998 u32 number = le32_to_cpu(elem->number); 1999 u16 cap = le16_to_cpu(elem->cap); 2000 bool found = true; 2001 2002 switch (cap) { 2003 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2004 caps->valid_functions = number; 2005 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 2006 caps->valid_functions); 2007 break; 2008 case ICE_AQC_CAPS_SRIOV: 2009 caps->sr_iov_1_1 = (number == 1); 2010 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 2011 caps->sr_iov_1_1); 2012 break; 2013 case ICE_AQC_CAPS_DCB: 2014 caps->dcb = (number == 1); 2015 caps->active_tc_bitmap = logical_id; 2016 caps->maxtc = phys_id; 2017 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 2018 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 2019 caps->active_tc_bitmap); 2020 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 2021 break; 2022 case ICE_AQC_CAPS_RSS: 2023 caps->rss_table_size = number; 2024 caps->rss_table_entry_width = logical_id; 2025 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 2026 caps->rss_table_size); 2027 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 2028 caps->rss_table_entry_width); 2029 break; 2030 case ICE_AQC_CAPS_RXQS: 2031 caps->num_rxq = number; 2032 caps->rxq_first_id = phys_id; 2033 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 2034 caps->num_rxq); 2035 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 2036 caps->rxq_first_id); 2037 break; 2038 case ICE_AQC_CAPS_TXQS: 2039 caps->num_txq = number; 2040 caps->txq_first_id = phys_id; 2041 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 2042 caps->num_txq); 2043 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 2044 caps->txq_first_id); 2045 break; 2046 case ICE_AQC_CAPS_MSIX: 2047 caps->num_msix_vectors = number; 2048 caps->msix_vector_first_id = phys_id; 2049 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 2050 caps->num_msix_vectors); 2051 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 2052 caps->msix_vector_first_id); 2053 break; 2054 case ICE_AQC_CAPS_PENDING_NVM_VER: 2055 caps->nvm_update_pending_nvm = true; 2056 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 2057 break; 2058 case ICE_AQC_CAPS_PENDING_OROM_VER: 2059 caps->nvm_update_pending_orom = true; 2060 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 2061 break; 2062 case ICE_AQC_CAPS_PENDING_NET_VER: 2063 caps->nvm_update_pending_netlist = true; 2064 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 2065 break; 2066 case ICE_AQC_CAPS_NVM_MGMT: 2067 caps->nvm_unified_update = 2068 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 2069 true : false; 2070 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 2071 caps->nvm_unified_update); 2072 break; 2073 case ICE_AQC_CAPS_RDMA: 2074 caps->rdma = (number == 1); 2075 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 2076 break; 2077 case ICE_AQC_CAPS_MAX_MTU: 2078 caps->max_mtu = number; 2079 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 2080 prefix, caps->max_mtu); 2081 break; 2082 case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: 2083 caps->pcie_reset_avoidance = (number > 0); 2084 ice_debug(hw, ICE_DBG_INIT, 2085 "%s: pcie_reset_avoidance = %d\n", prefix, 2086 caps->pcie_reset_avoidance); 2087 break; 2088 case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: 2089 caps->reset_restrict_support = (number == 1); 2090 ice_debug(hw, ICE_DBG_INIT, 2091 "%s: reset_restrict_support = %d\n", prefix, 2092 caps->reset_restrict_support); 2093 break; 2094 default: 2095 /* Not one of the recognized common capabilities */ 2096 found = false; 2097 } 2098 2099 return found; 2100 } 2101 2102 /** 2103 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 2104 * @hw: pointer to the HW structure 2105 * @caps: pointer to capabilities structure to fix 2106 * 2107 * Re-calculate the capabilities that are dependent on the number of physical 2108 * ports; i.e. some features are not supported or function differently on 2109 * devices with more than 4 ports. 2110 */ 2111 static void 2112 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 2113 { 2114 /* This assumes device capabilities are always scanned before function 2115 * capabilities during the initialization flow. 2116 */ 2117 if (hw->dev_caps.num_funcs > 4) { 2118 /* Max 4 TCs per port */ 2119 caps->maxtc = 4; 2120 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 2121 caps->maxtc); 2122 if (caps->rdma) { 2123 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 2124 caps->rdma = 0; 2125 } 2126 2127 /* print message only when processing device capabilities 2128 * during initialization. 2129 */ 2130 if (caps == &hw->dev_caps.common_cap) 2131 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 2132 } 2133 } 2134 2135 /** 2136 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 2137 * @hw: pointer to the HW struct 2138 * @func_p: pointer to function capabilities structure 2139 * @cap: pointer to the capability element to parse 2140 * 2141 * Extract function capabilities for ICE_AQC_CAPS_VF. 2142 */ 2143 static void 2144 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2145 struct ice_aqc_list_caps_elem *cap) 2146 { 2147 u32 logical_id = le32_to_cpu(cap->logical_id); 2148 u32 number = le32_to_cpu(cap->number); 2149 2150 func_p->num_allocd_vfs = number; 2151 func_p->vf_base_id = logical_id; 2152 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2153 func_p->num_allocd_vfs); 2154 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2155 func_p->vf_base_id); 2156 } 2157 2158 /** 2159 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2160 * @hw: pointer to the HW struct 2161 * @func_p: pointer to function capabilities structure 2162 * @cap: pointer to the capability element to parse 2163 * 2164 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2165 */ 2166 static void 2167 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2168 struct ice_aqc_list_caps_elem *cap) 2169 { 2170 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2171 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2172 le32_to_cpu(cap->number)); 2173 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2174 func_p->guar_num_vsi); 2175 } 2176 2177 /** 2178 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps 2179 * @hw: pointer to the HW struct 2180 * @func_p: pointer to function capabilities structure 2181 * @cap: pointer to the capability element to parse 2182 * 2183 * Extract function capabilities for ICE_AQC_CAPS_1588. 2184 */ 2185 static void 2186 ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2187 struct ice_aqc_list_caps_elem *cap) 2188 { 2189 struct ice_ts_func_info *info = &func_p->ts_func_info; 2190 u32 number = le32_to_cpu(cap->number); 2191 2192 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); 2193 func_p->common_cap.ieee_1588 = info->ena; 2194 2195 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); 2196 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); 2197 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); 2198 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); 2199 2200 info->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S; 2201 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); 2202 2203 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { 2204 info->time_ref = (enum ice_time_ref_freq)info->clk_freq; 2205 } else { 2206 /* Unknown clock frequency, so assume a (probably incorrect) 2207 * default to avoid out-of-bounds look ups of frequency 2208 * related information. 2209 */ 2210 ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n", 2211 info->clk_freq); 2212 info->time_ref = ICE_TIME_REF_FREQ_25_000; 2213 } 2214 2215 ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n", 2216 func_p->common_cap.ieee_1588); 2217 ice_debug(hw, ICE_DBG_INIT, "func caps: src_tmr_owned = %u\n", 2218 info->src_tmr_owned); 2219 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_ena = %u\n", 2220 info->tmr_ena); 2221 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_owned = %u\n", 2222 info->tmr_index_owned); 2223 ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n", 2224 info->tmr_index_assoc); 2225 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n", 2226 info->clk_freq); 2227 ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n", 2228 info->clk_src); 2229 } 2230 2231 /** 2232 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2233 * @hw: pointer to the HW struct 2234 * @func_p: pointer to function capabilities structure 2235 * 2236 * Extract function capabilities for ICE_AQC_CAPS_FD. 2237 */ 2238 static void 2239 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2240 { 2241 u32 reg_val, val; 2242 2243 reg_val = rd32(hw, GLQF_FD_SIZE); 2244 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2245 GLQF_FD_SIZE_FD_GSIZE_S; 2246 func_p->fd_fltr_guar = 2247 ice_get_num_per_func(hw, val); 2248 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2249 GLQF_FD_SIZE_FD_BSIZE_S; 2250 func_p->fd_fltr_best_effort = val; 2251 2252 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2253 func_p->fd_fltr_guar); 2254 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2255 func_p->fd_fltr_best_effort); 2256 } 2257 2258 /** 2259 * ice_parse_func_caps - Parse function capabilities 2260 * @hw: pointer to the HW struct 2261 * @func_p: pointer to function capabilities structure 2262 * @buf: buffer containing the function capability records 2263 * @cap_count: the number of capabilities 2264 * 2265 * Helper function to parse function (0x000A) capabilities list. For 2266 * capabilities shared between device and function, this relies on 2267 * ice_parse_common_caps. 2268 * 2269 * Loop through the list of provided capabilities and extract the relevant 2270 * data into the function capabilities structured. 2271 */ 2272 static void 2273 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2274 void *buf, u32 cap_count) 2275 { 2276 struct ice_aqc_list_caps_elem *cap_resp; 2277 u32 i; 2278 2279 cap_resp = buf; 2280 2281 memset(func_p, 0, sizeof(*func_p)); 2282 2283 for (i = 0; i < cap_count; i++) { 2284 u16 cap = le16_to_cpu(cap_resp[i].cap); 2285 bool found; 2286 2287 found = ice_parse_common_caps(hw, &func_p->common_cap, 2288 &cap_resp[i], "func caps"); 2289 2290 switch (cap) { 2291 case ICE_AQC_CAPS_VF: 2292 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2293 break; 2294 case ICE_AQC_CAPS_VSI: 2295 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2296 break; 2297 case ICE_AQC_CAPS_1588: 2298 ice_parse_1588_func_caps(hw, func_p, &cap_resp[i]); 2299 break; 2300 case ICE_AQC_CAPS_FD: 2301 ice_parse_fdir_func_caps(hw, func_p); 2302 break; 2303 default: 2304 /* Don't list common capabilities as unknown */ 2305 if (!found) 2306 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2307 i, cap); 2308 break; 2309 } 2310 } 2311 2312 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2313 } 2314 2315 /** 2316 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2317 * @hw: pointer to the HW struct 2318 * @dev_p: pointer to device capabilities structure 2319 * @cap: capability element to parse 2320 * 2321 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2322 */ 2323 static void 2324 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2325 struct ice_aqc_list_caps_elem *cap) 2326 { 2327 u32 number = le32_to_cpu(cap->number); 2328 2329 dev_p->num_funcs = hweight32(number); 2330 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2331 dev_p->num_funcs); 2332 } 2333 2334 /** 2335 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2336 * @hw: pointer to the HW struct 2337 * @dev_p: pointer to device capabilities structure 2338 * @cap: capability element to parse 2339 * 2340 * Parse ICE_AQC_CAPS_VF for device capabilities. 2341 */ 2342 static void 2343 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2344 struct ice_aqc_list_caps_elem *cap) 2345 { 2346 u32 number = le32_to_cpu(cap->number); 2347 2348 dev_p->num_vfs_exposed = number; 2349 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2350 dev_p->num_vfs_exposed); 2351 } 2352 2353 /** 2354 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2355 * @hw: pointer to the HW struct 2356 * @dev_p: pointer to device capabilities structure 2357 * @cap: capability element to parse 2358 * 2359 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2360 */ 2361 static void 2362 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2363 struct ice_aqc_list_caps_elem *cap) 2364 { 2365 u32 number = le32_to_cpu(cap->number); 2366 2367 dev_p->num_vsi_allocd_to_host = number; 2368 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2369 dev_p->num_vsi_allocd_to_host); 2370 } 2371 2372 /** 2373 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps 2374 * @hw: pointer to the HW struct 2375 * @dev_p: pointer to device capabilities structure 2376 * @cap: capability element to parse 2377 * 2378 * Parse ICE_AQC_CAPS_1588 for device capabilities. 2379 */ 2380 static void 2381 ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2382 struct ice_aqc_list_caps_elem *cap) 2383 { 2384 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; 2385 u32 logical_id = le32_to_cpu(cap->logical_id); 2386 u32 phys_id = le32_to_cpu(cap->phys_id); 2387 u32 number = le32_to_cpu(cap->number); 2388 2389 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); 2390 dev_p->common_cap.ieee_1588 = info->ena; 2391 2392 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; 2393 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); 2394 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); 2395 2396 info->tmr1_owner = (number & ICE_TS_TMR1_OWNR_M) >> ICE_TS_TMR1_OWNR_S; 2397 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); 2398 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); 2399 2400 info->ena_ports = logical_id; 2401 info->tmr_own_map = phys_id; 2402 2403 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n", 2404 dev_p->common_cap.ieee_1588); 2405 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owner = %u\n", 2406 info->tmr0_owner); 2407 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_owned = %u\n", 2408 info->tmr0_owned); 2409 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr0_ena = %u\n", 2410 info->tmr0_ena); 2411 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owner = %u\n", 2412 info->tmr1_owner); 2413 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_owned = %u\n", 2414 info->tmr1_owned); 2415 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n", 2416 info->tmr1_ena); 2417 ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n", 2418 info->ena_ports); 2419 ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n", 2420 info->tmr_own_map); 2421 } 2422 2423 /** 2424 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2425 * @hw: pointer to the HW struct 2426 * @dev_p: pointer to device capabilities structure 2427 * @cap: capability element to parse 2428 * 2429 * Parse ICE_AQC_CAPS_FD for device capabilities. 2430 */ 2431 static void 2432 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2433 struct ice_aqc_list_caps_elem *cap) 2434 { 2435 u32 number = le32_to_cpu(cap->number); 2436 2437 dev_p->num_flow_director_fltr = number; 2438 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2439 dev_p->num_flow_director_fltr); 2440 } 2441 2442 /** 2443 * ice_parse_dev_caps - Parse device capabilities 2444 * @hw: pointer to the HW struct 2445 * @dev_p: pointer to device capabilities structure 2446 * @buf: buffer containing the device capability records 2447 * @cap_count: the number of capabilities 2448 * 2449 * Helper device to parse device (0x000B) capabilities list. For 2450 * capabilities shared between device and function, this relies on 2451 * ice_parse_common_caps. 2452 * 2453 * Loop through the list of provided capabilities and extract the relevant 2454 * data into the device capabilities structured. 2455 */ 2456 static void 2457 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2458 void *buf, u32 cap_count) 2459 { 2460 struct ice_aqc_list_caps_elem *cap_resp; 2461 u32 i; 2462 2463 cap_resp = buf; 2464 2465 memset(dev_p, 0, sizeof(*dev_p)); 2466 2467 for (i = 0; i < cap_count; i++) { 2468 u16 cap = le16_to_cpu(cap_resp[i].cap); 2469 bool found; 2470 2471 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2472 &cap_resp[i], "dev caps"); 2473 2474 switch (cap) { 2475 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2476 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2477 break; 2478 case ICE_AQC_CAPS_VF: 2479 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2480 break; 2481 case ICE_AQC_CAPS_VSI: 2482 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2483 break; 2484 case ICE_AQC_CAPS_1588: 2485 ice_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]); 2486 break; 2487 case ICE_AQC_CAPS_FD: 2488 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2489 break; 2490 default: 2491 /* Don't list common capabilities as unknown */ 2492 if (!found) 2493 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2494 i, cap); 2495 break; 2496 } 2497 } 2498 2499 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2500 } 2501 2502 /** 2503 * ice_aq_list_caps - query function/device capabilities 2504 * @hw: pointer to the HW struct 2505 * @buf: a buffer to hold the capabilities 2506 * @buf_size: size of the buffer 2507 * @cap_count: if not NULL, set to the number of capabilities reported 2508 * @opc: capabilities type to discover, device or function 2509 * @cd: pointer to command details structure or NULL 2510 * 2511 * Get the function (0x000A) or device (0x000B) capabilities description from 2512 * firmware and store it in the buffer. 2513 * 2514 * If the cap_count pointer is not NULL, then it is set to the number of 2515 * capabilities firmware will report. Note that if the buffer size is too 2516 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2517 * cap_count will still be updated in this case. It is recommended that the 2518 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2519 * firmware could return) to avoid this. 2520 */ 2521 int 2522 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2523 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2524 { 2525 struct ice_aqc_list_caps *cmd; 2526 struct ice_aq_desc desc; 2527 int status; 2528 2529 cmd = &desc.params.get_cap; 2530 2531 if (opc != ice_aqc_opc_list_func_caps && 2532 opc != ice_aqc_opc_list_dev_caps) 2533 return -EINVAL; 2534 2535 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2536 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2537 2538 if (cap_count) 2539 *cap_count = le32_to_cpu(cmd->count); 2540 2541 return status; 2542 } 2543 2544 /** 2545 * ice_discover_dev_caps - Read and extract device capabilities 2546 * @hw: pointer to the hardware structure 2547 * @dev_caps: pointer to device capabilities structure 2548 * 2549 * Read the device capabilities and extract them into the dev_caps structure 2550 * for later use. 2551 */ 2552 int 2553 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2554 { 2555 u32 cap_count = 0; 2556 void *cbuf; 2557 int status; 2558 2559 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2560 if (!cbuf) 2561 return -ENOMEM; 2562 2563 /* Although the driver doesn't know the number of capabilities the 2564 * device will return, we can simply send a 4KB buffer, the maximum 2565 * possible size that firmware can return. 2566 */ 2567 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2568 2569 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2570 ice_aqc_opc_list_dev_caps, NULL); 2571 if (!status) 2572 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2573 kfree(cbuf); 2574 2575 return status; 2576 } 2577 2578 /** 2579 * ice_discover_func_caps - Read and extract function capabilities 2580 * @hw: pointer to the hardware structure 2581 * @func_caps: pointer to function capabilities structure 2582 * 2583 * Read the function capabilities and extract them into the func_caps structure 2584 * for later use. 2585 */ 2586 static int 2587 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2588 { 2589 u32 cap_count = 0; 2590 void *cbuf; 2591 int status; 2592 2593 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2594 if (!cbuf) 2595 return -ENOMEM; 2596 2597 /* Although the driver doesn't know the number of capabilities the 2598 * device will return, we can simply send a 4KB buffer, the maximum 2599 * possible size that firmware can return. 2600 */ 2601 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2602 2603 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2604 ice_aqc_opc_list_func_caps, NULL); 2605 if (!status) 2606 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2607 kfree(cbuf); 2608 2609 return status; 2610 } 2611 2612 /** 2613 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2614 * @hw: pointer to the hardware structure 2615 */ 2616 void ice_set_safe_mode_caps(struct ice_hw *hw) 2617 { 2618 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2619 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2620 struct ice_hw_common_caps cached_caps; 2621 u32 num_funcs; 2622 2623 /* cache some func_caps values that should be restored after memset */ 2624 cached_caps = func_caps->common_cap; 2625 2626 /* unset func capabilities */ 2627 memset(func_caps, 0, sizeof(*func_caps)); 2628 2629 #define ICE_RESTORE_FUNC_CAP(name) \ 2630 func_caps->common_cap.name = cached_caps.name 2631 2632 /* restore cached values */ 2633 ICE_RESTORE_FUNC_CAP(valid_functions); 2634 ICE_RESTORE_FUNC_CAP(txq_first_id); 2635 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2636 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2637 ICE_RESTORE_FUNC_CAP(max_mtu); 2638 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2639 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2640 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2641 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2642 2643 /* one Tx and one Rx queue in safe mode */ 2644 func_caps->common_cap.num_rxq = 1; 2645 func_caps->common_cap.num_txq = 1; 2646 2647 /* two MSIX vectors, one for traffic and one for misc causes */ 2648 func_caps->common_cap.num_msix_vectors = 2; 2649 func_caps->guar_num_vsi = 1; 2650 2651 /* cache some dev_caps values that should be restored after memset */ 2652 cached_caps = dev_caps->common_cap; 2653 num_funcs = dev_caps->num_funcs; 2654 2655 /* unset dev capabilities */ 2656 memset(dev_caps, 0, sizeof(*dev_caps)); 2657 2658 #define ICE_RESTORE_DEV_CAP(name) \ 2659 dev_caps->common_cap.name = cached_caps.name 2660 2661 /* restore cached values */ 2662 ICE_RESTORE_DEV_CAP(valid_functions); 2663 ICE_RESTORE_DEV_CAP(txq_first_id); 2664 ICE_RESTORE_DEV_CAP(rxq_first_id); 2665 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2666 ICE_RESTORE_DEV_CAP(max_mtu); 2667 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2668 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 2669 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 2670 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 2671 dev_caps->num_funcs = num_funcs; 2672 2673 /* one Tx and one Rx queue per function in safe mode */ 2674 dev_caps->common_cap.num_rxq = num_funcs; 2675 dev_caps->common_cap.num_txq = num_funcs; 2676 2677 /* two MSIX vectors per function */ 2678 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2679 } 2680 2681 /** 2682 * ice_get_caps - get info about the HW 2683 * @hw: pointer to the hardware structure 2684 */ 2685 int ice_get_caps(struct ice_hw *hw) 2686 { 2687 int status; 2688 2689 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2690 if (status) 2691 return status; 2692 2693 return ice_discover_func_caps(hw, &hw->func_caps); 2694 } 2695 2696 /** 2697 * ice_aq_manage_mac_write - manage MAC address write command 2698 * @hw: pointer to the HW struct 2699 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2700 * @flags: flags to control write behavior 2701 * @cd: pointer to command details structure or NULL 2702 * 2703 * This function is used to write MAC address to the NVM (0x0108). 2704 */ 2705 int 2706 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2707 struct ice_sq_cd *cd) 2708 { 2709 struct ice_aqc_manage_mac_write *cmd; 2710 struct ice_aq_desc desc; 2711 2712 cmd = &desc.params.mac_write; 2713 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2714 2715 cmd->flags = flags; 2716 ether_addr_copy(cmd->mac_addr, mac_addr); 2717 2718 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2719 } 2720 2721 /** 2722 * ice_aq_clear_pxe_mode 2723 * @hw: pointer to the HW struct 2724 * 2725 * Tell the firmware that the driver is taking over from PXE (0x0110). 2726 */ 2727 static int ice_aq_clear_pxe_mode(struct ice_hw *hw) 2728 { 2729 struct ice_aq_desc desc; 2730 2731 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2732 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2733 2734 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2735 } 2736 2737 /** 2738 * ice_clear_pxe_mode - clear pxe operations mode 2739 * @hw: pointer to the HW struct 2740 * 2741 * Make sure all PXE mode settings are cleared, including things 2742 * like descriptor fetch/write-back mode. 2743 */ 2744 void ice_clear_pxe_mode(struct ice_hw *hw) 2745 { 2746 if (ice_check_sq_alive(hw, &hw->adminq)) 2747 ice_aq_clear_pxe_mode(hw); 2748 } 2749 2750 /** 2751 * ice_aq_set_port_params - set physical port parameters. 2752 * @pi: pointer to the port info struct 2753 * @double_vlan: if set double VLAN is enabled 2754 * @cd: pointer to command details structure or NULL 2755 * 2756 * Set Physical port parameters (0x0203) 2757 */ 2758 int 2759 ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan, 2760 struct ice_sq_cd *cd) 2761 2762 { 2763 struct ice_aqc_set_port_params *cmd; 2764 struct ice_hw *hw = pi->hw; 2765 struct ice_aq_desc desc; 2766 u16 cmd_flags = 0; 2767 2768 cmd = &desc.params.set_port_params; 2769 2770 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 2771 if (double_vlan) 2772 cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 2773 cmd->cmd_flags = cpu_to_le16(cmd_flags); 2774 2775 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2776 } 2777 2778 /** 2779 * ice_is_100m_speed_supported 2780 * @hw: pointer to the HW struct 2781 * 2782 * returns true if 100M speeds are supported by the device, 2783 * false otherwise. 2784 */ 2785 bool ice_is_100m_speed_supported(struct ice_hw *hw) 2786 { 2787 switch (hw->device_id) { 2788 case ICE_DEV_ID_E822C_SGMII: 2789 case ICE_DEV_ID_E822L_SGMII: 2790 case ICE_DEV_ID_E823L_1GBE: 2791 case ICE_DEV_ID_E823C_SGMII: 2792 return true; 2793 default: 2794 return false; 2795 } 2796 } 2797 2798 /** 2799 * ice_get_link_speed_based_on_phy_type - returns link speed 2800 * @phy_type_low: lower part of phy_type 2801 * @phy_type_high: higher part of phy_type 2802 * 2803 * This helper function will convert an entry in PHY type structure 2804 * [phy_type_low, phy_type_high] to its corresponding link speed. 2805 * Note: In the structure of [phy_type_low, phy_type_high], there should 2806 * be one bit set, as this function will convert one PHY type to its 2807 * speed. 2808 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2809 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2810 */ 2811 static u16 2812 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2813 { 2814 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2815 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2816 2817 switch (phy_type_low) { 2818 case ICE_PHY_TYPE_LOW_100BASE_TX: 2819 case ICE_PHY_TYPE_LOW_100M_SGMII: 2820 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2821 break; 2822 case ICE_PHY_TYPE_LOW_1000BASE_T: 2823 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2824 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2825 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2826 case ICE_PHY_TYPE_LOW_1G_SGMII: 2827 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2828 break; 2829 case ICE_PHY_TYPE_LOW_2500BASE_T: 2830 case ICE_PHY_TYPE_LOW_2500BASE_X: 2831 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2832 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2833 break; 2834 case ICE_PHY_TYPE_LOW_5GBASE_T: 2835 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2836 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2837 break; 2838 case ICE_PHY_TYPE_LOW_10GBASE_T: 2839 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2840 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2841 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2842 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2843 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2844 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2845 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2846 break; 2847 case ICE_PHY_TYPE_LOW_25GBASE_T: 2848 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2849 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2850 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2851 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2852 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2853 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2854 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2855 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2856 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2857 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2858 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2859 break; 2860 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2861 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2862 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2863 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2864 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2865 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2866 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2867 break; 2868 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2869 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2870 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2871 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2872 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2873 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2874 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2875 case ICE_PHY_TYPE_LOW_50G_AUI2: 2876 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2877 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2878 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2879 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2880 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2881 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2882 case ICE_PHY_TYPE_LOW_50G_AUI1: 2883 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2884 break; 2885 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2886 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2887 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2888 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2889 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2890 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2891 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2892 case ICE_PHY_TYPE_LOW_100G_AUI4: 2893 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2894 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2895 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2896 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2897 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2898 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2899 break; 2900 default: 2901 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2902 break; 2903 } 2904 2905 switch (phy_type_high) { 2906 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2907 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2908 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2909 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2910 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2911 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2912 break; 2913 default: 2914 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2915 break; 2916 } 2917 2918 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2919 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2920 return ICE_AQ_LINK_SPEED_UNKNOWN; 2921 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2922 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2923 return ICE_AQ_LINK_SPEED_UNKNOWN; 2924 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2925 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2926 return speed_phy_type_low; 2927 else 2928 return speed_phy_type_high; 2929 } 2930 2931 /** 2932 * ice_update_phy_type 2933 * @phy_type_low: pointer to the lower part of phy_type 2934 * @phy_type_high: pointer to the higher part of phy_type 2935 * @link_speeds_bitmap: targeted link speeds bitmap 2936 * 2937 * Note: For the link_speeds_bitmap structure, you can check it at 2938 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2939 * link_speeds_bitmap include multiple speeds. 2940 * 2941 * Each entry in this [phy_type_low, phy_type_high] structure will 2942 * present a certain link speed. This helper function will turn on bits 2943 * in [phy_type_low, phy_type_high] structure based on the value of 2944 * link_speeds_bitmap input parameter. 2945 */ 2946 void 2947 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2948 u16 link_speeds_bitmap) 2949 { 2950 u64 pt_high; 2951 u64 pt_low; 2952 int index; 2953 u16 speed; 2954 2955 /* We first check with low part of phy_type */ 2956 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2957 pt_low = BIT_ULL(index); 2958 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2959 2960 if (link_speeds_bitmap & speed) 2961 *phy_type_low |= BIT_ULL(index); 2962 } 2963 2964 /* We then check with high part of phy_type */ 2965 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2966 pt_high = BIT_ULL(index); 2967 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2968 2969 if (link_speeds_bitmap & speed) 2970 *phy_type_high |= BIT_ULL(index); 2971 } 2972 } 2973 2974 /** 2975 * ice_aq_set_phy_cfg 2976 * @hw: pointer to the HW struct 2977 * @pi: port info structure of the interested logical port 2978 * @cfg: structure with PHY configuration data to be set 2979 * @cd: pointer to command details structure or NULL 2980 * 2981 * Set the various PHY configuration parameters supported on the Port. 2982 * One or more of the Set PHY config parameters may be ignored in an MFP 2983 * mode as the PF may not have the privilege to set some of the PHY Config 2984 * parameters. This status will be indicated by the command response (0x0601). 2985 */ 2986 int 2987 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2988 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2989 { 2990 struct ice_aq_desc desc; 2991 int status; 2992 2993 if (!cfg) 2994 return -EINVAL; 2995 2996 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2997 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2998 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2999 cfg->caps); 3000 3001 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 3002 } 3003 3004 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 3005 desc.params.set_phy.lport_num = pi->lport; 3006 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3007 3008 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 3009 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 3010 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 3011 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 3012 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 3013 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 3014 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 3015 cfg->low_power_ctrl_an); 3016 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 3017 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 3018 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 3019 cfg->link_fec_opt); 3020 3021 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 3022 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 3023 status = 0; 3024 3025 if (!status) 3026 pi->phy.curr_user_phy_cfg = *cfg; 3027 3028 return status; 3029 } 3030 3031 /** 3032 * ice_update_link_info - update status of the HW network link 3033 * @pi: port info structure of the interested logical port 3034 */ 3035 int ice_update_link_info(struct ice_port_info *pi) 3036 { 3037 struct ice_link_status *li; 3038 int status; 3039 3040 if (!pi) 3041 return -EINVAL; 3042 3043 li = &pi->phy.link_info; 3044 3045 status = ice_aq_get_link_info(pi, true, NULL, NULL); 3046 if (status) 3047 return status; 3048 3049 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 3050 struct ice_aqc_get_phy_caps_data *pcaps; 3051 struct ice_hw *hw; 3052 3053 hw = pi->hw; 3054 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 3055 GFP_KERNEL); 3056 if (!pcaps) 3057 return -ENOMEM; 3058 3059 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 3060 pcaps, NULL); 3061 3062 devm_kfree(ice_hw_to_dev(hw), pcaps); 3063 } 3064 3065 return status; 3066 } 3067 3068 /** 3069 * ice_cache_phy_user_req 3070 * @pi: port information structure 3071 * @cache_data: PHY logging data 3072 * @cache_mode: PHY logging mode 3073 * 3074 * Log the user request on (FC, FEC, SPEED) for later use. 3075 */ 3076 static void 3077 ice_cache_phy_user_req(struct ice_port_info *pi, 3078 struct ice_phy_cache_mode_data cache_data, 3079 enum ice_phy_cache_mode cache_mode) 3080 { 3081 if (!pi) 3082 return; 3083 3084 switch (cache_mode) { 3085 case ICE_FC_MODE: 3086 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 3087 break; 3088 case ICE_SPEED_MODE: 3089 pi->phy.curr_user_speed_req = 3090 cache_data.data.curr_user_speed_req; 3091 break; 3092 case ICE_FEC_MODE: 3093 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 3094 break; 3095 default: 3096 break; 3097 } 3098 } 3099 3100 /** 3101 * ice_caps_to_fc_mode 3102 * @caps: PHY capabilities 3103 * 3104 * Convert PHY FC capabilities to ice FC mode 3105 */ 3106 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 3107 { 3108 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 3109 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3110 return ICE_FC_FULL; 3111 3112 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 3113 return ICE_FC_TX_PAUSE; 3114 3115 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 3116 return ICE_FC_RX_PAUSE; 3117 3118 return ICE_FC_NONE; 3119 } 3120 3121 /** 3122 * ice_caps_to_fec_mode 3123 * @caps: PHY capabilities 3124 * @fec_options: Link FEC options 3125 * 3126 * Convert PHY FEC capabilities to ice FEC mode 3127 */ 3128 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 3129 { 3130 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 3131 return ICE_FEC_AUTO; 3132 3133 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3134 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3135 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 3136 ICE_AQC_PHY_FEC_25G_KR_REQ)) 3137 return ICE_FEC_BASER; 3138 3139 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3140 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 3141 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 3142 return ICE_FEC_RS; 3143 3144 return ICE_FEC_NONE; 3145 } 3146 3147 /** 3148 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 3149 * @pi: port information structure 3150 * @cfg: PHY configuration data to set FC mode 3151 * @req_mode: FC mode to configure 3152 */ 3153 int 3154 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3155 enum ice_fc_mode req_mode) 3156 { 3157 struct ice_phy_cache_mode_data cache_data; 3158 u8 pause_mask = 0x0; 3159 3160 if (!pi || !cfg) 3161 return -EINVAL; 3162 3163 switch (req_mode) { 3164 case ICE_FC_FULL: 3165 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3166 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3167 break; 3168 case ICE_FC_RX_PAUSE: 3169 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 3170 break; 3171 case ICE_FC_TX_PAUSE: 3172 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 3173 break; 3174 default: 3175 break; 3176 } 3177 3178 /* clear the old pause settings */ 3179 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 3180 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 3181 3182 /* set the new capabilities */ 3183 cfg->caps |= pause_mask; 3184 3185 /* Cache user FC request */ 3186 cache_data.data.curr_user_fc_req = req_mode; 3187 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 3188 3189 return 0; 3190 } 3191 3192 /** 3193 * ice_set_fc 3194 * @pi: port information structure 3195 * @aq_failures: pointer to status code, specific to ice_set_fc routine 3196 * @ena_auto_link_update: enable automatic link update 3197 * 3198 * Set the requested flow control mode. 3199 */ 3200 int 3201 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 3202 { 3203 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 3204 struct ice_aqc_get_phy_caps_data *pcaps; 3205 struct ice_hw *hw; 3206 int status; 3207 3208 if (!pi || !aq_failures) 3209 return -EINVAL; 3210 3211 *aq_failures = 0; 3212 hw = pi->hw; 3213 3214 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 3215 if (!pcaps) 3216 return -ENOMEM; 3217 3218 /* Get the current PHY config */ 3219 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3220 pcaps, NULL); 3221 if (status) { 3222 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 3223 goto out; 3224 } 3225 3226 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 3227 3228 /* Configure the set PHY data */ 3229 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 3230 if (status) 3231 goto out; 3232 3233 /* If the capabilities have changed, then set the new config */ 3234 if (cfg.caps != pcaps->caps) { 3235 int retry_count, retry_max = 10; 3236 3237 /* Auto restart link so settings take effect */ 3238 if (ena_auto_link_update) 3239 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3240 3241 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 3242 if (status) { 3243 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 3244 goto out; 3245 } 3246 3247 /* Update the link info 3248 * It sometimes takes a really long time for link to 3249 * come back from the atomic reset. Thus, we wait a 3250 * little bit. 3251 */ 3252 for (retry_count = 0; retry_count < retry_max; retry_count++) { 3253 status = ice_update_link_info(pi); 3254 3255 if (!status) 3256 break; 3257 3258 mdelay(100); 3259 } 3260 3261 if (status) 3262 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 3263 } 3264 3265 out: 3266 devm_kfree(ice_hw_to_dev(hw), pcaps); 3267 return status; 3268 } 3269 3270 /** 3271 * ice_phy_caps_equals_cfg 3272 * @phy_caps: PHY capabilities 3273 * @phy_cfg: PHY configuration 3274 * 3275 * Helper function to determine if PHY capabilities matches PHY 3276 * configuration 3277 */ 3278 bool 3279 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 3280 struct ice_aqc_set_phy_cfg_data *phy_cfg) 3281 { 3282 u8 caps_mask, cfg_mask; 3283 3284 if (!phy_caps || !phy_cfg) 3285 return false; 3286 3287 /* These bits are not common between capabilities and configuration. 3288 * Do not use them to determine equality. 3289 */ 3290 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 3291 ICE_AQC_GET_PHY_EN_MOD_QUAL); 3292 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 3293 3294 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 3295 phy_caps->phy_type_high != phy_cfg->phy_type_high || 3296 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 3297 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 3298 phy_caps->eee_cap != phy_cfg->eee_cap || 3299 phy_caps->eeer_value != phy_cfg->eeer_value || 3300 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3301 return false; 3302 3303 return true; 3304 } 3305 3306 /** 3307 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3308 * @pi: port information structure 3309 * @caps: PHY ability structure to copy date from 3310 * @cfg: PHY configuration structure to copy data to 3311 * 3312 * Helper function to copy AQC PHY get ability data to PHY set configuration 3313 * data structure 3314 */ 3315 void 3316 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3317 struct ice_aqc_get_phy_caps_data *caps, 3318 struct ice_aqc_set_phy_cfg_data *cfg) 3319 { 3320 if (!pi || !caps || !cfg) 3321 return; 3322 3323 memset(cfg, 0, sizeof(*cfg)); 3324 cfg->phy_type_low = caps->phy_type_low; 3325 cfg->phy_type_high = caps->phy_type_high; 3326 cfg->caps = caps->caps; 3327 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3328 cfg->eee_cap = caps->eee_cap; 3329 cfg->eeer_value = caps->eeer_value; 3330 cfg->link_fec_opt = caps->link_fec_options; 3331 cfg->module_compliance_enforcement = 3332 caps->module_compliance_enforcement; 3333 } 3334 3335 /** 3336 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3337 * @pi: port information structure 3338 * @cfg: PHY configuration data to set FEC mode 3339 * @fec: FEC mode to configure 3340 */ 3341 int 3342 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3343 enum ice_fec_mode fec) 3344 { 3345 struct ice_aqc_get_phy_caps_data *pcaps; 3346 struct ice_hw *hw; 3347 int status; 3348 3349 if (!pi || !cfg) 3350 return -EINVAL; 3351 3352 hw = pi->hw; 3353 3354 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3355 if (!pcaps) 3356 return -ENOMEM; 3357 3358 status = ice_aq_get_phy_caps(pi, false, 3359 (ice_fw_supports_report_dflt_cfg(hw) ? 3360 ICE_AQC_REPORT_DFLT_CFG : 3361 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3362 if (status) 3363 goto out; 3364 3365 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3366 cfg->link_fec_opt = pcaps->link_fec_options; 3367 3368 switch (fec) { 3369 case ICE_FEC_BASER: 3370 /* Clear RS bits, and AND BASE-R ability 3371 * bits and OR request bits. 3372 */ 3373 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3374 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3375 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3376 ICE_AQC_PHY_FEC_25G_KR_REQ; 3377 break; 3378 case ICE_FEC_RS: 3379 /* Clear BASE-R bits, and AND RS ability 3380 * bits and OR request bits. 3381 */ 3382 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3383 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3384 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3385 break; 3386 case ICE_FEC_NONE: 3387 /* Clear all FEC option bits. */ 3388 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3389 break; 3390 case ICE_FEC_AUTO: 3391 /* AND auto FEC bit, and all caps bits. */ 3392 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3393 cfg->link_fec_opt |= pcaps->link_fec_options; 3394 break; 3395 default: 3396 status = -EINVAL; 3397 break; 3398 } 3399 3400 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 3401 !ice_fw_supports_report_dflt_cfg(hw)) { 3402 struct ice_link_default_override_tlv tlv = { 0 }; 3403 3404 status = ice_get_link_default_override(&tlv, pi); 3405 if (status) 3406 goto out; 3407 3408 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3409 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3410 cfg->link_fec_opt = tlv.fec_options; 3411 } 3412 3413 out: 3414 kfree(pcaps); 3415 3416 return status; 3417 } 3418 3419 /** 3420 * ice_get_link_status - get status of the HW network link 3421 * @pi: port information structure 3422 * @link_up: pointer to bool (true/false = linkup/linkdown) 3423 * 3424 * Variable link_up is true if link is up, false if link is down. 3425 * The variable link_up is invalid if status is non zero. As a 3426 * result of this call, link status reporting becomes enabled 3427 */ 3428 int ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3429 { 3430 struct ice_phy_info *phy_info; 3431 int status = 0; 3432 3433 if (!pi || !link_up) 3434 return -EINVAL; 3435 3436 phy_info = &pi->phy; 3437 3438 if (phy_info->get_link_info) { 3439 status = ice_update_link_info(pi); 3440 3441 if (status) 3442 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3443 status); 3444 } 3445 3446 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3447 3448 return status; 3449 } 3450 3451 /** 3452 * ice_aq_set_link_restart_an 3453 * @pi: pointer to the port information structure 3454 * @ena_link: if true: enable link, if false: disable link 3455 * @cd: pointer to command details structure or NULL 3456 * 3457 * Sets up the link and restarts the Auto-Negotiation over the link. 3458 */ 3459 int 3460 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3461 struct ice_sq_cd *cd) 3462 { 3463 struct ice_aqc_restart_an *cmd; 3464 struct ice_aq_desc desc; 3465 3466 cmd = &desc.params.restart_an; 3467 3468 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3469 3470 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3471 cmd->lport_num = pi->lport; 3472 if (ena_link) 3473 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3474 else 3475 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3476 3477 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3478 } 3479 3480 /** 3481 * ice_aq_set_event_mask 3482 * @hw: pointer to the HW struct 3483 * @port_num: port number of the physical function 3484 * @mask: event mask to be set 3485 * @cd: pointer to command details structure or NULL 3486 * 3487 * Set event mask (0x0613) 3488 */ 3489 int 3490 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3491 struct ice_sq_cd *cd) 3492 { 3493 struct ice_aqc_set_event_mask *cmd; 3494 struct ice_aq_desc desc; 3495 3496 cmd = &desc.params.set_event_mask; 3497 3498 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3499 3500 cmd->lport_num = port_num; 3501 3502 cmd->event_mask = cpu_to_le16(mask); 3503 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3504 } 3505 3506 /** 3507 * ice_aq_set_mac_loopback 3508 * @hw: pointer to the HW struct 3509 * @ena_lpbk: Enable or Disable loopback 3510 * @cd: pointer to command details structure or NULL 3511 * 3512 * Enable/disable loopback on a given port 3513 */ 3514 int 3515 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3516 { 3517 struct ice_aqc_set_mac_lb *cmd; 3518 struct ice_aq_desc desc; 3519 3520 cmd = &desc.params.set_mac_lb; 3521 3522 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3523 if (ena_lpbk) 3524 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3525 3526 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3527 } 3528 3529 /** 3530 * ice_aq_set_port_id_led 3531 * @pi: pointer to the port information 3532 * @is_orig_mode: is this LED set to original mode (by the net-list) 3533 * @cd: pointer to command details structure or NULL 3534 * 3535 * Set LED value for the given port (0x06e9) 3536 */ 3537 int 3538 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3539 struct ice_sq_cd *cd) 3540 { 3541 struct ice_aqc_set_port_id_led *cmd; 3542 struct ice_hw *hw = pi->hw; 3543 struct ice_aq_desc desc; 3544 3545 cmd = &desc.params.set_port_id_led; 3546 3547 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3548 3549 if (is_orig_mode) 3550 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3551 else 3552 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3553 3554 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3555 } 3556 3557 /** 3558 * ice_aq_get_port_options 3559 * @hw: pointer to the HW struct 3560 * @options: buffer for the resultant port options 3561 * @option_count: input - size of the buffer in port options structures, 3562 * output - number of returned port options 3563 * @lport: logical port to call the command with (optional) 3564 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3565 * when PF owns more than 1 port it must be true 3566 * @active_option_idx: index of active port option in returned buffer 3567 * @active_option_valid: active option in returned buffer is valid 3568 * @pending_option_idx: index of pending port option in returned buffer 3569 * @pending_option_valid: pending option in returned buffer is valid 3570 * 3571 * Calls Get Port Options AQC (0x06ea) and verifies result. 3572 */ 3573 int 3574 ice_aq_get_port_options(struct ice_hw *hw, 3575 struct ice_aqc_get_port_options_elem *options, 3576 u8 *option_count, u8 lport, bool lport_valid, 3577 u8 *active_option_idx, bool *active_option_valid, 3578 u8 *pending_option_idx, bool *pending_option_valid) 3579 { 3580 struct ice_aqc_get_port_options *cmd; 3581 struct ice_aq_desc desc; 3582 int status; 3583 u8 i; 3584 3585 /* options buffer shall be able to hold max returned options */ 3586 if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 3587 return -EINVAL; 3588 3589 cmd = &desc.params.get_port_options; 3590 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 3591 3592 if (lport_valid) 3593 cmd->lport_num = lport; 3594 cmd->lport_num_valid = lport_valid; 3595 3596 status = ice_aq_send_cmd(hw, &desc, options, 3597 *option_count * sizeof(*options), NULL); 3598 if (status) 3599 return status; 3600 3601 /* verify direct FW response & set output parameters */ 3602 *option_count = FIELD_GET(ICE_AQC_PORT_OPT_COUNT_M, 3603 cmd->port_options_count); 3604 ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 3605 *active_option_valid = FIELD_GET(ICE_AQC_PORT_OPT_VALID, 3606 cmd->port_options); 3607 if (*active_option_valid) { 3608 *active_option_idx = FIELD_GET(ICE_AQC_PORT_OPT_ACTIVE_M, 3609 cmd->port_options); 3610 if (*active_option_idx > (*option_count - 1)) 3611 return -EIO; 3612 ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 3613 *active_option_idx); 3614 } 3615 3616 *pending_option_valid = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_VALID, 3617 cmd->pending_port_option_status); 3618 if (*pending_option_valid) { 3619 *pending_option_idx = FIELD_GET(ICE_AQC_PENDING_PORT_OPT_IDX_M, 3620 cmd->pending_port_option_status); 3621 if (*pending_option_idx > (*option_count - 1)) 3622 return -EIO; 3623 ice_debug(hw, ICE_DBG_PHY, "pending idx: %x\n", 3624 *pending_option_idx); 3625 } 3626 3627 /* mask output options fields */ 3628 for (i = 0; i < *option_count; i++) { 3629 options[i].pmd = FIELD_GET(ICE_AQC_PORT_OPT_PMD_COUNT_M, 3630 options[i].pmd); 3631 options[i].max_lane_speed = FIELD_GET(ICE_AQC_PORT_OPT_MAX_LANE_M, 3632 options[i].max_lane_speed); 3633 ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 3634 options[i].pmd, options[i].max_lane_speed); 3635 } 3636 3637 return 0; 3638 } 3639 3640 /** 3641 * ice_aq_set_port_option 3642 * @hw: pointer to the HW struct 3643 * @lport: logical port to call the command with 3644 * @lport_valid: when false, FW uses port owned by the PF instead of lport, 3645 * when PF owns more than 1 port it must be true 3646 * @new_option: new port option to be written 3647 * 3648 * Calls Set Port Options AQC (0x06eb). 3649 */ 3650 int 3651 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 3652 u8 new_option) 3653 { 3654 struct ice_aqc_set_port_option *cmd; 3655 struct ice_aq_desc desc; 3656 3657 if (new_option > ICE_AQC_PORT_OPT_COUNT_M) 3658 return -EINVAL; 3659 3660 cmd = &desc.params.set_port_option; 3661 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_option); 3662 3663 if (lport_valid) 3664 cmd->lport_num = lport; 3665 3666 cmd->lport_num_valid = lport_valid; 3667 cmd->selected_port_option = new_option; 3668 3669 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 3670 } 3671 3672 /** 3673 * ice_aq_sff_eeprom 3674 * @hw: pointer to the HW struct 3675 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3676 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3677 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3678 * @page: QSFP page 3679 * @set_page: set or ignore the page 3680 * @data: pointer to data buffer to be read/written to the I2C device. 3681 * @length: 1-16 for read, 1 for write. 3682 * @write: 0 read, 1 for write. 3683 * @cd: pointer to command details structure or NULL 3684 * 3685 * Read/Write SFF EEPROM (0x06EE) 3686 */ 3687 int 3688 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3689 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3690 bool write, struct ice_sq_cd *cd) 3691 { 3692 struct ice_aqc_sff_eeprom *cmd; 3693 struct ice_aq_desc desc; 3694 int status; 3695 3696 if (!data || (mem_addr & 0xff00)) 3697 return -EINVAL; 3698 3699 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3700 cmd = &desc.params.read_write_sff_param; 3701 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 3702 cmd->lport_num = (u8)(lport & 0xff); 3703 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3704 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 3705 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3706 ((set_page << 3707 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3708 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3709 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3710 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3711 if (write) 3712 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 3713 3714 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3715 return status; 3716 } 3717 3718 /** 3719 * __ice_aq_get_set_rss_lut 3720 * @hw: pointer to the hardware structure 3721 * @params: RSS LUT parameters 3722 * @set: set true to set the table, false to get the table 3723 * 3724 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3725 */ 3726 static int 3727 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 3728 { 3729 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 3730 struct ice_aqc_get_set_rss_lut *cmd_resp; 3731 struct ice_aq_desc desc; 3732 int status; 3733 u8 *lut; 3734 3735 if (!params) 3736 return -EINVAL; 3737 3738 vsi_handle = params->vsi_handle; 3739 lut = params->lut; 3740 3741 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3742 return -EINVAL; 3743 3744 lut_size = params->lut_size; 3745 lut_type = params->lut_type; 3746 glob_lut_idx = params->global_lut_id; 3747 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 3748 3749 cmd_resp = &desc.params.get_set_rss_lut; 3750 3751 if (set) { 3752 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3753 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3754 } else { 3755 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3756 } 3757 3758 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3759 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3760 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3761 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3762 3763 switch (lut_type) { 3764 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3765 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3766 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3767 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3768 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3769 break; 3770 default: 3771 status = -EINVAL; 3772 goto ice_aq_get_set_rss_lut_exit; 3773 } 3774 3775 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3776 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3777 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3778 3779 if (!set) 3780 goto ice_aq_get_set_rss_lut_send; 3781 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3782 if (!set) 3783 goto ice_aq_get_set_rss_lut_send; 3784 } else { 3785 goto ice_aq_get_set_rss_lut_send; 3786 } 3787 3788 /* LUT size is only valid for Global and PF table types */ 3789 switch (lut_size) { 3790 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3791 break; 3792 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3793 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3794 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3795 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3796 break; 3797 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3798 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3799 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3800 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3801 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3802 break; 3803 } 3804 fallthrough; 3805 default: 3806 status = -EINVAL; 3807 goto ice_aq_get_set_rss_lut_exit; 3808 } 3809 3810 ice_aq_get_set_rss_lut_send: 3811 cmd_resp->flags = cpu_to_le16(flags); 3812 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3813 3814 ice_aq_get_set_rss_lut_exit: 3815 return status; 3816 } 3817 3818 /** 3819 * ice_aq_get_rss_lut 3820 * @hw: pointer to the hardware structure 3821 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 3822 * 3823 * get the RSS lookup table, PF or VSI type 3824 */ 3825 int 3826 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 3827 { 3828 return __ice_aq_get_set_rss_lut(hw, get_params, false); 3829 } 3830 3831 /** 3832 * ice_aq_set_rss_lut 3833 * @hw: pointer to the hardware structure 3834 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 3835 * 3836 * set the RSS lookup table, PF or VSI type 3837 */ 3838 int 3839 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 3840 { 3841 return __ice_aq_get_set_rss_lut(hw, set_params, true); 3842 } 3843 3844 /** 3845 * __ice_aq_get_set_rss_key 3846 * @hw: pointer to the HW struct 3847 * @vsi_id: VSI FW index 3848 * @key: pointer to key info struct 3849 * @set: set true to set the key, false to get the key 3850 * 3851 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3852 */ 3853 static int 3854 __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3855 struct ice_aqc_get_set_rss_keys *key, bool set) 3856 { 3857 struct ice_aqc_get_set_rss_key *cmd_resp; 3858 u16 key_size = sizeof(*key); 3859 struct ice_aq_desc desc; 3860 3861 cmd_resp = &desc.params.get_set_rss_key; 3862 3863 if (set) { 3864 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3865 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3866 } else { 3867 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3868 } 3869 3870 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3871 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3872 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3873 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3874 3875 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3876 } 3877 3878 /** 3879 * ice_aq_get_rss_key 3880 * @hw: pointer to the HW struct 3881 * @vsi_handle: software VSI handle 3882 * @key: pointer to key info struct 3883 * 3884 * get the RSS key per VSI 3885 */ 3886 int 3887 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3888 struct ice_aqc_get_set_rss_keys *key) 3889 { 3890 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 3891 return -EINVAL; 3892 3893 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3894 key, false); 3895 } 3896 3897 /** 3898 * ice_aq_set_rss_key 3899 * @hw: pointer to the HW struct 3900 * @vsi_handle: software VSI handle 3901 * @keys: pointer to key info struct 3902 * 3903 * set the RSS key per VSI 3904 */ 3905 int 3906 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3907 struct ice_aqc_get_set_rss_keys *keys) 3908 { 3909 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 3910 return -EINVAL; 3911 3912 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3913 keys, true); 3914 } 3915 3916 /** 3917 * ice_aq_add_lan_txq 3918 * @hw: pointer to the hardware structure 3919 * @num_qgrps: Number of added queue groups 3920 * @qg_list: list of queue groups to be added 3921 * @buf_size: size of buffer for indirect command 3922 * @cd: pointer to command details structure or NULL 3923 * 3924 * Add Tx LAN queue (0x0C30) 3925 * 3926 * NOTE: 3927 * Prior to calling add Tx LAN queue: 3928 * Initialize the following as part of the Tx queue context: 3929 * Completion queue ID if the queue uses Completion queue, Quanta profile, 3930 * Cache profile and Packet shaper profile. 3931 * 3932 * After add Tx LAN queue AQ command is completed: 3933 * Interrupts should be associated with specific queues, 3934 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3935 * flow. 3936 */ 3937 static int 3938 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3939 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3940 struct ice_sq_cd *cd) 3941 { 3942 struct ice_aqc_add_tx_qgrp *list; 3943 struct ice_aqc_add_txqs *cmd; 3944 struct ice_aq_desc desc; 3945 u16 i, sum_size = 0; 3946 3947 cmd = &desc.params.add_txqs; 3948 3949 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3950 3951 if (!qg_list) 3952 return -EINVAL; 3953 3954 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3955 return -EINVAL; 3956 3957 for (i = 0, list = qg_list; i < num_qgrps; i++) { 3958 sum_size += struct_size(list, txqs, list->num_txqs); 3959 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 3960 list->num_txqs); 3961 } 3962 3963 if (buf_size != sum_size) 3964 return -EINVAL; 3965 3966 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3967 3968 cmd->num_qgrps = num_qgrps; 3969 3970 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3971 } 3972 3973 /** 3974 * ice_aq_dis_lan_txq 3975 * @hw: pointer to the hardware structure 3976 * @num_qgrps: number of groups in the list 3977 * @qg_list: the list of groups to disable 3978 * @buf_size: the total size of the qg_list buffer in bytes 3979 * @rst_src: if called due to reset, specifies the reset source 3980 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3981 * @cd: pointer to command details structure or NULL 3982 * 3983 * Disable LAN Tx queue (0x0C31) 3984 */ 3985 static int 3986 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3987 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3988 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3989 struct ice_sq_cd *cd) 3990 { 3991 struct ice_aqc_dis_txq_item *item; 3992 struct ice_aqc_dis_txqs *cmd; 3993 struct ice_aq_desc desc; 3994 u16 i, sz = 0; 3995 int status; 3996 3997 cmd = &desc.params.dis_txqs; 3998 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3999 4000 /* qg_list can be NULL only in VM/VF reset flow */ 4001 if (!qg_list && !rst_src) 4002 return -EINVAL; 4003 4004 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 4005 return -EINVAL; 4006 4007 cmd->num_entries = num_qgrps; 4008 4009 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 4010 ICE_AQC_Q_DIS_TIMEOUT_M); 4011 4012 switch (rst_src) { 4013 case ICE_VM_RESET: 4014 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 4015 cmd->vmvf_and_timeout |= 4016 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 4017 break; 4018 case ICE_VF_RESET: 4019 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 4020 /* In this case, FW expects vmvf_num to be absolute VF ID */ 4021 cmd->vmvf_and_timeout |= 4022 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 4023 ICE_AQC_Q_DIS_VMVF_NUM_M); 4024 break; 4025 case ICE_NO_RESET: 4026 default: 4027 break; 4028 } 4029 4030 /* flush pipe on time out */ 4031 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 4032 /* If no queue group info, we are in a reset flow. Issue the AQ */ 4033 if (!qg_list) 4034 goto do_aq; 4035 4036 /* set RD bit to indicate that command buffer is provided by the driver 4037 * and it needs to be read by the firmware 4038 */ 4039 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4040 4041 for (i = 0, item = qg_list; i < num_qgrps; i++) { 4042 u16 item_size = struct_size(item, q_id, item->num_qs); 4043 4044 /* If the num of queues is even, add 2 bytes of padding */ 4045 if ((item->num_qs % 2) == 0) 4046 item_size += 2; 4047 4048 sz += item_size; 4049 4050 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 4051 } 4052 4053 if (buf_size != sz) 4054 return -EINVAL; 4055 4056 do_aq: 4057 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 4058 if (status) { 4059 if (!qg_list) 4060 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 4061 vmvf_num, hw->adminq.sq_last_status); 4062 else 4063 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 4064 le16_to_cpu(qg_list[0].q_id[0]), 4065 hw->adminq.sq_last_status); 4066 } 4067 return status; 4068 } 4069 4070 /** 4071 * ice_aq_add_rdma_qsets 4072 * @hw: pointer to the hardware structure 4073 * @num_qset_grps: Number of RDMA Qset groups 4074 * @qset_list: list of Qset groups to be added 4075 * @buf_size: size of buffer for indirect command 4076 * @cd: pointer to command details structure or NULL 4077 * 4078 * Add Tx RDMA Qsets (0x0C33) 4079 */ 4080 static int 4081 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 4082 struct ice_aqc_add_rdma_qset_data *qset_list, 4083 u16 buf_size, struct ice_sq_cd *cd) 4084 { 4085 struct ice_aqc_add_rdma_qset_data *list; 4086 struct ice_aqc_add_rdma_qset *cmd; 4087 struct ice_aq_desc desc; 4088 u16 i, sum_size = 0; 4089 4090 cmd = &desc.params.add_rdma_qset; 4091 4092 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 4093 4094 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 4095 return -EINVAL; 4096 4097 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 4098 u16 num_qsets = le16_to_cpu(list->num_qsets); 4099 4100 sum_size += struct_size(list, rdma_qsets, num_qsets); 4101 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 4102 num_qsets); 4103 } 4104 4105 if (buf_size != sum_size) 4106 return -EINVAL; 4107 4108 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 4109 4110 cmd->num_qset_grps = num_qset_grps; 4111 4112 return ice_aq_send_cmd(hw, &desc, qset_list, buf_size, cd); 4113 } 4114 4115 /* End of FW Admin Queue command wrappers */ 4116 4117 /** 4118 * ice_write_byte - write a byte to a packed context structure 4119 * @src_ctx: the context structure to read from 4120 * @dest_ctx: the context to be written to 4121 * @ce_info: a description of the struct to be filled 4122 */ 4123 static void 4124 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4125 { 4126 u8 src_byte, dest_byte, mask; 4127 u8 *from, *dest; 4128 u16 shift_width; 4129 4130 /* copy from the next struct field */ 4131 from = src_ctx + ce_info->offset; 4132 4133 /* prepare the bits and mask */ 4134 shift_width = ce_info->lsb % 8; 4135 mask = (u8)(BIT(ce_info->width) - 1); 4136 4137 src_byte = *from; 4138 src_byte &= mask; 4139 4140 /* shift to correct alignment */ 4141 mask <<= shift_width; 4142 src_byte <<= shift_width; 4143 4144 /* get the current bits from the target bit string */ 4145 dest = dest_ctx + (ce_info->lsb / 8); 4146 4147 memcpy(&dest_byte, dest, sizeof(dest_byte)); 4148 4149 dest_byte &= ~mask; /* get the bits not changing */ 4150 dest_byte |= src_byte; /* add in the new bits */ 4151 4152 /* put it all back */ 4153 memcpy(dest, &dest_byte, sizeof(dest_byte)); 4154 } 4155 4156 /** 4157 * ice_write_word - write a word to a packed context structure 4158 * @src_ctx: the context structure to read from 4159 * @dest_ctx: the context to be written to 4160 * @ce_info: a description of the struct to be filled 4161 */ 4162 static void 4163 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4164 { 4165 u16 src_word, mask; 4166 __le16 dest_word; 4167 u8 *from, *dest; 4168 u16 shift_width; 4169 4170 /* copy from the next struct field */ 4171 from = src_ctx + ce_info->offset; 4172 4173 /* prepare the bits and mask */ 4174 shift_width = ce_info->lsb % 8; 4175 mask = BIT(ce_info->width) - 1; 4176 4177 /* don't swizzle the bits until after the mask because the mask bits 4178 * will be in a different bit position on big endian machines 4179 */ 4180 src_word = *(u16 *)from; 4181 src_word &= mask; 4182 4183 /* shift to correct alignment */ 4184 mask <<= shift_width; 4185 src_word <<= shift_width; 4186 4187 /* get the current bits from the target bit string */ 4188 dest = dest_ctx + (ce_info->lsb / 8); 4189 4190 memcpy(&dest_word, dest, sizeof(dest_word)); 4191 4192 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 4193 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 4194 4195 /* put it all back */ 4196 memcpy(dest, &dest_word, sizeof(dest_word)); 4197 } 4198 4199 /** 4200 * ice_write_dword - write a dword to a packed context structure 4201 * @src_ctx: the context structure to read from 4202 * @dest_ctx: the context to be written to 4203 * @ce_info: a description of the struct to be filled 4204 */ 4205 static void 4206 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4207 { 4208 u32 src_dword, mask; 4209 __le32 dest_dword; 4210 u8 *from, *dest; 4211 u16 shift_width; 4212 4213 /* copy from the next struct field */ 4214 from = src_ctx + ce_info->offset; 4215 4216 /* prepare the bits and mask */ 4217 shift_width = ce_info->lsb % 8; 4218 4219 /* if the field width is exactly 32 on an x86 machine, then the shift 4220 * operation will not work because the SHL instructions count is masked 4221 * to 5 bits so the shift will do nothing 4222 */ 4223 if (ce_info->width < 32) 4224 mask = BIT(ce_info->width) - 1; 4225 else 4226 mask = (u32)~0; 4227 4228 /* don't swizzle the bits until after the mask because the mask bits 4229 * will be in a different bit position on big endian machines 4230 */ 4231 src_dword = *(u32 *)from; 4232 src_dword &= mask; 4233 4234 /* shift to correct alignment */ 4235 mask <<= shift_width; 4236 src_dword <<= shift_width; 4237 4238 /* get the current bits from the target bit string */ 4239 dest = dest_ctx + (ce_info->lsb / 8); 4240 4241 memcpy(&dest_dword, dest, sizeof(dest_dword)); 4242 4243 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 4244 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 4245 4246 /* put it all back */ 4247 memcpy(dest, &dest_dword, sizeof(dest_dword)); 4248 } 4249 4250 /** 4251 * ice_write_qword - write a qword to a packed context structure 4252 * @src_ctx: the context structure to read from 4253 * @dest_ctx: the context to be written to 4254 * @ce_info: a description of the struct to be filled 4255 */ 4256 static void 4257 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 4258 { 4259 u64 src_qword, mask; 4260 __le64 dest_qword; 4261 u8 *from, *dest; 4262 u16 shift_width; 4263 4264 /* copy from the next struct field */ 4265 from = src_ctx + ce_info->offset; 4266 4267 /* prepare the bits and mask */ 4268 shift_width = ce_info->lsb % 8; 4269 4270 /* if the field width is exactly 64 on an x86 machine, then the shift 4271 * operation will not work because the SHL instructions count is masked 4272 * to 6 bits so the shift will do nothing 4273 */ 4274 if (ce_info->width < 64) 4275 mask = BIT_ULL(ce_info->width) - 1; 4276 else 4277 mask = (u64)~0; 4278 4279 /* don't swizzle the bits until after the mask because the mask bits 4280 * will be in a different bit position on big endian machines 4281 */ 4282 src_qword = *(u64 *)from; 4283 src_qword &= mask; 4284 4285 /* shift to correct alignment */ 4286 mask <<= shift_width; 4287 src_qword <<= shift_width; 4288 4289 /* get the current bits from the target bit string */ 4290 dest = dest_ctx + (ce_info->lsb / 8); 4291 4292 memcpy(&dest_qword, dest, sizeof(dest_qword)); 4293 4294 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 4295 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 4296 4297 /* put it all back */ 4298 memcpy(dest, &dest_qword, sizeof(dest_qword)); 4299 } 4300 4301 /** 4302 * ice_set_ctx - set context bits in packed structure 4303 * @hw: pointer to the hardware structure 4304 * @src_ctx: pointer to a generic non-packed context structure 4305 * @dest_ctx: pointer to memory for the packed structure 4306 * @ce_info: a description of the structure to be transformed 4307 */ 4308 int 4309 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 4310 const struct ice_ctx_ele *ce_info) 4311 { 4312 int f; 4313 4314 for (f = 0; ce_info[f].width; f++) { 4315 /* We have to deal with each element of the FW response 4316 * using the correct size so that we are correct regardless 4317 * of the endianness of the machine. 4318 */ 4319 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 4320 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 4321 f, ce_info[f].width, ce_info[f].size_of); 4322 continue; 4323 } 4324 switch (ce_info[f].size_of) { 4325 case sizeof(u8): 4326 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 4327 break; 4328 case sizeof(u16): 4329 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 4330 break; 4331 case sizeof(u32): 4332 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 4333 break; 4334 case sizeof(u64): 4335 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 4336 break; 4337 default: 4338 return -EINVAL; 4339 } 4340 } 4341 4342 return 0; 4343 } 4344 4345 /** 4346 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 4347 * @hw: pointer to the HW struct 4348 * @vsi_handle: software VSI handle 4349 * @tc: TC number 4350 * @q_handle: software queue handle 4351 */ 4352 struct ice_q_ctx * 4353 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 4354 { 4355 struct ice_vsi_ctx *vsi; 4356 struct ice_q_ctx *q_ctx; 4357 4358 vsi = ice_get_vsi_ctx(hw, vsi_handle); 4359 if (!vsi) 4360 return NULL; 4361 if (q_handle >= vsi->num_lan_q_entries[tc]) 4362 return NULL; 4363 if (!vsi->lan_q_ctx[tc]) 4364 return NULL; 4365 q_ctx = vsi->lan_q_ctx[tc]; 4366 return &q_ctx[q_handle]; 4367 } 4368 4369 /** 4370 * ice_ena_vsi_txq 4371 * @pi: port information structure 4372 * @vsi_handle: software VSI handle 4373 * @tc: TC number 4374 * @q_handle: software queue handle 4375 * @num_qgrps: Number of added queue groups 4376 * @buf: list of queue groups to be added 4377 * @buf_size: size of buffer for indirect command 4378 * @cd: pointer to command details structure or NULL 4379 * 4380 * This function adds one LAN queue 4381 */ 4382 int 4383 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 4384 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 4385 struct ice_sq_cd *cd) 4386 { 4387 struct ice_aqc_txsched_elem_data node = { 0 }; 4388 struct ice_sched_node *parent; 4389 struct ice_q_ctx *q_ctx; 4390 struct ice_hw *hw; 4391 int status; 4392 4393 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4394 return -EIO; 4395 4396 if (num_qgrps > 1 || buf->num_txqs > 1) 4397 return -ENOSPC; 4398 4399 hw = pi->hw; 4400 4401 if (!ice_is_vsi_valid(hw, vsi_handle)) 4402 return -EINVAL; 4403 4404 mutex_lock(&pi->sched_lock); 4405 4406 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 4407 if (!q_ctx) { 4408 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 4409 q_handle); 4410 status = -EINVAL; 4411 goto ena_txq_exit; 4412 } 4413 4414 /* find a parent node */ 4415 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4416 ICE_SCHED_NODE_OWNER_LAN); 4417 if (!parent) { 4418 status = -EINVAL; 4419 goto ena_txq_exit; 4420 } 4421 4422 buf->parent_teid = parent->info.node_teid; 4423 node.parent_teid = parent->info.node_teid; 4424 /* Mark that the values in the "generic" section as valid. The default 4425 * value in the "generic" section is zero. This means that : 4426 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4427 * - 0 priority among siblings, indicated by Bit 1-3. 4428 * - WFQ, indicated by Bit 4. 4429 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4430 * Bit 5-6. 4431 * - Bit 7 is reserved. 4432 * Without setting the generic section as valid in valid_sections, the 4433 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4434 */ 4435 buf->txqs[0].info.valid_sections = 4436 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4437 ICE_AQC_ELEM_VALID_EIR; 4438 buf->txqs[0].info.generic = 0; 4439 buf->txqs[0].info.cir_bw.bw_profile_idx = 4440 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4441 buf->txqs[0].info.cir_bw.bw_alloc = 4442 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4443 buf->txqs[0].info.eir_bw.bw_profile_idx = 4444 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4445 buf->txqs[0].info.eir_bw.bw_alloc = 4446 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4447 4448 /* add the LAN queue */ 4449 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4450 if (status) { 4451 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4452 le16_to_cpu(buf->txqs[0].txq_id), 4453 hw->adminq.sq_last_status); 4454 goto ena_txq_exit; 4455 } 4456 4457 node.node_teid = buf->txqs[0].q_teid; 4458 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4459 q_ctx->q_handle = q_handle; 4460 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4461 4462 /* add a leaf node into scheduler tree queue layer */ 4463 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 4464 if (!status) 4465 status = ice_sched_replay_q_bw(pi, q_ctx); 4466 4467 ena_txq_exit: 4468 mutex_unlock(&pi->sched_lock); 4469 return status; 4470 } 4471 4472 /** 4473 * ice_dis_vsi_txq 4474 * @pi: port information structure 4475 * @vsi_handle: software VSI handle 4476 * @tc: TC number 4477 * @num_queues: number of queues 4478 * @q_handles: pointer to software queue handle array 4479 * @q_ids: pointer to the q_id array 4480 * @q_teids: pointer to queue node teids 4481 * @rst_src: if called due to reset, specifies the reset source 4482 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4483 * @cd: pointer to command details structure or NULL 4484 * 4485 * This function removes queues and their corresponding nodes in SW DB 4486 */ 4487 int 4488 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4489 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4490 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4491 struct ice_sq_cd *cd) 4492 { 4493 struct ice_aqc_dis_txq_item *qg_list; 4494 struct ice_q_ctx *q_ctx; 4495 int status = -ENOENT; 4496 struct ice_hw *hw; 4497 u16 i, buf_size; 4498 4499 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4500 return -EIO; 4501 4502 hw = pi->hw; 4503 4504 if (!num_queues) { 4505 /* if queue is disabled already yet the disable queue command 4506 * has to be sent to complete the VF reset, then call 4507 * ice_aq_dis_lan_txq without any queue information 4508 */ 4509 if (rst_src) 4510 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4511 vmvf_num, NULL); 4512 return -EIO; 4513 } 4514 4515 buf_size = struct_size(qg_list, q_id, 1); 4516 qg_list = kzalloc(buf_size, GFP_KERNEL); 4517 if (!qg_list) 4518 return -ENOMEM; 4519 4520 mutex_lock(&pi->sched_lock); 4521 4522 for (i = 0; i < num_queues; i++) { 4523 struct ice_sched_node *node; 4524 4525 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4526 if (!node) 4527 continue; 4528 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4529 if (!q_ctx) { 4530 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4531 q_handles[i]); 4532 continue; 4533 } 4534 if (q_ctx->q_handle != q_handles[i]) { 4535 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4536 q_ctx->q_handle, q_handles[i]); 4537 continue; 4538 } 4539 qg_list->parent_teid = node->info.parent_teid; 4540 qg_list->num_qs = 1; 4541 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4542 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4543 vmvf_num, cd); 4544 4545 if (status) 4546 break; 4547 ice_free_sched_node(pi, node); 4548 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4549 } 4550 mutex_unlock(&pi->sched_lock); 4551 kfree(qg_list); 4552 return status; 4553 } 4554 4555 /** 4556 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4557 * @pi: port information structure 4558 * @vsi_handle: software VSI handle 4559 * @tc_bitmap: TC bitmap 4560 * @maxqs: max queues array per TC 4561 * @owner: LAN or RDMA 4562 * 4563 * This function adds/updates the VSI queues per TC. 4564 */ 4565 static int 4566 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4567 u16 *maxqs, u8 owner) 4568 { 4569 int status = 0; 4570 u8 i; 4571 4572 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4573 return -EIO; 4574 4575 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4576 return -EINVAL; 4577 4578 mutex_lock(&pi->sched_lock); 4579 4580 ice_for_each_traffic_class(i) { 4581 /* configuration is possible only if TC node is present */ 4582 if (!ice_sched_get_tc_node(pi, i)) 4583 continue; 4584 4585 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4586 ice_is_tc_ena(tc_bitmap, i)); 4587 if (status) 4588 break; 4589 } 4590 4591 mutex_unlock(&pi->sched_lock); 4592 return status; 4593 } 4594 4595 /** 4596 * ice_cfg_vsi_lan - configure VSI LAN queues 4597 * @pi: port information structure 4598 * @vsi_handle: software VSI handle 4599 * @tc_bitmap: TC bitmap 4600 * @max_lanqs: max LAN queues array per TC 4601 * 4602 * This function adds/updates the VSI LAN queues per TC. 4603 */ 4604 int 4605 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4606 u16 *max_lanqs) 4607 { 4608 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4609 ICE_SCHED_NODE_OWNER_LAN); 4610 } 4611 4612 /** 4613 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 4614 * @pi: port information structure 4615 * @vsi_handle: software VSI handle 4616 * @tc_bitmap: TC bitmap 4617 * @max_rdmaqs: max RDMA queues array per TC 4618 * 4619 * This function adds/updates the VSI RDMA queues per TC. 4620 */ 4621 int 4622 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4623 u16 *max_rdmaqs) 4624 { 4625 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_rdmaqs, 4626 ICE_SCHED_NODE_OWNER_RDMA); 4627 } 4628 4629 /** 4630 * ice_ena_vsi_rdma_qset 4631 * @pi: port information structure 4632 * @vsi_handle: software VSI handle 4633 * @tc: TC number 4634 * @rdma_qset: pointer to RDMA Qset 4635 * @num_qsets: number of RDMA Qsets 4636 * @qset_teid: pointer to Qset node TEIDs 4637 * 4638 * This function adds RDMA Qset 4639 */ 4640 int 4641 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4642 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 4643 { 4644 struct ice_aqc_txsched_elem_data node = { 0 }; 4645 struct ice_aqc_add_rdma_qset_data *buf; 4646 struct ice_sched_node *parent; 4647 struct ice_hw *hw; 4648 u16 i, buf_size; 4649 int ret; 4650 4651 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4652 return -EIO; 4653 hw = pi->hw; 4654 4655 if (!ice_is_vsi_valid(hw, vsi_handle)) 4656 return -EINVAL; 4657 4658 buf_size = struct_size(buf, rdma_qsets, num_qsets); 4659 buf = kzalloc(buf_size, GFP_KERNEL); 4660 if (!buf) 4661 return -ENOMEM; 4662 mutex_lock(&pi->sched_lock); 4663 4664 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4665 ICE_SCHED_NODE_OWNER_RDMA); 4666 if (!parent) { 4667 ret = -EINVAL; 4668 goto rdma_error_exit; 4669 } 4670 buf->parent_teid = parent->info.node_teid; 4671 node.parent_teid = parent->info.node_teid; 4672 4673 buf->num_qsets = cpu_to_le16(num_qsets); 4674 for (i = 0; i < num_qsets; i++) { 4675 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 4676 buf->rdma_qsets[i].info.valid_sections = 4677 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4678 ICE_AQC_ELEM_VALID_EIR; 4679 buf->rdma_qsets[i].info.generic = 0; 4680 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 4681 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4682 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 4683 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4684 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 4685 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4686 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 4687 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4688 } 4689 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 4690 if (ret) { 4691 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 4692 goto rdma_error_exit; 4693 } 4694 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4695 for (i = 0; i < num_qsets; i++) { 4696 node.node_teid = buf->rdma_qsets[i].qset_teid; 4697 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 4698 &node); 4699 if (ret) 4700 break; 4701 qset_teid[i] = le32_to_cpu(node.node_teid); 4702 } 4703 rdma_error_exit: 4704 mutex_unlock(&pi->sched_lock); 4705 kfree(buf); 4706 return ret; 4707 } 4708 4709 /** 4710 * ice_dis_vsi_rdma_qset - free RDMA resources 4711 * @pi: port_info struct 4712 * @count: number of RDMA Qsets to free 4713 * @qset_teid: TEID of Qset node 4714 * @q_id: list of queue IDs being disabled 4715 */ 4716 int 4717 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 4718 u16 *q_id) 4719 { 4720 struct ice_aqc_dis_txq_item *qg_list; 4721 struct ice_hw *hw; 4722 int status = 0; 4723 u16 qg_size; 4724 int i; 4725 4726 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4727 return -EIO; 4728 4729 hw = pi->hw; 4730 4731 qg_size = struct_size(qg_list, q_id, 1); 4732 qg_list = kzalloc(qg_size, GFP_KERNEL); 4733 if (!qg_list) 4734 return -ENOMEM; 4735 4736 mutex_lock(&pi->sched_lock); 4737 4738 for (i = 0; i < count; i++) { 4739 struct ice_sched_node *node; 4740 4741 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 4742 if (!node) 4743 continue; 4744 4745 qg_list->parent_teid = node->info.parent_teid; 4746 qg_list->num_qs = 1; 4747 qg_list->q_id[0] = 4748 cpu_to_le16(q_id[i] | 4749 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 4750 4751 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 4752 ICE_NO_RESET, 0, NULL); 4753 if (status) 4754 break; 4755 4756 ice_free_sched_node(pi, node); 4757 } 4758 4759 mutex_unlock(&pi->sched_lock); 4760 kfree(qg_list); 4761 return status; 4762 } 4763 4764 /** 4765 * ice_replay_pre_init - replay pre initialization 4766 * @hw: pointer to the HW struct 4767 * 4768 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4769 */ 4770 static int ice_replay_pre_init(struct ice_hw *hw) 4771 { 4772 struct ice_switch_info *sw = hw->switch_info; 4773 u8 i; 4774 4775 /* Delete old entries from replay filter list head if there is any */ 4776 ice_rm_all_sw_replay_rule_info(hw); 4777 /* In start of replay, move entries into replay_rules list, it 4778 * will allow adding rules entries back to filt_rules list, 4779 * which is operational list. 4780 */ 4781 for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 4782 list_replace_init(&sw->recp_list[i].filt_rules, 4783 &sw->recp_list[i].filt_replay_rules); 4784 ice_sched_replay_agg_vsi_preinit(hw); 4785 4786 return 0; 4787 } 4788 4789 /** 4790 * ice_replay_vsi - replay VSI configuration 4791 * @hw: pointer to the HW struct 4792 * @vsi_handle: driver VSI handle 4793 * 4794 * Restore all VSI configuration after reset. It is required to call this 4795 * function with main VSI first. 4796 */ 4797 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4798 { 4799 int status; 4800 4801 if (!ice_is_vsi_valid(hw, vsi_handle)) 4802 return -EINVAL; 4803 4804 /* Replay pre-initialization if there is any */ 4805 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 4806 status = ice_replay_pre_init(hw); 4807 if (status) 4808 return status; 4809 } 4810 /* Replay per VSI all RSS configurations */ 4811 status = ice_replay_rss_cfg(hw, vsi_handle); 4812 if (status) 4813 return status; 4814 /* Replay per VSI all filters */ 4815 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 4816 if (!status) 4817 status = ice_replay_vsi_agg(hw, vsi_handle); 4818 return status; 4819 } 4820 4821 /** 4822 * ice_replay_post - post replay configuration cleanup 4823 * @hw: pointer to the HW struct 4824 * 4825 * Post replay cleanup. 4826 */ 4827 void ice_replay_post(struct ice_hw *hw) 4828 { 4829 /* Delete old entries from replay filter list head */ 4830 ice_rm_all_sw_replay_rule_info(hw); 4831 ice_sched_replay_agg(hw); 4832 } 4833 4834 /** 4835 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4836 * @hw: ptr to the hardware info 4837 * @reg: offset of 64 bit HW register to read from 4838 * @prev_stat_loaded: bool to specify if previous stats are loaded 4839 * @prev_stat: ptr to previous loaded stat value 4840 * @cur_stat: ptr to current stat value 4841 */ 4842 void 4843 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4844 u64 *prev_stat, u64 *cur_stat) 4845 { 4846 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4847 4848 /* device stats are not reset at PFR, they likely will not be zeroed 4849 * when the driver starts. Thus, save the value from the first read 4850 * without adding to the statistic value so that we report stats which 4851 * count up from zero. 4852 */ 4853 if (!prev_stat_loaded) { 4854 *prev_stat = new_data; 4855 return; 4856 } 4857 4858 /* Calculate the difference between the new and old values, and then 4859 * add it to the software stat value. 4860 */ 4861 if (new_data >= *prev_stat) 4862 *cur_stat += new_data - *prev_stat; 4863 else 4864 /* to manage the potential roll-over */ 4865 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4866 4867 /* Update the previously stored value to prepare for next read */ 4868 *prev_stat = new_data; 4869 } 4870 4871 /** 4872 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4873 * @hw: ptr to the hardware info 4874 * @reg: offset of HW register to read from 4875 * @prev_stat_loaded: bool to specify if previous stats are loaded 4876 * @prev_stat: ptr to previous loaded stat value 4877 * @cur_stat: ptr to current stat value 4878 */ 4879 void 4880 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4881 u64 *prev_stat, u64 *cur_stat) 4882 { 4883 u32 new_data; 4884 4885 new_data = rd32(hw, reg); 4886 4887 /* device stats are not reset at PFR, they likely will not be zeroed 4888 * when the driver starts. Thus, save the value from the first read 4889 * without adding to the statistic value so that we report stats which 4890 * count up from zero. 4891 */ 4892 if (!prev_stat_loaded) { 4893 *prev_stat = new_data; 4894 return; 4895 } 4896 4897 /* Calculate the difference between the new and old values, and then 4898 * add it to the software stat value. 4899 */ 4900 if (new_data >= *prev_stat) 4901 *cur_stat += new_data - *prev_stat; 4902 else 4903 /* to manage the potential roll-over */ 4904 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 4905 4906 /* Update the previously stored value to prepare for next read */ 4907 *prev_stat = new_data; 4908 } 4909 4910 /** 4911 * ice_sched_query_elem - query element information from HW 4912 * @hw: pointer to the HW struct 4913 * @node_teid: node TEID to be queried 4914 * @buf: buffer to element information 4915 * 4916 * This function queries HW element information 4917 */ 4918 int 4919 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4920 struct ice_aqc_txsched_elem_data *buf) 4921 { 4922 u16 buf_size, num_elem_ret = 0; 4923 int status; 4924 4925 buf_size = sizeof(*buf); 4926 memset(buf, 0, buf_size); 4927 buf->node_teid = cpu_to_le32(node_teid); 4928 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 4929 NULL); 4930 if (status || num_elem_ret != 1) 4931 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 4932 return status; 4933 } 4934 4935 /** 4936 * ice_aq_read_i2c 4937 * @hw: pointer to the hw struct 4938 * @topo_addr: topology address for a device to communicate with 4939 * @bus_addr: 7-bit I2C bus address 4940 * @addr: I2C memory address (I2C offset) with up to 16 bits 4941 * @params: I2C parameters: bit [7] - Repeated start, 4942 * bits [6:5] data offset size, 4943 * bit [4] - I2C address type, 4944 * bits [3:0] - data size to read (0-16 bytes) 4945 * @data: pointer to data (0 to 16 bytes) to be read from the I2C device 4946 * @cd: pointer to command details structure or NULL 4947 * 4948 * Read I2C (0x06E2) 4949 */ 4950 int 4951 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 4952 u16 bus_addr, __le16 addr, u8 params, u8 *data, 4953 struct ice_sq_cd *cd) 4954 { 4955 struct ice_aq_desc desc = { 0 }; 4956 struct ice_aqc_i2c *cmd; 4957 u8 data_size; 4958 int status; 4959 4960 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_i2c); 4961 cmd = &desc.params.read_write_i2c; 4962 4963 if (!data) 4964 return -EINVAL; 4965 4966 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 4967 4968 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 4969 cmd->topo_addr = topo_addr; 4970 cmd->i2c_params = params; 4971 cmd->i2c_addr = addr; 4972 4973 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 4974 if (!status) { 4975 struct ice_aqc_read_i2c_resp *resp; 4976 u8 i; 4977 4978 resp = &desc.params.read_i2c_resp; 4979 for (i = 0; i < data_size; i++) { 4980 *data = resp->i2c_data[i]; 4981 data++; 4982 } 4983 } 4984 4985 return status; 4986 } 4987 4988 /** 4989 * ice_aq_write_i2c 4990 * @hw: pointer to the hw struct 4991 * @topo_addr: topology address for a device to communicate with 4992 * @bus_addr: 7-bit I2C bus address 4993 * @addr: I2C memory address (I2C offset) with up to 16 bits 4994 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes) 4995 * @data: pointer to data (0 to 4 bytes) to be written to the I2C device 4996 * @cd: pointer to command details structure or NULL 4997 * 4998 * Write I2C (0x06E3) 4999 * 5000 * * Return: 5001 * * 0 - Successful write to the i2c device 5002 * * -EINVAL - Data size greater than 4 bytes 5003 * * -EIO - FW error 5004 */ 5005 int 5006 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 5007 u16 bus_addr, __le16 addr, u8 params, u8 *data, 5008 struct ice_sq_cd *cd) 5009 { 5010 struct ice_aq_desc desc = { 0 }; 5011 struct ice_aqc_i2c *cmd; 5012 u8 data_size; 5013 5014 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_i2c); 5015 cmd = &desc.params.read_write_i2c; 5016 5017 data_size = FIELD_GET(ICE_AQC_I2C_DATA_SIZE_M, params); 5018 5019 /* data_size limited to 4 */ 5020 if (data_size > 4) 5021 return -EINVAL; 5022 5023 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); 5024 cmd->topo_addr = topo_addr; 5025 cmd->i2c_params = params; 5026 cmd->i2c_addr = addr; 5027 5028 memcpy(cmd->i2c_data, data, data_size); 5029 5030 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5031 } 5032 5033 /** 5034 * ice_aq_set_driver_param - Set driver parameter to share via firmware 5035 * @hw: pointer to the HW struct 5036 * @idx: parameter index to set 5037 * @value: the value to set the parameter to 5038 * @cd: pointer to command details structure or NULL 5039 * 5040 * Set the value of one of the software defined parameters. All PFs connected 5041 * to this device can read the value using ice_aq_get_driver_param. 5042 * 5043 * Note that firmware provides no synchronization or locking, and will not 5044 * save the parameter value during a device reset. It is expected that 5045 * a single PF will write the parameter value, while all other PFs will only 5046 * read it. 5047 */ 5048 int 5049 ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx, 5050 u32 value, struct ice_sq_cd *cd) 5051 { 5052 struct ice_aqc_driver_shared_params *cmd; 5053 struct ice_aq_desc desc; 5054 5055 if (idx >= ICE_AQC_DRIVER_PARAM_MAX) 5056 return -EIO; 5057 5058 cmd = &desc.params.drv_shared_params; 5059 5060 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params); 5061 5062 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_SET; 5063 cmd->param_indx = idx; 5064 cmd->param_val = cpu_to_le32(value); 5065 5066 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5067 } 5068 5069 /** 5070 * ice_aq_get_driver_param - Get driver parameter shared via firmware 5071 * @hw: pointer to the HW struct 5072 * @idx: parameter index to set 5073 * @value: storage to return the shared parameter 5074 * @cd: pointer to command details structure or NULL 5075 * 5076 * Get the value of one of the software defined parameters. 5077 * 5078 * Note that firmware provides no synchronization or locking. It is expected 5079 * that only a single PF will write a given parameter. 5080 */ 5081 int 5082 ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx, 5083 u32 *value, struct ice_sq_cd *cd) 5084 { 5085 struct ice_aqc_driver_shared_params *cmd; 5086 struct ice_aq_desc desc; 5087 int status; 5088 5089 if (idx >= ICE_AQC_DRIVER_PARAM_MAX) 5090 return -EIO; 5091 5092 cmd = &desc.params.drv_shared_params; 5093 5094 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params); 5095 5096 cmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_GET; 5097 cmd->param_indx = idx; 5098 5099 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5100 if (status) 5101 return status; 5102 5103 *value = le32_to_cpu(cmd->param_val); 5104 5105 return 0; 5106 } 5107 5108 /** 5109 * ice_aq_set_gpio 5110 * @hw: pointer to the hw struct 5111 * @gpio_ctrl_handle: GPIO controller node handle 5112 * @pin_idx: IO Number of the GPIO that needs to be set 5113 * @value: SW provide IO value to set in the LSB 5114 * @cd: pointer to command details structure or NULL 5115 * 5116 * Sends 0x06EC AQ command to set the GPIO pin state that's part of the topology 5117 */ 5118 int 5119 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 5120 struct ice_sq_cd *cd) 5121 { 5122 struct ice_aqc_gpio *cmd; 5123 struct ice_aq_desc desc; 5124 5125 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio); 5126 cmd = &desc.params.read_write_gpio; 5127 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5128 cmd->gpio_num = pin_idx; 5129 cmd->gpio_val = value ? 1 : 0; 5130 5131 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5132 } 5133 5134 /** 5135 * ice_aq_get_gpio 5136 * @hw: pointer to the hw struct 5137 * @gpio_ctrl_handle: GPIO controller node handle 5138 * @pin_idx: IO Number of the GPIO that needs to be set 5139 * @value: IO value read 5140 * @cd: pointer to command details structure or NULL 5141 * 5142 * Sends 0x06ED AQ command to get the value of a GPIO signal which is part of 5143 * the topology 5144 */ 5145 int 5146 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 5147 bool *value, struct ice_sq_cd *cd) 5148 { 5149 struct ice_aqc_gpio *cmd; 5150 struct ice_aq_desc desc; 5151 int status; 5152 5153 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio); 5154 cmd = &desc.params.read_write_gpio; 5155 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); 5156 cmd->gpio_num = pin_idx; 5157 5158 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5159 if (status) 5160 return status; 5161 5162 *value = !!cmd->gpio_val; 5163 return 0; 5164 } 5165 5166 /** 5167 * ice_fw_supports_link_override 5168 * @hw: pointer to the hardware structure 5169 * 5170 * Checks if the firmware supports link override 5171 */ 5172 bool ice_fw_supports_link_override(struct ice_hw *hw) 5173 { 5174 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 5175 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 5176 return true; 5177 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 5178 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 5179 return true; 5180 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 5181 return true; 5182 } 5183 5184 return false; 5185 } 5186 5187 /** 5188 * ice_get_link_default_override 5189 * @ldo: pointer to the link default override struct 5190 * @pi: pointer to the port info struct 5191 * 5192 * Gets the link default override for a port 5193 */ 5194 int 5195 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 5196 struct ice_port_info *pi) 5197 { 5198 u16 i, tlv, tlv_len, tlv_start, buf, offset; 5199 struct ice_hw *hw = pi->hw; 5200 int status; 5201 5202 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 5203 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 5204 if (status) { 5205 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 5206 return status; 5207 } 5208 5209 /* Each port has its own config; calculate for our port */ 5210 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 5211 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 5212 5213 /* link options first */ 5214 status = ice_read_sr_word(hw, tlv_start, &buf); 5215 if (status) { 5216 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5217 return status; 5218 } 5219 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 5220 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 5221 ICE_LINK_OVERRIDE_PHY_CFG_S; 5222 5223 /* link PHY config */ 5224 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 5225 status = ice_read_sr_word(hw, offset, &buf); 5226 if (status) { 5227 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 5228 return status; 5229 } 5230 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 5231 5232 /* PHY types low */ 5233 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 5234 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5235 status = ice_read_sr_word(hw, (offset + i), &buf); 5236 if (status) { 5237 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5238 return status; 5239 } 5240 /* shift 16 bits at a time to fill 64 bits */ 5241 ldo->phy_type_low |= ((u64)buf << (i * 16)); 5242 } 5243 5244 /* PHY types high */ 5245 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 5246 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 5247 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 5248 status = ice_read_sr_word(hw, (offset + i), &buf); 5249 if (status) { 5250 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 5251 return status; 5252 } 5253 /* shift 16 bits at a time to fill 64 bits */ 5254 ldo->phy_type_high |= ((u64)buf << (i * 16)); 5255 } 5256 5257 return status; 5258 } 5259 5260 /** 5261 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 5262 * @caps: get PHY capability data 5263 */ 5264 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 5265 { 5266 if (caps->caps & ICE_AQC_PHY_AN_MODE || 5267 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 5268 ICE_AQC_PHY_AN_EN_CLAUSE73 | 5269 ICE_AQC_PHY_AN_EN_CLAUSE37)) 5270 return true; 5271 5272 return false; 5273 } 5274 5275 /** 5276 * ice_aq_set_lldp_mib - Set the LLDP MIB 5277 * @hw: pointer to the HW struct 5278 * @mib_type: Local, Remote or both Local and Remote MIBs 5279 * @buf: pointer to the caller-supplied buffer to store the MIB block 5280 * @buf_size: size of the buffer (in bytes) 5281 * @cd: pointer to command details structure or NULL 5282 * 5283 * Set the LLDP MIB. (0x0A08) 5284 */ 5285 int 5286 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 5287 struct ice_sq_cd *cd) 5288 { 5289 struct ice_aqc_lldp_set_local_mib *cmd; 5290 struct ice_aq_desc desc; 5291 5292 cmd = &desc.params.lldp_set_mib; 5293 5294 if (buf_size == 0 || !buf) 5295 return -EINVAL; 5296 5297 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 5298 5299 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 5300 desc.datalen = cpu_to_le16(buf_size); 5301 5302 cmd->type = mib_type; 5303 cmd->length = cpu_to_le16(buf_size); 5304 5305 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 5306 } 5307 5308 /** 5309 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 5310 * @hw: pointer to HW struct 5311 */ 5312 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 5313 { 5314 if (hw->mac_type != ICE_MAC_E810) 5315 return false; 5316 5317 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) { 5318 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN) 5319 return true; 5320 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN && 5321 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH) 5322 return true; 5323 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) { 5324 return true; 5325 } 5326 return false; 5327 } 5328 5329 /** 5330 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 5331 * @hw: pointer to HW struct 5332 * @vsi_num: absolute HW index for VSI 5333 * @add: boolean for if adding or removing a filter 5334 */ 5335 int 5336 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 5337 { 5338 struct ice_aqc_lldp_filter_ctrl *cmd; 5339 struct ice_aq_desc desc; 5340 5341 cmd = &desc.params.lldp_filter_ctrl; 5342 5343 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 5344 5345 if (add) 5346 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 5347 else 5348 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 5349 5350 cmd->vsi_num = cpu_to_le16(vsi_num); 5351 5352 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5353 } 5354 5355 /** 5356 * ice_fw_supports_report_dflt_cfg 5357 * @hw: pointer to the hardware structure 5358 * 5359 * Checks if the firmware supports report default configuration 5360 */ 5361 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 5362 { 5363 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5364 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN) 5365 return true; 5366 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN && 5367 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH) 5368 return true; 5369 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5370 return true; 5371 } 5372 return false; 5373 } 5374