1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_lib.h" 6 #include "ice_sched.h" 7 #include "ice_adminq_cmd.h" 8 #include "ice_flow.h" 9 10 #define ICE_PF_RESET_WAIT_COUNT 300 11 12 /** 13 * ice_set_mac_type - Sets MAC type 14 * @hw: pointer to the HW structure 15 * 16 * This function sets the MAC type of the adapter based on the 17 * vendor ID and device ID stored in the HW structure. 18 */ 19 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 20 { 21 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 22 return ICE_ERR_DEVICE_NOT_SUPPORTED; 23 24 switch (hw->device_id) { 25 case ICE_DEV_ID_E810C_BACKPLANE: 26 case ICE_DEV_ID_E810C_QSFP: 27 case ICE_DEV_ID_E810C_SFP: 28 case ICE_DEV_ID_E810_XXV_SFP: 29 hw->mac_type = ICE_MAC_E810; 30 break; 31 case ICE_DEV_ID_E823C_10G_BASE_T: 32 case ICE_DEV_ID_E823C_BACKPLANE: 33 case ICE_DEV_ID_E823C_QSFP: 34 case ICE_DEV_ID_E823C_SFP: 35 case ICE_DEV_ID_E823C_SGMII: 36 case ICE_DEV_ID_E822C_10G_BASE_T: 37 case ICE_DEV_ID_E822C_BACKPLANE: 38 case ICE_DEV_ID_E822C_QSFP: 39 case ICE_DEV_ID_E822C_SFP: 40 case ICE_DEV_ID_E822C_SGMII: 41 case ICE_DEV_ID_E822L_10G_BASE_T: 42 case ICE_DEV_ID_E822L_BACKPLANE: 43 case ICE_DEV_ID_E822L_SFP: 44 case ICE_DEV_ID_E822L_SGMII: 45 case ICE_DEV_ID_E823L_10G_BASE_T: 46 case ICE_DEV_ID_E823L_1GBE: 47 case ICE_DEV_ID_E823L_BACKPLANE: 48 case ICE_DEV_ID_E823L_QSFP: 49 case ICE_DEV_ID_E823L_SFP: 50 hw->mac_type = ICE_MAC_GENERIC; 51 break; 52 default: 53 hw->mac_type = ICE_MAC_UNKNOWN; 54 break; 55 } 56 57 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 58 return 0; 59 } 60 61 /** 62 * ice_clear_pf_cfg - Clear PF configuration 63 * @hw: pointer to the hardware structure 64 * 65 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 66 * configuration, flow director filters, etc.). 67 */ 68 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 69 { 70 struct ice_aq_desc desc; 71 72 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 73 74 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 75 } 76 77 /** 78 * ice_aq_manage_mac_read - manage MAC address read command 79 * @hw: pointer to the HW struct 80 * @buf: a virtual buffer to hold the manage MAC read response 81 * @buf_size: Size of the virtual buffer 82 * @cd: pointer to command details structure or NULL 83 * 84 * This function is used to return per PF station MAC address (0x0107). 85 * NOTE: Upon successful completion of this command, MAC address information 86 * is returned in user specified buffer. Please interpret user specified 87 * buffer as "manage_mac_read" response. 88 * Response such as various MAC addresses are stored in HW struct (port.mac) 89 * ice_discover_dev_caps is expected to be called before this function is 90 * called. 91 */ 92 static enum ice_status 93 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 94 struct ice_sq_cd *cd) 95 { 96 struct ice_aqc_manage_mac_read_resp *resp; 97 struct ice_aqc_manage_mac_read *cmd; 98 struct ice_aq_desc desc; 99 enum ice_status status; 100 u16 flags; 101 u8 i; 102 103 cmd = &desc.params.mac_read; 104 105 if (buf_size < sizeof(*resp)) 106 return ICE_ERR_BUF_TOO_SHORT; 107 108 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 109 110 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 111 if (status) 112 return status; 113 114 resp = buf; 115 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 116 117 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 118 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 119 return ICE_ERR_CFG; 120 } 121 122 /* A single port can report up to two (LAN and WoL) addresses */ 123 for (i = 0; i < cmd->num_addr; i++) 124 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 125 ether_addr_copy(hw->port_info->mac.lan_addr, 126 resp[i].mac_addr); 127 ether_addr_copy(hw->port_info->mac.perm_addr, 128 resp[i].mac_addr); 129 break; 130 } 131 132 return 0; 133 } 134 135 /** 136 * ice_aq_get_phy_caps - returns PHY capabilities 137 * @pi: port information structure 138 * @qual_mods: report qualified modules 139 * @report_mode: report mode capabilities 140 * @pcaps: structure for PHY capabilities to be filled 141 * @cd: pointer to command details structure or NULL 142 * 143 * Returns the various PHY capabilities supported on the Port (0x0600) 144 */ 145 enum ice_status 146 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 147 struct ice_aqc_get_phy_caps_data *pcaps, 148 struct ice_sq_cd *cd) 149 { 150 struct ice_aqc_get_phy_caps *cmd; 151 u16 pcaps_size = sizeof(*pcaps); 152 struct ice_aq_desc desc; 153 enum ice_status status; 154 struct ice_hw *hw; 155 156 cmd = &desc.params.get_phy; 157 158 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 159 return ICE_ERR_PARAM; 160 hw = pi->hw; 161 162 if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 163 !ice_fw_supports_report_dflt_cfg(hw)) 164 return ICE_ERR_PARAM; 165 166 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 167 168 if (qual_mods) 169 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 170 171 cmd->param0 |= cpu_to_le16(report_mode); 172 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 173 174 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 175 report_mode); 176 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 177 (unsigned long long)le64_to_cpu(pcaps->phy_type_low)); 178 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 179 (unsigned long long)le64_to_cpu(pcaps->phy_type_high)); 180 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 181 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 182 pcaps->low_power_ctrl_an); 183 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 184 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 185 pcaps->eeer_value); 186 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 187 pcaps->link_fec_options); 188 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 189 pcaps->module_compliance_enforcement); 190 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 191 pcaps->extended_compliance_code); 192 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 193 pcaps->module_type[0]); 194 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 195 pcaps->module_type[1]); 196 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 197 pcaps->module_type[2]); 198 199 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 200 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 201 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 202 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 203 sizeof(pi->phy.link_info.module_type)); 204 } 205 206 return status; 207 } 208 209 /** 210 * ice_aq_get_link_topo_handle - get link topology node return status 211 * @pi: port information structure 212 * @node_type: requested node type 213 * @cd: pointer to command details structure or NULL 214 * 215 * Get link topology node return status for specified node type (0x06E0) 216 * 217 * Node type cage can be used to determine if cage is present. If AQC 218 * returns error (ENOENT), then no cage present. If no cage present, then 219 * connection type is backplane or BASE-T. 220 */ 221 static enum ice_status 222 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 223 struct ice_sq_cd *cd) 224 { 225 struct ice_aqc_get_link_topo *cmd; 226 struct ice_aq_desc desc; 227 228 cmd = &desc.params.get_link_topo; 229 230 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 231 232 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 233 ICE_AQC_LINK_TOPO_NODE_CTX_S); 234 235 /* set node type */ 236 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 237 238 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 239 } 240 241 /** 242 * ice_is_media_cage_present 243 * @pi: port information structure 244 * 245 * Returns true if media cage is present, else false. If no cage, then 246 * media type is backplane or BASE-T. 247 */ 248 static bool ice_is_media_cage_present(struct ice_port_info *pi) 249 { 250 /* Node type cage can be used to determine if cage is present. If AQC 251 * returns error (ENOENT), then no cage present. If no cage present then 252 * connection type is backplane or BASE-T. 253 */ 254 return !ice_aq_get_link_topo_handle(pi, 255 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 256 NULL); 257 } 258 259 /** 260 * ice_get_media_type - Gets media type 261 * @pi: port information structure 262 */ 263 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 264 { 265 struct ice_link_status *hw_link_info; 266 267 if (!pi) 268 return ICE_MEDIA_UNKNOWN; 269 270 hw_link_info = &pi->phy.link_info; 271 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 272 /* If more than one media type is selected, report unknown */ 273 return ICE_MEDIA_UNKNOWN; 274 275 if (hw_link_info->phy_type_low) { 276 /* 1G SGMII is a special case where some DA cable PHYs 277 * may show this as an option when it really shouldn't 278 * be since SGMII is meant to be between a MAC and a PHY 279 * in a backplane. Try to detect this case and handle it 280 */ 281 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 282 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 283 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 284 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 285 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 286 return ICE_MEDIA_DA; 287 288 switch (hw_link_info->phy_type_low) { 289 case ICE_PHY_TYPE_LOW_1000BASE_SX: 290 case ICE_PHY_TYPE_LOW_1000BASE_LX: 291 case ICE_PHY_TYPE_LOW_10GBASE_SR: 292 case ICE_PHY_TYPE_LOW_10GBASE_LR: 293 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 294 case ICE_PHY_TYPE_LOW_25GBASE_SR: 295 case ICE_PHY_TYPE_LOW_25GBASE_LR: 296 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 297 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 298 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 299 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 300 case ICE_PHY_TYPE_LOW_50GBASE_SR: 301 case ICE_PHY_TYPE_LOW_50GBASE_FR: 302 case ICE_PHY_TYPE_LOW_50GBASE_LR: 303 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 304 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 305 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 306 case ICE_PHY_TYPE_LOW_100GBASE_DR: 307 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 308 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 309 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 310 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 311 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 312 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 313 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 314 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 315 return ICE_MEDIA_FIBER; 316 case ICE_PHY_TYPE_LOW_100BASE_TX: 317 case ICE_PHY_TYPE_LOW_1000BASE_T: 318 case ICE_PHY_TYPE_LOW_2500BASE_T: 319 case ICE_PHY_TYPE_LOW_5GBASE_T: 320 case ICE_PHY_TYPE_LOW_10GBASE_T: 321 case ICE_PHY_TYPE_LOW_25GBASE_T: 322 return ICE_MEDIA_BASET; 323 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 324 case ICE_PHY_TYPE_LOW_25GBASE_CR: 325 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 326 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 327 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 328 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 329 case ICE_PHY_TYPE_LOW_50GBASE_CP: 330 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 331 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 332 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 333 return ICE_MEDIA_DA; 334 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 335 case ICE_PHY_TYPE_LOW_40G_XLAUI: 336 case ICE_PHY_TYPE_LOW_50G_LAUI2: 337 case ICE_PHY_TYPE_LOW_50G_AUI2: 338 case ICE_PHY_TYPE_LOW_50G_AUI1: 339 case ICE_PHY_TYPE_LOW_100G_AUI4: 340 case ICE_PHY_TYPE_LOW_100G_CAUI4: 341 if (ice_is_media_cage_present(pi)) 342 return ICE_MEDIA_DA; 343 fallthrough; 344 case ICE_PHY_TYPE_LOW_1000BASE_KX: 345 case ICE_PHY_TYPE_LOW_2500BASE_KX: 346 case ICE_PHY_TYPE_LOW_2500BASE_X: 347 case ICE_PHY_TYPE_LOW_5GBASE_KR: 348 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 349 case ICE_PHY_TYPE_LOW_25GBASE_KR: 350 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 351 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 352 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 353 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 354 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 355 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 356 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 357 return ICE_MEDIA_BACKPLANE; 358 } 359 } else { 360 switch (hw_link_info->phy_type_high) { 361 case ICE_PHY_TYPE_HIGH_100G_AUI2: 362 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 363 if (ice_is_media_cage_present(pi)) 364 return ICE_MEDIA_DA; 365 fallthrough; 366 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 367 return ICE_MEDIA_BACKPLANE; 368 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 369 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 370 return ICE_MEDIA_FIBER; 371 } 372 } 373 return ICE_MEDIA_UNKNOWN; 374 } 375 376 /** 377 * ice_aq_get_link_info 378 * @pi: port information structure 379 * @ena_lse: enable/disable LinkStatusEvent reporting 380 * @link: pointer to link status structure - optional 381 * @cd: pointer to command details structure or NULL 382 * 383 * Get Link Status (0x607). Returns the link status of the adapter. 384 */ 385 enum ice_status 386 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 387 struct ice_link_status *link, struct ice_sq_cd *cd) 388 { 389 struct ice_aqc_get_link_status_data link_data = { 0 }; 390 struct ice_aqc_get_link_status *resp; 391 struct ice_link_status *li_old, *li; 392 enum ice_media_type *hw_media_type; 393 struct ice_fc_info *hw_fc_info; 394 bool tx_pause, rx_pause; 395 struct ice_aq_desc desc; 396 enum ice_status status; 397 struct ice_hw *hw; 398 u16 cmd_flags; 399 400 if (!pi) 401 return ICE_ERR_PARAM; 402 hw = pi->hw; 403 li_old = &pi->phy.link_info_old; 404 hw_media_type = &pi->phy.media_type; 405 li = &pi->phy.link_info; 406 hw_fc_info = &pi->fc; 407 408 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 409 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 410 resp = &desc.params.get_link_status; 411 resp->cmd_flags = cpu_to_le16(cmd_flags); 412 resp->lport_num = pi->lport; 413 414 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 415 416 if (status) 417 return status; 418 419 /* save off old link status information */ 420 *li_old = *li; 421 422 /* update current link status information */ 423 li->link_speed = le16_to_cpu(link_data.link_speed); 424 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 425 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 426 *hw_media_type = ice_get_media_type(pi); 427 li->link_info = link_data.link_info; 428 li->an_info = link_data.an_info; 429 li->ext_info = link_data.ext_info; 430 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 431 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 432 li->topo_media_conflict = link_data.topo_media_conflict; 433 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 434 ICE_AQ_CFG_PACING_TYPE_M); 435 436 /* update fc info */ 437 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 438 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 439 if (tx_pause && rx_pause) 440 hw_fc_info->current_mode = ICE_FC_FULL; 441 else if (tx_pause) 442 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 443 else if (rx_pause) 444 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 445 else 446 hw_fc_info->current_mode = ICE_FC_NONE; 447 448 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 449 450 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 451 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 452 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 453 (unsigned long long)li->phy_type_low); 454 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 455 (unsigned long long)li->phy_type_high); 456 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 457 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 458 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 459 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 460 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 461 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 462 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 463 li->max_frame_size); 464 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 465 466 /* save link status information */ 467 if (link) 468 *link = *li; 469 470 /* flag cleared so calling functions don't call AQ again */ 471 pi->phy.get_link_info = false; 472 473 return 0; 474 } 475 476 /** 477 * ice_fill_tx_timer_and_fc_thresh 478 * @hw: pointer to the HW struct 479 * @cmd: pointer to MAC cfg structure 480 * 481 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 482 * descriptor 483 */ 484 static void 485 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 486 struct ice_aqc_set_mac_cfg *cmd) 487 { 488 u16 fc_thres_val, tx_timer_val; 489 u32 val; 490 491 /* We read back the transmit timer and FC threshold value of 492 * LFC. Thus, we will use index = 493 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 494 * 495 * Also, because we are operating on transmit timer and FC 496 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 497 */ 498 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 499 500 /* Retrieve the transmit timer */ 501 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 502 tx_timer_val = val & 503 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 504 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val); 505 506 /* Retrieve the FC threshold */ 507 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 508 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 509 510 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val); 511 } 512 513 /** 514 * ice_aq_set_mac_cfg 515 * @hw: pointer to the HW struct 516 * @max_frame_size: Maximum Frame Size to be supported 517 * @cd: pointer to command details structure or NULL 518 * 519 * Set MAC configuration (0x0603) 520 */ 521 enum ice_status 522 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 523 { 524 struct ice_aqc_set_mac_cfg *cmd; 525 struct ice_aq_desc desc; 526 527 cmd = &desc.params.set_mac_cfg; 528 529 if (max_frame_size == 0) 530 return ICE_ERR_PARAM; 531 532 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 533 534 cmd->max_frame_size = cpu_to_le16(max_frame_size); 535 536 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 537 538 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 539 } 540 541 /** 542 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 543 * @hw: pointer to the HW struct 544 */ 545 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 546 { 547 struct ice_switch_info *sw; 548 enum ice_status status; 549 550 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 551 sizeof(*hw->switch_info), GFP_KERNEL); 552 sw = hw->switch_info; 553 554 if (!sw) 555 return ICE_ERR_NO_MEMORY; 556 557 INIT_LIST_HEAD(&sw->vsi_list_map_head); 558 559 status = ice_init_def_sw_recp(hw); 560 if (status) { 561 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 562 return status; 563 } 564 return 0; 565 } 566 567 /** 568 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 569 * @hw: pointer to the HW struct 570 */ 571 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 572 { 573 struct ice_switch_info *sw = hw->switch_info; 574 struct ice_vsi_list_map_info *v_pos_map; 575 struct ice_vsi_list_map_info *v_tmp_map; 576 struct ice_sw_recipe *recps; 577 u8 i; 578 579 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 580 list_entry) { 581 list_del(&v_pos_map->list_entry); 582 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 583 } 584 recps = hw->switch_info->recp_list; 585 for (i = 0; i < ICE_SW_LKUP_LAST; i++) { 586 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 587 588 recps[i].root_rid = i; 589 mutex_destroy(&recps[i].filt_rule_lock); 590 list_for_each_entry_safe(lst_itr, tmp_entry, 591 &recps[i].filt_rules, list_entry) { 592 list_del(&lst_itr->list_entry); 593 devm_kfree(ice_hw_to_dev(hw), lst_itr); 594 } 595 } 596 ice_rm_all_sw_replay_rule_info(hw); 597 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 598 devm_kfree(ice_hw_to_dev(hw), sw); 599 } 600 601 /** 602 * ice_get_fw_log_cfg - get FW logging configuration 603 * @hw: pointer to the HW struct 604 */ 605 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw) 606 { 607 struct ice_aq_desc desc; 608 enum ice_status status; 609 __le16 *config; 610 u16 size; 611 612 size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX; 613 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL); 614 if (!config) 615 return ICE_ERR_NO_MEMORY; 616 617 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 618 619 status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 620 if (!status) { 621 u16 i; 622 623 /* Save FW logging information into the HW structure */ 624 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 625 u16 v, m, flgs; 626 627 v = le16_to_cpu(config[i]); 628 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 629 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 630 631 if (m < ICE_AQC_FW_LOG_ID_MAX) 632 hw->fw_log.evnts[m].cur = flgs; 633 } 634 } 635 636 devm_kfree(ice_hw_to_dev(hw), config); 637 638 return status; 639 } 640 641 /** 642 * ice_cfg_fw_log - configure FW logging 643 * @hw: pointer to the HW struct 644 * @enable: enable certain FW logging events if true, disable all if false 645 * 646 * This function enables/disables the FW logging via Rx CQ events and a UART 647 * port based on predetermined configurations. FW logging via the Rx CQ can be 648 * enabled/disabled for individual PF's. However, FW logging via the UART can 649 * only be enabled/disabled for all PFs on the same device. 650 * 651 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 652 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 653 * before initializing the device. 654 * 655 * When re/configuring FW logging, callers need to update the "cfg" elements of 656 * the hw->fw_log.evnts array with the desired logging event configurations for 657 * modules of interest. When disabling FW logging completely, the callers can 658 * just pass false in the "enable" parameter. On completion, the function will 659 * update the "cur" element of the hw->fw_log.evnts array with the resulting 660 * logging event configurations of the modules that are being re/configured. FW 661 * logging modules that are not part of a reconfiguration operation retain their 662 * previous states. 663 * 664 * Before resetting the device, it is recommended that the driver disables FW 665 * logging before shutting down the control queue. When disabling FW logging 666 * ("enable" = false), the latest configurations of FW logging events stored in 667 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 668 * a device reset. 669 * 670 * When enabling FW logging to emit log messages via the Rx CQ during the 671 * device's initialization phase, a mechanism alternative to interrupt handlers 672 * needs to be used to extract FW log messages from the Rx CQ periodically and 673 * to prevent the Rx CQ from being full and stalling other types of control 674 * messages from FW to SW. Interrupts are typically disabled during the device's 675 * initialization phase. 676 */ 677 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable) 678 { 679 struct ice_aqc_fw_logging *cmd; 680 enum ice_status status = 0; 681 u16 i, chgs = 0, len = 0; 682 struct ice_aq_desc desc; 683 __le16 *data = NULL; 684 u8 actv_evnts = 0; 685 void *buf = NULL; 686 687 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 688 return 0; 689 690 /* Disable FW logging only when the control queue is still responsive */ 691 if (!enable && 692 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 693 return 0; 694 695 /* Get current FW log settings */ 696 status = ice_get_fw_log_cfg(hw); 697 if (status) 698 return status; 699 700 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 701 cmd = &desc.params.fw_logging; 702 703 /* Indicate which controls are valid */ 704 if (hw->fw_log.cq_en) 705 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 706 707 if (hw->fw_log.uart_en) 708 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 709 710 if (enable) { 711 /* Fill in an array of entries with FW logging modules and 712 * logging events being reconfigured. 713 */ 714 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 715 u16 val; 716 717 /* Keep track of enabled event types */ 718 actv_evnts |= hw->fw_log.evnts[i].cfg; 719 720 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 721 continue; 722 723 if (!data) { 724 data = devm_kcalloc(ice_hw_to_dev(hw), 725 ICE_AQC_FW_LOG_ID_MAX, 726 sizeof(*data), 727 GFP_KERNEL); 728 if (!data) 729 return ICE_ERR_NO_MEMORY; 730 } 731 732 val = i << ICE_AQC_FW_LOG_ID_S; 733 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 734 data[chgs++] = cpu_to_le16(val); 735 } 736 737 /* Only enable FW logging if at least one module is specified. 738 * If FW logging is currently enabled but all modules are not 739 * enabled to emit log messages, disable FW logging altogether. 740 */ 741 if (actv_evnts) { 742 /* Leave if there is effectively no change */ 743 if (!chgs) 744 goto out; 745 746 if (hw->fw_log.cq_en) 747 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 748 749 if (hw->fw_log.uart_en) 750 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 751 752 buf = data; 753 len = sizeof(*data) * chgs; 754 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 755 } 756 } 757 758 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 759 if (!status) { 760 /* Update the current configuration to reflect events enabled. 761 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 762 * logging mode is enabled for the device. They do not reflect 763 * actual modules being enabled to emit log messages. So, their 764 * values remain unchanged even when all modules are disabled. 765 */ 766 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 767 768 hw->fw_log.actv_evnts = actv_evnts; 769 for (i = 0; i < cnt; i++) { 770 u16 v, m; 771 772 if (!enable) { 773 /* When disabling all FW logging events as part 774 * of device's de-initialization, the original 775 * configurations are retained, and can be used 776 * to reconfigure FW logging later if the device 777 * is re-initialized. 778 */ 779 hw->fw_log.evnts[i].cur = 0; 780 continue; 781 } 782 783 v = le16_to_cpu(data[i]); 784 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 785 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 786 } 787 } 788 789 out: 790 if (data) 791 devm_kfree(ice_hw_to_dev(hw), data); 792 793 return status; 794 } 795 796 /** 797 * ice_output_fw_log 798 * @hw: pointer to the HW struct 799 * @desc: pointer to the AQ message descriptor 800 * @buf: pointer to the buffer accompanying the AQ message 801 * 802 * Formats a FW Log message and outputs it via the standard driver logs. 803 */ 804 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 805 { 806 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 807 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 808 le16_to_cpu(desc->datalen)); 809 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 810 } 811 812 /** 813 * ice_get_itr_intrl_gran 814 * @hw: pointer to the HW struct 815 * 816 * Determines the ITR/INTRL granularities based on the maximum aggregate 817 * bandwidth according to the device's configuration during power-on. 818 */ 819 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 820 { 821 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 822 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 823 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 824 825 switch (max_agg_bw) { 826 case ICE_MAX_AGG_BW_200G: 827 case ICE_MAX_AGG_BW_100G: 828 case ICE_MAX_AGG_BW_50G: 829 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 830 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 831 break; 832 case ICE_MAX_AGG_BW_25G: 833 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 834 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 835 break; 836 } 837 } 838 839 /** 840 * ice_init_hw - main hardware initialization routine 841 * @hw: pointer to the hardware structure 842 */ 843 enum ice_status ice_init_hw(struct ice_hw *hw) 844 { 845 struct ice_aqc_get_phy_caps_data *pcaps; 846 enum ice_status status; 847 u16 mac_buf_len; 848 void *mac_buf; 849 850 /* Set MAC type based on DeviceID */ 851 status = ice_set_mac_type(hw); 852 if (status) 853 return status; 854 855 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 856 PF_FUNC_RID_FUNC_NUM_M) >> 857 PF_FUNC_RID_FUNC_NUM_S; 858 859 status = ice_reset(hw, ICE_RESET_PFR); 860 if (status) 861 return status; 862 863 ice_get_itr_intrl_gran(hw); 864 865 status = ice_create_all_ctrlq(hw); 866 if (status) 867 goto err_unroll_cqinit; 868 869 /* Enable FW logging. Not fatal if this fails. */ 870 status = ice_cfg_fw_log(hw, true); 871 if (status) 872 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 873 874 status = ice_clear_pf_cfg(hw); 875 if (status) 876 goto err_unroll_cqinit; 877 878 /* Set bit to enable Flow Director filters */ 879 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 880 INIT_LIST_HEAD(&hw->fdir_list_head); 881 882 ice_clear_pxe_mode(hw); 883 884 status = ice_init_nvm(hw); 885 if (status) 886 goto err_unroll_cqinit; 887 888 status = ice_get_caps(hw); 889 if (status) 890 goto err_unroll_cqinit; 891 892 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 893 sizeof(*hw->port_info), GFP_KERNEL); 894 if (!hw->port_info) { 895 status = ICE_ERR_NO_MEMORY; 896 goto err_unroll_cqinit; 897 } 898 899 /* set the back pointer to HW */ 900 hw->port_info->hw = hw; 901 902 /* Initialize port_info struct with switch configuration data */ 903 status = ice_get_initial_sw_cfg(hw); 904 if (status) 905 goto err_unroll_alloc; 906 907 hw->evb_veb = true; 908 909 /* Query the allocated resources for Tx scheduler */ 910 status = ice_sched_query_res_alloc(hw); 911 if (status) { 912 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 913 goto err_unroll_alloc; 914 } 915 ice_sched_get_psm_clk_freq(hw); 916 917 /* Initialize port_info struct with scheduler data */ 918 status = ice_sched_init_port(hw->port_info); 919 if (status) 920 goto err_unroll_sched; 921 922 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 923 if (!pcaps) { 924 status = ICE_ERR_NO_MEMORY; 925 goto err_unroll_sched; 926 } 927 928 /* Initialize port_info struct with PHY capabilities */ 929 status = ice_aq_get_phy_caps(hw->port_info, false, 930 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, 931 NULL); 932 devm_kfree(ice_hw_to_dev(hw), pcaps); 933 if (status) 934 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 935 status); 936 937 /* Initialize port_info struct with link information */ 938 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 939 if (status) 940 goto err_unroll_sched; 941 942 /* need a valid SW entry point to build a Tx tree */ 943 if (!hw->sw_entry_point_layer) { 944 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 945 status = ICE_ERR_CFG; 946 goto err_unroll_sched; 947 } 948 INIT_LIST_HEAD(&hw->agg_list); 949 /* Initialize max burst size */ 950 if (!hw->max_burst_size) 951 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 952 953 status = ice_init_fltr_mgmt_struct(hw); 954 if (status) 955 goto err_unroll_sched; 956 957 /* Get MAC information */ 958 /* A single port can report up to two (LAN and WoL) addresses */ 959 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 960 sizeof(struct ice_aqc_manage_mac_read_resp), 961 GFP_KERNEL); 962 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 963 964 if (!mac_buf) { 965 status = ICE_ERR_NO_MEMORY; 966 goto err_unroll_fltr_mgmt_struct; 967 } 968 969 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 970 devm_kfree(ice_hw_to_dev(hw), mac_buf); 971 972 if (status) 973 goto err_unroll_fltr_mgmt_struct; 974 /* enable jumbo frame support at MAC level */ 975 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 976 if (status) 977 goto err_unroll_fltr_mgmt_struct; 978 /* Obtain counter base index which would be used by flow director */ 979 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 980 if (status) 981 goto err_unroll_fltr_mgmt_struct; 982 status = ice_init_hw_tbls(hw); 983 if (status) 984 goto err_unroll_fltr_mgmt_struct; 985 mutex_init(&hw->tnl_lock); 986 return 0; 987 988 err_unroll_fltr_mgmt_struct: 989 ice_cleanup_fltr_mgmt_struct(hw); 990 err_unroll_sched: 991 ice_sched_cleanup_all(hw); 992 err_unroll_alloc: 993 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 994 err_unroll_cqinit: 995 ice_destroy_all_ctrlq(hw); 996 return status; 997 } 998 999 /** 1000 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 1001 * @hw: pointer to the hardware structure 1002 * 1003 * This should be called only during nominal operation, not as a result of 1004 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 1005 * applicable initializations if it fails for any reason. 1006 */ 1007 void ice_deinit_hw(struct ice_hw *hw) 1008 { 1009 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1010 ice_cleanup_fltr_mgmt_struct(hw); 1011 1012 ice_sched_cleanup_all(hw); 1013 ice_sched_clear_agg(hw); 1014 ice_free_seg(hw); 1015 ice_free_hw_tbls(hw); 1016 mutex_destroy(&hw->tnl_lock); 1017 1018 if (hw->port_info) { 1019 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1020 hw->port_info = NULL; 1021 } 1022 1023 /* Attempt to disable FW logging before shutting down control queues */ 1024 ice_cfg_fw_log(hw, false); 1025 ice_destroy_all_ctrlq(hw); 1026 1027 /* Clear VSI contexts if not already cleared */ 1028 ice_clear_all_vsi_ctx(hw); 1029 } 1030 1031 /** 1032 * ice_check_reset - Check to see if a global reset is complete 1033 * @hw: pointer to the hardware structure 1034 */ 1035 enum ice_status ice_check_reset(struct ice_hw *hw) 1036 { 1037 u32 cnt, reg = 0, grst_timeout, uld_mask; 1038 1039 /* Poll for Device Active state in case a recent CORER, GLOBR, 1040 * or EMPR has occurred. The grst delay value is in 100ms units. 1041 * Add 1sec for outstanding AQ commands that can take a long time. 1042 */ 1043 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1044 GLGEN_RSTCTL_GRSTDEL_S) + 10; 1045 1046 for (cnt = 0; cnt < grst_timeout; cnt++) { 1047 mdelay(100); 1048 reg = rd32(hw, GLGEN_RSTAT); 1049 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1050 break; 1051 } 1052 1053 if (cnt == grst_timeout) { 1054 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1055 return ICE_ERR_RESET_FAILED; 1056 } 1057 1058 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1059 GLNVM_ULD_PCIER_DONE_1_M |\ 1060 GLNVM_ULD_CORER_DONE_M |\ 1061 GLNVM_ULD_GLOBR_DONE_M |\ 1062 GLNVM_ULD_POR_DONE_M |\ 1063 GLNVM_ULD_POR_DONE_1_M |\ 1064 GLNVM_ULD_PCIER_DONE_2_M) 1065 1066 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? 1067 GLNVM_ULD_PE_DONE_M : 0); 1068 1069 /* Device is Active; check Global Reset processes are done */ 1070 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1071 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1072 if (reg == uld_mask) { 1073 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1074 break; 1075 } 1076 mdelay(10); 1077 } 1078 1079 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1080 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1081 reg); 1082 return ICE_ERR_RESET_FAILED; 1083 } 1084 1085 return 0; 1086 } 1087 1088 /** 1089 * ice_pf_reset - Reset the PF 1090 * @hw: pointer to the hardware structure 1091 * 1092 * If a global reset has been triggered, this function checks 1093 * for its completion and then issues the PF reset 1094 */ 1095 static enum ice_status ice_pf_reset(struct ice_hw *hw) 1096 { 1097 u32 cnt, reg; 1098 1099 /* If at function entry a global reset was already in progress, i.e. 1100 * state is not 'device active' or any of the reset done bits are not 1101 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1102 * global reset is done. 1103 */ 1104 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1105 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1106 /* poll on global reset currently in progress until done */ 1107 if (ice_check_reset(hw)) 1108 return ICE_ERR_RESET_FAILED; 1109 1110 return 0; 1111 } 1112 1113 /* Reset the PF */ 1114 reg = rd32(hw, PFGEN_CTRL); 1115 1116 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1117 1118 /* Wait for the PFR to complete. The wait time is the global config lock 1119 * timeout plus the PFR timeout which will account for a possible reset 1120 * that is occurring during a download package operation. 1121 */ 1122 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1123 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1124 reg = rd32(hw, PFGEN_CTRL); 1125 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1126 break; 1127 1128 mdelay(1); 1129 } 1130 1131 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1132 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1133 return ICE_ERR_RESET_FAILED; 1134 } 1135 1136 return 0; 1137 } 1138 1139 /** 1140 * ice_reset - Perform different types of reset 1141 * @hw: pointer to the hardware structure 1142 * @req: reset request 1143 * 1144 * This function triggers a reset as specified by the req parameter. 1145 * 1146 * Note: 1147 * If anything other than a PF reset is triggered, PXE mode is restored. 1148 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1149 * interface has been restored in the rebuild flow. 1150 */ 1151 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1152 { 1153 u32 val = 0; 1154 1155 switch (req) { 1156 case ICE_RESET_PFR: 1157 return ice_pf_reset(hw); 1158 case ICE_RESET_CORER: 1159 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1160 val = GLGEN_RTRIG_CORER_M; 1161 break; 1162 case ICE_RESET_GLOBR: 1163 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1164 val = GLGEN_RTRIG_GLOBR_M; 1165 break; 1166 default: 1167 return ICE_ERR_PARAM; 1168 } 1169 1170 val |= rd32(hw, GLGEN_RTRIG); 1171 wr32(hw, GLGEN_RTRIG, val); 1172 ice_flush(hw); 1173 1174 /* wait for the FW to be ready */ 1175 return ice_check_reset(hw); 1176 } 1177 1178 /** 1179 * ice_copy_rxq_ctx_to_hw 1180 * @hw: pointer to the hardware structure 1181 * @ice_rxq_ctx: pointer to the rxq context 1182 * @rxq_index: the index of the Rx queue 1183 * 1184 * Copies rxq context from dense structure to HW register space 1185 */ 1186 static enum ice_status 1187 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1188 { 1189 u8 i; 1190 1191 if (!ice_rxq_ctx) 1192 return ICE_ERR_BAD_PTR; 1193 1194 if (rxq_index > QRX_CTRL_MAX_INDEX) 1195 return ICE_ERR_PARAM; 1196 1197 /* Copy each dword separately to HW */ 1198 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1199 wr32(hw, QRX_CONTEXT(i, rxq_index), 1200 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1201 1202 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1203 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1204 } 1205 1206 return 0; 1207 } 1208 1209 /* LAN Rx Queue Context */ 1210 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1211 /* Field Width LSB */ 1212 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1213 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1214 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1215 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1216 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1217 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1218 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1219 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1220 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1221 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1222 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1223 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1224 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1225 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1226 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1227 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1228 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1229 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1230 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1231 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1232 { 0 } 1233 }; 1234 1235 /** 1236 * ice_write_rxq_ctx 1237 * @hw: pointer to the hardware structure 1238 * @rlan_ctx: pointer to the rxq context 1239 * @rxq_index: the index of the Rx queue 1240 * 1241 * Converts rxq context from sparse to dense structure and then writes 1242 * it to HW register space and enables the hardware to prefetch descriptors 1243 * instead of only fetching them on demand 1244 */ 1245 enum ice_status 1246 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1247 u32 rxq_index) 1248 { 1249 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1250 1251 if (!rlan_ctx) 1252 return ICE_ERR_BAD_PTR; 1253 1254 rlan_ctx->prefena = 1; 1255 1256 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1257 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1258 } 1259 1260 /* LAN Tx Queue Context */ 1261 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1262 /* Field Width LSB */ 1263 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1264 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1265 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1266 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1267 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1268 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1269 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1270 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1271 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1272 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1273 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1274 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1275 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1276 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1277 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1278 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1279 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1280 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1281 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1282 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1283 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1284 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1285 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1286 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1287 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1288 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1289 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1290 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1291 { 0 } 1292 }; 1293 1294 /* FW Admin Queue command wrappers */ 1295 1296 /* Software lock/mutex that is meant to be held while the Global Config Lock 1297 * in firmware is acquired by the software to prevent most (but not all) types 1298 * of AQ commands from being sent to FW 1299 */ 1300 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1301 1302 /** 1303 * ice_should_retry_sq_send_cmd 1304 * @opcode: AQ opcode 1305 * 1306 * Decide if we should retry the send command routine for the ATQ, depending 1307 * on the opcode. 1308 */ 1309 static bool ice_should_retry_sq_send_cmd(u16 opcode) 1310 { 1311 switch (opcode) { 1312 case ice_aqc_opc_get_link_topo: 1313 case ice_aqc_opc_lldp_stop: 1314 case ice_aqc_opc_lldp_start: 1315 case ice_aqc_opc_lldp_filter_ctrl: 1316 return true; 1317 } 1318 1319 return false; 1320 } 1321 1322 /** 1323 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1324 * @hw: pointer to the HW struct 1325 * @cq: pointer to the specific Control queue 1326 * @desc: prefilled descriptor describing the command 1327 * @buf: buffer to use for indirect commands (or NULL for direct commands) 1328 * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1329 * @cd: pointer to command details structure 1330 * 1331 * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1332 * Queue if the EBUSY AQ error is returned. 1333 */ 1334 static enum ice_status 1335 ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1336 struct ice_aq_desc *desc, void *buf, u16 buf_size, 1337 struct ice_sq_cd *cd) 1338 { 1339 struct ice_aq_desc desc_cpy; 1340 enum ice_status status; 1341 bool is_cmd_for_retry; 1342 u8 *buf_cpy = NULL; 1343 u8 idx = 0; 1344 u16 opcode; 1345 1346 opcode = le16_to_cpu(desc->opcode); 1347 is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1348 memset(&desc_cpy, 0, sizeof(desc_cpy)); 1349 1350 if (is_cmd_for_retry) { 1351 if (buf) { 1352 buf_cpy = kzalloc(buf_size, GFP_KERNEL); 1353 if (!buf_cpy) 1354 return ICE_ERR_NO_MEMORY; 1355 } 1356 1357 memcpy(&desc_cpy, desc, sizeof(desc_cpy)); 1358 } 1359 1360 do { 1361 status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1362 1363 if (!is_cmd_for_retry || !status || 1364 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1365 break; 1366 1367 if (buf_cpy) 1368 memcpy(buf, buf_cpy, buf_size); 1369 1370 memcpy(desc, &desc_cpy, sizeof(desc_cpy)); 1371 1372 mdelay(ICE_SQ_SEND_DELAY_TIME_MS); 1373 1374 } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1375 1376 kfree(buf_cpy); 1377 1378 return status; 1379 } 1380 1381 /** 1382 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1383 * @hw: pointer to the HW struct 1384 * @desc: descriptor describing the command 1385 * @buf: buffer to use for indirect commands (NULL for direct commands) 1386 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1387 * @cd: pointer to command details structure 1388 * 1389 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1390 */ 1391 enum ice_status 1392 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1393 u16 buf_size, struct ice_sq_cd *cd) 1394 { 1395 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1396 bool lock_acquired = false; 1397 enum ice_status status; 1398 1399 /* When a package download is in process (i.e. when the firmware's 1400 * Global Configuration Lock resource is held), only the Download 1401 * Package, Get Version, Get Package Info List and Release Resource 1402 * (with resource ID set to Global Config Lock) AdminQ commands are 1403 * allowed; all others must block until the package download completes 1404 * and the Global Config Lock is released. See also 1405 * ice_acquire_global_cfg_lock(). 1406 */ 1407 switch (le16_to_cpu(desc->opcode)) { 1408 case ice_aqc_opc_download_pkg: 1409 case ice_aqc_opc_get_pkg_info_list: 1410 case ice_aqc_opc_get_ver: 1411 break; 1412 case ice_aqc_opc_release_res: 1413 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1414 break; 1415 fallthrough; 1416 default: 1417 mutex_lock(&ice_global_cfg_lock_sw); 1418 lock_acquired = true; 1419 break; 1420 } 1421 1422 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 1423 if (lock_acquired) 1424 mutex_unlock(&ice_global_cfg_lock_sw); 1425 1426 return status; 1427 } 1428 1429 /** 1430 * ice_aq_get_fw_ver 1431 * @hw: pointer to the HW struct 1432 * @cd: pointer to command details structure or NULL 1433 * 1434 * Get the firmware version (0x0001) from the admin queue commands 1435 */ 1436 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1437 { 1438 struct ice_aqc_get_ver *resp; 1439 struct ice_aq_desc desc; 1440 enum ice_status status; 1441 1442 resp = &desc.params.get_ver; 1443 1444 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1445 1446 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1447 1448 if (!status) { 1449 hw->fw_branch = resp->fw_branch; 1450 hw->fw_maj_ver = resp->fw_major; 1451 hw->fw_min_ver = resp->fw_minor; 1452 hw->fw_patch = resp->fw_patch; 1453 hw->fw_build = le32_to_cpu(resp->fw_build); 1454 hw->api_branch = resp->api_branch; 1455 hw->api_maj_ver = resp->api_major; 1456 hw->api_min_ver = resp->api_minor; 1457 hw->api_patch = resp->api_patch; 1458 } 1459 1460 return status; 1461 } 1462 1463 /** 1464 * ice_aq_send_driver_ver 1465 * @hw: pointer to the HW struct 1466 * @dv: driver's major, minor version 1467 * @cd: pointer to command details structure or NULL 1468 * 1469 * Send the driver version (0x0002) to the firmware 1470 */ 1471 enum ice_status 1472 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1473 struct ice_sq_cd *cd) 1474 { 1475 struct ice_aqc_driver_ver *cmd; 1476 struct ice_aq_desc desc; 1477 u16 len; 1478 1479 cmd = &desc.params.driver_ver; 1480 1481 if (!dv) 1482 return ICE_ERR_PARAM; 1483 1484 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1485 1486 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1487 cmd->major_ver = dv->major_ver; 1488 cmd->minor_ver = dv->minor_ver; 1489 cmd->build_ver = dv->build_ver; 1490 cmd->subbuild_ver = dv->subbuild_ver; 1491 1492 len = 0; 1493 while (len < sizeof(dv->driver_string) && 1494 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1495 len++; 1496 1497 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1498 } 1499 1500 /** 1501 * ice_aq_q_shutdown 1502 * @hw: pointer to the HW struct 1503 * @unloading: is the driver unloading itself 1504 * 1505 * Tell the Firmware that we're shutting down the AdminQ and whether 1506 * or not the driver is unloading as well (0x0003). 1507 */ 1508 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1509 { 1510 struct ice_aqc_q_shutdown *cmd; 1511 struct ice_aq_desc desc; 1512 1513 cmd = &desc.params.q_shutdown; 1514 1515 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1516 1517 if (unloading) 1518 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1519 1520 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1521 } 1522 1523 /** 1524 * ice_aq_req_res 1525 * @hw: pointer to the HW struct 1526 * @res: resource ID 1527 * @access: access type 1528 * @sdp_number: resource number 1529 * @timeout: the maximum time in ms that the driver may hold the resource 1530 * @cd: pointer to command details structure or NULL 1531 * 1532 * Requests common resource using the admin queue commands (0x0008). 1533 * When attempting to acquire the Global Config Lock, the driver can 1534 * learn of three states: 1535 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1536 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1537 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1538 * successfully downloaded the package; the driver does 1539 * not have to download the package and can continue 1540 * loading 1541 * 1542 * Note that if the caller is in an acquire lock, perform action, release lock 1543 * phase of operation, it is possible that the FW may detect a timeout and issue 1544 * a CORER. In this case, the driver will receive a CORER interrupt and will 1545 * have to determine its cause. The calling thread that is handling this flow 1546 * will likely get an error propagated back to it indicating the Download 1547 * Package, Update Package or the Release Resource AQ commands timed out. 1548 */ 1549 static enum ice_status 1550 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1551 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1552 struct ice_sq_cd *cd) 1553 { 1554 struct ice_aqc_req_res *cmd_resp; 1555 struct ice_aq_desc desc; 1556 enum ice_status status; 1557 1558 cmd_resp = &desc.params.res_owner; 1559 1560 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1561 1562 cmd_resp->res_id = cpu_to_le16(res); 1563 cmd_resp->access_type = cpu_to_le16(access); 1564 cmd_resp->res_number = cpu_to_le32(sdp_number); 1565 cmd_resp->timeout = cpu_to_le32(*timeout); 1566 *timeout = 0; 1567 1568 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1569 1570 /* The completion specifies the maximum time in ms that the driver 1571 * may hold the resource in the Timeout field. 1572 */ 1573 1574 /* Global config lock response utilizes an additional status field. 1575 * 1576 * If the Global config lock resource is held by some other driver, the 1577 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1578 * and the timeout field indicates the maximum time the current owner 1579 * of the resource has to free it. 1580 */ 1581 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1582 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1583 *timeout = le32_to_cpu(cmd_resp->timeout); 1584 return 0; 1585 } else if (le16_to_cpu(cmd_resp->status) == 1586 ICE_AQ_RES_GLBL_IN_PROG) { 1587 *timeout = le32_to_cpu(cmd_resp->timeout); 1588 return ICE_ERR_AQ_ERROR; 1589 } else if (le16_to_cpu(cmd_resp->status) == 1590 ICE_AQ_RES_GLBL_DONE) { 1591 return ICE_ERR_AQ_NO_WORK; 1592 } 1593 1594 /* invalid FW response, force a timeout immediately */ 1595 *timeout = 0; 1596 return ICE_ERR_AQ_ERROR; 1597 } 1598 1599 /* If the resource is held by some other driver, the command completes 1600 * with a busy return value and the timeout field indicates the maximum 1601 * time the current owner of the resource has to free it. 1602 */ 1603 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1604 *timeout = le32_to_cpu(cmd_resp->timeout); 1605 1606 return status; 1607 } 1608 1609 /** 1610 * ice_aq_release_res 1611 * @hw: pointer to the HW struct 1612 * @res: resource ID 1613 * @sdp_number: resource number 1614 * @cd: pointer to command details structure or NULL 1615 * 1616 * release common resource using the admin queue commands (0x0009) 1617 */ 1618 static enum ice_status 1619 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1620 struct ice_sq_cd *cd) 1621 { 1622 struct ice_aqc_req_res *cmd; 1623 struct ice_aq_desc desc; 1624 1625 cmd = &desc.params.res_owner; 1626 1627 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1628 1629 cmd->res_id = cpu_to_le16(res); 1630 cmd->res_number = cpu_to_le32(sdp_number); 1631 1632 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1633 } 1634 1635 /** 1636 * ice_acquire_res 1637 * @hw: pointer to the HW structure 1638 * @res: resource ID 1639 * @access: access type (read or write) 1640 * @timeout: timeout in milliseconds 1641 * 1642 * This function will attempt to acquire the ownership of a resource. 1643 */ 1644 enum ice_status 1645 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1646 enum ice_aq_res_access_type access, u32 timeout) 1647 { 1648 #define ICE_RES_POLLING_DELAY_MS 10 1649 u32 delay = ICE_RES_POLLING_DELAY_MS; 1650 u32 time_left = timeout; 1651 enum ice_status status; 1652 1653 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1654 1655 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1656 * previously acquired the resource and performed any necessary updates; 1657 * in this case the caller does not obtain the resource and has no 1658 * further work to do. 1659 */ 1660 if (status == ICE_ERR_AQ_NO_WORK) 1661 goto ice_acquire_res_exit; 1662 1663 if (status) 1664 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1665 1666 /* If necessary, poll until the current lock owner timeouts */ 1667 timeout = time_left; 1668 while (status && timeout && time_left) { 1669 mdelay(delay); 1670 timeout = (timeout > delay) ? timeout - delay : 0; 1671 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1672 1673 if (status == ICE_ERR_AQ_NO_WORK) 1674 /* lock free, but no work to do */ 1675 break; 1676 1677 if (!status) 1678 /* lock acquired */ 1679 break; 1680 } 1681 if (status && status != ICE_ERR_AQ_NO_WORK) 1682 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1683 1684 ice_acquire_res_exit: 1685 if (status == ICE_ERR_AQ_NO_WORK) { 1686 if (access == ICE_RES_WRITE) 1687 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1688 else 1689 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1690 } 1691 return status; 1692 } 1693 1694 /** 1695 * ice_release_res 1696 * @hw: pointer to the HW structure 1697 * @res: resource ID 1698 * 1699 * This function will release a resource using the proper Admin Command. 1700 */ 1701 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1702 { 1703 enum ice_status status; 1704 u32 total_delay = 0; 1705 1706 status = ice_aq_release_res(hw, res, 0, NULL); 1707 1708 /* there are some rare cases when trying to release the resource 1709 * results in an admin queue timeout, so handle them correctly 1710 */ 1711 while ((status == ICE_ERR_AQ_TIMEOUT) && 1712 (total_delay < hw->adminq.sq_cmd_timeout)) { 1713 mdelay(1); 1714 status = ice_aq_release_res(hw, res, 0, NULL); 1715 total_delay++; 1716 } 1717 } 1718 1719 /** 1720 * ice_aq_alloc_free_res - command to allocate/free resources 1721 * @hw: pointer to the HW struct 1722 * @num_entries: number of resource entries in buffer 1723 * @buf: Indirect buffer to hold data parameters and response 1724 * @buf_size: size of buffer for indirect commands 1725 * @opc: pass in the command opcode 1726 * @cd: pointer to command details structure or NULL 1727 * 1728 * Helper function to allocate/free resources using the admin queue commands 1729 */ 1730 enum ice_status 1731 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1732 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1733 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1734 { 1735 struct ice_aqc_alloc_free_res_cmd *cmd; 1736 struct ice_aq_desc desc; 1737 1738 cmd = &desc.params.sw_res_ctrl; 1739 1740 if (!buf) 1741 return ICE_ERR_PARAM; 1742 1743 if (buf_size < flex_array_size(buf, elem, num_entries)) 1744 return ICE_ERR_PARAM; 1745 1746 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1747 1748 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1749 1750 cmd->num_entries = cpu_to_le16(num_entries); 1751 1752 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1753 } 1754 1755 /** 1756 * ice_alloc_hw_res - allocate resource 1757 * @hw: pointer to the HW struct 1758 * @type: type of resource 1759 * @num: number of resources to allocate 1760 * @btm: allocate from bottom 1761 * @res: pointer to array that will receive the resources 1762 */ 1763 enum ice_status 1764 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1765 { 1766 struct ice_aqc_alloc_free_res_elem *buf; 1767 enum ice_status status; 1768 u16 buf_len; 1769 1770 buf_len = struct_size(buf, elem, num); 1771 buf = kzalloc(buf_len, GFP_KERNEL); 1772 if (!buf) 1773 return ICE_ERR_NO_MEMORY; 1774 1775 /* Prepare buffer to allocate resource. */ 1776 buf->num_elems = cpu_to_le16(num); 1777 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1778 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1779 if (btm) 1780 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1781 1782 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1783 ice_aqc_opc_alloc_res, NULL); 1784 if (status) 1785 goto ice_alloc_res_exit; 1786 1787 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 1788 1789 ice_alloc_res_exit: 1790 kfree(buf); 1791 return status; 1792 } 1793 1794 /** 1795 * ice_free_hw_res - free allocated HW resource 1796 * @hw: pointer to the HW struct 1797 * @type: type of resource to free 1798 * @num: number of resources 1799 * @res: pointer to array that contains the resources to free 1800 */ 1801 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1802 { 1803 struct ice_aqc_alloc_free_res_elem *buf; 1804 enum ice_status status; 1805 u16 buf_len; 1806 1807 buf_len = struct_size(buf, elem, num); 1808 buf = kzalloc(buf_len, GFP_KERNEL); 1809 if (!buf) 1810 return ICE_ERR_NO_MEMORY; 1811 1812 /* Prepare buffer to free resource. */ 1813 buf->num_elems = cpu_to_le16(num); 1814 buf->res_type = cpu_to_le16(type); 1815 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 1816 1817 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1818 ice_aqc_opc_free_res, NULL); 1819 if (status) 1820 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1821 1822 kfree(buf); 1823 return status; 1824 } 1825 1826 /** 1827 * ice_get_num_per_func - determine number of resources per PF 1828 * @hw: pointer to the HW structure 1829 * @max: value to be evenly split between each PF 1830 * 1831 * Determine the number of valid functions by going through the bitmap returned 1832 * from parsing capabilities and use this to calculate the number of resources 1833 * per PF based on the max value passed in. 1834 */ 1835 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1836 { 1837 u8 funcs; 1838 1839 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1840 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 1841 ICE_CAPS_VALID_FUNCS_M); 1842 1843 if (!funcs) 1844 return 0; 1845 1846 return max / funcs; 1847 } 1848 1849 /** 1850 * ice_parse_common_caps - parse common device/function capabilities 1851 * @hw: pointer to the HW struct 1852 * @caps: pointer to common capabilities structure 1853 * @elem: the capability element to parse 1854 * @prefix: message prefix for tracing capabilities 1855 * 1856 * Given a capability element, extract relevant details into the common 1857 * capability structure. 1858 * 1859 * Returns: true if the capability matches one of the common capability ids, 1860 * false otherwise. 1861 */ 1862 static bool 1863 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1864 struct ice_aqc_list_caps_elem *elem, const char *prefix) 1865 { 1866 u32 logical_id = le32_to_cpu(elem->logical_id); 1867 u32 phys_id = le32_to_cpu(elem->phys_id); 1868 u32 number = le32_to_cpu(elem->number); 1869 u16 cap = le16_to_cpu(elem->cap); 1870 bool found = true; 1871 1872 switch (cap) { 1873 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1874 caps->valid_functions = number; 1875 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 1876 caps->valid_functions); 1877 break; 1878 case ICE_AQC_CAPS_SRIOV: 1879 caps->sr_iov_1_1 = (number == 1); 1880 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 1881 caps->sr_iov_1_1); 1882 break; 1883 case ICE_AQC_CAPS_DCB: 1884 caps->dcb = (number == 1); 1885 caps->active_tc_bitmap = logical_id; 1886 caps->maxtc = phys_id; 1887 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 1888 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 1889 caps->active_tc_bitmap); 1890 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 1891 break; 1892 case ICE_AQC_CAPS_RSS: 1893 caps->rss_table_size = number; 1894 caps->rss_table_entry_width = logical_id; 1895 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 1896 caps->rss_table_size); 1897 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 1898 caps->rss_table_entry_width); 1899 break; 1900 case ICE_AQC_CAPS_RXQS: 1901 caps->num_rxq = number; 1902 caps->rxq_first_id = phys_id; 1903 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 1904 caps->num_rxq); 1905 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 1906 caps->rxq_first_id); 1907 break; 1908 case ICE_AQC_CAPS_TXQS: 1909 caps->num_txq = number; 1910 caps->txq_first_id = phys_id; 1911 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 1912 caps->num_txq); 1913 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 1914 caps->txq_first_id); 1915 break; 1916 case ICE_AQC_CAPS_MSIX: 1917 caps->num_msix_vectors = number; 1918 caps->msix_vector_first_id = phys_id; 1919 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 1920 caps->num_msix_vectors); 1921 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 1922 caps->msix_vector_first_id); 1923 break; 1924 case ICE_AQC_CAPS_PENDING_NVM_VER: 1925 caps->nvm_update_pending_nvm = true; 1926 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 1927 break; 1928 case ICE_AQC_CAPS_PENDING_OROM_VER: 1929 caps->nvm_update_pending_orom = true; 1930 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 1931 break; 1932 case ICE_AQC_CAPS_PENDING_NET_VER: 1933 caps->nvm_update_pending_netlist = true; 1934 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 1935 break; 1936 case ICE_AQC_CAPS_NVM_MGMT: 1937 caps->nvm_unified_update = 1938 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 1939 true : false; 1940 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 1941 caps->nvm_unified_update); 1942 break; 1943 case ICE_AQC_CAPS_RDMA: 1944 caps->rdma = (number == 1); 1945 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); 1946 break; 1947 case ICE_AQC_CAPS_MAX_MTU: 1948 caps->max_mtu = number; 1949 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 1950 prefix, caps->max_mtu); 1951 break; 1952 default: 1953 /* Not one of the recognized common capabilities */ 1954 found = false; 1955 } 1956 1957 return found; 1958 } 1959 1960 /** 1961 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 1962 * @hw: pointer to the HW structure 1963 * @caps: pointer to capabilities structure to fix 1964 * 1965 * Re-calculate the capabilities that are dependent on the number of physical 1966 * ports; i.e. some features are not supported or function differently on 1967 * devices with more than 4 ports. 1968 */ 1969 static void 1970 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 1971 { 1972 /* This assumes device capabilities are always scanned before function 1973 * capabilities during the initialization flow. 1974 */ 1975 if (hw->dev_caps.num_funcs > 4) { 1976 /* Max 4 TCs per port */ 1977 caps->maxtc = 4; 1978 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 1979 caps->maxtc); 1980 if (caps->rdma) { 1981 ice_debug(hw, ICE_DBG_INIT, "forcing RDMA off\n"); 1982 caps->rdma = 0; 1983 } 1984 1985 /* print message only when processing device capabilities 1986 * during initialization. 1987 */ 1988 if (caps == &hw->dev_caps.common_cap) 1989 dev_info(ice_hw_to_dev(hw), "RDMA functionality is not available with the current device configuration.\n"); 1990 } 1991 } 1992 1993 /** 1994 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 1995 * @hw: pointer to the HW struct 1996 * @func_p: pointer to function capabilities structure 1997 * @cap: pointer to the capability element to parse 1998 * 1999 * Extract function capabilities for ICE_AQC_CAPS_VF. 2000 */ 2001 static void 2002 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2003 struct ice_aqc_list_caps_elem *cap) 2004 { 2005 u32 logical_id = le32_to_cpu(cap->logical_id); 2006 u32 number = le32_to_cpu(cap->number); 2007 2008 func_p->num_allocd_vfs = number; 2009 func_p->vf_base_id = logical_id; 2010 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 2011 func_p->num_allocd_vfs); 2012 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 2013 func_p->vf_base_id); 2014 } 2015 2016 /** 2017 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 2018 * @hw: pointer to the HW struct 2019 * @func_p: pointer to function capabilities structure 2020 * @cap: pointer to the capability element to parse 2021 * 2022 * Extract function capabilities for ICE_AQC_CAPS_VSI. 2023 */ 2024 static void 2025 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2026 struct ice_aqc_list_caps_elem *cap) 2027 { 2028 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 2029 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 2030 le32_to_cpu(cap->number)); 2031 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 2032 func_p->guar_num_vsi); 2033 } 2034 2035 /** 2036 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 2037 * @hw: pointer to the HW struct 2038 * @func_p: pointer to function capabilities structure 2039 * 2040 * Extract function capabilities for ICE_AQC_CAPS_FD. 2041 */ 2042 static void 2043 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 2044 { 2045 u32 reg_val, val; 2046 2047 reg_val = rd32(hw, GLQF_FD_SIZE); 2048 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 2049 GLQF_FD_SIZE_FD_GSIZE_S; 2050 func_p->fd_fltr_guar = 2051 ice_get_num_per_func(hw, val); 2052 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 2053 GLQF_FD_SIZE_FD_BSIZE_S; 2054 func_p->fd_fltr_best_effort = val; 2055 2056 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 2057 func_p->fd_fltr_guar); 2058 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 2059 func_p->fd_fltr_best_effort); 2060 } 2061 2062 /** 2063 * ice_parse_func_caps - Parse function capabilities 2064 * @hw: pointer to the HW struct 2065 * @func_p: pointer to function capabilities structure 2066 * @buf: buffer containing the function capability records 2067 * @cap_count: the number of capabilities 2068 * 2069 * Helper function to parse function (0x000A) capabilities list. For 2070 * capabilities shared between device and function, this relies on 2071 * ice_parse_common_caps. 2072 * 2073 * Loop through the list of provided capabilities and extract the relevant 2074 * data into the function capabilities structured. 2075 */ 2076 static void 2077 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2078 void *buf, u32 cap_count) 2079 { 2080 struct ice_aqc_list_caps_elem *cap_resp; 2081 u32 i; 2082 2083 cap_resp = buf; 2084 2085 memset(func_p, 0, sizeof(*func_p)); 2086 2087 for (i = 0; i < cap_count; i++) { 2088 u16 cap = le16_to_cpu(cap_resp[i].cap); 2089 bool found; 2090 2091 found = ice_parse_common_caps(hw, &func_p->common_cap, 2092 &cap_resp[i], "func caps"); 2093 2094 switch (cap) { 2095 case ICE_AQC_CAPS_VF: 2096 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2097 break; 2098 case ICE_AQC_CAPS_VSI: 2099 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2100 break; 2101 case ICE_AQC_CAPS_FD: 2102 ice_parse_fdir_func_caps(hw, func_p); 2103 break; 2104 default: 2105 /* Don't list common capabilities as unknown */ 2106 if (!found) 2107 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2108 i, cap); 2109 break; 2110 } 2111 } 2112 2113 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2114 } 2115 2116 /** 2117 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2118 * @hw: pointer to the HW struct 2119 * @dev_p: pointer to device capabilities structure 2120 * @cap: capability element to parse 2121 * 2122 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2123 */ 2124 static void 2125 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2126 struct ice_aqc_list_caps_elem *cap) 2127 { 2128 u32 number = le32_to_cpu(cap->number); 2129 2130 dev_p->num_funcs = hweight32(number); 2131 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2132 dev_p->num_funcs); 2133 } 2134 2135 /** 2136 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2137 * @hw: pointer to the HW struct 2138 * @dev_p: pointer to device capabilities structure 2139 * @cap: capability element to parse 2140 * 2141 * Parse ICE_AQC_CAPS_VF for device capabilities. 2142 */ 2143 static void 2144 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2145 struct ice_aqc_list_caps_elem *cap) 2146 { 2147 u32 number = le32_to_cpu(cap->number); 2148 2149 dev_p->num_vfs_exposed = number; 2150 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2151 dev_p->num_vfs_exposed); 2152 } 2153 2154 /** 2155 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2156 * @hw: pointer to the HW struct 2157 * @dev_p: pointer to device capabilities structure 2158 * @cap: capability element to parse 2159 * 2160 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2161 */ 2162 static void 2163 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2164 struct ice_aqc_list_caps_elem *cap) 2165 { 2166 u32 number = le32_to_cpu(cap->number); 2167 2168 dev_p->num_vsi_allocd_to_host = number; 2169 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2170 dev_p->num_vsi_allocd_to_host); 2171 } 2172 2173 /** 2174 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2175 * @hw: pointer to the HW struct 2176 * @dev_p: pointer to device capabilities structure 2177 * @cap: capability element to parse 2178 * 2179 * Parse ICE_AQC_CAPS_FD for device capabilities. 2180 */ 2181 static void 2182 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2183 struct ice_aqc_list_caps_elem *cap) 2184 { 2185 u32 number = le32_to_cpu(cap->number); 2186 2187 dev_p->num_flow_director_fltr = number; 2188 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2189 dev_p->num_flow_director_fltr); 2190 } 2191 2192 /** 2193 * ice_parse_dev_caps - Parse device capabilities 2194 * @hw: pointer to the HW struct 2195 * @dev_p: pointer to device capabilities structure 2196 * @buf: buffer containing the device capability records 2197 * @cap_count: the number of capabilities 2198 * 2199 * Helper device to parse device (0x000B) capabilities list. For 2200 * capabilities shared between device and function, this relies on 2201 * ice_parse_common_caps. 2202 * 2203 * Loop through the list of provided capabilities and extract the relevant 2204 * data into the device capabilities structured. 2205 */ 2206 static void 2207 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2208 void *buf, u32 cap_count) 2209 { 2210 struct ice_aqc_list_caps_elem *cap_resp; 2211 u32 i; 2212 2213 cap_resp = buf; 2214 2215 memset(dev_p, 0, sizeof(*dev_p)); 2216 2217 for (i = 0; i < cap_count; i++) { 2218 u16 cap = le16_to_cpu(cap_resp[i].cap); 2219 bool found; 2220 2221 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2222 &cap_resp[i], "dev caps"); 2223 2224 switch (cap) { 2225 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2226 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2227 break; 2228 case ICE_AQC_CAPS_VF: 2229 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2230 break; 2231 case ICE_AQC_CAPS_VSI: 2232 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2233 break; 2234 case ICE_AQC_CAPS_FD: 2235 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2236 break; 2237 default: 2238 /* Don't list common capabilities as unknown */ 2239 if (!found) 2240 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2241 i, cap); 2242 break; 2243 } 2244 } 2245 2246 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2247 } 2248 2249 /** 2250 * ice_aq_list_caps - query function/device capabilities 2251 * @hw: pointer to the HW struct 2252 * @buf: a buffer to hold the capabilities 2253 * @buf_size: size of the buffer 2254 * @cap_count: if not NULL, set to the number of capabilities reported 2255 * @opc: capabilities type to discover, device or function 2256 * @cd: pointer to command details structure or NULL 2257 * 2258 * Get the function (0x000A) or device (0x000B) capabilities description from 2259 * firmware and store it in the buffer. 2260 * 2261 * If the cap_count pointer is not NULL, then it is set to the number of 2262 * capabilities firmware will report. Note that if the buffer size is too 2263 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2264 * cap_count will still be updated in this case. It is recommended that the 2265 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2266 * firmware could return) to avoid this. 2267 */ 2268 enum ice_status 2269 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2270 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2271 { 2272 struct ice_aqc_list_caps *cmd; 2273 struct ice_aq_desc desc; 2274 enum ice_status status; 2275 2276 cmd = &desc.params.get_cap; 2277 2278 if (opc != ice_aqc_opc_list_func_caps && 2279 opc != ice_aqc_opc_list_dev_caps) 2280 return ICE_ERR_PARAM; 2281 2282 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2283 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2284 2285 if (cap_count) 2286 *cap_count = le32_to_cpu(cmd->count); 2287 2288 return status; 2289 } 2290 2291 /** 2292 * ice_discover_dev_caps - Read and extract device capabilities 2293 * @hw: pointer to the hardware structure 2294 * @dev_caps: pointer to device capabilities structure 2295 * 2296 * Read the device capabilities and extract them into the dev_caps structure 2297 * for later use. 2298 */ 2299 enum ice_status 2300 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2301 { 2302 enum ice_status status; 2303 u32 cap_count = 0; 2304 void *cbuf; 2305 2306 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2307 if (!cbuf) 2308 return ICE_ERR_NO_MEMORY; 2309 2310 /* Although the driver doesn't know the number of capabilities the 2311 * device will return, we can simply send a 4KB buffer, the maximum 2312 * possible size that firmware can return. 2313 */ 2314 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2315 2316 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2317 ice_aqc_opc_list_dev_caps, NULL); 2318 if (!status) 2319 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2320 kfree(cbuf); 2321 2322 return status; 2323 } 2324 2325 /** 2326 * ice_discover_func_caps - Read and extract function capabilities 2327 * @hw: pointer to the hardware structure 2328 * @func_caps: pointer to function capabilities structure 2329 * 2330 * Read the function capabilities and extract them into the func_caps structure 2331 * for later use. 2332 */ 2333 static enum ice_status 2334 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2335 { 2336 enum ice_status status; 2337 u32 cap_count = 0; 2338 void *cbuf; 2339 2340 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2341 if (!cbuf) 2342 return ICE_ERR_NO_MEMORY; 2343 2344 /* Although the driver doesn't know the number of capabilities the 2345 * device will return, we can simply send a 4KB buffer, the maximum 2346 * possible size that firmware can return. 2347 */ 2348 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2349 2350 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2351 ice_aqc_opc_list_func_caps, NULL); 2352 if (!status) 2353 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2354 kfree(cbuf); 2355 2356 return status; 2357 } 2358 2359 /** 2360 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2361 * @hw: pointer to the hardware structure 2362 */ 2363 void ice_set_safe_mode_caps(struct ice_hw *hw) 2364 { 2365 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2366 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2367 struct ice_hw_common_caps cached_caps; 2368 u32 num_funcs; 2369 2370 /* cache some func_caps values that should be restored after memset */ 2371 cached_caps = func_caps->common_cap; 2372 2373 /* unset func capabilities */ 2374 memset(func_caps, 0, sizeof(*func_caps)); 2375 2376 #define ICE_RESTORE_FUNC_CAP(name) \ 2377 func_caps->common_cap.name = cached_caps.name 2378 2379 /* restore cached values */ 2380 ICE_RESTORE_FUNC_CAP(valid_functions); 2381 ICE_RESTORE_FUNC_CAP(txq_first_id); 2382 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2383 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2384 ICE_RESTORE_FUNC_CAP(max_mtu); 2385 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2386 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2387 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2388 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2389 2390 /* one Tx and one Rx queue in safe mode */ 2391 func_caps->common_cap.num_rxq = 1; 2392 func_caps->common_cap.num_txq = 1; 2393 2394 /* two MSIX vectors, one for traffic and one for misc causes */ 2395 func_caps->common_cap.num_msix_vectors = 2; 2396 func_caps->guar_num_vsi = 1; 2397 2398 /* cache some dev_caps values that should be restored after memset */ 2399 cached_caps = dev_caps->common_cap; 2400 num_funcs = dev_caps->num_funcs; 2401 2402 /* unset dev capabilities */ 2403 memset(dev_caps, 0, sizeof(*dev_caps)); 2404 2405 #define ICE_RESTORE_DEV_CAP(name) \ 2406 dev_caps->common_cap.name = cached_caps.name 2407 2408 /* restore cached values */ 2409 ICE_RESTORE_DEV_CAP(valid_functions); 2410 ICE_RESTORE_DEV_CAP(txq_first_id); 2411 ICE_RESTORE_DEV_CAP(rxq_first_id); 2412 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2413 ICE_RESTORE_DEV_CAP(max_mtu); 2414 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2415 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 2416 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 2417 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 2418 dev_caps->num_funcs = num_funcs; 2419 2420 /* one Tx and one Rx queue per function in safe mode */ 2421 dev_caps->common_cap.num_rxq = num_funcs; 2422 dev_caps->common_cap.num_txq = num_funcs; 2423 2424 /* two MSIX vectors per function */ 2425 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2426 } 2427 2428 /** 2429 * ice_get_caps - get info about the HW 2430 * @hw: pointer to the hardware structure 2431 */ 2432 enum ice_status ice_get_caps(struct ice_hw *hw) 2433 { 2434 enum ice_status status; 2435 2436 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2437 if (status) 2438 return status; 2439 2440 return ice_discover_func_caps(hw, &hw->func_caps); 2441 } 2442 2443 /** 2444 * ice_aq_manage_mac_write - manage MAC address write command 2445 * @hw: pointer to the HW struct 2446 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2447 * @flags: flags to control write behavior 2448 * @cd: pointer to command details structure or NULL 2449 * 2450 * This function is used to write MAC address to the NVM (0x0108). 2451 */ 2452 enum ice_status 2453 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2454 struct ice_sq_cd *cd) 2455 { 2456 struct ice_aqc_manage_mac_write *cmd; 2457 struct ice_aq_desc desc; 2458 2459 cmd = &desc.params.mac_write; 2460 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2461 2462 cmd->flags = flags; 2463 ether_addr_copy(cmd->mac_addr, mac_addr); 2464 2465 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2466 } 2467 2468 /** 2469 * ice_aq_clear_pxe_mode 2470 * @hw: pointer to the HW struct 2471 * 2472 * Tell the firmware that the driver is taking over from PXE (0x0110). 2473 */ 2474 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2475 { 2476 struct ice_aq_desc desc; 2477 2478 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2479 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2480 2481 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2482 } 2483 2484 /** 2485 * ice_clear_pxe_mode - clear pxe operations mode 2486 * @hw: pointer to the HW struct 2487 * 2488 * Make sure all PXE mode settings are cleared, including things 2489 * like descriptor fetch/write-back mode. 2490 */ 2491 void ice_clear_pxe_mode(struct ice_hw *hw) 2492 { 2493 if (ice_check_sq_alive(hw, &hw->adminq)) 2494 ice_aq_clear_pxe_mode(hw); 2495 } 2496 2497 /** 2498 * ice_get_link_speed_based_on_phy_type - returns link speed 2499 * @phy_type_low: lower part of phy_type 2500 * @phy_type_high: higher part of phy_type 2501 * 2502 * This helper function will convert an entry in PHY type structure 2503 * [phy_type_low, phy_type_high] to its corresponding link speed. 2504 * Note: In the structure of [phy_type_low, phy_type_high], there should 2505 * be one bit set, as this function will convert one PHY type to its 2506 * speed. 2507 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2508 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2509 */ 2510 static u16 2511 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2512 { 2513 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2514 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2515 2516 switch (phy_type_low) { 2517 case ICE_PHY_TYPE_LOW_100BASE_TX: 2518 case ICE_PHY_TYPE_LOW_100M_SGMII: 2519 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2520 break; 2521 case ICE_PHY_TYPE_LOW_1000BASE_T: 2522 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2523 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2524 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2525 case ICE_PHY_TYPE_LOW_1G_SGMII: 2526 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2527 break; 2528 case ICE_PHY_TYPE_LOW_2500BASE_T: 2529 case ICE_PHY_TYPE_LOW_2500BASE_X: 2530 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2531 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2532 break; 2533 case ICE_PHY_TYPE_LOW_5GBASE_T: 2534 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2535 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2536 break; 2537 case ICE_PHY_TYPE_LOW_10GBASE_T: 2538 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2539 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2540 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2541 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2542 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2543 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2544 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2545 break; 2546 case ICE_PHY_TYPE_LOW_25GBASE_T: 2547 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2548 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2549 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2550 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2551 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2552 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2553 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2554 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2555 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2556 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2557 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2558 break; 2559 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2560 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2561 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2562 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2563 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2564 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2565 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2566 break; 2567 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2568 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2569 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2570 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2571 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2572 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2573 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2574 case ICE_PHY_TYPE_LOW_50G_AUI2: 2575 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2576 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2577 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2578 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2579 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2580 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2581 case ICE_PHY_TYPE_LOW_50G_AUI1: 2582 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2583 break; 2584 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2585 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2586 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2587 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2588 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2589 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2590 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2591 case ICE_PHY_TYPE_LOW_100G_AUI4: 2592 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2593 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2594 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2595 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2596 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2597 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2598 break; 2599 default: 2600 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2601 break; 2602 } 2603 2604 switch (phy_type_high) { 2605 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2606 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2607 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2608 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2609 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2610 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2611 break; 2612 default: 2613 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2614 break; 2615 } 2616 2617 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2618 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2619 return ICE_AQ_LINK_SPEED_UNKNOWN; 2620 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2621 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2622 return ICE_AQ_LINK_SPEED_UNKNOWN; 2623 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2624 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2625 return speed_phy_type_low; 2626 else 2627 return speed_phy_type_high; 2628 } 2629 2630 /** 2631 * ice_update_phy_type 2632 * @phy_type_low: pointer to the lower part of phy_type 2633 * @phy_type_high: pointer to the higher part of phy_type 2634 * @link_speeds_bitmap: targeted link speeds bitmap 2635 * 2636 * Note: For the link_speeds_bitmap structure, you can check it at 2637 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2638 * link_speeds_bitmap include multiple speeds. 2639 * 2640 * Each entry in this [phy_type_low, phy_type_high] structure will 2641 * present a certain link speed. This helper function will turn on bits 2642 * in [phy_type_low, phy_type_high] structure based on the value of 2643 * link_speeds_bitmap input parameter. 2644 */ 2645 void 2646 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2647 u16 link_speeds_bitmap) 2648 { 2649 u64 pt_high; 2650 u64 pt_low; 2651 int index; 2652 u16 speed; 2653 2654 /* We first check with low part of phy_type */ 2655 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2656 pt_low = BIT_ULL(index); 2657 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2658 2659 if (link_speeds_bitmap & speed) 2660 *phy_type_low |= BIT_ULL(index); 2661 } 2662 2663 /* We then check with high part of phy_type */ 2664 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2665 pt_high = BIT_ULL(index); 2666 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2667 2668 if (link_speeds_bitmap & speed) 2669 *phy_type_high |= BIT_ULL(index); 2670 } 2671 } 2672 2673 /** 2674 * ice_aq_set_phy_cfg 2675 * @hw: pointer to the HW struct 2676 * @pi: port info structure of the interested logical port 2677 * @cfg: structure with PHY configuration data to be set 2678 * @cd: pointer to command details structure or NULL 2679 * 2680 * Set the various PHY configuration parameters supported on the Port. 2681 * One or more of the Set PHY config parameters may be ignored in an MFP 2682 * mode as the PF may not have the privilege to set some of the PHY Config 2683 * parameters. This status will be indicated by the command response (0x0601). 2684 */ 2685 enum ice_status 2686 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2687 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2688 { 2689 struct ice_aq_desc desc; 2690 enum ice_status status; 2691 2692 if (!cfg) 2693 return ICE_ERR_PARAM; 2694 2695 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2696 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2697 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2698 cfg->caps); 2699 2700 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2701 } 2702 2703 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2704 desc.params.set_phy.lport_num = pi->lport; 2705 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2706 2707 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 2708 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 2709 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 2710 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 2711 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 2712 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 2713 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 2714 cfg->low_power_ctrl_an); 2715 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 2716 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 2717 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 2718 cfg->link_fec_opt); 2719 2720 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2721 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 2722 status = 0; 2723 2724 if (!status) 2725 pi->phy.curr_user_phy_cfg = *cfg; 2726 2727 return status; 2728 } 2729 2730 /** 2731 * ice_update_link_info - update status of the HW network link 2732 * @pi: port info structure of the interested logical port 2733 */ 2734 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2735 { 2736 struct ice_link_status *li; 2737 enum ice_status status; 2738 2739 if (!pi) 2740 return ICE_ERR_PARAM; 2741 2742 li = &pi->phy.link_info; 2743 2744 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2745 if (status) 2746 return status; 2747 2748 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2749 struct ice_aqc_get_phy_caps_data *pcaps; 2750 struct ice_hw *hw; 2751 2752 hw = pi->hw; 2753 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 2754 GFP_KERNEL); 2755 if (!pcaps) 2756 return ICE_ERR_NO_MEMORY; 2757 2758 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 2759 pcaps, NULL); 2760 2761 devm_kfree(ice_hw_to_dev(hw), pcaps); 2762 } 2763 2764 return status; 2765 } 2766 2767 /** 2768 * ice_cache_phy_user_req 2769 * @pi: port information structure 2770 * @cache_data: PHY logging data 2771 * @cache_mode: PHY logging mode 2772 * 2773 * Log the user request on (FC, FEC, SPEED) for later use. 2774 */ 2775 static void 2776 ice_cache_phy_user_req(struct ice_port_info *pi, 2777 struct ice_phy_cache_mode_data cache_data, 2778 enum ice_phy_cache_mode cache_mode) 2779 { 2780 if (!pi) 2781 return; 2782 2783 switch (cache_mode) { 2784 case ICE_FC_MODE: 2785 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 2786 break; 2787 case ICE_SPEED_MODE: 2788 pi->phy.curr_user_speed_req = 2789 cache_data.data.curr_user_speed_req; 2790 break; 2791 case ICE_FEC_MODE: 2792 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 2793 break; 2794 default: 2795 break; 2796 } 2797 } 2798 2799 /** 2800 * ice_caps_to_fc_mode 2801 * @caps: PHY capabilities 2802 * 2803 * Convert PHY FC capabilities to ice FC mode 2804 */ 2805 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 2806 { 2807 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 2808 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2809 return ICE_FC_FULL; 2810 2811 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 2812 return ICE_FC_TX_PAUSE; 2813 2814 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2815 return ICE_FC_RX_PAUSE; 2816 2817 return ICE_FC_NONE; 2818 } 2819 2820 /** 2821 * ice_caps_to_fec_mode 2822 * @caps: PHY capabilities 2823 * @fec_options: Link FEC options 2824 * 2825 * Convert PHY FEC capabilities to ice FEC mode 2826 */ 2827 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 2828 { 2829 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 2830 return ICE_FEC_AUTO; 2831 2832 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2833 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2834 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 2835 ICE_AQC_PHY_FEC_25G_KR_REQ)) 2836 return ICE_FEC_BASER; 2837 2838 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2839 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 2840 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 2841 return ICE_FEC_RS; 2842 2843 return ICE_FEC_NONE; 2844 } 2845 2846 /** 2847 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 2848 * @pi: port information structure 2849 * @cfg: PHY configuration data to set FC mode 2850 * @req_mode: FC mode to configure 2851 */ 2852 enum ice_status 2853 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 2854 enum ice_fc_mode req_mode) 2855 { 2856 struct ice_phy_cache_mode_data cache_data; 2857 u8 pause_mask = 0x0; 2858 2859 if (!pi || !cfg) 2860 return ICE_ERR_BAD_PTR; 2861 2862 switch (req_mode) { 2863 case ICE_FC_FULL: 2864 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2865 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2866 break; 2867 case ICE_FC_RX_PAUSE: 2868 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2869 break; 2870 case ICE_FC_TX_PAUSE: 2871 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2872 break; 2873 default: 2874 break; 2875 } 2876 2877 /* clear the old pause settings */ 2878 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2879 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2880 2881 /* set the new capabilities */ 2882 cfg->caps |= pause_mask; 2883 2884 /* Cache user FC request */ 2885 cache_data.data.curr_user_fc_req = req_mode; 2886 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 2887 2888 return 0; 2889 } 2890 2891 /** 2892 * ice_set_fc 2893 * @pi: port information structure 2894 * @aq_failures: pointer to status code, specific to ice_set_fc routine 2895 * @ena_auto_link_update: enable automatic link update 2896 * 2897 * Set the requested flow control mode. 2898 */ 2899 enum ice_status 2900 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2901 { 2902 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2903 struct ice_aqc_get_phy_caps_data *pcaps; 2904 enum ice_status status; 2905 struct ice_hw *hw; 2906 2907 if (!pi || !aq_failures) 2908 return ICE_ERR_BAD_PTR; 2909 2910 *aq_failures = 0; 2911 hw = pi->hw; 2912 2913 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 2914 if (!pcaps) 2915 return ICE_ERR_NO_MEMORY; 2916 2917 /* Get the current PHY config */ 2918 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 2919 pcaps, NULL); 2920 if (status) { 2921 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2922 goto out; 2923 } 2924 2925 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 2926 2927 /* Configure the set PHY data */ 2928 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 2929 if (status) 2930 goto out; 2931 2932 /* If the capabilities have changed, then set the new config */ 2933 if (cfg.caps != pcaps->caps) { 2934 int retry_count, retry_max = 10; 2935 2936 /* Auto restart link so settings take effect */ 2937 if (ena_auto_link_update) 2938 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2939 2940 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 2941 if (status) { 2942 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 2943 goto out; 2944 } 2945 2946 /* Update the link info 2947 * It sometimes takes a really long time for link to 2948 * come back from the atomic reset. Thus, we wait a 2949 * little bit. 2950 */ 2951 for (retry_count = 0; retry_count < retry_max; retry_count++) { 2952 status = ice_update_link_info(pi); 2953 2954 if (!status) 2955 break; 2956 2957 mdelay(100); 2958 } 2959 2960 if (status) 2961 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 2962 } 2963 2964 out: 2965 devm_kfree(ice_hw_to_dev(hw), pcaps); 2966 return status; 2967 } 2968 2969 /** 2970 * ice_phy_caps_equals_cfg 2971 * @phy_caps: PHY capabilities 2972 * @phy_cfg: PHY configuration 2973 * 2974 * Helper function to determine if PHY capabilities matches PHY 2975 * configuration 2976 */ 2977 bool 2978 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 2979 struct ice_aqc_set_phy_cfg_data *phy_cfg) 2980 { 2981 u8 caps_mask, cfg_mask; 2982 2983 if (!phy_caps || !phy_cfg) 2984 return false; 2985 2986 /* These bits are not common between capabilities and configuration. 2987 * Do not use them to determine equality. 2988 */ 2989 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 2990 ICE_AQC_GET_PHY_EN_MOD_QUAL); 2991 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2992 2993 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 2994 phy_caps->phy_type_high != phy_cfg->phy_type_high || 2995 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 2996 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 2997 phy_caps->eee_cap != phy_cfg->eee_cap || 2998 phy_caps->eeer_value != phy_cfg->eeer_value || 2999 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 3000 return false; 3001 3002 return true; 3003 } 3004 3005 /** 3006 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 3007 * @pi: port information structure 3008 * @caps: PHY ability structure to copy date from 3009 * @cfg: PHY configuration structure to copy data to 3010 * 3011 * Helper function to copy AQC PHY get ability data to PHY set configuration 3012 * data structure 3013 */ 3014 void 3015 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 3016 struct ice_aqc_get_phy_caps_data *caps, 3017 struct ice_aqc_set_phy_cfg_data *cfg) 3018 { 3019 if (!pi || !caps || !cfg) 3020 return; 3021 3022 memset(cfg, 0, sizeof(*cfg)); 3023 cfg->phy_type_low = caps->phy_type_low; 3024 cfg->phy_type_high = caps->phy_type_high; 3025 cfg->caps = caps->caps; 3026 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 3027 cfg->eee_cap = caps->eee_cap; 3028 cfg->eeer_value = caps->eeer_value; 3029 cfg->link_fec_opt = caps->link_fec_options; 3030 cfg->module_compliance_enforcement = 3031 caps->module_compliance_enforcement; 3032 } 3033 3034 /** 3035 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 3036 * @pi: port information structure 3037 * @cfg: PHY configuration data to set FEC mode 3038 * @fec: FEC mode to configure 3039 */ 3040 enum ice_status 3041 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 3042 enum ice_fec_mode fec) 3043 { 3044 struct ice_aqc_get_phy_caps_data *pcaps; 3045 enum ice_status status; 3046 struct ice_hw *hw; 3047 3048 if (!pi || !cfg) 3049 return ICE_ERR_BAD_PTR; 3050 3051 hw = pi->hw; 3052 3053 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 3054 if (!pcaps) 3055 return ICE_ERR_NO_MEMORY; 3056 3057 status = ice_aq_get_phy_caps(pi, false, 3058 (ice_fw_supports_report_dflt_cfg(hw) ? 3059 ICE_AQC_REPORT_DFLT_CFG : 3060 ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3061 if (status) 3062 goto out; 3063 3064 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 3065 cfg->link_fec_opt = pcaps->link_fec_options; 3066 3067 switch (fec) { 3068 case ICE_FEC_BASER: 3069 /* Clear RS bits, and AND BASE-R ability 3070 * bits and OR request bits. 3071 */ 3072 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 3073 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3074 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3075 ICE_AQC_PHY_FEC_25G_KR_REQ; 3076 break; 3077 case ICE_FEC_RS: 3078 /* Clear BASE-R bits, and AND RS ability 3079 * bits and OR request bits. 3080 */ 3081 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3082 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3083 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3084 break; 3085 case ICE_FEC_NONE: 3086 /* Clear all FEC option bits. */ 3087 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3088 break; 3089 case ICE_FEC_AUTO: 3090 /* AND auto FEC bit, and all caps bits. */ 3091 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3092 cfg->link_fec_opt |= pcaps->link_fec_options; 3093 break; 3094 default: 3095 status = ICE_ERR_PARAM; 3096 break; 3097 } 3098 3099 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(hw) && 3100 !ice_fw_supports_report_dflt_cfg(hw)) { 3101 struct ice_link_default_override_tlv tlv; 3102 3103 if (ice_get_link_default_override(&tlv, pi)) 3104 goto out; 3105 3106 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3107 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3108 cfg->link_fec_opt = tlv.fec_options; 3109 } 3110 3111 out: 3112 kfree(pcaps); 3113 3114 return status; 3115 } 3116 3117 /** 3118 * ice_get_link_status - get status of the HW network link 3119 * @pi: port information structure 3120 * @link_up: pointer to bool (true/false = linkup/linkdown) 3121 * 3122 * Variable link_up is true if link is up, false if link is down. 3123 * The variable link_up is invalid if status is non zero. As a 3124 * result of this call, link status reporting becomes enabled 3125 */ 3126 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3127 { 3128 struct ice_phy_info *phy_info; 3129 enum ice_status status = 0; 3130 3131 if (!pi || !link_up) 3132 return ICE_ERR_PARAM; 3133 3134 phy_info = &pi->phy; 3135 3136 if (phy_info->get_link_info) { 3137 status = ice_update_link_info(pi); 3138 3139 if (status) 3140 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3141 status); 3142 } 3143 3144 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3145 3146 return status; 3147 } 3148 3149 /** 3150 * ice_aq_set_link_restart_an 3151 * @pi: pointer to the port information structure 3152 * @ena_link: if true: enable link, if false: disable link 3153 * @cd: pointer to command details structure or NULL 3154 * 3155 * Sets up the link and restarts the Auto-Negotiation over the link. 3156 */ 3157 enum ice_status 3158 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3159 struct ice_sq_cd *cd) 3160 { 3161 struct ice_aqc_restart_an *cmd; 3162 struct ice_aq_desc desc; 3163 3164 cmd = &desc.params.restart_an; 3165 3166 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3167 3168 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3169 cmd->lport_num = pi->lport; 3170 if (ena_link) 3171 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3172 else 3173 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3174 3175 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3176 } 3177 3178 /** 3179 * ice_aq_set_event_mask 3180 * @hw: pointer to the HW struct 3181 * @port_num: port number of the physical function 3182 * @mask: event mask to be set 3183 * @cd: pointer to command details structure or NULL 3184 * 3185 * Set event mask (0x0613) 3186 */ 3187 enum ice_status 3188 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3189 struct ice_sq_cd *cd) 3190 { 3191 struct ice_aqc_set_event_mask *cmd; 3192 struct ice_aq_desc desc; 3193 3194 cmd = &desc.params.set_event_mask; 3195 3196 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3197 3198 cmd->lport_num = port_num; 3199 3200 cmd->event_mask = cpu_to_le16(mask); 3201 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3202 } 3203 3204 /** 3205 * ice_aq_set_mac_loopback 3206 * @hw: pointer to the HW struct 3207 * @ena_lpbk: Enable or Disable loopback 3208 * @cd: pointer to command details structure or NULL 3209 * 3210 * Enable/disable loopback on a given port 3211 */ 3212 enum ice_status 3213 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3214 { 3215 struct ice_aqc_set_mac_lb *cmd; 3216 struct ice_aq_desc desc; 3217 3218 cmd = &desc.params.set_mac_lb; 3219 3220 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3221 if (ena_lpbk) 3222 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3223 3224 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3225 } 3226 3227 /** 3228 * ice_aq_set_port_id_led 3229 * @pi: pointer to the port information 3230 * @is_orig_mode: is this LED set to original mode (by the net-list) 3231 * @cd: pointer to command details structure or NULL 3232 * 3233 * Set LED value for the given port (0x06e9) 3234 */ 3235 enum ice_status 3236 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3237 struct ice_sq_cd *cd) 3238 { 3239 struct ice_aqc_set_port_id_led *cmd; 3240 struct ice_hw *hw = pi->hw; 3241 struct ice_aq_desc desc; 3242 3243 cmd = &desc.params.set_port_id_led; 3244 3245 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3246 3247 if (is_orig_mode) 3248 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3249 else 3250 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3251 3252 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3253 } 3254 3255 /** 3256 * ice_aq_sff_eeprom 3257 * @hw: pointer to the HW struct 3258 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3259 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3260 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3261 * @page: QSFP page 3262 * @set_page: set or ignore the page 3263 * @data: pointer to data buffer to be read/written to the I2C device. 3264 * @length: 1-16 for read, 1 for write. 3265 * @write: 0 read, 1 for write. 3266 * @cd: pointer to command details structure or NULL 3267 * 3268 * Read/Write SFF EEPROM (0x06EE) 3269 */ 3270 enum ice_status 3271 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3272 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3273 bool write, struct ice_sq_cd *cd) 3274 { 3275 struct ice_aqc_sff_eeprom *cmd; 3276 struct ice_aq_desc desc; 3277 enum ice_status status; 3278 3279 if (!data || (mem_addr & 0xff00)) 3280 return ICE_ERR_PARAM; 3281 3282 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3283 cmd = &desc.params.read_write_sff_param; 3284 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD); 3285 cmd->lport_num = (u8)(lport & 0xff); 3286 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3287 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 3288 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3289 ((set_page << 3290 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3291 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3292 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3293 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3294 if (write) 3295 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 3296 3297 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3298 return status; 3299 } 3300 3301 /** 3302 * __ice_aq_get_set_rss_lut 3303 * @hw: pointer to the hardware structure 3304 * @params: RSS LUT parameters 3305 * @set: set true to set the table, false to get the table 3306 * 3307 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3308 */ 3309 static enum ice_status 3310 __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 3311 { 3312 u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 3313 struct ice_aqc_get_set_rss_lut *cmd_resp; 3314 struct ice_aq_desc desc; 3315 enum ice_status status; 3316 u8 *lut; 3317 3318 if (!params) 3319 return ICE_ERR_PARAM; 3320 3321 vsi_handle = params->vsi_handle; 3322 lut = params->lut; 3323 3324 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3325 return ICE_ERR_PARAM; 3326 3327 lut_size = params->lut_size; 3328 lut_type = params->lut_type; 3329 glob_lut_idx = params->global_lut_id; 3330 vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 3331 3332 cmd_resp = &desc.params.get_set_rss_lut; 3333 3334 if (set) { 3335 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3336 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3337 } else { 3338 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3339 } 3340 3341 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3342 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3343 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3344 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3345 3346 switch (lut_type) { 3347 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3348 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3349 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3350 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3351 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3352 break; 3353 default: 3354 status = ICE_ERR_PARAM; 3355 goto ice_aq_get_set_rss_lut_exit; 3356 } 3357 3358 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3359 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3360 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3361 3362 if (!set) 3363 goto ice_aq_get_set_rss_lut_send; 3364 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3365 if (!set) 3366 goto ice_aq_get_set_rss_lut_send; 3367 } else { 3368 goto ice_aq_get_set_rss_lut_send; 3369 } 3370 3371 /* LUT size is only valid for Global and PF table types */ 3372 switch (lut_size) { 3373 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3374 break; 3375 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3376 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3377 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3378 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3379 break; 3380 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3381 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3382 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3383 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3384 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3385 break; 3386 } 3387 fallthrough; 3388 default: 3389 status = ICE_ERR_PARAM; 3390 goto ice_aq_get_set_rss_lut_exit; 3391 } 3392 3393 ice_aq_get_set_rss_lut_send: 3394 cmd_resp->flags = cpu_to_le16(flags); 3395 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3396 3397 ice_aq_get_set_rss_lut_exit: 3398 return status; 3399 } 3400 3401 /** 3402 * ice_aq_get_rss_lut 3403 * @hw: pointer to the hardware structure 3404 * @get_params: RSS LUT parameters used to specify which RSS LUT to get 3405 * 3406 * get the RSS lookup table, PF or VSI type 3407 */ 3408 enum ice_status 3409 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 3410 { 3411 return __ice_aq_get_set_rss_lut(hw, get_params, false); 3412 } 3413 3414 /** 3415 * ice_aq_set_rss_lut 3416 * @hw: pointer to the hardware structure 3417 * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 3418 * 3419 * set the RSS lookup table, PF or VSI type 3420 */ 3421 enum ice_status 3422 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 3423 { 3424 return __ice_aq_get_set_rss_lut(hw, set_params, true); 3425 } 3426 3427 /** 3428 * __ice_aq_get_set_rss_key 3429 * @hw: pointer to the HW struct 3430 * @vsi_id: VSI FW index 3431 * @key: pointer to key info struct 3432 * @set: set true to set the key, false to get the key 3433 * 3434 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3435 */ 3436 static enum 3437 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3438 struct ice_aqc_get_set_rss_keys *key, 3439 bool set) 3440 { 3441 struct ice_aqc_get_set_rss_key *cmd_resp; 3442 u16 key_size = sizeof(*key); 3443 struct ice_aq_desc desc; 3444 3445 cmd_resp = &desc.params.get_set_rss_key; 3446 3447 if (set) { 3448 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3449 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3450 } else { 3451 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3452 } 3453 3454 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3455 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3456 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3457 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3458 3459 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3460 } 3461 3462 /** 3463 * ice_aq_get_rss_key 3464 * @hw: pointer to the HW struct 3465 * @vsi_handle: software VSI handle 3466 * @key: pointer to key info struct 3467 * 3468 * get the RSS key per VSI 3469 */ 3470 enum ice_status 3471 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3472 struct ice_aqc_get_set_rss_keys *key) 3473 { 3474 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 3475 return ICE_ERR_PARAM; 3476 3477 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3478 key, false); 3479 } 3480 3481 /** 3482 * ice_aq_set_rss_key 3483 * @hw: pointer to the HW struct 3484 * @vsi_handle: software VSI handle 3485 * @keys: pointer to key info struct 3486 * 3487 * set the RSS key per VSI 3488 */ 3489 enum ice_status 3490 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3491 struct ice_aqc_get_set_rss_keys *keys) 3492 { 3493 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 3494 return ICE_ERR_PARAM; 3495 3496 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3497 keys, true); 3498 } 3499 3500 /** 3501 * ice_aq_add_lan_txq 3502 * @hw: pointer to the hardware structure 3503 * @num_qgrps: Number of added queue groups 3504 * @qg_list: list of queue groups to be added 3505 * @buf_size: size of buffer for indirect command 3506 * @cd: pointer to command details structure or NULL 3507 * 3508 * Add Tx LAN queue (0x0C30) 3509 * 3510 * NOTE: 3511 * Prior to calling add Tx LAN queue: 3512 * Initialize the following as part of the Tx queue context: 3513 * Completion queue ID if the queue uses Completion queue, Quanta profile, 3514 * Cache profile and Packet shaper profile. 3515 * 3516 * After add Tx LAN queue AQ command is completed: 3517 * Interrupts should be associated with specific queues, 3518 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3519 * flow. 3520 */ 3521 static enum ice_status 3522 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3523 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3524 struct ice_sq_cd *cd) 3525 { 3526 struct ice_aqc_add_tx_qgrp *list; 3527 struct ice_aqc_add_txqs *cmd; 3528 struct ice_aq_desc desc; 3529 u16 i, sum_size = 0; 3530 3531 cmd = &desc.params.add_txqs; 3532 3533 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3534 3535 if (!qg_list) 3536 return ICE_ERR_PARAM; 3537 3538 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3539 return ICE_ERR_PARAM; 3540 3541 for (i = 0, list = qg_list; i < num_qgrps; i++) { 3542 sum_size += struct_size(list, txqs, list->num_txqs); 3543 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 3544 list->num_txqs); 3545 } 3546 3547 if (buf_size != sum_size) 3548 return ICE_ERR_PARAM; 3549 3550 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3551 3552 cmd->num_qgrps = num_qgrps; 3553 3554 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3555 } 3556 3557 /** 3558 * ice_aq_dis_lan_txq 3559 * @hw: pointer to the hardware structure 3560 * @num_qgrps: number of groups in the list 3561 * @qg_list: the list of groups to disable 3562 * @buf_size: the total size of the qg_list buffer in bytes 3563 * @rst_src: if called due to reset, specifies the reset source 3564 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3565 * @cd: pointer to command details structure or NULL 3566 * 3567 * Disable LAN Tx queue (0x0C31) 3568 */ 3569 static enum ice_status 3570 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3571 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3572 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3573 struct ice_sq_cd *cd) 3574 { 3575 struct ice_aqc_dis_txq_item *item; 3576 struct ice_aqc_dis_txqs *cmd; 3577 struct ice_aq_desc desc; 3578 enum ice_status status; 3579 u16 i, sz = 0; 3580 3581 cmd = &desc.params.dis_txqs; 3582 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3583 3584 /* qg_list can be NULL only in VM/VF reset flow */ 3585 if (!qg_list && !rst_src) 3586 return ICE_ERR_PARAM; 3587 3588 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3589 return ICE_ERR_PARAM; 3590 3591 cmd->num_entries = num_qgrps; 3592 3593 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3594 ICE_AQC_Q_DIS_TIMEOUT_M); 3595 3596 switch (rst_src) { 3597 case ICE_VM_RESET: 3598 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3599 cmd->vmvf_and_timeout |= 3600 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3601 break; 3602 case ICE_VF_RESET: 3603 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 3604 /* In this case, FW expects vmvf_num to be absolute VF ID */ 3605 cmd->vmvf_and_timeout |= 3606 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 3607 ICE_AQC_Q_DIS_VMVF_NUM_M); 3608 break; 3609 case ICE_NO_RESET: 3610 default: 3611 break; 3612 } 3613 3614 /* flush pipe on time out */ 3615 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3616 /* If no queue group info, we are in a reset flow. Issue the AQ */ 3617 if (!qg_list) 3618 goto do_aq; 3619 3620 /* set RD bit to indicate that command buffer is provided by the driver 3621 * and it needs to be read by the firmware 3622 */ 3623 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3624 3625 for (i = 0, item = qg_list; i < num_qgrps; i++) { 3626 u16 item_size = struct_size(item, q_id, item->num_qs); 3627 3628 /* If the num of queues is even, add 2 bytes of padding */ 3629 if ((item->num_qs % 2) == 0) 3630 item_size += 2; 3631 3632 sz += item_size; 3633 3634 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 3635 } 3636 3637 if (buf_size != sz) 3638 return ICE_ERR_PARAM; 3639 3640 do_aq: 3641 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3642 if (status) { 3643 if (!qg_list) 3644 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 3645 vmvf_num, hw->adminq.sq_last_status); 3646 else 3647 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 3648 le16_to_cpu(qg_list[0].q_id[0]), 3649 hw->adminq.sq_last_status); 3650 } 3651 return status; 3652 } 3653 3654 /** 3655 * ice_aq_add_rdma_qsets 3656 * @hw: pointer to the hardware structure 3657 * @num_qset_grps: Number of RDMA Qset groups 3658 * @qset_list: list of Qset groups to be added 3659 * @buf_size: size of buffer for indirect command 3660 * @cd: pointer to command details structure or NULL 3661 * 3662 * Add Tx RDMA Qsets (0x0C33) 3663 */ 3664 static int 3665 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 3666 struct ice_aqc_add_rdma_qset_data *qset_list, 3667 u16 buf_size, struct ice_sq_cd *cd) 3668 { 3669 struct ice_aqc_add_rdma_qset_data *list; 3670 struct ice_aqc_add_rdma_qset *cmd; 3671 struct ice_aq_desc desc; 3672 u16 i, sum_size = 0; 3673 3674 cmd = &desc.params.add_rdma_qset; 3675 3676 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_rdma_qset); 3677 3678 if (num_qset_grps > ICE_LAN_TXQ_MAX_QGRPS) 3679 return -EINVAL; 3680 3681 for (i = 0, list = qset_list; i < num_qset_grps; i++) { 3682 u16 num_qsets = le16_to_cpu(list->num_qsets); 3683 3684 sum_size += struct_size(list, rdma_qsets, num_qsets); 3685 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + 3686 num_qsets); 3687 } 3688 3689 if (buf_size != sum_size) 3690 return -EINVAL; 3691 3692 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3693 3694 cmd->num_qset_grps = num_qset_grps; 3695 3696 return ice_status_to_errno(ice_aq_send_cmd(hw, &desc, qset_list, 3697 buf_size, cd)); 3698 } 3699 3700 /* End of FW Admin Queue command wrappers */ 3701 3702 /** 3703 * ice_write_byte - write a byte to a packed context structure 3704 * @src_ctx: the context structure to read from 3705 * @dest_ctx: the context to be written to 3706 * @ce_info: a description of the struct to be filled 3707 */ 3708 static void 3709 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3710 { 3711 u8 src_byte, dest_byte, mask; 3712 u8 *from, *dest; 3713 u16 shift_width; 3714 3715 /* copy from the next struct field */ 3716 from = src_ctx + ce_info->offset; 3717 3718 /* prepare the bits and mask */ 3719 shift_width = ce_info->lsb % 8; 3720 mask = (u8)(BIT(ce_info->width) - 1); 3721 3722 src_byte = *from; 3723 src_byte &= mask; 3724 3725 /* shift to correct alignment */ 3726 mask <<= shift_width; 3727 src_byte <<= shift_width; 3728 3729 /* get the current bits from the target bit string */ 3730 dest = dest_ctx + (ce_info->lsb / 8); 3731 3732 memcpy(&dest_byte, dest, sizeof(dest_byte)); 3733 3734 dest_byte &= ~mask; /* get the bits not changing */ 3735 dest_byte |= src_byte; /* add in the new bits */ 3736 3737 /* put it all back */ 3738 memcpy(dest, &dest_byte, sizeof(dest_byte)); 3739 } 3740 3741 /** 3742 * ice_write_word - write a word to a packed context structure 3743 * @src_ctx: the context structure to read from 3744 * @dest_ctx: the context to be written to 3745 * @ce_info: a description of the struct to be filled 3746 */ 3747 static void 3748 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3749 { 3750 u16 src_word, mask; 3751 __le16 dest_word; 3752 u8 *from, *dest; 3753 u16 shift_width; 3754 3755 /* copy from the next struct field */ 3756 from = src_ctx + ce_info->offset; 3757 3758 /* prepare the bits and mask */ 3759 shift_width = ce_info->lsb % 8; 3760 mask = BIT(ce_info->width) - 1; 3761 3762 /* don't swizzle the bits until after the mask because the mask bits 3763 * will be in a different bit position on big endian machines 3764 */ 3765 src_word = *(u16 *)from; 3766 src_word &= mask; 3767 3768 /* shift to correct alignment */ 3769 mask <<= shift_width; 3770 src_word <<= shift_width; 3771 3772 /* get the current bits from the target bit string */ 3773 dest = dest_ctx + (ce_info->lsb / 8); 3774 3775 memcpy(&dest_word, dest, sizeof(dest_word)); 3776 3777 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 3778 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 3779 3780 /* put it all back */ 3781 memcpy(dest, &dest_word, sizeof(dest_word)); 3782 } 3783 3784 /** 3785 * ice_write_dword - write a dword to a packed context structure 3786 * @src_ctx: the context structure to read from 3787 * @dest_ctx: the context to be written to 3788 * @ce_info: a description of the struct to be filled 3789 */ 3790 static void 3791 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3792 { 3793 u32 src_dword, mask; 3794 __le32 dest_dword; 3795 u8 *from, *dest; 3796 u16 shift_width; 3797 3798 /* copy from the next struct field */ 3799 from = src_ctx + ce_info->offset; 3800 3801 /* prepare the bits and mask */ 3802 shift_width = ce_info->lsb % 8; 3803 3804 /* if the field width is exactly 32 on an x86 machine, then the shift 3805 * operation will not work because the SHL instructions count is masked 3806 * to 5 bits so the shift will do nothing 3807 */ 3808 if (ce_info->width < 32) 3809 mask = BIT(ce_info->width) - 1; 3810 else 3811 mask = (u32)~0; 3812 3813 /* don't swizzle the bits until after the mask because the mask bits 3814 * will be in a different bit position on big endian machines 3815 */ 3816 src_dword = *(u32 *)from; 3817 src_dword &= mask; 3818 3819 /* shift to correct alignment */ 3820 mask <<= shift_width; 3821 src_dword <<= shift_width; 3822 3823 /* get the current bits from the target bit string */ 3824 dest = dest_ctx + (ce_info->lsb / 8); 3825 3826 memcpy(&dest_dword, dest, sizeof(dest_dword)); 3827 3828 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 3829 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 3830 3831 /* put it all back */ 3832 memcpy(dest, &dest_dword, sizeof(dest_dword)); 3833 } 3834 3835 /** 3836 * ice_write_qword - write a qword to a packed context structure 3837 * @src_ctx: the context structure to read from 3838 * @dest_ctx: the context to be written to 3839 * @ce_info: a description of the struct to be filled 3840 */ 3841 static void 3842 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3843 { 3844 u64 src_qword, mask; 3845 __le64 dest_qword; 3846 u8 *from, *dest; 3847 u16 shift_width; 3848 3849 /* copy from the next struct field */ 3850 from = src_ctx + ce_info->offset; 3851 3852 /* prepare the bits and mask */ 3853 shift_width = ce_info->lsb % 8; 3854 3855 /* if the field width is exactly 64 on an x86 machine, then the shift 3856 * operation will not work because the SHL instructions count is masked 3857 * to 6 bits so the shift will do nothing 3858 */ 3859 if (ce_info->width < 64) 3860 mask = BIT_ULL(ce_info->width) - 1; 3861 else 3862 mask = (u64)~0; 3863 3864 /* don't swizzle the bits until after the mask because the mask bits 3865 * will be in a different bit position on big endian machines 3866 */ 3867 src_qword = *(u64 *)from; 3868 src_qword &= mask; 3869 3870 /* shift to correct alignment */ 3871 mask <<= shift_width; 3872 src_qword <<= shift_width; 3873 3874 /* get the current bits from the target bit string */ 3875 dest = dest_ctx + (ce_info->lsb / 8); 3876 3877 memcpy(&dest_qword, dest, sizeof(dest_qword)); 3878 3879 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 3880 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 3881 3882 /* put it all back */ 3883 memcpy(dest, &dest_qword, sizeof(dest_qword)); 3884 } 3885 3886 /** 3887 * ice_set_ctx - set context bits in packed structure 3888 * @hw: pointer to the hardware structure 3889 * @src_ctx: pointer to a generic non-packed context structure 3890 * @dest_ctx: pointer to memory for the packed structure 3891 * @ce_info: a description of the structure to be transformed 3892 */ 3893 enum ice_status 3894 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 3895 const struct ice_ctx_ele *ce_info) 3896 { 3897 int f; 3898 3899 for (f = 0; ce_info[f].width; f++) { 3900 /* We have to deal with each element of the FW response 3901 * using the correct size so that we are correct regardless 3902 * of the endianness of the machine. 3903 */ 3904 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 3905 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 3906 f, ce_info[f].width, ce_info[f].size_of); 3907 continue; 3908 } 3909 switch (ce_info[f].size_of) { 3910 case sizeof(u8): 3911 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 3912 break; 3913 case sizeof(u16): 3914 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 3915 break; 3916 case sizeof(u32): 3917 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 3918 break; 3919 case sizeof(u64): 3920 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 3921 break; 3922 default: 3923 return ICE_ERR_INVAL_SIZE; 3924 } 3925 } 3926 3927 return 0; 3928 } 3929 3930 /** 3931 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 3932 * @hw: pointer to the HW struct 3933 * @vsi_handle: software VSI handle 3934 * @tc: TC number 3935 * @q_handle: software queue handle 3936 */ 3937 struct ice_q_ctx * 3938 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 3939 { 3940 struct ice_vsi_ctx *vsi; 3941 struct ice_q_ctx *q_ctx; 3942 3943 vsi = ice_get_vsi_ctx(hw, vsi_handle); 3944 if (!vsi) 3945 return NULL; 3946 if (q_handle >= vsi->num_lan_q_entries[tc]) 3947 return NULL; 3948 if (!vsi->lan_q_ctx[tc]) 3949 return NULL; 3950 q_ctx = vsi->lan_q_ctx[tc]; 3951 return &q_ctx[q_handle]; 3952 } 3953 3954 /** 3955 * ice_ena_vsi_txq 3956 * @pi: port information structure 3957 * @vsi_handle: software VSI handle 3958 * @tc: TC number 3959 * @q_handle: software queue handle 3960 * @num_qgrps: Number of added queue groups 3961 * @buf: list of queue groups to be added 3962 * @buf_size: size of buffer for indirect command 3963 * @cd: pointer to command details structure or NULL 3964 * 3965 * This function adds one LAN queue 3966 */ 3967 enum ice_status 3968 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 3969 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 3970 struct ice_sq_cd *cd) 3971 { 3972 struct ice_aqc_txsched_elem_data node = { 0 }; 3973 struct ice_sched_node *parent; 3974 struct ice_q_ctx *q_ctx; 3975 enum ice_status status; 3976 struct ice_hw *hw; 3977 3978 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3979 return ICE_ERR_CFG; 3980 3981 if (num_qgrps > 1 || buf->num_txqs > 1) 3982 return ICE_ERR_MAX_LIMIT; 3983 3984 hw = pi->hw; 3985 3986 if (!ice_is_vsi_valid(hw, vsi_handle)) 3987 return ICE_ERR_PARAM; 3988 3989 mutex_lock(&pi->sched_lock); 3990 3991 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 3992 if (!q_ctx) { 3993 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 3994 q_handle); 3995 status = ICE_ERR_PARAM; 3996 goto ena_txq_exit; 3997 } 3998 3999 /* find a parent node */ 4000 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4001 ICE_SCHED_NODE_OWNER_LAN); 4002 if (!parent) { 4003 status = ICE_ERR_PARAM; 4004 goto ena_txq_exit; 4005 } 4006 4007 buf->parent_teid = parent->info.node_teid; 4008 node.parent_teid = parent->info.node_teid; 4009 /* Mark that the values in the "generic" section as valid. The default 4010 * value in the "generic" section is zero. This means that : 4011 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 4012 * - 0 priority among siblings, indicated by Bit 1-3. 4013 * - WFQ, indicated by Bit 4. 4014 * - 0 Adjustment value is used in PSM credit update flow, indicated by 4015 * Bit 5-6. 4016 * - Bit 7 is reserved. 4017 * Without setting the generic section as valid in valid_sections, the 4018 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 4019 */ 4020 buf->txqs[0].info.valid_sections = 4021 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4022 ICE_AQC_ELEM_VALID_EIR; 4023 buf->txqs[0].info.generic = 0; 4024 buf->txqs[0].info.cir_bw.bw_profile_idx = 4025 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4026 buf->txqs[0].info.cir_bw.bw_alloc = 4027 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4028 buf->txqs[0].info.eir_bw.bw_profile_idx = 4029 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4030 buf->txqs[0].info.eir_bw.bw_alloc = 4031 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4032 4033 /* add the LAN queue */ 4034 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 4035 if (status) { 4036 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 4037 le16_to_cpu(buf->txqs[0].txq_id), 4038 hw->adminq.sq_last_status); 4039 goto ena_txq_exit; 4040 } 4041 4042 node.node_teid = buf->txqs[0].q_teid; 4043 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4044 q_ctx->q_handle = q_handle; 4045 q_ctx->q_teid = le32_to_cpu(node.node_teid); 4046 4047 /* add a leaf node into scheduler tree queue layer */ 4048 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 4049 if (!status) 4050 status = ice_sched_replay_q_bw(pi, q_ctx); 4051 4052 ena_txq_exit: 4053 mutex_unlock(&pi->sched_lock); 4054 return status; 4055 } 4056 4057 /** 4058 * ice_dis_vsi_txq 4059 * @pi: port information structure 4060 * @vsi_handle: software VSI handle 4061 * @tc: TC number 4062 * @num_queues: number of queues 4063 * @q_handles: pointer to software queue handle array 4064 * @q_ids: pointer to the q_id array 4065 * @q_teids: pointer to queue node teids 4066 * @rst_src: if called due to reset, specifies the reset source 4067 * @vmvf_num: the relative VM or VF number that is undergoing the reset 4068 * @cd: pointer to command details structure or NULL 4069 * 4070 * This function removes queues and their corresponding nodes in SW DB 4071 */ 4072 enum ice_status 4073 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 4074 u16 *q_handles, u16 *q_ids, u32 *q_teids, 4075 enum ice_disq_rst_src rst_src, u16 vmvf_num, 4076 struct ice_sq_cd *cd) 4077 { 4078 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 4079 struct ice_aqc_dis_txq_item *qg_list; 4080 struct ice_q_ctx *q_ctx; 4081 struct ice_hw *hw; 4082 u16 i, buf_size; 4083 4084 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4085 return ICE_ERR_CFG; 4086 4087 hw = pi->hw; 4088 4089 if (!num_queues) { 4090 /* if queue is disabled already yet the disable queue command 4091 * has to be sent to complete the VF reset, then call 4092 * ice_aq_dis_lan_txq without any queue information 4093 */ 4094 if (rst_src) 4095 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 4096 vmvf_num, NULL); 4097 return ICE_ERR_CFG; 4098 } 4099 4100 buf_size = struct_size(qg_list, q_id, 1); 4101 qg_list = kzalloc(buf_size, GFP_KERNEL); 4102 if (!qg_list) 4103 return ICE_ERR_NO_MEMORY; 4104 4105 mutex_lock(&pi->sched_lock); 4106 4107 for (i = 0; i < num_queues; i++) { 4108 struct ice_sched_node *node; 4109 4110 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 4111 if (!node) 4112 continue; 4113 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4114 if (!q_ctx) { 4115 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4116 q_handles[i]); 4117 continue; 4118 } 4119 if (q_ctx->q_handle != q_handles[i]) { 4120 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4121 q_ctx->q_handle, q_handles[i]); 4122 continue; 4123 } 4124 qg_list->parent_teid = node->info.parent_teid; 4125 qg_list->num_qs = 1; 4126 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4127 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4128 vmvf_num, cd); 4129 4130 if (status) 4131 break; 4132 ice_free_sched_node(pi, node); 4133 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4134 } 4135 mutex_unlock(&pi->sched_lock); 4136 kfree(qg_list); 4137 return status; 4138 } 4139 4140 /** 4141 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4142 * @pi: port information structure 4143 * @vsi_handle: software VSI handle 4144 * @tc_bitmap: TC bitmap 4145 * @maxqs: max queues array per TC 4146 * @owner: LAN or RDMA 4147 * 4148 * This function adds/updates the VSI queues per TC. 4149 */ 4150 static enum ice_status 4151 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4152 u16 *maxqs, u8 owner) 4153 { 4154 enum ice_status status = 0; 4155 u8 i; 4156 4157 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4158 return ICE_ERR_CFG; 4159 4160 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4161 return ICE_ERR_PARAM; 4162 4163 mutex_lock(&pi->sched_lock); 4164 4165 ice_for_each_traffic_class(i) { 4166 /* configuration is possible only if TC node is present */ 4167 if (!ice_sched_get_tc_node(pi, i)) 4168 continue; 4169 4170 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4171 ice_is_tc_ena(tc_bitmap, i)); 4172 if (status) 4173 break; 4174 } 4175 4176 mutex_unlock(&pi->sched_lock); 4177 return status; 4178 } 4179 4180 /** 4181 * ice_cfg_vsi_lan - configure VSI LAN queues 4182 * @pi: port information structure 4183 * @vsi_handle: software VSI handle 4184 * @tc_bitmap: TC bitmap 4185 * @max_lanqs: max LAN queues array per TC 4186 * 4187 * This function adds/updates the VSI LAN queues per TC. 4188 */ 4189 enum ice_status 4190 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4191 u16 *max_lanqs) 4192 { 4193 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4194 ICE_SCHED_NODE_OWNER_LAN); 4195 } 4196 4197 /** 4198 * ice_cfg_vsi_rdma - configure the VSI RDMA queues 4199 * @pi: port information structure 4200 * @vsi_handle: software VSI handle 4201 * @tc_bitmap: TC bitmap 4202 * @max_rdmaqs: max RDMA queues array per TC 4203 * 4204 * This function adds/updates the VSI RDMA queues per TC. 4205 */ 4206 int 4207 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 4208 u16 *max_rdmaqs) 4209 { 4210 return ice_status_to_errno(ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, 4211 max_rdmaqs, 4212 ICE_SCHED_NODE_OWNER_RDMA)); 4213 } 4214 4215 /** 4216 * ice_ena_vsi_rdma_qset 4217 * @pi: port information structure 4218 * @vsi_handle: software VSI handle 4219 * @tc: TC number 4220 * @rdma_qset: pointer to RDMA Qset 4221 * @num_qsets: number of RDMA Qsets 4222 * @qset_teid: pointer to Qset node TEIDs 4223 * 4224 * This function adds RDMA Qset 4225 */ 4226 int 4227 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4228 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid) 4229 { 4230 struct ice_aqc_txsched_elem_data node = { 0 }; 4231 struct ice_aqc_add_rdma_qset_data *buf; 4232 struct ice_sched_node *parent; 4233 enum ice_status status; 4234 struct ice_hw *hw; 4235 u16 i, buf_size; 4236 int ret; 4237 4238 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4239 return -EIO; 4240 hw = pi->hw; 4241 4242 if (!ice_is_vsi_valid(hw, vsi_handle)) 4243 return -EINVAL; 4244 4245 buf_size = struct_size(buf, rdma_qsets, num_qsets); 4246 buf = kzalloc(buf_size, GFP_KERNEL); 4247 if (!buf) 4248 return -ENOMEM; 4249 mutex_lock(&pi->sched_lock); 4250 4251 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 4252 ICE_SCHED_NODE_OWNER_RDMA); 4253 if (!parent) { 4254 ret = -EINVAL; 4255 goto rdma_error_exit; 4256 } 4257 buf->parent_teid = parent->info.node_teid; 4258 node.parent_teid = parent->info.node_teid; 4259 4260 buf->num_qsets = cpu_to_le16(num_qsets); 4261 for (i = 0; i < num_qsets; i++) { 4262 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); 4263 buf->rdma_qsets[i].info.valid_sections = 4264 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 4265 ICE_AQC_ELEM_VALID_EIR; 4266 buf->rdma_qsets[i].info.generic = 0; 4267 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = 4268 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4269 buf->rdma_qsets[i].info.cir_bw.bw_alloc = 4270 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4271 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = 4272 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 4273 buf->rdma_qsets[i].info.eir_bw.bw_alloc = 4274 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 4275 } 4276 ret = ice_aq_add_rdma_qsets(hw, 1, buf, buf_size, NULL); 4277 if (ret) { 4278 ice_debug(hw, ICE_DBG_RDMA, "add RDMA qset failed\n"); 4279 goto rdma_error_exit; 4280 } 4281 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 4282 for (i = 0; i < num_qsets; i++) { 4283 node.node_teid = buf->rdma_qsets[i].qset_teid; 4284 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, 4285 &node); 4286 if (status) { 4287 ret = ice_status_to_errno(status); 4288 break; 4289 } 4290 qset_teid[i] = le32_to_cpu(node.node_teid); 4291 } 4292 rdma_error_exit: 4293 mutex_unlock(&pi->sched_lock); 4294 kfree(buf); 4295 return ret; 4296 } 4297 4298 /** 4299 * ice_dis_vsi_rdma_qset - free RDMA resources 4300 * @pi: port_info struct 4301 * @count: number of RDMA Qsets to free 4302 * @qset_teid: TEID of Qset node 4303 * @q_id: list of queue IDs being disabled 4304 */ 4305 int 4306 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 4307 u16 *q_id) 4308 { 4309 struct ice_aqc_dis_txq_item *qg_list; 4310 enum ice_status status = 0; 4311 struct ice_hw *hw; 4312 u16 qg_size; 4313 int i; 4314 4315 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4316 return -EIO; 4317 4318 hw = pi->hw; 4319 4320 qg_size = struct_size(qg_list, q_id, 1); 4321 qg_list = kzalloc(qg_size, GFP_KERNEL); 4322 if (!qg_list) 4323 return -ENOMEM; 4324 4325 mutex_lock(&pi->sched_lock); 4326 4327 for (i = 0; i < count; i++) { 4328 struct ice_sched_node *node; 4329 4330 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); 4331 if (!node) 4332 continue; 4333 4334 qg_list->parent_teid = node->info.parent_teid; 4335 qg_list->num_qs = 1; 4336 qg_list->q_id[0] = 4337 cpu_to_le16(q_id[i] | 4338 ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET); 4339 4340 status = ice_aq_dis_lan_txq(hw, 1, qg_list, qg_size, 4341 ICE_NO_RESET, 0, NULL); 4342 if (status) 4343 break; 4344 4345 ice_free_sched_node(pi, node); 4346 } 4347 4348 mutex_unlock(&pi->sched_lock); 4349 kfree(qg_list); 4350 return ice_status_to_errno(status); 4351 } 4352 4353 /** 4354 * ice_replay_pre_init - replay pre initialization 4355 * @hw: pointer to the HW struct 4356 * 4357 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4358 */ 4359 static enum ice_status ice_replay_pre_init(struct ice_hw *hw) 4360 { 4361 struct ice_switch_info *sw = hw->switch_info; 4362 u8 i; 4363 4364 /* Delete old entries from replay filter list head if there is any */ 4365 ice_rm_all_sw_replay_rule_info(hw); 4366 /* In start of replay, move entries into replay_rules list, it 4367 * will allow adding rules entries back to filt_rules list, 4368 * which is operational list. 4369 */ 4370 for (i = 0; i < ICE_SW_LKUP_LAST; i++) 4371 list_replace_init(&sw->recp_list[i].filt_rules, 4372 &sw->recp_list[i].filt_replay_rules); 4373 ice_sched_replay_agg_vsi_preinit(hw); 4374 4375 return 0; 4376 } 4377 4378 /** 4379 * ice_replay_vsi - replay VSI configuration 4380 * @hw: pointer to the HW struct 4381 * @vsi_handle: driver VSI handle 4382 * 4383 * Restore all VSI configuration after reset. It is required to call this 4384 * function with main VSI first. 4385 */ 4386 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4387 { 4388 enum ice_status status; 4389 4390 if (!ice_is_vsi_valid(hw, vsi_handle)) 4391 return ICE_ERR_PARAM; 4392 4393 /* Replay pre-initialization if there is any */ 4394 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 4395 status = ice_replay_pre_init(hw); 4396 if (status) 4397 return status; 4398 } 4399 /* Replay per VSI all RSS configurations */ 4400 status = ice_replay_rss_cfg(hw, vsi_handle); 4401 if (status) 4402 return status; 4403 /* Replay per VSI all filters */ 4404 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 4405 if (!status) 4406 status = ice_replay_vsi_agg(hw, vsi_handle); 4407 return status; 4408 } 4409 4410 /** 4411 * ice_replay_post - post replay configuration cleanup 4412 * @hw: pointer to the HW struct 4413 * 4414 * Post replay cleanup. 4415 */ 4416 void ice_replay_post(struct ice_hw *hw) 4417 { 4418 /* Delete old entries from replay filter list head */ 4419 ice_rm_all_sw_replay_rule_info(hw); 4420 ice_sched_replay_agg(hw); 4421 } 4422 4423 /** 4424 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4425 * @hw: ptr to the hardware info 4426 * @reg: offset of 64 bit HW register to read from 4427 * @prev_stat_loaded: bool to specify if previous stats are loaded 4428 * @prev_stat: ptr to previous loaded stat value 4429 * @cur_stat: ptr to current stat value 4430 */ 4431 void 4432 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4433 u64 *prev_stat, u64 *cur_stat) 4434 { 4435 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4436 4437 /* device stats are not reset at PFR, they likely will not be zeroed 4438 * when the driver starts. Thus, save the value from the first read 4439 * without adding to the statistic value so that we report stats which 4440 * count up from zero. 4441 */ 4442 if (!prev_stat_loaded) { 4443 *prev_stat = new_data; 4444 return; 4445 } 4446 4447 /* Calculate the difference between the new and old values, and then 4448 * add it to the software stat value. 4449 */ 4450 if (new_data >= *prev_stat) 4451 *cur_stat += new_data - *prev_stat; 4452 else 4453 /* to manage the potential roll-over */ 4454 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4455 4456 /* Update the previously stored value to prepare for next read */ 4457 *prev_stat = new_data; 4458 } 4459 4460 /** 4461 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4462 * @hw: ptr to the hardware info 4463 * @reg: offset of HW register to read from 4464 * @prev_stat_loaded: bool to specify if previous stats are loaded 4465 * @prev_stat: ptr to previous loaded stat value 4466 * @cur_stat: ptr to current stat value 4467 */ 4468 void 4469 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4470 u64 *prev_stat, u64 *cur_stat) 4471 { 4472 u32 new_data; 4473 4474 new_data = rd32(hw, reg); 4475 4476 /* device stats are not reset at PFR, they likely will not be zeroed 4477 * when the driver starts. Thus, save the value from the first read 4478 * without adding to the statistic value so that we report stats which 4479 * count up from zero. 4480 */ 4481 if (!prev_stat_loaded) { 4482 *prev_stat = new_data; 4483 return; 4484 } 4485 4486 /* Calculate the difference between the new and old values, and then 4487 * add it to the software stat value. 4488 */ 4489 if (new_data >= *prev_stat) 4490 *cur_stat += new_data - *prev_stat; 4491 else 4492 /* to manage the potential roll-over */ 4493 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 4494 4495 /* Update the previously stored value to prepare for next read */ 4496 *prev_stat = new_data; 4497 } 4498 4499 /** 4500 * ice_sched_query_elem - query element information from HW 4501 * @hw: pointer to the HW struct 4502 * @node_teid: node TEID to be queried 4503 * @buf: buffer to element information 4504 * 4505 * This function queries HW element information 4506 */ 4507 enum ice_status 4508 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4509 struct ice_aqc_txsched_elem_data *buf) 4510 { 4511 u16 buf_size, num_elem_ret = 0; 4512 enum ice_status status; 4513 4514 buf_size = sizeof(*buf); 4515 memset(buf, 0, buf_size); 4516 buf->node_teid = cpu_to_le32(node_teid); 4517 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 4518 NULL); 4519 if (status || num_elem_ret != 1) 4520 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 4521 return status; 4522 } 4523 4524 /** 4525 * ice_fw_supports_link_override 4526 * @hw: pointer to the hardware structure 4527 * 4528 * Checks if the firmware supports link override 4529 */ 4530 bool ice_fw_supports_link_override(struct ice_hw *hw) 4531 { 4532 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 4533 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 4534 return true; 4535 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 4536 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 4537 return true; 4538 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 4539 return true; 4540 } 4541 4542 return false; 4543 } 4544 4545 /** 4546 * ice_get_link_default_override 4547 * @ldo: pointer to the link default override struct 4548 * @pi: pointer to the port info struct 4549 * 4550 * Gets the link default override for a port 4551 */ 4552 enum ice_status 4553 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 4554 struct ice_port_info *pi) 4555 { 4556 u16 i, tlv, tlv_len, tlv_start, buf, offset; 4557 struct ice_hw *hw = pi->hw; 4558 enum ice_status status; 4559 4560 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 4561 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 4562 if (status) { 4563 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 4564 return status; 4565 } 4566 4567 /* Each port has its own config; calculate for our port */ 4568 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 4569 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 4570 4571 /* link options first */ 4572 status = ice_read_sr_word(hw, tlv_start, &buf); 4573 if (status) { 4574 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4575 return status; 4576 } 4577 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 4578 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 4579 ICE_LINK_OVERRIDE_PHY_CFG_S; 4580 4581 /* link PHY config */ 4582 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 4583 status = ice_read_sr_word(hw, offset, &buf); 4584 if (status) { 4585 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 4586 return status; 4587 } 4588 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 4589 4590 /* PHY types low */ 4591 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 4592 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4593 status = ice_read_sr_word(hw, (offset + i), &buf); 4594 if (status) { 4595 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4596 return status; 4597 } 4598 /* shift 16 bits at a time to fill 64 bits */ 4599 ldo->phy_type_low |= ((u64)buf << (i * 16)); 4600 } 4601 4602 /* PHY types high */ 4603 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 4604 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 4605 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4606 status = ice_read_sr_word(hw, (offset + i), &buf); 4607 if (status) { 4608 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4609 return status; 4610 } 4611 /* shift 16 bits at a time to fill 64 bits */ 4612 ldo->phy_type_high |= ((u64)buf << (i * 16)); 4613 } 4614 4615 return status; 4616 } 4617 4618 /** 4619 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 4620 * @caps: get PHY capability data 4621 */ 4622 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 4623 { 4624 if (caps->caps & ICE_AQC_PHY_AN_MODE || 4625 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 4626 ICE_AQC_PHY_AN_EN_CLAUSE73 | 4627 ICE_AQC_PHY_AN_EN_CLAUSE37)) 4628 return true; 4629 4630 return false; 4631 } 4632 4633 /** 4634 * ice_aq_set_lldp_mib - Set the LLDP MIB 4635 * @hw: pointer to the HW struct 4636 * @mib_type: Local, Remote or both Local and Remote MIBs 4637 * @buf: pointer to the caller-supplied buffer to store the MIB block 4638 * @buf_size: size of the buffer (in bytes) 4639 * @cd: pointer to command details structure or NULL 4640 * 4641 * Set the LLDP MIB. (0x0A08) 4642 */ 4643 enum ice_status 4644 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 4645 struct ice_sq_cd *cd) 4646 { 4647 struct ice_aqc_lldp_set_local_mib *cmd; 4648 struct ice_aq_desc desc; 4649 4650 cmd = &desc.params.lldp_set_mib; 4651 4652 if (buf_size == 0 || !buf) 4653 return ICE_ERR_PARAM; 4654 4655 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 4656 4657 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 4658 desc.datalen = cpu_to_le16(buf_size); 4659 4660 cmd->type = mib_type; 4661 cmd->length = cpu_to_le16(buf_size); 4662 4663 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4664 } 4665 4666 /** 4667 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl 4668 * @hw: pointer to HW struct 4669 */ 4670 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 4671 { 4672 if (hw->mac_type != ICE_MAC_E810) 4673 return false; 4674 4675 if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) { 4676 if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN) 4677 return true; 4678 if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN && 4679 hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH) 4680 return true; 4681 } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) { 4682 return true; 4683 } 4684 return false; 4685 } 4686 4687 /** 4688 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 4689 * @hw: pointer to HW struct 4690 * @vsi_num: absolute HW index for VSI 4691 * @add: boolean for if adding or removing a filter 4692 */ 4693 enum ice_status 4694 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 4695 { 4696 struct ice_aqc_lldp_filter_ctrl *cmd; 4697 struct ice_aq_desc desc; 4698 4699 cmd = &desc.params.lldp_filter_ctrl; 4700 4701 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 4702 4703 if (add) 4704 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 4705 else 4706 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 4707 4708 cmd->vsi_num = cpu_to_le16(vsi_num); 4709 4710 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4711 } 4712 4713 /** 4714 * ice_fw_supports_report_dflt_cfg 4715 * @hw: pointer to the hardware structure 4716 * 4717 * Checks if the firmware supports report default configuration 4718 */ 4719 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 4720 { 4721 if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 4722 if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN) 4723 return true; 4724 if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN && 4725 hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH) 4726 return true; 4727 } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 4728 return true; 4729 } 4730 return false; 4731 } 4732