1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 9 #define ICE_PF_RESET_WAIT_COUNT 300 10 11 /** 12 * ice_set_mac_type - Sets MAC type 13 * @hw: pointer to the HW structure 14 * 15 * This function sets the MAC type of the adapter based on the 16 * vendor ID and device ID stored in the HW structure. 17 */ 18 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 19 { 20 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 21 return ICE_ERR_DEVICE_NOT_SUPPORTED; 22 23 hw->mac_type = ICE_MAC_GENERIC; 24 return 0; 25 } 26 27 /** 28 * ice_clear_pf_cfg - Clear PF configuration 29 * @hw: pointer to the hardware structure 30 * 31 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 32 * configuration, flow director filters, etc.). 33 */ 34 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 35 { 36 struct ice_aq_desc desc; 37 38 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 39 40 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 41 } 42 43 /** 44 * ice_aq_manage_mac_read - manage MAC address read command 45 * @hw: pointer to the HW struct 46 * @buf: a virtual buffer to hold the manage MAC read response 47 * @buf_size: Size of the virtual buffer 48 * @cd: pointer to command details structure or NULL 49 * 50 * This function is used to return per PF station MAC address (0x0107). 51 * NOTE: Upon successful completion of this command, MAC address information 52 * is returned in user specified buffer. Please interpret user specified 53 * buffer as "manage_mac_read" response. 54 * Response such as various MAC addresses are stored in HW struct (port.mac) 55 * ice_aq_discover_caps is expected to be called before this function is called. 56 */ 57 static enum ice_status 58 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 59 struct ice_sq_cd *cd) 60 { 61 struct ice_aqc_manage_mac_read_resp *resp; 62 struct ice_aqc_manage_mac_read *cmd; 63 struct ice_aq_desc desc; 64 enum ice_status status; 65 u16 flags; 66 u8 i; 67 68 cmd = &desc.params.mac_read; 69 70 if (buf_size < sizeof(*resp)) 71 return ICE_ERR_BUF_TOO_SHORT; 72 73 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 74 75 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 76 if (status) 77 return status; 78 79 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 80 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 81 82 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 83 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 84 return ICE_ERR_CFG; 85 } 86 87 /* A single port can report up to two (LAN and WoL) addresses */ 88 for (i = 0; i < cmd->num_addr; i++) 89 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 90 ether_addr_copy(hw->port_info->mac.lan_addr, 91 resp[i].mac_addr); 92 ether_addr_copy(hw->port_info->mac.perm_addr, 93 resp[i].mac_addr); 94 break; 95 } 96 97 return 0; 98 } 99 100 /** 101 * ice_aq_get_phy_caps - returns PHY capabilities 102 * @pi: port information structure 103 * @qual_mods: report qualified modules 104 * @report_mode: report mode capabilities 105 * @pcaps: structure for PHY capabilities to be filled 106 * @cd: pointer to command details structure or NULL 107 * 108 * Returns the various PHY capabilities supported on the Port (0x0600) 109 */ 110 enum ice_status 111 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 112 struct ice_aqc_get_phy_caps_data *pcaps, 113 struct ice_sq_cd *cd) 114 { 115 struct ice_aqc_get_phy_caps *cmd; 116 u16 pcaps_size = sizeof(*pcaps); 117 struct ice_aq_desc desc; 118 enum ice_status status; 119 120 cmd = &desc.params.get_phy; 121 122 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 123 return ICE_ERR_PARAM; 124 125 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 126 127 if (qual_mods) 128 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 129 130 cmd->param0 |= cpu_to_le16(report_mode); 131 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd); 132 133 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) { 134 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 135 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 136 } 137 138 return status; 139 } 140 141 /** 142 * ice_get_media_type - Gets media type 143 * @pi: port information structure 144 */ 145 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 146 { 147 struct ice_link_status *hw_link_info; 148 149 if (!pi) 150 return ICE_MEDIA_UNKNOWN; 151 152 hw_link_info = &pi->phy.link_info; 153 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 154 /* If more than one media type is selected, report unknown */ 155 return ICE_MEDIA_UNKNOWN; 156 157 if (hw_link_info->phy_type_low) { 158 switch (hw_link_info->phy_type_low) { 159 case ICE_PHY_TYPE_LOW_1000BASE_SX: 160 case ICE_PHY_TYPE_LOW_1000BASE_LX: 161 case ICE_PHY_TYPE_LOW_10GBASE_SR: 162 case ICE_PHY_TYPE_LOW_10GBASE_LR: 163 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 164 case ICE_PHY_TYPE_LOW_25GBASE_SR: 165 case ICE_PHY_TYPE_LOW_25GBASE_LR: 166 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 167 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 168 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 169 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 170 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 171 case ICE_PHY_TYPE_LOW_50GBASE_SR: 172 case ICE_PHY_TYPE_LOW_50GBASE_FR: 173 case ICE_PHY_TYPE_LOW_50GBASE_LR: 174 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 175 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 176 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 177 case ICE_PHY_TYPE_LOW_100GBASE_DR: 178 return ICE_MEDIA_FIBER; 179 case ICE_PHY_TYPE_LOW_100BASE_TX: 180 case ICE_PHY_TYPE_LOW_1000BASE_T: 181 case ICE_PHY_TYPE_LOW_2500BASE_T: 182 case ICE_PHY_TYPE_LOW_5GBASE_T: 183 case ICE_PHY_TYPE_LOW_10GBASE_T: 184 case ICE_PHY_TYPE_LOW_25GBASE_T: 185 return ICE_MEDIA_BASET; 186 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 187 case ICE_PHY_TYPE_LOW_25GBASE_CR: 188 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 189 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 190 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 191 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 192 case ICE_PHY_TYPE_LOW_50GBASE_CP: 193 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 194 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 195 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 196 return ICE_MEDIA_DA; 197 case ICE_PHY_TYPE_LOW_1000BASE_KX: 198 case ICE_PHY_TYPE_LOW_2500BASE_KX: 199 case ICE_PHY_TYPE_LOW_2500BASE_X: 200 case ICE_PHY_TYPE_LOW_5GBASE_KR: 201 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 202 case ICE_PHY_TYPE_LOW_25GBASE_KR: 203 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 204 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 205 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 206 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 207 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 208 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 209 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 210 return ICE_MEDIA_BACKPLANE; 211 } 212 } else { 213 switch (hw_link_info->phy_type_high) { 214 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 215 return ICE_MEDIA_BACKPLANE; 216 } 217 } 218 return ICE_MEDIA_UNKNOWN; 219 } 220 221 /** 222 * ice_aq_get_link_info 223 * @pi: port information structure 224 * @ena_lse: enable/disable LinkStatusEvent reporting 225 * @link: pointer to link status structure - optional 226 * @cd: pointer to command details structure or NULL 227 * 228 * Get Link Status (0x607). Returns the link status of the adapter. 229 */ 230 enum ice_status 231 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 232 struct ice_link_status *link, struct ice_sq_cd *cd) 233 { 234 struct ice_aqc_get_link_status_data link_data = { 0 }; 235 struct ice_aqc_get_link_status *resp; 236 struct ice_link_status *li_old, *li; 237 enum ice_media_type *hw_media_type; 238 struct ice_fc_info *hw_fc_info; 239 bool tx_pause, rx_pause; 240 struct ice_aq_desc desc; 241 enum ice_status status; 242 struct ice_hw *hw; 243 u16 cmd_flags; 244 245 if (!pi) 246 return ICE_ERR_PARAM; 247 hw = pi->hw; 248 li_old = &pi->phy.link_info_old; 249 hw_media_type = &pi->phy.media_type; 250 li = &pi->phy.link_info; 251 hw_fc_info = &pi->fc; 252 253 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 254 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 255 resp = &desc.params.get_link_status; 256 resp->cmd_flags = cpu_to_le16(cmd_flags); 257 resp->lport_num = pi->lport; 258 259 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 260 261 if (status) 262 return status; 263 264 /* save off old link status information */ 265 *li_old = *li; 266 267 /* update current link status information */ 268 li->link_speed = le16_to_cpu(link_data.link_speed); 269 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 270 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 271 *hw_media_type = ice_get_media_type(pi); 272 li->link_info = link_data.link_info; 273 li->an_info = link_data.an_info; 274 li->ext_info = link_data.ext_info; 275 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 276 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 277 li->topo_media_conflict = link_data.topo_media_conflict; 278 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 279 ICE_AQ_CFG_PACING_TYPE_M); 280 281 /* update fc info */ 282 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 283 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 284 if (tx_pause && rx_pause) 285 hw_fc_info->current_mode = ICE_FC_FULL; 286 else if (tx_pause) 287 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 288 else if (rx_pause) 289 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 290 else 291 hw_fc_info->current_mode = ICE_FC_NONE; 292 293 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 294 295 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed); 296 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n", 297 (unsigned long long)li->phy_type_low); 298 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n", 299 (unsigned long long)li->phy_type_high); 300 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type); 301 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info); 302 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info); 303 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info); 304 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena); 305 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size); 306 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing); 307 308 /* save link status information */ 309 if (link) 310 *link = *li; 311 312 /* flag cleared so calling functions don't call AQ again */ 313 pi->phy.get_link_info = false; 314 315 return 0; 316 } 317 318 /** 319 * ice_fill_tx_timer_and_fc_thresh 320 * @hw: pointer to the HW struct 321 * @cmd: pointer to MAC cfg structure 322 * 323 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 324 * descriptor 325 */ 326 static void 327 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 328 struct ice_aqc_set_mac_cfg *cmd) 329 { 330 u16 fc_thres_val, tx_timer_val; 331 u32 val; 332 333 /* We read back the transmit timer and FC threshold value of 334 * LFC. Thus, we will use index = 335 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 336 * 337 * Also, because we are operating on transmit timer and FC 338 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 339 */ 340 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 341 342 /* Retrieve the transmit timer */ 343 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 344 tx_timer_val = val & 345 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 346 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val); 347 348 /* Retrieve the FC threshold */ 349 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 350 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 351 352 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val); 353 } 354 355 /** 356 * ice_aq_set_mac_cfg 357 * @hw: pointer to the HW struct 358 * @max_frame_size: Maximum Frame Size to be supported 359 * @cd: pointer to command details structure or NULL 360 * 361 * Set MAC configuration (0x0603) 362 */ 363 enum ice_status 364 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 365 { 366 struct ice_aqc_set_mac_cfg *cmd; 367 struct ice_aq_desc desc; 368 369 cmd = &desc.params.set_mac_cfg; 370 371 if (max_frame_size == 0) 372 return ICE_ERR_PARAM; 373 374 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 375 376 cmd->max_frame_size = cpu_to_le16(max_frame_size); 377 378 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 379 380 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 381 } 382 383 /** 384 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 385 * @hw: pointer to the HW struct 386 */ 387 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 388 { 389 struct ice_switch_info *sw; 390 enum ice_status status; 391 392 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 393 sizeof(*hw->switch_info), GFP_KERNEL); 394 sw = hw->switch_info; 395 396 if (!sw) 397 return ICE_ERR_NO_MEMORY; 398 399 INIT_LIST_HEAD(&sw->vsi_list_map_head); 400 401 status = ice_init_def_sw_recp(hw); 402 if (status) { 403 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 404 return status; 405 } 406 return 0; 407 } 408 409 /** 410 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 411 * @hw: pointer to the HW struct 412 */ 413 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 414 { 415 struct ice_switch_info *sw = hw->switch_info; 416 struct ice_vsi_list_map_info *v_pos_map; 417 struct ice_vsi_list_map_info *v_tmp_map; 418 struct ice_sw_recipe *recps; 419 u8 i; 420 421 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 422 list_entry) { 423 list_del(&v_pos_map->list_entry); 424 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 425 } 426 recps = hw->switch_info->recp_list; 427 for (i = 0; i < ICE_SW_LKUP_LAST; i++) { 428 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 429 430 recps[i].root_rid = i; 431 mutex_destroy(&recps[i].filt_rule_lock); 432 list_for_each_entry_safe(lst_itr, tmp_entry, 433 &recps[i].filt_rules, list_entry) { 434 list_del(&lst_itr->list_entry); 435 devm_kfree(ice_hw_to_dev(hw), lst_itr); 436 } 437 } 438 ice_rm_all_sw_replay_rule_info(hw); 439 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 440 devm_kfree(ice_hw_to_dev(hw), sw); 441 } 442 443 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \ 444 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry))) 445 #define ICE_FW_LOG_DESC_SIZE_MAX \ 446 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX) 447 448 /** 449 * ice_get_fw_log_cfg - get FW logging configuration 450 * @hw: pointer to the HW struct 451 */ 452 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw) 453 { 454 struct ice_aqc_fw_logging_data *config; 455 struct ice_aq_desc desc; 456 enum ice_status status; 457 u16 size; 458 459 size = ICE_FW_LOG_DESC_SIZE_MAX; 460 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL); 461 if (!config) 462 return ICE_ERR_NO_MEMORY; 463 464 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 465 466 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_BUF); 467 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 468 469 status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 470 if (!status) { 471 u16 i; 472 473 /* Save FW logging information into the HW structure */ 474 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 475 u16 v, m, flgs; 476 477 v = le16_to_cpu(config->entry[i]); 478 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 479 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 480 481 if (m < ICE_AQC_FW_LOG_ID_MAX) 482 hw->fw_log.evnts[m].cur = flgs; 483 } 484 } 485 486 devm_kfree(ice_hw_to_dev(hw), config); 487 488 return status; 489 } 490 491 /** 492 * ice_cfg_fw_log - configure FW logging 493 * @hw: pointer to the HW struct 494 * @enable: enable certain FW logging events if true, disable all if false 495 * 496 * This function enables/disables the FW logging via Rx CQ events and a UART 497 * port based on predetermined configurations. FW logging via the Rx CQ can be 498 * enabled/disabled for individual PF's. However, FW logging via the UART can 499 * only be enabled/disabled for all PFs on the same device. 500 * 501 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 502 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 503 * before initializing the device. 504 * 505 * When re/configuring FW logging, callers need to update the "cfg" elements of 506 * the hw->fw_log.evnts array with the desired logging event configurations for 507 * modules of interest. When disabling FW logging completely, the callers can 508 * just pass false in the "enable" parameter. On completion, the function will 509 * update the "cur" element of the hw->fw_log.evnts array with the resulting 510 * logging event configurations of the modules that are being re/configured. FW 511 * logging modules that are not part of a reconfiguration operation retain their 512 * previous states. 513 * 514 * Before resetting the device, it is recommended that the driver disables FW 515 * logging before shutting down the control queue. When disabling FW logging 516 * ("enable" = false), the latest configurations of FW logging events stored in 517 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 518 * a device reset. 519 * 520 * When enabling FW logging to emit log messages via the Rx CQ during the 521 * device's initialization phase, a mechanism alternative to interrupt handlers 522 * needs to be used to extract FW log messages from the Rx CQ periodically and 523 * to prevent the Rx CQ from being full and stalling other types of control 524 * messages from FW to SW. Interrupts are typically disabled during the device's 525 * initialization phase. 526 */ 527 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable) 528 { 529 struct ice_aqc_fw_logging_data *data = NULL; 530 struct ice_aqc_fw_logging *cmd; 531 enum ice_status status = 0; 532 u16 i, chgs = 0, len = 0; 533 struct ice_aq_desc desc; 534 u8 actv_evnts = 0; 535 void *buf = NULL; 536 537 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 538 return 0; 539 540 /* Disable FW logging only when the control queue is still responsive */ 541 if (!enable && 542 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 543 return 0; 544 545 /* Get current FW log settings */ 546 status = ice_get_fw_log_cfg(hw); 547 if (status) 548 return status; 549 550 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 551 cmd = &desc.params.fw_logging; 552 553 /* Indicate which controls are valid */ 554 if (hw->fw_log.cq_en) 555 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 556 557 if (hw->fw_log.uart_en) 558 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 559 560 if (enable) { 561 /* Fill in an array of entries with FW logging modules and 562 * logging events being reconfigured. 563 */ 564 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 565 u16 val; 566 567 /* Keep track of enabled event types */ 568 actv_evnts |= hw->fw_log.evnts[i].cfg; 569 570 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 571 continue; 572 573 if (!data) { 574 data = devm_kzalloc(ice_hw_to_dev(hw), 575 ICE_FW_LOG_DESC_SIZE_MAX, 576 GFP_KERNEL); 577 if (!data) 578 return ICE_ERR_NO_MEMORY; 579 } 580 581 val = i << ICE_AQC_FW_LOG_ID_S; 582 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 583 data->entry[chgs++] = cpu_to_le16(val); 584 } 585 586 /* Only enable FW logging if at least one module is specified. 587 * If FW logging is currently enabled but all modules are not 588 * enabled to emit log messages, disable FW logging altogether. 589 */ 590 if (actv_evnts) { 591 /* Leave if there is effectively no change */ 592 if (!chgs) 593 goto out; 594 595 if (hw->fw_log.cq_en) 596 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 597 598 if (hw->fw_log.uart_en) 599 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 600 601 buf = data; 602 len = ICE_FW_LOG_DESC_SIZE(chgs); 603 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 604 } 605 } 606 607 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 608 if (!status) { 609 /* Update the current configuration to reflect events enabled. 610 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 611 * logging mode is enabled for the device. They do not reflect 612 * actual modules being enabled to emit log messages. So, their 613 * values remain unchanged even when all modules are disabled. 614 */ 615 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 616 617 hw->fw_log.actv_evnts = actv_evnts; 618 for (i = 0; i < cnt; i++) { 619 u16 v, m; 620 621 if (!enable) { 622 /* When disabling all FW logging events as part 623 * of device's de-initialization, the original 624 * configurations are retained, and can be used 625 * to reconfigure FW logging later if the device 626 * is re-initialized. 627 */ 628 hw->fw_log.evnts[i].cur = 0; 629 continue; 630 } 631 632 v = le16_to_cpu(data->entry[i]); 633 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 634 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 635 } 636 } 637 638 out: 639 if (data) 640 devm_kfree(ice_hw_to_dev(hw), data); 641 642 return status; 643 } 644 645 /** 646 * ice_output_fw_log 647 * @hw: pointer to the HW struct 648 * @desc: pointer to the AQ message descriptor 649 * @buf: pointer to the buffer accompanying the AQ message 650 * 651 * Formats a FW Log message and outputs it via the standard driver logs. 652 */ 653 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 654 { 655 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 656 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 657 le16_to_cpu(desc->datalen)); 658 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 659 } 660 661 /** 662 * ice_get_itr_intrl_gran 663 * @hw: pointer to the HW struct 664 * 665 * Determines the ITR/INTRL granularities based on the maximum aggregate 666 * bandwidth according to the device's configuration during power-on. 667 */ 668 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 669 { 670 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 671 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 672 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 673 674 switch (max_agg_bw) { 675 case ICE_MAX_AGG_BW_200G: 676 case ICE_MAX_AGG_BW_100G: 677 case ICE_MAX_AGG_BW_50G: 678 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 679 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 680 break; 681 case ICE_MAX_AGG_BW_25G: 682 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 683 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 684 break; 685 } 686 } 687 688 /** 689 * ice_init_hw - main hardware initialization routine 690 * @hw: pointer to the hardware structure 691 */ 692 enum ice_status ice_init_hw(struct ice_hw *hw) 693 { 694 struct ice_aqc_get_phy_caps_data *pcaps; 695 enum ice_status status; 696 u16 mac_buf_len; 697 void *mac_buf; 698 699 /* Set MAC type based on DeviceID */ 700 status = ice_set_mac_type(hw); 701 if (status) 702 return status; 703 704 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 705 PF_FUNC_RID_FUNC_NUM_M) >> 706 PF_FUNC_RID_FUNC_NUM_S; 707 708 status = ice_reset(hw, ICE_RESET_PFR); 709 if (status) 710 return status; 711 712 ice_get_itr_intrl_gran(hw); 713 714 status = ice_create_all_ctrlq(hw); 715 if (status) 716 goto err_unroll_cqinit; 717 718 /* Enable FW logging. Not fatal if this fails. */ 719 status = ice_cfg_fw_log(hw, true); 720 if (status) 721 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 722 723 status = ice_clear_pf_cfg(hw); 724 if (status) 725 goto err_unroll_cqinit; 726 727 /* Set bit to enable Flow Director filters */ 728 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 729 INIT_LIST_HEAD(&hw->fdir_list_head); 730 731 ice_clear_pxe_mode(hw); 732 733 status = ice_init_nvm(hw); 734 if (status) 735 goto err_unroll_cqinit; 736 737 status = ice_get_caps(hw); 738 if (status) 739 goto err_unroll_cqinit; 740 741 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 742 sizeof(*hw->port_info), GFP_KERNEL); 743 if (!hw->port_info) { 744 status = ICE_ERR_NO_MEMORY; 745 goto err_unroll_cqinit; 746 } 747 748 /* set the back pointer to HW */ 749 hw->port_info->hw = hw; 750 751 /* Initialize port_info struct with switch configuration data */ 752 status = ice_get_initial_sw_cfg(hw); 753 if (status) 754 goto err_unroll_alloc; 755 756 hw->evb_veb = true; 757 758 /* Query the allocated resources for Tx scheduler */ 759 status = ice_sched_query_res_alloc(hw); 760 if (status) { 761 ice_debug(hw, ICE_DBG_SCHED, 762 "Failed to get scheduler allocated resources\n"); 763 goto err_unroll_alloc; 764 } 765 766 /* Initialize port_info struct with scheduler data */ 767 status = ice_sched_init_port(hw->port_info); 768 if (status) 769 goto err_unroll_sched; 770 771 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 772 if (!pcaps) { 773 status = ICE_ERR_NO_MEMORY; 774 goto err_unroll_sched; 775 } 776 777 /* Initialize port_info struct with PHY capabilities */ 778 status = ice_aq_get_phy_caps(hw->port_info, false, 779 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); 780 devm_kfree(ice_hw_to_dev(hw), pcaps); 781 if (status) 782 goto err_unroll_sched; 783 784 /* Initialize port_info struct with link information */ 785 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 786 if (status) 787 goto err_unroll_sched; 788 789 /* need a valid SW entry point to build a Tx tree */ 790 if (!hw->sw_entry_point_layer) { 791 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 792 status = ICE_ERR_CFG; 793 goto err_unroll_sched; 794 } 795 INIT_LIST_HEAD(&hw->agg_list); 796 /* Initialize max burst size */ 797 if (!hw->max_burst_size) 798 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 799 800 status = ice_init_fltr_mgmt_struct(hw); 801 if (status) 802 goto err_unroll_sched; 803 804 /* Get MAC information */ 805 /* A single port can report up to two (LAN and WoL) addresses */ 806 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 807 sizeof(struct ice_aqc_manage_mac_read_resp), 808 GFP_KERNEL); 809 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 810 811 if (!mac_buf) { 812 status = ICE_ERR_NO_MEMORY; 813 goto err_unroll_fltr_mgmt_struct; 814 } 815 816 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 817 devm_kfree(ice_hw_to_dev(hw), mac_buf); 818 819 if (status) 820 goto err_unroll_fltr_mgmt_struct; 821 /* enable jumbo frame support at MAC level */ 822 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 823 if (status) 824 goto err_unroll_fltr_mgmt_struct; 825 /* Obtain counter base index which would be used by flow director */ 826 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 827 if (status) 828 goto err_unroll_fltr_mgmt_struct; 829 status = ice_init_hw_tbls(hw); 830 if (status) 831 goto err_unroll_fltr_mgmt_struct; 832 mutex_init(&hw->tnl_lock); 833 return 0; 834 835 err_unroll_fltr_mgmt_struct: 836 ice_cleanup_fltr_mgmt_struct(hw); 837 err_unroll_sched: 838 ice_sched_cleanup_all(hw); 839 err_unroll_alloc: 840 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 841 err_unroll_cqinit: 842 ice_destroy_all_ctrlq(hw); 843 return status; 844 } 845 846 /** 847 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 848 * @hw: pointer to the hardware structure 849 * 850 * This should be called only during nominal operation, not as a result of 851 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 852 * applicable initializations if it fails for any reason. 853 */ 854 void ice_deinit_hw(struct ice_hw *hw) 855 { 856 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 857 ice_cleanup_fltr_mgmt_struct(hw); 858 859 ice_sched_cleanup_all(hw); 860 ice_sched_clear_agg(hw); 861 ice_free_seg(hw); 862 ice_free_hw_tbls(hw); 863 mutex_destroy(&hw->tnl_lock); 864 865 if (hw->port_info) { 866 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 867 hw->port_info = NULL; 868 } 869 870 /* Attempt to disable FW logging before shutting down control queues */ 871 ice_cfg_fw_log(hw, false); 872 ice_destroy_all_ctrlq(hw); 873 874 /* Clear VSI contexts if not already cleared */ 875 ice_clear_all_vsi_ctx(hw); 876 } 877 878 /** 879 * ice_check_reset - Check to see if a global reset is complete 880 * @hw: pointer to the hardware structure 881 */ 882 enum ice_status ice_check_reset(struct ice_hw *hw) 883 { 884 u32 cnt, reg = 0, grst_delay, uld_mask; 885 886 /* Poll for Device Active state in case a recent CORER, GLOBR, 887 * or EMPR has occurred. The grst delay value is in 100ms units. 888 * Add 1sec for outstanding AQ commands that can take a long time. 889 */ 890 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 891 GLGEN_RSTCTL_GRSTDEL_S) + 10; 892 893 for (cnt = 0; cnt < grst_delay; cnt++) { 894 mdelay(100); 895 reg = rd32(hw, GLGEN_RSTAT); 896 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 897 break; 898 } 899 900 if (cnt == grst_delay) { 901 ice_debug(hw, ICE_DBG_INIT, 902 "Global reset polling failed to complete.\n"); 903 return ICE_ERR_RESET_FAILED; 904 } 905 906 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 907 GLNVM_ULD_PCIER_DONE_1_M |\ 908 GLNVM_ULD_CORER_DONE_M |\ 909 GLNVM_ULD_GLOBR_DONE_M |\ 910 GLNVM_ULD_POR_DONE_M |\ 911 GLNVM_ULD_POR_DONE_1_M |\ 912 GLNVM_ULD_PCIER_DONE_2_M) 913 914 uld_mask = ICE_RESET_DONE_MASK; 915 916 /* Device is Active; check Global Reset processes are done */ 917 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 918 reg = rd32(hw, GLNVM_ULD) & uld_mask; 919 if (reg == uld_mask) { 920 ice_debug(hw, ICE_DBG_INIT, 921 "Global reset processes done. %d\n", cnt); 922 break; 923 } 924 mdelay(10); 925 } 926 927 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 928 ice_debug(hw, ICE_DBG_INIT, 929 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 930 reg); 931 return ICE_ERR_RESET_FAILED; 932 } 933 934 return 0; 935 } 936 937 /** 938 * ice_pf_reset - Reset the PF 939 * @hw: pointer to the hardware structure 940 * 941 * If a global reset has been triggered, this function checks 942 * for its completion and then issues the PF reset 943 */ 944 static enum ice_status ice_pf_reset(struct ice_hw *hw) 945 { 946 u32 cnt, reg; 947 948 /* If at function entry a global reset was already in progress, i.e. 949 * state is not 'device active' or any of the reset done bits are not 950 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 951 * global reset is done. 952 */ 953 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 954 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 955 /* poll on global reset currently in progress until done */ 956 if (ice_check_reset(hw)) 957 return ICE_ERR_RESET_FAILED; 958 959 return 0; 960 } 961 962 /* Reset the PF */ 963 reg = rd32(hw, PFGEN_CTRL); 964 965 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 966 967 /* Wait for the PFR to complete. The wait time is the global config lock 968 * timeout plus the PFR timeout which will account for a possible reset 969 * that is occurring during a download package operation. 970 */ 971 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 972 ICE_PF_RESET_WAIT_COUNT; cnt++) { 973 reg = rd32(hw, PFGEN_CTRL); 974 if (!(reg & PFGEN_CTRL_PFSWR_M)) 975 break; 976 977 mdelay(1); 978 } 979 980 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 981 ice_debug(hw, ICE_DBG_INIT, 982 "PF reset polling failed to complete.\n"); 983 return ICE_ERR_RESET_FAILED; 984 } 985 986 return 0; 987 } 988 989 /** 990 * ice_reset - Perform different types of reset 991 * @hw: pointer to the hardware structure 992 * @req: reset request 993 * 994 * This function triggers a reset as specified by the req parameter. 995 * 996 * Note: 997 * If anything other than a PF reset is triggered, PXE mode is restored. 998 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 999 * interface has been restored in the rebuild flow. 1000 */ 1001 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1002 { 1003 u32 val = 0; 1004 1005 switch (req) { 1006 case ICE_RESET_PFR: 1007 return ice_pf_reset(hw); 1008 case ICE_RESET_CORER: 1009 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1010 val = GLGEN_RTRIG_CORER_M; 1011 break; 1012 case ICE_RESET_GLOBR: 1013 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1014 val = GLGEN_RTRIG_GLOBR_M; 1015 break; 1016 default: 1017 return ICE_ERR_PARAM; 1018 } 1019 1020 val |= rd32(hw, GLGEN_RTRIG); 1021 wr32(hw, GLGEN_RTRIG, val); 1022 ice_flush(hw); 1023 1024 /* wait for the FW to be ready */ 1025 return ice_check_reset(hw); 1026 } 1027 1028 /** 1029 * ice_copy_rxq_ctx_to_hw 1030 * @hw: pointer to the hardware structure 1031 * @ice_rxq_ctx: pointer to the rxq context 1032 * @rxq_index: the index of the Rx queue 1033 * 1034 * Copies rxq context from dense structure to HW register space 1035 */ 1036 static enum ice_status 1037 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1038 { 1039 u8 i; 1040 1041 if (!ice_rxq_ctx) 1042 return ICE_ERR_BAD_PTR; 1043 1044 if (rxq_index > QRX_CTRL_MAX_INDEX) 1045 return ICE_ERR_PARAM; 1046 1047 /* Copy each dword separately to HW */ 1048 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1049 wr32(hw, QRX_CONTEXT(i, rxq_index), 1050 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1051 1052 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1053 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1054 } 1055 1056 return 0; 1057 } 1058 1059 /* LAN Rx Queue Context */ 1060 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1061 /* Field Width LSB */ 1062 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1063 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1064 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1065 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1066 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1067 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1068 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1069 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1070 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1071 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1072 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1073 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1074 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1075 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1076 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1077 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1078 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1079 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1080 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1081 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1082 { 0 } 1083 }; 1084 1085 /** 1086 * ice_write_rxq_ctx 1087 * @hw: pointer to the hardware structure 1088 * @rlan_ctx: pointer to the rxq context 1089 * @rxq_index: the index of the Rx queue 1090 * 1091 * Converts rxq context from sparse to dense structure and then writes 1092 * it to HW register space and enables the hardware to prefetch descriptors 1093 * instead of only fetching them on demand 1094 */ 1095 enum ice_status 1096 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1097 u32 rxq_index) 1098 { 1099 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1100 1101 if (!rlan_ctx) 1102 return ICE_ERR_BAD_PTR; 1103 1104 rlan_ctx->prefena = 1; 1105 1106 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1107 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1108 } 1109 1110 /* LAN Tx Queue Context */ 1111 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1112 /* Field Width LSB */ 1113 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1114 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1115 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1116 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1117 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1118 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1119 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1120 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1121 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1122 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1123 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1124 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1125 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1126 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1127 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1128 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1129 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1130 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1131 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1132 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1133 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1134 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1135 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1136 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1137 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1138 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1139 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1140 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1141 { 0 } 1142 }; 1143 1144 /* FW Admin Queue command wrappers */ 1145 1146 /* Software lock/mutex that is meant to be held while the Global Config Lock 1147 * in firmware is acquired by the software to prevent most (but not all) types 1148 * of AQ commands from being sent to FW 1149 */ 1150 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1151 1152 /** 1153 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1154 * @hw: pointer to the HW struct 1155 * @desc: descriptor describing the command 1156 * @buf: buffer to use for indirect commands (NULL for direct commands) 1157 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1158 * @cd: pointer to command details structure 1159 * 1160 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1161 */ 1162 enum ice_status 1163 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1164 u16 buf_size, struct ice_sq_cd *cd) 1165 { 1166 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1167 bool lock_acquired = false; 1168 enum ice_status status; 1169 1170 /* When a package download is in process (i.e. when the firmware's 1171 * Global Configuration Lock resource is held), only the Download 1172 * Package, Get Version, Get Package Info List and Release Resource 1173 * (with resource ID set to Global Config Lock) AdminQ commands are 1174 * allowed; all others must block until the package download completes 1175 * and the Global Config Lock is released. See also 1176 * ice_acquire_global_cfg_lock(). 1177 */ 1178 switch (le16_to_cpu(desc->opcode)) { 1179 case ice_aqc_opc_download_pkg: 1180 case ice_aqc_opc_get_pkg_info_list: 1181 case ice_aqc_opc_get_ver: 1182 break; 1183 case ice_aqc_opc_release_res: 1184 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1185 break; 1186 fallthrough; 1187 default: 1188 mutex_lock(&ice_global_cfg_lock_sw); 1189 lock_acquired = true; 1190 break; 1191 } 1192 1193 status = ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); 1194 if (lock_acquired) 1195 mutex_unlock(&ice_global_cfg_lock_sw); 1196 1197 return status; 1198 } 1199 1200 /** 1201 * ice_aq_get_fw_ver 1202 * @hw: pointer to the HW struct 1203 * @cd: pointer to command details structure or NULL 1204 * 1205 * Get the firmware version (0x0001) from the admin queue commands 1206 */ 1207 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1208 { 1209 struct ice_aqc_get_ver *resp; 1210 struct ice_aq_desc desc; 1211 enum ice_status status; 1212 1213 resp = &desc.params.get_ver; 1214 1215 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1216 1217 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1218 1219 if (!status) { 1220 hw->fw_branch = resp->fw_branch; 1221 hw->fw_maj_ver = resp->fw_major; 1222 hw->fw_min_ver = resp->fw_minor; 1223 hw->fw_patch = resp->fw_patch; 1224 hw->fw_build = le32_to_cpu(resp->fw_build); 1225 hw->api_branch = resp->api_branch; 1226 hw->api_maj_ver = resp->api_major; 1227 hw->api_min_ver = resp->api_minor; 1228 hw->api_patch = resp->api_patch; 1229 } 1230 1231 return status; 1232 } 1233 1234 /** 1235 * ice_aq_send_driver_ver 1236 * @hw: pointer to the HW struct 1237 * @dv: driver's major, minor version 1238 * @cd: pointer to command details structure or NULL 1239 * 1240 * Send the driver version (0x0002) to the firmware 1241 */ 1242 enum ice_status 1243 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1244 struct ice_sq_cd *cd) 1245 { 1246 struct ice_aqc_driver_ver *cmd; 1247 struct ice_aq_desc desc; 1248 u16 len; 1249 1250 cmd = &desc.params.driver_ver; 1251 1252 if (!dv) 1253 return ICE_ERR_PARAM; 1254 1255 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1256 1257 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1258 cmd->major_ver = dv->major_ver; 1259 cmd->minor_ver = dv->minor_ver; 1260 cmd->build_ver = dv->build_ver; 1261 cmd->subbuild_ver = dv->subbuild_ver; 1262 1263 len = 0; 1264 while (len < sizeof(dv->driver_string) && 1265 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1266 len++; 1267 1268 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1269 } 1270 1271 /** 1272 * ice_aq_q_shutdown 1273 * @hw: pointer to the HW struct 1274 * @unloading: is the driver unloading itself 1275 * 1276 * Tell the Firmware that we're shutting down the AdminQ and whether 1277 * or not the driver is unloading as well (0x0003). 1278 */ 1279 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1280 { 1281 struct ice_aqc_q_shutdown *cmd; 1282 struct ice_aq_desc desc; 1283 1284 cmd = &desc.params.q_shutdown; 1285 1286 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1287 1288 if (unloading) 1289 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1290 1291 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1292 } 1293 1294 /** 1295 * ice_aq_req_res 1296 * @hw: pointer to the HW struct 1297 * @res: resource ID 1298 * @access: access type 1299 * @sdp_number: resource number 1300 * @timeout: the maximum time in ms that the driver may hold the resource 1301 * @cd: pointer to command details structure or NULL 1302 * 1303 * Requests common resource using the admin queue commands (0x0008). 1304 * When attempting to acquire the Global Config Lock, the driver can 1305 * learn of three states: 1306 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1307 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1308 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1309 * successfully downloaded the package; the driver does 1310 * not have to download the package and can continue 1311 * loading 1312 * 1313 * Note that if the caller is in an acquire lock, perform action, release lock 1314 * phase of operation, it is possible that the FW may detect a timeout and issue 1315 * a CORER. In this case, the driver will receive a CORER interrupt and will 1316 * have to determine its cause. The calling thread that is handling this flow 1317 * will likely get an error propagated back to it indicating the Download 1318 * Package, Update Package or the Release Resource AQ commands timed out. 1319 */ 1320 static enum ice_status 1321 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1322 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1323 struct ice_sq_cd *cd) 1324 { 1325 struct ice_aqc_req_res *cmd_resp; 1326 struct ice_aq_desc desc; 1327 enum ice_status status; 1328 1329 cmd_resp = &desc.params.res_owner; 1330 1331 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1332 1333 cmd_resp->res_id = cpu_to_le16(res); 1334 cmd_resp->access_type = cpu_to_le16(access); 1335 cmd_resp->res_number = cpu_to_le32(sdp_number); 1336 cmd_resp->timeout = cpu_to_le32(*timeout); 1337 *timeout = 0; 1338 1339 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1340 1341 /* The completion specifies the maximum time in ms that the driver 1342 * may hold the resource in the Timeout field. 1343 */ 1344 1345 /* Global config lock response utilizes an additional status field. 1346 * 1347 * If the Global config lock resource is held by some other driver, the 1348 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1349 * and the timeout field indicates the maximum time the current owner 1350 * of the resource has to free it. 1351 */ 1352 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1353 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1354 *timeout = le32_to_cpu(cmd_resp->timeout); 1355 return 0; 1356 } else if (le16_to_cpu(cmd_resp->status) == 1357 ICE_AQ_RES_GLBL_IN_PROG) { 1358 *timeout = le32_to_cpu(cmd_resp->timeout); 1359 return ICE_ERR_AQ_ERROR; 1360 } else if (le16_to_cpu(cmd_resp->status) == 1361 ICE_AQ_RES_GLBL_DONE) { 1362 return ICE_ERR_AQ_NO_WORK; 1363 } 1364 1365 /* invalid FW response, force a timeout immediately */ 1366 *timeout = 0; 1367 return ICE_ERR_AQ_ERROR; 1368 } 1369 1370 /* If the resource is held by some other driver, the command completes 1371 * with a busy return value and the timeout field indicates the maximum 1372 * time the current owner of the resource has to free it. 1373 */ 1374 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1375 *timeout = le32_to_cpu(cmd_resp->timeout); 1376 1377 return status; 1378 } 1379 1380 /** 1381 * ice_aq_release_res 1382 * @hw: pointer to the HW struct 1383 * @res: resource ID 1384 * @sdp_number: resource number 1385 * @cd: pointer to command details structure or NULL 1386 * 1387 * release common resource using the admin queue commands (0x0009) 1388 */ 1389 static enum ice_status 1390 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1391 struct ice_sq_cd *cd) 1392 { 1393 struct ice_aqc_req_res *cmd; 1394 struct ice_aq_desc desc; 1395 1396 cmd = &desc.params.res_owner; 1397 1398 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1399 1400 cmd->res_id = cpu_to_le16(res); 1401 cmd->res_number = cpu_to_le32(sdp_number); 1402 1403 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1404 } 1405 1406 /** 1407 * ice_acquire_res 1408 * @hw: pointer to the HW structure 1409 * @res: resource ID 1410 * @access: access type (read or write) 1411 * @timeout: timeout in milliseconds 1412 * 1413 * This function will attempt to acquire the ownership of a resource. 1414 */ 1415 enum ice_status 1416 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1417 enum ice_aq_res_access_type access, u32 timeout) 1418 { 1419 #define ICE_RES_POLLING_DELAY_MS 10 1420 u32 delay = ICE_RES_POLLING_DELAY_MS; 1421 u32 time_left = timeout; 1422 enum ice_status status; 1423 1424 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1425 1426 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1427 * previously acquired the resource and performed any necessary updates; 1428 * in this case the caller does not obtain the resource and has no 1429 * further work to do. 1430 */ 1431 if (status == ICE_ERR_AQ_NO_WORK) 1432 goto ice_acquire_res_exit; 1433 1434 if (status) 1435 ice_debug(hw, ICE_DBG_RES, 1436 "resource %d acquire type %d failed.\n", res, access); 1437 1438 /* If necessary, poll until the current lock owner timeouts */ 1439 timeout = time_left; 1440 while (status && timeout && time_left) { 1441 mdelay(delay); 1442 timeout = (timeout > delay) ? timeout - delay : 0; 1443 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1444 1445 if (status == ICE_ERR_AQ_NO_WORK) 1446 /* lock free, but no work to do */ 1447 break; 1448 1449 if (!status) 1450 /* lock acquired */ 1451 break; 1452 } 1453 if (status && status != ICE_ERR_AQ_NO_WORK) 1454 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1455 1456 ice_acquire_res_exit: 1457 if (status == ICE_ERR_AQ_NO_WORK) { 1458 if (access == ICE_RES_WRITE) 1459 ice_debug(hw, ICE_DBG_RES, 1460 "resource indicates no work to do.\n"); 1461 else 1462 ice_debug(hw, ICE_DBG_RES, 1463 "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1464 } 1465 return status; 1466 } 1467 1468 /** 1469 * ice_release_res 1470 * @hw: pointer to the HW structure 1471 * @res: resource ID 1472 * 1473 * This function will release a resource using the proper Admin Command. 1474 */ 1475 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1476 { 1477 enum ice_status status; 1478 u32 total_delay = 0; 1479 1480 status = ice_aq_release_res(hw, res, 0, NULL); 1481 1482 /* there are some rare cases when trying to release the resource 1483 * results in an admin queue timeout, so handle them correctly 1484 */ 1485 while ((status == ICE_ERR_AQ_TIMEOUT) && 1486 (total_delay < hw->adminq.sq_cmd_timeout)) { 1487 mdelay(1); 1488 status = ice_aq_release_res(hw, res, 0, NULL); 1489 total_delay++; 1490 } 1491 } 1492 1493 /** 1494 * ice_aq_alloc_free_res - command to allocate/free resources 1495 * @hw: pointer to the HW struct 1496 * @num_entries: number of resource entries in buffer 1497 * @buf: Indirect buffer to hold data parameters and response 1498 * @buf_size: size of buffer for indirect commands 1499 * @opc: pass in the command opcode 1500 * @cd: pointer to command details structure or NULL 1501 * 1502 * Helper function to allocate/free resources using the admin queue commands 1503 */ 1504 enum ice_status 1505 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1506 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1507 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1508 { 1509 struct ice_aqc_alloc_free_res_cmd *cmd; 1510 struct ice_aq_desc desc; 1511 1512 cmd = &desc.params.sw_res_ctrl; 1513 1514 if (!buf) 1515 return ICE_ERR_PARAM; 1516 1517 if (buf_size < (num_entries * sizeof(buf->elem[0]))) 1518 return ICE_ERR_PARAM; 1519 1520 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1521 1522 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1523 1524 cmd->num_entries = cpu_to_le16(num_entries); 1525 1526 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1527 } 1528 1529 /** 1530 * ice_alloc_hw_res - allocate resource 1531 * @hw: pointer to the HW struct 1532 * @type: type of resource 1533 * @num: number of resources to allocate 1534 * @btm: allocate from bottom 1535 * @res: pointer to array that will receive the resources 1536 */ 1537 enum ice_status 1538 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1539 { 1540 struct ice_aqc_alloc_free_res_elem *buf; 1541 enum ice_status status; 1542 u16 buf_len; 1543 1544 buf_len = struct_size(buf, elem, num - 1); 1545 buf = kzalloc(buf_len, GFP_KERNEL); 1546 if (!buf) 1547 return ICE_ERR_NO_MEMORY; 1548 1549 /* Prepare buffer to allocate resource. */ 1550 buf->num_elems = cpu_to_le16(num); 1551 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1552 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1553 if (btm) 1554 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1555 1556 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1557 ice_aqc_opc_alloc_res, NULL); 1558 if (status) 1559 goto ice_alloc_res_exit; 1560 1561 memcpy(res, buf->elem, sizeof(buf->elem) * num); 1562 1563 ice_alloc_res_exit: 1564 kfree(buf); 1565 return status; 1566 } 1567 1568 /** 1569 * ice_free_hw_res - free allocated HW resource 1570 * @hw: pointer to the HW struct 1571 * @type: type of resource to free 1572 * @num: number of resources 1573 * @res: pointer to array that contains the resources to free 1574 */ 1575 enum ice_status 1576 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1577 { 1578 struct ice_aqc_alloc_free_res_elem *buf; 1579 enum ice_status status; 1580 u16 buf_len; 1581 1582 buf_len = struct_size(buf, elem, num - 1); 1583 buf = kzalloc(buf_len, GFP_KERNEL); 1584 if (!buf) 1585 return ICE_ERR_NO_MEMORY; 1586 1587 /* Prepare buffer to free resource. */ 1588 buf->num_elems = cpu_to_le16(num); 1589 buf->res_type = cpu_to_le16(type); 1590 memcpy(buf->elem, res, sizeof(buf->elem) * num); 1591 1592 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1593 ice_aqc_opc_free_res, NULL); 1594 if (status) 1595 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1596 1597 kfree(buf); 1598 return status; 1599 } 1600 1601 /** 1602 * ice_get_num_per_func - determine number of resources per PF 1603 * @hw: pointer to the HW structure 1604 * @max: value to be evenly split between each PF 1605 * 1606 * Determine the number of valid functions by going through the bitmap returned 1607 * from parsing capabilities and use this to calculate the number of resources 1608 * per PF based on the max value passed in. 1609 */ 1610 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1611 { 1612 u8 funcs; 1613 1614 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1615 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 1616 ICE_CAPS_VALID_FUNCS_M); 1617 1618 if (!funcs) 1619 return 0; 1620 1621 return max / funcs; 1622 } 1623 1624 /** 1625 * ice_parse_caps - parse function/device capabilities 1626 * @hw: pointer to the HW struct 1627 * @buf: pointer to a buffer containing function/device capability records 1628 * @cap_count: number of capability records in the list 1629 * @opc: type of capabilities list to parse 1630 * 1631 * Helper function to parse function(0x000a)/device(0x000b) capabilities list. 1632 */ 1633 static void 1634 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, 1635 enum ice_adminq_opc opc) 1636 { 1637 struct ice_aqc_list_caps_elem *cap_resp; 1638 struct ice_hw_func_caps *func_p = NULL; 1639 struct ice_hw_dev_caps *dev_p = NULL; 1640 struct ice_hw_common_caps *caps; 1641 char const *prefix; 1642 u32 i; 1643 1644 if (!buf) 1645 return; 1646 1647 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 1648 1649 if (opc == ice_aqc_opc_list_dev_caps) { 1650 dev_p = &hw->dev_caps; 1651 caps = &dev_p->common_cap; 1652 prefix = "dev cap"; 1653 } else if (opc == ice_aqc_opc_list_func_caps) { 1654 func_p = &hw->func_caps; 1655 caps = &func_p->common_cap; 1656 prefix = "func cap"; 1657 } else { 1658 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n"); 1659 return; 1660 } 1661 1662 for (i = 0; caps && i < cap_count; i++, cap_resp++) { 1663 u32 logical_id = le32_to_cpu(cap_resp->logical_id); 1664 u32 phys_id = le32_to_cpu(cap_resp->phys_id); 1665 u32 number = le32_to_cpu(cap_resp->number); 1666 u16 cap = le16_to_cpu(cap_resp->cap); 1667 1668 switch (cap) { 1669 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1670 caps->valid_functions = number; 1671 ice_debug(hw, ICE_DBG_INIT, 1672 "%s: valid_functions (bitmap) = %d\n", prefix, 1673 caps->valid_functions); 1674 1675 /* store func count for resource management purposes */ 1676 if (dev_p) 1677 dev_p->num_funcs = hweight32(number); 1678 break; 1679 case ICE_AQC_CAPS_SRIOV: 1680 caps->sr_iov_1_1 = (number == 1); 1681 ice_debug(hw, ICE_DBG_INIT, 1682 "%s: sr_iov_1_1 = %d\n", prefix, 1683 caps->sr_iov_1_1); 1684 break; 1685 case ICE_AQC_CAPS_VF: 1686 if (dev_p) { 1687 dev_p->num_vfs_exposed = number; 1688 ice_debug(hw, ICE_DBG_INIT, 1689 "%s: num_vfs_exposed = %d\n", prefix, 1690 dev_p->num_vfs_exposed); 1691 } else if (func_p) { 1692 func_p->num_allocd_vfs = number; 1693 func_p->vf_base_id = logical_id; 1694 ice_debug(hw, ICE_DBG_INIT, 1695 "%s: num_allocd_vfs = %d\n", prefix, 1696 func_p->num_allocd_vfs); 1697 ice_debug(hw, ICE_DBG_INIT, 1698 "%s: vf_base_id = %d\n", prefix, 1699 func_p->vf_base_id); 1700 } 1701 break; 1702 case ICE_AQC_CAPS_VSI: 1703 if (dev_p) { 1704 dev_p->num_vsi_allocd_to_host = number; 1705 ice_debug(hw, ICE_DBG_INIT, 1706 "%s: num_vsi_allocd_to_host = %d\n", 1707 prefix, 1708 dev_p->num_vsi_allocd_to_host); 1709 } else if (func_p) { 1710 func_p->guar_num_vsi = 1711 ice_get_num_per_func(hw, ICE_MAX_VSI); 1712 ice_debug(hw, ICE_DBG_INIT, 1713 "%s: guar_num_vsi (fw) = %d\n", 1714 prefix, number); 1715 ice_debug(hw, ICE_DBG_INIT, 1716 "%s: guar_num_vsi = %d\n", 1717 prefix, func_p->guar_num_vsi); 1718 } 1719 break; 1720 case ICE_AQC_CAPS_DCB: 1721 caps->dcb = (number == 1); 1722 caps->active_tc_bitmap = logical_id; 1723 caps->maxtc = phys_id; 1724 ice_debug(hw, ICE_DBG_INIT, 1725 "%s: dcb = %d\n", prefix, caps->dcb); 1726 ice_debug(hw, ICE_DBG_INIT, 1727 "%s: active_tc_bitmap = %d\n", prefix, 1728 caps->active_tc_bitmap); 1729 ice_debug(hw, ICE_DBG_INIT, 1730 "%s: maxtc = %d\n", prefix, caps->maxtc); 1731 break; 1732 case ICE_AQC_CAPS_RSS: 1733 caps->rss_table_size = number; 1734 caps->rss_table_entry_width = logical_id; 1735 ice_debug(hw, ICE_DBG_INIT, 1736 "%s: rss_table_size = %d\n", prefix, 1737 caps->rss_table_size); 1738 ice_debug(hw, ICE_DBG_INIT, 1739 "%s: rss_table_entry_width = %d\n", prefix, 1740 caps->rss_table_entry_width); 1741 break; 1742 case ICE_AQC_CAPS_RXQS: 1743 caps->num_rxq = number; 1744 caps->rxq_first_id = phys_id; 1745 ice_debug(hw, ICE_DBG_INIT, 1746 "%s: num_rxq = %d\n", prefix, 1747 caps->num_rxq); 1748 ice_debug(hw, ICE_DBG_INIT, 1749 "%s: rxq_first_id = %d\n", prefix, 1750 caps->rxq_first_id); 1751 break; 1752 case ICE_AQC_CAPS_TXQS: 1753 caps->num_txq = number; 1754 caps->txq_first_id = phys_id; 1755 ice_debug(hw, ICE_DBG_INIT, 1756 "%s: num_txq = %d\n", prefix, 1757 caps->num_txq); 1758 ice_debug(hw, ICE_DBG_INIT, 1759 "%s: txq_first_id = %d\n", prefix, 1760 caps->txq_first_id); 1761 break; 1762 case ICE_AQC_CAPS_MSIX: 1763 caps->num_msix_vectors = number; 1764 caps->msix_vector_first_id = phys_id; 1765 ice_debug(hw, ICE_DBG_INIT, 1766 "%s: num_msix_vectors = %d\n", prefix, 1767 caps->num_msix_vectors); 1768 ice_debug(hw, ICE_DBG_INIT, 1769 "%s: msix_vector_first_id = %d\n", prefix, 1770 caps->msix_vector_first_id); 1771 break; 1772 case ICE_AQC_CAPS_FD: 1773 if (dev_p) { 1774 dev_p->num_flow_director_fltr = number; 1775 ice_debug(hw, ICE_DBG_INIT, 1776 "%s: num_flow_director_fltr = %d\n", 1777 prefix, 1778 dev_p->num_flow_director_fltr); 1779 } 1780 if (func_p) { 1781 u32 reg_val, val; 1782 1783 reg_val = rd32(hw, GLQF_FD_SIZE); 1784 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 1785 GLQF_FD_SIZE_FD_GSIZE_S; 1786 func_p->fd_fltr_guar = 1787 ice_get_num_per_func(hw, val); 1788 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 1789 GLQF_FD_SIZE_FD_BSIZE_S; 1790 func_p->fd_fltr_best_effort = val; 1791 ice_debug(hw, ICE_DBG_INIT, 1792 "%s: fd_fltr_guar = %d\n", 1793 prefix, func_p->fd_fltr_guar); 1794 ice_debug(hw, ICE_DBG_INIT, 1795 "%s: fd_fltr_best_effort = %d\n", 1796 prefix, func_p->fd_fltr_best_effort); 1797 } 1798 break; 1799 case ICE_AQC_CAPS_MAX_MTU: 1800 caps->max_mtu = number; 1801 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 1802 prefix, caps->max_mtu); 1803 break; 1804 default: 1805 ice_debug(hw, ICE_DBG_INIT, 1806 "%s: unknown capability[%d]: 0x%x\n", prefix, 1807 i, cap); 1808 break; 1809 } 1810 } 1811 1812 /* Re-calculate capabilities that are dependent on the number of 1813 * physical ports; i.e. some features are not supported or function 1814 * differently on devices with more than 4 ports. 1815 */ 1816 if (hw->dev_caps.num_funcs > 4) { 1817 /* Max 4 TCs per port */ 1818 caps->maxtc = 4; 1819 ice_debug(hw, ICE_DBG_INIT, 1820 "%s: maxtc = %d (based on #ports)\n", prefix, 1821 caps->maxtc); 1822 } 1823 } 1824 1825 /** 1826 * ice_aq_discover_caps - query function/device capabilities 1827 * @hw: pointer to the HW struct 1828 * @buf: a virtual buffer to hold the capabilities 1829 * @buf_size: Size of the virtual buffer 1830 * @cap_count: cap count needed if AQ err==ENOMEM 1831 * @opc: capabilities type to discover - pass in the command opcode 1832 * @cd: pointer to command details structure or NULL 1833 * 1834 * Get the function(0x000a)/device(0x000b) capabilities description from 1835 * the firmware. 1836 */ 1837 static enum ice_status 1838 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 1839 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1840 { 1841 struct ice_aqc_list_caps *cmd; 1842 struct ice_aq_desc desc; 1843 enum ice_status status; 1844 1845 cmd = &desc.params.get_cap; 1846 1847 if (opc != ice_aqc_opc_list_func_caps && 1848 opc != ice_aqc_opc_list_dev_caps) 1849 return ICE_ERR_PARAM; 1850 1851 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1852 1853 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1854 if (!status) 1855 ice_parse_caps(hw, buf, le32_to_cpu(cmd->count), opc); 1856 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM) 1857 *cap_count = le32_to_cpu(cmd->count); 1858 return status; 1859 } 1860 1861 /** 1862 * ice_discover_caps - get info about the HW 1863 * @hw: pointer to the hardware structure 1864 * @opc: capabilities type to discover - pass in the command opcode 1865 */ 1866 static enum ice_status 1867 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc) 1868 { 1869 enum ice_status status; 1870 u32 cap_count; 1871 u16 cbuf_len; 1872 u8 retries; 1873 1874 /* The driver doesn't know how many capabilities the device will return 1875 * so the buffer size required isn't known ahead of time. The driver 1876 * starts with cbuf_len and if this turns out to be insufficient, the 1877 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs. 1878 * The driver then allocates the buffer based on the count and retries 1879 * the operation. So it follows that the retry count is 2. 1880 */ 1881 #define ICE_GET_CAP_BUF_COUNT 40 1882 #define ICE_GET_CAP_RETRY_COUNT 2 1883 1884 cap_count = ICE_GET_CAP_BUF_COUNT; 1885 retries = ICE_GET_CAP_RETRY_COUNT; 1886 1887 do { 1888 void *cbuf; 1889 1890 cbuf_len = (u16)(cap_count * 1891 sizeof(struct ice_aqc_list_caps_elem)); 1892 cbuf = devm_kzalloc(ice_hw_to_dev(hw), cbuf_len, GFP_KERNEL); 1893 if (!cbuf) 1894 return ICE_ERR_NO_MEMORY; 1895 1896 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count, 1897 opc, NULL); 1898 devm_kfree(ice_hw_to_dev(hw), cbuf); 1899 1900 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM) 1901 break; 1902 1903 /* If ENOMEM is returned, try again with bigger buffer */ 1904 } while (--retries); 1905 1906 return status; 1907 } 1908 1909 /** 1910 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 1911 * @hw: pointer to the hardware structure 1912 */ 1913 void ice_set_safe_mode_caps(struct ice_hw *hw) 1914 { 1915 struct ice_hw_func_caps *func_caps = &hw->func_caps; 1916 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 1917 u32 valid_func, rxq_first_id, txq_first_id; 1918 u32 msix_vector_first_id, max_mtu; 1919 u32 num_funcs; 1920 1921 /* cache some func_caps values that should be restored after memset */ 1922 valid_func = func_caps->common_cap.valid_functions; 1923 txq_first_id = func_caps->common_cap.txq_first_id; 1924 rxq_first_id = func_caps->common_cap.rxq_first_id; 1925 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id; 1926 max_mtu = func_caps->common_cap.max_mtu; 1927 1928 /* unset func capabilities */ 1929 memset(func_caps, 0, sizeof(*func_caps)); 1930 1931 /* restore cached values */ 1932 func_caps->common_cap.valid_functions = valid_func; 1933 func_caps->common_cap.txq_first_id = txq_first_id; 1934 func_caps->common_cap.rxq_first_id = rxq_first_id; 1935 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id; 1936 func_caps->common_cap.max_mtu = max_mtu; 1937 1938 /* one Tx and one Rx queue in safe mode */ 1939 func_caps->common_cap.num_rxq = 1; 1940 func_caps->common_cap.num_txq = 1; 1941 1942 /* two MSIX vectors, one for traffic and one for misc causes */ 1943 func_caps->common_cap.num_msix_vectors = 2; 1944 func_caps->guar_num_vsi = 1; 1945 1946 /* cache some dev_caps values that should be restored after memset */ 1947 valid_func = dev_caps->common_cap.valid_functions; 1948 txq_first_id = dev_caps->common_cap.txq_first_id; 1949 rxq_first_id = dev_caps->common_cap.rxq_first_id; 1950 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id; 1951 max_mtu = dev_caps->common_cap.max_mtu; 1952 num_funcs = dev_caps->num_funcs; 1953 1954 /* unset dev capabilities */ 1955 memset(dev_caps, 0, sizeof(*dev_caps)); 1956 1957 /* restore cached values */ 1958 dev_caps->common_cap.valid_functions = valid_func; 1959 dev_caps->common_cap.txq_first_id = txq_first_id; 1960 dev_caps->common_cap.rxq_first_id = rxq_first_id; 1961 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id; 1962 dev_caps->common_cap.max_mtu = max_mtu; 1963 dev_caps->num_funcs = num_funcs; 1964 1965 /* one Tx and one Rx queue per function in safe mode */ 1966 dev_caps->common_cap.num_rxq = num_funcs; 1967 dev_caps->common_cap.num_txq = num_funcs; 1968 1969 /* two MSIX vectors per function */ 1970 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 1971 } 1972 1973 /** 1974 * ice_get_caps - get info about the HW 1975 * @hw: pointer to the hardware structure 1976 */ 1977 enum ice_status ice_get_caps(struct ice_hw *hw) 1978 { 1979 enum ice_status status; 1980 1981 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps); 1982 if (!status) 1983 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps); 1984 1985 return status; 1986 } 1987 1988 /** 1989 * ice_aq_manage_mac_write - manage MAC address write command 1990 * @hw: pointer to the HW struct 1991 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 1992 * @flags: flags to control write behavior 1993 * @cd: pointer to command details structure or NULL 1994 * 1995 * This function is used to write MAC address to the NVM (0x0108). 1996 */ 1997 enum ice_status 1998 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 1999 struct ice_sq_cd *cd) 2000 { 2001 struct ice_aqc_manage_mac_write *cmd; 2002 struct ice_aq_desc desc; 2003 2004 cmd = &desc.params.mac_write; 2005 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2006 2007 cmd->flags = flags; 2008 ether_addr_copy(cmd->mac_addr, mac_addr); 2009 2010 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2011 } 2012 2013 /** 2014 * ice_aq_clear_pxe_mode 2015 * @hw: pointer to the HW struct 2016 * 2017 * Tell the firmware that the driver is taking over from PXE (0x0110). 2018 */ 2019 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2020 { 2021 struct ice_aq_desc desc; 2022 2023 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2024 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2025 2026 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2027 } 2028 2029 /** 2030 * ice_clear_pxe_mode - clear pxe operations mode 2031 * @hw: pointer to the HW struct 2032 * 2033 * Make sure all PXE mode settings are cleared, including things 2034 * like descriptor fetch/write-back mode. 2035 */ 2036 void ice_clear_pxe_mode(struct ice_hw *hw) 2037 { 2038 if (ice_check_sq_alive(hw, &hw->adminq)) 2039 ice_aq_clear_pxe_mode(hw); 2040 } 2041 2042 /** 2043 * ice_get_link_speed_based_on_phy_type - returns link speed 2044 * @phy_type_low: lower part of phy_type 2045 * @phy_type_high: higher part of phy_type 2046 * 2047 * This helper function will convert an entry in PHY type structure 2048 * [phy_type_low, phy_type_high] to its corresponding link speed. 2049 * Note: In the structure of [phy_type_low, phy_type_high], there should 2050 * be one bit set, as this function will convert one PHY type to its 2051 * speed. 2052 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2053 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2054 */ 2055 static u16 2056 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2057 { 2058 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2059 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2060 2061 switch (phy_type_low) { 2062 case ICE_PHY_TYPE_LOW_100BASE_TX: 2063 case ICE_PHY_TYPE_LOW_100M_SGMII: 2064 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2065 break; 2066 case ICE_PHY_TYPE_LOW_1000BASE_T: 2067 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2068 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2069 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2070 case ICE_PHY_TYPE_LOW_1G_SGMII: 2071 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2072 break; 2073 case ICE_PHY_TYPE_LOW_2500BASE_T: 2074 case ICE_PHY_TYPE_LOW_2500BASE_X: 2075 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2076 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2077 break; 2078 case ICE_PHY_TYPE_LOW_5GBASE_T: 2079 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2080 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2081 break; 2082 case ICE_PHY_TYPE_LOW_10GBASE_T: 2083 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2084 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2085 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2086 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2087 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2088 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2089 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2090 break; 2091 case ICE_PHY_TYPE_LOW_25GBASE_T: 2092 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2093 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2094 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2095 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2096 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2097 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2098 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2099 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2100 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2101 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2102 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2103 break; 2104 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2105 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2106 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2107 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2108 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2109 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2110 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2111 break; 2112 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2113 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2114 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2115 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2116 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2117 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2118 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2119 case ICE_PHY_TYPE_LOW_50G_AUI2: 2120 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2121 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2122 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2123 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2124 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2125 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2126 case ICE_PHY_TYPE_LOW_50G_AUI1: 2127 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2128 break; 2129 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2130 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2131 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2132 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2133 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2134 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2135 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2136 case ICE_PHY_TYPE_LOW_100G_AUI4: 2137 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2138 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2139 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2140 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2141 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2142 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2143 break; 2144 default: 2145 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2146 break; 2147 } 2148 2149 switch (phy_type_high) { 2150 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2151 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2152 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2153 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2154 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2155 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2156 break; 2157 default: 2158 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2159 break; 2160 } 2161 2162 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2163 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2164 return ICE_AQ_LINK_SPEED_UNKNOWN; 2165 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2166 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2167 return ICE_AQ_LINK_SPEED_UNKNOWN; 2168 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2169 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2170 return speed_phy_type_low; 2171 else 2172 return speed_phy_type_high; 2173 } 2174 2175 /** 2176 * ice_update_phy_type 2177 * @phy_type_low: pointer to the lower part of phy_type 2178 * @phy_type_high: pointer to the higher part of phy_type 2179 * @link_speeds_bitmap: targeted link speeds bitmap 2180 * 2181 * Note: For the link_speeds_bitmap structure, you can check it at 2182 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2183 * link_speeds_bitmap include multiple speeds. 2184 * 2185 * Each entry in this [phy_type_low, phy_type_high] structure will 2186 * present a certain link speed. This helper function will turn on bits 2187 * in [phy_type_low, phy_type_high] structure based on the value of 2188 * link_speeds_bitmap input parameter. 2189 */ 2190 void 2191 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2192 u16 link_speeds_bitmap) 2193 { 2194 u64 pt_high; 2195 u64 pt_low; 2196 int index; 2197 u16 speed; 2198 2199 /* We first check with low part of phy_type */ 2200 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2201 pt_low = BIT_ULL(index); 2202 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2203 2204 if (link_speeds_bitmap & speed) 2205 *phy_type_low |= BIT_ULL(index); 2206 } 2207 2208 /* We then check with high part of phy_type */ 2209 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2210 pt_high = BIT_ULL(index); 2211 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2212 2213 if (link_speeds_bitmap & speed) 2214 *phy_type_high |= BIT_ULL(index); 2215 } 2216 } 2217 2218 /** 2219 * ice_aq_set_phy_cfg 2220 * @hw: pointer to the HW struct 2221 * @lport: logical port number 2222 * @cfg: structure with PHY configuration data to be set 2223 * @cd: pointer to command details structure or NULL 2224 * 2225 * Set the various PHY configuration parameters supported on the Port. 2226 * One or more of the Set PHY config parameters may be ignored in an MFP 2227 * mode as the PF may not have the privilege to set some of the PHY Config 2228 * parameters. This status will be indicated by the command response (0x0601). 2229 */ 2230 enum ice_status 2231 ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport, 2232 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2233 { 2234 struct ice_aq_desc desc; 2235 enum ice_status status; 2236 2237 if (!cfg) 2238 return ICE_ERR_PARAM; 2239 2240 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2241 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2242 ice_debug(hw, ICE_DBG_PHY, 2243 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2244 cfg->caps); 2245 2246 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2247 } 2248 2249 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2250 desc.params.set_phy.lport_num = lport; 2251 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2252 2253 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n", 2254 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 2255 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n", 2256 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 2257 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps); 2258 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n", 2259 cfg->low_power_ctrl); 2260 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap); 2261 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value); 2262 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt); 2263 2264 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2265 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 2266 status = 0; 2267 2268 return status; 2269 } 2270 2271 /** 2272 * ice_update_link_info - update status of the HW network link 2273 * @pi: port info structure of the interested logical port 2274 */ 2275 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2276 { 2277 struct ice_link_status *li; 2278 enum ice_status status; 2279 2280 if (!pi) 2281 return ICE_ERR_PARAM; 2282 2283 li = &pi->phy.link_info; 2284 2285 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2286 if (status) 2287 return status; 2288 2289 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2290 struct ice_aqc_get_phy_caps_data *pcaps; 2291 struct ice_hw *hw; 2292 2293 hw = pi->hw; 2294 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 2295 GFP_KERNEL); 2296 if (!pcaps) 2297 return ICE_ERR_NO_MEMORY; 2298 2299 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, 2300 pcaps, NULL); 2301 if (!status) 2302 memcpy(li->module_type, &pcaps->module_type, 2303 sizeof(li->module_type)); 2304 2305 devm_kfree(ice_hw_to_dev(hw), pcaps); 2306 } 2307 2308 return status; 2309 } 2310 2311 /** 2312 * ice_set_fc 2313 * @pi: port information structure 2314 * @aq_failures: pointer to status code, specific to ice_set_fc routine 2315 * @ena_auto_link_update: enable automatic link update 2316 * 2317 * Set the requested flow control mode. 2318 */ 2319 enum ice_status 2320 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2321 { 2322 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2323 struct ice_aqc_get_phy_caps_data *pcaps; 2324 enum ice_status status; 2325 u8 pause_mask = 0x0; 2326 struct ice_hw *hw; 2327 2328 if (!pi) 2329 return ICE_ERR_PARAM; 2330 hw = pi->hw; 2331 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE; 2332 2333 switch (pi->fc.req_mode) { 2334 case ICE_FC_FULL: 2335 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2336 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2337 break; 2338 case ICE_FC_RX_PAUSE: 2339 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2340 break; 2341 case ICE_FC_TX_PAUSE: 2342 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2343 break; 2344 default: 2345 break; 2346 } 2347 2348 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 2349 if (!pcaps) 2350 return ICE_ERR_NO_MEMORY; 2351 2352 /* Get the current PHY config */ 2353 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 2354 NULL); 2355 if (status) { 2356 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2357 goto out; 2358 } 2359 2360 /* clear the old pause settings */ 2361 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2362 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2363 2364 /* set the new capabilities */ 2365 cfg.caps |= pause_mask; 2366 2367 /* If the capabilities have changed, then set the new config */ 2368 if (cfg.caps != pcaps->caps) { 2369 int retry_count, retry_max = 10; 2370 2371 /* Auto restart link so settings take effect */ 2372 if (ena_auto_link_update) 2373 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2374 /* Copy over all the old settings */ 2375 cfg.phy_type_high = pcaps->phy_type_high; 2376 cfg.phy_type_low = pcaps->phy_type_low; 2377 cfg.low_power_ctrl = pcaps->low_power_ctrl; 2378 cfg.eee_cap = pcaps->eee_cap; 2379 cfg.eeer_value = pcaps->eeer_value; 2380 cfg.link_fec_opt = pcaps->link_fec_options; 2381 2382 status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL); 2383 if (status) { 2384 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 2385 goto out; 2386 } 2387 2388 /* Update the link info 2389 * It sometimes takes a really long time for link to 2390 * come back from the atomic reset. Thus, we wait a 2391 * little bit. 2392 */ 2393 for (retry_count = 0; retry_count < retry_max; retry_count++) { 2394 status = ice_update_link_info(pi); 2395 2396 if (!status) 2397 break; 2398 2399 mdelay(100); 2400 } 2401 2402 if (status) 2403 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 2404 } 2405 2406 out: 2407 devm_kfree(ice_hw_to_dev(hw), pcaps); 2408 return status; 2409 } 2410 2411 /** 2412 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 2413 * @caps: PHY ability structure to copy date from 2414 * @cfg: PHY configuration structure to copy data to 2415 * 2416 * Helper function to copy AQC PHY get ability data to PHY set configuration 2417 * data structure 2418 */ 2419 void 2420 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps, 2421 struct ice_aqc_set_phy_cfg_data *cfg) 2422 { 2423 if (!caps || !cfg) 2424 return; 2425 2426 cfg->phy_type_low = caps->phy_type_low; 2427 cfg->phy_type_high = caps->phy_type_high; 2428 cfg->caps = caps->caps; 2429 cfg->low_power_ctrl = caps->low_power_ctrl; 2430 cfg->eee_cap = caps->eee_cap; 2431 cfg->eeer_value = caps->eeer_value; 2432 cfg->link_fec_opt = caps->link_fec_options; 2433 } 2434 2435 /** 2436 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 2437 * @cfg: PHY configuration data to set FEC mode 2438 * @fec: FEC mode to configure 2439 * 2440 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC 2441 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps 2442 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling. 2443 */ 2444 void 2445 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec) 2446 { 2447 switch (fec) { 2448 case ICE_FEC_BASER: 2449 /* Clear RS bits, and AND BASE-R ability 2450 * bits and OR request bits. 2451 */ 2452 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2453 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 2454 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2455 ICE_AQC_PHY_FEC_25G_KR_REQ; 2456 break; 2457 case ICE_FEC_RS: 2458 /* Clear BASE-R bits, and AND RS ability 2459 * bits and OR request bits. 2460 */ 2461 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 2462 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2463 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 2464 break; 2465 case ICE_FEC_NONE: 2466 /* Clear all FEC option bits. */ 2467 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 2468 break; 2469 case ICE_FEC_AUTO: 2470 /* AND auto FEC bit, and all caps bits. */ 2471 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 2472 break; 2473 } 2474 } 2475 2476 /** 2477 * ice_get_link_status - get status of the HW network link 2478 * @pi: port information structure 2479 * @link_up: pointer to bool (true/false = linkup/linkdown) 2480 * 2481 * Variable link_up is true if link is up, false if link is down. 2482 * The variable link_up is invalid if status is non zero. As a 2483 * result of this call, link status reporting becomes enabled 2484 */ 2485 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 2486 { 2487 struct ice_phy_info *phy_info; 2488 enum ice_status status = 0; 2489 2490 if (!pi || !link_up) 2491 return ICE_ERR_PARAM; 2492 2493 phy_info = &pi->phy; 2494 2495 if (phy_info->get_link_info) { 2496 status = ice_update_link_info(pi); 2497 2498 if (status) 2499 ice_debug(pi->hw, ICE_DBG_LINK, 2500 "get link status error, status = %d\n", 2501 status); 2502 } 2503 2504 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 2505 2506 return status; 2507 } 2508 2509 /** 2510 * ice_aq_set_link_restart_an 2511 * @pi: pointer to the port information structure 2512 * @ena_link: if true: enable link, if false: disable link 2513 * @cd: pointer to command details structure or NULL 2514 * 2515 * Sets up the link and restarts the Auto-Negotiation over the link. 2516 */ 2517 enum ice_status 2518 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 2519 struct ice_sq_cd *cd) 2520 { 2521 struct ice_aqc_restart_an *cmd; 2522 struct ice_aq_desc desc; 2523 2524 cmd = &desc.params.restart_an; 2525 2526 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 2527 2528 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 2529 cmd->lport_num = pi->lport; 2530 if (ena_link) 2531 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 2532 else 2533 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 2534 2535 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 2536 } 2537 2538 /** 2539 * ice_aq_set_event_mask 2540 * @hw: pointer to the HW struct 2541 * @port_num: port number of the physical function 2542 * @mask: event mask to be set 2543 * @cd: pointer to command details structure or NULL 2544 * 2545 * Set event mask (0x0613) 2546 */ 2547 enum ice_status 2548 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 2549 struct ice_sq_cd *cd) 2550 { 2551 struct ice_aqc_set_event_mask *cmd; 2552 struct ice_aq_desc desc; 2553 2554 cmd = &desc.params.set_event_mask; 2555 2556 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 2557 2558 cmd->lport_num = port_num; 2559 2560 cmd->event_mask = cpu_to_le16(mask); 2561 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2562 } 2563 2564 /** 2565 * ice_aq_set_mac_loopback 2566 * @hw: pointer to the HW struct 2567 * @ena_lpbk: Enable or Disable loopback 2568 * @cd: pointer to command details structure or NULL 2569 * 2570 * Enable/disable loopback on a given port 2571 */ 2572 enum ice_status 2573 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 2574 { 2575 struct ice_aqc_set_mac_lb *cmd; 2576 struct ice_aq_desc desc; 2577 2578 cmd = &desc.params.set_mac_lb; 2579 2580 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 2581 if (ena_lpbk) 2582 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 2583 2584 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2585 } 2586 2587 /** 2588 * ice_aq_set_port_id_led 2589 * @pi: pointer to the port information 2590 * @is_orig_mode: is this LED set to original mode (by the net-list) 2591 * @cd: pointer to command details structure or NULL 2592 * 2593 * Set LED value for the given port (0x06e9) 2594 */ 2595 enum ice_status 2596 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 2597 struct ice_sq_cd *cd) 2598 { 2599 struct ice_aqc_set_port_id_led *cmd; 2600 struct ice_hw *hw = pi->hw; 2601 struct ice_aq_desc desc; 2602 2603 cmd = &desc.params.set_port_id_led; 2604 2605 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 2606 2607 if (is_orig_mode) 2608 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 2609 else 2610 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 2611 2612 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2613 } 2614 2615 /** 2616 * ice_aq_sff_eeprom 2617 * @hw: pointer to the HW struct 2618 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 2619 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 2620 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 2621 * @page: QSFP page 2622 * @set_page: set or ignore the page 2623 * @data: pointer to data buffer to be read/written to the I2C device. 2624 * @length: 1-16 for read, 1 for write. 2625 * @write: 0 read, 1 for write. 2626 * @cd: pointer to command details structure or NULL 2627 * 2628 * Read/Write SFF EEPROM (0x06EE) 2629 */ 2630 enum ice_status 2631 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 2632 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 2633 bool write, struct ice_sq_cd *cd) 2634 { 2635 struct ice_aqc_sff_eeprom *cmd; 2636 struct ice_aq_desc desc; 2637 enum ice_status status; 2638 2639 if (!data || (mem_addr & 0xff00)) 2640 return ICE_ERR_PARAM; 2641 2642 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 2643 cmd = &desc.params.read_write_sff_param; 2644 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF); 2645 cmd->lport_num = (u8)(lport & 0xff); 2646 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 2647 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 2648 ICE_AQC_SFF_I2CBUS_7BIT_M) | 2649 ((set_page << 2650 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 2651 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 2652 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 2653 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 2654 if (write) 2655 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 2656 2657 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 2658 return status; 2659 } 2660 2661 /** 2662 * __ice_aq_get_set_rss_lut 2663 * @hw: pointer to the hardware structure 2664 * @vsi_id: VSI FW index 2665 * @lut_type: LUT table type 2666 * @lut: pointer to the LUT buffer provided by the caller 2667 * @lut_size: size of the LUT buffer 2668 * @glob_lut_idx: global LUT index 2669 * @set: set true to set the table, false to get the table 2670 * 2671 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 2672 */ 2673 static enum ice_status 2674 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 2675 u16 lut_size, u8 glob_lut_idx, bool set) 2676 { 2677 struct ice_aqc_get_set_rss_lut *cmd_resp; 2678 struct ice_aq_desc desc; 2679 enum ice_status status; 2680 u16 flags = 0; 2681 2682 cmd_resp = &desc.params.get_set_rss_lut; 2683 2684 if (set) { 2685 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 2686 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2687 } else { 2688 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 2689 } 2690 2691 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 2692 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 2693 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 2694 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 2695 2696 switch (lut_type) { 2697 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 2698 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 2699 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 2700 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 2701 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 2702 break; 2703 default: 2704 status = ICE_ERR_PARAM; 2705 goto ice_aq_get_set_rss_lut_exit; 2706 } 2707 2708 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 2709 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 2710 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 2711 2712 if (!set) 2713 goto ice_aq_get_set_rss_lut_send; 2714 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 2715 if (!set) 2716 goto ice_aq_get_set_rss_lut_send; 2717 } else { 2718 goto ice_aq_get_set_rss_lut_send; 2719 } 2720 2721 /* LUT size is only valid for Global and PF table types */ 2722 switch (lut_size) { 2723 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 2724 break; 2725 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 2726 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 2727 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 2728 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 2729 break; 2730 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 2731 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 2732 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 2733 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 2734 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 2735 break; 2736 } 2737 fallthrough; 2738 default: 2739 status = ICE_ERR_PARAM; 2740 goto ice_aq_get_set_rss_lut_exit; 2741 } 2742 2743 ice_aq_get_set_rss_lut_send: 2744 cmd_resp->flags = cpu_to_le16(flags); 2745 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 2746 2747 ice_aq_get_set_rss_lut_exit: 2748 return status; 2749 } 2750 2751 /** 2752 * ice_aq_get_rss_lut 2753 * @hw: pointer to the hardware structure 2754 * @vsi_handle: software VSI handle 2755 * @lut_type: LUT table type 2756 * @lut: pointer to the LUT buffer provided by the caller 2757 * @lut_size: size of the LUT buffer 2758 * 2759 * get the RSS lookup table, PF or VSI type 2760 */ 2761 enum ice_status 2762 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 2763 u8 *lut, u16 lut_size) 2764 { 2765 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 2766 return ICE_ERR_PARAM; 2767 2768 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2769 lut_type, lut, lut_size, 0, false); 2770 } 2771 2772 /** 2773 * ice_aq_set_rss_lut 2774 * @hw: pointer to the hardware structure 2775 * @vsi_handle: software VSI handle 2776 * @lut_type: LUT table type 2777 * @lut: pointer to the LUT buffer provided by the caller 2778 * @lut_size: size of the LUT buffer 2779 * 2780 * set the RSS lookup table, PF or VSI type 2781 */ 2782 enum ice_status 2783 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 2784 u8 *lut, u16 lut_size) 2785 { 2786 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 2787 return ICE_ERR_PARAM; 2788 2789 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2790 lut_type, lut, lut_size, 0, true); 2791 } 2792 2793 /** 2794 * __ice_aq_get_set_rss_key 2795 * @hw: pointer to the HW struct 2796 * @vsi_id: VSI FW index 2797 * @key: pointer to key info struct 2798 * @set: set true to set the key, false to get the key 2799 * 2800 * get (0x0B04) or set (0x0B02) the RSS key per VSI 2801 */ 2802 static enum 2803 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 2804 struct ice_aqc_get_set_rss_keys *key, 2805 bool set) 2806 { 2807 struct ice_aqc_get_set_rss_key *cmd_resp; 2808 u16 key_size = sizeof(*key); 2809 struct ice_aq_desc desc; 2810 2811 cmd_resp = &desc.params.get_set_rss_key; 2812 2813 if (set) { 2814 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 2815 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2816 } else { 2817 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 2818 } 2819 2820 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 2821 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 2822 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 2823 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 2824 2825 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 2826 } 2827 2828 /** 2829 * ice_aq_get_rss_key 2830 * @hw: pointer to the HW struct 2831 * @vsi_handle: software VSI handle 2832 * @key: pointer to key info struct 2833 * 2834 * get the RSS key per VSI 2835 */ 2836 enum ice_status 2837 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 2838 struct ice_aqc_get_set_rss_keys *key) 2839 { 2840 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 2841 return ICE_ERR_PARAM; 2842 2843 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2844 key, false); 2845 } 2846 2847 /** 2848 * ice_aq_set_rss_key 2849 * @hw: pointer to the HW struct 2850 * @vsi_handle: software VSI handle 2851 * @keys: pointer to key info struct 2852 * 2853 * set the RSS key per VSI 2854 */ 2855 enum ice_status 2856 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 2857 struct ice_aqc_get_set_rss_keys *keys) 2858 { 2859 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 2860 return ICE_ERR_PARAM; 2861 2862 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2863 keys, true); 2864 } 2865 2866 /** 2867 * ice_aq_add_lan_txq 2868 * @hw: pointer to the hardware structure 2869 * @num_qgrps: Number of added queue groups 2870 * @qg_list: list of queue groups to be added 2871 * @buf_size: size of buffer for indirect command 2872 * @cd: pointer to command details structure or NULL 2873 * 2874 * Add Tx LAN queue (0x0C30) 2875 * 2876 * NOTE: 2877 * Prior to calling add Tx LAN queue: 2878 * Initialize the following as part of the Tx queue context: 2879 * Completion queue ID if the queue uses Completion queue, Quanta profile, 2880 * Cache profile and Packet shaper profile. 2881 * 2882 * After add Tx LAN queue AQ command is completed: 2883 * Interrupts should be associated with specific queues, 2884 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 2885 * flow. 2886 */ 2887 static enum ice_status 2888 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 2889 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 2890 struct ice_sq_cd *cd) 2891 { 2892 u16 i, sum_header_size, sum_q_size = 0; 2893 struct ice_aqc_add_tx_qgrp *list; 2894 struct ice_aqc_add_txqs *cmd; 2895 struct ice_aq_desc desc; 2896 2897 cmd = &desc.params.add_txqs; 2898 2899 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 2900 2901 if (!qg_list) 2902 return ICE_ERR_PARAM; 2903 2904 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 2905 return ICE_ERR_PARAM; 2906 2907 sum_header_size = num_qgrps * 2908 (sizeof(*qg_list) - sizeof(*qg_list->txqs)); 2909 2910 list = qg_list; 2911 for (i = 0; i < num_qgrps; i++) { 2912 struct ice_aqc_add_txqs_perq *q = list->txqs; 2913 2914 sum_q_size += list->num_txqs * sizeof(*q); 2915 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs); 2916 } 2917 2918 if (buf_size != (sum_header_size + sum_q_size)) 2919 return ICE_ERR_PARAM; 2920 2921 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2922 2923 cmd->num_qgrps = num_qgrps; 2924 2925 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 2926 } 2927 2928 /** 2929 * ice_aq_dis_lan_txq 2930 * @hw: pointer to the hardware structure 2931 * @num_qgrps: number of groups in the list 2932 * @qg_list: the list of groups to disable 2933 * @buf_size: the total size of the qg_list buffer in bytes 2934 * @rst_src: if called due to reset, specifies the reset source 2935 * @vmvf_num: the relative VM or VF number that is undergoing the reset 2936 * @cd: pointer to command details structure or NULL 2937 * 2938 * Disable LAN Tx queue (0x0C31) 2939 */ 2940 static enum ice_status 2941 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 2942 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 2943 enum ice_disq_rst_src rst_src, u16 vmvf_num, 2944 struct ice_sq_cd *cd) 2945 { 2946 struct ice_aqc_dis_txqs *cmd; 2947 struct ice_aq_desc desc; 2948 enum ice_status status; 2949 u16 i, sz = 0; 2950 2951 cmd = &desc.params.dis_txqs; 2952 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 2953 2954 /* qg_list can be NULL only in VM/VF reset flow */ 2955 if (!qg_list && !rst_src) 2956 return ICE_ERR_PARAM; 2957 2958 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 2959 return ICE_ERR_PARAM; 2960 2961 cmd->num_entries = num_qgrps; 2962 2963 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 2964 ICE_AQC_Q_DIS_TIMEOUT_M); 2965 2966 switch (rst_src) { 2967 case ICE_VM_RESET: 2968 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 2969 cmd->vmvf_and_timeout |= 2970 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 2971 break; 2972 case ICE_VF_RESET: 2973 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 2974 /* In this case, FW expects vmvf_num to be absolute VF ID */ 2975 cmd->vmvf_and_timeout |= 2976 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 2977 ICE_AQC_Q_DIS_VMVF_NUM_M); 2978 break; 2979 case ICE_NO_RESET: 2980 default: 2981 break; 2982 } 2983 2984 /* flush pipe on time out */ 2985 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 2986 /* If no queue group info, we are in a reset flow. Issue the AQ */ 2987 if (!qg_list) 2988 goto do_aq; 2989 2990 /* set RD bit to indicate that command buffer is provided by the driver 2991 * and it needs to be read by the firmware 2992 */ 2993 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2994 2995 for (i = 0; i < num_qgrps; ++i) { 2996 /* Calculate the size taken up by the queue IDs in this group */ 2997 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id); 2998 2999 /* Add the size of the group header */ 3000 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id); 3001 3002 /* If the num of queues is even, add 2 bytes of padding */ 3003 if ((qg_list[i].num_qs % 2) == 0) 3004 sz += 2; 3005 } 3006 3007 if (buf_size != sz) 3008 return ICE_ERR_PARAM; 3009 3010 do_aq: 3011 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3012 if (status) { 3013 if (!qg_list) 3014 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 3015 vmvf_num, hw->adminq.sq_last_status); 3016 else 3017 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 3018 le16_to_cpu(qg_list[0].q_id[0]), 3019 hw->adminq.sq_last_status); 3020 } 3021 return status; 3022 } 3023 3024 /* End of FW Admin Queue command wrappers */ 3025 3026 /** 3027 * ice_write_byte - write a byte to a packed context structure 3028 * @src_ctx: the context structure to read from 3029 * @dest_ctx: the context to be written to 3030 * @ce_info: a description of the struct to be filled 3031 */ 3032 static void 3033 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3034 { 3035 u8 src_byte, dest_byte, mask; 3036 u8 *from, *dest; 3037 u16 shift_width; 3038 3039 /* copy from the next struct field */ 3040 from = src_ctx + ce_info->offset; 3041 3042 /* prepare the bits and mask */ 3043 shift_width = ce_info->lsb % 8; 3044 mask = (u8)(BIT(ce_info->width) - 1); 3045 3046 src_byte = *from; 3047 src_byte &= mask; 3048 3049 /* shift to correct alignment */ 3050 mask <<= shift_width; 3051 src_byte <<= shift_width; 3052 3053 /* get the current bits from the target bit string */ 3054 dest = dest_ctx + (ce_info->lsb / 8); 3055 3056 memcpy(&dest_byte, dest, sizeof(dest_byte)); 3057 3058 dest_byte &= ~mask; /* get the bits not changing */ 3059 dest_byte |= src_byte; /* add in the new bits */ 3060 3061 /* put it all back */ 3062 memcpy(dest, &dest_byte, sizeof(dest_byte)); 3063 } 3064 3065 /** 3066 * ice_write_word - write a word to a packed context structure 3067 * @src_ctx: the context structure to read from 3068 * @dest_ctx: the context to be written to 3069 * @ce_info: a description of the struct to be filled 3070 */ 3071 static void 3072 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3073 { 3074 u16 src_word, mask; 3075 __le16 dest_word; 3076 u8 *from, *dest; 3077 u16 shift_width; 3078 3079 /* copy from the next struct field */ 3080 from = src_ctx + ce_info->offset; 3081 3082 /* prepare the bits and mask */ 3083 shift_width = ce_info->lsb % 8; 3084 mask = BIT(ce_info->width) - 1; 3085 3086 /* don't swizzle the bits until after the mask because the mask bits 3087 * will be in a different bit position on big endian machines 3088 */ 3089 src_word = *(u16 *)from; 3090 src_word &= mask; 3091 3092 /* shift to correct alignment */ 3093 mask <<= shift_width; 3094 src_word <<= shift_width; 3095 3096 /* get the current bits from the target bit string */ 3097 dest = dest_ctx + (ce_info->lsb / 8); 3098 3099 memcpy(&dest_word, dest, sizeof(dest_word)); 3100 3101 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 3102 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 3103 3104 /* put it all back */ 3105 memcpy(dest, &dest_word, sizeof(dest_word)); 3106 } 3107 3108 /** 3109 * ice_write_dword - write a dword to a packed context structure 3110 * @src_ctx: the context structure to read from 3111 * @dest_ctx: the context to be written to 3112 * @ce_info: a description of the struct to be filled 3113 */ 3114 static void 3115 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3116 { 3117 u32 src_dword, mask; 3118 __le32 dest_dword; 3119 u8 *from, *dest; 3120 u16 shift_width; 3121 3122 /* copy from the next struct field */ 3123 from = src_ctx + ce_info->offset; 3124 3125 /* prepare the bits and mask */ 3126 shift_width = ce_info->lsb % 8; 3127 3128 /* if the field width is exactly 32 on an x86 machine, then the shift 3129 * operation will not work because the SHL instructions count is masked 3130 * to 5 bits so the shift will do nothing 3131 */ 3132 if (ce_info->width < 32) 3133 mask = BIT(ce_info->width) - 1; 3134 else 3135 mask = (u32)~0; 3136 3137 /* don't swizzle the bits until after the mask because the mask bits 3138 * will be in a different bit position on big endian machines 3139 */ 3140 src_dword = *(u32 *)from; 3141 src_dword &= mask; 3142 3143 /* shift to correct alignment */ 3144 mask <<= shift_width; 3145 src_dword <<= shift_width; 3146 3147 /* get the current bits from the target bit string */ 3148 dest = dest_ctx + (ce_info->lsb / 8); 3149 3150 memcpy(&dest_dword, dest, sizeof(dest_dword)); 3151 3152 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 3153 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 3154 3155 /* put it all back */ 3156 memcpy(dest, &dest_dword, sizeof(dest_dword)); 3157 } 3158 3159 /** 3160 * ice_write_qword - write a qword to a packed context structure 3161 * @src_ctx: the context structure to read from 3162 * @dest_ctx: the context to be written to 3163 * @ce_info: a description of the struct to be filled 3164 */ 3165 static void 3166 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3167 { 3168 u64 src_qword, mask; 3169 __le64 dest_qword; 3170 u8 *from, *dest; 3171 u16 shift_width; 3172 3173 /* copy from the next struct field */ 3174 from = src_ctx + ce_info->offset; 3175 3176 /* prepare the bits and mask */ 3177 shift_width = ce_info->lsb % 8; 3178 3179 /* if the field width is exactly 64 on an x86 machine, then the shift 3180 * operation will not work because the SHL instructions count is masked 3181 * to 6 bits so the shift will do nothing 3182 */ 3183 if (ce_info->width < 64) 3184 mask = BIT_ULL(ce_info->width) - 1; 3185 else 3186 mask = (u64)~0; 3187 3188 /* don't swizzle the bits until after the mask because the mask bits 3189 * will be in a different bit position on big endian machines 3190 */ 3191 src_qword = *(u64 *)from; 3192 src_qword &= mask; 3193 3194 /* shift to correct alignment */ 3195 mask <<= shift_width; 3196 src_qword <<= shift_width; 3197 3198 /* get the current bits from the target bit string */ 3199 dest = dest_ctx + (ce_info->lsb / 8); 3200 3201 memcpy(&dest_qword, dest, sizeof(dest_qword)); 3202 3203 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 3204 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 3205 3206 /* put it all back */ 3207 memcpy(dest, &dest_qword, sizeof(dest_qword)); 3208 } 3209 3210 /** 3211 * ice_set_ctx - set context bits in packed structure 3212 * @hw: pointer to the hardware structure 3213 * @src_ctx: pointer to a generic non-packed context structure 3214 * @dest_ctx: pointer to memory for the packed structure 3215 * @ce_info: a description of the structure to be transformed 3216 */ 3217 enum ice_status 3218 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 3219 const struct ice_ctx_ele *ce_info) 3220 { 3221 int f; 3222 3223 for (f = 0; ce_info[f].width; f++) { 3224 /* We have to deal with each element of the FW response 3225 * using the correct size so that we are correct regardless 3226 * of the endianness of the machine. 3227 */ 3228 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 3229 ice_debug(hw, ICE_DBG_QCTX, 3230 "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 3231 f, ce_info[f].width, ce_info[f].size_of); 3232 continue; 3233 } 3234 switch (ce_info[f].size_of) { 3235 case sizeof(u8): 3236 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 3237 break; 3238 case sizeof(u16): 3239 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 3240 break; 3241 case sizeof(u32): 3242 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 3243 break; 3244 case sizeof(u64): 3245 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 3246 break; 3247 default: 3248 return ICE_ERR_INVAL_SIZE; 3249 } 3250 } 3251 3252 return 0; 3253 } 3254 3255 /** 3256 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 3257 * @hw: pointer to the HW struct 3258 * @vsi_handle: software VSI handle 3259 * @tc: TC number 3260 * @q_handle: software queue handle 3261 */ 3262 struct ice_q_ctx * 3263 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 3264 { 3265 struct ice_vsi_ctx *vsi; 3266 struct ice_q_ctx *q_ctx; 3267 3268 vsi = ice_get_vsi_ctx(hw, vsi_handle); 3269 if (!vsi) 3270 return NULL; 3271 if (q_handle >= vsi->num_lan_q_entries[tc]) 3272 return NULL; 3273 if (!vsi->lan_q_ctx[tc]) 3274 return NULL; 3275 q_ctx = vsi->lan_q_ctx[tc]; 3276 return &q_ctx[q_handle]; 3277 } 3278 3279 /** 3280 * ice_ena_vsi_txq 3281 * @pi: port information structure 3282 * @vsi_handle: software VSI handle 3283 * @tc: TC number 3284 * @q_handle: software queue handle 3285 * @num_qgrps: Number of added queue groups 3286 * @buf: list of queue groups to be added 3287 * @buf_size: size of buffer for indirect command 3288 * @cd: pointer to command details structure or NULL 3289 * 3290 * This function adds one LAN queue 3291 */ 3292 enum ice_status 3293 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 3294 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 3295 struct ice_sq_cd *cd) 3296 { 3297 struct ice_aqc_txsched_elem_data node = { 0 }; 3298 struct ice_sched_node *parent; 3299 struct ice_q_ctx *q_ctx; 3300 enum ice_status status; 3301 struct ice_hw *hw; 3302 3303 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3304 return ICE_ERR_CFG; 3305 3306 if (num_qgrps > 1 || buf->num_txqs > 1) 3307 return ICE_ERR_MAX_LIMIT; 3308 3309 hw = pi->hw; 3310 3311 if (!ice_is_vsi_valid(hw, vsi_handle)) 3312 return ICE_ERR_PARAM; 3313 3314 mutex_lock(&pi->sched_lock); 3315 3316 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 3317 if (!q_ctx) { 3318 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 3319 q_handle); 3320 status = ICE_ERR_PARAM; 3321 goto ena_txq_exit; 3322 } 3323 3324 /* find a parent node */ 3325 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 3326 ICE_SCHED_NODE_OWNER_LAN); 3327 if (!parent) { 3328 status = ICE_ERR_PARAM; 3329 goto ena_txq_exit; 3330 } 3331 3332 buf->parent_teid = parent->info.node_teid; 3333 node.parent_teid = parent->info.node_teid; 3334 /* Mark that the values in the "generic" section as valid. The default 3335 * value in the "generic" section is zero. This means that : 3336 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 3337 * - 0 priority among siblings, indicated by Bit 1-3. 3338 * - WFQ, indicated by Bit 4. 3339 * - 0 Adjustment value is used in PSM credit update flow, indicated by 3340 * Bit 5-6. 3341 * - Bit 7 is reserved. 3342 * Without setting the generic section as valid in valid_sections, the 3343 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 3344 */ 3345 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC; 3346 3347 /* add the LAN queue */ 3348 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 3349 if (status) { 3350 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 3351 le16_to_cpu(buf->txqs[0].txq_id), 3352 hw->adminq.sq_last_status); 3353 goto ena_txq_exit; 3354 } 3355 3356 node.node_teid = buf->txqs[0].q_teid; 3357 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 3358 q_ctx->q_handle = q_handle; 3359 q_ctx->q_teid = le32_to_cpu(node.node_teid); 3360 3361 /* add a leaf node into scheduler tree queue layer */ 3362 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 3363 if (!status) 3364 status = ice_sched_replay_q_bw(pi, q_ctx); 3365 3366 ena_txq_exit: 3367 mutex_unlock(&pi->sched_lock); 3368 return status; 3369 } 3370 3371 /** 3372 * ice_dis_vsi_txq 3373 * @pi: port information structure 3374 * @vsi_handle: software VSI handle 3375 * @tc: TC number 3376 * @num_queues: number of queues 3377 * @q_handles: pointer to software queue handle array 3378 * @q_ids: pointer to the q_id array 3379 * @q_teids: pointer to queue node teids 3380 * @rst_src: if called due to reset, specifies the reset source 3381 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3382 * @cd: pointer to command details structure or NULL 3383 * 3384 * This function removes queues and their corresponding nodes in SW DB 3385 */ 3386 enum ice_status 3387 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 3388 u16 *q_handles, u16 *q_ids, u32 *q_teids, 3389 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3390 struct ice_sq_cd *cd) 3391 { 3392 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 3393 struct ice_aqc_dis_txq_item qg_list; 3394 struct ice_q_ctx *q_ctx; 3395 u16 i; 3396 3397 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3398 return ICE_ERR_CFG; 3399 3400 if (!num_queues) { 3401 /* if queue is disabled already yet the disable queue command 3402 * has to be sent to complete the VF reset, then call 3403 * ice_aq_dis_lan_txq without any queue information 3404 */ 3405 if (rst_src) 3406 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src, 3407 vmvf_num, NULL); 3408 return ICE_ERR_CFG; 3409 } 3410 3411 mutex_lock(&pi->sched_lock); 3412 3413 for (i = 0; i < num_queues; i++) { 3414 struct ice_sched_node *node; 3415 3416 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 3417 if (!node) 3418 continue; 3419 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]); 3420 if (!q_ctx) { 3421 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 3422 q_handles[i]); 3423 continue; 3424 } 3425 if (q_ctx->q_handle != q_handles[i]) { 3426 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 3427 q_ctx->q_handle, q_handles[i]); 3428 continue; 3429 } 3430 qg_list.parent_teid = node->info.parent_teid; 3431 qg_list.num_qs = 1; 3432 qg_list.q_id[0] = cpu_to_le16(q_ids[i]); 3433 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list, 3434 sizeof(qg_list), rst_src, vmvf_num, 3435 cd); 3436 3437 if (status) 3438 break; 3439 ice_free_sched_node(pi, node); 3440 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 3441 } 3442 mutex_unlock(&pi->sched_lock); 3443 return status; 3444 } 3445 3446 /** 3447 * ice_cfg_vsi_qs - configure the new/existing VSI queues 3448 * @pi: port information structure 3449 * @vsi_handle: software VSI handle 3450 * @tc_bitmap: TC bitmap 3451 * @maxqs: max queues array per TC 3452 * @owner: LAN or RDMA 3453 * 3454 * This function adds/updates the VSI queues per TC. 3455 */ 3456 static enum ice_status 3457 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 3458 u16 *maxqs, u8 owner) 3459 { 3460 enum ice_status status = 0; 3461 u8 i; 3462 3463 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3464 return ICE_ERR_CFG; 3465 3466 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3467 return ICE_ERR_PARAM; 3468 3469 mutex_lock(&pi->sched_lock); 3470 3471 ice_for_each_traffic_class(i) { 3472 /* configuration is possible only if TC node is present */ 3473 if (!ice_sched_get_tc_node(pi, i)) 3474 continue; 3475 3476 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 3477 ice_is_tc_ena(tc_bitmap, i)); 3478 if (status) 3479 break; 3480 } 3481 3482 mutex_unlock(&pi->sched_lock); 3483 return status; 3484 } 3485 3486 /** 3487 * ice_cfg_vsi_lan - configure VSI LAN queues 3488 * @pi: port information structure 3489 * @vsi_handle: software VSI handle 3490 * @tc_bitmap: TC bitmap 3491 * @max_lanqs: max LAN queues array per TC 3492 * 3493 * This function adds/updates the VSI LAN queues per TC. 3494 */ 3495 enum ice_status 3496 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 3497 u16 *max_lanqs) 3498 { 3499 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 3500 ICE_SCHED_NODE_OWNER_LAN); 3501 } 3502 3503 /** 3504 * ice_replay_pre_init - replay pre initialization 3505 * @hw: pointer to the HW struct 3506 * 3507 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 3508 */ 3509 static enum ice_status ice_replay_pre_init(struct ice_hw *hw) 3510 { 3511 struct ice_switch_info *sw = hw->switch_info; 3512 u8 i; 3513 3514 /* Delete old entries from replay filter list head if there is any */ 3515 ice_rm_all_sw_replay_rule_info(hw); 3516 /* In start of replay, move entries into replay_rules list, it 3517 * will allow adding rules entries back to filt_rules list, 3518 * which is operational list. 3519 */ 3520 for (i = 0; i < ICE_SW_LKUP_LAST; i++) 3521 list_replace_init(&sw->recp_list[i].filt_rules, 3522 &sw->recp_list[i].filt_replay_rules); 3523 3524 return 0; 3525 } 3526 3527 /** 3528 * ice_replay_vsi - replay VSI configuration 3529 * @hw: pointer to the HW struct 3530 * @vsi_handle: driver VSI handle 3531 * 3532 * Restore all VSI configuration after reset. It is required to call this 3533 * function with main VSI first. 3534 */ 3535 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 3536 { 3537 enum ice_status status; 3538 3539 if (!ice_is_vsi_valid(hw, vsi_handle)) 3540 return ICE_ERR_PARAM; 3541 3542 /* Replay pre-initialization if there is any */ 3543 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 3544 status = ice_replay_pre_init(hw); 3545 if (status) 3546 return status; 3547 } 3548 /* Replay per VSI all RSS configurations */ 3549 status = ice_replay_rss_cfg(hw, vsi_handle); 3550 if (status) 3551 return status; 3552 /* Replay per VSI all filters */ 3553 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 3554 return status; 3555 } 3556 3557 /** 3558 * ice_replay_post - post replay configuration cleanup 3559 * @hw: pointer to the HW struct 3560 * 3561 * Post replay cleanup. 3562 */ 3563 void ice_replay_post(struct ice_hw *hw) 3564 { 3565 /* Delete old entries from replay filter list head */ 3566 ice_rm_all_sw_replay_rule_info(hw); 3567 } 3568 3569 /** 3570 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 3571 * @hw: ptr to the hardware info 3572 * @reg: offset of 64 bit HW register to read from 3573 * @prev_stat_loaded: bool to specify if previous stats are loaded 3574 * @prev_stat: ptr to previous loaded stat value 3575 * @cur_stat: ptr to current stat value 3576 */ 3577 void 3578 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 3579 u64 *prev_stat, u64 *cur_stat) 3580 { 3581 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 3582 3583 /* device stats are not reset at PFR, they likely will not be zeroed 3584 * when the driver starts. Thus, save the value from the first read 3585 * without adding to the statistic value so that we report stats which 3586 * count up from zero. 3587 */ 3588 if (!prev_stat_loaded) { 3589 *prev_stat = new_data; 3590 return; 3591 } 3592 3593 /* Calculate the difference between the new and old values, and then 3594 * add it to the software stat value. 3595 */ 3596 if (new_data >= *prev_stat) 3597 *cur_stat += new_data - *prev_stat; 3598 else 3599 /* to manage the potential roll-over */ 3600 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 3601 3602 /* Update the previously stored value to prepare for next read */ 3603 *prev_stat = new_data; 3604 } 3605 3606 /** 3607 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 3608 * @hw: ptr to the hardware info 3609 * @reg: offset of HW register to read from 3610 * @prev_stat_loaded: bool to specify if previous stats are loaded 3611 * @prev_stat: ptr to previous loaded stat value 3612 * @cur_stat: ptr to current stat value 3613 */ 3614 void 3615 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 3616 u64 *prev_stat, u64 *cur_stat) 3617 { 3618 u32 new_data; 3619 3620 new_data = rd32(hw, reg); 3621 3622 /* device stats are not reset at PFR, they likely will not be zeroed 3623 * when the driver starts. Thus, save the value from the first read 3624 * without adding to the statistic value so that we report stats which 3625 * count up from zero. 3626 */ 3627 if (!prev_stat_loaded) { 3628 *prev_stat = new_data; 3629 return; 3630 } 3631 3632 /* Calculate the difference between the new and old values, and then 3633 * add it to the software stat value. 3634 */ 3635 if (new_data >= *prev_stat) 3636 *cur_stat += new_data - *prev_stat; 3637 else 3638 /* to manage the potential roll-over */ 3639 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 3640 3641 /* Update the previously stored value to prepare for next read */ 3642 *prev_stat = new_data; 3643 } 3644 3645 /** 3646 * ice_sched_query_elem - query element information from HW 3647 * @hw: pointer to the HW struct 3648 * @node_teid: node TEID to be queried 3649 * @buf: buffer to element information 3650 * 3651 * This function queries HW element information 3652 */ 3653 enum ice_status 3654 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 3655 struct ice_aqc_get_elem *buf) 3656 { 3657 u16 buf_size, num_elem_ret = 0; 3658 enum ice_status status; 3659 3660 buf_size = sizeof(*buf); 3661 memset(buf, 0, buf_size); 3662 buf->generic[0].node_teid = cpu_to_le32(node_teid); 3663 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 3664 NULL); 3665 if (status || num_elem_ret != 1) 3666 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 3667 return status; 3668 } 3669