1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 8 #define ICE_PF_RESET_WAIT_COUNT 200 9 10 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \ 11 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \ 12 ((ICE_RX_OPC_MDID << \ 13 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \ 14 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \ 15 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \ 16 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M)) 17 18 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \ 19 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \ 20 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \ 21 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \ 22 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \ 23 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \ 24 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \ 25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \ 26 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \ 27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M)) 28 29 /** 30 * ice_set_mac_type - Sets MAC type 31 * @hw: pointer to the HW structure 32 * 33 * This function sets the MAC type of the adapter based on the 34 * vendor ID and device ID stored in the HW structure. 35 */ 36 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 37 { 38 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 39 return ICE_ERR_DEVICE_NOT_SUPPORTED; 40 41 hw->mac_type = ICE_MAC_GENERIC; 42 return 0; 43 } 44 45 /** 46 * ice_dev_onetime_setup - Temporary HW/FW workarounds 47 * @hw: pointer to the HW structure 48 * 49 * This function provides temporary workarounds for certain issues 50 * that are expected to be fixed in the HW/FW. 51 */ 52 void ice_dev_onetime_setup(struct ice_hw *hw) 53 { 54 /* configure Rx - set non pxe mode */ 55 wr32(hw, GLLAN_RCTL_0, 0x1); 56 57 #define MBX_PF_VT_PFALLOC 0x00231E80 58 /* set VFs per PF */ 59 wr32(hw, MBX_PF_VT_PFALLOC, rd32(hw, PF_VT_PFALLOC_HIF)); 60 } 61 62 /** 63 * ice_clear_pf_cfg - Clear PF configuration 64 * @hw: pointer to the hardware structure 65 * 66 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 67 * configuration, flow director filters, etc.). 68 */ 69 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 70 { 71 struct ice_aq_desc desc; 72 73 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 74 75 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 76 } 77 78 /** 79 * ice_aq_manage_mac_read - manage MAC address read command 80 * @hw: pointer to the HW struct 81 * @buf: a virtual buffer to hold the manage MAC read response 82 * @buf_size: Size of the virtual buffer 83 * @cd: pointer to command details structure or NULL 84 * 85 * This function is used to return per PF station MAC address (0x0107). 86 * NOTE: Upon successful completion of this command, MAC address information 87 * is returned in user specified buffer. Please interpret user specified 88 * buffer as "manage_mac_read" response. 89 * Response such as various MAC addresses are stored in HW struct (port.mac) 90 * ice_aq_discover_caps is expected to be called before this function is called. 91 */ 92 static enum ice_status 93 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 94 struct ice_sq_cd *cd) 95 { 96 struct ice_aqc_manage_mac_read_resp *resp; 97 struct ice_aqc_manage_mac_read *cmd; 98 struct ice_aq_desc desc; 99 enum ice_status status; 100 u16 flags; 101 u8 i; 102 103 cmd = &desc.params.mac_read; 104 105 if (buf_size < sizeof(*resp)) 106 return ICE_ERR_BUF_TOO_SHORT; 107 108 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 109 110 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 111 if (status) 112 return status; 113 114 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 115 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 116 117 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 118 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 119 return ICE_ERR_CFG; 120 } 121 122 /* A single port can report up to two (LAN and WoL) addresses */ 123 for (i = 0; i < cmd->num_addr; i++) 124 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 125 ether_addr_copy(hw->port_info->mac.lan_addr, 126 resp[i].mac_addr); 127 ether_addr_copy(hw->port_info->mac.perm_addr, 128 resp[i].mac_addr); 129 break; 130 } 131 132 return 0; 133 } 134 135 /** 136 * ice_aq_get_phy_caps - returns PHY capabilities 137 * @pi: port information structure 138 * @qual_mods: report qualified modules 139 * @report_mode: report mode capabilities 140 * @pcaps: structure for PHY capabilities to be filled 141 * @cd: pointer to command details structure or NULL 142 * 143 * Returns the various PHY capabilities supported on the Port (0x0600) 144 */ 145 enum ice_status 146 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 147 struct ice_aqc_get_phy_caps_data *pcaps, 148 struct ice_sq_cd *cd) 149 { 150 struct ice_aqc_get_phy_caps *cmd; 151 u16 pcaps_size = sizeof(*pcaps); 152 struct ice_aq_desc desc; 153 enum ice_status status; 154 155 cmd = &desc.params.get_phy; 156 157 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 158 return ICE_ERR_PARAM; 159 160 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 161 162 if (qual_mods) 163 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 164 165 cmd->param0 |= cpu_to_le16(report_mode); 166 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd); 167 168 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) { 169 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 170 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 171 } 172 173 return status; 174 } 175 176 /** 177 * ice_get_media_type - Gets media type 178 * @pi: port information structure 179 */ 180 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 181 { 182 struct ice_link_status *hw_link_info; 183 184 if (!pi) 185 return ICE_MEDIA_UNKNOWN; 186 187 hw_link_info = &pi->phy.link_info; 188 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 189 /* If more than one media type is selected, report unknown */ 190 return ICE_MEDIA_UNKNOWN; 191 192 if (hw_link_info->phy_type_low) { 193 switch (hw_link_info->phy_type_low) { 194 case ICE_PHY_TYPE_LOW_1000BASE_SX: 195 case ICE_PHY_TYPE_LOW_1000BASE_LX: 196 case ICE_PHY_TYPE_LOW_10GBASE_SR: 197 case ICE_PHY_TYPE_LOW_10GBASE_LR: 198 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 199 case ICE_PHY_TYPE_LOW_25GBASE_SR: 200 case ICE_PHY_TYPE_LOW_25GBASE_LR: 201 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 202 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 203 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 204 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 205 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 206 case ICE_PHY_TYPE_LOW_50GBASE_SR: 207 case ICE_PHY_TYPE_LOW_50GBASE_FR: 208 case ICE_PHY_TYPE_LOW_50GBASE_LR: 209 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 210 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 211 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 212 case ICE_PHY_TYPE_LOW_100GBASE_DR: 213 return ICE_MEDIA_FIBER; 214 case ICE_PHY_TYPE_LOW_100BASE_TX: 215 case ICE_PHY_TYPE_LOW_1000BASE_T: 216 case ICE_PHY_TYPE_LOW_2500BASE_T: 217 case ICE_PHY_TYPE_LOW_5GBASE_T: 218 case ICE_PHY_TYPE_LOW_10GBASE_T: 219 case ICE_PHY_TYPE_LOW_25GBASE_T: 220 return ICE_MEDIA_BASET; 221 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 222 case ICE_PHY_TYPE_LOW_25GBASE_CR: 223 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 224 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 225 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 226 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 227 case ICE_PHY_TYPE_LOW_50GBASE_CP: 228 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 229 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 230 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 231 return ICE_MEDIA_DA; 232 case ICE_PHY_TYPE_LOW_1000BASE_KX: 233 case ICE_PHY_TYPE_LOW_2500BASE_KX: 234 case ICE_PHY_TYPE_LOW_2500BASE_X: 235 case ICE_PHY_TYPE_LOW_5GBASE_KR: 236 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 237 case ICE_PHY_TYPE_LOW_25GBASE_KR: 238 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 239 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 240 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 241 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 242 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 243 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 244 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 245 return ICE_MEDIA_BACKPLANE; 246 } 247 } else { 248 switch (hw_link_info->phy_type_high) { 249 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 250 return ICE_MEDIA_BACKPLANE; 251 } 252 } 253 return ICE_MEDIA_UNKNOWN; 254 } 255 256 /** 257 * ice_aq_get_link_info 258 * @pi: port information structure 259 * @ena_lse: enable/disable LinkStatusEvent reporting 260 * @link: pointer to link status structure - optional 261 * @cd: pointer to command details structure or NULL 262 * 263 * Get Link Status (0x607). Returns the link status of the adapter. 264 */ 265 enum ice_status 266 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 267 struct ice_link_status *link, struct ice_sq_cd *cd) 268 { 269 struct ice_link_status *hw_link_info_old, *hw_link_info; 270 struct ice_aqc_get_link_status_data link_data = { 0 }; 271 struct ice_aqc_get_link_status *resp; 272 enum ice_media_type *hw_media_type; 273 struct ice_fc_info *hw_fc_info; 274 bool tx_pause, rx_pause; 275 struct ice_aq_desc desc; 276 enum ice_status status; 277 u16 cmd_flags; 278 279 if (!pi) 280 return ICE_ERR_PARAM; 281 hw_link_info_old = &pi->phy.link_info_old; 282 hw_media_type = &pi->phy.media_type; 283 hw_link_info = &pi->phy.link_info; 284 hw_fc_info = &pi->fc; 285 286 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 287 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 288 resp = &desc.params.get_link_status; 289 resp->cmd_flags = cpu_to_le16(cmd_flags); 290 resp->lport_num = pi->lport; 291 292 status = ice_aq_send_cmd(pi->hw, &desc, &link_data, sizeof(link_data), 293 cd); 294 295 if (status) 296 return status; 297 298 /* save off old link status information */ 299 *hw_link_info_old = *hw_link_info; 300 301 /* update current link status information */ 302 hw_link_info->link_speed = le16_to_cpu(link_data.link_speed); 303 hw_link_info->phy_type_low = le64_to_cpu(link_data.phy_type_low); 304 hw_link_info->phy_type_high = le64_to_cpu(link_data.phy_type_high); 305 *hw_media_type = ice_get_media_type(pi); 306 hw_link_info->link_info = link_data.link_info; 307 hw_link_info->an_info = link_data.an_info; 308 hw_link_info->ext_info = link_data.ext_info; 309 hw_link_info->max_frame_size = le16_to_cpu(link_data.max_frame_size); 310 hw_link_info->pacing = link_data.cfg & ICE_AQ_CFG_PACING_M; 311 312 /* update fc info */ 313 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 314 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 315 if (tx_pause && rx_pause) 316 hw_fc_info->current_mode = ICE_FC_FULL; 317 else if (tx_pause) 318 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 319 else if (rx_pause) 320 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 321 else 322 hw_fc_info->current_mode = ICE_FC_NONE; 323 324 hw_link_info->lse_ena = 325 !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 326 327 /* save link status information */ 328 if (link) 329 *link = *hw_link_info; 330 331 /* flag cleared so calling functions don't call AQ again */ 332 pi->phy.get_link_info = false; 333 334 return 0; 335 } 336 337 /** 338 * ice_init_flex_flags 339 * @hw: pointer to the hardware structure 340 * @prof_id: Rx Descriptor Builder profile ID 341 * 342 * Function to initialize Rx flex flags 343 */ 344 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id) 345 { 346 u8 idx = 0; 347 348 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout: 349 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE 350 * flexiflags1[3:0] - Not used for flag programming 351 * flexiflags2[7:0] - Tunnel and VLAN types 352 * 2 invalid fields in last index 353 */ 354 switch (prof_id) { 355 /* Rx flex flags are currently programmed for the NIC profiles only. 356 * Different flag bit programming configurations can be added per 357 * profile as needed. 358 */ 359 case ICE_RXDID_FLEX_NIC: 360 case ICE_RXDID_FLEX_NIC_2: 361 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG, 362 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI, 363 ICE_FLG_FIN, idx++); 364 /* flex flag 1 is not used for flexi-flag programming, skipping 365 * these four FLG64 bits. 366 */ 367 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST, 368 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++); 369 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI, 370 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100, 371 ICE_FLG_EVLAN_x9100, idx++); 372 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100, 373 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC, 374 ICE_FLG_TNL0, idx++); 375 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2, 376 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx); 377 break; 378 379 default: 380 ice_debug(hw, ICE_DBG_INIT, 381 "Flag programming for profile ID %d not supported\n", 382 prof_id); 383 } 384 } 385 386 /** 387 * ice_init_flex_flds 388 * @hw: pointer to the hardware structure 389 * @prof_id: Rx Descriptor Builder profile ID 390 * 391 * Function to initialize flex descriptors 392 */ 393 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id) 394 { 395 enum ice_flex_rx_mdid mdid; 396 397 switch (prof_id) { 398 case ICE_RXDID_FLEX_NIC: 399 case ICE_RXDID_FLEX_NIC_2: 400 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_LOW, 0); 401 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_HIGH, 1); 402 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_FLOW_ID_LOWER, 2); 403 404 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ? 405 ICE_RX_MDID_SRC_VSI : ICE_RX_MDID_FLOW_ID_HIGH; 406 407 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3); 408 409 ice_init_flex_flags(hw, prof_id); 410 break; 411 412 default: 413 ice_debug(hw, ICE_DBG_INIT, 414 "Field init for profile ID %d not supported\n", 415 prof_id); 416 } 417 } 418 419 /** 420 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 421 * @hw: pointer to the HW struct 422 */ 423 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 424 { 425 struct ice_switch_info *sw; 426 427 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 428 sizeof(*hw->switch_info), GFP_KERNEL); 429 sw = hw->switch_info; 430 431 if (!sw) 432 return ICE_ERR_NO_MEMORY; 433 434 INIT_LIST_HEAD(&sw->vsi_list_map_head); 435 436 return ice_init_def_sw_recp(hw); 437 } 438 439 /** 440 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 441 * @hw: pointer to the HW struct 442 */ 443 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 444 { 445 struct ice_switch_info *sw = hw->switch_info; 446 struct ice_vsi_list_map_info *v_pos_map; 447 struct ice_vsi_list_map_info *v_tmp_map; 448 struct ice_sw_recipe *recps; 449 u8 i; 450 451 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 452 list_entry) { 453 list_del(&v_pos_map->list_entry); 454 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 455 } 456 recps = hw->switch_info->recp_list; 457 for (i = 0; i < ICE_SW_LKUP_LAST; i++) { 458 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 459 460 recps[i].root_rid = i; 461 mutex_destroy(&recps[i].filt_rule_lock); 462 list_for_each_entry_safe(lst_itr, tmp_entry, 463 &recps[i].filt_rules, list_entry) { 464 list_del(&lst_itr->list_entry); 465 devm_kfree(ice_hw_to_dev(hw), lst_itr); 466 } 467 } 468 ice_rm_all_sw_replay_rule_info(hw); 469 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 470 devm_kfree(ice_hw_to_dev(hw), sw); 471 } 472 473 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \ 474 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry))) 475 #define ICE_FW_LOG_DESC_SIZE_MAX \ 476 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX) 477 478 /** 479 * ice_cfg_fw_log - configure FW logging 480 * @hw: pointer to the HW struct 481 * @enable: enable certain FW logging events if true, disable all if false 482 * 483 * This function enables/disables the FW logging via Rx CQ events and a UART 484 * port based on predetermined configurations. FW logging via the Rx CQ can be 485 * enabled/disabled for individual PF's. However, FW logging via the UART can 486 * only be enabled/disabled for all PFs on the same device. 487 * 488 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 489 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 490 * before initializing the device. 491 * 492 * When re/configuring FW logging, callers need to update the "cfg" elements of 493 * the hw->fw_log.evnts array with the desired logging event configurations for 494 * modules of interest. When disabling FW logging completely, the callers can 495 * just pass false in the "enable" parameter. On completion, the function will 496 * update the "cur" element of the hw->fw_log.evnts array with the resulting 497 * logging event configurations of the modules that are being re/configured. FW 498 * logging modules that are not part of a reconfiguration operation retain their 499 * previous states. 500 * 501 * Before resetting the device, it is recommended that the driver disables FW 502 * logging before shutting down the control queue. When disabling FW logging 503 * ("enable" = false), the latest configurations of FW logging events stored in 504 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 505 * a device reset. 506 * 507 * When enabling FW logging to emit log messages via the Rx CQ during the 508 * device's initialization phase, a mechanism alternative to interrupt handlers 509 * needs to be used to extract FW log messages from the Rx CQ periodically and 510 * to prevent the Rx CQ from being full and stalling other types of control 511 * messages from FW to SW. Interrupts are typically disabled during the device's 512 * initialization phase. 513 */ 514 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable) 515 { 516 struct ice_aqc_fw_logging_data *data = NULL; 517 struct ice_aqc_fw_logging *cmd; 518 enum ice_status status = 0; 519 u16 i, chgs = 0, len = 0; 520 struct ice_aq_desc desc; 521 u8 actv_evnts = 0; 522 void *buf = NULL; 523 524 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 525 return 0; 526 527 /* Disable FW logging only when the control queue is still responsive */ 528 if (!enable && 529 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 530 return 0; 531 532 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 533 cmd = &desc.params.fw_logging; 534 535 /* Indicate which controls are valid */ 536 if (hw->fw_log.cq_en) 537 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 538 539 if (hw->fw_log.uart_en) 540 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 541 542 if (enable) { 543 /* Fill in an array of entries with FW logging modules and 544 * logging events being reconfigured. 545 */ 546 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 547 u16 val; 548 549 /* Keep track of enabled event types */ 550 actv_evnts |= hw->fw_log.evnts[i].cfg; 551 552 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 553 continue; 554 555 if (!data) { 556 data = devm_kzalloc(ice_hw_to_dev(hw), 557 ICE_FW_LOG_DESC_SIZE_MAX, 558 GFP_KERNEL); 559 if (!data) 560 return ICE_ERR_NO_MEMORY; 561 } 562 563 val = i << ICE_AQC_FW_LOG_ID_S; 564 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 565 data->entry[chgs++] = cpu_to_le16(val); 566 } 567 568 /* Only enable FW logging if at least one module is specified. 569 * If FW logging is currently enabled but all modules are not 570 * enabled to emit log messages, disable FW logging altogether. 571 */ 572 if (actv_evnts) { 573 /* Leave if there is effectively no change */ 574 if (!chgs) 575 goto out; 576 577 if (hw->fw_log.cq_en) 578 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 579 580 if (hw->fw_log.uart_en) 581 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 582 583 buf = data; 584 len = ICE_FW_LOG_DESC_SIZE(chgs); 585 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 586 } 587 } 588 589 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 590 if (!status) { 591 /* Update the current configuration to reflect events enabled. 592 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 593 * logging mode is enabled for the device. They do not reflect 594 * actual modules being enabled to emit log messages. So, their 595 * values remain unchanged even when all modules are disabled. 596 */ 597 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 598 599 hw->fw_log.actv_evnts = actv_evnts; 600 for (i = 0; i < cnt; i++) { 601 u16 v, m; 602 603 if (!enable) { 604 /* When disabling all FW logging events as part 605 * of device's de-initialization, the original 606 * configurations are retained, and can be used 607 * to reconfigure FW logging later if the device 608 * is re-initialized. 609 */ 610 hw->fw_log.evnts[i].cur = 0; 611 continue; 612 } 613 614 v = le16_to_cpu(data->entry[i]); 615 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 616 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 617 } 618 } 619 620 out: 621 if (data) 622 devm_kfree(ice_hw_to_dev(hw), data); 623 624 return status; 625 } 626 627 /** 628 * ice_output_fw_log 629 * @hw: pointer to the HW struct 630 * @desc: pointer to the AQ message descriptor 631 * @buf: pointer to the buffer accompanying the AQ message 632 * 633 * Formats a FW Log message and outputs it via the standard driver logs. 634 */ 635 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 636 { 637 ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg Start ]\n"); 638 ice_debug_array(hw, ICE_DBG_AQ_MSG, 16, 1, (u8 *)buf, 639 le16_to_cpu(desc->datalen)); 640 ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg End ]\n"); 641 } 642 643 /** 644 * ice_get_itr_intrl_gran - determine int/intrl granularity 645 * @hw: pointer to the HW struct 646 * 647 * Determines the itr/intrl granularities based on the maximum aggregate 648 * bandwidth according to the device's configuration during power-on. 649 */ 650 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 651 { 652 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 653 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 654 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 655 656 switch (max_agg_bw) { 657 case ICE_MAX_AGG_BW_200G: 658 case ICE_MAX_AGG_BW_100G: 659 case ICE_MAX_AGG_BW_50G: 660 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 661 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 662 break; 663 case ICE_MAX_AGG_BW_25G: 664 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 665 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 666 break; 667 } 668 } 669 670 /** 671 * ice_init_hw - main hardware initialization routine 672 * @hw: pointer to the hardware structure 673 */ 674 enum ice_status ice_init_hw(struct ice_hw *hw) 675 { 676 struct ice_aqc_get_phy_caps_data *pcaps; 677 enum ice_status status; 678 u16 mac_buf_len; 679 void *mac_buf; 680 681 /* Set MAC type based on DeviceID */ 682 status = ice_set_mac_type(hw); 683 if (status) 684 return status; 685 686 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 687 PF_FUNC_RID_FUNC_NUM_M) >> 688 PF_FUNC_RID_FUNC_NUM_S; 689 690 status = ice_reset(hw, ICE_RESET_PFR); 691 if (status) 692 return status; 693 694 ice_get_itr_intrl_gran(hw); 695 696 status = ice_init_all_ctrlq(hw); 697 if (status) 698 goto err_unroll_cqinit; 699 700 /* Enable FW logging. Not fatal if this fails. */ 701 status = ice_cfg_fw_log(hw, true); 702 if (status) 703 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 704 705 status = ice_clear_pf_cfg(hw); 706 if (status) 707 goto err_unroll_cqinit; 708 709 ice_clear_pxe_mode(hw); 710 711 status = ice_init_nvm(hw); 712 if (status) 713 goto err_unroll_cqinit; 714 715 status = ice_get_caps(hw); 716 if (status) 717 goto err_unroll_cqinit; 718 719 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 720 sizeof(*hw->port_info), GFP_KERNEL); 721 if (!hw->port_info) { 722 status = ICE_ERR_NO_MEMORY; 723 goto err_unroll_cqinit; 724 } 725 726 /* set the back pointer to HW */ 727 hw->port_info->hw = hw; 728 729 /* Initialize port_info struct with switch configuration data */ 730 status = ice_get_initial_sw_cfg(hw); 731 if (status) 732 goto err_unroll_alloc; 733 734 hw->evb_veb = true; 735 736 /* Query the allocated resources for Tx scheduler */ 737 status = ice_sched_query_res_alloc(hw); 738 if (status) { 739 ice_debug(hw, ICE_DBG_SCHED, 740 "Failed to get scheduler allocated resources\n"); 741 goto err_unroll_alloc; 742 } 743 744 /* Initialize port_info struct with scheduler data */ 745 status = ice_sched_init_port(hw->port_info); 746 if (status) 747 goto err_unroll_sched; 748 749 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 750 if (!pcaps) { 751 status = ICE_ERR_NO_MEMORY; 752 goto err_unroll_sched; 753 } 754 755 /* Initialize port_info struct with PHY capabilities */ 756 status = ice_aq_get_phy_caps(hw->port_info, false, 757 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); 758 devm_kfree(ice_hw_to_dev(hw), pcaps); 759 if (status) 760 goto err_unroll_sched; 761 762 /* Initialize port_info struct with link information */ 763 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 764 if (status) 765 goto err_unroll_sched; 766 767 /* need a valid SW entry point to build a Tx tree */ 768 if (!hw->sw_entry_point_layer) { 769 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 770 status = ICE_ERR_CFG; 771 goto err_unroll_sched; 772 } 773 INIT_LIST_HEAD(&hw->agg_list); 774 775 status = ice_init_fltr_mgmt_struct(hw); 776 if (status) 777 goto err_unroll_sched; 778 779 ice_dev_onetime_setup(hw); 780 781 /* Get MAC information */ 782 /* A single port can report up to two (LAN and WoL) addresses */ 783 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 784 sizeof(struct ice_aqc_manage_mac_read_resp), 785 GFP_KERNEL); 786 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 787 788 if (!mac_buf) { 789 status = ICE_ERR_NO_MEMORY; 790 goto err_unroll_fltr_mgmt_struct; 791 } 792 793 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 794 devm_kfree(ice_hw_to_dev(hw), mac_buf); 795 796 if (status) 797 goto err_unroll_fltr_mgmt_struct; 798 799 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC); 800 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2); 801 802 return 0; 803 804 err_unroll_fltr_mgmt_struct: 805 ice_cleanup_fltr_mgmt_struct(hw); 806 err_unroll_sched: 807 ice_sched_cleanup_all(hw); 808 err_unroll_alloc: 809 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 810 err_unroll_cqinit: 811 ice_shutdown_all_ctrlq(hw); 812 return status; 813 } 814 815 /** 816 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 817 * @hw: pointer to the hardware structure 818 */ 819 void ice_deinit_hw(struct ice_hw *hw) 820 { 821 ice_cleanup_fltr_mgmt_struct(hw); 822 823 ice_sched_cleanup_all(hw); 824 ice_sched_clear_agg(hw); 825 826 if (hw->port_info) { 827 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 828 hw->port_info = NULL; 829 } 830 831 /* Attempt to disable FW logging before shutting down control queues */ 832 ice_cfg_fw_log(hw, false); 833 ice_shutdown_all_ctrlq(hw); 834 835 /* Clear VSI contexts if not already cleared */ 836 ice_clear_all_vsi_ctx(hw); 837 } 838 839 /** 840 * ice_check_reset - Check to see if a global reset is complete 841 * @hw: pointer to the hardware structure 842 */ 843 enum ice_status ice_check_reset(struct ice_hw *hw) 844 { 845 u32 cnt, reg = 0, grst_delay; 846 847 /* Poll for Device Active state in case a recent CORER, GLOBR, 848 * or EMPR has occurred. The grst delay value is in 100ms units. 849 * Add 1sec for outstanding AQ commands that can take a long time. 850 */ 851 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 852 GLGEN_RSTCTL_GRSTDEL_S) + 10; 853 854 for (cnt = 0; cnt < grst_delay; cnt++) { 855 mdelay(100); 856 reg = rd32(hw, GLGEN_RSTAT); 857 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 858 break; 859 } 860 861 if (cnt == grst_delay) { 862 ice_debug(hw, ICE_DBG_INIT, 863 "Global reset polling failed to complete.\n"); 864 return ICE_ERR_RESET_FAILED; 865 } 866 867 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \ 868 GLNVM_ULD_GLOBR_DONE_M) 869 870 /* Device is Active; check Global Reset processes are done */ 871 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 872 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK; 873 if (reg == ICE_RESET_DONE_MASK) { 874 ice_debug(hw, ICE_DBG_INIT, 875 "Global reset processes done. %d\n", cnt); 876 break; 877 } 878 mdelay(10); 879 } 880 881 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 882 ice_debug(hw, ICE_DBG_INIT, 883 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 884 reg); 885 return ICE_ERR_RESET_FAILED; 886 } 887 888 return 0; 889 } 890 891 /** 892 * ice_pf_reset - Reset the PF 893 * @hw: pointer to the hardware structure 894 * 895 * If a global reset has been triggered, this function checks 896 * for its completion and then issues the PF reset 897 */ 898 static enum ice_status ice_pf_reset(struct ice_hw *hw) 899 { 900 u32 cnt, reg; 901 902 /* If at function entry a global reset was already in progress, i.e. 903 * state is not 'device active' or any of the reset done bits are not 904 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 905 * global reset is done. 906 */ 907 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 908 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 909 /* poll on global reset currently in progress until done */ 910 if (ice_check_reset(hw)) 911 return ICE_ERR_RESET_FAILED; 912 913 return 0; 914 } 915 916 /* Reset the PF */ 917 reg = rd32(hw, PFGEN_CTRL); 918 919 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 920 921 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 922 reg = rd32(hw, PFGEN_CTRL); 923 if (!(reg & PFGEN_CTRL_PFSWR_M)) 924 break; 925 926 mdelay(1); 927 } 928 929 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 930 ice_debug(hw, ICE_DBG_INIT, 931 "PF reset polling failed to complete.\n"); 932 return ICE_ERR_RESET_FAILED; 933 } 934 935 return 0; 936 } 937 938 /** 939 * ice_reset - Perform different types of reset 940 * @hw: pointer to the hardware structure 941 * @req: reset request 942 * 943 * This function triggers a reset as specified by the req parameter. 944 * 945 * Note: 946 * If anything other than a PF reset is triggered, PXE mode is restored. 947 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 948 * interface has been restored in the rebuild flow. 949 */ 950 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 951 { 952 u32 val = 0; 953 954 switch (req) { 955 case ICE_RESET_PFR: 956 return ice_pf_reset(hw); 957 case ICE_RESET_CORER: 958 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 959 val = GLGEN_RTRIG_CORER_M; 960 break; 961 case ICE_RESET_GLOBR: 962 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 963 val = GLGEN_RTRIG_GLOBR_M; 964 break; 965 default: 966 return ICE_ERR_PARAM; 967 } 968 969 val |= rd32(hw, GLGEN_RTRIG); 970 wr32(hw, GLGEN_RTRIG, val); 971 ice_flush(hw); 972 973 /* wait for the FW to be ready */ 974 return ice_check_reset(hw); 975 } 976 977 /** 978 * ice_copy_rxq_ctx_to_hw 979 * @hw: pointer to the hardware structure 980 * @ice_rxq_ctx: pointer to the rxq context 981 * @rxq_index: the index of the Rx queue 982 * 983 * Copies rxq context from dense structure to HW register space 984 */ 985 static enum ice_status 986 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 987 { 988 u8 i; 989 990 if (!ice_rxq_ctx) 991 return ICE_ERR_BAD_PTR; 992 993 if (rxq_index > QRX_CTRL_MAX_INDEX) 994 return ICE_ERR_PARAM; 995 996 /* Copy each dword separately to HW */ 997 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 998 wr32(hw, QRX_CONTEXT(i, rxq_index), 999 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1000 1001 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1002 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1003 } 1004 1005 return 0; 1006 } 1007 1008 /* LAN Rx Queue Context */ 1009 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1010 /* Field Width LSB */ 1011 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1012 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1013 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1014 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1015 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1016 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1017 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1018 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1019 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1020 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1021 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1022 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1023 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1024 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1025 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1026 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1027 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1028 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1029 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1030 { 0 } 1031 }; 1032 1033 /** 1034 * ice_write_rxq_ctx 1035 * @hw: pointer to the hardware structure 1036 * @rlan_ctx: pointer to the rxq context 1037 * @rxq_index: the index of the Rx queue 1038 * 1039 * Converts rxq context from sparse to dense structure and then writes 1040 * it to HW register space 1041 */ 1042 enum ice_status 1043 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1044 u32 rxq_index) 1045 { 1046 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1047 1048 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1049 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1050 } 1051 1052 /* LAN Tx Queue Context */ 1053 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1054 /* Field Width LSB */ 1055 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1056 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1057 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1058 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1059 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1060 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1061 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1062 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1063 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1064 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1065 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1066 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1067 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1068 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1069 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1070 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1071 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1072 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1073 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1074 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1075 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1076 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1077 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1078 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1079 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1080 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1081 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 110, 171), 1082 { 0 } 1083 }; 1084 1085 /** 1086 * ice_debug_cq 1087 * @hw: pointer to the hardware structure 1088 * @mask: debug mask 1089 * @desc: pointer to control queue descriptor 1090 * @buf: pointer to command buffer 1091 * @buf_len: max length of buf 1092 * 1093 * Dumps debug log about control command with descriptor contents. 1094 */ 1095 void 1096 ice_debug_cq(struct ice_hw *hw, u32 __maybe_unused mask, void *desc, void *buf, 1097 u16 buf_len) 1098 { 1099 struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc; 1100 u16 len; 1101 1102 #ifndef CONFIG_DYNAMIC_DEBUG 1103 if (!(mask & hw->debug_mask)) 1104 return; 1105 #endif 1106 1107 if (!desc) 1108 return; 1109 1110 len = le16_to_cpu(cq_desc->datalen); 1111 1112 ice_debug(hw, mask, 1113 "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 1114 le16_to_cpu(cq_desc->opcode), 1115 le16_to_cpu(cq_desc->flags), 1116 le16_to_cpu(cq_desc->datalen), le16_to_cpu(cq_desc->retval)); 1117 ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 1118 le32_to_cpu(cq_desc->cookie_high), 1119 le32_to_cpu(cq_desc->cookie_low)); 1120 ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 1121 le32_to_cpu(cq_desc->params.generic.param0), 1122 le32_to_cpu(cq_desc->params.generic.param1)); 1123 ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 1124 le32_to_cpu(cq_desc->params.generic.addr_high), 1125 le32_to_cpu(cq_desc->params.generic.addr_low)); 1126 if (buf && cq_desc->datalen != 0) { 1127 ice_debug(hw, mask, "Buffer:\n"); 1128 if (buf_len < len) 1129 len = buf_len; 1130 1131 ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len); 1132 } 1133 } 1134 1135 /* FW Admin Queue command wrappers */ 1136 1137 /** 1138 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1139 * @hw: pointer to the HW struct 1140 * @desc: descriptor describing the command 1141 * @buf: buffer to use for indirect commands (NULL for direct commands) 1142 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1143 * @cd: pointer to command details structure 1144 * 1145 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1146 */ 1147 enum ice_status 1148 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1149 u16 buf_size, struct ice_sq_cd *cd) 1150 { 1151 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); 1152 } 1153 1154 /** 1155 * ice_aq_get_fw_ver 1156 * @hw: pointer to the HW struct 1157 * @cd: pointer to command details structure or NULL 1158 * 1159 * Get the firmware version (0x0001) from the admin queue commands 1160 */ 1161 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1162 { 1163 struct ice_aqc_get_ver *resp; 1164 struct ice_aq_desc desc; 1165 enum ice_status status; 1166 1167 resp = &desc.params.get_ver; 1168 1169 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1170 1171 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1172 1173 if (!status) { 1174 hw->fw_branch = resp->fw_branch; 1175 hw->fw_maj_ver = resp->fw_major; 1176 hw->fw_min_ver = resp->fw_minor; 1177 hw->fw_patch = resp->fw_patch; 1178 hw->fw_build = le32_to_cpu(resp->fw_build); 1179 hw->api_branch = resp->api_branch; 1180 hw->api_maj_ver = resp->api_major; 1181 hw->api_min_ver = resp->api_minor; 1182 hw->api_patch = resp->api_patch; 1183 } 1184 1185 return status; 1186 } 1187 1188 /** 1189 * ice_aq_q_shutdown 1190 * @hw: pointer to the HW struct 1191 * @unloading: is the driver unloading itself 1192 * 1193 * Tell the Firmware that we're shutting down the AdminQ and whether 1194 * or not the driver is unloading as well (0x0003). 1195 */ 1196 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1197 { 1198 struct ice_aqc_q_shutdown *cmd; 1199 struct ice_aq_desc desc; 1200 1201 cmd = &desc.params.q_shutdown; 1202 1203 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1204 1205 if (unloading) 1206 cmd->driver_unloading = cpu_to_le32(ICE_AQC_DRIVER_UNLOADING); 1207 1208 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1209 } 1210 1211 /** 1212 * ice_aq_req_res 1213 * @hw: pointer to the HW struct 1214 * @res: resource ID 1215 * @access: access type 1216 * @sdp_number: resource number 1217 * @timeout: the maximum time in ms that the driver may hold the resource 1218 * @cd: pointer to command details structure or NULL 1219 * 1220 * Requests common resource using the admin queue commands (0x0008). 1221 * When attempting to acquire the Global Config Lock, the driver can 1222 * learn of three states: 1223 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1224 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1225 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1226 * successfully downloaded the package; the driver does 1227 * not have to download the package and can continue 1228 * loading 1229 * 1230 * Note that if the caller is in an acquire lock, perform action, release lock 1231 * phase of operation, it is possible that the FW may detect a timeout and issue 1232 * a CORER. In this case, the driver will receive a CORER interrupt and will 1233 * have to determine its cause. The calling thread that is handling this flow 1234 * will likely get an error propagated back to it indicating the Download 1235 * Package, Update Package or the Release Resource AQ commands timed out. 1236 */ 1237 static enum ice_status 1238 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1239 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1240 struct ice_sq_cd *cd) 1241 { 1242 struct ice_aqc_req_res *cmd_resp; 1243 struct ice_aq_desc desc; 1244 enum ice_status status; 1245 1246 cmd_resp = &desc.params.res_owner; 1247 1248 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1249 1250 cmd_resp->res_id = cpu_to_le16(res); 1251 cmd_resp->access_type = cpu_to_le16(access); 1252 cmd_resp->res_number = cpu_to_le32(sdp_number); 1253 cmd_resp->timeout = cpu_to_le32(*timeout); 1254 *timeout = 0; 1255 1256 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1257 1258 /* The completion specifies the maximum time in ms that the driver 1259 * may hold the resource in the Timeout field. 1260 */ 1261 1262 /* Global config lock response utilizes an additional status field. 1263 * 1264 * If the Global config lock resource is held by some other driver, the 1265 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1266 * and the timeout field indicates the maximum time the current owner 1267 * of the resource has to free it. 1268 */ 1269 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1270 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1271 *timeout = le32_to_cpu(cmd_resp->timeout); 1272 return 0; 1273 } else if (le16_to_cpu(cmd_resp->status) == 1274 ICE_AQ_RES_GLBL_IN_PROG) { 1275 *timeout = le32_to_cpu(cmd_resp->timeout); 1276 return ICE_ERR_AQ_ERROR; 1277 } else if (le16_to_cpu(cmd_resp->status) == 1278 ICE_AQ_RES_GLBL_DONE) { 1279 return ICE_ERR_AQ_NO_WORK; 1280 } 1281 1282 /* invalid FW response, force a timeout immediately */ 1283 *timeout = 0; 1284 return ICE_ERR_AQ_ERROR; 1285 } 1286 1287 /* If the resource is held by some other driver, the command completes 1288 * with a busy return value and the timeout field indicates the maximum 1289 * time the current owner of the resource has to free it. 1290 */ 1291 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1292 *timeout = le32_to_cpu(cmd_resp->timeout); 1293 1294 return status; 1295 } 1296 1297 /** 1298 * ice_aq_release_res 1299 * @hw: pointer to the HW struct 1300 * @res: resource ID 1301 * @sdp_number: resource number 1302 * @cd: pointer to command details structure or NULL 1303 * 1304 * release common resource using the admin queue commands (0x0009) 1305 */ 1306 static enum ice_status 1307 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1308 struct ice_sq_cd *cd) 1309 { 1310 struct ice_aqc_req_res *cmd; 1311 struct ice_aq_desc desc; 1312 1313 cmd = &desc.params.res_owner; 1314 1315 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1316 1317 cmd->res_id = cpu_to_le16(res); 1318 cmd->res_number = cpu_to_le32(sdp_number); 1319 1320 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1321 } 1322 1323 /** 1324 * ice_acquire_res 1325 * @hw: pointer to the HW structure 1326 * @res: resource ID 1327 * @access: access type (read or write) 1328 * @timeout: timeout in milliseconds 1329 * 1330 * This function will attempt to acquire the ownership of a resource. 1331 */ 1332 enum ice_status 1333 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1334 enum ice_aq_res_access_type access, u32 timeout) 1335 { 1336 #define ICE_RES_POLLING_DELAY_MS 10 1337 u32 delay = ICE_RES_POLLING_DELAY_MS; 1338 u32 time_left = timeout; 1339 enum ice_status status; 1340 1341 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1342 1343 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1344 * previously acquired the resource and performed any necessary updates; 1345 * in this case the caller does not obtain the resource and has no 1346 * further work to do. 1347 */ 1348 if (status == ICE_ERR_AQ_NO_WORK) 1349 goto ice_acquire_res_exit; 1350 1351 if (status) 1352 ice_debug(hw, ICE_DBG_RES, 1353 "resource %d acquire type %d failed.\n", res, access); 1354 1355 /* If necessary, poll until the current lock owner timeouts */ 1356 timeout = time_left; 1357 while (status && timeout && time_left) { 1358 mdelay(delay); 1359 timeout = (timeout > delay) ? timeout - delay : 0; 1360 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1361 1362 if (status == ICE_ERR_AQ_NO_WORK) 1363 /* lock free, but no work to do */ 1364 break; 1365 1366 if (!status) 1367 /* lock acquired */ 1368 break; 1369 } 1370 if (status && status != ICE_ERR_AQ_NO_WORK) 1371 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1372 1373 ice_acquire_res_exit: 1374 if (status == ICE_ERR_AQ_NO_WORK) { 1375 if (access == ICE_RES_WRITE) 1376 ice_debug(hw, ICE_DBG_RES, 1377 "resource indicates no work to do.\n"); 1378 else 1379 ice_debug(hw, ICE_DBG_RES, 1380 "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1381 } 1382 return status; 1383 } 1384 1385 /** 1386 * ice_release_res 1387 * @hw: pointer to the HW structure 1388 * @res: resource ID 1389 * 1390 * This function will release a resource using the proper Admin Command. 1391 */ 1392 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1393 { 1394 enum ice_status status; 1395 u32 total_delay = 0; 1396 1397 status = ice_aq_release_res(hw, res, 0, NULL); 1398 1399 /* there are some rare cases when trying to release the resource 1400 * results in an admin queue timeout, so handle them correctly 1401 */ 1402 while ((status == ICE_ERR_AQ_TIMEOUT) && 1403 (total_delay < hw->adminq.sq_cmd_timeout)) { 1404 mdelay(1); 1405 status = ice_aq_release_res(hw, res, 0, NULL); 1406 total_delay++; 1407 } 1408 } 1409 1410 /** 1411 * ice_get_num_per_func - determine number of resources per PF 1412 * @hw: pointer to the HW structure 1413 * @max: value to be evenly split between each PF 1414 * 1415 * Determine the number of valid functions by going through the bitmap returned 1416 * from parsing capabilities and use this to calculate the number of resources 1417 * per PF based on the max value passed in. 1418 */ 1419 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1420 { 1421 u8 funcs; 1422 1423 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1424 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 1425 ICE_CAPS_VALID_FUNCS_M); 1426 1427 if (!funcs) 1428 return 0; 1429 1430 return max / funcs; 1431 } 1432 1433 /** 1434 * ice_parse_caps - parse function/device capabilities 1435 * @hw: pointer to the HW struct 1436 * @buf: pointer to a buffer containing function/device capability records 1437 * @cap_count: number of capability records in the list 1438 * @opc: type of capabilities list to parse 1439 * 1440 * Helper function to parse function(0x000a)/device(0x000b) capabilities list. 1441 */ 1442 static void 1443 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, 1444 enum ice_adminq_opc opc) 1445 { 1446 struct ice_aqc_list_caps_elem *cap_resp; 1447 struct ice_hw_func_caps *func_p = NULL; 1448 struct ice_hw_dev_caps *dev_p = NULL; 1449 struct ice_hw_common_caps *caps; 1450 u32 i; 1451 1452 if (!buf) 1453 return; 1454 1455 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 1456 1457 if (opc == ice_aqc_opc_list_dev_caps) { 1458 dev_p = &hw->dev_caps; 1459 caps = &dev_p->common_cap; 1460 } else if (opc == ice_aqc_opc_list_func_caps) { 1461 func_p = &hw->func_caps; 1462 caps = &func_p->common_cap; 1463 } else { 1464 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n"); 1465 return; 1466 } 1467 1468 for (i = 0; caps && i < cap_count; i++, cap_resp++) { 1469 u32 logical_id = le32_to_cpu(cap_resp->logical_id); 1470 u32 phys_id = le32_to_cpu(cap_resp->phys_id); 1471 u32 number = le32_to_cpu(cap_resp->number); 1472 u16 cap = le16_to_cpu(cap_resp->cap); 1473 1474 switch (cap) { 1475 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1476 caps->valid_functions = number; 1477 ice_debug(hw, ICE_DBG_INIT, 1478 "HW caps: Valid Functions = %d\n", 1479 caps->valid_functions); 1480 break; 1481 case ICE_AQC_CAPS_SRIOV: 1482 caps->sr_iov_1_1 = (number == 1); 1483 ice_debug(hw, ICE_DBG_INIT, 1484 "HW caps: SR-IOV = %d\n", caps->sr_iov_1_1); 1485 break; 1486 case ICE_AQC_CAPS_VF: 1487 if (dev_p) { 1488 dev_p->num_vfs_exposed = number; 1489 ice_debug(hw, ICE_DBG_INIT, 1490 "HW caps: VFs exposed = %d\n", 1491 dev_p->num_vfs_exposed); 1492 } else if (func_p) { 1493 func_p->num_allocd_vfs = number; 1494 func_p->vf_base_id = logical_id; 1495 ice_debug(hw, ICE_DBG_INIT, 1496 "HW caps: VFs allocated = %d\n", 1497 func_p->num_allocd_vfs); 1498 ice_debug(hw, ICE_DBG_INIT, 1499 "HW caps: VF base_id = %d\n", 1500 func_p->vf_base_id); 1501 } 1502 break; 1503 case ICE_AQC_CAPS_VSI: 1504 if (dev_p) { 1505 dev_p->num_vsi_allocd_to_host = number; 1506 ice_debug(hw, ICE_DBG_INIT, 1507 "HW caps: Dev.VSI cnt = %d\n", 1508 dev_p->num_vsi_allocd_to_host); 1509 } else if (func_p) { 1510 func_p->guar_num_vsi = 1511 ice_get_num_per_func(hw, ICE_MAX_VSI); 1512 ice_debug(hw, ICE_DBG_INIT, 1513 "HW caps: Func.VSI cnt = %d\n", 1514 number); 1515 } 1516 break; 1517 case ICE_AQC_CAPS_RSS: 1518 caps->rss_table_size = number; 1519 caps->rss_table_entry_width = logical_id; 1520 ice_debug(hw, ICE_DBG_INIT, 1521 "HW caps: RSS table size = %d\n", 1522 caps->rss_table_size); 1523 ice_debug(hw, ICE_DBG_INIT, 1524 "HW caps: RSS table width = %d\n", 1525 caps->rss_table_entry_width); 1526 break; 1527 case ICE_AQC_CAPS_RXQS: 1528 caps->num_rxq = number; 1529 caps->rxq_first_id = phys_id; 1530 ice_debug(hw, ICE_DBG_INIT, 1531 "HW caps: Num Rx Qs = %d\n", caps->num_rxq); 1532 ice_debug(hw, ICE_DBG_INIT, 1533 "HW caps: Rx first queue ID = %d\n", 1534 caps->rxq_first_id); 1535 break; 1536 case ICE_AQC_CAPS_TXQS: 1537 caps->num_txq = number; 1538 caps->txq_first_id = phys_id; 1539 ice_debug(hw, ICE_DBG_INIT, 1540 "HW caps: Num Tx Qs = %d\n", caps->num_txq); 1541 ice_debug(hw, ICE_DBG_INIT, 1542 "HW caps: Tx first queue ID = %d\n", 1543 caps->txq_first_id); 1544 break; 1545 case ICE_AQC_CAPS_MSIX: 1546 caps->num_msix_vectors = number; 1547 caps->msix_vector_first_id = phys_id; 1548 ice_debug(hw, ICE_DBG_INIT, 1549 "HW caps: MSIX vector count = %d\n", 1550 caps->num_msix_vectors); 1551 ice_debug(hw, ICE_DBG_INIT, 1552 "HW caps: MSIX first vector index = %d\n", 1553 caps->msix_vector_first_id); 1554 break; 1555 case ICE_AQC_CAPS_MAX_MTU: 1556 caps->max_mtu = number; 1557 if (dev_p) 1558 ice_debug(hw, ICE_DBG_INIT, 1559 "HW caps: Dev.MaxMTU = %d\n", 1560 caps->max_mtu); 1561 else if (func_p) 1562 ice_debug(hw, ICE_DBG_INIT, 1563 "HW caps: func.MaxMTU = %d\n", 1564 caps->max_mtu); 1565 break; 1566 default: 1567 ice_debug(hw, ICE_DBG_INIT, 1568 "HW caps: Unknown capability[%d]: 0x%x\n", i, 1569 cap); 1570 break; 1571 } 1572 } 1573 } 1574 1575 /** 1576 * ice_aq_discover_caps - query function/device capabilities 1577 * @hw: pointer to the HW struct 1578 * @buf: a virtual buffer to hold the capabilities 1579 * @buf_size: Size of the virtual buffer 1580 * @cap_count: cap count needed if AQ err==ENOMEM 1581 * @opc: capabilities type to discover - pass in the command opcode 1582 * @cd: pointer to command details structure or NULL 1583 * 1584 * Get the function(0x000a)/device(0x000b) capabilities description from 1585 * the firmware. 1586 */ 1587 static enum ice_status 1588 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 1589 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1590 { 1591 struct ice_aqc_list_caps *cmd; 1592 struct ice_aq_desc desc; 1593 enum ice_status status; 1594 1595 cmd = &desc.params.get_cap; 1596 1597 if (opc != ice_aqc_opc_list_func_caps && 1598 opc != ice_aqc_opc_list_dev_caps) 1599 return ICE_ERR_PARAM; 1600 1601 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1602 1603 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1604 if (!status) 1605 ice_parse_caps(hw, buf, le32_to_cpu(cmd->count), opc); 1606 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM) 1607 *cap_count = le32_to_cpu(cmd->count); 1608 return status; 1609 } 1610 1611 /** 1612 * ice_discover_caps - get info about the HW 1613 * @hw: pointer to the hardware structure 1614 * @opc: capabilities type to discover - pass in the command opcode 1615 */ 1616 static enum ice_status 1617 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc) 1618 { 1619 enum ice_status status; 1620 u32 cap_count; 1621 u16 cbuf_len; 1622 u8 retries; 1623 1624 /* The driver doesn't know how many capabilities the device will return 1625 * so the buffer size required isn't known ahead of time. The driver 1626 * starts with cbuf_len and if this turns out to be insufficient, the 1627 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs. 1628 * The driver then allocates the buffer based on the count and retries 1629 * the operation. So it follows that the retry count is 2. 1630 */ 1631 #define ICE_GET_CAP_BUF_COUNT 40 1632 #define ICE_GET_CAP_RETRY_COUNT 2 1633 1634 cap_count = ICE_GET_CAP_BUF_COUNT; 1635 retries = ICE_GET_CAP_RETRY_COUNT; 1636 1637 do { 1638 void *cbuf; 1639 1640 cbuf_len = (u16)(cap_count * 1641 sizeof(struct ice_aqc_list_caps_elem)); 1642 cbuf = devm_kzalloc(ice_hw_to_dev(hw), cbuf_len, GFP_KERNEL); 1643 if (!cbuf) 1644 return ICE_ERR_NO_MEMORY; 1645 1646 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count, 1647 opc, NULL); 1648 devm_kfree(ice_hw_to_dev(hw), cbuf); 1649 1650 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM) 1651 break; 1652 1653 /* If ENOMEM is returned, try again with bigger buffer */ 1654 } while (--retries); 1655 1656 return status; 1657 } 1658 1659 /** 1660 * ice_get_caps - get info about the HW 1661 * @hw: pointer to the hardware structure 1662 */ 1663 enum ice_status ice_get_caps(struct ice_hw *hw) 1664 { 1665 enum ice_status status; 1666 1667 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps); 1668 if (!status) 1669 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps); 1670 1671 return status; 1672 } 1673 1674 /** 1675 * ice_aq_manage_mac_write - manage MAC address write command 1676 * @hw: pointer to the HW struct 1677 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 1678 * @flags: flags to control write behavior 1679 * @cd: pointer to command details structure or NULL 1680 * 1681 * This function is used to write MAC address to the NVM (0x0108). 1682 */ 1683 enum ice_status 1684 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 1685 struct ice_sq_cd *cd) 1686 { 1687 struct ice_aqc_manage_mac_write *cmd; 1688 struct ice_aq_desc desc; 1689 1690 cmd = &desc.params.mac_write; 1691 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 1692 1693 cmd->flags = flags; 1694 1695 /* Prep values for flags, sah, sal */ 1696 cmd->sah = htons(*((const u16 *)mac_addr)); 1697 cmd->sal = htonl(*((const u32 *)(mac_addr + 2))); 1698 1699 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1700 } 1701 1702 /** 1703 * ice_aq_clear_pxe_mode 1704 * @hw: pointer to the HW struct 1705 * 1706 * Tell the firmware that the driver is taking over from PXE (0x0110). 1707 */ 1708 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 1709 { 1710 struct ice_aq_desc desc; 1711 1712 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 1713 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 1714 1715 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1716 } 1717 1718 /** 1719 * ice_clear_pxe_mode - clear pxe operations mode 1720 * @hw: pointer to the HW struct 1721 * 1722 * Make sure all PXE mode settings are cleared, including things 1723 * like descriptor fetch/write-back mode. 1724 */ 1725 void ice_clear_pxe_mode(struct ice_hw *hw) 1726 { 1727 if (ice_check_sq_alive(hw, &hw->adminq)) 1728 ice_aq_clear_pxe_mode(hw); 1729 } 1730 1731 /** 1732 * ice_get_link_speed_based_on_phy_type - returns link speed 1733 * @phy_type_low: lower part of phy_type 1734 * @phy_type_high: higher part of phy_type 1735 * 1736 * This helper function will convert an entry in PHY type structure 1737 * [phy_type_low, phy_type_high] to its corresponding link speed. 1738 * Note: In the structure of [phy_type_low, phy_type_high], there should 1739 * be one bit set, as this function will convert one PHY type to its 1740 * speed. 1741 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 1742 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 1743 */ 1744 static u16 1745 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 1746 { 1747 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 1748 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 1749 1750 switch (phy_type_low) { 1751 case ICE_PHY_TYPE_LOW_100BASE_TX: 1752 case ICE_PHY_TYPE_LOW_100M_SGMII: 1753 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 1754 break; 1755 case ICE_PHY_TYPE_LOW_1000BASE_T: 1756 case ICE_PHY_TYPE_LOW_1000BASE_SX: 1757 case ICE_PHY_TYPE_LOW_1000BASE_LX: 1758 case ICE_PHY_TYPE_LOW_1000BASE_KX: 1759 case ICE_PHY_TYPE_LOW_1G_SGMII: 1760 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 1761 break; 1762 case ICE_PHY_TYPE_LOW_2500BASE_T: 1763 case ICE_PHY_TYPE_LOW_2500BASE_X: 1764 case ICE_PHY_TYPE_LOW_2500BASE_KX: 1765 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 1766 break; 1767 case ICE_PHY_TYPE_LOW_5GBASE_T: 1768 case ICE_PHY_TYPE_LOW_5GBASE_KR: 1769 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 1770 break; 1771 case ICE_PHY_TYPE_LOW_10GBASE_T: 1772 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 1773 case ICE_PHY_TYPE_LOW_10GBASE_SR: 1774 case ICE_PHY_TYPE_LOW_10GBASE_LR: 1775 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 1776 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 1777 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 1778 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 1779 break; 1780 case ICE_PHY_TYPE_LOW_25GBASE_T: 1781 case ICE_PHY_TYPE_LOW_25GBASE_CR: 1782 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 1783 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 1784 case ICE_PHY_TYPE_LOW_25GBASE_SR: 1785 case ICE_PHY_TYPE_LOW_25GBASE_LR: 1786 case ICE_PHY_TYPE_LOW_25GBASE_KR: 1787 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 1788 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 1789 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 1790 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 1791 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 1792 break; 1793 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 1794 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 1795 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 1796 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 1797 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 1798 case ICE_PHY_TYPE_LOW_40G_XLAUI: 1799 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 1800 break; 1801 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 1802 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 1803 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 1804 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 1805 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 1806 case ICE_PHY_TYPE_LOW_50G_LAUI2: 1807 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 1808 case ICE_PHY_TYPE_LOW_50G_AUI2: 1809 case ICE_PHY_TYPE_LOW_50GBASE_CP: 1810 case ICE_PHY_TYPE_LOW_50GBASE_SR: 1811 case ICE_PHY_TYPE_LOW_50GBASE_FR: 1812 case ICE_PHY_TYPE_LOW_50GBASE_LR: 1813 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 1814 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 1815 case ICE_PHY_TYPE_LOW_50G_AUI1: 1816 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 1817 break; 1818 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 1819 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 1820 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 1821 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 1822 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 1823 case ICE_PHY_TYPE_LOW_100G_CAUI4: 1824 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 1825 case ICE_PHY_TYPE_LOW_100G_AUI4: 1826 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 1827 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 1828 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 1829 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 1830 case ICE_PHY_TYPE_LOW_100GBASE_DR: 1831 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 1832 break; 1833 default: 1834 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 1835 break; 1836 } 1837 1838 switch (phy_type_high) { 1839 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 1840 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 1841 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 1842 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 1843 case ICE_PHY_TYPE_HIGH_100G_AUI2: 1844 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 1845 break; 1846 default: 1847 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 1848 break; 1849 } 1850 1851 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 1852 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 1853 return ICE_AQ_LINK_SPEED_UNKNOWN; 1854 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 1855 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 1856 return ICE_AQ_LINK_SPEED_UNKNOWN; 1857 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 1858 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 1859 return speed_phy_type_low; 1860 else 1861 return speed_phy_type_high; 1862 } 1863 1864 /** 1865 * ice_update_phy_type 1866 * @phy_type_low: pointer to the lower part of phy_type 1867 * @phy_type_high: pointer to the higher part of phy_type 1868 * @link_speeds_bitmap: targeted link speeds bitmap 1869 * 1870 * Note: For the link_speeds_bitmap structure, you can check it at 1871 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 1872 * link_speeds_bitmap include multiple speeds. 1873 * 1874 * Each entry in this [phy_type_low, phy_type_high] structure will 1875 * present a certain link speed. This helper function will turn on bits 1876 * in [phy_type_low, phy_type_high] structure based on the value of 1877 * link_speeds_bitmap input parameter. 1878 */ 1879 void 1880 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 1881 u16 link_speeds_bitmap) 1882 { 1883 u64 pt_high; 1884 u64 pt_low; 1885 int index; 1886 u16 speed; 1887 1888 /* We first check with low part of phy_type */ 1889 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 1890 pt_low = BIT_ULL(index); 1891 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 1892 1893 if (link_speeds_bitmap & speed) 1894 *phy_type_low |= BIT_ULL(index); 1895 } 1896 1897 /* We then check with high part of phy_type */ 1898 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 1899 pt_high = BIT_ULL(index); 1900 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 1901 1902 if (link_speeds_bitmap & speed) 1903 *phy_type_high |= BIT_ULL(index); 1904 } 1905 } 1906 1907 /** 1908 * ice_aq_set_phy_cfg 1909 * @hw: pointer to the HW struct 1910 * @lport: logical port number 1911 * @cfg: structure with PHY configuration data to be set 1912 * @cd: pointer to command details structure or NULL 1913 * 1914 * Set the various PHY configuration parameters supported on the Port. 1915 * One or more of the Set PHY config parameters may be ignored in an MFP 1916 * mode as the PF may not have the privilege to set some of the PHY Config 1917 * parameters. This status will be indicated by the command response (0x0601). 1918 */ 1919 enum ice_status 1920 ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport, 1921 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 1922 { 1923 struct ice_aq_desc desc; 1924 1925 if (!cfg) 1926 return ICE_ERR_PARAM; 1927 1928 /* Ensure that only valid bits of cfg->caps can be turned on. */ 1929 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 1930 ice_debug(hw, ICE_DBG_PHY, 1931 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 1932 cfg->caps); 1933 1934 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 1935 } 1936 1937 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 1938 desc.params.set_phy.lport_num = lport; 1939 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1940 1941 return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 1942 } 1943 1944 /** 1945 * ice_update_link_info - update status of the HW network link 1946 * @pi: port info structure of the interested logical port 1947 */ 1948 enum ice_status ice_update_link_info(struct ice_port_info *pi) 1949 { 1950 struct ice_aqc_get_phy_caps_data *pcaps; 1951 struct ice_phy_info *phy_info; 1952 enum ice_status status; 1953 struct ice_hw *hw; 1954 1955 if (!pi) 1956 return ICE_ERR_PARAM; 1957 1958 hw = pi->hw; 1959 1960 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 1961 if (!pcaps) 1962 return ICE_ERR_NO_MEMORY; 1963 1964 phy_info = &pi->phy; 1965 status = ice_aq_get_link_info(pi, true, NULL, NULL); 1966 if (status) 1967 goto out; 1968 1969 if (phy_info->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) { 1970 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, 1971 pcaps, NULL); 1972 if (status) 1973 goto out; 1974 1975 memcpy(phy_info->link_info.module_type, &pcaps->module_type, 1976 sizeof(phy_info->link_info.module_type)); 1977 } 1978 out: 1979 devm_kfree(ice_hw_to_dev(hw), pcaps); 1980 return status; 1981 } 1982 1983 /** 1984 * ice_set_fc 1985 * @pi: port information structure 1986 * @aq_failures: pointer to status code, specific to ice_set_fc routine 1987 * @ena_auto_link_update: enable automatic link update 1988 * 1989 * Set the requested flow control mode. 1990 */ 1991 enum ice_status 1992 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 1993 { 1994 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 1995 struct ice_aqc_get_phy_caps_data *pcaps; 1996 enum ice_status status; 1997 u8 pause_mask = 0x0; 1998 struct ice_hw *hw; 1999 2000 if (!pi) 2001 return ICE_ERR_PARAM; 2002 hw = pi->hw; 2003 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE; 2004 2005 switch (pi->fc.req_mode) { 2006 case ICE_FC_FULL: 2007 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2008 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2009 break; 2010 case ICE_FC_RX_PAUSE: 2011 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2012 break; 2013 case ICE_FC_TX_PAUSE: 2014 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2015 break; 2016 default: 2017 break; 2018 } 2019 2020 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 2021 if (!pcaps) 2022 return ICE_ERR_NO_MEMORY; 2023 2024 /* Get the current PHY config */ 2025 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 2026 NULL); 2027 if (status) { 2028 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2029 goto out; 2030 } 2031 2032 /* clear the old pause settings */ 2033 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2034 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2035 2036 /* set the new capabilities */ 2037 cfg.caps |= pause_mask; 2038 2039 /* If the capabilities have changed, then set the new config */ 2040 if (cfg.caps != pcaps->caps) { 2041 int retry_count, retry_max = 10; 2042 2043 /* Auto restart link so settings take effect */ 2044 if (ena_auto_link_update) 2045 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2046 /* Copy over all the old settings */ 2047 cfg.phy_type_high = pcaps->phy_type_high; 2048 cfg.phy_type_low = pcaps->phy_type_low; 2049 cfg.low_power_ctrl = pcaps->low_power_ctrl; 2050 cfg.eee_cap = pcaps->eee_cap; 2051 cfg.eeer_value = pcaps->eeer_value; 2052 cfg.link_fec_opt = pcaps->link_fec_options; 2053 2054 status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL); 2055 if (status) { 2056 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 2057 goto out; 2058 } 2059 2060 /* Update the link info 2061 * It sometimes takes a really long time for link to 2062 * come back from the atomic reset. Thus, we wait a 2063 * little bit. 2064 */ 2065 for (retry_count = 0; retry_count < retry_max; retry_count++) { 2066 status = ice_update_link_info(pi); 2067 2068 if (!status) 2069 break; 2070 2071 mdelay(100); 2072 } 2073 2074 if (status) 2075 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 2076 } 2077 2078 out: 2079 devm_kfree(ice_hw_to_dev(hw), pcaps); 2080 return status; 2081 } 2082 2083 /** 2084 * ice_get_link_status - get status of the HW network link 2085 * @pi: port information structure 2086 * @link_up: pointer to bool (true/false = linkup/linkdown) 2087 * 2088 * Variable link_up is true if link is up, false if link is down. 2089 * The variable link_up is invalid if status is non zero. As a 2090 * result of this call, link status reporting becomes enabled 2091 */ 2092 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 2093 { 2094 struct ice_phy_info *phy_info; 2095 enum ice_status status = 0; 2096 2097 if (!pi || !link_up) 2098 return ICE_ERR_PARAM; 2099 2100 phy_info = &pi->phy; 2101 2102 if (phy_info->get_link_info) { 2103 status = ice_update_link_info(pi); 2104 2105 if (status) 2106 ice_debug(pi->hw, ICE_DBG_LINK, 2107 "get link status error, status = %d\n", 2108 status); 2109 } 2110 2111 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 2112 2113 return status; 2114 } 2115 2116 /** 2117 * ice_aq_set_link_restart_an 2118 * @pi: pointer to the port information structure 2119 * @ena_link: if true: enable link, if false: disable link 2120 * @cd: pointer to command details structure or NULL 2121 * 2122 * Sets up the link and restarts the Auto-Negotiation over the link. 2123 */ 2124 enum ice_status 2125 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 2126 struct ice_sq_cd *cd) 2127 { 2128 struct ice_aqc_restart_an *cmd; 2129 struct ice_aq_desc desc; 2130 2131 cmd = &desc.params.restart_an; 2132 2133 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 2134 2135 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 2136 cmd->lport_num = pi->lport; 2137 if (ena_link) 2138 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 2139 else 2140 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 2141 2142 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 2143 } 2144 2145 /** 2146 * ice_aq_set_event_mask 2147 * @hw: pointer to the HW struct 2148 * @port_num: port number of the physical function 2149 * @mask: event mask to be set 2150 * @cd: pointer to command details structure or NULL 2151 * 2152 * Set event mask (0x0613) 2153 */ 2154 enum ice_status 2155 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 2156 struct ice_sq_cd *cd) 2157 { 2158 struct ice_aqc_set_event_mask *cmd; 2159 struct ice_aq_desc desc; 2160 2161 cmd = &desc.params.set_event_mask; 2162 2163 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 2164 2165 cmd->lport_num = port_num; 2166 2167 cmd->event_mask = cpu_to_le16(mask); 2168 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2169 } 2170 2171 /** 2172 * ice_aq_set_port_id_led 2173 * @pi: pointer to the port information 2174 * @is_orig_mode: is this LED set to original mode (by the net-list) 2175 * @cd: pointer to command details structure or NULL 2176 * 2177 * Set LED value for the given port (0x06e9) 2178 */ 2179 enum ice_status 2180 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 2181 struct ice_sq_cd *cd) 2182 { 2183 struct ice_aqc_set_port_id_led *cmd; 2184 struct ice_hw *hw = pi->hw; 2185 struct ice_aq_desc desc; 2186 2187 cmd = &desc.params.set_port_id_led; 2188 2189 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 2190 2191 if (is_orig_mode) 2192 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 2193 else 2194 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 2195 2196 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2197 } 2198 2199 /** 2200 * __ice_aq_get_set_rss_lut 2201 * @hw: pointer to the hardware structure 2202 * @vsi_id: VSI FW index 2203 * @lut_type: LUT table type 2204 * @lut: pointer to the LUT buffer provided by the caller 2205 * @lut_size: size of the LUT buffer 2206 * @glob_lut_idx: global LUT index 2207 * @set: set true to set the table, false to get the table 2208 * 2209 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 2210 */ 2211 static enum ice_status 2212 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 2213 u16 lut_size, u8 glob_lut_idx, bool set) 2214 { 2215 struct ice_aqc_get_set_rss_lut *cmd_resp; 2216 struct ice_aq_desc desc; 2217 enum ice_status status; 2218 u16 flags = 0; 2219 2220 cmd_resp = &desc.params.get_set_rss_lut; 2221 2222 if (set) { 2223 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 2224 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2225 } else { 2226 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 2227 } 2228 2229 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 2230 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 2231 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 2232 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 2233 2234 switch (lut_type) { 2235 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 2236 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 2237 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 2238 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 2239 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 2240 break; 2241 default: 2242 status = ICE_ERR_PARAM; 2243 goto ice_aq_get_set_rss_lut_exit; 2244 } 2245 2246 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 2247 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 2248 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 2249 2250 if (!set) 2251 goto ice_aq_get_set_rss_lut_send; 2252 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 2253 if (!set) 2254 goto ice_aq_get_set_rss_lut_send; 2255 } else { 2256 goto ice_aq_get_set_rss_lut_send; 2257 } 2258 2259 /* LUT size is only valid for Global and PF table types */ 2260 switch (lut_size) { 2261 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 2262 break; 2263 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 2264 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 2265 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 2266 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 2267 break; 2268 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 2269 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 2270 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 2271 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 2272 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 2273 break; 2274 } 2275 /* fall-through */ 2276 default: 2277 status = ICE_ERR_PARAM; 2278 goto ice_aq_get_set_rss_lut_exit; 2279 } 2280 2281 ice_aq_get_set_rss_lut_send: 2282 cmd_resp->flags = cpu_to_le16(flags); 2283 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 2284 2285 ice_aq_get_set_rss_lut_exit: 2286 return status; 2287 } 2288 2289 /** 2290 * ice_aq_get_rss_lut 2291 * @hw: pointer to the hardware structure 2292 * @vsi_handle: software VSI handle 2293 * @lut_type: LUT table type 2294 * @lut: pointer to the LUT buffer provided by the caller 2295 * @lut_size: size of the LUT buffer 2296 * 2297 * get the RSS lookup table, PF or VSI type 2298 */ 2299 enum ice_status 2300 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 2301 u8 *lut, u16 lut_size) 2302 { 2303 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 2304 return ICE_ERR_PARAM; 2305 2306 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2307 lut_type, lut, lut_size, 0, false); 2308 } 2309 2310 /** 2311 * ice_aq_set_rss_lut 2312 * @hw: pointer to the hardware structure 2313 * @vsi_handle: software VSI handle 2314 * @lut_type: LUT table type 2315 * @lut: pointer to the LUT buffer provided by the caller 2316 * @lut_size: size of the LUT buffer 2317 * 2318 * set the RSS lookup table, PF or VSI type 2319 */ 2320 enum ice_status 2321 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 2322 u8 *lut, u16 lut_size) 2323 { 2324 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 2325 return ICE_ERR_PARAM; 2326 2327 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2328 lut_type, lut, lut_size, 0, true); 2329 } 2330 2331 /** 2332 * __ice_aq_get_set_rss_key 2333 * @hw: pointer to the HW struct 2334 * @vsi_id: VSI FW index 2335 * @key: pointer to key info struct 2336 * @set: set true to set the key, false to get the key 2337 * 2338 * get (0x0B04) or set (0x0B02) the RSS key per VSI 2339 */ 2340 static enum 2341 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 2342 struct ice_aqc_get_set_rss_keys *key, 2343 bool set) 2344 { 2345 struct ice_aqc_get_set_rss_key *cmd_resp; 2346 u16 key_size = sizeof(*key); 2347 struct ice_aq_desc desc; 2348 2349 cmd_resp = &desc.params.get_set_rss_key; 2350 2351 if (set) { 2352 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 2353 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2354 } else { 2355 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 2356 } 2357 2358 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 2359 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 2360 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 2361 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 2362 2363 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 2364 } 2365 2366 /** 2367 * ice_aq_get_rss_key 2368 * @hw: pointer to the HW struct 2369 * @vsi_handle: software VSI handle 2370 * @key: pointer to key info struct 2371 * 2372 * get the RSS key per VSI 2373 */ 2374 enum ice_status 2375 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 2376 struct ice_aqc_get_set_rss_keys *key) 2377 { 2378 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 2379 return ICE_ERR_PARAM; 2380 2381 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2382 key, false); 2383 } 2384 2385 /** 2386 * ice_aq_set_rss_key 2387 * @hw: pointer to the HW struct 2388 * @vsi_handle: software VSI handle 2389 * @keys: pointer to key info struct 2390 * 2391 * set the RSS key per VSI 2392 */ 2393 enum ice_status 2394 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 2395 struct ice_aqc_get_set_rss_keys *keys) 2396 { 2397 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 2398 return ICE_ERR_PARAM; 2399 2400 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2401 keys, true); 2402 } 2403 2404 /** 2405 * ice_aq_add_lan_txq 2406 * @hw: pointer to the hardware structure 2407 * @num_qgrps: Number of added queue groups 2408 * @qg_list: list of queue groups to be added 2409 * @buf_size: size of buffer for indirect command 2410 * @cd: pointer to command details structure or NULL 2411 * 2412 * Add Tx LAN queue (0x0C30) 2413 * 2414 * NOTE: 2415 * Prior to calling add Tx LAN queue: 2416 * Initialize the following as part of the Tx queue context: 2417 * Completion queue ID if the queue uses Completion queue, Quanta profile, 2418 * Cache profile and Packet shaper profile. 2419 * 2420 * After add Tx LAN queue AQ command is completed: 2421 * Interrupts should be associated with specific queues, 2422 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 2423 * flow. 2424 */ 2425 static enum ice_status 2426 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 2427 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 2428 struct ice_sq_cd *cd) 2429 { 2430 u16 i, sum_header_size, sum_q_size = 0; 2431 struct ice_aqc_add_tx_qgrp *list; 2432 struct ice_aqc_add_txqs *cmd; 2433 struct ice_aq_desc desc; 2434 2435 cmd = &desc.params.add_txqs; 2436 2437 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 2438 2439 if (!qg_list) 2440 return ICE_ERR_PARAM; 2441 2442 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 2443 return ICE_ERR_PARAM; 2444 2445 sum_header_size = num_qgrps * 2446 (sizeof(*qg_list) - sizeof(*qg_list->txqs)); 2447 2448 list = qg_list; 2449 for (i = 0; i < num_qgrps; i++) { 2450 struct ice_aqc_add_txqs_perq *q = list->txqs; 2451 2452 sum_q_size += list->num_txqs * sizeof(*q); 2453 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs); 2454 } 2455 2456 if (buf_size != (sum_header_size + sum_q_size)) 2457 return ICE_ERR_PARAM; 2458 2459 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2460 2461 cmd->num_qgrps = num_qgrps; 2462 2463 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 2464 } 2465 2466 /** 2467 * ice_aq_dis_lan_txq 2468 * @hw: pointer to the hardware structure 2469 * @num_qgrps: number of groups in the list 2470 * @qg_list: the list of groups to disable 2471 * @buf_size: the total size of the qg_list buffer in bytes 2472 * @rst_src: if called due to reset, specifies the reset source 2473 * @vmvf_num: the relative VM or VF number that is undergoing the reset 2474 * @cd: pointer to command details structure or NULL 2475 * 2476 * Disable LAN Tx queue (0x0C31) 2477 */ 2478 static enum ice_status 2479 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 2480 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 2481 enum ice_disq_rst_src rst_src, u16 vmvf_num, 2482 struct ice_sq_cd *cd) 2483 { 2484 struct ice_aqc_dis_txqs *cmd; 2485 struct ice_aq_desc desc; 2486 enum ice_status status; 2487 u16 i, sz = 0; 2488 2489 cmd = &desc.params.dis_txqs; 2490 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 2491 2492 /* qg_list can be NULL only in VM/VF reset flow */ 2493 if (!qg_list && !rst_src) 2494 return ICE_ERR_PARAM; 2495 2496 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 2497 return ICE_ERR_PARAM; 2498 2499 cmd->num_entries = num_qgrps; 2500 2501 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 2502 ICE_AQC_Q_DIS_TIMEOUT_M); 2503 2504 switch (rst_src) { 2505 case ICE_VM_RESET: 2506 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 2507 cmd->vmvf_and_timeout |= 2508 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 2509 break; 2510 case ICE_VF_RESET: 2511 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 2512 /* In this case, FW expects vmvf_num to be absolute VF ID */ 2513 cmd->vmvf_and_timeout |= 2514 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 2515 ICE_AQC_Q_DIS_VMVF_NUM_M); 2516 break; 2517 case ICE_NO_RESET: 2518 default: 2519 break; 2520 } 2521 2522 /* flush pipe on time out */ 2523 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 2524 /* If no queue group info, we are in a reset flow. Issue the AQ */ 2525 if (!qg_list) 2526 goto do_aq; 2527 2528 /* set RD bit to indicate that command buffer is provided by the driver 2529 * and it needs to be read by the firmware 2530 */ 2531 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2532 2533 for (i = 0; i < num_qgrps; ++i) { 2534 /* Calculate the size taken up by the queue IDs in this group */ 2535 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id); 2536 2537 /* Add the size of the group header */ 2538 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id); 2539 2540 /* If the num of queues is even, add 2 bytes of padding */ 2541 if ((qg_list[i].num_qs % 2) == 0) 2542 sz += 2; 2543 } 2544 2545 if (buf_size != sz) 2546 return ICE_ERR_PARAM; 2547 2548 do_aq: 2549 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 2550 if (status) { 2551 if (!qg_list) 2552 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 2553 vmvf_num, hw->adminq.sq_last_status); 2554 else 2555 ice_debug(hw, ICE_DBG_SCHED, "disable Q %d failed %d\n", 2556 le16_to_cpu(qg_list[0].q_id[0]), 2557 hw->adminq.sq_last_status); 2558 } 2559 return status; 2560 } 2561 2562 /* End of FW Admin Queue command wrappers */ 2563 2564 /** 2565 * ice_write_byte - write a byte to a packed context structure 2566 * @src_ctx: the context structure to read from 2567 * @dest_ctx: the context to be written to 2568 * @ce_info: a description of the struct to be filled 2569 */ 2570 static void 2571 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2572 { 2573 u8 src_byte, dest_byte, mask; 2574 u8 *from, *dest; 2575 u16 shift_width; 2576 2577 /* copy from the next struct field */ 2578 from = src_ctx + ce_info->offset; 2579 2580 /* prepare the bits and mask */ 2581 shift_width = ce_info->lsb % 8; 2582 mask = (u8)(BIT(ce_info->width) - 1); 2583 2584 src_byte = *from; 2585 src_byte &= mask; 2586 2587 /* shift to correct alignment */ 2588 mask <<= shift_width; 2589 src_byte <<= shift_width; 2590 2591 /* get the current bits from the target bit string */ 2592 dest = dest_ctx + (ce_info->lsb / 8); 2593 2594 memcpy(&dest_byte, dest, sizeof(dest_byte)); 2595 2596 dest_byte &= ~mask; /* get the bits not changing */ 2597 dest_byte |= src_byte; /* add in the new bits */ 2598 2599 /* put it all back */ 2600 memcpy(dest, &dest_byte, sizeof(dest_byte)); 2601 } 2602 2603 /** 2604 * ice_write_word - write a word to a packed context structure 2605 * @src_ctx: the context structure to read from 2606 * @dest_ctx: the context to be written to 2607 * @ce_info: a description of the struct to be filled 2608 */ 2609 static void 2610 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2611 { 2612 u16 src_word, mask; 2613 __le16 dest_word; 2614 u8 *from, *dest; 2615 u16 shift_width; 2616 2617 /* copy from the next struct field */ 2618 from = src_ctx + ce_info->offset; 2619 2620 /* prepare the bits and mask */ 2621 shift_width = ce_info->lsb % 8; 2622 mask = BIT(ce_info->width) - 1; 2623 2624 /* don't swizzle the bits until after the mask because the mask bits 2625 * will be in a different bit position on big endian machines 2626 */ 2627 src_word = *(u16 *)from; 2628 src_word &= mask; 2629 2630 /* shift to correct alignment */ 2631 mask <<= shift_width; 2632 src_word <<= shift_width; 2633 2634 /* get the current bits from the target bit string */ 2635 dest = dest_ctx + (ce_info->lsb / 8); 2636 2637 memcpy(&dest_word, dest, sizeof(dest_word)); 2638 2639 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 2640 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 2641 2642 /* put it all back */ 2643 memcpy(dest, &dest_word, sizeof(dest_word)); 2644 } 2645 2646 /** 2647 * ice_write_dword - write a dword to a packed context structure 2648 * @src_ctx: the context structure to read from 2649 * @dest_ctx: the context to be written to 2650 * @ce_info: a description of the struct to be filled 2651 */ 2652 static void 2653 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2654 { 2655 u32 src_dword, mask; 2656 __le32 dest_dword; 2657 u8 *from, *dest; 2658 u16 shift_width; 2659 2660 /* copy from the next struct field */ 2661 from = src_ctx + ce_info->offset; 2662 2663 /* prepare the bits and mask */ 2664 shift_width = ce_info->lsb % 8; 2665 2666 /* if the field width is exactly 32 on an x86 machine, then the shift 2667 * operation will not work because the SHL instructions count is masked 2668 * to 5 bits so the shift will do nothing 2669 */ 2670 if (ce_info->width < 32) 2671 mask = BIT(ce_info->width) - 1; 2672 else 2673 mask = (u32)~0; 2674 2675 /* don't swizzle the bits until after the mask because the mask bits 2676 * will be in a different bit position on big endian machines 2677 */ 2678 src_dword = *(u32 *)from; 2679 src_dword &= mask; 2680 2681 /* shift to correct alignment */ 2682 mask <<= shift_width; 2683 src_dword <<= shift_width; 2684 2685 /* get the current bits from the target bit string */ 2686 dest = dest_ctx + (ce_info->lsb / 8); 2687 2688 memcpy(&dest_dword, dest, sizeof(dest_dword)); 2689 2690 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 2691 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 2692 2693 /* put it all back */ 2694 memcpy(dest, &dest_dword, sizeof(dest_dword)); 2695 } 2696 2697 /** 2698 * ice_write_qword - write a qword to a packed context structure 2699 * @src_ctx: the context structure to read from 2700 * @dest_ctx: the context to be written to 2701 * @ce_info: a description of the struct to be filled 2702 */ 2703 static void 2704 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2705 { 2706 u64 src_qword, mask; 2707 __le64 dest_qword; 2708 u8 *from, *dest; 2709 u16 shift_width; 2710 2711 /* copy from the next struct field */ 2712 from = src_ctx + ce_info->offset; 2713 2714 /* prepare the bits and mask */ 2715 shift_width = ce_info->lsb % 8; 2716 2717 /* if the field width is exactly 64 on an x86 machine, then the shift 2718 * operation will not work because the SHL instructions count is masked 2719 * to 6 bits so the shift will do nothing 2720 */ 2721 if (ce_info->width < 64) 2722 mask = BIT_ULL(ce_info->width) - 1; 2723 else 2724 mask = (u64)~0; 2725 2726 /* don't swizzle the bits until after the mask because the mask bits 2727 * will be in a different bit position on big endian machines 2728 */ 2729 src_qword = *(u64 *)from; 2730 src_qword &= mask; 2731 2732 /* shift to correct alignment */ 2733 mask <<= shift_width; 2734 src_qword <<= shift_width; 2735 2736 /* get the current bits from the target bit string */ 2737 dest = dest_ctx + (ce_info->lsb / 8); 2738 2739 memcpy(&dest_qword, dest, sizeof(dest_qword)); 2740 2741 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 2742 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 2743 2744 /* put it all back */ 2745 memcpy(dest, &dest_qword, sizeof(dest_qword)); 2746 } 2747 2748 /** 2749 * ice_set_ctx - set context bits in packed structure 2750 * @src_ctx: pointer to a generic non-packed context structure 2751 * @dest_ctx: pointer to memory for the packed structure 2752 * @ce_info: a description of the structure to be transformed 2753 */ 2754 enum ice_status 2755 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2756 { 2757 int f; 2758 2759 for (f = 0; ce_info[f].width; f++) { 2760 /* We have to deal with each element of the FW response 2761 * using the correct size so that we are correct regardless 2762 * of the endianness of the machine. 2763 */ 2764 switch (ce_info[f].size_of) { 2765 case sizeof(u8): 2766 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 2767 break; 2768 case sizeof(u16): 2769 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 2770 break; 2771 case sizeof(u32): 2772 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 2773 break; 2774 case sizeof(u64): 2775 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 2776 break; 2777 default: 2778 return ICE_ERR_INVAL_SIZE; 2779 } 2780 } 2781 2782 return 0; 2783 } 2784 2785 /** 2786 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 2787 * @hw: pointer to the HW struct 2788 * @vsi_handle: software VSI handle 2789 * @tc: TC number 2790 * @q_handle: software queue handle 2791 */ 2792 static struct ice_q_ctx * 2793 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 2794 { 2795 struct ice_vsi_ctx *vsi; 2796 struct ice_q_ctx *q_ctx; 2797 2798 vsi = ice_get_vsi_ctx(hw, vsi_handle); 2799 if (!vsi) 2800 return NULL; 2801 if (q_handle >= vsi->num_lan_q_entries[tc]) 2802 return NULL; 2803 if (!vsi->lan_q_ctx[tc]) 2804 return NULL; 2805 q_ctx = vsi->lan_q_ctx[tc]; 2806 return &q_ctx[q_handle]; 2807 } 2808 2809 /** 2810 * ice_ena_vsi_txq 2811 * @pi: port information structure 2812 * @vsi_handle: software VSI handle 2813 * @tc: TC number 2814 * @q_handle: software queue handle 2815 * @num_qgrps: Number of added queue groups 2816 * @buf: list of queue groups to be added 2817 * @buf_size: size of buffer for indirect command 2818 * @cd: pointer to command details structure or NULL 2819 * 2820 * This function adds one LAN queue 2821 */ 2822 enum ice_status 2823 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 2824 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 2825 struct ice_sq_cd *cd) 2826 { 2827 struct ice_aqc_txsched_elem_data node = { 0 }; 2828 struct ice_sched_node *parent; 2829 struct ice_q_ctx *q_ctx; 2830 enum ice_status status; 2831 struct ice_hw *hw; 2832 2833 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 2834 return ICE_ERR_CFG; 2835 2836 if (num_qgrps > 1 || buf->num_txqs > 1) 2837 return ICE_ERR_MAX_LIMIT; 2838 2839 hw = pi->hw; 2840 2841 if (!ice_is_vsi_valid(hw, vsi_handle)) 2842 return ICE_ERR_PARAM; 2843 2844 mutex_lock(&pi->sched_lock); 2845 2846 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 2847 if (!q_ctx) { 2848 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 2849 q_handle); 2850 status = ICE_ERR_PARAM; 2851 goto ena_txq_exit; 2852 } 2853 2854 /* find a parent node */ 2855 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 2856 ICE_SCHED_NODE_OWNER_LAN); 2857 if (!parent) { 2858 status = ICE_ERR_PARAM; 2859 goto ena_txq_exit; 2860 } 2861 2862 buf->parent_teid = parent->info.node_teid; 2863 node.parent_teid = parent->info.node_teid; 2864 /* Mark that the values in the "generic" section as valid. The default 2865 * value in the "generic" section is zero. This means that : 2866 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 2867 * - 0 priority among siblings, indicated by Bit 1-3. 2868 * - WFQ, indicated by Bit 4. 2869 * - 0 Adjustment value is used in PSM credit update flow, indicated by 2870 * Bit 5-6. 2871 * - Bit 7 is reserved. 2872 * Without setting the generic section as valid in valid_sections, the 2873 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 2874 */ 2875 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC; 2876 2877 /* add the LAN queue */ 2878 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 2879 if (status) { 2880 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 2881 le16_to_cpu(buf->txqs[0].txq_id), 2882 hw->adminq.sq_last_status); 2883 goto ena_txq_exit; 2884 } 2885 2886 node.node_teid = buf->txqs[0].q_teid; 2887 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 2888 q_ctx->q_handle = q_handle; 2889 2890 /* add a leaf node into schduler tree queue layer */ 2891 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 2892 2893 ena_txq_exit: 2894 mutex_unlock(&pi->sched_lock); 2895 return status; 2896 } 2897 2898 /** 2899 * ice_dis_vsi_txq 2900 * @pi: port information structure 2901 * @vsi_handle: software VSI handle 2902 * @tc: TC number 2903 * @num_queues: number of queues 2904 * @q_handles: pointer to software queue handle array 2905 * @q_ids: pointer to the q_id array 2906 * @q_teids: pointer to queue node teids 2907 * @rst_src: if called due to reset, specifies the reset source 2908 * @vmvf_num: the relative VM or VF number that is undergoing the reset 2909 * @cd: pointer to command details structure or NULL 2910 * 2911 * This function removes queues and their corresponding nodes in SW DB 2912 */ 2913 enum ice_status 2914 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 2915 u16 *q_handles, u16 *q_ids, u32 *q_teids, 2916 enum ice_disq_rst_src rst_src, u16 vmvf_num, 2917 struct ice_sq_cd *cd) 2918 { 2919 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 2920 struct ice_aqc_dis_txq_item qg_list; 2921 struct ice_q_ctx *q_ctx; 2922 u16 i; 2923 2924 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 2925 return ICE_ERR_CFG; 2926 2927 2928 if (!num_queues) { 2929 /* if queue is disabled already yet the disable queue command 2930 * has to be sent to complete the VF reset, then call 2931 * ice_aq_dis_lan_txq without any queue information 2932 */ 2933 if (rst_src) 2934 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src, 2935 vmvf_num, NULL); 2936 return ICE_ERR_CFG; 2937 } 2938 2939 mutex_lock(&pi->sched_lock); 2940 2941 for (i = 0; i < num_queues; i++) { 2942 struct ice_sched_node *node; 2943 2944 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 2945 if (!node) 2946 continue; 2947 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]); 2948 if (!q_ctx) { 2949 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 2950 q_handles[i]); 2951 continue; 2952 } 2953 if (q_ctx->q_handle != q_handles[i]) { 2954 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 2955 q_ctx->q_handle, q_handles[i]); 2956 continue; 2957 } 2958 qg_list.parent_teid = node->info.parent_teid; 2959 qg_list.num_qs = 1; 2960 qg_list.q_id[0] = cpu_to_le16(q_ids[i]); 2961 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list, 2962 sizeof(qg_list), rst_src, vmvf_num, 2963 cd); 2964 2965 if (status) 2966 break; 2967 ice_free_sched_node(pi, node); 2968 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 2969 } 2970 mutex_unlock(&pi->sched_lock); 2971 return status; 2972 } 2973 2974 /** 2975 * ice_cfg_vsi_qs - configure the new/existing VSI queues 2976 * @pi: port information structure 2977 * @vsi_handle: software VSI handle 2978 * @tc_bitmap: TC bitmap 2979 * @maxqs: max queues array per TC 2980 * @owner: LAN or RDMA 2981 * 2982 * This function adds/updates the VSI queues per TC. 2983 */ 2984 static enum ice_status 2985 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 2986 u16 *maxqs, u8 owner) 2987 { 2988 enum ice_status status = 0; 2989 u8 i; 2990 2991 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 2992 return ICE_ERR_CFG; 2993 2994 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 2995 return ICE_ERR_PARAM; 2996 2997 mutex_lock(&pi->sched_lock); 2998 2999 ice_for_each_traffic_class(i) { 3000 /* configuration is possible only if TC node is present */ 3001 if (!ice_sched_get_tc_node(pi, i)) 3002 continue; 3003 3004 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 3005 ice_is_tc_ena(tc_bitmap, i)); 3006 if (status) 3007 break; 3008 } 3009 3010 mutex_unlock(&pi->sched_lock); 3011 return status; 3012 } 3013 3014 /** 3015 * ice_cfg_vsi_lan - configure VSI LAN queues 3016 * @pi: port information structure 3017 * @vsi_handle: software VSI handle 3018 * @tc_bitmap: TC bitmap 3019 * @max_lanqs: max LAN queues array per TC 3020 * 3021 * This function adds/updates the VSI LAN queues per TC. 3022 */ 3023 enum ice_status 3024 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 3025 u16 *max_lanqs) 3026 { 3027 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 3028 ICE_SCHED_NODE_OWNER_LAN); 3029 } 3030 3031 /** 3032 * ice_replay_pre_init - replay pre initialization 3033 * @hw: pointer to the HW struct 3034 * 3035 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 3036 */ 3037 static enum ice_status ice_replay_pre_init(struct ice_hw *hw) 3038 { 3039 struct ice_switch_info *sw = hw->switch_info; 3040 u8 i; 3041 3042 /* Delete old entries from replay filter list head if there is any */ 3043 ice_rm_all_sw_replay_rule_info(hw); 3044 /* In start of replay, move entries into replay_rules list, it 3045 * will allow adding rules entries back to filt_rules list, 3046 * which is operational list. 3047 */ 3048 for (i = 0; i < ICE_SW_LKUP_LAST; i++) 3049 list_replace_init(&sw->recp_list[i].filt_rules, 3050 &sw->recp_list[i].filt_replay_rules); 3051 3052 return 0; 3053 } 3054 3055 /** 3056 * ice_replay_vsi - replay VSI configuration 3057 * @hw: pointer to the HW struct 3058 * @vsi_handle: driver VSI handle 3059 * 3060 * Restore all VSI configuration after reset. It is required to call this 3061 * function with main VSI first. 3062 */ 3063 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 3064 { 3065 enum ice_status status; 3066 3067 if (!ice_is_vsi_valid(hw, vsi_handle)) 3068 return ICE_ERR_PARAM; 3069 3070 /* Replay pre-initialization if there is any */ 3071 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 3072 status = ice_replay_pre_init(hw); 3073 if (status) 3074 return status; 3075 } 3076 3077 /* Replay per VSI all filters */ 3078 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 3079 return status; 3080 } 3081 3082 /** 3083 * ice_replay_post - post replay configuration cleanup 3084 * @hw: pointer to the HW struct 3085 * 3086 * Post replay cleanup. 3087 */ 3088 void ice_replay_post(struct ice_hw *hw) 3089 { 3090 /* Delete old entries from replay filter list head */ 3091 ice_rm_all_sw_replay_rule_info(hw); 3092 } 3093 3094 /** 3095 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 3096 * @hw: ptr to the hardware info 3097 * @hireg: high 32 bit HW register to read from 3098 * @loreg: low 32 bit HW register to read from 3099 * @prev_stat_loaded: bool to specify if previous stats are loaded 3100 * @prev_stat: ptr to previous loaded stat value 3101 * @cur_stat: ptr to current stat value 3102 */ 3103 void 3104 ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg, 3105 bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat) 3106 { 3107 u64 new_data; 3108 3109 new_data = rd32(hw, loreg); 3110 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; 3111 3112 /* device stats are not reset at PFR, they likely will not be zeroed 3113 * when the driver starts. So save the first values read and use them as 3114 * offsets to be subtracted from the raw values in order to report stats 3115 * that count from zero. 3116 */ 3117 if (!prev_stat_loaded) 3118 *prev_stat = new_data; 3119 if (new_data >= *prev_stat) 3120 *cur_stat = new_data - *prev_stat; 3121 else 3122 /* to manage the potential roll-over */ 3123 *cur_stat = (new_data + BIT_ULL(40)) - *prev_stat; 3124 *cur_stat &= 0xFFFFFFFFFFULL; 3125 } 3126 3127 /** 3128 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 3129 * @hw: ptr to the hardware info 3130 * @reg: HW register to read from 3131 * @prev_stat_loaded: bool to specify if previous stats are loaded 3132 * @prev_stat: ptr to previous loaded stat value 3133 * @cur_stat: ptr to current stat value 3134 */ 3135 void 3136 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 3137 u64 *prev_stat, u64 *cur_stat) 3138 { 3139 u32 new_data; 3140 3141 new_data = rd32(hw, reg); 3142 3143 /* device stats are not reset at PFR, they likely will not be zeroed 3144 * when the driver starts. So save the first values read and use them as 3145 * offsets to be subtracted from the raw values in order to report stats 3146 * that count from zero. 3147 */ 3148 if (!prev_stat_loaded) 3149 *prev_stat = new_data; 3150 if (new_data >= *prev_stat) 3151 *cur_stat = new_data - *prev_stat; 3152 else 3153 /* to manage the potential roll-over */ 3154 *cur_stat = (new_data + BIT_ULL(32)) - *prev_stat; 3155 } 3156 3157 /** 3158 * ice_sched_query_elem - query element information from HW 3159 * @hw: pointer to the HW struct 3160 * @node_teid: node TEID to be queried 3161 * @buf: buffer to element information 3162 * 3163 * This function queries HW element information 3164 */ 3165 enum ice_status 3166 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 3167 struct ice_aqc_get_elem *buf) 3168 { 3169 u16 buf_size, num_elem_ret = 0; 3170 enum ice_status status; 3171 3172 buf_size = sizeof(*buf); 3173 memset(buf, 0, buf_size); 3174 buf->generic[0].node_teid = cpu_to_le32(node_teid); 3175 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 3176 NULL); 3177 if (status || num_elem_ret != 1) 3178 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 3179 return status; 3180 } 3181