1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 9 #define ICE_PF_RESET_WAIT_COUNT 300 10 11 /** 12 * ice_set_mac_type - Sets MAC type 13 * @hw: pointer to the HW structure 14 * 15 * This function sets the MAC type of the adapter based on the 16 * vendor ID and device ID stored in the HW structure. 17 */ 18 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 19 { 20 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 21 return ICE_ERR_DEVICE_NOT_SUPPORTED; 22 23 switch (hw->device_id) { 24 case ICE_DEV_ID_E810C_BACKPLANE: 25 case ICE_DEV_ID_E810C_QSFP: 26 case ICE_DEV_ID_E810C_SFP: 27 case ICE_DEV_ID_E810_XXV_SFP: 28 hw->mac_type = ICE_MAC_E810; 29 break; 30 case ICE_DEV_ID_E823C_10G_BASE_T: 31 case ICE_DEV_ID_E823C_BACKPLANE: 32 case ICE_DEV_ID_E823C_QSFP: 33 case ICE_DEV_ID_E823C_SFP: 34 case ICE_DEV_ID_E823C_SGMII: 35 case ICE_DEV_ID_E822C_10G_BASE_T: 36 case ICE_DEV_ID_E822C_BACKPLANE: 37 case ICE_DEV_ID_E822C_QSFP: 38 case ICE_DEV_ID_E822C_SFP: 39 case ICE_DEV_ID_E822C_SGMII: 40 case ICE_DEV_ID_E822L_10G_BASE_T: 41 case ICE_DEV_ID_E822L_BACKPLANE: 42 case ICE_DEV_ID_E822L_SFP: 43 case ICE_DEV_ID_E822L_SGMII: 44 case ICE_DEV_ID_E823L_10G_BASE_T: 45 case ICE_DEV_ID_E823L_1GBE: 46 case ICE_DEV_ID_E823L_BACKPLANE: 47 case ICE_DEV_ID_E823L_QSFP: 48 case ICE_DEV_ID_E823L_SFP: 49 hw->mac_type = ICE_MAC_GENERIC; 50 break; 51 default: 52 hw->mac_type = ICE_MAC_UNKNOWN; 53 break; 54 } 55 56 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 57 return 0; 58 } 59 60 /** 61 * ice_clear_pf_cfg - Clear PF configuration 62 * @hw: pointer to the hardware structure 63 * 64 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 65 * configuration, flow director filters, etc.). 66 */ 67 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 68 { 69 struct ice_aq_desc desc; 70 71 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 72 73 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 74 } 75 76 /** 77 * ice_aq_manage_mac_read - manage MAC address read command 78 * @hw: pointer to the HW struct 79 * @buf: a virtual buffer to hold the manage MAC read response 80 * @buf_size: Size of the virtual buffer 81 * @cd: pointer to command details structure or NULL 82 * 83 * This function is used to return per PF station MAC address (0x0107). 84 * NOTE: Upon successful completion of this command, MAC address information 85 * is returned in user specified buffer. Please interpret user specified 86 * buffer as "manage_mac_read" response. 87 * Response such as various MAC addresses are stored in HW struct (port.mac) 88 * ice_discover_dev_caps is expected to be called before this function is 89 * called. 90 */ 91 static enum ice_status 92 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 93 struct ice_sq_cd *cd) 94 { 95 struct ice_aqc_manage_mac_read_resp *resp; 96 struct ice_aqc_manage_mac_read *cmd; 97 struct ice_aq_desc desc; 98 enum ice_status status; 99 u16 flags; 100 u8 i; 101 102 cmd = &desc.params.mac_read; 103 104 if (buf_size < sizeof(*resp)) 105 return ICE_ERR_BUF_TOO_SHORT; 106 107 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 108 109 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 110 if (status) 111 return status; 112 113 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 114 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 115 116 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 117 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 118 return ICE_ERR_CFG; 119 } 120 121 /* A single port can report up to two (LAN and WoL) addresses */ 122 for (i = 0; i < cmd->num_addr; i++) 123 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 124 ether_addr_copy(hw->port_info->mac.lan_addr, 125 resp[i].mac_addr); 126 ether_addr_copy(hw->port_info->mac.perm_addr, 127 resp[i].mac_addr); 128 break; 129 } 130 131 return 0; 132 } 133 134 /** 135 * ice_aq_get_phy_caps - returns PHY capabilities 136 * @pi: port information structure 137 * @qual_mods: report qualified modules 138 * @report_mode: report mode capabilities 139 * @pcaps: structure for PHY capabilities to be filled 140 * @cd: pointer to command details structure or NULL 141 * 142 * Returns the various PHY capabilities supported on the Port (0x0600) 143 */ 144 enum ice_status 145 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 146 struct ice_aqc_get_phy_caps_data *pcaps, 147 struct ice_sq_cd *cd) 148 { 149 struct ice_aqc_get_phy_caps *cmd; 150 u16 pcaps_size = sizeof(*pcaps); 151 struct ice_aq_desc desc; 152 enum ice_status status; 153 struct ice_hw *hw; 154 155 cmd = &desc.params.get_phy; 156 157 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 158 return ICE_ERR_PARAM; 159 hw = pi->hw; 160 161 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 162 163 if (qual_mods) 164 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 165 166 cmd->param0 |= cpu_to_le16(report_mode); 167 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 168 169 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 170 report_mode); 171 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 172 (unsigned long long)le64_to_cpu(pcaps->phy_type_low)); 173 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 174 (unsigned long long)le64_to_cpu(pcaps->phy_type_high)); 175 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 176 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 177 pcaps->low_power_ctrl_an); 178 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 179 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 180 pcaps->eeer_value); 181 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 182 pcaps->link_fec_options); 183 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 184 pcaps->module_compliance_enforcement); 185 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 186 pcaps->extended_compliance_code); 187 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 188 pcaps->module_type[0]); 189 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 190 pcaps->module_type[1]); 191 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 192 pcaps->module_type[2]); 193 194 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) { 195 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 196 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 197 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 198 sizeof(pi->phy.link_info.module_type)); 199 } 200 201 return status; 202 } 203 204 /** 205 * ice_aq_get_link_topo_handle - get link topology node return status 206 * @pi: port information structure 207 * @node_type: requested node type 208 * @cd: pointer to command details structure or NULL 209 * 210 * Get link topology node return status for specified node type (0x06E0) 211 * 212 * Node type cage can be used to determine if cage is present. If AQC 213 * returns error (ENOENT), then no cage present. If no cage present, then 214 * connection type is backplane or BASE-T. 215 */ 216 static enum ice_status 217 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 218 struct ice_sq_cd *cd) 219 { 220 struct ice_aqc_get_link_topo *cmd; 221 struct ice_aq_desc desc; 222 223 cmd = &desc.params.get_link_topo; 224 225 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 226 227 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 228 ICE_AQC_LINK_TOPO_NODE_CTX_S); 229 230 /* set node type */ 231 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 232 233 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 234 } 235 236 /** 237 * ice_is_media_cage_present 238 * @pi: port information structure 239 * 240 * Returns true if media cage is present, else false. If no cage, then 241 * media type is backplane or BASE-T. 242 */ 243 static bool ice_is_media_cage_present(struct ice_port_info *pi) 244 { 245 /* Node type cage can be used to determine if cage is present. If AQC 246 * returns error (ENOENT), then no cage present. If no cage present then 247 * connection type is backplane or BASE-T. 248 */ 249 return !ice_aq_get_link_topo_handle(pi, 250 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 251 NULL); 252 } 253 254 /** 255 * ice_get_media_type - Gets media type 256 * @pi: port information structure 257 */ 258 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 259 { 260 struct ice_link_status *hw_link_info; 261 262 if (!pi) 263 return ICE_MEDIA_UNKNOWN; 264 265 hw_link_info = &pi->phy.link_info; 266 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 267 /* If more than one media type is selected, report unknown */ 268 return ICE_MEDIA_UNKNOWN; 269 270 if (hw_link_info->phy_type_low) { 271 /* 1G SGMII is a special case where some DA cable PHYs 272 * may show this as an option when it really shouldn't 273 * be since SGMII is meant to be between a MAC and a PHY 274 * in a backplane. Try to detect this case and handle it 275 */ 276 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 277 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 278 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 279 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 280 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 281 return ICE_MEDIA_DA; 282 283 switch (hw_link_info->phy_type_low) { 284 case ICE_PHY_TYPE_LOW_1000BASE_SX: 285 case ICE_PHY_TYPE_LOW_1000BASE_LX: 286 case ICE_PHY_TYPE_LOW_10GBASE_SR: 287 case ICE_PHY_TYPE_LOW_10GBASE_LR: 288 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 289 case ICE_PHY_TYPE_LOW_25GBASE_SR: 290 case ICE_PHY_TYPE_LOW_25GBASE_LR: 291 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 292 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 293 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 294 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 295 case ICE_PHY_TYPE_LOW_50GBASE_SR: 296 case ICE_PHY_TYPE_LOW_50GBASE_FR: 297 case ICE_PHY_TYPE_LOW_50GBASE_LR: 298 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 299 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 300 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 301 case ICE_PHY_TYPE_LOW_100GBASE_DR: 302 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 303 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 304 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 305 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 306 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 307 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 308 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 309 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 310 return ICE_MEDIA_FIBER; 311 case ICE_PHY_TYPE_LOW_100BASE_TX: 312 case ICE_PHY_TYPE_LOW_1000BASE_T: 313 case ICE_PHY_TYPE_LOW_2500BASE_T: 314 case ICE_PHY_TYPE_LOW_5GBASE_T: 315 case ICE_PHY_TYPE_LOW_10GBASE_T: 316 case ICE_PHY_TYPE_LOW_25GBASE_T: 317 return ICE_MEDIA_BASET; 318 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 319 case ICE_PHY_TYPE_LOW_25GBASE_CR: 320 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 321 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 322 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 323 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 324 case ICE_PHY_TYPE_LOW_50GBASE_CP: 325 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 326 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 327 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 328 return ICE_MEDIA_DA; 329 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 330 case ICE_PHY_TYPE_LOW_40G_XLAUI: 331 case ICE_PHY_TYPE_LOW_50G_LAUI2: 332 case ICE_PHY_TYPE_LOW_50G_AUI2: 333 case ICE_PHY_TYPE_LOW_50G_AUI1: 334 case ICE_PHY_TYPE_LOW_100G_AUI4: 335 case ICE_PHY_TYPE_LOW_100G_CAUI4: 336 if (ice_is_media_cage_present(pi)) 337 return ICE_MEDIA_DA; 338 fallthrough; 339 case ICE_PHY_TYPE_LOW_1000BASE_KX: 340 case ICE_PHY_TYPE_LOW_2500BASE_KX: 341 case ICE_PHY_TYPE_LOW_2500BASE_X: 342 case ICE_PHY_TYPE_LOW_5GBASE_KR: 343 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 344 case ICE_PHY_TYPE_LOW_25GBASE_KR: 345 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 346 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 347 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 348 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 349 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 350 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 351 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 352 return ICE_MEDIA_BACKPLANE; 353 } 354 } else { 355 switch (hw_link_info->phy_type_high) { 356 case ICE_PHY_TYPE_HIGH_100G_AUI2: 357 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 358 if (ice_is_media_cage_present(pi)) 359 return ICE_MEDIA_DA; 360 fallthrough; 361 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 362 return ICE_MEDIA_BACKPLANE; 363 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 364 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 365 return ICE_MEDIA_FIBER; 366 } 367 } 368 return ICE_MEDIA_UNKNOWN; 369 } 370 371 /** 372 * ice_aq_get_link_info 373 * @pi: port information structure 374 * @ena_lse: enable/disable LinkStatusEvent reporting 375 * @link: pointer to link status structure - optional 376 * @cd: pointer to command details structure or NULL 377 * 378 * Get Link Status (0x607). Returns the link status of the adapter. 379 */ 380 enum ice_status 381 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 382 struct ice_link_status *link, struct ice_sq_cd *cd) 383 { 384 struct ice_aqc_get_link_status_data link_data = { 0 }; 385 struct ice_aqc_get_link_status *resp; 386 struct ice_link_status *li_old, *li; 387 enum ice_media_type *hw_media_type; 388 struct ice_fc_info *hw_fc_info; 389 bool tx_pause, rx_pause; 390 struct ice_aq_desc desc; 391 enum ice_status status; 392 struct ice_hw *hw; 393 u16 cmd_flags; 394 395 if (!pi) 396 return ICE_ERR_PARAM; 397 hw = pi->hw; 398 li_old = &pi->phy.link_info_old; 399 hw_media_type = &pi->phy.media_type; 400 li = &pi->phy.link_info; 401 hw_fc_info = &pi->fc; 402 403 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 404 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 405 resp = &desc.params.get_link_status; 406 resp->cmd_flags = cpu_to_le16(cmd_flags); 407 resp->lport_num = pi->lport; 408 409 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 410 411 if (status) 412 return status; 413 414 /* save off old link status information */ 415 *li_old = *li; 416 417 /* update current link status information */ 418 li->link_speed = le16_to_cpu(link_data.link_speed); 419 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 420 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 421 *hw_media_type = ice_get_media_type(pi); 422 li->link_info = link_data.link_info; 423 li->an_info = link_data.an_info; 424 li->ext_info = link_data.ext_info; 425 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 426 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 427 li->topo_media_conflict = link_data.topo_media_conflict; 428 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 429 ICE_AQ_CFG_PACING_TYPE_M); 430 431 /* update fc info */ 432 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 433 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 434 if (tx_pause && rx_pause) 435 hw_fc_info->current_mode = ICE_FC_FULL; 436 else if (tx_pause) 437 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 438 else if (rx_pause) 439 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 440 else 441 hw_fc_info->current_mode = ICE_FC_NONE; 442 443 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 444 445 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 446 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 447 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 448 (unsigned long long)li->phy_type_low); 449 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 450 (unsigned long long)li->phy_type_high); 451 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 452 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 453 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 454 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 455 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 456 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 457 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 458 li->max_frame_size); 459 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 460 461 /* save link status information */ 462 if (link) 463 *link = *li; 464 465 /* flag cleared so calling functions don't call AQ again */ 466 pi->phy.get_link_info = false; 467 468 return 0; 469 } 470 471 /** 472 * ice_fill_tx_timer_and_fc_thresh 473 * @hw: pointer to the HW struct 474 * @cmd: pointer to MAC cfg structure 475 * 476 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 477 * descriptor 478 */ 479 static void 480 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 481 struct ice_aqc_set_mac_cfg *cmd) 482 { 483 u16 fc_thres_val, tx_timer_val; 484 u32 val; 485 486 /* We read back the transmit timer and FC threshold value of 487 * LFC. Thus, we will use index = 488 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 489 * 490 * Also, because we are operating on transmit timer and FC 491 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 492 */ 493 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 494 495 /* Retrieve the transmit timer */ 496 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 497 tx_timer_val = val & 498 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 499 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val); 500 501 /* Retrieve the FC threshold */ 502 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 503 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 504 505 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val); 506 } 507 508 /** 509 * ice_aq_set_mac_cfg 510 * @hw: pointer to the HW struct 511 * @max_frame_size: Maximum Frame Size to be supported 512 * @cd: pointer to command details structure or NULL 513 * 514 * Set MAC configuration (0x0603) 515 */ 516 enum ice_status 517 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 518 { 519 struct ice_aqc_set_mac_cfg *cmd; 520 struct ice_aq_desc desc; 521 522 cmd = &desc.params.set_mac_cfg; 523 524 if (max_frame_size == 0) 525 return ICE_ERR_PARAM; 526 527 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 528 529 cmd->max_frame_size = cpu_to_le16(max_frame_size); 530 531 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 532 533 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 534 } 535 536 /** 537 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 538 * @hw: pointer to the HW struct 539 */ 540 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 541 { 542 struct ice_switch_info *sw; 543 enum ice_status status; 544 545 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 546 sizeof(*hw->switch_info), GFP_KERNEL); 547 sw = hw->switch_info; 548 549 if (!sw) 550 return ICE_ERR_NO_MEMORY; 551 552 INIT_LIST_HEAD(&sw->vsi_list_map_head); 553 554 status = ice_init_def_sw_recp(hw); 555 if (status) { 556 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 557 return status; 558 } 559 return 0; 560 } 561 562 /** 563 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 564 * @hw: pointer to the HW struct 565 */ 566 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 567 { 568 struct ice_switch_info *sw = hw->switch_info; 569 struct ice_vsi_list_map_info *v_pos_map; 570 struct ice_vsi_list_map_info *v_tmp_map; 571 struct ice_sw_recipe *recps; 572 u8 i; 573 574 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 575 list_entry) { 576 list_del(&v_pos_map->list_entry); 577 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 578 } 579 recps = hw->switch_info->recp_list; 580 for (i = 0; i < ICE_SW_LKUP_LAST; i++) { 581 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 582 583 recps[i].root_rid = i; 584 mutex_destroy(&recps[i].filt_rule_lock); 585 list_for_each_entry_safe(lst_itr, tmp_entry, 586 &recps[i].filt_rules, list_entry) { 587 list_del(&lst_itr->list_entry); 588 devm_kfree(ice_hw_to_dev(hw), lst_itr); 589 } 590 } 591 ice_rm_all_sw_replay_rule_info(hw); 592 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 593 devm_kfree(ice_hw_to_dev(hw), sw); 594 } 595 596 /** 597 * ice_get_fw_log_cfg - get FW logging configuration 598 * @hw: pointer to the HW struct 599 */ 600 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw) 601 { 602 struct ice_aq_desc desc; 603 enum ice_status status; 604 __le16 *config; 605 u16 size; 606 607 size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX; 608 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL); 609 if (!config) 610 return ICE_ERR_NO_MEMORY; 611 612 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 613 614 status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 615 if (!status) { 616 u16 i; 617 618 /* Save FW logging information into the HW structure */ 619 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 620 u16 v, m, flgs; 621 622 v = le16_to_cpu(config[i]); 623 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 624 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 625 626 if (m < ICE_AQC_FW_LOG_ID_MAX) 627 hw->fw_log.evnts[m].cur = flgs; 628 } 629 } 630 631 devm_kfree(ice_hw_to_dev(hw), config); 632 633 return status; 634 } 635 636 /** 637 * ice_cfg_fw_log - configure FW logging 638 * @hw: pointer to the HW struct 639 * @enable: enable certain FW logging events if true, disable all if false 640 * 641 * This function enables/disables the FW logging via Rx CQ events and a UART 642 * port based on predetermined configurations. FW logging via the Rx CQ can be 643 * enabled/disabled for individual PF's. However, FW logging via the UART can 644 * only be enabled/disabled for all PFs on the same device. 645 * 646 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 647 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 648 * before initializing the device. 649 * 650 * When re/configuring FW logging, callers need to update the "cfg" elements of 651 * the hw->fw_log.evnts array with the desired logging event configurations for 652 * modules of interest. When disabling FW logging completely, the callers can 653 * just pass false in the "enable" parameter. On completion, the function will 654 * update the "cur" element of the hw->fw_log.evnts array with the resulting 655 * logging event configurations of the modules that are being re/configured. FW 656 * logging modules that are not part of a reconfiguration operation retain their 657 * previous states. 658 * 659 * Before resetting the device, it is recommended that the driver disables FW 660 * logging before shutting down the control queue. When disabling FW logging 661 * ("enable" = false), the latest configurations of FW logging events stored in 662 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 663 * a device reset. 664 * 665 * When enabling FW logging to emit log messages via the Rx CQ during the 666 * device's initialization phase, a mechanism alternative to interrupt handlers 667 * needs to be used to extract FW log messages from the Rx CQ periodically and 668 * to prevent the Rx CQ from being full and stalling other types of control 669 * messages from FW to SW. Interrupts are typically disabled during the device's 670 * initialization phase. 671 */ 672 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable) 673 { 674 struct ice_aqc_fw_logging *cmd; 675 enum ice_status status = 0; 676 u16 i, chgs = 0, len = 0; 677 struct ice_aq_desc desc; 678 __le16 *data = NULL; 679 u8 actv_evnts = 0; 680 void *buf = NULL; 681 682 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 683 return 0; 684 685 /* Disable FW logging only when the control queue is still responsive */ 686 if (!enable && 687 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 688 return 0; 689 690 /* Get current FW log settings */ 691 status = ice_get_fw_log_cfg(hw); 692 if (status) 693 return status; 694 695 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 696 cmd = &desc.params.fw_logging; 697 698 /* Indicate which controls are valid */ 699 if (hw->fw_log.cq_en) 700 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 701 702 if (hw->fw_log.uart_en) 703 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 704 705 if (enable) { 706 /* Fill in an array of entries with FW logging modules and 707 * logging events being reconfigured. 708 */ 709 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 710 u16 val; 711 712 /* Keep track of enabled event types */ 713 actv_evnts |= hw->fw_log.evnts[i].cfg; 714 715 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 716 continue; 717 718 if (!data) { 719 data = devm_kcalloc(ice_hw_to_dev(hw), 720 sizeof(*data), 721 ICE_AQC_FW_LOG_ID_MAX, 722 GFP_KERNEL); 723 if (!data) 724 return ICE_ERR_NO_MEMORY; 725 } 726 727 val = i << ICE_AQC_FW_LOG_ID_S; 728 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 729 data[chgs++] = cpu_to_le16(val); 730 } 731 732 /* Only enable FW logging if at least one module is specified. 733 * If FW logging is currently enabled but all modules are not 734 * enabled to emit log messages, disable FW logging altogether. 735 */ 736 if (actv_evnts) { 737 /* Leave if there is effectively no change */ 738 if (!chgs) 739 goto out; 740 741 if (hw->fw_log.cq_en) 742 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 743 744 if (hw->fw_log.uart_en) 745 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 746 747 buf = data; 748 len = sizeof(*data) * chgs; 749 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 750 } 751 } 752 753 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 754 if (!status) { 755 /* Update the current configuration to reflect events enabled. 756 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 757 * logging mode is enabled for the device. They do not reflect 758 * actual modules being enabled to emit log messages. So, their 759 * values remain unchanged even when all modules are disabled. 760 */ 761 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 762 763 hw->fw_log.actv_evnts = actv_evnts; 764 for (i = 0; i < cnt; i++) { 765 u16 v, m; 766 767 if (!enable) { 768 /* When disabling all FW logging events as part 769 * of device's de-initialization, the original 770 * configurations are retained, and can be used 771 * to reconfigure FW logging later if the device 772 * is re-initialized. 773 */ 774 hw->fw_log.evnts[i].cur = 0; 775 continue; 776 } 777 778 v = le16_to_cpu(data[i]); 779 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 780 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 781 } 782 } 783 784 out: 785 if (data) 786 devm_kfree(ice_hw_to_dev(hw), data); 787 788 return status; 789 } 790 791 /** 792 * ice_output_fw_log 793 * @hw: pointer to the HW struct 794 * @desc: pointer to the AQ message descriptor 795 * @buf: pointer to the buffer accompanying the AQ message 796 * 797 * Formats a FW Log message and outputs it via the standard driver logs. 798 */ 799 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 800 { 801 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 802 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 803 le16_to_cpu(desc->datalen)); 804 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 805 } 806 807 /** 808 * ice_get_itr_intrl_gran 809 * @hw: pointer to the HW struct 810 * 811 * Determines the ITR/INTRL granularities based on the maximum aggregate 812 * bandwidth according to the device's configuration during power-on. 813 */ 814 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 815 { 816 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 817 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 818 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 819 820 switch (max_agg_bw) { 821 case ICE_MAX_AGG_BW_200G: 822 case ICE_MAX_AGG_BW_100G: 823 case ICE_MAX_AGG_BW_50G: 824 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 825 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 826 break; 827 case ICE_MAX_AGG_BW_25G: 828 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 829 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 830 break; 831 } 832 } 833 834 /** 835 * ice_init_hw - main hardware initialization routine 836 * @hw: pointer to the hardware structure 837 */ 838 enum ice_status ice_init_hw(struct ice_hw *hw) 839 { 840 struct ice_aqc_get_phy_caps_data *pcaps; 841 enum ice_status status; 842 u16 mac_buf_len; 843 void *mac_buf; 844 845 /* Set MAC type based on DeviceID */ 846 status = ice_set_mac_type(hw); 847 if (status) 848 return status; 849 850 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 851 PF_FUNC_RID_FUNC_NUM_M) >> 852 PF_FUNC_RID_FUNC_NUM_S; 853 854 status = ice_reset(hw, ICE_RESET_PFR); 855 if (status) 856 return status; 857 858 ice_get_itr_intrl_gran(hw); 859 860 status = ice_create_all_ctrlq(hw); 861 if (status) 862 goto err_unroll_cqinit; 863 864 /* Enable FW logging. Not fatal if this fails. */ 865 status = ice_cfg_fw_log(hw, true); 866 if (status) 867 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 868 869 status = ice_clear_pf_cfg(hw); 870 if (status) 871 goto err_unroll_cqinit; 872 873 /* Set bit to enable Flow Director filters */ 874 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 875 INIT_LIST_HEAD(&hw->fdir_list_head); 876 877 ice_clear_pxe_mode(hw); 878 879 status = ice_init_nvm(hw); 880 if (status) 881 goto err_unroll_cqinit; 882 883 status = ice_get_caps(hw); 884 if (status) 885 goto err_unroll_cqinit; 886 887 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 888 sizeof(*hw->port_info), GFP_KERNEL); 889 if (!hw->port_info) { 890 status = ICE_ERR_NO_MEMORY; 891 goto err_unroll_cqinit; 892 } 893 894 /* set the back pointer to HW */ 895 hw->port_info->hw = hw; 896 897 /* Initialize port_info struct with switch configuration data */ 898 status = ice_get_initial_sw_cfg(hw); 899 if (status) 900 goto err_unroll_alloc; 901 902 hw->evb_veb = true; 903 904 /* Query the allocated resources for Tx scheduler */ 905 status = ice_sched_query_res_alloc(hw); 906 if (status) { 907 ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 908 goto err_unroll_alloc; 909 } 910 911 /* Initialize port_info struct with scheduler data */ 912 status = ice_sched_init_port(hw->port_info); 913 if (status) 914 goto err_unroll_sched; 915 916 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 917 if (!pcaps) { 918 status = ICE_ERR_NO_MEMORY; 919 goto err_unroll_sched; 920 } 921 922 /* Initialize port_info struct with PHY capabilities */ 923 status = ice_aq_get_phy_caps(hw->port_info, false, 924 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); 925 devm_kfree(ice_hw_to_dev(hw), pcaps); 926 if (status) 927 dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 928 status); 929 930 /* Initialize port_info struct with link information */ 931 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 932 if (status) 933 goto err_unroll_sched; 934 935 /* need a valid SW entry point to build a Tx tree */ 936 if (!hw->sw_entry_point_layer) { 937 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 938 status = ICE_ERR_CFG; 939 goto err_unroll_sched; 940 } 941 INIT_LIST_HEAD(&hw->agg_list); 942 /* Initialize max burst size */ 943 if (!hw->max_burst_size) 944 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 945 946 status = ice_init_fltr_mgmt_struct(hw); 947 if (status) 948 goto err_unroll_sched; 949 950 /* Get MAC information */ 951 /* A single port can report up to two (LAN and WoL) addresses */ 952 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 953 sizeof(struct ice_aqc_manage_mac_read_resp), 954 GFP_KERNEL); 955 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 956 957 if (!mac_buf) { 958 status = ICE_ERR_NO_MEMORY; 959 goto err_unroll_fltr_mgmt_struct; 960 } 961 962 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 963 devm_kfree(ice_hw_to_dev(hw), mac_buf); 964 965 if (status) 966 goto err_unroll_fltr_mgmt_struct; 967 /* enable jumbo frame support at MAC level */ 968 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 969 if (status) 970 goto err_unroll_fltr_mgmt_struct; 971 /* Obtain counter base index which would be used by flow director */ 972 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 973 if (status) 974 goto err_unroll_fltr_mgmt_struct; 975 status = ice_init_hw_tbls(hw); 976 if (status) 977 goto err_unroll_fltr_mgmt_struct; 978 mutex_init(&hw->tnl_lock); 979 return 0; 980 981 err_unroll_fltr_mgmt_struct: 982 ice_cleanup_fltr_mgmt_struct(hw); 983 err_unroll_sched: 984 ice_sched_cleanup_all(hw); 985 err_unroll_alloc: 986 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 987 err_unroll_cqinit: 988 ice_destroy_all_ctrlq(hw); 989 return status; 990 } 991 992 /** 993 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 994 * @hw: pointer to the hardware structure 995 * 996 * This should be called only during nominal operation, not as a result of 997 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 998 * applicable initializations if it fails for any reason. 999 */ 1000 void ice_deinit_hw(struct ice_hw *hw) 1001 { 1002 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1003 ice_cleanup_fltr_mgmt_struct(hw); 1004 1005 ice_sched_cleanup_all(hw); 1006 ice_sched_clear_agg(hw); 1007 ice_free_seg(hw); 1008 ice_free_hw_tbls(hw); 1009 mutex_destroy(&hw->tnl_lock); 1010 1011 if (hw->port_info) { 1012 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1013 hw->port_info = NULL; 1014 } 1015 1016 /* Attempt to disable FW logging before shutting down control queues */ 1017 ice_cfg_fw_log(hw, false); 1018 ice_destroy_all_ctrlq(hw); 1019 1020 /* Clear VSI contexts if not already cleared */ 1021 ice_clear_all_vsi_ctx(hw); 1022 } 1023 1024 /** 1025 * ice_check_reset - Check to see if a global reset is complete 1026 * @hw: pointer to the hardware structure 1027 */ 1028 enum ice_status ice_check_reset(struct ice_hw *hw) 1029 { 1030 u32 cnt, reg = 0, grst_timeout, uld_mask; 1031 1032 /* Poll for Device Active state in case a recent CORER, GLOBR, 1033 * or EMPR has occurred. The grst delay value is in 100ms units. 1034 * Add 1sec for outstanding AQ commands that can take a long time. 1035 */ 1036 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1037 GLGEN_RSTCTL_GRSTDEL_S) + 10; 1038 1039 for (cnt = 0; cnt < grst_timeout; cnt++) { 1040 mdelay(100); 1041 reg = rd32(hw, GLGEN_RSTAT); 1042 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1043 break; 1044 } 1045 1046 if (cnt == grst_timeout) { 1047 ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1048 return ICE_ERR_RESET_FAILED; 1049 } 1050 1051 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1052 GLNVM_ULD_PCIER_DONE_1_M |\ 1053 GLNVM_ULD_CORER_DONE_M |\ 1054 GLNVM_ULD_GLOBR_DONE_M |\ 1055 GLNVM_ULD_POR_DONE_M |\ 1056 GLNVM_ULD_POR_DONE_1_M |\ 1057 GLNVM_ULD_PCIER_DONE_2_M) 1058 1059 uld_mask = ICE_RESET_DONE_MASK; 1060 1061 /* Device is Active; check Global Reset processes are done */ 1062 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1063 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1064 if (reg == uld_mask) { 1065 ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1066 break; 1067 } 1068 mdelay(10); 1069 } 1070 1071 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1072 ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1073 reg); 1074 return ICE_ERR_RESET_FAILED; 1075 } 1076 1077 return 0; 1078 } 1079 1080 /** 1081 * ice_pf_reset - Reset the PF 1082 * @hw: pointer to the hardware structure 1083 * 1084 * If a global reset has been triggered, this function checks 1085 * for its completion and then issues the PF reset 1086 */ 1087 static enum ice_status ice_pf_reset(struct ice_hw *hw) 1088 { 1089 u32 cnt, reg; 1090 1091 /* If at function entry a global reset was already in progress, i.e. 1092 * state is not 'device active' or any of the reset done bits are not 1093 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1094 * global reset is done. 1095 */ 1096 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1097 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1098 /* poll on global reset currently in progress until done */ 1099 if (ice_check_reset(hw)) 1100 return ICE_ERR_RESET_FAILED; 1101 1102 return 0; 1103 } 1104 1105 /* Reset the PF */ 1106 reg = rd32(hw, PFGEN_CTRL); 1107 1108 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1109 1110 /* Wait for the PFR to complete. The wait time is the global config lock 1111 * timeout plus the PFR timeout which will account for a possible reset 1112 * that is occurring during a download package operation. 1113 */ 1114 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1115 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1116 reg = rd32(hw, PFGEN_CTRL); 1117 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1118 break; 1119 1120 mdelay(1); 1121 } 1122 1123 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1124 ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1125 return ICE_ERR_RESET_FAILED; 1126 } 1127 1128 return 0; 1129 } 1130 1131 /** 1132 * ice_reset - Perform different types of reset 1133 * @hw: pointer to the hardware structure 1134 * @req: reset request 1135 * 1136 * This function triggers a reset as specified by the req parameter. 1137 * 1138 * Note: 1139 * If anything other than a PF reset is triggered, PXE mode is restored. 1140 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1141 * interface has been restored in the rebuild flow. 1142 */ 1143 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1144 { 1145 u32 val = 0; 1146 1147 switch (req) { 1148 case ICE_RESET_PFR: 1149 return ice_pf_reset(hw); 1150 case ICE_RESET_CORER: 1151 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1152 val = GLGEN_RTRIG_CORER_M; 1153 break; 1154 case ICE_RESET_GLOBR: 1155 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1156 val = GLGEN_RTRIG_GLOBR_M; 1157 break; 1158 default: 1159 return ICE_ERR_PARAM; 1160 } 1161 1162 val |= rd32(hw, GLGEN_RTRIG); 1163 wr32(hw, GLGEN_RTRIG, val); 1164 ice_flush(hw); 1165 1166 /* wait for the FW to be ready */ 1167 return ice_check_reset(hw); 1168 } 1169 1170 /** 1171 * ice_copy_rxq_ctx_to_hw 1172 * @hw: pointer to the hardware structure 1173 * @ice_rxq_ctx: pointer to the rxq context 1174 * @rxq_index: the index of the Rx queue 1175 * 1176 * Copies rxq context from dense structure to HW register space 1177 */ 1178 static enum ice_status 1179 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1180 { 1181 u8 i; 1182 1183 if (!ice_rxq_ctx) 1184 return ICE_ERR_BAD_PTR; 1185 1186 if (rxq_index > QRX_CTRL_MAX_INDEX) 1187 return ICE_ERR_PARAM; 1188 1189 /* Copy each dword separately to HW */ 1190 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1191 wr32(hw, QRX_CONTEXT(i, rxq_index), 1192 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1193 1194 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1195 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1196 } 1197 1198 return 0; 1199 } 1200 1201 /* LAN Rx Queue Context */ 1202 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1203 /* Field Width LSB */ 1204 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1205 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1206 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1207 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1208 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1209 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1210 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1211 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1212 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1213 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1214 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1215 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1216 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1217 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1218 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1219 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1220 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1221 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1222 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1223 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1224 { 0 } 1225 }; 1226 1227 /** 1228 * ice_write_rxq_ctx 1229 * @hw: pointer to the hardware structure 1230 * @rlan_ctx: pointer to the rxq context 1231 * @rxq_index: the index of the Rx queue 1232 * 1233 * Converts rxq context from sparse to dense structure and then writes 1234 * it to HW register space and enables the hardware to prefetch descriptors 1235 * instead of only fetching them on demand 1236 */ 1237 enum ice_status 1238 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1239 u32 rxq_index) 1240 { 1241 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1242 1243 if (!rlan_ctx) 1244 return ICE_ERR_BAD_PTR; 1245 1246 rlan_ctx->prefena = 1; 1247 1248 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1249 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1250 } 1251 1252 /* LAN Tx Queue Context */ 1253 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1254 /* Field Width LSB */ 1255 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1256 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1257 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1258 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1259 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1260 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1261 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1262 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1263 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1264 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1265 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1266 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1267 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1268 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1269 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1270 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1271 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1272 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1273 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1274 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1275 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1276 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1277 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1278 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1279 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1280 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1281 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1282 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1283 { 0 } 1284 }; 1285 1286 /* FW Admin Queue command wrappers */ 1287 1288 /* Software lock/mutex that is meant to be held while the Global Config Lock 1289 * in firmware is acquired by the software to prevent most (but not all) types 1290 * of AQ commands from being sent to FW 1291 */ 1292 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1293 1294 /** 1295 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1296 * @hw: pointer to the HW struct 1297 * @desc: descriptor describing the command 1298 * @buf: buffer to use for indirect commands (NULL for direct commands) 1299 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1300 * @cd: pointer to command details structure 1301 * 1302 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1303 */ 1304 enum ice_status 1305 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1306 u16 buf_size, struct ice_sq_cd *cd) 1307 { 1308 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1309 bool lock_acquired = false; 1310 enum ice_status status; 1311 1312 /* When a package download is in process (i.e. when the firmware's 1313 * Global Configuration Lock resource is held), only the Download 1314 * Package, Get Version, Get Package Info List and Release Resource 1315 * (with resource ID set to Global Config Lock) AdminQ commands are 1316 * allowed; all others must block until the package download completes 1317 * and the Global Config Lock is released. See also 1318 * ice_acquire_global_cfg_lock(). 1319 */ 1320 switch (le16_to_cpu(desc->opcode)) { 1321 case ice_aqc_opc_download_pkg: 1322 case ice_aqc_opc_get_pkg_info_list: 1323 case ice_aqc_opc_get_ver: 1324 break; 1325 case ice_aqc_opc_release_res: 1326 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1327 break; 1328 fallthrough; 1329 default: 1330 mutex_lock(&ice_global_cfg_lock_sw); 1331 lock_acquired = true; 1332 break; 1333 } 1334 1335 status = ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); 1336 if (lock_acquired) 1337 mutex_unlock(&ice_global_cfg_lock_sw); 1338 1339 return status; 1340 } 1341 1342 /** 1343 * ice_aq_get_fw_ver 1344 * @hw: pointer to the HW struct 1345 * @cd: pointer to command details structure or NULL 1346 * 1347 * Get the firmware version (0x0001) from the admin queue commands 1348 */ 1349 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1350 { 1351 struct ice_aqc_get_ver *resp; 1352 struct ice_aq_desc desc; 1353 enum ice_status status; 1354 1355 resp = &desc.params.get_ver; 1356 1357 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1358 1359 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1360 1361 if (!status) { 1362 hw->fw_branch = resp->fw_branch; 1363 hw->fw_maj_ver = resp->fw_major; 1364 hw->fw_min_ver = resp->fw_minor; 1365 hw->fw_patch = resp->fw_patch; 1366 hw->fw_build = le32_to_cpu(resp->fw_build); 1367 hw->api_branch = resp->api_branch; 1368 hw->api_maj_ver = resp->api_major; 1369 hw->api_min_ver = resp->api_minor; 1370 hw->api_patch = resp->api_patch; 1371 } 1372 1373 return status; 1374 } 1375 1376 /** 1377 * ice_aq_send_driver_ver 1378 * @hw: pointer to the HW struct 1379 * @dv: driver's major, minor version 1380 * @cd: pointer to command details structure or NULL 1381 * 1382 * Send the driver version (0x0002) to the firmware 1383 */ 1384 enum ice_status 1385 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1386 struct ice_sq_cd *cd) 1387 { 1388 struct ice_aqc_driver_ver *cmd; 1389 struct ice_aq_desc desc; 1390 u16 len; 1391 1392 cmd = &desc.params.driver_ver; 1393 1394 if (!dv) 1395 return ICE_ERR_PARAM; 1396 1397 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1398 1399 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1400 cmd->major_ver = dv->major_ver; 1401 cmd->minor_ver = dv->minor_ver; 1402 cmd->build_ver = dv->build_ver; 1403 cmd->subbuild_ver = dv->subbuild_ver; 1404 1405 len = 0; 1406 while (len < sizeof(dv->driver_string) && 1407 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1408 len++; 1409 1410 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1411 } 1412 1413 /** 1414 * ice_aq_q_shutdown 1415 * @hw: pointer to the HW struct 1416 * @unloading: is the driver unloading itself 1417 * 1418 * Tell the Firmware that we're shutting down the AdminQ and whether 1419 * or not the driver is unloading as well (0x0003). 1420 */ 1421 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1422 { 1423 struct ice_aqc_q_shutdown *cmd; 1424 struct ice_aq_desc desc; 1425 1426 cmd = &desc.params.q_shutdown; 1427 1428 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1429 1430 if (unloading) 1431 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1432 1433 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1434 } 1435 1436 /** 1437 * ice_aq_req_res 1438 * @hw: pointer to the HW struct 1439 * @res: resource ID 1440 * @access: access type 1441 * @sdp_number: resource number 1442 * @timeout: the maximum time in ms that the driver may hold the resource 1443 * @cd: pointer to command details structure or NULL 1444 * 1445 * Requests common resource using the admin queue commands (0x0008). 1446 * When attempting to acquire the Global Config Lock, the driver can 1447 * learn of three states: 1448 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1449 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1450 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1451 * successfully downloaded the package; the driver does 1452 * not have to download the package and can continue 1453 * loading 1454 * 1455 * Note that if the caller is in an acquire lock, perform action, release lock 1456 * phase of operation, it is possible that the FW may detect a timeout and issue 1457 * a CORER. In this case, the driver will receive a CORER interrupt and will 1458 * have to determine its cause. The calling thread that is handling this flow 1459 * will likely get an error propagated back to it indicating the Download 1460 * Package, Update Package or the Release Resource AQ commands timed out. 1461 */ 1462 static enum ice_status 1463 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1464 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1465 struct ice_sq_cd *cd) 1466 { 1467 struct ice_aqc_req_res *cmd_resp; 1468 struct ice_aq_desc desc; 1469 enum ice_status status; 1470 1471 cmd_resp = &desc.params.res_owner; 1472 1473 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1474 1475 cmd_resp->res_id = cpu_to_le16(res); 1476 cmd_resp->access_type = cpu_to_le16(access); 1477 cmd_resp->res_number = cpu_to_le32(sdp_number); 1478 cmd_resp->timeout = cpu_to_le32(*timeout); 1479 *timeout = 0; 1480 1481 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1482 1483 /* The completion specifies the maximum time in ms that the driver 1484 * may hold the resource in the Timeout field. 1485 */ 1486 1487 /* Global config lock response utilizes an additional status field. 1488 * 1489 * If the Global config lock resource is held by some other driver, the 1490 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1491 * and the timeout field indicates the maximum time the current owner 1492 * of the resource has to free it. 1493 */ 1494 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1495 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1496 *timeout = le32_to_cpu(cmd_resp->timeout); 1497 return 0; 1498 } else if (le16_to_cpu(cmd_resp->status) == 1499 ICE_AQ_RES_GLBL_IN_PROG) { 1500 *timeout = le32_to_cpu(cmd_resp->timeout); 1501 return ICE_ERR_AQ_ERROR; 1502 } else if (le16_to_cpu(cmd_resp->status) == 1503 ICE_AQ_RES_GLBL_DONE) { 1504 return ICE_ERR_AQ_NO_WORK; 1505 } 1506 1507 /* invalid FW response, force a timeout immediately */ 1508 *timeout = 0; 1509 return ICE_ERR_AQ_ERROR; 1510 } 1511 1512 /* If the resource is held by some other driver, the command completes 1513 * with a busy return value and the timeout field indicates the maximum 1514 * time the current owner of the resource has to free it. 1515 */ 1516 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1517 *timeout = le32_to_cpu(cmd_resp->timeout); 1518 1519 return status; 1520 } 1521 1522 /** 1523 * ice_aq_release_res 1524 * @hw: pointer to the HW struct 1525 * @res: resource ID 1526 * @sdp_number: resource number 1527 * @cd: pointer to command details structure or NULL 1528 * 1529 * release common resource using the admin queue commands (0x0009) 1530 */ 1531 static enum ice_status 1532 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1533 struct ice_sq_cd *cd) 1534 { 1535 struct ice_aqc_req_res *cmd; 1536 struct ice_aq_desc desc; 1537 1538 cmd = &desc.params.res_owner; 1539 1540 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1541 1542 cmd->res_id = cpu_to_le16(res); 1543 cmd->res_number = cpu_to_le32(sdp_number); 1544 1545 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1546 } 1547 1548 /** 1549 * ice_acquire_res 1550 * @hw: pointer to the HW structure 1551 * @res: resource ID 1552 * @access: access type (read or write) 1553 * @timeout: timeout in milliseconds 1554 * 1555 * This function will attempt to acquire the ownership of a resource. 1556 */ 1557 enum ice_status 1558 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1559 enum ice_aq_res_access_type access, u32 timeout) 1560 { 1561 #define ICE_RES_POLLING_DELAY_MS 10 1562 u32 delay = ICE_RES_POLLING_DELAY_MS; 1563 u32 time_left = timeout; 1564 enum ice_status status; 1565 1566 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1567 1568 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1569 * previously acquired the resource and performed any necessary updates; 1570 * in this case the caller does not obtain the resource and has no 1571 * further work to do. 1572 */ 1573 if (status == ICE_ERR_AQ_NO_WORK) 1574 goto ice_acquire_res_exit; 1575 1576 if (status) 1577 ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1578 1579 /* If necessary, poll until the current lock owner timeouts */ 1580 timeout = time_left; 1581 while (status && timeout && time_left) { 1582 mdelay(delay); 1583 timeout = (timeout > delay) ? timeout - delay : 0; 1584 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1585 1586 if (status == ICE_ERR_AQ_NO_WORK) 1587 /* lock free, but no work to do */ 1588 break; 1589 1590 if (!status) 1591 /* lock acquired */ 1592 break; 1593 } 1594 if (status && status != ICE_ERR_AQ_NO_WORK) 1595 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1596 1597 ice_acquire_res_exit: 1598 if (status == ICE_ERR_AQ_NO_WORK) { 1599 if (access == ICE_RES_WRITE) 1600 ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1601 else 1602 ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1603 } 1604 return status; 1605 } 1606 1607 /** 1608 * ice_release_res 1609 * @hw: pointer to the HW structure 1610 * @res: resource ID 1611 * 1612 * This function will release a resource using the proper Admin Command. 1613 */ 1614 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1615 { 1616 enum ice_status status; 1617 u32 total_delay = 0; 1618 1619 status = ice_aq_release_res(hw, res, 0, NULL); 1620 1621 /* there are some rare cases when trying to release the resource 1622 * results in an admin queue timeout, so handle them correctly 1623 */ 1624 while ((status == ICE_ERR_AQ_TIMEOUT) && 1625 (total_delay < hw->adminq.sq_cmd_timeout)) { 1626 mdelay(1); 1627 status = ice_aq_release_res(hw, res, 0, NULL); 1628 total_delay++; 1629 } 1630 } 1631 1632 /** 1633 * ice_aq_alloc_free_res - command to allocate/free resources 1634 * @hw: pointer to the HW struct 1635 * @num_entries: number of resource entries in buffer 1636 * @buf: Indirect buffer to hold data parameters and response 1637 * @buf_size: size of buffer for indirect commands 1638 * @opc: pass in the command opcode 1639 * @cd: pointer to command details structure or NULL 1640 * 1641 * Helper function to allocate/free resources using the admin queue commands 1642 */ 1643 enum ice_status 1644 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1645 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1646 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1647 { 1648 struct ice_aqc_alloc_free_res_cmd *cmd; 1649 struct ice_aq_desc desc; 1650 1651 cmd = &desc.params.sw_res_ctrl; 1652 1653 if (!buf) 1654 return ICE_ERR_PARAM; 1655 1656 if (buf_size < (num_entries * sizeof(buf->elem[0]))) 1657 return ICE_ERR_PARAM; 1658 1659 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1660 1661 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1662 1663 cmd->num_entries = cpu_to_le16(num_entries); 1664 1665 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1666 } 1667 1668 /** 1669 * ice_alloc_hw_res - allocate resource 1670 * @hw: pointer to the HW struct 1671 * @type: type of resource 1672 * @num: number of resources to allocate 1673 * @btm: allocate from bottom 1674 * @res: pointer to array that will receive the resources 1675 */ 1676 enum ice_status 1677 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1678 { 1679 struct ice_aqc_alloc_free_res_elem *buf; 1680 enum ice_status status; 1681 u16 buf_len; 1682 1683 buf_len = struct_size(buf, elem, num); 1684 buf = kzalloc(buf_len, GFP_KERNEL); 1685 if (!buf) 1686 return ICE_ERR_NO_MEMORY; 1687 1688 /* Prepare buffer to allocate resource. */ 1689 buf->num_elems = cpu_to_le16(num); 1690 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1691 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1692 if (btm) 1693 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1694 1695 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1696 ice_aqc_opc_alloc_res, NULL); 1697 if (status) 1698 goto ice_alloc_res_exit; 1699 1700 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 1701 1702 ice_alloc_res_exit: 1703 kfree(buf); 1704 return status; 1705 } 1706 1707 /** 1708 * ice_free_hw_res - free allocated HW resource 1709 * @hw: pointer to the HW struct 1710 * @type: type of resource to free 1711 * @num: number of resources 1712 * @res: pointer to array that contains the resources to free 1713 */ 1714 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1715 { 1716 struct ice_aqc_alloc_free_res_elem *buf; 1717 enum ice_status status; 1718 u16 buf_len; 1719 1720 buf_len = struct_size(buf, elem, num); 1721 buf = kzalloc(buf_len, GFP_KERNEL); 1722 if (!buf) 1723 return ICE_ERR_NO_MEMORY; 1724 1725 /* Prepare buffer to free resource. */ 1726 buf->num_elems = cpu_to_le16(num); 1727 buf->res_type = cpu_to_le16(type); 1728 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 1729 1730 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1731 ice_aqc_opc_free_res, NULL); 1732 if (status) 1733 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1734 1735 kfree(buf); 1736 return status; 1737 } 1738 1739 /** 1740 * ice_get_num_per_func - determine number of resources per PF 1741 * @hw: pointer to the HW structure 1742 * @max: value to be evenly split between each PF 1743 * 1744 * Determine the number of valid functions by going through the bitmap returned 1745 * from parsing capabilities and use this to calculate the number of resources 1746 * per PF based on the max value passed in. 1747 */ 1748 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1749 { 1750 u8 funcs; 1751 1752 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1753 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 1754 ICE_CAPS_VALID_FUNCS_M); 1755 1756 if (!funcs) 1757 return 0; 1758 1759 return max / funcs; 1760 } 1761 1762 /** 1763 * ice_parse_common_caps - parse common device/function capabilities 1764 * @hw: pointer to the HW struct 1765 * @caps: pointer to common capabilities structure 1766 * @elem: the capability element to parse 1767 * @prefix: message prefix for tracing capabilities 1768 * 1769 * Given a capability element, extract relevant details into the common 1770 * capability structure. 1771 * 1772 * Returns: true if the capability matches one of the common capability ids, 1773 * false otherwise. 1774 */ 1775 static bool 1776 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1777 struct ice_aqc_list_caps_elem *elem, const char *prefix) 1778 { 1779 u32 logical_id = le32_to_cpu(elem->logical_id); 1780 u32 phys_id = le32_to_cpu(elem->phys_id); 1781 u32 number = le32_to_cpu(elem->number); 1782 u16 cap = le16_to_cpu(elem->cap); 1783 bool found = true; 1784 1785 switch (cap) { 1786 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1787 caps->valid_functions = number; 1788 ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 1789 caps->valid_functions); 1790 break; 1791 case ICE_AQC_CAPS_SRIOV: 1792 caps->sr_iov_1_1 = (number == 1); 1793 ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 1794 caps->sr_iov_1_1); 1795 break; 1796 case ICE_AQC_CAPS_DCB: 1797 caps->dcb = (number == 1); 1798 caps->active_tc_bitmap = logical_id; 1799 caps->maxtc = phys_id; 1800 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 1801 ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 1802 caps->active_tc_bitmap); 1803 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 1804 break; 1805 case ICE_AQC_CAPS_RSS: 1806 caps->rss_table_size = number; 1807 caps->rss_table_entry_width = logical_id; 1808 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 1809 caps->rss_table_size); 1810 ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 1811 caps->rss_table_entry_width); 1812 break; 1813 case ICE_AQC_CAPS_RXQS: 1814 caps->num_rxq = number; 1815 caps->rxq_first_id = phys_id; 1816 ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 1817 caps->num_rxq); 1818 ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 1819 caps->rxq_first_id); 1820 break; 1821 case ICE_AQC_CAPS_TXQS: 1822 caps->num_txq = number; 1823 caps->txq_first_id = phys_id; 1824 ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 1825 caps->num_txq); 1826 ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 1827 caps->txq_first_id); 1828 break; 1829 case ICE_AQC_CAPS_MSIX: 1830 caps->num_msix_vectors = number; 1831 caps->msix_vector_first_id = phys_id; 1832 ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 1833 caps->num_msix_vectors); 1834 ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 1835 caps->msix_vector_first_id); 1836 break; 1837 case ICE_AQC_CAPS_PENDING_NVM_VER: 1838 caps->nvm_update_pending_nvm = true; 1839 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 1840 break; 1841 case ICE_AQC_CAPS_PENDING_OROM_VER: 1842 caps->nvm_update_pending_orom = true; 1843 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 1844 break; 1845 case ICE_AQC_CAPS_PENDING_NET_VER: 1846 caps->nvm_update_pending_netlist = true; 1847 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 1848 break; 1849 case ICE_AQC_CAPS_NVM_MGMT: 1850 caps->nvm_unified_update = 1851 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 1852 true : false; 1853 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 1854 caps->nvm_unified_update); 1855 break; 1856 case ICE_AQC_CAPS_MAX_MTU: 1857 caps->max_mtu = number; 1858 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 1859 prefix, caps->max_mtu); 1860 break; 1861 default: 1862 /* Not one of the recognized common capabilities */ 1863 found = false; 1864 } 1865 1866 return found; 1867 } 1868 1869 /** 1870 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 1871 * @hw: pointer to the HW structure 1872 * @caps: pointer to capabilities structure to fix 1873 * 1874 * Re-calculate the capabilities that are dependent on the number of physical 1875 * ports; i.e. some features are not supported or function differently on 1876 * devices with more than 4 ports. 1877 */ 1878 static void 1879 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 1880 { 1881 /* This assumes device capabilities are always scanned before function 1882 * capabilities during the initialization flow. 1883 */ 1884 if (hw->dev_caps.num_funcs > 4) { 1885 /* Max 4 TCs per port */ 1886 caps->maxtc = 4; 1887 ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 1888 caps->maxtc); 1889 } 1890 } 1891 1892 /** 1893 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 1894 * @hw: pointer to the HW struct 1895 * @func_p: pointer to function capabilities structure 1896 * @cap: pointer to the capability element to parse 1897 * 1898 * Extract function capabilities for ICE_AQC_CAPS_VF. 1899 */ 1900 static void 1901 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 1902 struct ice_aqc_list_caps_elem *cap) 1903 { 1904 u32 logical_id = le32_to_cpu(cap->logical_id); 1905 u32 number = le32_to_cpu(cap->number); 1906 1907 func_p->num_allocd_vfs = number; 1908 func_p->vf_base_id = logical_id; 1909 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 1910 func_p->num_allocd_vfs); 1911 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 1912 func_p->vf_base_id); 1913 } 1914 1915 /** 1916 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 1917 * @hw: pointer to the HW struct 1918 * @func_p: pointer to function capabilities structure 1919 * @cap: pointer to the capability element to parse 1920 * 1921 * Extract function capabilities for ICE_AQC_CAPS_VSI. 1922 */ 1923 static void 1924 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 1925 struct ice_aqc_list_caps_elem *cap) 1926 { 1927 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 1928 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 1929 le32_to_cpu(cap->number)); 1930 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 1931 func_p->guar_num_vsi); 1932 } 1933 1934 /** 1935 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 1936 * @hw: pointer to the HW struct 1937 * @func_p: pointer to function capabilities structure 1938 * 1939 * Extract function capabilities for ICE_AQC_CAPS_FD. 1940 */ 1941 static void 1942 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 1943 { 1944 u32 reg_val, val; 1945 1946 reg_val = rd32(hw, GLQF_FD_SIZE); 1947 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 1948 GLQF_FD_SIZE_FD_GSIZE_S; 1949 func_p->fd_fltr_guar = 1950 ice_get_num_per_func(hw, val); 1951 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 1952 GLQF_FD_SIZE_FD_BSIZE_S; 1953 func_p->fd_fltr_best_effort = val; 1954 1955 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 1956 func_p->fd_fltr_guar); 1957 ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 1958 func_p->fd_fltr_best_effort); 1959 } 1960 1961 /** 1962 * ice_parse_func_caps - Parse function capabilities 1963 * @hw: pointer to the HW struct 1964 * @func_p: pointer to function capabilities structure 1965 * @buf: buffer containing the function capability records 1966 * @cap_count: the number of capabilities 1967 * 1968 * Helper function to parse function (0x000A) capabilities list. For 1969 * capabilities shared between device and function, this relies on 1970 * ice_parse_common_caps. 1971 * 1972 * Loop through the list of provided capabilities and extract the relevant 1973 * data into the function capabilities structured. 1974 */ 1975 static void 1976 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 1977 void *buf, u32 cap_count) 1978 { 1979 struct ice_aqc_list_caps_elem *cap_resp; 1980 u32 i; 1981 1982 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 1983 1984 memset(func_p, 0, sizeof(*func_p)); 1985 1986 for (i = 0; i < cap_count; i++) { 1987 u16 cap = le16_to_cpu(cap_resp[i].cap); 1988 bool found; 1989 1990 found = ice_parse_common_caps(hw, &func_p->common_cap, 1991 &cap_resp[i], "func caps"); 1992 1993 switch (cap) { 1994 case ICE_AQC_CAPS_VF: 1995 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 1996 break; 1997 case ICE_AQC_CAPS_VSI: 1998 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 1999 break; 2000 case ICE_AQC_CAPS_FD: 2001 ice_parse_fdir_func_caps(hw, func_p); 2002 break; 2003 default: 2004 /* Don't list common capabilities as unknown */ 2005 if (!found) 2006 ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2007 i, cap); 2008 break; 2009 } 2010 } 2011 2012 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2013 } 2014 2015 /** 2016 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2017 * @hw: pointer to the HW struct 2018 * @dev_p: pointer to device capabilities structure 2019 * @cap: capability element to parse 2020 * 2021 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2022 */ 2023 static void 2024 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2025 struct ice_aqc_list_caps_elem *cap) 2026 { 2027 u32 number = le32_to_cpu(cap->number); 2028 2029 dev_p->num_funcs = hweight32(number); 2030 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2031 dev_p->num_funcs); 2032 } 2033 2034 /** 2035 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2036 * @hw: pointer to the HW struct 2037 * @dev_p: pointer to device capabilities structure 2038 * @cap: capability element to parse 2039 * 2040 * Parse ICE_AQC_CAPS_VF for device capabilities. 2041 */ 2042 static void 2043 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2044 struct ice_aqc_list_caps_elem *cap) 2045 { 2046 u32 number = le32_to_cpu(cap->number); 2047 2048 dev_p->num_vfs_exposed = number; 2049 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2050 dev_p->num_vfs_exposed); 2051 } 2052 2053 /** 2054 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2055 * @hw: pointer to the HW struct 2056 * @dev_p: pointer to device capabilities structure 2057 * @cap: capability element to parse 2058 * 2059 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2060 */ 2061 static void 2062 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2063 struct ice_aqc_list_caps_elem *cap) 2064 { 2065 u32 number = le32_to_cpu(cap->number); 2066 2067 dev_p->num_vsi_allocd_to_host = number; 2068 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2069 dev_p->num_vsi_allocd_to_host); 2070 } 2071 2072 /** 2073 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2074 * @hw: pointer to the HW struct 2075 * @dev_p: pointer to device capabilities structure 2076 * @cap: capability element to parse 2077 * 2078 * Parse ICE_AQC_CAPS_FD for device capabilities. 2079 */ 2080 static void 2081 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2082 struct ice_aqc_list_caps_elem *cap) 2083 { 2084 u32 number = le32_to_cpu(cap->number); 2085 2086 dev_p->num_flow_director_fltr = number; 2087 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2088 dev_p->num_flow_director_fltr); 2089 } 2090 2091 /** 2092 * ice_parse_dev_caps - Parse device capabilities 2093 * @hw: pointer to the HW struct 2094 * @dev_p: pointer to device capabilities structure 2095 * @buf: buffer containing the device capability records 2096 * @cap_count: the number of capabilities 2097 * 2098 * Helper device to parse device (0x000B) capabilities list. For 2099 * capabilities shared between device and function, this relies on 2100 * ice_parse_common_caps. 2101 * 2102 * Loop through the list of provided capabilities and extract the relevant 2103 * data into the device capabilities structured. 2104 */ 2105 static void 2106 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2107 void *buf, u32 cap_count) 2108 { 2109 struct ice_aqc_list_caps_elem *cap_resp; 2110 u32 i; 2111 2112 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2113 2114 memset(dev_p, 0, sizeof(*dev_p)); 2115 2116 for (i = 0; i < cap_count; i++) { 2117 u16 cap = le16_to_cpu(cap_resp[i].cap); 2118 bool found; 2119 2120 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2121 &cap_resp[i], "dev caps"); 2122 2123 switch (cap) { 2124 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2125 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2126 break; 2127 case ICE_AQC_CAPS_VF: 2128 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2129 break; 2130 case ICE_AQC_CAPS_VSI: 2131 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2132 break; 2133 case ICE_AQC_CAPS_FD: 2134 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2135 break; 2136 default: 2137 /* Don't list common capabilities as unknown */ 2138 if (!found) 2139 ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2140 i, cap); 2141 break; 2142 } 2143 } 2144 2145 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2146 } 2147 2148 /** 2149 * ice_aq_list_caps - query function/device capabilities 2150 * @hw: pointer to the HW struct 2151 * @buf: a buffer to hold the capabilities 2152 * @buf_size: size of the buffer 2153 * @cap_count: if not NULL, set to the number of capabilities reported 2154 * @opc: capabilities type to discover, device or function 2155 * @cd: pointer to command details structure or NULL 2156 * 2157 * Get the function (0x000A) or device (0x000B) capabilities description from 2158 * firmware and store it in the buffer. 2159 * 2160 * If the cap_count pointer is not NULL, then it is set to the number of 2161 * capabilities firmware will report. Note that if the buffer size is too 2162 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2163 * cap_count will still be updated in this case. It is recommended that the 2164 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2165 * firmware could return) to avoid this. 2166 */ 2167 enum ice_status 2168 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2169 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2170 { 2171 struct ice_aqc_list_caps *cmd; 2172 struct ice_aq_desc desc; 2173 enum ice_status status; 2174 2175 cmd = &desc.params.get_cap; 2176 2177 if (opc != ice_aqc_opc_list_func_caps && 2178 opc != ice_aqc_opc_list_dev_caps) 2179 return ICE_ERR_PARAM; 2180 2181 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2182 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2183 2184 if (cap_count) 2185 *cap_count = le32_to_cpu(cmd->count); 2186 2187 return status; 2188 } 2189 2190 /** 2191 * ice_discover_dev_caps - Read and extract device capabilities 2192 * @hw: pointer to the hardware structure 2193 * @dev_caps: pointer to device capabilities structure 2194 * 2195 * Read the device capabilities and extract them into the dev_caps structure 2196 * for later use. 2197 */ 2198 enum ice_status 2199 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2200 { 2201 enum ice_status status; 2202 u32 cap_count = 0; 2203 void *cbuf; 2204 2205 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2206 if (!cbuf) 2207 return ICE_ERR_NO_MEMORY; 2208 2209 /* Although the driver doesn't know the number of capabilities the 2210 * device will return, we can simply send a 4KB buffer, the maximum 2211 * possible size that firmware can return. 2212 */ 2213 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2214 2215 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2216 ice_aqc_opc_list_dev_caps, NULL); 2217 if (!status) 2218 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2219 kfree(cbuf); 2220 2221 return status; 2222 } 2223 2224 /** 2225 * ice_discover_func_caps - Read and extract function capabilities 2226 * @hw: pointer to the hardware structure 2227 * @func_caps: pointer to function capabilities structure 2228 * 2229 * Read the function capabilities and extract them into the func_caps structure 2230 * for later use. 2231 */ 2232 static enum ice_status 2233 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2234 { 2235 enum ice_status status; 2236 u32 cap_count = 0; 2237 void *cbuf; 2238 2239 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2240 if (!cbuf) 2241 return ICE_ERR_NO_MEMORY; 2242 2243 /* Although the driver doesn't know the number of capabilities the 2244 * device will return, we can simply send a 4KB buffer, the maximum 2245 * possible size that firmware can return. 2246 */ 2247 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2248 2249 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2250 ice_aqc_opc_list_func_caps, NULL); 2251 if (!status) 2252 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2253 kfree(cbuf); 2254 2255 return status; 2256 } 2257 2258 /** 2259 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2260 * @hw: pointer to the hardware structure 2261 */ 2262 void ice_set_safe_mode_caps(struct ice_hw *hw) 2263 { 2264 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2265 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2266 struct ice_hw_common_caps cached_caps; 2267 u32 num_funcs; 2268 2269 /* cache some func_caps values that should be restored after memset */ 2270 cached_caps = func_caps->common_cap; 2271 2272 /* unset func capabilities */ 2273 memset(func_caps, 0, sizeof(*func_caps)); 2274 2275 #define ICE_RESTORE_FUNC_CAP(name) \ 2276 func_caps->common_cap.name = cached_caps.name 2277 2278 /* restore cached values */ 2279 ICE_RESTORE_FUNC_CAP(valid_functions); 2280 ICE_RESTORE_FUNC_CAP(txq_first_id); 2281 ICE_RESTORE_FUNC_CAP(rxq_first_id); 2282 ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2283 ICE_RESTORE_FUNC_CAP(max_mtu); 2284 ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2285 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2286 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2287 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2288 2289 /* one Tx and one Rx queue in safe mode */ 2290 func_caps->common_cap.num_rxq = 1; 2291 func_caps->common_cap.num_txq = 1; 2292 2293 /* two MSIX vectors, one for traffic and one for misc causes */ 2294 func_caps->common_cap.num_msix_vectors = 2; 2295 func_caps->guar_num_vsi = 1; 2296 2297 /* cache some dev_caps values that should be restored after memset */ 2298 cached_caps = dev_caps->common_cap; 2299 num_funcs = dev_caps->num_funcs; 2300 2301 /* unset dev capabilities */ 2302 memset(dev_caps, 0, sizeof(*dev_caps)); 2303 2304 #define ICE_RESTORE_DEV_CAP(name) \ 2305 dev_caps->common_cap.name = cached_caps.name 2306 2307 /* restore cached values */ 2308 ICE_RESTORE_DEV_CAP(valid_functions); 2309 ICE_RESTORE_DEV_CAP(txq_first_id); 2310 ICE_RESTORE_DEV_CAP(rxq_first_id); 2311 ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2312 ICE_RESTORE_DEV_CAP(max_mtu); 2313 ICE_RESTORE_DEV_CAP(nvm_unified_update); 2314 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 2315 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 2316 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 2317 dev_caps->num_funcs = num_funcs; 2318 2319 /* one Tx and one Rx queue per function in safe mode */ 2320 dev_caps->common_cap.num_rxq = num_funcs; 2321 dev_caps->common_cap.num_txq = num_funcs; 2322 2323 /* two MSIX vectors per function */ 2324 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2325 } 2326 2327 /** 2328 * ice_get_caps - get info about the HW 2329 * @hw: pointer to the hardware structure 2330 */ 2331 enum ice_status ice_get_caps(struct ice_hw *hw) 2332 { 2333 enum ice_status status; 2334 2335 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2336 if (status) 2337 return status; 2338 2339 return ice_discover_func_caps(hw, &hw->func_caps); 2340 } 2341 2342 /** 2343 * ice_aq_manage_mac_write - manage MAC address write command 2344 * @hw: pointer to the HW struct 2345 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2346 * @flags: flags to control write behavior 2347 * @cd: pointer to command details structure or NULL 2348 * 2349 * This function is used to write MAC address to the NVM (0x0108). 2350 */ 2351 enum ice_status 2352 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2353 struct ice_sq_cd *cd) 2354 { 2355 struct ice_aqc_manage_mac_write *cmd; 2356 struct ice_aq_desc desc; 2357 2358 cmd = &desc.params.mac_write; 2359 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2360 2361 cmd->flags = flags; 2362 ether_addr_copy(cmd->mac_addr, mac_addr); 2363 2364 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2365 } 2366 2367 /** 2368 * ice_aq_clear_pxe_mode 2369 * @hw: pointer to the HW struct 2370 * 2371 * Tell the firmware that the driver is taking over from PXE (0x0110). 2372 */ 2373 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2374 { 2375 struct ice_aq_desc desc; 2376 2377 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2378 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2379 2380 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2381 } 2382 2383 /** 2384 * ice_clear_pxe_mode - clear pxe operations mode 2385 * @hw: pointer to the HW struct 2386 * 2387 * Make sure all PXE mode settings are cleared, including things 2388 * like descriptor fetch/write-back mode. 2389 */ 2390 void ice_clear_pxe_mode(struct ice_hw *hw) 2391 { 2392 if (ice_check_sq_alive(hw, &hw->adminq)) 2393 ice_aq_clear_pxe_mode(hw); 2394 } 2395 2396 /** 2397 * ice_get_link_speed_based_on_phy_type - returns link speed 2398 * @phy_type_low: lower part of phy_type 2399 * @phy_type_high: higher part of phy_type 2400 * 2401 * This helper function will convert an entry in PHY type structure 2402 * [phy_type_low, phy_type_high] to its corresponding link speed. 2403 * Note: In the structure of [phy_type_low, phy_type_high], there should 2404 * be one bit set, as this function will convert one PHY type to its 2405 * speed. 2406 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2407 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2408 */ 2409 static u16 2410 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2411 { 2412 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2413 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2414 2415 switch (phy_type_low) { 2416 case ICE_PHY_TYPE_LOW_100BASE_TX: 2417 case ICE_PHY_TYPE_LOW_100M_SGMII: 2418 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2419 break; 2420 case ICE_PHY_TYPE_LOW_1000BASE_T: 2421 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2422 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2423 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2424 case ICE_PHY_TYPE_LOW_1G_SGMII: 2425 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2426 break; 2427 case ICE_PHY_TYPE_LOW_2500BASE_T: 2428 case ICE_PHY_TYPE_LOW_2500BASE_X: 2429 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2430 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2431 break; 2432 case ICE_PHY_TYPE_LOW_5GBASE_T: 2433 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2434 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2435 break; 2436 case ICE_PHY_TYPE_LOW_10GBASE_T: 2437 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2438 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2439 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2440 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2441 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2442 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2443 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2444 break; 2445 case ICE_PHY_TYPE_LOW_25GBASE_T: 2446 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2447 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2448 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2449 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2450 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2451 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2452 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2453 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2454 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2455 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2456 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2457 break; 2458 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2459 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2460 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2461 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2462 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2463 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2464 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2465 break; 2466 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2467 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2468 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2469 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2470 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2471 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2472 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2473 case ICE_PHY_TYPE_LOW_50G_AUI2: 2474 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2475 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2476 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2477 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2478 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2479 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2480 case ICE_PHY_TYPE_LOW_50G_AUI1: 2481 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2482 break; 2483 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2484 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2485 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2486 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2487 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2488 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2489 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2490 case ICE_PHY_TYPE_LOW_100G_AUI4: 2491 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2492 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2493 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2494 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2495 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2496 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2497 break; 2498 default: 2499 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2500 break; 2501 } 2502 2503 switch (phy_type_high) { 2504 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2505 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2506 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2507 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2508 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2509 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2510 break; 2511 default: 2512 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2513 break; 2514 } 2515 2516 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2517 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2518 return ICE_AQ_LINK_SPEED_UNKNOWN; 2519 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2520 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2521 return ICE_AQ_LINK_SPEED_UNKNOWN; 2522 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2523 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2524 return speed_phy_type_low; 2525 else 2526 return speed_phy_type_high; 2527 } 2528 2529 /** 2530 * ice_update_phy_type 2531 * @phy_type_low: pointer to the lower part of phy_type 2532 * @phy_type_high: pointer to the higher part of phy_type 2533 * @link_speeds_bitmap: targeted link speeds bitmap 2534 * 2535 * Note: For the link_speeds_bitmap structure, you can check it at 2536 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2537 * link_speeds_bitmap include multiple speeds. 2538 * 2539 * Each entry in this [phy_type_low, phy_type_high] structure will 2540 * present a certain link speed. This helper function will turn on bits 2541 * in [phy_type_low, phy_type_high] structure based on the value of 2542 * link_speeds_bitmap input parameter. 2543 */ 2544 void 2545 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2546 u16 link_speeds_bitmap) 2547 { 2548 u64 pt_high; 2549 u64 pt_low; 2550 int index; 2551 u16 speed; 2552 2553 /* We first check with low part of phy_type */ 2554 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2555 pt_low = BIT_ULL(index); 2556 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2557 2558 if (link_speeds_bitmap & speed) 2559 *phy_type_low |= BIT_ULL(index); 2560 } 2561 2562 /* We then check with high part of phy_type */ 2563 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2564 pt_high = BIT_ULL(index); 2565 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2566 2567 if (link_speeds_bitmap & speed) 2568 *phy_type_high |= BIT_ULL(index); 2569 } 2570 } 2571 2572 /** 2573 * ice_aq_set_phy_cfg 2574 * @hw: pointer to the HW struct 2575 * @pi: port info structure of the interested logical port 2576 * @cfg: structure with PHY configuration data to be set 2577 * @cd: pointer to command details structure or NULL 2578 * 2579 * Set the various PHY configuration parameters supported on the Port. 2580 * One or more of the Set PHY config parameters may be ignored in an MFP 2581 * mode as the PF may not have the privilege to set some of the PHY Config 2582 * parameters. This status will be indicated by the command response (0x0601). 2583 */ 2584 enum ice_status 2585 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2586 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2587 { 2588 struct ice_aq_desc desc; 2589 enum ice_status status; 2590 2591 if (!cfg) 2592 return ICE_ERR_PARAM; 2593 2594 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2595 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2596 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2597 cfg->caps); 2598 2599 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2600 } 2601 2602 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2603 desc.params.set_phy.lport_num = pi->lport; 2604 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2605 2606 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 2607 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 2608 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 2609 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 2610 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 2611 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 2612 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 2613 cfg->low_power_ctrl_an); 2614 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 2615 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 2616 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 2617 cfg->link_fec_opt); 2618 2619 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2620 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 2621 status = 0; 2622 2623 if (!status) 2624 pi->phy.curr_user_phy_cfg = *cfg; 2625 2626 return status; 2627 } 2628 2629 /** 2630 * ice_update_link_info - update status of the HW network link 2631 * @pi: port info structure of the interested logical port 2632 */ 2633 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2634 { 2635 struct ice_link_status *li; 2636 enum ice_status status; 2637 2638 if (!pi) 2639 return ICE_ERR_PARAM; 2640 2641 li = &pi->phy.link_info; 2642 2643 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2644 if (status) 2645 return status; 2646 2647 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2648 struct ice_aqc_get_phy_caps_data *pcaps; 2649 struct ice_hw *hw; 2650 2651 hw = pi->hw; 2652 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 2653 GFP_KERNEL); 2654 if (!pcaps) 2655 return ICE_ERR_NO_MEMORY; 2656 2657 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, 2658 pcaps, NULL); 2659 2660 devm_kfree(ice_hw_to_dev(hw), pcaps); 2661 } 2662 2663 return status; 2664 } 2665 2666 /** 2667 * ice_cache_phy_user_req 2668 * @pi: port information structure 2669 * @cache_data: PHY logging data 2670 * @cache_mode: PHY logging mode 2671 * 2672 * Log the user request on (FC, FEC, SPEED) for later use. 2673 */ 2674 static void 2675 ice_cache_phy_user_req(struct ice_port_info *pi, 2676 struct ice_phy_cache_mode_data cache_data, 2677 enum ice_phy_cache_mode cache_mode) 2678 { 2679 if (!pi) 2680 return; 2681 2682 switch (cache_mode) { 2683 case ICE_FC_MODE: 2684 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 2685 break; 2686 case ICE_SPEED_MODE: 2687 pi->phy.curr_user_speed_req = 2688 cache_data.data.curr_user_speed_req; 2689 break; 2690 case ICE_FEC_MODE: 2691 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 2692 break; 2693 default: 2694 break; 2695 } 2696 } 2697 2698 /** 2699 * ice_caps_to_fc_mode 2700 * @caps: PHY capabilities 2701 * 2702 * Convert PHY FC capabilities to ice FC mode 2703 */ 2704 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 2705 { 2706 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 2707 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2708 return ICE_FC_FULL; 2709 2710 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 2711 return ICE_FC_TX_PAUSE; 2712 2713 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2714 return ICE_FC_RX_PAUSE; 2715 2716 return ICE_FC_NONE; 2717 } 2718 2719 /** 2720 * ice_caps_to_fec_mode 2721 * @caps: PHY capabilities 2722 * @fec_options: Link FEC options 2723 * 2724 * Convert PHY FEC capabilities to ice FEC mode 2725 */ 2726 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 2727 { 2728 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 2729 return ICE_FEC_AUTO; 2730 2731 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2732 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2733 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 2734 ICE_AQC_PHY_FEC_25G_KR_REQ)) 2735 return ICE_FEC_BASER; 2736 2737 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2738 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 2739 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 2740 return ICE_FEC_RS; 2741 2742 return ICE_FEC_NONE; 2743 } 2744 2745 /** 2746 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 2747 * @pi: port information structure 2748 * @cfg: PHY configuration data to set FC mode 2749 * @req_mode: FC mode to configure 2750 */ 2751 enum ice_status 2752 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 2753 enum ice_fc_mode req_mode) 2754 { 2755 struct ice_phy_cache_mode_data cache_data; 2756 u8 pause_mask = 0x0; 2757 2758 if (!pi || !cfg) 2759 return ICE_ERR_BAD_PTR; 2760 2761 switch (req_mode) { 2762 case ICE_FC_FULL: 2763 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2764 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2765 break; 2766 case ICE_FC_RX_PAUSE: 2767 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2768 break; 2769 case ICE_FC_TX_PAUSE: 2770 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2771 break; 2772 default: 2773 break; 2774 } 2775 2776 /* clear the old pause settings */ 2777 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2778 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2779 2780 /* set the new capabilities */ 2781 cfg->caps |= pause_mask; 2782 2783 /* Cache user FC request */ 2784 cache_data.data.curr_user_fc_req = req_mode; 2785 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 2786 2787 return 0; 2788 } 2789 2790 /** 2791 * ice_set_fc 2792 * @pi: port information structure 2793 * @aq_failures: pointer to status code, specific to ice_set_fc routine 2794 * @ena_auto_link_update: enable automatic link update 2795 * 2796 * Set the requested flow control mode. 2797 */ 2798 enum ice_status 2799 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2800 { 2801 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2802 struct ice_aqc_get_phy_caps_data *pcaps; 2803 enum ice_status status; 2804 struct ice_hw *hw; 2805 2806 if (!pi || !aq_failures) 2807 return ICE_ERR_BAD_PTR; 2808 2809 *aq_failures = 0; 2810 hw = pi->hw; 2811 2812 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 2813 if (!pcaps) 2814 return ICE_ERR_NO_MEMORY; 2815 2816 /* Get the current PHY config */ 2817 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 2818 NULL); 2819 if (status) { 2820 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2821 goto out; 2822 } 2823 2824 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 2825 2826 /* Configure the set PHY data */ 2827 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 2828 if (status) 2829 goto out; 2830 2831 /* If the capabilities have changed, then set the new config */ 2832 if (cfg.caps != pcaps->caps) { 2833 int retry_count, retry_max = 10; 2834 2835 /* Auto restart link so settings take effect */ 2836 if (ena_auto_link_update) 2837 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2838 2839 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 2840 if (status) { 2841 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 2842 goto out; 2843 } 2844 2845 /* Update the link info 2846 * It sometimes takes a really long time for link to 2847 * come back from the atomic reset. Thus, we wait a 2848 * little bit. 2849 */ 2850 for (retry_count = 0; retry_count < retry_max; retry_count++) { 2851 status = ice_update_link_info(pi); 2852 2853 if (!status) 2854 break; 2855 2856 mdelay(100); 2857 } 2858 2859 if (status) 2860 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 2861 } 2862 2863 out: 2864 devm_kfree(ice_hw_to_dev(hw), pcaps); 2865 return status; 2866 } 2867 2868 /** 2869 * ice_phy_caps_equals_cfg 2870 * @phy_caps: PHY capabilities 2871 * @phy_cfg: PHY configuration 2872 * 2873 * Helper function to determine if PHY capabilities matches PHY 2874 * configuration 2875 */ 2876 bool 2877 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 2878 struct ice_aqc_set_phy_cfg_data *phy_cfg) 2879 { 2880 u8 caps_mask, cfg_mask; 2881 2882 if (!phy_caps || !phy_cfg) 2883 return false; 2884 2885 /* These bits are not common between capabilities and configuration. 2886 * Do not use them to determine equality. 2887 */ 2888 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 2889 ICE_AQC_GET_PHY_EN_MOD_QUAL); 2890 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2891 2892 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 2893 phy_caps->phy_type_high != phy_cfg->phy_type_high || 2894 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 2895 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 2896 phy_caps->eee_cap != phy_cfg->eee_cap || 2897 phy_caps->eeer_value != phy_cfg->eeer_value || 2898 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 2899 return false; 2900 2901 return true; 2902 } 2903 2904 /** 2905 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 2906 * @pi: port information structure 2907 * @caps: PHY ability structure to copy date from 2908 * @cfg: PHY configuration structure to copy data to 2909 * 2910 * Helper function to copy AQC PHY get ability data to PHY set configuration 2911 * data structure 2912 */ 2913 void 2914 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 2915 struct ice_aqc_get_phy_caps_data *caps, 2916 struct ice_aqc_set_phy_cfg_data *cfg) 2917 { 2918 if (!pi || !caps || !cfg) 2919 return; 2920 2921 memset(cfg, 0, sizeof(*cfg)); 2922 cfg->phy_type_low = caps->phy_type_low; 2923 cfg->phy_type_high = caps->phy_type_high; 2924 cfg->caps = caps->caps; 2925 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 2926 cfg->eee_cap = caps->eee_cap; 2927 cfg->eeer_value = caps->eeer_value; 2928 cfg->link_fec_opt = caps->link_fec_options; 2929 cfg->module_compliance_enforcement = 2930 caps->module_compliance_enforcement; 2931 2932 if (ice_fw_supports_link_override(pi->hw)) { 2933 struct ice_link_default_override_tlv tlv; 2934 2935 if (ice_get_link_default_override(&tlv, pi)) 2936 return; 2937 2938 if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) 2939 cfg->module_compliance_enforcement |= 2940 ICE_LINK_OVERRIDE_STRICT_MODE; 2941 } 2942 } 2943 2944 /** 2945 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 2946 * @pi: port information structure 2947 * @cfg: PHY configuration data to set FEC mode 2948 * @fec: FEC mode to configure 2949 */ 2950 enum ice_status 2951 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 2952 enum ice_fec_mode fec) 2953 { 2954 struct ice_aqc_get_phy_caps_data *pcaps; 2955 enum ice_status status; 2956 2957 if (!pi || !cfg) 2958 return ICE_ERR_BAD_PTR; 2959 2960 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 2961 if (!pcaps) 2962 return ICE_ERR_NO_MEMORY; 2963 2964 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps, 2965 NULL); 2966 if (status) 2967 goto out; 2968 2969 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 2970 cfg->link_fec_opt = pcaps->link_fec_options; 2971 2972 switch (fec) { 2973 case ICE_FEC_BASER: 2974 /* Clear RS bits, and AND BASE-R ability 2975 * bits and OR request bits. 2976 */ 2977 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2978 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 2979 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2980 ICE_AQC_PHY_FEC_25G_KR_REQ; 2981 break; 2982 case ICE_FEC_RS: 2983 /* Clear BASE-R bits, and AND RS ability 2984 * bits and OR request bits. 2985 */ 2986 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 2987 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2988 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 2989 break; 2990 case ICE_FEC_NONE: 2991 /* Clear all FEC option bits. */ 2992 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 2993 break; 2994 case ICE_FEC_AUTO: 2995 /* AND auto FEC bit, and all caps bits. */ 2996 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 2997 cfg->link_fec_opt |= pcaps->link_fec_options; 2998 break; 2999 default: 3000 status = ICE_ERR_PARAM; 3001 break; 3002 } 3003 3004 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) { 3005 struct ice_link_default_override_tlv tlv; 3006 3007 if (ice_get_link_default_override(&tlv, pi)) 3008 goto out; 3009 3010 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3011 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3012 cfg->link_fec_opt = tlv.fec_options; 3013 } 3014 3015 out: 3016 kfree(pcaps); 3017 3018 return status; 3019 } 3020 3021 /** 3022 * ice_get_link_status - get status of the HW network link 3023 * @pi: port information structure 3024 * @link_up: pointer to bool (true/false = linkup/linkdown) 3025 * 3026 * Variable link_up is true if link is up, false if link is down. 3027 * The variable link_up is invalid if status is non zero. As a 3028 * result of this call, link status reporting becomes enabled 3029 */ 3030 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3031 { 3032 struct ice_phy_info *phy_info; 3033 enum ice_status status = 0; 3034 3035 if (!pi || !link_up) 3036 return ICE_ERR_PARAM; 3037 3038 phy_info = &pi->phy; 3039 3040 if (phy_info->get_link_info) { 3041 status = ice_update_link_info(pi); 3042 3043 if (status) 3044 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 3045 status); 3046 } 3047 3048 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3049 3050 return status; 3051 } 3052 3053 /** 3054 * ice_aq_set_link_restart_an 3055 * @pi: pointer to the port information structure 3056 * @ena_link: if true: enable link, if false: disable link 3057 * @cd: pointer to command details structure or NULL 3058 * 3059 * Sets up the link and restarts the Auto-Negotiation over the link. 3060 */ 3061 enum ice_status 3062 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3063 struct ice_sq_cd *cd) 3064 { 3065 struct ice_aqc_restart_an *cmd; 3066 struct ice_aq_desc desc; 3067 3068 cmd = &desc.params.restart_an; 3069 3070 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3071 3072 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3073 cmd->lport_num = pi->lport; 3074 if (ena_link) 3075 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3076 else 3077 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3078 3079 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3080 } 3081 3082 /** 3083 * ice_aq_set_event_mask 3084 * @hw: pointer to the HW struct 3085 * @port_num: port number of the physical function 3086 * @mask: event mask to be set 3087 * @cd: pointer to command details structure or NULL 3088 * 3089 * Set event mask (0x0613) 3090 */ 3091 enum ice_status 3092 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3093 struct ice_sq_cd *cd) 3094 { 3095 struct ice_aqc_set_event_mask *cmd; 3096 struct ice_aq_desc desc; 3097 3098 cmd = &desc.params.set_event_mask; 3099 3100 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3101 3102 cmd->lport_num = port_num; 3103 3104 cmd->event_mask = cpu_to_le16(mask); 3105 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3106 } 3107 3108 /** 3109 * ice_aq_set_mac_loopback 3110 * @hw: pointer to the HW struct 3111 * @ena_lpbk: Enable or Disable loopback 3112 * @cd: pointer to command details structure or NULL 3113 * 3114 * Enable/disable loopback on a given port 3115 */ 3116 enum ice_status 3117 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3118 { 3119 struct ice_aqc_set_mac_lb *cmd; 3120 struct ice_aq_desc desc; 3121 3122 cmd = &desc.params.set_mac_lb; 3123 3124 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3125 if (ena_lpbk) 3126 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3127 3128 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3129 } 3130 3131 /** 3132 * ice_aq_set_port_id_led 3133 * @pi: pointer to the port information 3134 * @is_orig_mode: is this LED set to original mode (by the net-list) 3135 * @cd: pointer to command details structure or NULL 3136 * 3137 * Set LED value for the given port (0x06e9) 3138 */ 3139 enum ice_status 3140 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3141 struct ice_sq_cd *cd) 3142 { 3143 struct ice_aqc_set_port_id_led *cmd; 3144 struct ice_hw *hw = pi->hw; 3145 struct ice_aq_desc desc; 3146 3147 cmd = &desc.params.set_port_id_led; 3148 3149 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3150 3151 if (is_orig_mode) 3152 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3153 else 3154 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3155 3156 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3157 } 3158 3159 /** 3160 * ice_aq_sff_eeprom 3161 * @hw: pointer to the HW struct 3162 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3163 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3164 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3165 * @page: QSFP page 3166 * @set_page: set or ignore the page 3167 * @data: pointer to data buffer to be read/written to the I2C device. 3168 * @length: 1-16 for read, 1 for write. 3169 * @write: 0 read, 1 for write. 3170 * @cd: pointer to command details structure or NULL 3171 * 3172 * Read/Write SFF EEPROM (0x06EE) 3173 */ 3174 enum ice_status 3175 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3176 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3177 bool write, struct ice_sq_cd *cd) 3178 { 3179 struct ice_aqc_sff_eeprom *cmd; 3180 struct ice_aq_desc desc; 3181 enum ice_status status; 3182 3183 if (!data || (mem_addr & 0xff00)) 3184 return ICE_ERR_PARAM; 3185 3186 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3187 cmd = &desc.params.read_write_sff_param; 3188 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF); 3189 cmd->lport_num = (u8)(lport & 0xff); 3190 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3191 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 3192 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3193 ((set_page << 3194 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3195 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3196 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3197 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3198 if (write) 3199 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 3200 3201 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3202 return status; 3203 } 3204 3205 /** 3206 * __ice_aq_get_set_rss_lut 3207 * @hw: pointer to the hardware structure 3208 * @vsi_id: VSI FW index 3209 * @lut_type: LUT table type 3210 * @lut: pointer to the LUT buffer provided by the caller 3211 * @lut_size: size of the LUT buffer 3212 * @glob_lut_idx: global LUT index 3213 * @set: set true to set the table, false to get the table 3214 * 3215 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3216 */ 3217 static enum ice_status 3218 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 3219 u16 lut_size, u8 glob_lut_idx, bool set) 3220 { 3221 struct ice_aqc_get_set_rss_lut *cmd_resp; 3222 struct ice_aq_desc desc; 3223 enum ice_status status; 3224 u16 flags = 0; 3225 3226 cmd_resp = &desc.params.get_set_rss_lut; 3227 3228 if (set) { 3229 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3230 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3231 } else { 3232 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3233 } 3234 3235 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3236 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3237 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3238 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3239 3240 switch (lut_type) { 3241 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3242 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3243 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3244 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3245 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3246 break; 3247 default: 3248 status = ICE_ERR_PARAM; 3249 goto ice_aq_get_set_rss_lut_exit; 3250 } 3251 3252 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3253 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3254 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3255 3256 if (!set) 3257 goto ice_aq_get_set_rss_lut_send; 3258 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3259 if (!set) 3260 goto ice_aq_get_set_rss_lut_send; 3261 } else { 3262 goto ice_aq_get_set_rss_lut_send; 3263 } 3264 3265 /* LUT size is only valid for Global and PF table types */ 3266 switch (lut_size) { 3267 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3268 break; 3269 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3270 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3271 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3272 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3273 break; 3274 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3275 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3276 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3277 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3278 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3279 break; 3280 } 3281 fallthrough; 3282 default: 3283 status = ICE_ERR_PARAM; 3284 goto ice_aq_get_set_rss_lut_exit; 3285 } 3286 3287 ice_aq_get_set_rss_lut_send: 3288 cmd_resp->flags = cpu_to_le16(flags); 3289 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3290 3291 ice_aq_get_set_rss_lut_exit: 3292 return status; 3293 } 3294 3295 /** 3296 * ice_aq_get_rss_lut 3297 * @hw: pointer to the hardware structure 3298 * @vsi_handle: software VSI handle 3299 * @lut_type: LUT table type 3300 * @lut: pointer to the LUT buffer provided by the caller 3301 * @lut_size: size of the LUT buffer 3302 * 3303 * get the RSS lookup table, PF or VSI type 3304 */ 3305 enum ice_status 3306 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 3307 u8 *lut, u16 lut_size) 3308 { 3309 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3310 return ICE_ERR_PARAM; 3311 3312 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3313 lut_type, lut, lut_size, 0, false); 3314 } 3315 3316 /** 3317 * ice_aq_set_rss_lut 3318 * @hw: pointer to the hardware structure 3319 * @vsi_handle: software VSI handle 3320 * @lut_type: LUT table type 3321 * @lut: pointer to the LUT buffer provided by the caller 3322 * @lut_size: size of the LUT buffer 3323 * 3324 * set the RSS lookup table, PF or VSI type 3325 */ 3326 enum ice_status 3327 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 3328 u8 *lut, u16 lut_size) 3329 { 3330 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3331 return ICE_ERR_PARAM; 3332 3333 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3334 lut_type, lut, lut_size, 0, true); 3335 } 3336 3337 /** 3338 * __ice_aq_get_set_rss_key 3339 * @hw: pointer to the HW struct 3340 * @vsi_id: VSI FW index 3341 * @key: pointer to key info struct 3342 * @set: set true to set the key, false to get the key 3343 * 3344 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3345 */ 3346 static enum 3347 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3348 struct ice_aqc_get_set_rss_keys *key, 3349 bool set) 3350 { 3351 struct ice_aqc_get_set_rss_key *cmd_resp; 3352 u16 key_size = sizeof(*key); 3353 struct ice_aq_desc desc; 3354 3355 cmd_resp = &desc.params.get_set_rss_key; 3356 3357 if (set) { 3358 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3359 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3360 } else { 3361 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3362 } 3363 3364 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3365 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3366 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3367 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3368 3369 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3370 } 3371 3372 /** 3373 * ice_aq_get_rss_key 3374 * @hw: pointer to the HW struct 3375 * @vsi_handle: software VSI handle 3376 * @key: pointer to key info struct 3377 * 3378 * get the RSS key per VSI 3379 */ 3380 enum ice_status 3381 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3382 struct ice_aqc_get_set_rss_keys *key) 3383 { 3384 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 3385 return ICE_ERR_PARAM; 3386 3387 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3388 key, false); 3389 } 3390 3391 /** 3392 * ice_aq_set_rss_key 3393 * @hw: pointer to the HW struct 3394 * @vsi_handle: software VSI handle 3395 * @keys: pointer to key info struct 3396 * 3397 * set the RSS key per VSI 3398 */ 3399 enum ice_status 3400 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3401 struct ice_aqc_get_set_rss_keys *keys) 3402 { 3403 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 3404 return ICE_ERR_PARAM; 3405 3406 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3407 keys, true); 3408 } 3409 3410 /** 3411 * ice_aq_add_lan_txq 3412 * @hw: pointer to the hardware structure 3413 * @num_qgrps: Number of added queue groups 3414 * @qg_list: list of queue groups to be added 3415 * @buf_size: size of buffer for indirect command 3416 * @cd: pointer to command details structure or NULL 3417 * 3418 * Add Tx LAN queue (0x0C30) 3419 * 3420 * NOTE: 3421 * Prior to calling add Tx LAN queue: 3422 * Initialize the following as part of the Tx queue context: 3423 * Completion queue ID if the queue uses Completion queue, Quanta profile, 3424 * Cache profile and Packet shaper profile. 3425 * 3426 * After add Tx LAN queue AQ command is completed: 3427 * Interrupts should be associated with specific queues, 3428 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3429 * flow. 3430 */ 3431 static enum ice_status 3432 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3433 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3434 struct ice_sq_cd *cd) 3435 { 3436 struct ice_aqc_add_tx_qgrp *list; 3437 struct ice_aqc_add_txqs *cmd; 3438 struct ice_aq_desc desc; 3439 u16 i, sum_size = 0; 3440 3441 cmd = &desc.params.add_txqs; 3442 3443 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3444 3445 if (!qg_list) 3446 return ICE_ERR_PARAM; 3447 3448 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3449 return ICE_ERR_PARAM; 3450 3451 for (i = 0, list = qg_list; i < num_qgrps; i++) { 3452 sum_size += struct_size(list, txqs, list->num_txqs); 3453 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 3454 list->num_txqs); 3455 } 3456 3457 if (buf_size != sum_size) 3458 return ICE_ERR_PARAM; 3459 3460 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3461 3462 cmd->num_qgrps = num_qgrps; 3463 3464 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3465 } 3466 3467 /** 3468 * ice_aq_dis_lan_txq 3469 * @hw: pointer to the hardware structure 3470 * @num_qgrps: number of groups in the list 3471 * @qg_list: the list of groups to disable 3472 * @buf_size: the total size of the qg_list buffer in bytes 3473 * @rst_src: if called due to reset, specifies the reset source 3474 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3475 * @cd: pointer to command details structure or NULL 3476 * 3477 * Disable LAN Tx queue (0x0C31) 3478 */ 3479 static enum ice_status 3480 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3481 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3482 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3483 struct ice_sq_cd *cd) 3484 { 3485 struct ice_aqc_dis_txq_item *item; 3486 struct ice_aqc_dis_txqs *cmd; 3487 struct ice_aq_desc desc; 3488 enum ice_status status; 3489 u16 i, sz = 0; 3490 3491 cmd = &desc.params.dis_txqs; 3492 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3493 3494 /* qg_list can be NULL only in VM/VF reset flow */ 3495 if (!qg_list && !rst_src) 3496 return ICE_ERR_PARAM; 3497 3498 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3499 return ICE_ERR_PARAM; 3500 3501 cmd->num_entries = num_qgrps; 3502 3503 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3504 ICE_AQC_Q_DIS_TIMEOUT_M); 3505 3506 switch (rst_src) { 3507 case ICE_VM_RESET: 3508 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3509 cmd->vmvf_and_timeout |= 3510 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3511 break; 3512 case ICE_VF_RESET: 3513 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 3514 /* In this case, FW expects vmvf_num to be absolute VF ID */ 3515 cmd->vmvf_and_timeout |= 3516 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 3517 ICE_AQC_Q_DIS_VMVF_NUM_M); 3518 break; 3519 case ICE_NO_RESET: 3520 default: 3521 break; 3522 } 3523 3524 /* flush pipe on time out */ 3525 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3526 /* If no queue group info, we are in a reset flow. Issue the AQ */ 3527 if (!qg_list) 3528 goto do_aq; 3529 3530 /* set RD bit to indicate that command buffer is provided by the driver 3531 * and it needs to be read by the firmware 3532 */ 3533 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3534 3535 for (i = 0, item = qg_list; i < num_qgrps; i++) { 3536 u16 item_size = struct_size(item, q_id, item->num_qs); 3537 3538 /* If the num of queues is even, add 2 bytes of padding */ 3539 if ((item->num_qs % 2) == 0) 3540 item_size += 2; 3541 3542 sz += item_size; 3543 3544 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 3545 } 3546 3547 if (buf_size != sz) 3548 return ICE_ERR_PARAM; 3549 3550 do_aq: 3551 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3552 if (status) { 3553 if (!qg_list) 3554 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 3555 vmvf_num, hw->adminq.sq_last_status); 3556 else 3557 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 3558 le16_to_cpu(qg_list[0].q_id[0]), 3559 hw->adminq.sq_last_status); 3560 } 3561 return status; 3562 } 3563 3564 /* End of FW Admin Queue command wrappers */ 3565 3566 /** 3567 * ice_write_byte - write a byte to a packed context structure 3568 * @src_ctx: the context structure to read from 3569 * @dest_ctx: the context to be written to 3570 * @ce_info: a description of the struct to be filled 3571 */ 3572 static void 3573 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3574 { 3575 u8 src_byte, dest_byte, mask; 3576 u8 *from, *dest; 3577 u16 shift_width; 3578 3579 /* copy from the next struct field */ 3580 from = src_ctx + ce_info->offset; 3581 3582 /* prepare the bits and mask */ 3583 shift_width = ce_info->lsb % 8; 3584 mask = (u8)(BIT(ce_info->width) - 1); 3585 3586 src_byte = *from; 3587 src_byte &= mask; 3588 3589 /* shift to correct alignment */ 3590 mask <<= shift_width; 3591 src_byte <<= shift_width; 3592 3593 /* get the current bits from the target bit string */ 3594 dest = dest_ctx + (ce_info->lsb / 8); 3595 3596 memcpy(&dest_byte, dest, sizeof(dest_byte)); 3597 3598 dest_byte &= ~mask; /* get the bits not changing */ 3599 dest_byte |= src_byte; /* add in the new bits */ 3600 3601 /* put it all back */ 3602 memcpy(dest, &dest_byte, sizeof(dest_byte)); 3603 } 3604 3605 /** 3606 * ice_write_word - write a word to a packed context structure 3607 * @src_ctx: the context structure to read from 3608 * @dest_ctx: the context to be written to 3609 * @ce_info: a description of the struct to be filled 3610 */ 3611 static void 3612 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3613 { 3614 u16 src_word, mask; 3615 __le16 dest_word; 3616 u8 *from, *dest; 3617 u16 shift_width; 3618 3619 /* copy from the next struct field */ 3620 from = src_ctx + ce_info->offset; 3621 3622 /* prepare the bits and mask */ 3623 shift_width = ce_info->lsb % 8; 3624 mask = BIT(ce_info->width) - 1; 3625 3626 /* don't swizzle the bits until after the mask because the mask bits 3627 * will be in a different bit position on big endian machines 3628 */ 3629 src_word = *(u16 *)from; 3630 src_word &= mask; 3631 3632 /* shift to correct alignment */ 3633 mask <<= shift_width; 3634 src_word <<= shift_width; 3635 3636 /* get the current bits from the target bit string */ 3637 dest = dest_ctx + (ce_info->lsb / 8); 3638 3639 memcpy(&dest_word, dest, sizeof(dest_word)); 3640 3641 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 3642 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 3643 3644 /* put it all back */ 3645 memcpy(dest, &dest_word, sizeof(dest_word)); 3646 } 3647 3648 /** 3649 * ice_write_dword - write a dword to a packed context structure 3650 * @src_ctx: the context structure to read from 3651 * @dest_ctx: the context to be written to 3652 * @ce_info: a description of the struct to be filled 3653 */ 3654 static void 3655 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3656 { 3657 u32 src_dword, mask; 3658 __le32 dest_dword; 3659 u8 *from, *dest; 3660 u16 shift_width; 3661 3662 /* copy from the next struct field */ 3663 from = src_ctx + ce_info->offset; 3664 3665 /* prepare the bits and mask */ 3666 shift_width = ce_info->lsb % 8; 3667 3668 /* if the field width is exactly 32 on an x86 machine, then the shift 3669 * operation will not work because the SHL instructions count is masked 3670 * to 5 bits so the shift will do nothing 3671 */ 3672 if (ce_info->width < 32) 3673 mask = BIT(ce_info->width) - 1; 3674 else 3675 mask = (u32)~0; 3676 3677 /* don't swizzle the bits until after the mask because the mask bits 3678 * will be in a different bit position on big endian machines 3679 */ 3680 src_dword = *(u32 *)from; 3681 src_dword &= mask; 3682 3683 /* shift to correct alignment */ 3684 mask <<= shift_width; 3685 src_dword <<= shift_width; 3686 3687 /* get the current bits from the target bit string */ 3688 dest = dest_ctx + (ce_info->lsb / 8); 3689 3690 memcpy(&dest_dword, dest, sizeof(dest_dword)); 3691 3692 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 3693 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 3694 3695 /* put it all back */ 3696 memcpy(dest, &dest_dword, sizeof(dest_dword)); 3697 } 3698 3699 /** 3700 * ice_write_qword - write a qword to a packed context structure 3701 * @src_ctx: the context structure to read from 3702 * @dest_ctx: the context to be written to 3703 * @ce_info: a description of the struct to be filled 3704 */ 3705 static void 3706 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3707 { 3708 u64 src_qword, mask; 3709 __le64 dest_qword; 3710 u8 *from, *dest; 3711 u16 shift_width; 3712 3713 /* copy from the next struct field */ 3714 from = src_ctx + ce_info->offset; 3715 3716 /* prepare the bits and mask */ 3717 shift_width = ce_info->lsb % 8; 3718 3719 /* if the field width is exactly 64 on an x86 machine, then the shift 3720 * operation will not work because the SHL instructions count is masked 3721 * to 6 bits so the shift will do nothing 3722 */ 3723 if (ce_info->width < 64) 3724 mask = BIT_ULL(ce_info->width) - 1; 3725 else 3726 mask = (u64)~0; 3727 3728 /* don't swizzle the bits until after the mask because the mask bits 3729 * will be in a different bit position on big endian machines 3730 */ 3731 src_qword = *(u64 *)from; 3732 src_qword &= mask; 3733 3734 /* shift to correct alignment */ 3735 mask <<= shift_width; 3736 src_qword <<= shift_width; 3737 3738 /* get the current bits from the target bit string */ 3739 dest = dest_ctx + (ce_info->lsb / 8); 3740 3741 memcpy(&dest_qword, dest, sizeof(dest_qword)); 3742 3743 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 3744 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 3745 3746 /* put it all back */ 3747 memcpy(dest, &dest_qword, sizeof(dest_qword)); 3748 } 3749 3750 /** 3751 * ice_set_ctx - set context bits in packed structure 3752 * @hw: pointer to the hardware structure 3753 * @src_ctx: pointer to a generic non-packed context structure 3754 * @dest_ctx: pointer to memory for the packed structure 3755 * @ce_info: a description of the structure to be transformed 3756 */ 3757 enum ice_status 3758 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 3759 const struct ice_ctx_ele *ce_info) 3760 { 3761 int f; 3762 3763 for (f = 0; ce_info[f].width; f++) { 3764 /* We have to deal with each element of the FW response 3765 * using the correct size so that we are correct regardless 3766 * of the endianness of the machine. 3767 */ 3768 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 3769 ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 3770 f, ce_info[f].width, ce_info[f].size_of); 3771 continue; 3772 } 3773 switch (ce_info[f].size_of) { 3774 case sizeof(u8): 3775 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 3776 break; 3777 case sizeof(u16): 3778 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 3779 break; 3780 case sizeof(u32): 3781 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 3782 break; 3783 case sizeof(u64): 3784 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 3785 break; 3786 default: 3787 return ICE_ERR_INVAL_SIZE; 3788 } 3789 } 3790 3791 return 0; 3792 } 3793 3794 /** 3795 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 3796 * @hw: pointer to the HW struct 3797 * @vsi_handle: software VSI handle 3798 * @tc: TC number 3799 * @q_handle: software queue handle 3800 */ 3801 struct ice_q_ctx * 3802 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 3803 { 3804 struct ice_vsi_ctx *vsi; 3805 struct ice_q_ctx *q_ctx; 3806 3807 vsi = ice_get_vsi_ctx(hw, vsi_handle); 3808 if (!vsi) 3809 return NULL; 3810 if (q_handle >= vsi->num_lan_q_entries[tc]) 3811 return NULL; 3812 if (!vsi->lan_q_ctx[tc]) 3813 return NULL; 3814 q_ctx = vsi->lan_q_ctx[tc]; 3815 return &q_ctx[q_handle]; 3816 } 3817 3818 /** 3819 * ice_ena_vsi_txq 3820 * @pi: port information structure 3821 * @vsi_handle: software VSI handle 3822 * @tc: TC number 3823 * @q_handle: software queue handle 3824 * @num_qgrps: Number of added queue groups 3825 * @buf: list of queue groups to be added 3826 * @buf_size: size of buffer for indirect command 3827 * @cd: pointer to command details structure or NULL 3828 * 3829 * This function adds one LAN queue 3830 */ 3831 enum ice_status 3832 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 3833 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 3834 struct ice_sq_cd *cd) 3835 { 3836 struct ice_aqc_txsched_elem_data node = { 0 }; 3837 struct ice_sched_node *parent; 3838 struct ice_q_ctx *q_ctx; 3839 enum ice_status status; 3840 struct ice_hw *hw; 3841 3842 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3843 return ICE_ERR_CFG; 3844 3845 if (num_qgrps > 1 || buf->num_txqs > 1) 3846 return ICE_ERR_MAX_LIMIT; 3847 3848 hw = pi->hw; 3849 3850 if (!ice_is_vsi_valid(hw, vsi_handle)) 3851 return ICE_ERR_PARAM; 3852 3853 mutex_lock(&pi->sched_lock); 3854 3855 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 3856 if (!q_ctx) { 3857 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 3858 q_handle); 3859 status = ICE_ERR_PARAM; 3860 goto ena_txq_exit; 3861 } 3862 3863 /* find a parent node */ 3864 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 3865 ICE_SCHED_NODE_OWNER_LAN); 3866 if (!parent) { 3867 status = ICE_ERR_PARAM; 3868 goto ena_txq_exit; 3869 } 3870 3871 buf->parent_teid = parent->info.node_teid; 3872 node.parent_teid = parent->info.node_teid; 3873 /* Mark that the values in the "generic" section as valid. The default 3874 * value in the "generic" section is zero. This means that : 3875 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 3876 * - 0 priority among siblings, indicated by Bit 1-3. 3877 * - WFQ, indicated by Bit 4. 3878 * - 0 Adjustment value is used in PSM credit update flow, indicated by 3879 * Bit 5-6. 3880 * - Bit 7 is reserved. 3881 * Without setting the generic section as valid in valid_sections, the 3882 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 3883 */ 3884 buf->txqs[0].info.valid_sections = 3885 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 3886 ICE_AQC_ELEM_VALID_EIR; 3887 buf->txqs[0].info.generic = 0; 3888 buf->txqs[0].info.cir_bw.bw_profile_idx = 3889 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 3890 buf->txqs[0].info.cir_bw.bw_alloc = 3891 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 3892 buf->txqs[0].info.eir_bw.bw_profile_idx = 3893 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 3894 buf->txqs[0].info.eir_bw.bw_alloc = 3895 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 3896 3897 /* add the LAN queue */ 3898 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 3899 if (status) { 3900 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 3901 le16_to_cpu(buf->txqs[0].txq_id), 3902 hw->adminq.sq_last_status); 3903 goto ena_txq_exit; 3904 } 3905 3906 node.node_teid = buf->txqs[0].q_teid; 3907 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 3908 q_ctx->q_handle = q_handle; 3909 q_ctx->q_teid = le32_to_cpu(node.node_teid); 3910 3911 /* add a leaf node into scheduler tree queue layer */ 3912 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 3913 if (!status) 3914 status = ice_sched_replay_q_bw(pi, q_ctx); 3915 3916 ena_txq_exit: 3917 mutex_unlock(&pi->sched_lock); 3918 return status; 3919 } 3920 3921 /** 3922 * ice_dis_vsi_txq 3923 * @pi: port information structure 3924 * @vsi_handle: software VSI handle 3925 * @tc: TC number 3926 * @num_queues: number of queues 3927 * @q_handles: pointer to software queue handle array 3928 * @q_ids: pointer to the q_id array 3929 * @q_teids: pointer to queue node teids 3930 * @rst_src: if called due to reset, specifies the reset source 3931 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3932 * @cd: pointer to command details structure or NULL 3933 * 3934 * This function removes queues and their corresponding nodes in SW DB 3935 */ 3936 enum ice_status 3937 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 3938 u16 *q_handles, u16 *q_ids, u32 *q_teids, 3939 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3940 struct ice_sq_cd *cd) 3941 { 3942 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 3943 struct ice_aqc_dis_txq_item *qg_list; 3944 struct ice_q_ctx *q_ctx; 3945 struct ice_hw *hw; 3946 u16 i, buf_size; 3947 3948 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3949 return ICE_ERR_CFG; 3950 3951 hw = pi->hw; 3952 3953 if (!num_queues) { 3954 /* if queue is disabled already yet the disable queue command 3955 * has to be sent to complete the VF reset, then call 3956 * ice_aq_dis_lan_txq without any queue information 3957 */ 3958 if (rst_src) 3959 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 3960 vmvf_num, NULL); 3961 return ICE_ERR_CFG; 3962 } 3963 3964 buf_size = struct_size(qg_list, q_id, 1); 3965 qg_list = kzalloc(buf_size, GFP_KERNEL); 3966 if (!qg_list) 3967 return ICE_ERR_NO_MEMORY; 3968 3969 mutex_lock(&pi->sched_lock); 3970 3971 for (i = 0; i < num_queues; i++) { 3972 struct ice_sched_node *node; 3973 3974 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 3975 if (!node) 3976 continue; 3977 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 3978 if (!q_ctx) { 3979 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 3980 q_handles[i]); 3981 continue; 3982 } 3983 if (q_ctx->q_handle != q_handles[i]) { 3984 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 3985 q_ctx->q_handle, q_handles[i]); 3986 continue; 3987 } 3988 qg_list->parent_teid = node->info.parent_teid; 3989 qg_list->num_qs = 1; 3990 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 3991 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 3992 vmvf_num, cd); 3993 3994 if (status) 3995 break; 3996 ice_free_sched_node(pi, node); 3997 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 3998 } 3999 mutex_unlock(&pi->sched_lock); 4000 kfree(qg_list); 4001 return status; 4002 } 4003 4004 /** 4005 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4006 * @pi: port information structure 4007 * @vsi_handle: software VSI handle 4008 * @tc_bitmap: TC bitmap 4009 * @maxqs: max queues array per TC 4010 * @owner: LAN or RDMA 4011 * 4012 * This function adds/updates the VSI queues per TC. 4013 */ 4014 static enum ice_status 4015 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4016 u16 *maxqs, u8 owner) 4017 { 4018 enum ice_status status = 0; 4019 u8 i; 4020 4021 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4022 return ICE_ERR_CFG; 4023 4024 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4025 return ICE_ERR_PARAM; 4026 4027 mutex_lock(&pi->sched_lock); 4028 4029 ice_for_each_traffic_class(i) { 4030 /* configuration is possible only if TC node is present */ 4031 if (!ice_sched_get_tc_node(pi, i)) 4032 continue; 4033 4034 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4035 ice_is_tc_ena(tc_bitmap, i)); 4036 if (status) 4037 break; 4038 } 4039 4040 mutex_unlock(&pi->sched_lock); 4041 return status; 4042 } 4043 4044 /** 4045 * ice_cfg_vsi_lan - configure VSI LAN queues 4046 * @pi: port information structure 4047 * @vsi_handle: software VSI handle 4048 * @tc_bitmap: TC bitmap 4049 * @max_lanqs: max LAN queues array per TC 4050 * 4051 * This function adds/updates the VSI LAN queues per TC. 4052 */ 4053 enum ice_status 4054 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4055 u16 *max_lanqs) 4056 { 4057 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4058 ICE_SCHED_NODE_OWNER_LAN); 4059 } 4060 4061 /** 4062 * ice_replay_pre_init - replay pre initialization 4063 * @hw: pointer to the HW struct 4064 * 4065 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4066 */ 4067 static enum ice_status ice_replay_pre_init(struct ice_hw *hw) 4068 { 4069 struct ice_switch_info *sw = hw->switch_info; 4070 u8 i; 4071 4072 /* Delete old entries from replay filter list head if there is any */ 4073 ice_rm_all_sw_replay_rule_info(hw); 4074 /* In start of replay, move entries into replay_rules list, it 4075 * will allow adding rules entries back to filt_rules list, 4076 * which is operational list. 4077 */ 4078 for (i = 0; i < ICE_SW_LKUP_LAST; i++) 4079 list_replace_init(&sw->recp_list[i].filt_rules, 4080 &sw->recp_list[i].filt_replay_rules); 4081 4082 return 0; 4083 } 4084 4085 /** 4086 * ice_replay_vsi - replay VSI configuration 4087 * @hw: pointer to the HW struct 4088 * @vsi_handle: driver VSI handle 4089 * 4090 * Restore all VSI configuration after reset. It is required to call this 4091 * function with main VSI first. 4092 */ 4093 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4094 { 4095 enum ice_status status; 4096 4097 if (!ice_is_vsi_valid(hw, vsi_handle)) 4098 return ICE_ERR_PARAM; 4099 4100 /* Replay pre-initialization if there is any */ 4101 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 4102 status = ice_replay_pre_init(hw); 4103 if (status) 4104 return status; 4105 } 4106 /* Replay per VSI all RSS configurations */ 4107 status = ice_replay_rss_cfg(hw, vsi_handle); 4108 if (status) 4109 return status; 4110 /* Replay per VSI all filters */ 4111 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 4112 return status; 4113 } 4114 4115 /** 4116 * ice_replay_post - post replay configuration cleanup 4117 * @hw: pointer to the HW struct 4118 * 4119 * Post replay cleanup. 4120 */ 4121 void ice_replay_post(struct ice_hw *hw) 4122 { 4123 /* Delete old entries from replay filter list head */ 4124 ice_rm_all_sw_replay_rule_info(hw); 4125 } 4126 4127 /** 4128 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4129 * @hw: ptr to the hardware info 4130 * @reg: offset of 64 bit HW register to read from 4131 * @prev_stat_loaded: bool to specify if previous stats are loaded 4132 * @prev_stat: ptr to previous loaded stat value 4133 * @cur_stat: ptr to current stat value 4134 */ 4135 void 4136 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4137 u64 *prev_stat, u64 *cur_stat) 4138 { 4139 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4140 4141 /* device stats are not reset at PFR, they likely will not be zeroed 4142 * when the driver starts. Thus, save the value from the first read 4143 * without adding to the statistic value so that we report stats which 4144 * count up from zero. 4145 */ 4146 if (!prev_stat_loaded) { 4147 *prev_stat = new_data; 4148 return; 4149 } 4150 4151 /* Calculate the difference between the new and old values, and then 4152 * add it to the software stat value. 4153 */ 4154 if (new_data >= *prev_stat) 4155 *cur_stat += new_data - *prev_stat; 4156 else 4157 /* to manage the potential roll-over */ 4158 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4159 4160 /* Update the previously stored value to prepare for next read */ 4161 *prev_stat = new_data; 4162 } 4163 4164 /** 4165 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4166 * @hw: ptr to the hardware info 4167 * @reg: offset of HW register to read from 4168 * @prev_stat_loaded: bool to specify if previous stats are loaded 4169 * @prev_stat: ptr to previous loaded stat value 4170 * @cur_stat: ptr to current stat value 4171 */ 4172 void 4173 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4174 u64 *prev_stat, u64 *cur_stat) 4175 { 4176 u32 new_data; 4177 4178 new_data = rd32(hw, reg); 4179 4180 /* device stats are not reset at PFR, they likely will not be zeroed 4181 * when the driver starts. Thus, save the value from the first read 4182 * without adding to the statistic value so that we report stats which 4183 * count up from zero. 4184 */ 4185 if (!prev_stat_loaded) { 4186 *prev_stat = new_data; 4187 return; 4188 } 4189 4190 /* Calculate the difference between the new and old values, and then 4191 * add it to the software stat value. 4192 */ 4193 if (new_data >= *prev_stat) 4194 *cur_stat += new_data - *prev_stat; 4195 else 4196 /* to manage the potential roll-over */ 4197 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 4198 4199 /* Update the previously stored value to prepare for next read */ 4200 *prev_stat = new_data; 4201 } 4202 4203 /** 4204 * ice_sched_query_elem - query element information from HW 4205 * @hw: pointer to the HW struct 4206 * @node_teid: node TEID to be queried 4207 * @buf: buffer to element information 4208 * 4209 * This function queries HW element information 4210 */ 4211 enum ice_status 4212 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4213 struct ice_aqc_txsched_elem_data *buf) 4214 { 4215 u16 buf_size, num_elem_ret = 0; 4216 enum ice_status status; 4217 4218 buf_size = sizeof(*buf); 4219 memset(buf, 0, buf_size); 4220 buf->node_teid = cpu_to_le32(node_teid); 4221 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 4222 NULL); 4223 if (status || num_elem_ret != 1) 4224 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 4225 return status; 4226 } 4227 4228 /** 4229 * ice_fw_supports_link_override 4230 * @hw: pointer to the hardware structure 4231 * 4232 * Checks if the firmware supports link override 4233 */ 4234 bool ice_fw_supports_link_override(struct ice_hw *hw) 4235 { 4236 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 4237 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 4238 return true; 4239 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 4240 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 4241 return true; 4242 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 4243 return true; 4244 } 4245 4246 return false; 4247 } 4248 4249 /** 4250 * ice_get_link_default_override 4251 * @ldo: pointer to the link default override struct 4252 * @pi: pointer to the port info struct 4253 * 4254 * Gets the link default override for a port 4255 */ 4256 enum ice_status 4257 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 4258 struct ice_port_info *pi) 4259 { 4260 u16 i, tlv, tlv_len, tlv_start, buf, offset; 4261 struct ice_hw *hw = pi->hw; 4262 enum ice_status status; 4263 4264 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 4265 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 4266 if (status) { 4267 ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 4268 return status; 4269 } 4270 4271 /* Each port has its own config; calculate for our port */ 4272 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 4273 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 4274 4275 /* link options first */ 4276 status = ice_read_sr_word(hw, tlv_start, &buf); 4277 if (status) { 4278 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4279 return status; 4280 } 4281 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 4282 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 4283 ICE_LINK_OVERRIDE_PHY_CFG_S; 4284 4285 /* link PHY config */ 4286 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 4287 status = ice_read_sr_word(hw, offset, &buf); 4288 if (status) { 4289 ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 4290 return status; 4291 } 4292 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 4293 4294 /* PHY types low */ 4295 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 4296 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4297 status = ice_read_sr_word(hw, (offset + i), &buf); 4298 if (status) { 4299 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4300 return status; 4301 } 4302 /* shift 16 bits at a time to fill 64 bits */ 4303 ldo->phy_type_low |= ((u64)buf << (i * 16)); 4304 } 4305 4306 /* PHY types high */ 4307 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 4308 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 4309 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4310 status = ice_read_sr_word(hw, (offset + i), &buf); 4311 if (status) { 4312 ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4313 return status; 4314 } 4315 /* shift 16 bits at a time to fill 64 bits */ 4316 ldo->phy_type_high |= ((u64)buf << (i * 16)); 4317 } 4318 4319 return status; 4320 } 4321 4322 /** 4323 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 4324 * @caps: get PHY capability data 4325 */ 4326 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 4327 { 4328 if (caps->caps & ICE_AQC_PHY_AN_MODE || 4329 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 4330 ICE_AQC_PHY_AN_EN_CLAUSE73 | 4331 ICE_AQC_PHY_AN_EN_CLAUSE37)) 4332 return true; 4333 4334 return false; 4335 } 4336 4337 /** 4338 * ice_aq_set_lldp_mib - Set the LLDP MIB 4339 * @hw: pointer to the HW struct 4340 * @mib_type: Local, Remote or both Local and Remote MIBs 4341 * @buf: pointer to the caller-supplied buffer to store the MIB block 4342 * @buf_size: size of the buffer (in bytes) 4343 * @cd: pointer to command details structure or NULL 4344 * 4345 * Set the LLDP MIB. (0x0A08) 4346 */ 4347 enum ice_status 4348 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 4349 struct ice_sq_cd *cd) 4350 { 4351 struct ice_aqc_lldp_set_local_mib *cmd; 4352 struct ice_aq_desc desc; 4353 4354 cmd = &desc.params.lldp_set_mib; 4355 4356 if (buf_size == 0 || !buf) 4357 return ICE_ERR_PARAM; 4358 4359 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 4360 4361 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 4362 desc.datalen = cpu_to_le16(buf_size); 4363 4364 cmd->type = mib_type; 4365 cmd->length = cpu_to_le16(buf_size); 4366 4367 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4368 } 4369