1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 8 #define ICE_PF_RESET_WAIT_COUNT 200 9 10 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \ 11 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \ 12 ((ICE_RX_OPC_MDID << \ 13 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \ 14 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \ 15 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \ 16 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M)) 17 18 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \ 19 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \ 20 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \ 21 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \ 22 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \ 23 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \ 24 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \ 25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \ 26 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \ 27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M)) 28 29 /** 30 * ice_set_mac_type - Sets MAC type 31 * @hw: pointer to the HW structure 32 * 33 * This function sets the MAC type of the adapter based on the 34 * vendor ID and device ID stored in the HW structure. 35 */ 36 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 37 { 38 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 39 return ICE_ERR_DEVICE_NOT_SUPPORTED; 40 41 hw->mac_type = ICE_MAC_GENERIC; 42 return 0; 43 } 44 45 /** 46 * ice_dev_onetime_setup - Temporary HW/FW workarounds 47 * @hw: pointer to the HW structure 48 * 49 * This function provides temporary workarounds for certain issues 50 * that are expected to be fixed in the HW/FW. 51 */ 52 void ice_dev_onetime_setup(struct ice_hw *hw) 53 { 54 /* configure Rx - set non pxe mode */ 55 wr32(hw, GLLAN_RCTL_0, 0x1); 56 57 #define MBX_PF_VT_PFALLOC 0x00231E80 58 /* set VFs per PF */ 59 wr32(hw, MBX_PF_VT_PFALLOC, rd32(hw, PF_VT_PFALLOC_HIF)); 60 } 61 62 /** 63 * ice_clear_pf_cfg - Clear PF configuration 64 * @hw: pointer to the hardware structure 65 * 66 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 67 * configuration, flow director filters, etc.). 68 */ 69 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 70 { 71 struct ice_aq_desc desc; 72 73 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 74 75 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 76 } 77 78 /** 79 * ice_aq_manage_mac_read - manage MAC address read command 80 * @hw: pointer to the HW struct 81 * @buf: a virtual buffer to hold the manage MAC read response 82 * @buf_size: Size of the virtual buffer 83 * @cd: pointer to command details structure or NULL 84 * 85 * This function is used to return per PF station MAC address (0x0107). 86 * NOTE: Upon successful completion of this command, MAC address information 87 * is returned in user specified buffer. Please interpret user specified 88 * buffer as "manage_mac_read" response. 89 * Response such as various MAC addresses are stored in HW struct (port.mac) 90 * ice_aq_discover_caps is expected to be called before this function is called. 91 */ 92 static enum ice_status 93 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 94 struct ice_sq_cd *cd) 95 { 96 struct ice_aqc_manage_mac_read_resp *resp; 97 struct ice_aqc_manage_mac_read *cmd; 98 struct ice_aq_desc desc; 99 enum ice_status status; 100 u16 flags; 101 u8 i; 102 103 cmd = &desc.params.mac_read; 104 105 if (buf_size < sizeof(*resp)) 106 return ICE_ERR_BUF_TOO_SHORT; 107 108 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 109 110 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 111 if (status) 112 return status; 113 114 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 115 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 116 117 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 118 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 119 return ICE_ERR_CFG; 120 } 121 122 /* A single port can report up to two (LAN and WoL) addresses */ 123 for (i = 0; i < cmd->num_addr; i++) 124 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 125 ether_addr_copy(hw->port_info->mac.lan_addr, 126 resp[i].mac_addr); 127 ether_addr_copy(hw->port_info->mac.perm_addr, 128 resp[i].mac_addr); 129 break; 130 } 131 132 return 0; 133 } 134 135 /** 136 * ice_aq_get_phy_caps - returns PHY capabilities 137 * @pi: port information structure 138 * @qual_mods: report qualified modules 139 * @report_mode: report mode capabilities 140 * @pcaps: structure for PHY capabilities to be filled 141 * @cd: pointer to command details structure or NULL 142 * 143 * Returns the various PHY capabilities supported on the Port (0x0600) 144 */ 145 enum ice_status 146 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 147 struct ice_aqc_get_phy_caps_data *pcaps, 148 struct ice_sq_cd *cd) 149 { 150 struct ice_aqc_get_phy_caps *cmd; 151 u16 pcaps_size = sizeof(*pcaps); 152 struct ice_aq_desc desc; 153 enum ice_status status; 154 155 cmd = &desc.params.get_phy; 156 157 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 158 return ICE_ERR_PARAM; 159 160 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 161 162 if (qual_mods) 163 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 164 165 cmd->param0 |= cpu_to_le16(report_mode); 166 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd); 167 168 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) { 169 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 170 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 171 } 172 173 return status; 174 } 175 176 /** 177 * ice_get_media_type - Gets media type 178 * @pi: port information structure 179 */ 180 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 181 { 182 struct ice_link_status *hw_link_info; 183 184 if (!pi) 185 return ICE_MEDIA_UNKNOWN; 186 187 hw_link_info = &pi->phy.link_info; 188 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 189 /* If more than one media type is selected, report unknown */ 190 return ICE_MEDIA_UNKNOWN; 191 192 if (hw_link_info->phy_type_low) { 193 switch (hw_link_info->phy_type_low) { 194 case ICE_PHY_TYPE_LOW_1000BASE_SX: 195 case ICE_PHY_TYPE_LOW_1000BASE_LX: 196 case ICE_PHY_TYPE_LOW_10GBASE_SR: 197 case ICE_PHY_TYPE_LOW_10GBASE_LR: 198 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 199 case ICE_PHY_TYPE_LOW_25GBASE_SR: 200 case ICE_PHY_TYPE_LOW_25GBASE_LR: 201 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 202 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 203 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 204 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 205 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 206 case ICE_PHY_TYPE_LOW_50GBASE_SR: 207 case ICE_PHY_TYPE_LOW_50GBASE_FR: 208 case ICE_PHY_TYPE_LOW_50GBASE_LR: 209 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 210 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 211 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 212 case ICE_PHY_TYPE_LOW_100GBASE_DR: 213 return ICE_MEDIA_FIBER; 214 case ICE_PHY_TYPE_LOW_100BASE_TX: 215 case ICE_PHY_TYPE_LOW_1000BASE_T: 216 case ICE_PHY_TYPE_LOW_2500BASE_T: 217 case ICE_PHY_TYPE_LOW_5GBASE_T: 218 case ICE_PHY_TYPE_LOW_10GBASE_T: 219 case ICE_PHY_TYPE_LOW_25GBASE_T: 220 return ICE_MEDIA_BASET; 221 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 222 case ICE_PHY_TYPE_LOW_25GBASE_CR: 223 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 224 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 225 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 226 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 227 case ICE_PHY_TYPE_LOW_50GBASE_CP: 228 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 229 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 230 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 231 return ICE_MEDIA_DA; 232 case ICE_PHY_TYPE_LOW_1000BASE_KX: 233 case ICE_PHY_TYPE_LOW_2500BASE_KX: 234 case ICE_PHY_TYPE_LOW_2500BASE_X: 235 case ICE_PHY_TYPE_LOW_5GBASE_KR: 236 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 237 case ICE_PHY_TYPE_LOW_25GBASE_KR: 238 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 239 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 240 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 241 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 242 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 243 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 244 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 245 return ICE_MEDIA_BACKPLANE; 246 } 247 } else { 248 switch (hw_link_info->phy_type_high) { 249 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 250 return ICE_MEDIA_BACKPLANE; 251 } 252 } 253 return ICE_MEDIA_UNKNOWN; 254 } 255 256 /** 257 * ice_aq_get_link_info 258 * @pi: port information structure 259 * @ena_lse: enable/disable LinkStatusEvent reporting 260 * @link: pointer to link status structure - optional 261 * @cd: pointer to command details structure or NULL 262 * 263 * Get Link Status (0x607). Returns the link status of the adapter. 264 */ 265 enum ice_status 266 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 267 struct ice_link_status *link, struct ice_sq_cd *cd) 268 { 269 struct ice_link_status *hw_link_info_old, *hw_link_info; 270 struct ice_aqc_get_link_status_data link_data = { 0 }; 271 struct ice_aqc_get_link_status *resp; 272 enum ice_media_type *hw_media_type; 273 struct ice_fc_info *hw_fc_info; 274 bool tx_pause, rx_pause; 275 struct ice_aq_desc desc; 276 enum ice_status status; 277 u16 cmd_flags; 278 279 if (!pi) 280 return ICE_ERR_PARAM; 281 hw_link_info_old = &pi->phy.link_info_old; 282 hw_media_type = &pi->phy.media_type; 283 hw_link_info = &pi->phy.link_info; 284 hw_fc_info = &pi->fc; 285 286 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 287 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 288 resp = &desc.params.get_link_status; 289 resp->cmd_flags = cpu_to_le16(cmd_flags); 290 resp->lport_num = pi->lport; 291 292 status = ice_aq_send_cmd(pi->hw, &desc, &link_data, sizeof(link_data), 293 cd); 294 295 if (status) 296 return status; 297 298 /* save off old link status information */ 299 *hw_link_info_old = *hw_link_info; 300 301 /* update current link status information */ 302 hw_link_info->link_speed = le16_to_cpu(link_data.link_speed); 303 hw_link_info->phy_type_low = le64_to_cpu(link_data.phy_type_low); 304 hw_link_info->phy_type_high = le64_to_cpu(link_data.phy_type_high); 305 *hw_media_type = ice_get_media_type(pi); 306 hw_link_info->link_info = link_data.link_info; 307 hw_link_info->an_info = link_data.an_info; 308 hw_link_info->ext_info = link_data.ext_info; 309 hw_link_info->max_frame_size = le16_to_cpu(link_data.max_frame_size); 310 hw_link_info->pacing = link_data.cfg & ICE_AQ_CFG_PACING_M; 311 312 /* update fc info */ 313 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 314 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 315 if (tx_pause && rx_pause) 316 hw_fc_info->current_mode = ICE_FC_FULL; 317 else if (tx_pause) 318 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 319 else if (rx_pause) 320 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 321 else 322 hw_fc_info->current_mode = ICE_FC_NONE; 323 324 hw_link_info->lse_ena = 325 !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 326 327 /* save link status information */ 328 if (link) 329 *link = *hw_link_info; 330 331 /* flag cleared so calling functions don't call AQ again */ 332 pi->phy.get_link_info = false; 333 334 return 0; 335 } 336 337 /** 338 * ice_init_flex_flags 339 * @hw: pointer to the hardware structure 340 * @prof_id: Rx Descriptor Builder profile ID 341 * 342 * Function to initialize Rx flex flags 343 */ 344 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id) 345 { 346 u8 idx = 0; 347 348 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout: 349 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE 350 * flexiflags1[3:0] - Not used for flag programming 351 * flexiflags2[7:0] - Tunnel and VLAN types 352 * 2 invalid fields in last index 353 */ 354 switch (prof_id) { 355 /* Rx flex flags are currently programmed for the NIC profiles only. 356 * Different flag bit programming configurations can be added per 357 * profile as needed. 358 */ 359 case ICE_RXDID_FLEX_NIC: 360 case ICE_RXDID_FLEX_NIC_2: 361 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG, 362 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI, 363 ICE_FLG_FIN, idx++); 364 /* flex flag 1 is not used for flexi-flag programming, skipping 365 * these four FLG64 bits. 366 */ 367 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST, 368 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++); 369 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI, 370 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100, 371 ICE_FLG_EVLAN_x9100, idx++); 372 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100, 373 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC, 374 ICE_FLG_TNL0, idx++); 375 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2, 376 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx); 377 break; 378 379 default: 380 ice_debug(hw, ICE_DBG_INIT, 381 "Flag programming for profile ID %d not supported\n", 382 prof_id); 383 } 384 } 385 386 /** 387 * ice_init_flex_flds 388 * @hw: pointer to the hardware structure 389 * @prof_id: Rx Descriptor Builder profile ID 390 * 391 * Function to initialize flex descriptors 392 */ 393 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id) 394 { 395 enum ice_flex_rx_mdid mdid; 396 397 switch (prof_id) { 398 case ICE_RXDID_FLEX_NIC: 399 case ICE_RXDID_FLEX_NIC_2: 400 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_LOW, 0); 401 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_HIGH, 1); 402 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_FLOW_ID_LOWER, 2); 403 404 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ? 405 ICE_RX_MDID_SRC_VSI : ICE_RX_MDID_FLOW_ID_HIGH; 406 407 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3); 408 409 ice_init_flex_flags(hw, prof_id); 410 break; 411 412 default: 413 ice_debug(hw, ICE_DBG_INIT, 414 "Field init for profile ID %d not supported\n", 415 prof_id); 416 } 417 } 418 419 /** 420 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 421 * @hw: pointer to the HW struct 422 */ 423 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 424 { 425 struct ice_switch_info *sw; 426 427 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 428 sizeof(*hw->switch_info), GFP_KERNEL); 429 sw = hw->switch_info; 430 431 if (!sw) 432 return ICE_ERR_NO_MEMORY; 433 434 INIT_LIST_HEAD(&sw->vsi_list_map_head); 435 436 return ice_init_def_sw_recp(hw); 437 } 438 439 /** 440 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 441 * @hw: pointer to the HW struct 442 */ 443 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 444 { 445 struct ice_switch_info *sw = hw->switch_info; 446 struct ice_vsi_list_map_info *v_pos_map; 447 struct ice_vsi_list_map_info *v_tmp_map; 448 struct ice_sw_recipe *recps; 449 u8 i; 450 451 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 452 list_entry) { 453 list_del(&v_pos_map->list_entry); 454 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 455 } 456 recps = hw->switch_info->recp_list; 457 for (i = 0; i < ICE_SW_LKUP_LAST; i++) { 458 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 459 460 recps[i].root_rid = i; 461 mutex_destroy(&recps[i].filt_rule_lock); 462 list_for_each_entry_safe(lst_itr, tmp_entry, 463 &recps[i].filt_rules, list_entry) { 464 list_del(&lst_itr->list_entry); 465 devm_kfree(ice_hw_to_dev(hw), lst_itr); 466 } 467 } 468 ice_rm_all_sw_replay_rule_info(hw); 469 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 470 devm_kfree(ice_hw_to_dev(hw), sw); 471 } 472 473 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \ 474 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry))) 475 #define ICE_FW_LOG_DESC_SIZE_MAX \ 476 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX) 477 478 /** 479 * ice_cfg_fw_log - configure FW logging 480 * @hw: pointer to the HW struct 481 * @enable: enable certain FW logging events if true, disable all if false 482 * 483 * This function enables/disables the FW logging via Rx CQ events and a UART 484 * port based on predetermined configurations. FW logging via the Rx CQ can be 485 * enabled/disabled for individual PF's. However, FW logging via the UART can 486 * only be enabled/disabled for all PFs on the same device. 487 * 488 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 489 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 490 * before initializing the device. 491 * 492 * When re/configuring FW logging, callers need to update the "cfg" elements of 493 * the hw->fw_log.evnts array with the desired logging event configurations for 494 * modules of interest. When disabling FW logging completely, the callers can 495 * just pass false in the "enable" parameter. On completion, the function will 496 * update the "cur" element of the hw->fw_log.evnts array with the resulting 497 * logging event configurations of the modules that are being re/configured. FW 498 * logging modules that are not part of a reconfiguration operation retain their 499 * previous states. 500 * 501 * Before resetting the device, it is recommended that the driver disables FW 502 * logging before shutting down the control queue. When disabling FW logging 503 * ("enable" = false), the latest configurations of FW logging events stored in 504 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 505 * a device reset. 506 * 507 * When enabling FW logging to emit log messages via the Rx CQ during the 508 * device's initialization phase, a mechanism alternative to interrupt handlers 509 * needs to be used to extract FW log messages from the Rx CQ periodically and 510 * to prevent the Rx CQ from being full and stalling other types of control 511 * messages from FW to SW. Interrupts are typically disabled during the device's 512 * initialization phase. 513 */ 514 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable) 515 { 516 struct ice_aqc_fw_logging_data *data = NULL; 517 struct ice_aqc_fw_logging *cmd; 518 enum ice_status status = 0; 519 u16 i, chgs = 0, len = 0; 520 struct ice_aq_desc desc; 521 u8 actv_evnts = 0; 522 void *buf = NULL; 523 524 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 525 return 0; 526 527 /* Disable FW logging only when the control queue is still responsive */ 528 if (!enable && 529 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 530 return 0; 531 532 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 533 cmd = &desc.params.fw_logging; 534 535 /* Indicate which controls are valid */ 536 if (hw->fw_log.cq_en) 537 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 538 539 if (hw->fw_log.uart_en) 540 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 541 542 if (enable) { 543 /* Fill in an array of entries with FW logging modules and 544 * logging events being reconfigured. 545 */ 546 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 547 u16 val; 548 549 /* Keep track of enabled event types */ 550 actv_evnts |= hw->fw_log.evnts[i].cfg; 551 552 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 553 continue; 554 555 if (!data) { 556 data = devm_kzalloc(ice_hw_to_dev(hw), 557 ICE_FW_LOG_DESC_SIZE_MAX, 558 GFP_KERNEL); 559 if (!data) 560 return ICE_ERR_NO_MEMORY; 561 } 562 563 val = i << ICE_AQC_FW_LOG_ID_S; 564 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 565 data->entry[chgs++] = cpu_to_le16(val); 566 } 567 568 /* Only enable FW logging if at least one module is specified. 569 * If FW logging is currently enabled but all modules are not 570 * enabled to emit log messages, disable FW logging altogether. 571 */ 572 if (actv_evnts) { 573 /* Leave if there is effectively no change */ 574 if (!chgs) 575 goto out; 576 577 if (hw->fw_log.cq_en) 578 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 579 580 if (hw->fw_log.uart_en) 581 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 582 583 buf = data; 584 len = ICE_FW_LOG_DESC_SIZE(chgs); 585 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 586 } 587 } 588 589 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 590 if (!status) { 591 /* Update the current configuration to reflect events enabled. 592 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 593 * logging mode is enabled for the device. They do not reflect 594 * actual modules being enabled to emit log messages. So, their 595 * values remain unchanged even when all modules are disabled. 596 */ 597 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 598 599 hw->fw_log.actv_evnts = actv_evnts; 600 for (i = 0; i < cnt; i++) { 601 u16 v, m; 602 603 if (!enable) { 604 /* When disabling all FW logging events as part 605 * of device's de-initialization, the original 606 * configurations are retained, and can be used 607 * to reconfigure FW logging later if the device 608 * is re-initialized. 609 */ 610 hw->fw_log.evnts[i].cur = 0; 611 continue; 612 } 613 614 v = le16_to_cpu(data->entry[i]); 615 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 616 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 617 } 618 } 619 620 out: 621 if (data) 622 devm_kfree(ice_hw_to_dev(hw), data); 623 624 return status; 625 } 626 627 /** 628 * ice_output_fw_log 629 * @hw: pointer to the HW struct 630 * @desc: pointer to the AQ message descriptor 631 * @buf: pointer to the buffer accompanying the AQ message 632 * 633 * Formats a FW Log message and outputs it via the standard driver logs. 634 */ 635 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 636 { 637 ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg Start ]\n"); 638 ice_debug_array(hw, ICE_DBG_AQ_MSG, 16, 1, (u8 *)buf, 639 le16_to_cpu(desc->datalen)); 640 ice_debug(hw, ICE_DBG_AQ_MSG, "[ FW Log Msg End ]\n"); 641 } 642 643 /** 644 * ice_get_itr_intrl_gran - determine int/intrl granularity 645 * @hw: pointer to the HW struct 646 * 647 * Determines the itr/intrl granularities based on the maximum aggregate 648 * bandwidth according to the device's configuration during power-on. 649 */ 650 static enum ice_status ice_get_itr_intrl_gran(struct ice_hw *hw) 651 { 652 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 653 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 654 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 655 656 switch (max_agg_bw) { 657 case ICE_MAX_AGG_BW_200G: 658 case ICE_MAX_AGG_BW_100G: 659 case ICE_MAX_AGG_BW_50G: 660 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 661 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 662 break; 663 case ICE_MAX_AGG_BW_25G: 664 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 665 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 666 break; 667 default: 668 ice_debug(hw, ICE_DBG_INIT, 669 "Failed to determine itr/intrl granularity\n"); 670 return ICE_ERR_CFG; 671 } 672 673 return 0; 674 } 675 676 /** 677 * ice_init_hw - main hardware initialization routine 678 * @hw: pointer to the hardware structure 679 */ 680 enum ice_status ice_init_hw(struct ice_hw *hw) 681 { 682 struct ice_aqc_get_phy_caps_data *pcaps; 683 enum ice_status status; 684 u16 mac_buf_len; 685 void *mac_buf; 686 687 /* Set MAC type based on DeviceID */ 688 status = ice_set_mac_type(hw); 689 if (status) 690 return status; 691 692 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 693 PF_FUNC_RID_FUNC_NUM_M) >> 694 PF_FUNC_RID_FUNC_NUM_S; 695 696 status = ice_reset(hw, ICE_RESET_PFR); 697 if (status) 698 return status; 699 700 status = ice_get_itr_intrl_gran(hw); 701 if (status) 702 return status; 703 704 status = ice_init_all_ctrlq(hw); 705 if (status) 706 goto err_unroll_cqinit; 707 708 /* Enable FW logging. Not fatal if this fails. */ 709 status = ice_cfg_fw_log(hw, true); 710 if (status) 711 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 712 713 status = ice_clear_pf_cfg(hw); 714 if (status) 715 goto err_unroll_cqinit; 716 717 ice_clear_pxe_mode(hw); 718 719 status = ice_init_nvm(hw); 720 if (status) 721 goto err_unroll_cqinit; 722 723 status = ice_get_caps(hw); 724 if (status) 725 goto err_unroll_cqinit; 726 727 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 728 sizeof(*hw->port_info), GFP_KERNEL); 729 if (!hw->port_info) { 730 status = ICE_ERR_NO_MEMORY; 731 goto err_unroll_cqinit; 732 } 733 734 /* set the back pointer to HW */ 735 hw->port_info->hw = hw; 736 737 /* Initialize port_info struct with switch configuration data */ 738 status = ice_get_initial_sw_cfg(hw); 739 if (status) 740 goto err_unroll_alloc; 741 742 hw->evb_veb = true; 743 744 /* Query the allocated resources for Tx scheduler */ 745 status = ice_sched_query_res_alloc(hw); 746 if (status) { 747 ice_debug(hw, ICE_DBG_SCHED, 748 "Failed to get scheduler allocated resources\n"); 749 goto err_unroll_alloc; 750 } 751 752 /* Initialize port_info struct with scheduler data */ 753 status = ice_sched_init_port(hw->port_info); 754 if (status) 755 goto err_unroll_sched; 756 757 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 758 if (!pcaps) { 759 status = ICE_ERR_NO_MEMORY; 760 goto err_unroll_sched; 761 } 762 763 /* Initialize port_info struct with PHY capabilities */ 764 status = ice_aq_get_phy_caps(hw->port_info, false, 765 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); 766 devm_kfree(ice_hw_to_dev(hw), pcaps); 767 if (status) 768 goto err_unroll_sched; 769 770 /* Initialize port_info struct with link information */ 771 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 772 if (status) 773 goto err_unroll_sched; 774 775 /* need a valid SW entry point to build a Tx tree */ 776 if (!hw->sw_entry_point_layer) { 777 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 778 status = ICE_ERR_CFG; 779 goto err_unroll_sched; 780 } 781 INIT_LIST_HEAD(&hw->agg_list); 782 783 status = ice_init_fltr_mgmt_struct(hw); 784 if (status) 785 goto err_unroll_sched; 786 787 ice_dev_onetime_setup(hw); 788 789 /* Get MAC information */ 790 /* A single port can report up to two (LAN and WoL) addresses */ 791 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 792 sizeof(struct ice_aqc_manage_mac_read_resp), 793 GFP_KERNEL); 794 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 795 796 if (!mac_buf) { 797 status = ICE_ERR_NO_MEMORY; 798 goto err_unroll_fltr_mgmt_struct; 799 } 800 801 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 802 devm_kfree(ice_hw_to_dev(hw), mac_buf); 803 804 if (status) 805 goto err_unroll_fltr_mgmt_struct; 806 807 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC); 808 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2); 809 810 return 0; 811 812 err_unroll_fltr_mgmt_struct: 813 ice_cleanup_fltr_mgmt_struct(hw); 814 err_unroll_sched: 815 ice_sched_cleanup_all(hw); 816 err_unroll_alloc: 817 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 818 err_unroll_cqinit: 819 ice_shutdown_all_ctrlq(hw); 820 return status; 821 } 822 823 /** 824 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 825 * @hw: pointer to the hardware structure 826 */ 827 void ice_deinit_hw(struct ice_hw *hw) 828 { 829 ice_cleanup_fltr_mgmt_struct(hw); 830 831 ice_sched_cleanup_all(hw); 832 ice_sched_clear_agg(hw); 833 834 if (hw->port_info) { 835 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 836 hw->port_info = NULL; 837 } 838 839 /* Attempt to disable FW logging before shutting down control queues */ 840 ice_cfg_fw_log(hw, false); 841 ice_shutdown_all_ctrlq(hw); 842 843 /* Clear VSI contexts if not already cleared */ 844 ice_clear_all_vsi_ctx(hw); 845 } 846 847 /** 848 * ice_check_reset - Check to see if a global reset is complete 849 * @hw: pointer to the hardware structure 850 */ 851 enum ice_status ice_check_reset(struct ice_hw *hw) 852 { 853 u32 cnt, reg = 0, grst_delay; 854 855 /* Poll for Device Active state in case a recent CORER, GLOBR, 856 * or EMPR has occurred. The grst delay value is in 100ms units. 857 * Add 1sec for outstanding AQ commands that can take a long time. 858 */ 859 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 860 GLGEN_RSTCTL_GRSTDEL_S) + 10; 861 862 for (cnt = 0; cnt < grst_delay; cnt++) { 863 mdelay(100); 864 reg = rd32(hw, GLGEN_RSTAT); 865 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 866 break; 867 } 868 869 if (cnt == grst_delay) { 870 ice_debug(hw, ICE_DBG_INIT, 871 "Global reset polling failed to complete.\n"); 872 return ICE_ERR_RESET_FAILED; 873 } 874 875 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \ 876 GLNVM_ULD_GLOBR_DONE_M) 877 878 /* Device is Active; check Global Reset processes are done */ 879 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 880 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK; 881 if (reg == ICE_RESET_DONE_MASK) { 882 ice_debug(hw, ICE_DBG_INIT, 883 "Global reset processes done. %d\n", cnt); 884 break; 885 } 886 mdelay(10); 887 } 888 889 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 890 ice_debug(hw, ICE_DBG_INIT, 891 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 892 reg); 893 return ICE_ERR_RESET_FAILED; 894 } 895 896 return 0; 897 } 898 899 /** 900 * ice_pf_reset - Reset the PF 901 * @hw: pointer to the hardware structure 902 * 903 * If a global reset has been triggered, this function checks 904 * for its completion and then issues the PF reset 905 */ 906 static enum ice_status ice_pf_reset(struct ice_hw *hw) 907 { 908 u32 cnt, reg; 909 910 /* If at function entry a global reset was already in progress, i.e. 911 * state is not 'device active' or any of the reset done bits are not 912 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 913 * global reset is done. 914 */ 915 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 916 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 917 /* poll on global reset currently in progress until done */ 918 if (ice_check_reset(hw)) 919 return ICE_ERR_RESET_FAILED; 920 921 return 0; 922 } 923 924 /* Reset the PF */ 925 reg = rd32(hw, PFGEN_CTRL); 926 927 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 928 929 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 930 reg = rd32(hw, PFGEN_CTRL); 931 if (!(reg & PFGEN_CTRL_PFSWR_M)) 932 break; 933 934 mdelay(1); 935 } 936 937 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 938 ice_debug(hw, ICE_DBG_INIT, 939 "PF reset polling failed to complete.\n"); 940 return ICE_ERR_RESET_FAILED; 941 } 942 943 return 0; 944 } 945 946 /** 947 * ice_reset - Perform different types of reset 948 * @hw: pointer to the hardware structure 949 * @req: reset request 950 * 951 * This function triggers a reset as specified by the req parameter. 952 * 953 * Note: 954 * If anything other than a PF reset is triggered, PXE mode is restored. 955 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 956 * interface has been restored in the rebuild flow. 957 */ 958 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 959 { 960 u32 val = 0; 961 962 switch (req) { 963 case ICE_RESET_PFR: 964 return ice_pf_reset(hw); 965 case ICE_RESET_CORER: 966 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 967 val = GLGEN_RTRIG_CORER_M; 968 break; 969 case ICE_RESET_GLOBR: 970 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 971 val = GLGEN_RTRIG_GLOBR_M; 972 break; 973 default: 974 return ICE_ERR_PARAM; 975 } 976 977 val |= rd32(hw, GLGEN_RTRIG); 978 wr32(hw, GLGEN_RTRIG, val); 979 ice_flush(hw); 980 981 /* wait for the FW to be ready */ 982 return ice_check_reset(hw); 983 } 984 985 /** 986 * ice_copy_rxq_ctx_to_hw 987 * @hw: pointer to the hardware structure 988 * @ice_rxq_ctx: pointer to the rxq context 989 * @rxq_index: the index of the Rx queue 990 * 991 * Copies rxq context from dense structure to HW register space 992 */ 993 static enum ice_status 994 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 995 { 996 u8 i; 997 998 if (!ice_rxq_ctx) 999 return ICE_ERR_BAD_PTR; 1000 1001 if (rxq_index > QRX_CTRL_MAX_INDEX) 1002 return ICE_ERR_PARAM; 1003 1004 /* Copy each dword separately to HW */ 1005 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1006 wr32(hw, QRX_CONTEXT(i, rxq_index), 1007 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1008 1009 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1010 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1011 } 1012 1013 return 0; 1014 } 1015 1016 /* LAN Rx Queue Context */ 1017 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1018 /* Field Width LSB */ 1019 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1020 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1021 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1022 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1023 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1024 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1025 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1026 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1027 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1028 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1029 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1030 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1031 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1032 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1033 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1034 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1035 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1036 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1037 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1038 { 0 } 1039 }; 1040 1041 /** 1042 * ice_write_rxq_ctx 1043 * @hw: pointer to the hardware structure 1044 * @rlan_ctx: pointer to the rxq context 1045 * @rxq_index: the index of the Rx queue 1046 * 1047 * Converts rxq context from sparse to dense structure and then writes 1048 * it to HW register space 1049 */ 1050 enum ice_status 1051 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1052 u32 rxq_index) 1053 { 1054 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1055 1056 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1057 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1058 } 1059 1060 /* LAN Tx Queue Context */ 1061 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1062 /* Field Width LSB */ 1063 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1064 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1065 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1066 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1067 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1068 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1069 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1070 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1071 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1072 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1073 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1074 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1075 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1076 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1077 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1078 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1079 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1080 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1081 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1082 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1083 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1084 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1085 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1086 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1087 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1088 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1089 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 110, 171), 1090 { 0 } 1091 }; 1092 1093 /** 1094 * ice_debug_cq 1095 * @hw: pointer to the hardware structure 1096 * @mask: debug mask 1097 * @desc: pointer to control queue descriptor 1098 * @buf: pointer to command buffer 1099 * @buf_len: max length of buf 1100 * 1101 * Dumps debug log about control command with descriptor contents. 1102 */ 1103 void 1104 ice_debug_cq(struct ice_hw *hw, u32 __maybe_unused mask, void *desc, void *buf, 1105 u16 buf_len) 1106 { 1107 struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc; 1108 u16 len; 1109 1110 #ifndef CONFIG_DYNAMIC_DEBUG 1111 if (!(mask & hw->debug_mask)) 1112 return; 1113 #endif 1114 1115 if (!desc) 1116 return; 1117 1118 len = le16_to_cpu(cq_desc->datalen); 1119 1120 ice_debug(hw, mask, 1121 "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 1122 le16_to_cpu(cq_desc->opcode), 1123 le16_to_cpu(cq_desc->flags), 1124 le16_to_cpu(cq_desc->datalen), le16_to_cpu(cq_desc->retval)); 1125 ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 1126 le32_to_cpu(cq_desc->cookie_high), 1127 le32_to_cpu(cq_desc->cookie_low)); 1128 ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 1129 le32_to_cpu(cq_desc->params.generic.param0), 1130 le32_to_cpu(cq_desc->params.generic.param1)); 1131 ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 1132 le32_to_cpu(cq_desc->params.generic.addr_high), 1133 le32_to_cpu(cq_desc->params.generic.addr_low)); 1134 if (buf && cq_desc->datalen != 0) { 1135 ice_debug(hw, mask, "Buffer:\n"); 1136 if (buf_len < len) 1137 len = buf_len; 1138 1139 ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len); 1140 } 1141 } 1142 1143 /* FW Admin Queue command wrappers */ 1144 1145 /** 1146 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1147 * @hw: pointer to the HW struct 1148 * @desc: descriptor describing the command 1149 * @buf: buffer to use for indirect commands (NULL for direct commands) 1150 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1151 * @cd: pointer to command details structure 1152 * 1153 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1154 */ 1155 enum ice_status 1156 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1157 u16 buf_size, struct ice_sq_cd *cd) 1158 { 1159 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); 1160 } 1161 1162 /** 1163 * ice_aq_get_fw_ver 1164 * @hw: pointer to the HW struct 1165 * @cd: pointer to command details structure or NULL 1166 * 1167 * Get the firmware version (0x0001) from the admin queue commands 1168 */ 1169 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1170 { 1171 struct ice_aqc_get_ver *resp; 1172 struct ice_aq_desc desc; 1173 enum ice_status status; 1174 1175 resp = &desc.params.get_ver; 1176 1177 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1178 1179 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1180 1181 if (!status) { 1182 hw->fw_branch = resp->fw_branch; 1183 hw->fw_maj_ver = resp->fw_major; 1184 hw->fw_min_ver = resp->fw_minor; 1185 hw->fw_patch = resp->fw_patch; 1186 hw->fw_build = le32_to_cpu(resp->fw_build); 1187 hw->api_branch = resp->api_branch; 1188 hw->api_maj_ver = resp->api_major; 1189 hw->api_min_ver = resp->api_minor; 1190 hw->api_patch = resp->api_patch; 1191 } 1192 1193 return status; 1194 } 1195 1196 /** 1197 * ice_aq_q_shutdown 1198 * @hw: pointer to the HW struct 1199 * @unloading: is the driver unloading itself 1200 * 1201 * Tell the Firmware that we're shutting down the AdminQ and whether 1202 * or not the driver is unloading as well (0x0003). 1203 */ 1204 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1205 { 1206 struct ice_aqc_q_shutdown *cmd; 1207 struct ice_aq_desc desc; 1208 1209 cmd = &desc.params.q_shutdown; 1210 1211 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1212 1213 if (unloading) 1214 cmd->driver_unloading = cpu_to_le32(ICE_AQC_DRIVER_UNLOADING); 1215 1216 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1217 } 1218 1219 /** 1220 * ice_aq_req_res 1221 * @hw: pointer to the HW struct 1222 * @res: resource ID 1223 * @access: access type 1224 * @sdp_number: resource number 1225 * @timeout: the maximum time in ms that the driver may hold the resource 1226 * @cd: pointer to command details structure or NULL 1227 * 1228 * Requests common resource using the admin queue commands (0x0008). 1229 * When attempting to acquire the Global Config Lock, the driver can 1230 * learn of three states: 1231 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1232 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1233 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1234 * successfully downloaded the package; the driver does 1235 * not have to download the package and can continue 1236 * loading 1237 * 1238 * Note that if the caller is in an acquire lock, perform action, release lock 1239 * phase of operation, it is possible that the FW may detect a timeout and issue 1240 * a CORER. In this case, the driver will receive a CORER interrupt and will 1241 * have to determine its cause. The calling thread that is handling this flow 1242 * will likely get an error propagated back to it indicating the Download 1243 * Package, Update Package or the Release Resource AQ commands timed out. 1244 */ 1245 static enum ice_status 1246 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1247 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1248 struct ice_sq_cd *cd) 1249 { 1250 struct ice_aqc_req_res *cmd_resp; 1251 struct ice_aq_desc desc; 1252 enum ice_status status; 1253 1254 cmd_resp = &desc.params.res_owner; 1255 1256 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1257 1258 cmd_resp->res_id = cpu_to_le16(res); 1259 cmd_resp->access_type = cpu_to_le16(access); 1260 cmd_resp->res_number = cpu_to_le32(sdp_number); 1261 cmd_resp->timeout = cpu_to_le32(*timeout); 1262 *timeout = 0; 1263 1264 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1265 1266 /* The completion specifies the maximum time in ms that the driver 1267 * may hold the resource in the Timeout field. 1268 */ 1269 1270 /* Global config lock response utilizes an additional status field. 1271 * 1272 * If the Global config lock resource is held by some other driver, the 1273 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1274 * and the timeout field indicates the maximum time the current owner 1275 * of the resource has to free it. 1276 */ 1277 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1278 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1279 *timeout = le32_to_cpu(cmd_resp->timeout); 1280 return 0; 1281 } else if (le16_to_cpu(cmd_resp->status) == 1282 ICE_AQ_RES_GLBL_IN_PROG) { 1283 *timeout = le32_to_cpu(cmd_resp->timeout); 1284 return ICE_ERR_AQ_ERROR; 1285 } else if (le16_to_cpu(cmd_resp->status) == 1286 ICE_AQ_RES_GLBL_DONE) { 1287 return ICE_ERR_AQ_NO_WORK; 1288 } 1289 1290 /* invalid FW response, force a timeout immediately */ 1291 *timeout = 0; 1292 return ICE_ERR_AQ_ERROR; 1293 } 1294 1295 /* If the resource is held by some other driver, the command completes 1296 * with a busy return value and the timeout field indicates the maximum 1297 * time the current owner of the resource has to free it. 1298 */ 1299 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1300 *timeout = le32_to_cpu(cmd_resp->timeout); 1301 1302 return status; 1303 } 1304 1305 /** 1306 * ice_aq_release_res 1307 * @hw: pointer to the HW struct 1308 * @res: resource ID 1309 * @sdp_number: resource number 1310 * @cd: pointer to command details structure or NULL 1311 * 1312 * release common resource using the admin queue commands (0x0009) 1313 */ 1314 static enum ice_status 1315 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1316 struct ice_sq_cd *cd) 1317 { 1318 struct ice_aqc_req_res *cmd; 1319 struct ice_aq_desc desc; 1320 1321 cmd = &desc.params.res_owner; 1322 1323 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1324 1325 cmd->res_id = cpu_to_le16(res); 1326 cmd->res_number = cpu_to_le32(sdp_number); 1327 1328 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1329 } 1330 1331 /** 1332 * ice_acquire_res 1333 * @hw: pointer to the HW structure 1334 * @res: resource ID 1335 * @access: access type (read or write) 1336 * @timeout: timeout in milliseconds 1337 * 1338 * This function will attempt to acquire the ownership of a resource. 1339 */ 1340 enum ice_status 1341 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1342 enum ice_aq_res_access_type access, u32 timeout) 1343 { 1344 #define ICE_RES_POLLING_DELAY_MS 10 1345 u32 delay = ICE_RES_POLLING_DELAY_MS; 1346 u32 time_left = timeout; 1347 enum ice_status status; 1348 1349 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1350 1351 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1352 * previously acquired the resource and performed any necessary updates; 1353 * in this case the caller does not obtain the resource and has no 1354 * further work to do. 1355 */ 1356 if (status == ICE_ERR_AQ_NO_WORK) 1357 goto ice_acquire_res_exit; 1358 1359 if (status) 1360 ice_debug(hw, ICE_DBG_RES, 1361 "resource %d acquire type %d failed.\n", res, access); 1362 1363 /* If necessary, poll until the current lock owner timeouts */ 1364 timeout = time_left; 1365 while (status && timeout && time_left) { 1366 mdelay(delay); 1367 timeout = (timeout > delay) ? timeout - delay : 0; 1368 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1369 1370 if (status == ICE_ERR_AQ_NO_WORK) 1371 /* lock free, but no work to do */ 1372 break; 1373 1374 if (!status) 1375 /* lock acquired */ 1376 break; 1377 } 1378 if (status && status != ICE_ERR_AQ_NO_WORK) 1379 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1380 1381 ice_acquire_res_exit: 1382 if (status == ICE_ERR_AQ_NO_WORK) { 1383 if (access == ICE_RES_WRITE) 1384 ice_debug(hw, ICE_DBG_RES, 1385 "resource indicates no work to do.\n"); 1386 else 1387 ice_debug(hw, ICE_DBG_RES, 1388 "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1389 } 1390 return status; 1391 } 1392 1393 /** 1394 * ice_release_res 1395 * @hw: pointer to the HW structure 1396 * @res: resource ID 1397 * 1398 * This function will release a resource using the proper Admin Command. 1399 */ 1400 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1401 { 1402 enum ice_status status; 1403 u32 total_delay = 0; 1404 1405 status = ice_aq_release_res(hw, res, 0, NULL); 1406 1407 /* there are some rare cases when trying to release the resource 1408 * results in an admin queue timeout, so handle them correctly 1409 */ 1410 while ((status == ICE_ERR_AQ_TIMEOUT) && 1411 (total_delay < hw->adminq.sq_cmd_timeout)) { 1412 mdelay(1); 1413 status = ice_aq_release_res(hw, res, 0, NULL); 1414 total_delay++; 1415 } 1416 } 1417 1418 /** 1419 * ice_get_num_per_func - determine number of resources per PF 1420 * @hw: pointer to the HW structure 1421 * @max: value to be evenly split between each PF 1422 * 1423 * Determine the number of valid functions by going through the bitmap returned 1424 * from parsing capabilities and use this to calculate the number of resources 1425 * per PF based on the max value passed in. 1426 */ 1427 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1428 { 1429 u8 funcs; 1430 1431 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1432 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 1433 ICE_CAPS_VALID_FUNCS_M); 1434 1435 if (!funcs) 1436 return 0; 1437 1438 return max / funcs; 1439 } 1440 1441 /** 1442 * ice_parse_caps - parse function/device capabilities 1443 * @hw: pointer to the HW struct 1444 * @buf: pointer to a buffer containing function/device capability records 1445 * @cap_count: number of capability records in the list 1446 * @opc: type of capabilities list to parse 1447 * 1448 * Helper function to parse function(0x000a)/device(0x000b) capabilities list. 1449 */ 1450 static void 1451 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, 1452 enum ice_adminq_opc opc) 1453 { 1454 struct ice_aqc_list_caps_elem *cap_resp; 1455 struct ice_hw_func_caps *func_p = NULL; 1456 struct ice_hw_dev_caps *dev_p = NULL; 1457 struct ice_hw_common_caps *caps; 1458 u32 i; 1459 1460 if (!buf) 1461 return; 1462 1463 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 1464 1465 if (opc == ice_aqc_opc_list_dev_caps) { 1466 dev_p = &hw->dev_caps; 1467 caps = &dev_p->common_cap; 1468 } else if (opc == ice_aqc_opc_list_func_caps) { 1469 func_p = &hw->func_caps; 1470 caps = &func_p->common_cap; 1471 } else { 1472 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n"); 1473 return; 1474 } 1475 1476 for (i = 0; caps && i < cap_count; i++, cap_resp++) { 1477 u32 logical_id = le32_to_cpu(cap_resp->logical_id); 1478 u32 phys_id = le32_to_cpu(cap_resp->phys_id); 1479 u32 number = le32_to_cpu(cap_resp->number); 1480 u16 cap = le16_to_cpu(cap_resp->cap); 1481 1482 switch (cap) { 1483 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1484 caps->valid_functions = number; 1485 ice_debug(hw, ICE_DBG_INIT, 1486 "HW caps: Valid Functions = %d\n", 1487 caps->valid_functions); 1488 break; 1489 case ICE_AQC_CAPS_SRIOV: 1490 caps->sr_iov_1_1 = (number == 1); 1491 ice_debug(hw, ICE_DBG_INIT, 1492 "HW caps: SR-IOV = %d\n", caps->sr_iov_1_1); 1493 break; 1494 case ICE_AQC_CAPS_VF: 1495 if (dev_p) { 1496 dev_p->num_vfs_exposed = number; 1497 ice_debug(hw, ICE_DBG_INIT, 1498 "HW caps: VFs exposed = %d\n", 1499 dev_p->num_vfs_exposed); 1500 } else if (func_p) { 1501 func_p->num_allocd_vfs = number; 1502 func_p->vf_base_id = logical_id; 1503 ice_debug(hw, ICE_DBG_INIT, 1504 "HW caps: VFs allocated = %d\n", 1505 func_p->num_allocd_vfs); 1506 ice_debug(hw, ICE_DBG_INIT, 1507 "HW caps: VF base_id = %d\n", 1508 func_p->vf_base_id); 1509 } 1510 break; 1511 case ICE_AQC_CAPS_VSI: 1512 if (dev_p) { 1513 dev_p->num_vsi_allocd_to_host = number; 1514 ice_debug(hw, ICE_DBG_INIT, 1515 "HW caps: Dev.VSI cnt = %d\n", 1516 dev_p->num_vsi_allocd_to_host); 1517 } else if (func_p) { 1518 func_p->guar_num_vsi = 1519 ice_get_num_per_func(hw, ICE_MAX_VSI); 1520 ice_debug(hw, ICE_DBG_INIT, 1521 "HW caps: Func.VSI cnt = %d\n", 1522 number); 1523 } 1524 break; 1525 case ICE_AQC_CAPS_RSS: 1526 caps->rss_table_size = number; 1527 caps->rss_table_entry_width = logical_id; 1528 ice_debug(hw, ICE_DBG_INIT, 1529 "HW caps: RSS table size = %d\n", 1530 caps->rss_table_size); 1531 ice_debug(hw, ICE_DBG_INIT, 1532 "HW caps: RSS table width = %d\n", 1533 caps->rss_table_entry_width); 1534 break; 1535 case ICE_AQC_CAPS_RXQS: 1536 caps->num_rxq = number; 1537 caps->rxq_first_id = phys_id; 1538 ice_debug(hw, ICE_DBG_INIT, 1539 "HW caps: Num Rx Qs = %d\n", caps->num_rxq); 1540 ice_debug(hw, ICE_DBG_INIT, 1541 "HW caps: Rx first queue ID = %d\n", 1542 caps->rxq_first_id); 1543 break; 1544 case ICE_AQC_CAPS_TXQS: 1545 caps->num_txq = number; 1546 caps->txq_first_id = phys_id; 1547 ice_debug(hw, ICE_DBG_INIT, 1548 "HW caps: Num Tx Qs = %d\n", caps->num_txq); 1549 ice_debug(hw, ICE_DBG_INIT, 1550 "HW caps: Tx first queue ID = %d\n", 1551 caps->txq_first_id); 1552 break; 1553 case ICE_AQC_CAPS_MSIX: 1554 caps->num_msix_vectors = number; 1555 caps->msix_vector_first_id = phys_id; 1556 ice_debug(hw, ICE_DBG_INIT, 1557 "HW caps: MSIX vector count = %d\n", 1558 caps->num_msix_vectors); 1559 ice_debug(hw, ICE_DBG_INIT, 1560 "HW caps: MSIX first vector index = %d\n", 1561 caps->msix_vector_first_id); 1562 break; 1563 case ICE_AQC_CAPS_MAX_MTU: 1564 caps->max_mtu = number; 1565 if (dev_p) 1566 ice_debug(hw, ICE_DBG_INIT, 1567 "HW caps: Dev.MaxMTU = %d\n", 1568 caps->max_mtu); 1569 else if (func_p) 1570 ice_debug(hw, ICE_DBG_INIT, 1571 "HW caps: func.MaxMTU = %d\n", 1572 caps->max_mtu); 1573 break; 1574 default: 1575 ice_debug(hw, ICE_DBG_INIT, 1576 "HW caps: Unknown capability[%d]: 0x%x\n", i, 1577 cap); 1578 break; 1579 } 1580 } 1581 } 1582 1583 /** 1584 * ice_aq_discover_caps - query function/device capabilities 1585 * @hw: pointer to the HW struct 1586 * @buf: a virtual buffer to hold the capabilities 1587 * @buf_size: Size of the virtual buffer 1588 * @cap_count: cap count needed if AQ err==ENOMEM 1589 * @opc: capabilities type to discover - pass in the command opcode 1590 * @cd: pointer to command details structure or NULL 1591 * 1592 * Get the function(0x000a)/device(0x000b) capabilities description from 1593 * the firmware. 1594 */ 1595 static enum ice_status 1596 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 1597 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1598 { 1599 struct ice_aqc_list_caps *cmd; 1600 struct ice_aq_desc desc; 1601 enum ice_status status; 1602 1603 cmd = &desc.params.get_cap; 1604 1605 if (opc != ice_aqc_opc_list_func_caps && 1606 opc != ice_aqc_opc_list_dev_caps) 1607 return ICE_ERR_PARAM; 1608 1609 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1610 1611 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1612 if (!status) 1613 ice_parse_caps(hw, buf, le32_to_cpu(cmd->count), opc); 1614 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM) 1615 *cap_count = le32_to_cpu(cmd->count); 1616 return status; 1617 } 1618 1619 /** 1620 * ice_discover_caps - get info about the HW 1621 * @hw: pointer to the hardware structure 1622 * @opc: capabilities type to discover - pass in the command opcode 1623 */ 1624 static enum ice_status 1625 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc) 1626 { 1627 enum ice_status status; 1628 u32 cap_count; 1629 u16 cbuf_len; 1630 u8 retries; 1631 1632 /* The driver doesn't know how many capabilities the device will return 1633 * so the buffer size required isn't known ahead of time. The driver 1634 * starts with cbuf_len and if this turns out to be insufficient, the 1635 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs. 1636 * The driver then allocates the buffer based on the count and retries 1637 * the operation. So it follows that the retry count is 2. 1638 */ 1639 #define ICE_GET_CAP_BUF_COUNT 40 1640 #define ICE_GET_CAP_RETRY_COUNT 2 1641 1642 cap_count = ICE_GET_CAP_BUF_COUNT; 1643 retries = ICE_GET_CAP_RETRY_COUNT; 1644 1645 do { 1646 void *cbuf; 1647 1648 cbuf_len = (u16)(cap_count * 1649 sizeof(struct ice_aqc_list_caps_elem)); 1650 cbuf = devm_kzalloc(ice_hw_to_dev(hw), cbuf_len, GFP_KERNEL); 1651 if (!cbuf) 1652 return ICE_ERR_NO_MEMORY; 1653 1654 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count, 1655 opc, NULL); 1656 devm_kfree(ice_hw_to_dev(hw), cbuf); 1657 1658 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM) 1659 break; 1660 1661 /* If ENOMEM is returned, try again with bigger buffer */ 1662 } while (--retries); 1663 1664 return status; 1665 } 1666 1667 /** 1668 * ice_get_caps - get info about the HW 1669 * @hw: pointer to the hardware structure 1670 */ 1671 enum ice_status ice_get_caps(struct ice_hw *hw) 1672 { 1673 enum ice_status status; 1674 1675 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps); 1676 if (!status) 1677 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps); 1678 1679 return status; 1680 } 1681 1682 /** 1683 * ice_aq_manage_mac_write - manage MAC address write command 1684 * @hw: pointer to the HW struct 1685 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 1686 * @flags: flags to control write behavior 1687 * @cd: pointer to command details structure or NULL 1688 * 1689 * This function is used to write MAC address to the NVM (0x0108). 1690 */ 1691 enum ice_status 1692 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 1693 struct ice_sq_cd *cd) 1694 { 1695 struct ice_aqc_manage_mac_write *cmd; 1696 struct ice_aq_desc desc; 1697 1698 cmd = &desc.params.mac_write; 1699 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 1700 1701 cmd->flags = flags; 1702 1703 /* Prep values for flags, sah, sal */ 1704 cmd->sah = htons(*((const u16 *)mac_addr)); 1705 cmd->sal = htonl(*((const u32 *)(mac_addr + 2))); 1706 1707 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1708 } 1709 1710 /** 1711 * ice_aq_clear_pxe_mode 1712 * @hw: pointer to the HW struct 1713 * 1714 * Tell the firmware that the driver is taking over from PXE (0x0110). 1715 */ 1716 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 1717 { 1718 struct ice_aq_desc desc; 1719 1720 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 1721 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 1722 1723 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1724 } 1725 1726 /** 1727 * ice_clear_pxe_mode - clear pxe operations mode 1728 * @hw: pointer to the HW struct 1729 * 1730 * Make sure all PXE mode settings are cleared, including things 1731 * like descriptor fetch/write-back mode. 1732 */ 1733 void ice_clear_pxe_mode(struct ice_hw *hw) 1734 { 1735 if (ice_check_sq_alive(hw, &hw->adminq)) 1736 ice_aq_clear_pxe_mode(hw); 1737 } 1738 1739 /** 1740 * ice_get_link_speed_based_on_phy_type - returns link speed 1741 * @phy_type_low: lower part of phy_type 1742 * @phy_type_high: higher part of phy_type 1743 * 1744 * This helper function will convert an entry in PHY type structure 1745 * [phy_type_low, phy_type_high] to its corresponding link speed. 1746 * Note: In the structure of [phy_type_low, phy_type_high], there should 1747 * be one bit set, as this function will convert one PHY type to its 1748 * speed. 1749 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 1750 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 1751 */ 1752 static u16 1753 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 1754 { 1755 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 1756 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 1757 1758 switch (phy_type_low) { 1759 case ICE_PHY_TYPE_LOW_100BASE_TX: 1760 case ICE_PHY_TYPE_LOW_100M_SGMII: 1761 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 1762 break; 1763 case ICE_PHY_TYPE_LOW_1000BASE_T: 1764 case ICE_PHY_TYPE_LOW_1000BASE_SX: 1765 case ICE_PHY_TYPE_LOW_1000BASE_LX: 1766 case ICE_PHY_TYPE_LOW_1000BASE_KX: 1767 case ICE_PHY_TYPE_LOW_1G_SGMII: 1768 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 1769 break; 1770 case ICE_PHY_TYPE_LOW_2500BASE_T: 1771 case ICE_PHY_TYPE_LOW_2500BASE_X: 1772 case ICE_PHY_TYPE_LOW_2500BASE_KX: 1773 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 1774 break; 1775 case ICE_PHY_TYPE_LOW_5GBASE_T: 1776 case ICE_PHY_TYPE_LOW_5GBASE_KR: 1777 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 1778 break; 1779 case ICE_PHY_TYPE_LOW_10GBASE_T: 1780 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 1781 case ICE_PHY_TYPE_LOW_10GBASE_SR: 1782 case ICE_PHY_TYPE_LOW_10GBASE_LR: 1783 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 1784 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 1785 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 1786 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 1787 break; 1788 case ICE_PHY_TYPE_LOW_25GBASE_T: 1789 case ICE_PHY_TYPE_LOW_25GBASE_CR: 1790 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 1791 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 1792 case ICE_PHY_TYPE_LOW_25GBASE_SR: 1793 case ICE_PHY_TYPE_LOW_25GBASE_LR: 1794 case ICE_PHY_TYPE_LOW_25GBASE_KR: 1795 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 1796 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 1797 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 1798 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 1799 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 1800 break; 1801 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 1802 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 1803 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 1804 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 1805 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 1806 case ICE_PHY_TYPE_LOW_40G_XLAUI: 1807 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 1808 break; 1809 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 1810 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 1811 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 1812 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 1813 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 1814 case ICE_PHY_TYPE_LOW_50G_LAUI2: 1815 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 1816 case ICE_PHY_TYPE_LOW_50G_AUI2: 1817 case ICE_PHY_TYPE_LOW_50GBASE_CP: 1818 case ICE_PHY_TYPE_LOW_50GBASE_SR: 1819 case ICE_PHY_TYPE_LOW_50GBASE_FR: 1820 case ICE_PHY_TYPE_LOW_50GBASE_LR: 1821 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 1822 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 1823 case ICE_PHY_TYPE_LOW_50G_AUI1: 1824 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 1825 break; 1826 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 1827 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 1828 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 1829 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 1830 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 1831 case ICE_PHY_TYPE_LOW_100G_CAUI4: 1832 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 1833 case ICE_PHY_TYPE_LOW_100G_AUI4: 1834 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 1835 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 1836 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 1837 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 1838 case ICE_PHY_TYPE_LOW_100GBASE_DR: 1839 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 1840 break; 1841 default: 1842 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 1843 break; 1844 } 1845 1846 switch (phy_type_high) { 1847 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 1848 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 1849 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 1850 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 1851 case ICE_PHY_TYPE_HIGH_100G_AUI2: 1852 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 1853 break; 1854 default: 1855 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 1856 break; 1857 } 1858 1859 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 1860 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 1861 return ICE_AQ_LINK_SPEED_UNKNOWN; 1862 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 1863 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 1864 return ICE_AQ_LINK_SPEED_UNKNOWN; 1865 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 1866 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 1867 return speed_phy_type_low; 1868 else 1869 return speed_phy_type_high; 1870 } 1871 1872 /** 1873 * ice_update_phy_type 1874 * @phy_type_low: pointer to the lower part of phy_type 1875 * @phy_type_high: pointer to the higher part of phy_type 1876 * @link_speeds_bitmap: targeted link speeds bitmap 1877 * 1878 * Note: For the link_speeds_bitmap structure, you can check it at 1879 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 1880 * link_speeds_bitmap include multiple speeds. 1881 * 1882 * Each entry in this [phy_type_low, phy_type_high] structure will 1883 * present a certain link speed. This helper function will turn on bits 1884 * in [phy_type_low, phy_type_high] structure based on the value of 1885 * link_speeds_bitmap input parameter. 1886 */ 1887 void 1888 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 1889 u16 link_speeds_bitmap) 1890 { 1891 u16 speed = ICE_AQ_LINK_SPEED_UNKNOWN; 1892 u64 pt_high; 1893 u64 pt_low; 1894 int index; 1895 1896 /* We first check with low part of phy_type */ 1897 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 1898 pt_low = BIT_ULL(index); 1899 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 1900 1901 if (link_speeds_bitmap & speed) 1902 *phy_type_low |= BIT_ULL(index); 1903 } 1904 1905 /* We then check with high part of phy_type */ 1906 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 1907 pt_high = BIT_ULL(index); 1908 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 1909 1910 if (link_speeds_bitmap & speed) 1911 *phy_type_high |= BIT_ULL(index); 1912 } 1913 } 1914 1915 /** 1916 * ice_aq_set_phy_cfg 1917 * @hw: pointer to the HW struct 1918 * @lport: logical port number 1919 * @cfg: structure with PHY configuration data to be set 1920 * @cd: pointer to command details structure or NULL 1921 * 1922 * Set the various PHY configuration parameters supported on the Port. 1923 * One or more of the Set PHY config parameters may be ignored in an MFP 1924 * mode as the PF may not have the privilege to set some of the PHY Config 1925 * parameters. This status will be indicated by the command response (0x0601). 1926 */ 1927 enum ice_status 1928 ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport, 1929 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 1930 { 1931 struct ice_aq_desc desc; 1932 1933 if (!cfg) 1934 return ICE_ERR_PARAM; 1935 1936 /* Ensure that only valid bits of cfg->caps can be turned on. */ 1937 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 1938 ice_debug(hw, ICE_DBG_PHY, 1939 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 1940 cfg->caps); 1941 1942 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 1943 } 1944 1945 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 1946 desc.params.set_phy.lport_num = lport; 1947 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1948 1949 return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 1950 } 1951 1952 /** 1953 * ice_update_link_info - update status of the HW network link 1954 * @pi: port info structure of the interested logical port 1955 */ 1956 enum ice_status ice_update_link_info(struct ice_port_info *pi) 1957 { 1958 struct ice_aqc_get_phy_caps_data *pcaps; 1959 struct ice_phy_info *phy_info; 1960 enum ice_status status; 1961 struct ice_hw *hw; 1962 1963 if (!pi) 1964 return ICE_ERR_PARAM; 1965 1966 hw = pi->hw; 1967 1968 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 1969 if (!pcaps) 1970 return ICE_ERR_NO_MEMORY; 1971 1972 phy_info = &pi->phy; 1973 status = ice_aq_get_link_info(pi, true, NULL, NULL); 1974 if (status) 1975 goto out; 1976 1977 if (phy_info->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) { 1978 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, 1979 pcaps, NULL); 1980 if (status) 1981 goto out; 1982 1983 memcpy(phy_info->link_info.module_type, &pcaps->module_type, 1984 sizeof(phy_info->link_info.module_type)); 1985 } 1986 out: 1987 devm_kfree(ice_hw_to_dev(hw), pcaps); 1988 return status; 1989 } 1990 1991 /** 1992 * ice_set_fc 1993 * @pi: port information structure 1994 * @aq_failures: pointer to status code, specific to ice_set_fc routine 1995 * @ena_auto_link_update: enable automatic link update 1996 * 1997 * Set the requested flow control mode. 1998 */ 1999 enum ice_status 2000 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2001 { 2002 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2003 struct ice_aqc_get_phy_caps_data *pcaps; 2004 enum ice_status status; 2005 u8 pause_mask = 0x0; 2006 struct ice_hw *hw; 2007 2008 if (!pi) 2009 return ICE_ERR_PARAM; 2010 hw = pi->hw; 2011 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE; 2012 2013 switch (pi->fc.req_mode) { 2014 case ICE_FC_FULL: 2015 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2016 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2017 break; 2018 case ICE_FC_RX_PAUSE: 2019 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2020 break; 2021 case ICE_FC_TX_PAUSE: 2022 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2023 break; 2024 default: 2025 break; 2026 } 2027 2028 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 2029 if (!pcaps) 2030 return ICE_ERR_NO_MEMORY; 2031 2032 /* Get the current PHY config */ 2033 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 2034 NULL); 2035 if (status) { 2036 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2037 goto out; 2038 } 2039 2040 /* clear the old pause settings */ 2041 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2042 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2043 2044 /* set the new capabilities */ 2045 cfg.caps |= pause_mask; 2046 2047 /* If the capabilities have changed, then set the new config */ 2048 if (cfg.caps != pcaps->caps) { 2049 int retry_count, retry_max = 10; 2050 2051 /* Auto restart link so settings take effect */ 2052 if (ena_auto_link_update) 2053 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2054 /* Copy over all the old settings */ 2055 cfg.phy_type_high = pcaps->phy_type_high; 2056 cfg.phy_type_low = pcaps->phy_type_low; 2057 cfg.low_power_ctrl = pcaps->low_power_ctrl; 2058 cfg.eee_cap = pcaps->eee_cap; 2059 cfg.eeer_value = pcaps->eeer_value; 2060 cfg.link_fec_opt = pcaps->link_fec_options; 2061 2062 status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL); 2063 if (status) { 2064 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 2065 goto out; 2066 } 2067 2068 /* Update the link info 2069 * It sometimes takes a really long time for link to 2070 * come back from the atomic reset. Thus, we wait a 2071 * little bit. 2072 */ 2073 for (retry_count = 0; retry_count < retry_max; retry_count++) { 2074 status = ice_update_link_info(pi); 2075 2076 if (!status) 2077 break; 2078 2079 mdelay(100); 2080 } 2081 2082 if (status) 2083 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 2084 } 2085 2086 out: 2087 devm_kfree(ice_hw_to_dev(hw), pcaps); 2088 return status; 2089 } 2090 2091 /** 2092 * ice_get_link_status - get status of the HW network link 2093 * @pi: port information structure 2094 * @link_up: pointer to bool (true/false = linkup/linkdown) 2095 * 2096 * Variable link_up is true if link is up, false if link is down. 2097 * The variable link_up is invalid if status is non zero. As a 2098 * result of this call, link status reporting becomes enabled 2099 */ 2100 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 2101 { 2102 struct ice_phy_info *phy_info; 2103 enum ice_status status = 0; 2104 2105 if (!pi || !link_up) 2106 return ICE_ERR_PARAM; 2107 2108 phy_info = &pi->phy; 2109 2110 if (phy_info->get_link_info) { 2111 status = ice_update_link_info(pi); 2112 2113 if (status) 2114 ice_debug(pi->hw, ICE_DBG_LINK, 2115 "get link status error, status = %d\n", 2116 status); 2117 } 2118 2119 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 2120 2121 return status; 2122 } 2123 2124 /** 2125 * ice_aq_set_link_restart_an 2126 * @pi: pointer to the port information structure 2127 * @ena_link: if true: enable link, if false: disable link 2128 * @cd: pointer to command details structure or NULL 2129 * 2130 * Sets up the link and restarts the Auto-Negotiation over the link. 2131 */ 2132 enum ice_status 2133 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 2134 struct ice_sq_cd *cd) 2135 { 2136 struct ice_aqc_restart_an *cmd; 2137 struct ice_aq_desc desc; 2138 2139 cmd = &desc.params.restart_an; 2140 2141 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 2142 2143 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 2144 cmd->lport_num = pi->lport; 2145 if (ena_link) 2146 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 2147 else 2148 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 2149 2150 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 2151 } 2152 2153 /** 2154 * ice_aq_set_event_mask 2155 * @hw: pointer to the HW struct 2156 * @port_num: port number of the physical function 2157 * @mask: event mask to be set 2158 * @cd: pointer to command details structure or NULL 2159 * 2160 * Set event mask (0x0613) 2161 */ 2162 enum ice_status 2163 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 2164 struct ice_sq_cd *cd) 2165 { 2166 struct ice_aqc_set_event_mask *cmd; 2167 struct ice_aq_desc desc; 2168 2169 cmd = &desc.params.set_event_mask; 2170 2171 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 2172 2173 cmd->lport_num = port_num; 2174 2175 cmd->event_mask = cpu_to_le16(mask); 2176 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2177 } 2178 2179 /** 2180 * ice_aq_set_port_id_led 2181 * @pi: pointer to the port information 2182 * @is_orig_mode: is this LED set to original mode (by the net-list) 2183 * @cd: pointer to command details structure or NULL 2184 * 2185 * Set LED value for the given port (0x06e9) 2186 */ 2187 enum ice_status 2188 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 2189 struct ice_sq_cd *cd) 2190 { 2191 struct ice_aqc_set_port_id_led *cmd; 2192 struct ice_hw *hw = pi->hw; 2193 struct ice_aq_desc desc; 2194 2195 cmd = &desc.params.set_port_id_led; 2196 2197 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 2198 2199 if (is_orig_mode) 2200 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 2201 else 2202 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 2203 2204 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2205 } 2206 2207 /** 2208 * __ice_aq_get_set_rss_lut 2209 * @hw: pointer to the hardware structure 2210 * @vsi_id: VSI FW index 2211 * @lut_type: LUT table type 2212 * @lut: pointer to the LUT buffer provided by the caller 2213 * @lut_size: size of the LUT buffer 2214 * @glob_lut_idx: global LUT index 2215 * @set: set true to set the table, false to get the table 2216 * 2217 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 2218 */ 2219 static enum ice_status 2220 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 2221 u16 lut_size, u8 glob_lut_idx, bool set) 2222 { 2223 struct ice_aqc_get_set_rss_lut *cmd_resp; 2224 struct ice_aq_desc desc; 2225 enum ice_status status; 2226 u16 flags = 0; 2227 2228 cmd_resp = &desc.params.get_set_rss_lut; 2229 2230 if (set) { 2231 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 2232 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2233 } else { 2234 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 2235 } 2236 2237 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 2238 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 2239 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 2240 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 2241 2242 switch (lut_type) { 2243 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 2244 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 2245 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 2246 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 2247 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 2248 break; 2249 default: 2250 status = ICE_ERR_PARAM; 2251 goto ice_aq_get_set_rss_lut_exit; 2252 } 2253 2254 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 2255 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 2256 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 2257 2258 if (!set) 2259 goto ice_aq_get_set_rss_lut_send; 2260 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 2261 if (!set) 2262 goto ice_aq_get_set_rss_lut_send; 2263 } else { 2264 goto ice_aq_get_set_rss_lut_send; 2265 } 2266 2267 /* LUT size is only valid for Global and PF table types */ 2268 switch (lut_size) { 2269 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 2270 break; 2271 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 2272 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 2273 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 2274 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 2275 break; 2276 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 2277 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 2278 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 2279 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 2280 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 2281 break; 2282 } 2283 /* fall-through */ 2284 default: 2285 status = ICE_ERR_PARAM; 2286 goto ice_aq_get_set_rss_lut_exit; 2287 } 2288 2289 ice_aq_get_set_rss_lut_send: 2290 cmd_resp->flags = cpu_to_le16(flags); 2291 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 2292 2293 ice_aq_get_set_rss_lut_exit: 2294 return status; 2295 } 2296 2297 /** 2298 * ice_aq_get_rss_lut 2299 * @hw: pointer to the hardware structure 2300 * @vsi_handle: software VSI handle 2301 * @lut_type: LUT table type 2302 * @lut: pointer to the LUT buffer provided by the caller 2303 * @lut_size: size of the LUT buffer 2304 * 2305 * get the RSS lookup table, PF or VSI type 2306 */ 2307 enum ice_status 2308 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 2309 u8 *lut, u16 lut_size) 2310 { 2311 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 2312 return ICE_ERR_PARAM; 2313 2314 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2315 lut_type, lut, lut_size, 0, false); 2316 } 2317 2318 /** 2319 * ice_aq_set_rss_lut 2320 * @hw: pointer to the hardware structure 2321 * @vsi_handle: software VSI handle 2322 * @lut_type: LUT table type 2323 * @lut: pointer to the LUT buffer provided by the caller 2324 * @lut_size: size of the LUT buffer 2325 * 2326 * set the RSS lookup table, PF or VSI type 2327 */ 2328 enum ice_status 2329 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 2330 u8 *lut, u16 lut_size) 2331 { 2332 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 2333 return ICE_ERR_PARAM; 2334 2335 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2336 lut_type, lut, lut_size, 0, true); 2337 } 2338 2339 /** 2340 * __ice_aq_get_set_rss_key 2341 * @hw: pointer to the HW struct 2342 * @vsi_id: VSI FW index 2343 * @key: pointer to key info struct 2344 * @set: set true to set the key, false to get the key 2345 * 2346 * get (0x0B04) or set (0x0B02) the RSS key per VSI 2347 */ 2348 static enum 2349 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 2350 struct ice_aqc_get_set_rss_keys *key, 2351 bool set) 2352 { 2353 struct ice_aqc_get_set_rss_key *cmd_resp; 2354 u16 key_size = sizeof(*key); 2355 struct ice_aq_desc desc; 2356 2357 cmd_resp = &desc.params.get_set_rss_key; 2358 2359 if (set) { 2360 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 2361 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2362 } else { 2363 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 2364 } 2365 2366 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 2367 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 2368 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 2369 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 2370 2371 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 2372 } 2373 2374 /** 2375 * ice_aq_get_rss_key 2376 * @hw: pointer to the HW struct 2377 * @vsi_handle: software VSI handle 2378 * @key: pointer to key info struct 2379 * 2380 * get the RSS key per VSI 2381 */ 2382 enum ice_status 2383 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 2384 struct ice_aqc_get_set_rss_keys *key) 2385 { 2386 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 2387 return ICE_ERR_PARAM; 2388 2389 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2390 key, false); 2391 } 2392 2393 /** 2394 * ice_aq_set_rss_key 2395 * @hw: pointer to the HW struct 2396 * @vsi_handle: software VSI handle 2397 * @keys: pointer to key info struct 2398 * 2399 * set the RSS key per VSI 2400 */ 2401 enum ice_status 2402 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 2403 struct ice_aqc_get_set_rss_keys *keys) 2404 { 2405 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 2406 return ICE_ERR_PARAM; 2407 2408 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 2409 keys, true); 2410 } 2411 2412 /** 2413 * ice_aq_add_lan_txq 2414 * @hw: pointer to the hardware structure 2415 * @num_qgrps: Number of added queue groups 2416 * @qg_list: list of queue groups to be added 2417 * @buf_size: size of buffer for indirect command 2418 * @cd: pointer to command details structure or NULL 2419 * 2420 * Add Tx LAN queue (0x0C30) 2421 * 2422 * NOTE: 2423 * Prior to calling add Tx LAN queue: 2424 * Initialize the following as part of the Tx queue context: 2425 * Completion queue ID if the queue uses Completion queue, Quanta profile, 2426 * Cache profile and Packet shaper profile. 2427 * 2428 * After add Tx LAN queue AQ command is completed: 2429 * Interrupts should be associated with specific queues, 2430 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 2431 * flow. 2432 */ 2433 static enum ice_status 2434 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 2435 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 2436 struct ice_sq_cd *cd) 2437 { 2438 u16 i, sum_header_size, sum_q_size = 0; 2439 struct ice_aqc_add_tx_qgrp *list; 2440 struct ice_aqc_add_txqs *cmd; 2441 struct ice_aq_desc desc; 2442 2443 cmd = &desc.params.add_txqs; 2444 2445 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 2446 2447 if (!qg_list) 2448 return ICE_ERR_PARAM; 2449 2450 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 2451 return ICE_ERR_PARAM; 2452 2453 sum_header_size = num_qgrps * 2454 (sizeof(*qg_list) - sizeof(*qg_list->txqs)); 2455 2456 list = qg_list; 2457 for (i = 0; i < num_qgrps; i++) { 2458 struct ice_aqc_add_txqs_perq *q = list->txqs; 2459 2460 sum_q_size += list->num_txqs * sizeof(*q); 2461 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs); 2462 } 2463 2464 if (buf_size != (sum_header_size + sum_q_size)) 2465 return ICE_ERR_PARAM; 2466 2467 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2468 2469 cmd->num_qgrps = num_qgrps; 2470 2471 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 2472 } 2473 2474 /** 2475 * ice_aq_dis_lan_txq 2476 * @hw: pointer to the hardware structure 2477 * @num_qgrps: number of groups in the list 2478 * @qg_list: the list of groups to disable 2479 * @buf_size: the total size of the qg_list buffer in bytes 2480 * @rst_src: if called due to reset, specifies the reset source 2481 * @vmvf_num: the relative VM or VF number that is undergoing the reset 2482 * @cd: pointer to command details structure or NULL 2483 * 2484 * Disable LAN Tx queue (0x0C31) 2485 */ 2486 static enum ice_status 2487 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 2488 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 2489 enum ice_disq_rst_src rst_src, u16 vmvf_num, 2490 struct ice_sq_cd *cd) 2491 { 2492 struct ice_aqc_dis_txqs *cmd; 2493 struct ice_aq_desc desc; 2494 enum ice_status status; 2495 u16 i, sz = 0; 2496 2497 cmd = &desc.params.dis_txqs; 2498 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 2499 2500 /* qg_list can be NULL only in VM/VF reset flow */ 2501 if (!qg_list && !rst_src) 2502 return ICE_ERR_PARAM; 2503 2504 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 2505 return ICE_ERR_PARAM; 2506 2507 cmd->num_entries = num_qgrps; 2508 2509 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 2510 ICE_AQC_Q_DIS_TIMEOUT_M); 2511 2512 switch (rst_src) { 2513 case ICE_VM_RESET: 2514 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 2515 cmd->vmvf_and_timeout |= 2516 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 2517 break; 2518 case ICE_VF_RESET: 2519 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 2520 /* In this case, FW expects vmvf_num to be absolute VF ID */ 2521 cmd->vmvf_and_timeout |= 2522 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 2523 ICE_AQC_Q_DIS_VMVF_NUM_M); 2524 break; 2525 case ICE_NO_RESET: 2526 default: 2527 break; 2528 } 2529 2530 /* flush pipe on time out */ 2531 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 2532 /* If no queue group info, we are in a reset flow. Issue the AQ */ 2533 if (!qg_list) 2534 goto do_aq; 2535 2536 /* set RD bit to indicate that command buffer is provided by the driver 2537 * and it needs to be read by the firmware 2538 */ 2539 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2540 2541 for (i = 0; i < num_qgrps; ++i) { 2542 /* Calculate the size taken up by the queue IDs in this group */ 2543 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id); 2544 2545 /* Add the size of the group header */ 2546 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id); 2547 2548 /* If the num of queues is even, add 2 bytes of padding */ 2549 if ((qg_list[i].num_qs % 2) == 0) 2550 sz += 2; 2551 } 2552 2553 if (buf_size != sz) 2554 return ICE_ERR_PARAM; 2555 2556 do_aq: 2557 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 2558 if (status) { 2559 if (!qg_list) 2560 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 2561 vmvf_num, hw->adminq.sq_last_status); 2562 else 2563 ice_debug(hw, ICE_DBG_SCHED, "disable Q %d failed %d\n", 2564 le16_to_cpu(qg_list[0].q_id[0]), 2565 hw->adminq.sq_last_status); 2566 } 2567 return status; 2568 } 2569 2570 /* End of FW Admin Queue command wrappers */ 2571 2572 /** 2573 * ice_write_byte - write a byte to a packed context structure 2574 * @src_ctx: the context structure to read from 2575 * @dest_ctx: the context to be written to 2576 * @ce_info: a description of the struct to be filled 2577 */ 2578 static void 2579 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2580 { 2581 u8 src_byte, dest_byte, mask; 2582 u8 *from, *dest; 2583 u16 shift_width; 2584 2585 /* copy from the next struct field */ 2586 from = src_ctx + ce_info->offset; 2587 2588 /* prepare the bits and mask */ 2589 shift_width = ce_info->lsb % 8; 2590 mask = (u8)(BIT(ce_info->width) - 1); 2591 2592 src_byte = *from; 2593 src_byte &= mask; 2594 2595 /* shift to correct alignment */ 2596 mask <<= shift_width; 2597 src_byte <<= shift_width; 2598 2599 /* get the current bits from the target bit string */ 2600 dest = dest_ctx + (ce_info->lsb / 8); 2601 2602 memcpy(&dest_byte, dest, sizeof(dest_byte)); 2603 2604 dest_byte &= ~mask; /* get the bits not changing */ 2605 dest_byte |= src_byte; /* add in the new bits */ 2606 2607 /* put it all back */ 2608 memcpy(dest, &dest_byte, sizeof(dest_byte)); 2609 } 2610 2611 /** 2612 * ice_write_word - write a word to a packed context structure 2613 * @src_ctx: the context structure to read from 2614 * @dest_ctx: the context to be written to 2615 * @ce_info: a description of the struct to be filled 2616 */ 2617 static void 2618 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2619 { 2620 u16 src_word, mask; 2621 __le16 dest_word; 2622 u8 *from, *dest; 2623 u16 shift_width; 2624 2625 /* copy from the next struct field */ 2626 from = src_ctx + ce_info->offset; 2627 2628 /* prepare the bits and mask */ 2629 shift_width = ce_info->lsb % 8; 2630 mask = BIT(ce_info->width) - 1; 2631 2632 /* don't swizzle the bits until after the mask because the mask bits 2633 * will be in a different bit position on big endian machines 2634 */ 2635 src_word = *(u16 *)from; 2636 src_word &= mask; 2637 2638 /* shift to correct alignment */ 2639 mask <<= shift_width; 2640 src_word <<= shift_width; 2641 2642 /* get the current bits from the target bit string */ 2643 dest = dest_ctx + (ce_info->lsb / 8); 2644 2645 memcpy(&dest_word, dest, sizeof(dest_word)); 2646 2647 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 2648 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 2649 2650 /* put it all back */ 2651 memcpy(dest, &dest_word, sizeof(dest_word)); 2652 } 2653 2654 /** 2655 * ice_write_dword - write a dword to a packed context structure 2656 * @src_ctx: the context structure to read from 2657 * @dest_ctx: the context to be written to 2658 * @ce_info: a description of the struct to be filled 2659 */ 2660 static void 2661 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2662 { 2663 u32 src_dword, mask; 2664 __le32 dest_dword; 2665 u8 *from, *dest; 2666 u16 shift_width; 2667 2668 /* copy from the next struct field */ 2669 from = src_ctx + ce_info->offset; 2670 2671 /* prepare the bits and mask */ 2672 shift_width = ce_info->lsb % 8; 2673 2674 /* if the field width is exactly 32 on an x86 machine, then the shift 2675 * operation will not work because the SHL instructions count is masked 2676 * to 5 bits so the shift will do nothing 2677 */ 2678 if (ce_info->width < 32) 2679 mask = BIT(ce_info->width) - 1; 2680 else 2681 mask = (u32)~0; 2682 2683 /* don't swizzle the bits until after the mask because the mask bits 2684 * will be in a different bit position on big endian machines 2685 */ 2686 src_dword = *(u32 *)from; 2687 src_dword &= mask; 2688 2689 /* shift to correct alignment */ 2690 mask <<= shift_width; 2691 src_dword <<= shift_width; 2692 2693 /* get the current bits from the target bit string */ 2694 dest = dest_ctx + (ce_info->lsb / 8); 2695 2696 memcpy(&dest_dword, dest, sizeof(dest_dword)); 2697 2698 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 2699 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 2700 2701 /* put it all back */ 2702 memcpy(dest, &dest_dword, sizeof(dest_dword)); 2703 } 2704 2705 /** 2706 * ice_write_qword - write a qword to a packed context structure 2707 * @src_ctx: the context structure to read from 2708 * @dest_ctx: the context to be written to 2709 * @ce_info: a description of the struct to be filled 2710 */ 2711 static void 2712 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2713 { 2714 u64 src_qword, mask; 2715 __le64 dest_qword; 2716 u8 *from, *dest; 2717 u16 shift_width; 2718 2719 /* copy from the next struct field */ 2720 from = src_ctx + ce_info->offset; 2721 2722 /* prepare the bits and mask */ 2723 shift_width = ce_info->lsb % 8; 2724 2725 /* if the field width is exactly 64 on an x86 machine, then the shift 2726 * operation will not work because the SHL instructions count is masked 2727 * to 6 bits so the shift will do nothing 2728 */ 2729 if (ce_info->width < 64) 2730 mask = BIT_ULL(ce_info->width) - 1; 2731 else 2732 mask = (u64)~0; 2733 2734 /* don't swizzle the bits until after the mask because the mask bits 2735 * will be in a different bit position on big endian machines 2736 */ 2737 src_qword = *(u64 *)from; 2738 src_qword &= mask; 2739 2740 /* shift to correct alignment */ 2741 mask <<= shift_width; 2742 src_qword <<= shift_width; 2743 2744 /* get the current bits from the target bit string */ 2745 dest = dest_ctx + (ce_info->lsb / 8); 2746 2747 memcpy(&dest_qword, dest, sizeof(dest_qword)); 2748 2749 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 2750 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 2751 2752 /* put it all back */ 2753 memcpy(dest, &dest_qword, sizeof(dest_qword)); 2754 } 2755 2756 /** 2757 * ice_set_ctx - set context bits in packed structure 2758 * @src_ctx: pointer to a generic non-packed context structure 2759 * @dest_ctx: pointer to memory for the packed structure 2760 * @ce_info: a description of the structure to be transformed 2761 */ 2762 enum ice_status 2763 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 2764 { 2765 int f; 2766 2767 for (f = 0; ce_info[f].width; f++) { 2768 /* We have to deal with each element of the FW response 2769 * using the correct size so that we are correct regardless 2770 * of the endianness of the machine. 2771 */ 2772 switch (ce_info[f].size_of) { 2773 case sizeof(u8): 2774 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 2775 break; 2776 case sizeof(u16): 2777 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 2778 break; 2779 case sizeof(u32): 2780 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 2781 break; 2782 case sizeof(u64): 2783 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 2784 break; 2785 default: 2786 return ICE_ERR_INVAL_SIZE; 2787 } 2788 } 2789 2790 return 0; 2791 } 2792 2793 /** 2794 * ice_ena_vsi_txq 2795 * @pi: port information structure 2796 * @vsi_handle: software VSI handle 2797 * @tc: TC number 2798 * @num_qgrps: Number of added queue groups 2799 * @buf: list of queue groups to be added 2800 * @buf_size: size of buffer for indirect command 2801 * @cd: pointer to command details structure or NULL 2802 * 2803 * This function adds one LAN queue 2804 */ 2805 enum ice_status 2806 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_qgrps, 2807 struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 2808 struct ice_sq_cd *cd) 2809 { 2810 struct ice_aqc_txsched_elem_data node = { 0 }; 2811 struct ice_sched_node *parent; 2812 enum ice_status status; 2813 struct ice_hw *hw; 2814 2815 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 2816 return ICE_ERR_CFG; 2817 2818 if (num_qgrps > 1 || buf->num_txqs > 1) 2819 return ICE_ERR_MAX_LIMIT; 2820 2821 hw = pi->hw; 2822 2823 if (!ice_is_vsi_valid(hw, vsi_handle)) 2824 return ICE_ERR_PARAM; 2825 2826 mutex_lock(&pi->sched_lock); 2827 2828 /* find a parent node */ 2829 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 2830 ICE_SCHED_NODE_OWNER_LAN); 2831 if (!parent) { 2832 status = ICE_ERR_PARAM; 2833 goto ena_txq_exit; 2834 } 2835 2836 buf->parent_teid = parent->info.node_teid; 2837 node.parent_teid = parent->info.node_teid; 2838 /* Mark that the values in the "generic" section as valid. The default 2839 * value in the "generic" section is zero. This means that : 2840 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 2841 * - 0 priority among siblings, indicated by Bit 1-3. 2842 * - WFQ, indicated by Bit 4. 2843 * - 0 Adjustment value is used in PSM credit update flow, indicated by 2844 * Bit 5-6. 2845 * - Bit 7 is reserved. 2846 * Without setting the generic section as valid in valid_sections, the 2847 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 2848 */ 2849 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC; 2850 2851 /* add the LAN queue */ 2852 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 2853 if (status) { 2854 ice_debug(hw, ICE_DBG_SCHED, "enable Q %d failed %d\n", 2855 le16_to_cpu(buf->txqs[0].txq_id), 2856 hw->adminq.sq_last_status); 2857 goto ena_txq_exit; 2858 } 2859 2860 node.node_teid = buf->txqs[0].q_teid; 2861 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 2862 2863 /* add a leaf node into schduler tree queue layer */ 2864 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 2865 2866 ena_txq_exit: 2867 mutex_unlock(&pi->sched_lock); 2868 return status; 2869 } 2870 2871 /** 2872 * ice_dis_vsi_txq 2873 * @pi: port information structure 2874 * @num_queues: number of queues 2875 * @q_ids: pointer to the q_id array 2876 * @q_teids: pointer to queue node teids 2877 * @rst_src: if called due to reset, specifies the reset source 2878 * @vmvf_num: the relative VM or VF number that is undergoing the reset 2879 * @cd: pointer to command details structure or NULL 2880 * 2881 * This function removes queues and their corresponding nodes in SW DB 2882 */ 2883 enum ice_status 2884 ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids, 2885 u32 *q_teids, enum ice_disq_rst_src rst_src, u16 vmvf_num, 2886 struct ice_sq_cd *cd) 2887 { 2888 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 2889 struct ice_aqc_dis_txq_item qg_list; 2890 u16 i; 2891 2892 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 2893 return ICE_ERR_CFG; 2894 2895 /* if queue is disabled already yet the disable queue command has to be 2896 * sent to complete the VF reset, then call ice_aq_dis_lan_txq without 2897 * any queue information 2898 */ 2899 2900 if (!num_queues && rst_src) 2901 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src, vmvf_num, 2902 NULL); 2903 2904 mutex_lock(&pi->sched_lock); 2905 2906 for (i = 0; i < num_queues; i++) { 2907 struct ice_sched_node *node; 2908 2909 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 2910 if (!node) 2911 continue; 2912 qg_list.parent_teid = node->info.parent_teid; 2913 qg_list.num_qs = 1; 2914 qg_list.q_id[0] = cpu_to_le16(q_ids[i]); 2915 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list, 2916 sizeof(qg_list), rst_src, vmvf_num, 2917 cd); 2918 2919 if (status) 2920 break; 2921 ice_free_sched_node(pi, node); 2922 } 2923 mutex_unlock(&pi->sched_lock); 2924 return status; 2925 } 2926 2927 /** 2928 * ice_cfg_vsi_qs - configure the new/existing VSI queues 2929 * @pi: port information structure 2930 * @vsi_handle: software VSI handle 2931 * @tc_bitmap: TC bitmap 2932 * @maxqs: max queues array per TC 2933 * @owner: LAN or RDMA 2934 * 2935 * This function adds/updates the VSI queues per TC. 2936 */ 2937 static enum ice_status 2938 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 2939 u16 *maxqs, u8 owner) 2940 { 2941 enum ice_status status = 0; 2942 u8 i; 2943 2944 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 2945 return ICE_ERR_CFG; 2946 2947 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 2948 return ICE_ERR_PARAM; 2949 2950 mutex_lock(&pi->sched_lock); 2951 2952 ice_for_each_traffic_class(i) { 2953 /* configuration is possible only if TC node is present */ 2954 if (!ice_sched_get_tc_node(pi, i)) 2955 continue; 2956 2957 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 2958 ice_is_tc_ena(tc_bitmap, i)); 2959 if (status) 2960 break; 2961 } 2962 2963 mutex_unlock(&pi->sched_lock); 2964 return status; 2965 } 2966 2967 /** 2968 * ice_cfg_vsi_lan - configure VSI LAN queues 2969 * @pi: port information structure 2970 * @vsi_handle: software VSI handle 2971 * @tc_bitmap: TC bitmap 2972 * @max_lanqs: max LAN queues array per TC 2973 * 2974 * This function adds/updates the VSI LAN queues per TC. 2975 */ 2976 enum ice_status 2977 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 2978 u16 *max_lanqs) 2979 { 2980 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 2981 ICE_SCHED_NODE_OWNER_LAN); 2982 } 2983 2984 /** 2985 * ice_replay_pre_init - replay pre initialization 2986 * @hw: pointer to the HW struct 2987 * 2988 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 2989 */ 2990 static enum ice_status ice_replay_pre_init(struct ice_hw *hw) 2991 { 2992 struct ice_switch_info *sw = hw->switch_info; 2993 u8 i; 2994 2995 /* Delete old entries from replay filter list head if there is any */ 2996 ice_rm_all_sw_replay_rule_info(hw); 2997 /* In start of replay, move entries into replay_rules list, it 2998 * will allow adding rules entries back to filt_rules list, 2999 * which is operational list. 3000 */ 3001 for (i = 0; i < ICE_SW_LKUP_LAST; i++) 3002 list_replace_init(&sw->recp_list[i].filt_rules, 3003 &sw->recp_list[i].filt_replay_rules); 3004 3005 return 0; 3006 } 3007 3008 /** 3009 * ice_replay_vsi - replay VSI configuration 3010 * @hw: pointer to the HW struct 3011 * @vsi_handle: driver VSI handle 3012 * 3013 * Restore all VSI configuration after reset. It is required to call this 3014 * function with main VSI first. 3015 */ 3016 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 3017 { 3018 enum ice_status status; 3019 3020 if (!ice_is_vsi_valid(hw, vsi_handle)) 3021 return ICE_ERR_PARAM; 3022 3023 /* Replay pre-initialization if there is any */ 3024 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 3025 status = ice_replay_pre_init(hw); 3026 if (status) 3027 return status; 3028 } 3029 3030 /* Replay per VSI all filters */ 3031 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 3032 return status; 3033 } 3034 3035 /** 3036 * ice_replay_post - post replay configuration cleanup 3037 * @hw: pointer to the HW struct 3038 * 3039 * Post replay cleanup. 3040 */ 3041 void ice_replay_post(struct ice_hw *hw) 3042 { 3043 /* Delete old entries from replay filter list head */ 3044 ice_rm_all_sw_replay_rule_info(hw); 3045 } 3046 3047 /** 3048 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 3049 * @hw: ptr to the hardware info 3050 * @hireg: high 32 bit HW register to read from 3051 * @loreg: low 32 bit HW register to read from 3052 * @prev_stat_loaded: bool to specify if previous stats are loaded 3053 * @prev_stat: ptr to previous loaded stat value 3054 * @cur_stat: ptr to current stat value 3055 */ 3056 void 3057 ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg, 3058 bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat) 3059 { 3060 u64 new_data; 3061 3062 new_data = rd32(hw, loreg); 3063 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; 3064 3065 /* device stats are not reset at PFR, they likely will not be zeroed 3066 * when the driver starts. So save the first values read and use them as 3067 * offsets to be subtracted from the raw values in order to report stats 3068 * that count from zero. 3069 */ 3070 if (!prev_stat_loaded) 3071 *prev_stat = new_data; 3072 if (new_data >= *prev_stat) 3073 *cur_stat = new_data - *prev_stat; 3074 else 3075 /* to manage the potential roll-over */ 3076 *cur_stat = (new_data + BIT_ULL(40)) - *prev_stat; 3077 *cur_stat &= 0xFFFFFFFFFFULL; 3078 } 3079 3080 /** 3081 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 3082 * @hw: ptr to the hardware info 3083 * @reg: HW register to read from 3084 * @prev_stat_loaded: bool to specify if previous stats are loaded 3085 * @prev_stat: ptr to previous loaded stat value 3086 * @cur_stat: ptr to current stat value 3087 */ 3088 void 3089 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 3090 u64 *prev_stat, u64 *cur_stat) 3091 { 3092 u32 new_data; 3093 3094 new_data = rd32(hw, reg); 3095 3096 /* device stats are not reset at PFR, they likely will not be zeroed 3097 * when the driver starts. So save the first values read and use them as 3098 * offsets to be subtracted from the raw values in order to report stats 3099 * that count from zero. 3100 */ 3101 if (!prev_stat_loaded) 3102 *prev_stat = new_data; 3103 if (new_data >= *prev_stat) 3104 *cur_stat = new_data - *prev_stat; 3105 else 3106 /* to manage the potential roll-over */ 3107 *cur_stat = (new_data + BIT_ULL(32)) - *prev_stat; 3108 } 3109 3110 /** 3111 * ice_sched_query_elem - query element information from HW 3112 * @hw: pointer to the HW struct 3113 * @node_teid: node TEID to be queried 3114 * @buf: buffer to element information 3115 * 3116 * This function queries HW element information 3117 */ 3118 enum ice_status 3119 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 3120 struct ice_aqc_get_elem *buf) 3121 { 3122 u16 buf_size, num_elem_ret = 0; 3123 enum ice_status status; 3124 3125 buf_size = sizeof(*buf); 3126 memset(buf, 0, buf_size); 3127 buf->generic[0].node_teid = cpu_to_le32(node_teid); 3128 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 3129 NULL); 3130 if (status || num_elem_ret != 1) 3131 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 3132 return status; 3133 } 3134