1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_sched.h" 6 #include "ice_adminq_cmd.h" 7 #include "ice_flow.h" 8 9 #define ICE_PF_RESET_WAIT_COUNT 300 10 11 /** 12 * ice_set_mac_type - Sets MAC type 13 * @hw: pointer to the HW structure 14 * 15 * This function sets the MAC type of the adapter based on the 16 * vendor ID and device ID stored in the HW structure. 17 */ 18 static enum ice_status ice_set_mac_type(struct ice_hw *hw) 19 { 20 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 21 return ICE_ERR_DEVICE_NOT_SUPPORTED; 22 23 switch (hw->device_id) { 24 case ICE_DEV_ID_E810C_BACKPLANE: 25 case ICE_DEV_ID_E810C_QSFP: 26 case ICE_DEV_ID_E810C_SFP: 27 case ICE_DEV_ID_E810_XXV_SFP: 28 hw->mac_type = ICE_MAC_E810; 29 break; 30 case ICE_DEV_ID_E823C_10G_BASE_T: 31 case ICE_DEV_ID_E823C_BACKPLANE: 32 case ICE_DEV_ID_E823C_QSFP: 33 case ICE_DEV_ID_E823C_SFP: 34 case ICE_DEV_ID_E823C_SGMII: 35 case ICE_DEV_ID_E822C_10G_BASE_T: 36 case ICE_DEV_ID_E822C_BACKPLANE: 37 case ICE_DEV_ID_E822C_QSFP: 38 case ICE_DEV_ID_E822C_SFP: 39 case ICE_DEV_ID_E822C_SGMII: 40 case ICE_DEV_ID_E822L_10G_BASE_T: 41 case ICE_DEV_ID_E822L_BACKPLANE: 42 case ICE_DEV_ID_E822L_SFP: 43 case ICE_DEV_ID_E822L_SGMII: 44 case ICE_DEV_ID_E823L_10G_BASE_T: 45 case ICE_DEV_ID_E823L_1GBE: 46 case ICE_DEV_ID_E823L_BACKPLANE: 47 case ICE_DEV_ID_E823L_QSFP: 48 case ICE_DEV_ID_E823L_SFP: 49 hw->mac_type = ICE_MAC_GENERIC; 50 break; 51 default: 52 hw->mac_type = ICE_MAC_UNKNOWN; 53 break; 54 } 55 56 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 57 return 0; 58 } 59 60 /** 61 * ice_clear_pf_cfg - Clear PF configuration 62 * @hw: pointer to the hardware structure 63 * 64 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 65 * configuration, flow director filters, etc.). 66 */ 67 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 68 { 69 struct ice_aq_desc desc; 70 71 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 72 73 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 74 } 75 76 /** 77 * ice_aq_manage_mac_read - manage MAC address read command 78 * @hw: pointer to the HW struct 79 * @buf: a virtual buffer to hold the manage MAC read response 80 * @buf_size: Size of the virtual buffer 81 * @cd: pointer to command details structure or NULL 82 * 83 * This function is used to return per PF station MAC address (0x0107). 84 * NOTE: Upon successful completion of this command, MAC address information 85 * is returned in user specified buffer. Please interpret user specified 86 * buffer as "manage_mac_read" response. 87 * Response such as various MAC addresses are stored in HW struct (port.mac) 88 * ice_discover_dev_caps is expected to be called before this function is 89 * called. 90 */ 91 static enum ice_status 92 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 93 struct ice_sq_cd *cd) 94 { 95 struct ice_aqc_manage_mac_read_resp *resp; 96 struct ice_aqc_manage_mac_read *cmd; 97 struct ice_aq_desc desc; 98 enum ice_status status; 99 u16 flags; 100 u8 i; 101 102 cmd = &desc.params.mac_read; 103 104 if (buf_size < sizeof(*resp)) 105 return ICE_ERR_BUF_TOO_SHORT; 106 107 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 108 109 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 110 if (status) 111 return status; 112 113 resp = (struct ice_aqc_manage_mac_read_resp *)buf; 114 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 115 116 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 117 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 118 return ICE_ERR_CFG; 119 } 120 121 /* A single port can report up to two (LAN and WoL) addresses */ 122 for (i = 0; i < cmd->num_addr; i++) 123 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 124 ether_addr_copy(hw->port_info->mac.lan_addr, 125 resp[i].mac_addr); 126 ether_addr_copy(hw->port_info->mac.perm_addr, 127 resp[i].mac_addr); 128 break; 129 } 130 131 return 0; 132 } 133 134 /** 135 * ice_aq_get_phy_caps - returns PHY capabilities 136 * @pi: port information structure 137 * @qual_mods: report qualified modules 138 * @report_mode: report mode capabilities 139 * @pcaps: structure for PHY capabilities to be filled 140 * @cd: pointer to command details structure or NULL 141 * 142 * Returns the various PHY capabilities supported on the Port (0x0600) 143 */ 144 enum ice_status 145 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 146 struct ice_aqc_get_phy_caps_data *pcaps, 147 struct ice_sq_cd *cd) 148 { 149 struct ice_aqc_get_phy_caps *cmd; 150 u16 pcaps_size = sizeof(*pcaps); 151 struct ice_aq_desc desc; 152 enum ice_status status; 153 struct ice_hw *hw; 154 155 cmd = &desc.params.get_phy; 156 157 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 158 return ICE_ERR_PARAM; 159 hw = pi->hw; 160 161 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 162 163 if (qual_mods) 164 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 165 166 cmd->param0 |= cpu_to_le16(report_mode); 167 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 168 169 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 170 report_mode); 171 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 172 (unsigned long long)le64_to_cpu(pcaps->phy_type_low)); 173 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 174 (unsigned long long)le64_to_cpu(pcaps->phy_type_high)); 175 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 176 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 177 pcaps->low_power_ctrl_an); 178 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 179 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 180 pcaps->eeer_value); 181 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 182 pcaps->link_fec_options); 183 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 184 pcaps->module_compliance_enforcement); 185 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 186 pcaps->extended_compliance_code); 187 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 188 pcaps->module_type[0]); 189 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 190 pcaps->module_type[1]); 191 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 192 pcaps->module_type[2]); 193 194 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) { 195 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 196 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 197 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 198 sizeof(pi->phy.link_info.module_type)); 199 } 200 201 return status; 202 } 203 204 /** 205 * ice_aq_get_link_topo_handle - get link topology node return status 206 * @pi: port information structure 207 * @node_type: requested node type 208 * @cd: pointer to command details structure or NULL 209 * 210 * Get link topology node return status for specified node type (0x06E0) 211 * 212 * Node type cage can be used to determine if cage is present. If AQC 213 * returns error (ENOENT), then no cage present. If no cage present, then 214 * connection type is backplane or BASE-T. 215 */ 216 static enum ice_status 217 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 218 struct ice_sq_cd *cd) 219 { 220 struct ice_aqc_get_link_topo *cmd; 221 struct ice_aq_desc desc; 222 223 cmd = &desc.params.get_link_topo; 224 225 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 226 227 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 228 ICE_AQC_LINK_TOPO_NODE_CTX_S); 229 230 /* set node type */ 231 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 232 233 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 234 } 235 236 /** 237 * ice_is_media_cage_present 238 * @pi: port information structure 239 * 240 * Returns true if media cage is present, else false. If no cage, then 241 * media type is backplane or BASE-T. 242 */ 243 static bool ice_is_media_cage_present(struct ice_port_info *pi) 244 { 245 /* Node type cage can be used to determine if cage is present. If AQC 246 * returns error (ENOENT), then no cage present. If no cage present then 247 * connection type is backplane or BASE-T. 248 */ 249 return !ice_aq_get_link_topo_handle(pi, 250 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 251 NULL); 252 } 253 254 /** 255 * ice_get_media_type - Gets media type 256 * @pi: port information structure 257 */ 258 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 259 { 260 struct ice_link_status *hw_link_info; 261 262 if (!pi) 263 return ICE_MEDIA_UNKNOWN; 264 265 hw_link_info = &pi->phy.link_info; 266 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 267 /* If more than one media type is selected, report unknown */ 268 return ICE_MEDIA_UNKNOWN; 269 270 if (hw_link_info->phy_type_low) { 271 /* 1G SGMII is a special case where some DA cable PHYs 272 * may show this as an option when it really shouldn't 273 * be since SGMII is meant to be between a MAC and a PHY 274 * in a backplane. Try to detect this case and handle it 275 */ 276 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 277 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 278 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 279 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 280 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 281 return ICE_MEDIA_DA; 282 283 switch (hw_link_info->phy_type_low) { 284 case ICE_PHY_TYPE_LOW_1000BASE_SX: 285 case ICE_PHY_TYPE_LOW_1000BASE_LX: 286 case ICE_PHY_TYPE_LOW_10GBASE_SR: 287 case ICE_PHY_TYPE_LOW_10GBASE_LR: 288 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 289 case ICE_PHY_TYPE_LOW_25GBASE_SR: 290 case ICE_PHY_TYPE_LOW_25GBASE_LR: 291 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 292 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 293 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 294 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 295 case ICE_PHY_TYPE_LOW_50GBASE_SR: 296 case ICE_PHY_TYPE_LOW_50GBASE_FR: 297 case ICE_PHY_TYPE_LOW_50GBASE_LR: 298 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 299 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 300 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 301 case ICE_PHY_TYPE_LOW_100GBASE_DR: 302 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 303 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 304 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 305 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 306 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 307 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 308 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 309 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 310 return ICE_MEDIA_FIBER; 311 case ICE_PHY_TYPE_LOW_100BASE_TX: 312 case ICE_PHY_TYPE_LOW_1000BASE_T: 313 case ICE_PHY_TYPE_LOW_2500BASE_T: 314 case ICE_PHY_TYPE_LOW_5GBASE_T: 315 case ICE_PHY_TYPE_LOW_10GBASE_T: 316 case ICE_PHY_TYPE_LOW_25GBASE_T: 317 return ICE_MEDIA_BASET; 318 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 319 case ICE_PHY_TYPE_LOW_25GBASE_CR: 320 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 321 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 322 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 323 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 324 case ICE_PHY_TYPE_LOW_50GBASE_CP: 325 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 326 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 327 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 328 return ICE_MEDIA_DA; 329 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 330 case ICE_PHY_TYPE_LOW_40G_XLAUI: 331 case ICE_PHY_TYPE_LOW_50G_LAUI2: 332 case ICE_PHY_TYPE_LOW_50G_AUI2: 333 case ICE_PHY_TYPE_LOW_50G_AUI1: 334 case ICE_PHY_TYPE_LOW_100G_AUI4: 335 case ICE_PHY_TYPE_LOW_100G_CAUI4: 336 if (ice_is_media_cage_present(pi)) 337 return ICE_MEDIA_DA; 338 fallthrough; 339 case ICE_PHY_TYPE_LOW_1000BASE_KX: 340 case ICE_PHY_TYPE_LOW_2500BASE_KX: 341 case ICE_PHY_TYPE_LOW_2500BASE_X: 342 case ICE_PHY_TYPE_LOW_5GBASE_KR: 343 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 344 case ICE_PHY_TYPE_LOW_25GBASE_KR: 345 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 346 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 347 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 348 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 349 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 350 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 351 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 352 return ICE_MEDIA_BACKPLANE; 353 } 354 } else { 355 switch (hw_link_info->phy_type_high) { 356 case ICE_PHY_TYPE_HIGH_100G_AUI2: 357 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 358 if (ice_is_media_cage_present(pi)) 359 return ICE_MEDIA_DA; 360 fallthrough; 361 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 362 return ICE_MEDIA_BACKPLANE; 363 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 364 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 365 return ICE_MEDIA_FIBER; 366 } 367 } 368 return ICE_MEDIA_UNKNOWN; 369 } 370 371 /** 372 * ice_aq_get_link_info 373 * @pi: port information structure 374 * @ena_lse: enable/disable LinkStatusEvent reporting 375 * @link: pointer to link status structure - optional 376 * @cd: pointer to command details structure or NULL 377 * 378 * Get Link Status (0x607). Returns the link status of the adapter. 379 */ 380 enum ice_status 381 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 382 struct ice_link_status *link, struct ice_sq_cd *cd) 383 { 384 struct ice_aqc_get_link_status_data link_data = { 0 }; 385 struct ice_aqc_get_link_status *resp; 386 struct ice_link_status *li_old, *li; 387 enum ice_media_type *hw_media_type; 388 struct ice_fc_info *hw_fc_info; 389 bool tx_pause, rx_pause; 390 struct ice_aq_desc desc; 391 enum ice_status status; 392 struct ice_hw *hw; 393 u16 cmd_flags; 394 395 if (!pi) 396 return ICE_ERR_PARAM; 397 hw = pi->hw; 398 li_old = &pi->phy.link_info_old; 399 hw_media_type = &pi->phy.media_type; 400 li = &pi->phy.link_info; 401 hw_fc_info = &pi->fc; 402 403 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 404 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 405 resp = &desc.params.get_link_status; 406 resp->cmd_flags = cpu_to_le16(cmd_flags); 407 resp->lport_num = pi->lport; 408 409 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 410 411 if (status) 412 return status; 413 414 /* save off old link status information */ 415 *li_old = *li; 416 417 /* update current link status information */ 418 li->link_speed = le16_to_cpu(link_data.link_speed); 419 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 420 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 421 *hw_media_type = ice_get_media_type(pi); 422 li->link_info = link_data.link_info; 423 li->an_info = link_data.an_info; 424 li->ext_info = link_data.ext_info; 425 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 426 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 427 li->topo_media_conflict = link_data.topo_media_conflict; 428 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 429 ICE_AQ_CFG_PACING_TYPE_M); 430 431 /* update fc info */ 432 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 433 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 434 if (tx_pause && rx_pause) 435 hw_fc_info->current_mode = ICE_FC_FULL; 436 else if (tx_pause) 437 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 438 else if (rx_pause) 439 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 440 else 441 hw_fc_info->current_mode = ICE_FC_NONE; 442 443 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 444 445 ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 446 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 447 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 448 (unsigned long long)li->phy_type_low); 449 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 450 (unsigned long long)li->phy_type_high); 451 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 452 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 453 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 454 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 455 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 456 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 457 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 458 li->max_frame_size); 459 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 460 461 /* save link status information */ 462 if (link) 463 *link = *li; 464 465 /* flag cleared so calling functions don't call AQ again */ 466 pi->phy.get_link_info = false; 467 468 return 0; 469 } 470 471 /** 472 * ice_fill_tx_timer_and_fc_thresh 473 * @hw: pointer to the HW struct 474 * @cmd: pointer to MAC cfg structure 475 * 476 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 477 * descriptor 478 */ 479 static void 480 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 481 struct ice_aqc_set_mac_cfg *cmd) 482 { 483 u16 fc_thres_val, tx_timer_val; 484 u32 val; 485 486 /* We read back the transmit timer and FC threshold value of 487 * LFC. Thus, we will use index = 488 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 489 * 490 * Also, because we are operating on transmit timer and FC 491 * threshold of LFC, we don't turn on any bit in tx_tmr_priority 492 */ 493 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 494 495 /* Retrieve the transmit timer */ 496 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 497 tx_timer_val = val & 498 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 499 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val); 500 501 /* Retrieve the FC threshold */ 502 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 503 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 504 505 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val); 506 } 507 508 /** 509 * ice_aq_set_mac_cfg 510 * @hw: pointer to the HW struct 511 * @max_frame_size: Maximum Frame Size to be supported 512 * @cd: pointer to command details structure or NULL 513 * 514 * Set MAC configuration (0x0603) 515 */ 516 enum ice_status 517 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 518 { 519 struct ice_aqc_set_mac_cfg *cmd; 520 struct ice_aq_desc desc; 521 522 cmd = &desc.params.set_mac_cfg; 523 524 if (max_frame_size == 0) 525 return ICE_ERR_PARAM; 526 527 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 528 529 cmd->max_frame_size = cpu_to_le16(max_frame_size); 530 531 ice_fill_tx_timer_and_fc_thresh(hw, cmd); 532 533 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 534 } 535 536 /** 537 * ice_init_fltr_mgmt_struct - initializes filter management list and locks 538 * @hw: pointer to the HW struct 539 */ 540 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 541 { 542 struct ice_switch_info *sw; 543 enum ice_status status; 544 545 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 546 sizeof(*hw->switch_info), GFP_KERNEL); 547 sw = hw->switch_info; 548 549 if (!sw) 550 return ICE_ERR_NO_MEMORY; 551 552 INIT_LIST_HEAD(&sw->vsi_list_map_head); 553 554 status = ice_init_def_sw_recp(hw); 555 if (status) { 556 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 557 return status; 558 } 559 return 0; 560 } 561 562 /** 563 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 564 * @hw: pointer to the HW struct 565 */ 566 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 567 { 568 struct ice_switch_info *sw = hw->switch_info; 569 struct ice_vsi_list_map_info *v_pos_map; 570 struct ice_vsi_list_map_info *v_tmp_map; 571 struct ice_sw_recipe *recps; 572 u8 i; 573 574 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 575 list_entry) { 576 list_del(&v_pos_map->list_entry); 577 devm_kfree(ice_hw_to_dev(hw), v_pos_map); 578 } 579 recps = hw->switch_info->recp_list; 580 for (i = 0; i < ICE_SW_LKUP_LAST; i++) { 581 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 582 583 recps[i].root_rid = i; 584 mutex_destroy(&recps[i].filt_rule_lock); 585 list_for_each_entry_safe(lst_itr, tmp_entry, 586 &recps[i].filt_rules, list_entry) { 587 list_del(&lst_itr->list_entry); 588 devm_kfree(ice_hw_to_dev(hw), lst_itr); 589 } 590 } 591 ice_rm_all_sw_replay_rule_info(hw); 592 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 593 devm_kfree(ice_hw_to_dev(hw), sw); 594 } 595 596 /** 597 * ice_get_fw_log_cfg - get FW logging configuration 598 * @hw: pointer to the HW struct 599 */ 600 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw) 601 { 602 struct ice_aq_desc desc; 603 enum ice_status status; 604 __le16 *config; 605 u16 size; 606 607 size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX; 608 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL); 609 if (!config) 610 return ICE_ERR_NO_MEMORY; 611 612 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 613 614 status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 615 if (!status) { 616 u16 i; 617 618 /* Save FW logging information into the HW structure */ 619 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 620 u16 v, m, flgs; 621 622 v = le16_to_cpu(config[i]); 623 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 624 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 625 626 if (m < ICE_AQC_FW_LOG_ID_MAX) 627 hw->fw_log.evnts[m].cur = flgs; 628 } 629 } 630 631 devm_kfree(ice_hw_to_dev(hw), config); 632 633 return status; 634 } 635 636 /** 637 * ice_cfg_fw_log - configure FW logging 638 * @hw: pointer to the HW struct 639 * @enable: enable certain FW logging events if true, disable all if false 640 * 641 * This function enables/disables the FW logging via Rx CQ events and a UART 642 * port based on predetermined configurations. FW logging via the Rx CQ can be 643 * enabled/disabled for individual PF's. However, FW logging via the UART can 644 * only be enabled/disabled for all PFs on the same device. 645 * 646 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 647 * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 648 * before initializing the device. 649 * 650 * When re/configuring FW logging, callers need to update the "cfg" elements of 651 * the hw->fw_log.evnts array with the desired logging event configurations for 652 * modules of interest. When disabling FW logging completely, the callers can 653 * just pass false in the "enable" parameter. On completion, the function will 654 * update the "cur" element of the hw->fw_log.evnts array with the resulting 655 * logging event configurations of the modules that are being re/configured. FW 656 * logging modules that are not part of a reconfiguration operation retain their 657 * previous states. 658 * 659 * Before resetting the device, it is recommended that the driver disables FW 660 * logging before shutting down the control queue. When disabling FW logging 661 * ("enable" = false), the latest configurations of FW logging events stored in 662 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 663 * a device reset. 664 * 665 * When enabling FW logging to emit log messages via the Rx CQ during the 666 * device's initialization phase, a mechanism alternative to interrupt handlers 667 * needs to be used to extract FW log messages from the Rx CQ periodically and 668 * to prevent the Rx CQ from being full and stalling other types of control 669 * messages from FW to SW. Interrupts are typically disabled during the device's 670 * initialization phase. 671 */ 672 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable) 673 { 674 struct ice_aqc_fw_logging *cmd; 675 enum ice_status status = 0; 676 u16 i, chgs = 0, len = 0; 677 struct ice_aq_desc desc; 678 __le16 *data = NULL; 679 u8 actv_evnts = 0; 680 void *buf = NULL; 681 682 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 683 return 0; 684 685 /* Disable FW logging only when the control queue is still responsive */ 686 if (!enable && 687 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 688 return 0; 689 690 /* Get current FW log settings */ 691 status = ice_get_fw_log_cfg(hw); 692 if (status) 693 return status; 694 695 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 696 cmd = &desc.params.fw_logging; 697 698 /* Indicate which controls are valid */ 699 if (hw->fw_log.cq_en) 700 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 701 702 if (hw->fw_log.uart_en) 703 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 704 705 if (enable) { 706 /* Fill in an array of entries with FW logging modules and 707 * logging events being reconfigured. 708 */ 709 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 710 u16 val; 711 712 /* Keep track of enabled event types */ 713 actv_evnts |= hw->fw_log.evnts[i].cfg; 714 715 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 716 continue; 717 718 if (!data) { 719 data = devm_kcalloc(ice_hw_to_dev(hw), 720 sizeof(*data), 721 ICE_AQC_FW_LOG_ID_MAX, 722 GFP_KERNEL); 723 if (!data) 724 return ICE_ERR_NO_MEMORY; 725 } 726 727 val = i << ICE_AQC_FW_LOG_ID_S; 728 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 729 data[chgs++] = cpu_to_le16(val); 730 } 731 732 /* Only enable FW logging if at least one module is specified. 733 * If FW logging is currently enabled but all modules are not 734 * enabled to emit log messages, disable FW logging altogether. 735 */ 736 if (actv_evnts) { 737 /* Leave if there is effectively no change */ 738 if (!chgs) 739 goto out; 740 741 if (hw->fw_log.cq_en) 742 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 743 744 if (hw->fw_log.uart_en) 745 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 746 747 buf = data; 748 len = sizeof(*data) * chgs; 749 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 750 } 751 } 752 753 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 754 if (!status) { 755 /* Update the current configuration to reflect events enabled. 756 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 757 * logging mode is enabled for the device. They do not reflect 758 * actual modules being enabled to emit log messages. So, their 759 * values remain unchanged even when all modules are disabled. 760 */ 761 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 762 763 hw->fw_log.actv_evnts = actv_evnts; 764 for (i = 0; i < cnt; i++) { 765 u16 v, m; 766 767 if (!enable) { 768 /* When disabling all FW logging events as part 769 * of device's de-initialization, the original 770 * configurations are retained, and can be used 771 * to reconfigure FW logging later if the device 772 * is re-initialized. 773 */ 774 hw->fw_log.evnts[i].cur = 0; 775 continue; 776 } 777 778 v = le16_to_cpu(data[i]); 779 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 780 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 781 } 782 } 783 784 out: 785 if (data) 786 devm_kfree(ice_hw_to_dev(hw), data); 787 788 return status; 789 } 790 791 /** 792 * ice_output_fw_log 793 * @hw: pointer to the HW struct 794 * @desc: pointer to the AQ message descriptor 795 * @buf: pointer to the buffer accompanying the AQ message 796 * 797 * Formats a FW Log message and outputs it via the standard driver logs. 798 */ 799 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 800 { 801 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 802 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 803 le16_to_cpu(desc->datalen)); 804 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 805 } 806 807 /** 808 * ice_get_itr_intrl_gran 809 * @hw: pointer to the HW struct 810 * 811 * Determines the ITR/INTRL granularities based on the maximum aggregate 812 * bandwidth according to the device's configuration during power-on. 813 */ 814 static void ice_get_itr_intrl_gran(struct ice_hw *hw) 815 { 816 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 817 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 818 GL_PWR_MODE_CTL_CAR_MAX_BW_S; 819 820 switch (max_agg_bw) { 821 case ICE_MAX_AGG_BW_200G: 822 case ICE_MAX_AGG_BW_100G: 823 case ICE_MAX_AGG_BW_50G: 824 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 825 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 826 break; 827 case ICE_MAX_AGG_BW_25G: 828 hw->itr_gran = ICE_ITR_GRAN_MAX_25; 829 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 830 break; 831 } 832 } 833 834 /** 835 * ice_init_hw - main hardware initialization routine 836 * @hw: pointer to the hardware structure 837 */ 838 enum ice_status ice_init_hw(struct ice_hw *hw) 839 { 840 struct ice_aqc_get_phy_caps_data *pcaps; 841 enum ice_status status; 842 u16 mac_buf_len; 843 void *mac_buf; 844 845 /* Set MAC type based on DeviceID */ 846 status = ice_set_mac_type(hw); 847 if (status) 848 return status; 849 850 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 851 PF_FUNC_RID_FUNC_NUM_M) >> 852 PF_FUNC_RID_FUNC_NUM_S; 853 854 status = ice_reset(hw, ICE_RESET_PFR); 855 if (status) 856 return status; 857 858 ice_get_itr_intrl_gran(hw); 859 860 status = ice_create_all_ctrlq(hw); 861 if (status) 862 goto err_unroll_cqinit; 863 864 /* Enable FW logging. Not fatal if this fails. */ 865 status = ice_cfg_fw_log(hw, true); 866 if (status) 867 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 868 869 status = ice_clear_pf_cfg(hw); 870 if (status) 871 goto err_unroll_cqinit; 872 873 /* Set bit to enable Flow Director filters */ 874 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 875 INIT_LIST_HEAD(&hw->fdir_list_head); 876 877 ice_clear_pxe_mode(hw); 878 879 status = ice_init_nvm(hw); 880 if (status) 881 goto err_unroll_cqinit; 882 883 status = ice_get_caps(hw); 884 if (status) 885 goto err_unroll_cqinit; 886 887 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 888 sizeof(*hw->port_info), GFP_KERNEL); 889 if (!hw->port_info) { 890 status = ICE_ERR_NO_MEMORY; 891 goto err_unroll_cqinit; 892 } 893 894 /* set the back pointer to HW */ 895 hw->port_info->hw = hw; 896 897 /* Initialize port_info struct with switch configuration data */ 898 status = ice_get_initial_sw_cfg(hw); 899 if (status) 900 goto err_unroll_alloc; 901 902 hw->evb_veb = true; 903 904 /* Query the allocated resources for Tx scheduler */ 905 status = ice_sched_query_res_alloc(hw); 906 if (status) { 907 ice_debug(hw, ICE_DBG_SCHED, 908 "Failed to get scheduler allocated resources\n"); 909 goto err_unroll_alloc; 910 } 911 912 /* Initialize port_info struct with scheduler data */ 913 status = ice_sched_init_port(hw->port_info); 914 if (status) 915 goto err_unroll_sched; 916 917 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 918 if (!pcaps) { 919 status = ICE_ERR_NO_MEMORY; 920 goto err_unroll_sched; 921 } 922 923 /* Initialize port_info struct with PHY capabilities */ 924 status = ice_aq_get_phy_caps(hw->port_info, false, 925 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); 926 devm_kfree(ice_hw_to_dev(hw), pcaps); 927 if (status) 928 goto err_unroll_sched; 929 930 /* Initialize port_info struct with link information */ 931 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 932 if (status) 933 goto err_unroll_sched; 934 935 /* need a valid SW entry point to build a Tx tree */ 936 if (!hw->sw_entry_point_layer) { 937 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 938 status = ICE_ERR_CFG; 939 goto err_unroll_sched; 940 } 941 INIT_LIST_HEAD(&hw->agg_list); 942 /* Initialize max burst size */ 943 if (!hw->max_burst_size) 944 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 945 946 status = ice_init_fltr_mgmt_struct(hw); 947 if (status) 948 goto err_unroll_sched; 949 950 /* Get MAC information */ 951 /* A single port can report up to two (LAN and WoL) addresses */ 952 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 953 sizeof(struct ice_aqc_manage_mac_read_resp), 954 GFP_KERNEL); 955 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 956 957 if (!mac_buf) { 958 status = ICE_ERR_NO_MEMORY; 959 goto err_unroll_fltr_mgmt_struct; 960 } 961 962 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 963 devm_kfree(ice_hw_to_dev(hw), mac_buf); 964 965 if (status) 966 goto err_unroll_fltr_mgmt_struct; 967 /* enable jumbo frame support at MAC level */ 968 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 969 if (status) 970 goto err_unroll_fltr_mgmt_struct; 971 /* Obtain counter base index which would be used by flow director */ 972 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 973 if (status) 974 goto err_unroll_fltr_mgmt_struct; 975 status = ice_init_hw_tbls(hw); 976 if (status) 977 goto err_unroll_fltr_mgmt_struct; 978 mutex_init(&hw->tnl_lock); 979 return 0; 980 981 err_unroll_fltr_mgmt_struct: 982 ice_cleanup_fltr_mgmt_struct(hw); 983 err_unroll_sched: 984 ice_sched_cleanup_all(hw); 985 err_unroll_alloc: 986 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 987 err_unroll_cqinit: 988 ice_destroy_all_ctrlq(hw); 989 return status; 990 } 991 992 /** 993 * ice_deinit_hw - unroll initialization operations done by ice_init_hw 994 * @hw: pointer to the hardware structure 995 * 996 * This should be called only during nominal operation, not as a result of 997 * ice_init_hw() failing since ice_init_hw() will take care of unrolling 998 * applicable initializations if it fails for any reason. 999 */ 1000 void ice_deinit_hw(struct ice_hw *hw) 1001 { 1002 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 1003 ice_cleanup_fltr_mgmt_struct(hw); 1004 1005 ice_sched_cleanup_all(hw); 1006 ice_sched_clear_agg(hw); 1007 ice_free_seg(hw); 1008 ice_free_hw_tbls(hw); 1009 mutex_destroy(&hw->tnl_lock); 1010 1011 if (hw->port_info) { 1012 devm_kfree(ice_hw_to_dev(hw), hw->port_info); 1013 hw->port_info = NULL; 1014 } 1015 1016 /* Attempt to disable FW logging before shutting down control queues */ 1017 ice_cfg_fw_log(hw, false); 1018 ice_destroy_all_ctrlq(hw); 1019 1020 /* Clear VSI contexts if not already cleared */ 1021 ice_clear_all_vsi_ctx(hw); 1022 } 1023 1024 /** 1025 * ice_check_reset - Check to see if a global reset is complete 1026 * @hw: pointer to the hardware structure 1027 */ 1028 enum ice_status ice_check_reset(struct ice_hw *hw) 1029 { 1030 u32 cnt, reg = 0, grst_timeout, uld_mask; 1031 1032 /* Poll for Device Active state in case a recent CORER, GLOBR, 1033 * or EMPR has occurred. The grst delay value is in 100ms units. 1034 * Add 1sec for outstanding AQ commands that can take a long time. 1035 */ 1036 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1037 GLGEN_RSTCTL_GRSTDEL_S) + 10; 1038 1039 for (cnt = 0; cnt < grst_timeout; cnt++) { 1040 mdelay(100); 1041 reg = rd32(hw, GLGEN_RSTAT); 1042 if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1043 break; 1044 } 1045 1046 if (cnt == grst_timeout) { 1047 ice_debug(hw, ICE_DBG_INIT, 1048 "Global reset polling failed to complete.\n"); 1049 return ICE_ERR_RESET_FAILED; 1050 } 1051 1052 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1053 GLNVM_ULD_PCIER_DONE_1_M |\ 1054 GLNVM_ULD_CORER_DONE_M |\ 1055 GLNVM_ULD_GLOBR_DONE_M |\ 1056 GLNVM_ULD_POR_DONE_M |\ 1057 GLNVM_ULD_POR_DONE_1_M |\ 1058 GLNVM_ULD_PCIER_DONE_2_M) 1059 1060 uld_mask = ICE_RESET_DONE_MASK; 1061 1062 /* Device is Active; check Global Reset processes are done */ 1063 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1064 reg = rd32(hw, GLNVM_ULD) & uld_mask; 1065 if (reg == uld_mask) { 1066 ice_debug(hw, ICE_DBG_INIT, 1067 "Global reset processes done. %d\n", cnt); 1068 break; 1069 } 1070 mdelay(10); 1071 } 1072 1073 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1074 ice_debug(hw, ICE_DBG_INIT, 1075 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1076 reg); 1077 return ICE_ERR_RESET_FAILED; 1078 } 1079 1080 return 0; 1081 } 1082 1083 /** 1084 * ice_pf_reset - Reset the PF 1085 * @hw: pointer to the hardware structure 1086 * 1087 * If a global reset has been triggered, this function checks 1088 * for its completion and then issues the PF reset 1089 */ 1090 static enum ice_status ice_pf_reset(struct ice_hw *hw) 1091 { 1092 u32 cnt, reg; 1093 1094 /* If at function entry a global reset was already in progress, i.e. 1095 * state is not 'device active' or any of the reset done bits are not 1096 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1097 * global reset is done. 1098 */ 1099 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1100 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1101 /* poll on global reset currently in progress until done */ 1102 if (ice_check_reset(hw)) 1103 return ICE_ERR_RESET_FAILED; 1104 1105 return 0; 1106 } 1107 1108 /* Reset the PF */ 1109 reg = rd32(hw, PFGEN_CTRL); 1110 1111 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1112 1113 /* Wait for the PFR to complete. The wait time is the global config lock 1114 * timeout plus the PFR timeout which will account for a possible reset 1115 * that is occurring during a download package operation. 1116 */ 1117 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1118 ICE_PF_RESET_WAIT_COUNT; cnt++) { 1119 reg = rd32(hw, PFGEN_CTRL); 1120 if (!(reg & PFGEN_CTRL_PFSWR_M)) 1121 break; 1122 1123 mdelay(1); 1124 } 1125 1126 if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1127 ice_debug(hw, ICE_DBG_INIT, 1128 "PF reset polling failed to complete.\n"); 1129 return ICE_ERR_RESET_FAILED; 1130 } 1131 1132 return 0; 1133 } 1134 1135 /** 1136 * ice_reset - Perform different types of reset 1137 * @hw: pointer to the hardware structure 1138 * @req: reset request 1139 * 1140 * This function triggers a reset as specified by the req parameter. 1141 * 1142 * Note: 1143 * If anything other than a PF reset is triggered, PXE mode is restored. 1144 * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1145 * interface has been restored in the rebuild flow. 1146 */ 1147 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1148 { 1149 u32 val = 0; 1150 1151 switch (req) { 1152 case ICE_RESET_PFR: 1153 return ice_pf_reset(hw); 1154 case ICE_RESET_CORER: 1155 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1156 val = GLGEN_RTRIG_CORER_M; 1157 break; 1158 case ICE_RESET_GLOBR: 1159 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1160 val = GLGEN_RTRIG_GLOBR_M; 1161 break; 1162 default: 1163 return ICE_ERR_PARAM; 1164 } 1165 1166 val |= rd32(hw, GLGEN_RTRIG); 1167 wr32(hw, GLGEN_RTRIG, val); 1168 ice_flush(hw); 1169 1170 /* wait for the FW to be ready */ 1171 return ice_check_reset(hw); 1172 } 1173 1174 /** 1175 * ice_copy_rxq_ctx_to_hw 1176 * @hw: pointer to the hardware structure 1177 * @ice_rxq_ctx: pointer to the rxq context 1178 * @rxq_index: the index of the Rx queue 1179 * 1180 * Copies rxq context from dense structure to HW register space 1181 */ 1182 static enum ice_status 1183 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1184 { 1185 u8 i; 1186 1187 if (!ice_rxq_ctx) 1188 return ICE_ERR_BAD_PTR; 1189 1190 if (rxq_index > QRX_CTRL_MAX_INDEX) 1191 return ICE_ERR_PARAM; 1192 1193 /* Copy each dword separately to HW */ 1194 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1195 wr32(hw, QRX_CONTEXT(i, rxq_index), 1196 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1197 1198 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1199 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1200 } 1201 1202 return 0; 1203 } 1204 1205 /* LAN Rx Queue Context */ 1206 static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1207 /* Field Width LSB */ 1208 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1209 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1210 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1211 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1212 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1213 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1214 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1215 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1216 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1217 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1218 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1219 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1220 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1221 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1222 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1223 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1224 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1225 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1226 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1227 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1228 { 0 } 1229 }; 1230 1231 /** 1232 * ice_write_rxq_ctx 1233 * @hw: pointer to the hardware structure 1234 * @rlan_ctx: pointer to the rxq context 1235 * @rxq_index: the index of the Rx queue 1236 * 1237 * Converts rxq context from sparse to dense structure and then writes 1238 * it to HW register space and enables the hardware to prefetch descriptors 1239 * instead of only fetching them on demand 1240 */ 1241 enum ice_status 1242 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1243 u32 rxq_index) 1244 { 1245 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1246 1247 if (!rlan_ctx) 1248 return ICE_ERR_BAD_PTR; 1249 1250 rlan_ctx->prefena = 1; 1251 1252 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1253 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1254 } 1255 1256 /* LAN Tx Queue Context */ 1257 const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1258 /* Field Width LSB */ 1259 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1260 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1261 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1262 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1263 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1264 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1265 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1266 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1267 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1268 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1269 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1270 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1271 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1272 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1273 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1274 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1275 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1276 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1277 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1278 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1279 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1280 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1281 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1282 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1283 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1284 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1285 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1286 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1287 { 0 } 1288 }; 1289 1290 /* FW Admin Queue command wrappers */ 1291 1292 /* Software lock/mutex that is meant to be held while the Global Config Lock 1293 * in firmware is acquired by the software to prevent most (but not all) types 1294 * of AQ commands from being sent to FW 1295 */ 1296 DEFINE_MUTEX(ice_global_cfg_lock_sw); 1297 1298 /** 1299 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1300 * @hw: pointer to the HW struct 1301 * @desc: descriptor describing the command 1302 * @buf: buffer to use for indirect commands (NULL for direct commands) 1303 * @buf_size: size of buffer for indirect commands (0 for direct commands) 1304 * @cd: pointer to command details structure 1305 * 1306 * Helper function to send FW Admin Queue commands to the FW Admin Queue. 1307 */ 1308 enum ice_status 1309 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 1310 u16 buf_size, struct ice_sq_cd *cd) 1311 { 1312 struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1313 bool lock_acquired = false; 1314 enum ice_status status; 1315 1316 /* When a package download is in process (i.e. when the firmware's 1317 * Global Configuration Lock resource is held), only the Download 1318 * Package, Get Version, Get Package Info List and Release Resource 1319 * (with resource ID set to Global Config Lock) AdminQ commands are 1320 * allowed; all others must block until the package download completes 1321 * and the Global Config Lock is released. See also 1322 * ice_acquire_global_cfg_lock(). 1323 */ 1324 switch (le16_to_cpu(desc->opcode)) { 1325 case ice_aqc_opc_download_pkg: 1326 case ice_aqc_opc_get_pkg_info_list: 1327 case ice_aqc_opc_get_ver: 1328 break; 1329 case ice_aqc_opc_release_res: 1330 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1331 break; 1332 fallthrough; 1333 default: 1334 mutex_lock(&ice_global_cfg_lock_sw); 1335 lock_acquired = true; 1336 break; 1337 } 1338 1339 status = ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); 1340 if (lock_acquired) 1341 mutex_unlock(&ice_global_cfg_lock_sw); 1342 1343 return status; 1344 } 1345 1346 /** 1347 * ice_aq_get_fw_ver 1348 * @hw: pointer to the HW struct 1349 * @cd: pointer to command details structure or NULL 1350 * 1351 * Get the firmware version (0x0001) from the admin queue commands 1352 */ 1353 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 1354 { 1355 struct ice_aqc_get_ver *resp; 1356 struct ice_aq_desc desc; 1357 enum ice_status status; 1358 1359 resp = &desc.params.get_ver; 1360 1361 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 1362 1363 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1364 1365 if (!status) { 1366 hw->fw_branch = resp->fw_branch; 1367 hw->fw_maj_ver = resp->fw_major; 1368 hw->fw_min_ver = resp->fw_minor; 1369 hw->fw_patch = resp->fw_patch; 1370 hw->fw_build = le32_to_cpu(resp->fw_build); 1371 hw->api_branch = resp->api_branch; 1372 hw->api_maj_ver = resp->api_major; 1373 hw->api_min_ver = resp->api_minor; 1374 hw->api_patch = resp->api_patch; 1375 } 1376 1377 return status; 1378 } 1379 1380 /** 1381 * ice_aq_send_driver_ver 1382 * @hw: pointer to the HW struct 1383 * @dv: driver's major, minor version 1384 * @cd: pointer to command details structure or NULL 1385 * 1386 * Send the driver version (0x0002) to the firmware 1387 */ 1388 enum ice_status 1389 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1390 struct ice_sq_cd *cd) 1391 { 1392 struct ice_aqc_driver_ver *cmd; 1393 struct ice_aq_desc desc; 1394 u16 len; 1395 1396 cmd = &desc.params.driver_ver; 1397 1398 if (!dv) 1399 return ICE_ERR_PARAM; 1400 1401 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1402 1403 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1404 cmd->major_ver = dv->major_ver; 1405 cmd->minor_ver = dv->minor_ver; 1406 cmd->build_ver = dv->build_ver; 1407 cmd->subbuild_ver = dv->subbuild_ver; 1408 1409 len = 0; 1410 while (len < sizeof(dv->driver_string) && 1411 isascii(dv->driver_string[len]) && dv->driver_string[len]) 1412 len++; 1413 1414 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1415 } 1416 1417 /** 1418 * ice_aq_q_shutdown 1419 * @hw: pointer to the HW struct 1420 * @unloading: is the driver unloading itself 1421 * 1422 * Tell the Firmware that we're shutting down the AdminQ and whether 1423 * or not the driver is unloading as well (0x0003). 1424 */ 1425 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 1426 { 1427 struct ice_aqc_q_shutdown *cmd; 1428 struct ice_aq_desc desc; 1429 1430 cmd = &desc.params.q_shutdown; 1431 1432 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 1433 1434 if (unloading) 1435 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 1436 1437 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 1438 } 1439 1440 /** 1441 * ice_aq_req_res 1442 * @hw: pointer to the HW struct 1443 * @res: resource ID 1444 * @access: access type 1445 * @sdp_number: resource number 1446 * @timeout: the maximum time in ms that the driver may hold the resource 1447 * @cd: pointer to command details structure or NULL 1448 * 1449 * Requests common resource using the admin queue commands (0x0008). 1450 * When attempting to acquire the Global Config Lock, the driver can 1451 * learn of three states: 1452 * 1) ICE_SUCCESS - acquired lock, and can perform download package 1453 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1454 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1455 * successfully downloaded the package; the driver does 1456 * not have to download the package and can continue 1457 * loading 1458 * 1459 * Note that if the caller is in an acquire lock, perform action, release lock 1460 * phase of operation, it is possible that the FW may detect a timeout and issue 1461 * a CORER. In this case, the driver will receive a CORER interrupt and will 1462 * have to determine its cause. The calling thread that is handling this flow 1463 * will likely get an error propagated back to it indicating the Download 1464 * Package, Update Package or the Release Resource AQ commands timed out. 1465 */ 1466 static enum ice_status 1467 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1468 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1469 struct ice_sq_cd *cd) 1470 { 1471 struct ice_aqc_req_res *cmd_resp; 1472 struct ice_aq_desc desc; 1473 enum ice_status status; 1474 1475 cmd_resp = &desc.params.res_owner; 1476 1477 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1478 1479 cmd_resp->res_id = cpu_to_le16(res); 1480 cmd_resp->access_type = cpu_to_le16(access); 1481 cmd_resp->res_number = cpu_to_le32(sdp_number); 1482 cmd_resp->timeout = cpu_to_le32(*timeout); 1483 *timeout = 0; 1484 1485 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1486 1487 /* The completion specifies the maximum time in ms that the driver 1488 * may hold the resource in the Timeout field. 1489 */ 1490 1491 /* Global config lock response utilizes an additional status field. 1492 * 1493 * If the Global config lock resource is held by some other driver, the 1494 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1495 * and the timeout field indicates the maximum time the current owner 1496 * of the resource has to free it. 1497 */ 1498 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1499 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1500 *timeout = le32_to_cpu(cmd_resp->timeout); 1501 return 0; 1502 } else if (le16_to_cpu(cmd_resp->status) == 1503 ICE_AQ_RES_GLBL_IN_PROG) { 1504 *timeout = le32_to_cpu(cmd_resp->timeout); 1505 return ICE_ERR_AQ_ERROR; 1506 } else if (le16_to_cpu(cmd_resp->status) == 1507 ICE_AQ_RES_GLBL_DONE) { 1508 return ICE_ERR_AQ_NO_WORK; 1509 } 1510 1511 /* invalid FW response, force a timeout immediately */ 1512 *timeout = 0; 1513 return ICE_ERR_AQ_ERROR; 1514 } 1515 1516 /* If the resource is held by some other driver, the command completes 1517 * with a busy return value and the timeout field indicates the maximum 1518 * time the current owner of the resource has to free it. 1519 */ 1520 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1521 *timeout = le32_to_cpu(cmd_resp->timeout); 1522 1523 return status; 1524 } 1525 1526 /** 1527 * ice_aq_release_res 1528 * @hw: pointer to the HW struct 1529 * @res: resource ID 1530 * @sdp_number: resource number 1531 * @cd: pointer to command details structure or NULL 1532 * 1533 * release common resource using the admin queue commands (0x0009) 1534 */ 1535 static enum ice_status 1536 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1537 struct ice_sq_cd *cd) 1538 { 1539 struct ice_aqc_req_res *cmd; 1540 struct ice_aq_desc desc; 1541 1542 cmd = &desc.params.res_owner; 1543 1544 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1545 1546 cmd->res_id = cpu_to_le16(res); 1547 cmd->res_number = cpu_to_le32(sdp_number); 1548 1549 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1550 } 1551 1552 /** 1553 * ice_acquire_res 1554 * @hw: pointer to the HW structure 1555 * @res: resource ID 1556 * @access: access type (read or write) 1557 * @timeout: timeout in milliseconds 1558 * 1559 * This function will attempt to acquire the ownership of a resource. 1560 */ 1561 enum ice_status 1562 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1563 enum ice_aq_res_access_type access, u32 timeout) 1564 { 1565 #define ICE_RES_POLLING_DELAY_MS 10 1566 u32 delay = ICE_RES_POLLING_DELAY_MS; 1567 u32 time_left = timeout; 1568 enum ice_status status; 1569 1570 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1571 1572 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1573 * previously acquired the resource and performed any necessary updates; 1574 * in this case the caller does not obtain the resource and has no 1575 * further work to do. 1576 */ 1577 if (status == ICE_ERR_AQ_NO_WORK) 1578 goto ice_acquire_res_exit; 1579 1580 if (status) 1581 ice_debug(hw, ICE_DBG_RES, 1582 "resource %d acquire type %d failed.\n", res, access); 1583 1584 /* If necessary, poll until the current lock owner timeouts */ 1585 timeout = time_left; 1586 while (status && timeout && time_left) { 1587 mdelay(delay); 1588 timeout = (timeout > delay) ? timeout - delay : 0; 1589 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1590 1591 if (status == ICE_ERR_AQ_NO_WORK) 1592 /* lock free, but no work to do */ 1593 break; 1594 1595 if (!status) 1596 /* lock acquired */ 1597 break; 1598 } 1599 if (status && status != ICE_ERR_AQ_NO_WORK) 1600 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1601 1602 ice_acquire_res_exit: 1603 if (status == ICE_ERR_AQ_NO_WORK) { 1604 if (access == ICE_RES_WRITE) 1605 ice_debug(hw, ICE_DBG_RES, 1606 "resource indicates no work to do.\n"); 1607 else 1608 ice_debug(hw, ICE_DBG_RES, 1609 "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1610 } 1611 return status; 1612 } 1613 1614 /** 1615 * ice_release_res 1616 * @hw: pointer to the HW structure 1617 * @res: resource ID 1618 * 1619 * This function will release a resource using the proper Admin Command. 1620 */ 1621 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1622 { 1623 enum ice_status status; 1624 u32 total_delay = 0; 1625 1626 status = ice_aq_release_res(hw, res, 0, NULL); 1627 1628 /* there are some rare cases when trying to release the resource 1629 * results in an admin queue timeout, so handle them correctly 1630 */ 1631 while ((status == ICE_ERR_AQ_TIMEOUT) && 1632 (total_delay < hw->adminq.sq_cmd_timeout)) { 1633 mdelay(1); 1634 status = ice_aq_release_res(hw, res, 0, NULL); 1635 total_delay++; 1636 } 1637 } 1638 1639 /** 1640 * ice_aq_alloc_free_res - command to allocate/free resources 1641 * @hw: pointer to the HW struct 1642 * @num_entries: number of resource entries in buffer 1643 * @buf: Indirect buffer to hold data parameters and response 1644 * @buf_size: size of buffer for indirect commands 1645 * @opc: pass in the command opcode 1646 * @cd: pointer to command details structure or NULL 1647 * 1648 * Helper function to allocate/free resources using the admin queue commands 1649 */ 1650 enum ice_status 1651 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 1652 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 1653 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 1654 { 1655 struct ice_aqc_alloc_free_res_cmd *cmd; 1656 struct ice_aq_desc desc; 1657 1658 cmd = &desc.params.sw_res_ctrl; 1659 1660 if (!buf) 1661 return ICE_ERR_PARAM; 1662 1663 if (buf_size < (num_entries * sizeof(buf->elem[0]))) 1664 return ICE_ERR_PARAM; 1665 1666 ice_fill_dflt_direct_cmd_desc(&desc, opc); 1667 1668 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1669 1670 cmd->num_entries = cpu_to_le16(num_entries); 1671 1672 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 1673 } 1674 1675 /** 1676 * ice_alloc_hw_res - allocate resource 1677 * @hw: pointer to the HW struct 1678 * @type: type of resource 1679 * @num: number of resources to allocate 1680 * @btm: allocate from bottom 1681 * @res: pointer to array that will receive the resources 1682 */ 1683 enum ice_status 1684 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 1685 { 1686 struct ice_aqc_alloc_free_res_elem *buf; 1687 enum ice_status status; 1688 u16 buf_len; 1689 1690 buf_len = struct_size(buf, elem, num); 1691 buf = kzalloc(buf_len, GFP_KERNEL); 1692 if (!buf) 1693 return ICE_ERR_NO_MEMORY; 1694 1695 /* Prepare buffer to allocate resource. */ 1696 buf->num_elems = cpu_to_le16(num); 1697 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 1698 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 1699 if (btm) 1700 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 1701 1702 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 1703 ice_aqc_opc_alloc_res, NULL); 1704 if (status) 1705 goto ice_alloc_res_exit; 1706 1707 memcpy(res, buf->elem, sizeof(*buf->elem) * num); 1708 1709 ice_alloc_res_exit: 1710 kfree(buf); 1711 return status; 1712 } 1713 1714 /** 1715 * ice_free_hw_res - free allocated HW resource 1716 * @hw: pointer to the HW struct 1717 * @type: type of resource to free 1718 * @num: number of resources 1719 * @res: pointer to array that contains the resources to free 1720 */ 1721 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1722 { 1723 struct ice_aqc_alloc_free_res_elem *buf; 1724 enum ice_status status; 1725 u16 buf_len; 1726 1727 buf_len = struct_size(buf, elem, num); 1728 buf = kzalloc(buf_len, GFP_KERNEL); 1729 if (!buf) 1730 return ICE_ERR_NO_MEMORY; 1731 1732 /* Prepare buffer to free resource. */ 1733 buf->num_elems = cpu_to_le16(num); 1734 buf->res_type = cpu_to_le16(type); 1735 memcpy(buf->elem, res, sizeof(*buf->elem) * num); 1736 1737 status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1738 ice_aqc_opc_free_res, NULL); 1739 if (status) 1740 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1741 1742 kfree(buf); 1743 return status; 1744 } 1745 1746 /** 1747 * ice_get_num_per_func - determine number of resources per PF 1748 * @hw: pointer to the HW structure 1749 * @max: value to be evenly split between each PF 1750 * 1751 * Determine the number of valid functions by going through the bitmap returned 1752 * from parsing capabilities and use this to calculate the number of resources 1753 * per PF based on the max value passed in. 1754 */ 1755 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1756 { 1757 u8 funcs; 1758 1759 #define ICE_CAPS_VALID_FUNCS_M 0xFF 1760 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 1761 ICE_CAPS_VALID_FUNCS_M); 1762 1763 if (!funcs) 1764 return 0; 1765 1766 return max / funcs; 1767 } 1768 1769 /** 1770 * ice_parse_common_caps - parse common device/function capabilities 1771 * @hw: pointer to the HW struct 1772 * @caps: pointer to common capabilities structure 1773 * @elem: the capability element to parse 1774 * @prefix: message prefix for tracing capabilities 1775 * 1776 * Given a capability element, extract relevant details into the common 1777 * capability structure. 1778 * 1779 * Returns: true if the capability matches one of the common capability ids, 1780 * false otherwise. 1781 */ 1782 static bool 1783 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1784 struct ice_aqc_list_caps_elem *elem, const char *prefix) 1785 { 1786 u32 logical_id = le32_to_cpu(elem->logical_id); 1787 u32 phys_id = le32_to_cpu(elem->phys_id); 1788 u32 number = le32_to_cpu(elem->number); 1789 u16 cap = le16_to_cpu(elem->cap); 1790 bool found = true; 1791 1792 switch (cap) { 1793 case ICE_AQC_CAPS_VALID_FUNCTIONS: 1794 caps->valid_functions = number; 1795 ice_debug(hw, ICE_DBG_INIT, 1796 "%s: valid_functions (bitmap) = %d\n", prefix, 1797 caps->valid_functions); 1798 break; 1799 case ICE_AQC_CAPS_SRIOV: 1800 caps->sr_iov_1_1 = (number == 1); 1801 ice_debug(hw, ICE_DBG_INIT, 1802 "%s: sr_iov_1_1 = %d\n", prefix, 1803 caps->sr_iov_1_1); 1804 break; 1805 case ICE_AQC_CAPS_DCB: 1806 caps->dcb = (number == 1); 1807 caps->active_tc_bitmap = logical_id; 1808 caps->maxtc = phys_id; 1809 ice_debug(hw, ICE_DBG_INIT, 1810 "%s: dcb = %d\n", prefix, caps->dcb); 1811 ice_debug(hw, ICE_DBG_INIT, 1812 "%s: active_tc_bitmap = %d\n", prefix, 1813 caps->active_tc_bitmap); 1814 ice_debug(hw, ICE_DBG_INIT, 1815 "%s: maxtc = %d\n", prefix, caps->maxtc); 1816 break; 1817 case ICE_AQC_CAPS_RSS: 1818 caps->rss_table_size = number; 1819 caps->rss_table_entry_width = logical_id; 1820 ice_debug(hw, ICE_DBG_INIT, 1821 "%s: rss_table_size = %d\n", prefix, 1822 caps->rss_table_size); 1823 ice_debug(hw, ICE_DBG_INIT, 1824 "%s: rss_table_entry_width = %d\n", prefix, 1825 caps->rss_table_entry_width); 1826 break; 1827 case ICE_AQC_CAPS_RXQS: 1828 caps->num_rxq = number; 1829 caps->rxq_first_id = phys_id; 1830 ice_debug(hw, ICE_DBG_INIT, 1831 "%s: num_rxq = %d\n", prefix, 1832 caps->num_rxq); 1833 ice_debug(hw, ICE_DBG_INIT, 1834 "%s: rxq_first_id = %d\n", prefix, 1835 caps->rxq_first_id); 1836 break; 1837 case ICE_AQC_CAPS_TXQS: 1838 caps->num_txq = number; 1839 caps->txq_first_id = phys_id; 1840 ice_debug(hw, ICE_DBG_INIT, 1841 "%s: num_txq = %d\n", prefix, 1842 caps->num_txq); 1843 ice_debug(hw, ICE_DBG_INIT, 1844 "%s: txq_first_id = %d\n", prefix, 1845 caps->txq_first_id); 1846 break; 1847 case ICE_AQC_CAPS_MSIX: 1848 caps->num_msix_vectors = number; 1849 caps->msix_vector_first_id = phys_id; 1850 ice_debug(hw, ICE_DBG_INIT, 1851 "%s: num_msix_vectors = %d\n", prefix, 1852 caps->num_msix_vectors); 1853 ice_debug(hw, ICE_DBG_INIT, 1854 "%s: msix_vector_first_id = %d\n", prefix, 1855 caps->msix_vector_first_id); 1856 break; 1857 case ICE_AQC_CAPS_PENDING_NVM_VER: 1858 caps->nvm_update_pending_nvm = true; 1859 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 1860 break; 1861 case ICE_AQC_CAPS_PENDING_OROM_VER: 1862 caps->nvm_update_pending_orom = true; 1863 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 1864 break; 1865 case ICE_AQC_CAPS_PENDING_NET_VER: 1866 caps->nvm_update_pending_netlist = true; 1867 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 1868 break; 1869 case ICE_AQC_CAPS_NVM_MGMT: 1870 caps->nvm_unified_update = 1871 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 1872 true : false; 1873 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 1874 caps->nvm_unified_update); 1875 break; 1876 case ICE_AQC_CAPS_MAX_MTU: 1877 caps->max_mtu = number; 1878 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 1879 prefix, caps->max_mtu); 1880 break; 1881 default: 1882 /* Not one of the recognized common capabilities */ 1883 found = false; 1884 } 1885 1886 return found; 1887 } 1888 1889 /** 1890 * ice_recalc_port_limited_caps - Recalculate port limited capabilities 1891 * @hw: pointer to the HW structure 1892 * @caps: pointer to capabilities structure to fix 1893 * 1894 * Re-calculate the capabilities that are dependent on the number of physical 1895 * ports; i.e. some features are not supported or function differently on 1896 * devices with more than 4 ports. 1897 */ 1898 static void 1899 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 1900 { 1901 /* This assumes device capabilities are always scanned before function 1902 * capabilities during the initialization flow. 1903 */ 1904 if (hw->dev_caps.num_funcs > 4) { 1905 /* Max 4 TCs per port */ 1906 caps->maxtc = 4; 1907 ice_debug(hw, ICE_DBG_INIT, 1908 "reducing maxtc to %d (based on #ports)\n", 1909 caps->maxtc); 1910 } 1911 } 1912 1913 /** 1914 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 1915 * @hw: pointer to the HW struct 1916 * @func_p: pointer to function capabilities structure 1917 * @cap: pointer to the capability element to parse 1918 * 1919 * Extract function capabilities for ICE_AQC_CAPS_VF. 1920 */ 1921 static void 1922 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 1923 struct ice_aqc_list_caps_elem *cap) 1924 { 1925 u32 logical_id = le32_to_cpu(cap->logical_id); 1926 u32 number = le32_to_cpu(cap->number); 1927 1928 func_p->num_allocd_vfs = number; 1929 func_p->vf_base_id = logical_id; 1930 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 1931 func_p->num_allocd_vfs); 1932 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 1933 func_p->vf_base_id); 1934 } 1935 1936 /** 1937 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 1938 * @hw: pointer to the HW struct 1939 * @func_p: pointer to function capabilities structure 1940 * @cap: pointer to the capability element to parse 1941 * 1942 * Extract function capabilities for ICE_AQC_CAPS_VSI. 1943 */ 1944 static void 1945 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 1946 struct ice_aqc_list_caps_elem *cap) 1947 { 1948 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 1949 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 1950 le32_to_cpu(cap->number)); 1951 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 1952 func_p->guar_num_vsi); 1953 } 1954 1955 /** 1956 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 1957 * @hw: pointer to the HW struct 1958 * @func_p: pointer to function capabilities structure 1959 * 1960 * Extract function capabilities for ICE_AQC_CAPS_FD. 1961 */ 1962 static void 1963 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 1964 { 1965 u32 reg_val, val; 1966 1967 reg_val = rd32(hw, GLQF_FD_SIZE); 1968 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 1969 GLQF_FD_SIZE_FD_GSIZE_S; 1970 func_p->fd_fltr_guar = 1971 ice_get_num_per_func(hw, val); 1972 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 1973 GLQF_FD_SIZE_FD_BSIZE_S; 1974 func_p->fd_fltr_best_effort = val; 1975 1976 ice_debug(hw, ICE_DBG_INIT, 1977 "func caps: fd_fltr_guar = %d\n", 1978 func_p->fd_fltr_guar); 1979 ice_debug(hw, ICE_DBG_INIT, 1980 "func caps: fd_fltr_best_effort = %d\n", 1981 func_p->fd_fltr_best_effort); 1982 } 1983 1984 /** 1985 * ice_parse_func_caps - Parse function capabilities 1986 * @hw: pointer to the HW struct 1987 * @func_p: pointer to function capabilities structure 1988 * @buf: buffer containing the function capability records 1989 * @cap_count: the number of capabilities 1990 * 1991 * Helper function to parse function (0x000A) capabilities list. For 1992 * capabilities shared between device and function, this relies on 1993 * ice_parse_common_caps. 1994 * 1995 * Loop through the list of provided capabilities and extract the relevant 1996 * data into the function capabilities structured. 1997 */ 1998 static void 1999 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 2000 void *buf, u32 cap_count) 2001 { 2002 struct ice_aqc_list_caps_elem *cap_resp; 2003 u32 i; 2004 2005 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2006 2007 memset(func_p, 0, sizeof(*func_p)); 2008 2009 for (i = 0; i < cap_count; i++) { 2010 u16 cap = le16_to_cpu(cap_resp[i].cap); 2011 bool found; 2012 2013 found = ice_parse_common_caps(hw, &func_p->common_cap, 2014 &cap_resp[i], "func caps"); 2015 2016 switch (cap) { 2017 case ICE_AQC_CAPS_VF: 2018 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 2019 break; 2020 case ICE_AQC_CAPS_VSI: 2021 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 2022 break; 2023 case ICE_AQC_CAPS_FD: 2024 ice_parse_fdir_func_caps(hw, func_p); 2025 break; 2026 default: 2027 /* Don't list common capabilities as unknown */ 2028 if (!found) 2029 ice_debug(hw, ICE_DBG_INIT, 2030 "func caps: unknown capability[%d]: 0x%x\n", 2031 i, cap); 2032 break; 2033 } 2034 } 2035 2036 ice_recalc_port_limited_caps(hw, &func_p->common_cap); 2037 } 2038 2039 /** 2040 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2041 * @hw: pointer to the HW struct 2042 * @dev_p: pointer to device capabilities structure 2043 * @cap: capability element to parse 2044 * 2045 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2046 */ 2047 static void 2048 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2049 struct ice_aqc_list_caps_elem *cap) 2050 { 2051 u32 number = le32_to_cpu(cap->number); 2052 2053 dev_p->num_funcs = hweight32(number); 2054 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2055 dev_p->num_funcs); 2056 } 2057 2058 /** 2059 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2060 * @hw: pointer to the HW struct 2061 * @dev_p: pointer to device capabilities structure 2062 * @cap: capability element to parse 2063 * 2064 * Parse ICE_AQC_CAPS_VF for device capabilities. 2065 */ 2066 static void 2067 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2068 struct ice_aqc_list_caps_elem *cap) 2069 { 2070 u32 number = le32_to_cpu(cap->number); 2071 2072 dev_p->num_vfs_exposed = number; 2073 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2074 dev_p->num_vfs_exposed); 2075 } 2076 2077 /** 2078 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2079 * @hw: pointer to the HW struct 2080 * @dev_p: pointer to device capabilities structure 2081 * @cap: capability element to parse 2082 * 2083 * Parse ICE_AQC_CAPS_VSI for device capabilities. 2084 */ 2085 static void 2086 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2087 struct ice_aqc_list_caps_elem *cap) 2088 { 2089 u32 number = le32_to_cpu(cap->number); 2090 2091 dev_p->num_vsi_allocd_to_host = number; 2092 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2093 dev_p->num_vsi_allocd_to_host); 2094 } 2095 2096 /** 2097 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2098 * @hw: pointer to the HW struct 2099 * @dev_p: pointer to device capabilities structure 2100 * @cap: capability element to parse 2101 * 2102 * Parse ICE_AQC_CAPS_FD for device capabilities. 2103 */ 2104 static void 2105 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2106 struct ice_aqc_list_caps_elem *cap) 2107 { 2108 u32 number = le32_to_cpu(cap->number); 2109 2110 dev_p->num_flow_director_fltr = number; 2111 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2112 dev_p->num_flow_director_fltr); 2113 } 2114 2115 /** 2116 * ice_parse_dev_caps - Parse device capabilities 2117 * @hw: pointer to the HW struct 2118 * @dev_p: pointer to device capabilities structure 2119 * @buf: buffer containing the device capability records 2120 * @cap_count: the number of capabilities 2121 * 2122 * Helper device to parse device (0x000B) capabilities list. For 2123 * capabilities shared between device and function, this relies on 2124 * ice_parse_common_caps. 2125 * 2126 * Loop through the list of provided capabilities and extract the relevant 2127 * data into the device capabilities structured. 2128 */ 2129 static void 2130 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2131 void *buf, u32 cap_count) 2132 { 2133 struct ice_aqc_list_caps_elem *cap_resp; 2134 u32 i; 2135 2136 cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2137 2138 memset(dev_p, 0, sizeof(*dev_p)); 2139 2140 for (i = 0; i < cap_count; i++) { 2141 u16 cap = le16_to_cpu(cap_resp[i].cap); 2142 bool found; 2143 2144 found = ice_parse_common_caps(hw, &dev_p->common_cap, 2145 &cap_resp[i], "dev caps"); 2146 2147 switch (cap) { 2148 case ICE_AQC_CAPS_VALID_FUNCTIONS: 2149 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2150 break; 2151 case ICE_AQC_CAPS_VF: 2152 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2153 break; 2154 case ICE_AQC_CAPS_VSI: 2155 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2156 break; 2157 case ICE_AQC_CAPS_FD: 2158 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2159 break; 2160 default: 2161 /* Don't list common capabilities as unknown */ 2162 if (!found) 2163 ice_debug(hw, ICE_DBG_INIT, 2164 "dev caps: unknown capability[%d]: 0x%x\n", 2165 i, cap); 2166 break; 2167 } 2168 } 2169 2170 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2171 } 2172 2173 /** 2174 * ice_aq_list_caps - query function/device capabilities 2175 * @hw: pointer to the HW struct 2176 * @buf: a buffer to hold the capabilities 2177 * @buf_size: size of the buffer 2178 * @cap_count: if not NULL, set to the number of capabilities reported 2179 * @opc: capabilities type to discover, device or function 2180 * @cd: pointer to command details structure or NULL 2181 * 2182 * Get the function (0x000A) or device (0x000B) capabilities description from 2183 * firmware and store it in the buffer. 2184 * 2185 * If the cap_count pointer is not NULL, then it is set to the number of 2186 * capabilities firmware will report. Note that if the buffer size is too 2187 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 2188 * cap_count will still be updated in this case. It is recommended that the 2189 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 2190 * firmware could return) to avoid this. 2191 */ 2192 enum ice_status 2193 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 2194 enum ice_adminq_opc opc, struct ice_sq_cd *cd) 2195 { 2196 struct ice_aqc_list_caps *cmd; 2197 struct ice_aq_desc desc; 2198 enum ice_status status; 2199 2200 cmd = &desc.params.get_cap; 2201 2202 if (opc != ice_aqc_opc_list_func_caps && 2203 opc != ice_aqc_opc_list_dev_caps) 2204 return ICE_ERR_PARAM; 2205 2206 ice_fill_dflt_direct_cmd_desc(&desc, opc); 2207 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2208 2209 if (cap_count) 2210 *cap_count = le32_to_cpu(cmd->count); 2211 2212 return status; 2213 } 2214 2215 /** 2216 * ice_discover_dev_caps - Read and extract device capabilities 2217 * @hw: pointer to the hardware structure 2218 * @dev_caps: pointer to device capabilities structure 2219 * 2220 * Read the device capabilities and extract them into the dev_caps structure 2221 * for later use. 2222 */ 2223 enum ice_status 2224 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 2225 { 2226 enum ice_status status; 2227 u32 cap_count = 0; 2228 void *cbuf; 2229 2230 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2231 if (!cbuf) 2232 return ICE_ERR_NO_MEMORY; 2233 2234 /* Although the driver doesn't know the number of capabilities the 2235 * device will return, we can simply send a 4KB buffer, the maximum 2236 * possible size that firmware can return. 2237 */ 2238 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2239 2240 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2241 ice_aqc_opc_list_dev_caps, NULL); 2242 if (!status) 2243 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 2244 kfree(cbuf); 2245 2246 return status; 2247 } 2248 2249 /** 2250 * ice_discover_func_caps - Read and extract function capabilities 2251 * @hw: pointer to the hardware structure 2252 * @func_caps: pointer to function capabilities structure 2253 * 2254 * Read the function capabilities and extract them into the func_caps structure 2255 * for later use. 2256 */ 2257 static enum ice_status 2258 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 2259 { 2260 enum ice_status status; 2261 u32 cap_count = 0; 2262 void *cbuf; 2263 2264 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 2265 if (!cbuf) 2266 return ICE_ERR_NO_MEMORY; 2267 2268 /* Although the driver doesn't know the number of capabilities the 2269 * device will return, we can simply send a 4KB buffer, the maximum 2270 * possible size that firmware can return. 2271 */ 2272 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 2273 2274 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 2275 ice_aqc_opc_list_func_caps, NULL); 2276 if (!status) 2277 ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 2278 kfree(cbuf); 2279 2280 return status; 2281 } 2282 2283 /** 2284 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2285 * @hw: pointer to the hardware structure 2286 */ 2287 void ice_set_safe_mode_caps(struct ice_hw *hw) 2288 { 2289 struct ice_hw_func_caps *func_caps = &hw->func_caps; 2290 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2291 u32 valid_func, rxq_first_id, txq_first_id; 2292 u32 msix_vector_first_id, max_mtu; 2293 u32 num_funcs; 2294 2295 /* cache some func_caps values that should be restored after memset */ 2296 valid_func = func_caps->common_cap.valid_functions; 2297 txq_first_id = func_caps->common_cap.txq_first_id; 2298 rxq_first_id = func_caps->common_cap.rxq_first_id; 2299 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id; 2300 max_mtu = func_caps->common_cap.max_mtu; 2301 2302 /* unset func capabilities */ 2303 memset(func_caps, 0, sizeof(*func_caps)); 2304 2305 /* restore cached values */ 2306 func_caps->common_cap.valid_functions = valid_func; 2307 func_caps->common_cap.txq_first_id = txq_first_id; 2308 func_caps->common_cap.rxq_first_id = rxq_first_id; 2309 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id; 2310 func_caps->common_cap.max_mtu = max_mtu; 2311 2312 /* one Tx and one Rx queue in safe mode */ 2313 func_caps->common_cap.num_rxq = 1; 2314 func_caps->common_cap.num_txq = 1; 2315 2316 /* two MSIX vectors, one for traffic and one for misc causes */ 2317 func_caps->common_cap.num_msix_vectors = 2; 2318 func_caps->guar_num_vsi = 1; 2319 2320 /* cache some dev_caps values that should be restored after memset */ 2321 valid_func = dev_caps->common_cap.valid_functions; 2322 txq_first_id = dev_caps->common_cap.txq_first_id; 2323 rxq_first_id = dev_caps->common_cap.rxq_first_id; 2324 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id; 2325 max_mtu = dev_caps->common_cap.max_mtu; 2326 num_funcs = dev_caps->num_funcs; 2327 2328 /* unset dev capabilities */ 2329 memset(dev_caps, 0, sizeof(*dev_caps)); 2330 2331 /* restore cached values */ 2332 dev_caps->common_cap.valid_functions = valid_func; 2333 dev_caps->common_cap.txq_first_id = txq_first_id; 2334 dev_caps->common_cap.rxq_first_id = rxq_first_id; 2335 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id; 2336 dev_caps->common_cap.max_mtu = max_mtu; 2337 dev_caps->num_funcs = num_funcs; 2338 2339 /* one Tx and one Rx queue per function in safe mode */ 2340 dev_caps->common_cap.num_rxq = num_funcs; 2341 dev_caps->common_cap.num_txq = num_funcs; 2342 2343 /* two MSIX vectors per function */ 2344 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2345 } 2346 2347 /** 2348 * ice_get_caps - get info about the HW 2349 * @hw: pointer to the hardware structure 2350 */ 2351 enum ice_status ice_get_caps(struct ice_hw *hw) 2352 { 2353 enum ice_status status; 2354 2355 status = ice_discover_dev_caps(hw, &hw->dev_caps); 2356 if (status) 2357 return status; 2358 2359 return ice_discover_func_caps(hw, &hw->func_caps); 2360 } 2361 2362 /** 2363 * ice_aq_manage_mac_write - manage MAC address write command 2364 * @hw: pointer to the HW struct 2365 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2366 * @flags: flags to control write behavior 2367 * @cd: pointer to command details structure or NULL 2368 * 2369 * This function is used to write MAC address to the NVM (0x0108). 2370 */ 2371 enum ice_status 2372 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2373 struct ice_sq_cd *cd) 2374 { 2375 struct ice_aqc_manage_mac_write *cmd; 2376 struct ice_aq_desc desc; 2377 2378 cmd = &desc.params.mac_write; 2379 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2380 2381 cmd->flags = flags; 2382 ether_addr_copy(cmd->mac_addr, mac_addr); 2383 2384 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2385 } 2386 2387 /** 2388 * ice_aq_clear_pxe_mode 2389 * @hw: pointer to the HW struct 2390 * 2391 * Tell the firmware that the driver is taking over from PXE (0x0110). 2392 */ 2393 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2394 { 2395 struct ice_aq_desc desc; 2396 2397 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2398 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2399 2400 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2401 } 2402 2403 /** 2404 * ice_clear_pxe_mode - clear pxe operations mode 2405 * @hw: pointer to the HW struct 2406 * 2407 * Make sure all PXE mode settings are cleared, including things 2408 * like descriptor fetch/write-back mode. 2409 */ 2410 void ice_clear_pxe_mode(struct ice_hw *hw) 2411 { 2412 if (ice_check_sq_alive(hw, &hw->adminq)) 2413 ice_aq_clear_pxe_mode(hw); 2414 } 2415 2416 /** 2417 * ice_get_link_speed_based_on_phy_type - returns link speed 2418 * @phy_type_low: lower part of phy_type 2419 * @phy_type_high: higher part of phy_type 2420 * 2421 * This helper function will convert an entry in PHY type structure 2422 * [phy_type_low, phy_type_high] to its corresponding link speed. 2423 * Note: In the structure of [phy_type_low, phy_type_high], there should 2424 * be one bit set, as this function will convert one PHY type to its 2425 * speed. 2426 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2427 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 2428 */ 2429 static u16 2430 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 2431 { 2432 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2433 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2434 2435 switch (phy_type_low) { 2436 case ICE_PHY_TYPE_LOW_100BASE_TX: 2437 case ICE_PHY_TYPE_LOW_100M_SGMII: 2438 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 2439 break; 2440 case ICE_PHY_TYPE_LOW_1000BASE_T: 2441 case ICE_PHY_TYPE_LOW_1000BASE_SX: 2442 case ICE_PHY_TYPE_LOW_1000BASE_LX: 2443 case ICE_PHY_TYPE_LOW_1000BASE_KX: 2444 case ICE_PHY_TYPE_LOW_1G_SGMII: 2445 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 2446 break; 2447 case ICE_PHY_TYPE_LOW_2500BASE_T: 2448 case ICE_PHY_TYPE_LOW_2500BASE_X: 2449 case ICE_PHY_TYPE_LOW_2500BASE_KX: 2450 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 2451 break; 2452 case ICE_PHY_TYPE_LOW_5GBASE_T: 2453 case ICE_PHY_TYPE_LOW_5GBASE_KR: 2454 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 2455 break; 2456 case ICE_PHY_TYPE_LOW_10GBASE_T: 2457 case ICE_PHY_TYPE_LOW_10G_SFI_DA: 2458 case ICE_PHY_TYPE_LOW_10GBASE_SR: 2459 case ICE_PHY_TYPE_LOW_10GBASE_LR: 2460 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 2461 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 2462 case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 2463 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 2464 break; 2465 case ICE_PHY_TYPE_LOW_25GBASE_T: 2466 case ICE_PHY_TYPE_LOW_25GBASE_CR: 2467 case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 2468 case ICE_PHY_TYPE_LOW_25GBASE_CR1: 2469 case ICE_PHY_TYPE_LOW_25GBASE_SR: 2470 case ICE_PHY_TYPE_LOW_25GBASE_LR: 2471 case ICE_PHY_TYPE_LOW_25GBASE_KR: 2472 case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 2473 case ICE_PHY_TYPE_LOW_25GBASE_KR1: 2474 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 2475 case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 2476 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 2477 break; 2478 case ICE_PHY_TYPE_LOW_40GBASE_CR4: 2479 case ICE_PHY_TYPE_LOW_40GBASE_SR4: 2480 case ICE_PHY_TYPE_LOW_40GBASE_LR4: 2481 case ICE_PHY_TYPE_LOW_40GBASE_KR4: 2482 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 2483 case ICE_PHY_TYPE_LOW_40G_XLAUI: 2484 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 2485 break; 2486 case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2487 case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2488 case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2489 case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2490 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2491 case ICE_PHY_TYPE_LOW_50G_LAUI2: 2492 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2493 case ICE_PHY_TYPE_LOW_50G_AUI2: 2494 case ICE_PHY_TYPE_LOW_50GBASE_CP: 2495 case ICE_PHY_TYPE_LOW_50GBASE_SR: 2496 case ICE_PHY_TYPE_LOW_50GBASE_FR: 2497 case ICE_PHY_TYPE_LOW_50GBASE_LR: 2498 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2499 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2500 case ICE_PHY_TYPE_LOW_50G_AUI1: 2501 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2502 break; 2503 case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2504 case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2505 case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2506 case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2507 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2508 case ICE_PHY_TYPE_LOW_100G_CAUI4: 2509 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2510 case ICE_PHY_TYPE_LOW_100G_AUI4: 2511 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2512 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2513 case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2514 case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2515 case ICE_PHY_TYPE_LOW_100GBASE_DR: 2516 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2517 break; 2518 default: 2519 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 2520 break; 2521 } 2522 2523 switch (phy_type_high) { 2524 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2525 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2526 case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2527 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2528 case ICE_PHY_TYPE_HIGH_100G_AUI2: 2529 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2530 break; 2531 default: 2532 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2533 break; 2534 } 2535 2536 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2537 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2538 return ICE_AQ_LINK_SPEED_UNKNOWN; 2539 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2540 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2541 return ICE_AQ_LINK_SPEED_UNKNOWN; 2542 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2543 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2544 return speed_phy_type_low; 2545 else 2546 return speed_phy_type_high; 2547 } 2548 2549 /** 2550 * ice_update_phy_type 2551 * @phy_type_low: pointer to the lower part of phy_type 2552 * @phy_type_high: pointer to the higher part of phy_type 2553 * @link_speeds_bitmap: targeted link speeds bitmap 2554 * 2555 * Note: For the link_speeds_bitmap structure, you can check it at 2556 * [ice_aqc_get_link_status->link_speed]. Caller can pass in 2557 * link_speeds_bitmap include multiple speeds. 2558 * 2559 * Each entry in this [phy_type_low, phy_type_high] structure will 2560 * present a certain link speed. This helper function will turn on bits 2561 * in [phy_type_low, phy_type_high] structure based on the value of 2562 * link_speeds_bitmap input parameter. 2563 */ 2564 void 2565 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2566 u16 link_speeds_bitmap) 2567 { 2568 u64 pt_high; 2569 u64 pt_low; 2570 int index; 2571 u16 speed; 2572 2573 /* We first check with low part of phy_type */ 2574 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 2575 pt_low = BIT_ULL(index); 2576 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 2577 2578 if (link_speeds_bitmap & speed) 2579 *phy_type_low |= BIT_ULL(index); 2580 } 2581 2582 /* We then check with high part of phy_type */ 2583 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2584 pt_high = BIT_ULL(index); 2585 speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2586 2587 if (link_speeds_bitmap & speed) 2588 *phy_type_high |= BIT_ULL(index); 2589 } 2590 } 2591 2592 /** 2593 * ice_aq_set_phy_cfg 2594 * @hw: pointer to the HW struct 2595 * @pi: port info structure of the interested logical port 2596 * @cfg: structure with PHY configuration data to be set 2597 * @cd: pointer to command details structure or NULL 2598 * 2599 * Set the various PHY configuration parameters supported on the Port. 2600 * One or more of the Set PHY config parameters may be ignored in an MFP 2601 * mode as the PF may not have the privilege to set some of the PHY Config 2602 * parameters. This status will be indicated by the command response (0x0601). 2603 */ 2604 enum ice_status 2605 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2606 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2607 { 2608 struct ice_aq_desc desc; 2609 enum ice_status status; 2610 2611 if (!cfg) 2612 return ICE_ERR_PARAM; 2613 2614 /* Ensure that only valid bits of cfg->caps can be turned on. */ 2615 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2616 ice_debug(hw, ICE_DBG_PHY, 2617 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2618 cfg->caps); 2619 2620 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2621 } 2622 2623 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 2624 desc.params.set_phy.lport_num = pi->lport; 2625 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2626 2627 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 2628 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 2629 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 2630 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 2631 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 2632 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 2633 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 2634 cfg->low_power_ctrl_an); 2635 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 2636 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 2637 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 2638 cfg->link_fec_opt); 2639 2640 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2641 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 2642 status = 0; 2643 2644 if (!status) 2645 pi->phy.curr_user_phy_cfg = *cfg; 2646 2647 return status; 2648 } 2649 2650 /** 2651 * ice_update_link_info - update status of the HW network link 2652 * @pi: port info structure of the interested logical port 2653 */ 2654 enum ice_status ice_update_link_info(struct ice_port_info *pi) 2655 { 2656 struct ice_link_status *li; 2657 enum ice_status status; 2658 2659 if (!pi) 2660 return ICE_ERR_PARAM; 2661 2662 li = &pi->phy.link_info; 2663 2664 status = ice_aq_get_link_info(pi, true, NULL, NULL); 2665 if (status) 2666 return status; 2667 2668 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2669 struct ice_aqc_get_phy_caps_data *pcaps; 2670 struct ice_hw *hw; 2671 2672 hw = pi->hw; 2673 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 2674 GFP_KERNEL); 2675 if (!pcaps) 2676 return ICE_ERR_NO_MEMORY; 2677 2678 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, 2679 pcaps, NULL); 2680 2681 devm_kfree(ice_hw_to_dev(hw), pcaps); 2682 } 2683 2684 return status; 2685 } 2686 2687 /** 2688 * ice_cache_phy_user_req 2689 * @pi: port information structure 2690 * @cache_data: PHY logging data 2691 * @cache_mode: PHY logging mode 2692 * 2693 * Log the user request on (FC, FEC, SPEED) for later use. 2694 */ 2695 static void 2696 ice_cache_phy_user_req(struct ice_port_info *pi, 2697 struct ice_phy_cache_mode_data cache_data, 2698 enum ice_phy_cache_mode cache_mode) 2699 { 2700 if (!pi) 2701 return; 2702 2703 switch (cache_mode) { 2704 case ICE_FC_MODE: 2705 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 2706 break; 2707 case ICE_SPEED_MODE: 2708 pi->phy.curr_user_speed_req = 2709 cache_data.data.curr_user_speed_req; 2710 break; 2711 case ICE_FEC_MODE: 2712 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 2713 break; 2714 default: 2715 break; 2716 } 2717 } 2718 2719 /** 2720 * ice_caps_to_fc_mode 2721 * @caps: PHY capabilities 2722 * 2723 * Convert PHY FC capabilities to ice FC mode 2724 */ 2725 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 2726 { 2727 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 2728 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2729 return ICE_FC_FULL; 2730 2731 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 2732 return ICE_FC_TX_PAUSE; 2733 2734 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 2735 return ICE_FC_RX_PAUSE; 2736 2737 return ICE_FC_NONE; 2738 } 2739 2740 /** 2741 * ice_caps_to_fec_mode 2742 * @caps: PHY capabilities 2743 * @fec_options: Link FEC options 2744 * 2745 * Convert PHY FEC capabilities to ice FEC mode 2746 */ 2747 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 2748 { 2749 if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 2750 return ICE_FEC_AUTO; 2751 2752 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2753 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2754 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 2755 ICE_AQC_PHY_FEC_25G_KR_REQ)) 2756 return ICE_FEC_BASER; 2757 2758 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2759 ICE_AQC_PHY_FEC_25G_RS_544_REQ | 2760 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 2761 return ICE_FEC_RS; 2762 2763 return ICE_FEC_NONE; 2764 } 2765 2766 /** 2767 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 2768 * @pi: port information structure 2769 * @cfg: PHY configuration data to set FC mode 2770 * @req_mode: FC mode to configure 2771 */ 2772 enum ice_status 2773 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 2774 enum ice_fc_mode req_mode) 2775 { 2776 struct ice_phy_cache_mode_data cache_data; 2777 u8 pause_mask = 0x0; 2778 2779 if (!pi || !cfg) 2780 return ICE_ERR_BAD_PTR; 2781 2782 switch (req_mode) { 2783 case ICE_FC_FULL: 2784 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2785 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2786 break; 2787 case ICE_FC_RX_PAUSE: 2788 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2789 break; 2790 case ICE_FC_TX_PAUSE: 2791 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2792 break; 2793 default: 2794 break; 2795 } 2796 2797 /* clear the old pause settings */ 2798 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 2799 ICE_AQC_PHY_EN_RX_LINK_PAUSE); 2800 2801 /* set the new capabilities */ 2802 cfg->caps |= pause_mask; 2803 2804 /* Cache user FC request */ 2805 cache_data.data.curr_user_fc_req = req_mode; 2806 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 2807 2808 return 0; 2809 } 2810 2811 /** 2812 * ice_set_fc 2813 * @pi: port information structure 2814 * @aq_failures: pointer to status code, specific to ice_set_fc routine 2815 * @ena_auto_link_update: enable automatic link update 2816 * 2817 * Set the requested flow control mode. 2818 */ 2819 enum ice_status 2820 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 2821 { 2822 struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 2823 struct ice_aqc_get_phy_caps_data *pcaps; 2824 enum ice_status status; 2825 struct ice_hw *hw; 2826 2827 if (!pi || !aq_failures) 2828 return ICE_ERR_BAD_PTR; 2829 2830 *aq_failures = 0; 2831 hw = pi->hw; 2832 2833 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 2834 if (!pcaps) 2835 return ICE_ERR_NO_MEMORY; 2836 2837 /* Get the current PHY config */ 2838 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 2839 NULL); 2840 if (status) { 2841 *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2842 goto out; 2843 } 2844 2845 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 2846 2847 /* Configure the set PHY data */ 2848 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 2849 if (status) 2850 goto out; 2851 2852 /* If the capabilities have changed, then set the new config */ 2853 if (cfg.caps != pcaps->caps) { 2854 int retry_count, retry_max = 10; 2855 2856 /* Auto restart link so settings take effect */ 2857 if (ena_auto_link_update) 2858 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2859 2860 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 2861 if (status) { 2862 *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 2863 goto out; 2864 } 2865 2866 /* Update the link info 2867 * It sometimes takes a really long time for link to 2868 * come back from the atomic reset. Thus, we wait a 2869 * little bit. 2870 */ 2871 for (retry_count = 0; retry_count < retry_max; retry_count++) { 2872 status = ice_update_link_info(pi); 2873 2874 if (!status) 2875 break; 2876 2877 mdelay(100); 2878 } 2879 2880 if (status) 2881 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 2882 } 2883 2884 out: 2885 devm_kfree(ice_hw_to_dev(hw), pcaps); 2886 return status; 2887 } 2888 2889 /** 2890 * ice_phy_caps_equals_cfg 2891 * @phy_caps: PHY capabilities 2892 * @phy_cfg: PHY configuration 2893 * 2894 * Helper function to determine if PHY capabilities matches PHY 2895 * configuration 2896 */ 2897 bool 2898 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 2899 struct ice_aqc_set_phy_cfg_data *phy_cfg) 2900 { 2901 u8 caps_mask, cfg_mask; 2902 2903 if (!phy_caps || !phy_cfg) 2904 return false; 2905 2906 /* These bits are not common between capabilities and configuration. 2907 * Do not use them to determine equality. 2908 */ 2909 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 2910 ICE_AQC_GET_PHY_EN_MOD_QUAL); 2911 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2912 2913 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 2914 phy_caps->phy_type_high != phy_cfg->phy_type_high || 2915 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 2916 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 2917 phy_caps->eee_cap != phy_cfg->eee_cap || 2918 phy_caps->eeer_value != phy_cfg->eeer_value || 2919 phy_caps->link_fec_options != phy_cfg->link_fec_opt) 2920 return false; 2921 2922 return true; 2923 } 2924 2925 /** 2926 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 2927 * @pi: port information structure 2928 * @caps: PHY ability structure to copy date from 2929 * @cfg: PHY configuration structure to copy data to 2930 * 2931 * Helper function to copy AQC PHY get ability data to PHY set configuration 2932 * data structure 2933 */ 2934 void 2935 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 2936 struct ice_aqc_get_phy_caps_data *caps, 2937 struct ice_aqc_set_phy_cfg_data *cfg) 2938 { 2939 if (!pi || !caps || !cfg) 2940 return; 2941 2942 memset(cfg, 0, sizeof(*cfg)); 2943 cfg->phy_type_low = caps->phy_type_low; 2944 cfg->phy_type_high = caps->phy_type_high; 2945 cfg->caps = caps->caps; 2946 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 2947 cfg->eee_cap = caps->eee_cap; 2948 cfg->eeer_value = caps->eeer_value; 2949 cfg->link_fec_opt = caps->link_fec_options; 2950 cfg->module_compliance_enforcement = 2951 caps->module_compliance_enforcement; 2952 2953 if (ice_fw_supports_link_override(pi->hw)) { 2954 struct ice_link_default_override_tlv tlv; 2955 2956 if (ice_get_link_default_override(&tlv, pi)) 2957 return; 2958 2959 if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) 2960 cfg->module_compliance_enforcement |= 2961 ICE_LINK_OVERRIDE_STRICT_MODE; 2962 } 2963 } 2964 2965 /** 2966 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 2967 * @pi: port information structure 2968 * @cfg: PHY configuration data to set FEC mode 2969 * @fec: FEC mode to configure 2970 */ 2971 enum ice_status 2972 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 2973 enum ice_fec_mode fec) 2974 { 2975 struct ice_aqc_get_phy_caps_data *pcaps; 2976 enum ice_status status; 2977 2978 if (!pi || !cfg) 2979 return ICE_ERR_BAD_PTR; 2980 2981 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 2982 if (!pcaps) 2983 return ICE_ERR_NO_MEMORY; 2984 2985 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps, 2986 NULL); 2987 if (status) 2988 goto out; 2989 2990 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 2991 cfg->link_fec_opt = pcaps->link_fec_options; 2992 2993 switch (fec) { 2994 case ICE_FEC_BASER: 2995 /* Clear RS bits, and AND BASE-R ability 2996 * bits and OR request bits. 2997 */ 2998 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2999 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 3000 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 3001 ICE_AQC_PHY_FEC_25G_KR_REQ; 3002 break; 3003 case ICE_FEC_RS: 3004 /* Clear BASE-R bits, and AND RS ability 3005 * bits and OR request bits. 3006 */ 3007 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 3008 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 3009 ICE_AQC_PHY_FEC_25G_RS_544_REQ; 3010 break; 3011 case ICE_FEC_NONE: 3012 /* Clear all FEC option bits. */ 3013 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 3014 break; 3015 case ICE_FEC_AUTO: 3016 /* AND auto FEC bit, and all caps bits. */ 3017 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 3018 cfg->link_fec_opt |= pcaps->link_fec_options; 3019 break; 3020 default: 3021 status = ICE_ERR_PARAM; 3022 break; 3023 } 3024 3025 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) { 3026 struct ice_link_default_override_tlv tlv; 3027 3028 if (ice_get_link_default_override(&tlv, pi)) 3029 goto out; 3030 3031 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3032 (tlv.options & ICE_LINK_OVERRIDE_EN)) 3033 cfg->link_fec_opt = tlv.fec_options; 3034 } 3035 3036 out: 3037 kfree(pcaps); 3038 3039 return status; 3040 } 3041 3042 /** 3043 * ice_get_link_status - get status of the HW network link 3044 * @pi: port information structure 3045 * @link_up: pointer to bool (true/false = linkup/linkdown) 3046 * 3047 * Variable link_up is true if link is up, false if link is down. 3048 * The variable link_up is invalid if status is non zero. As a 3049 * result of this call, link status reporting becomes enabled 3050 */ 3051 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 3052 { 3053 struct ice_phy_info *phy_info; 3054 enum ice_status status = 0; 3055 3056 if (!pi || !link_up) 3057 return ICE_ERR_PARAM; 3058 3059 phy_info = &pi->phy; 3060 3061 if (phy_info->get_link_info) { 3062 status = ice_update_link_info(pi); 3063 3064 if (status) 3065 ice_debug(pi->hw, ICE_DBG_LINK, 3066 "get link status error, status = %d\n", 3067 status); 3068 } 3069 3070 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 3071 3072 return status; 3073 } 3074 3075 /** 3076 * ice_aq_set_link_restart_an 3077 * @pi: pointer to the port information structure 3078 * @ena_link: if true: enable link, if false: disable link 3079 * @cd: pointer to command details structure or NULL 3080 * 3081 * Sets up the link and restarts the Auto-Negotiation over the link. 3082 */ 3083 enum ice_status 3084 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3085 struct ice_sq_cd *cd) 3086 { 3087 struct ice_aqc_restart_an *cmd; 3088 struct ice_aq_desc desc; 3089 3090 cmd = &desc.params.restart_an; 3091 3092 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3093 3094 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3095 cmd->lport_num = pi->lport; 3096 if (ena_link) 3097 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3098 else 3099 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3100 3101 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3102 } 3103 3104 /** 3105 * ice_aq_set_event_mask 3106 * @hw: pointer to the HW struct 3107 * @port_num: port number of the physical function 3108 * @mask: event mask to be set 3109 * @cd: pointer to command details structure or NULL 3110 * 3111 * Set event mask (0x0613) 3112 */ 3113 enum ice_status 3114 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3115 struct ice_sq_cd *cd) 3116 { 3117 struct ice_aqc_set_event_mask *cmd; 3118 struct ice_aq_desc desc; 3119 3120 cmd = &desc.params.set_event_mask; 3121 3122 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3123 3124 cmd->lport_num = port_num; 3125 3126 cmd->event_mask = cpu_to_le16(mask); 3127 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3128 } 3129 3130 /** 3131 * ice_aq_set_mac_loopback 3132 * @hw: pointer to the HW struct 3133 * @ena_lpbk: Enable or Disable loopback 3134 * @cd: pointer to command details structure or NULL 3135 * 3136 * Enable/disable loopback on a given port 3137 */ 3138 enum ice_status 3139 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 3140 { 3141 struct ice_aqc_set_mac_lb *cmd; 3142 struct ice_aq_desc desc; 3143 3144 cmd = &desc.params.set_mac_lb; 3145 3146 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 3147 if (ena_lpbk) 3148 cmd->lb_mode = ICE_AQ_MAC_LB_EN; 3149 3150 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3151 } 3152 3153 /** 3154 * ice_aq_set_port_id_led 3155 * @pi: pointer to the port information 3156 * @is_orig_mode: is this LED set to original mode (by the net-list) 3157 * @cd: pointer to command details structure or NULL 3158 * 3159 * Set LED value for the given port (0x06e9) 3160 */ 3161 enum ice_status 3162 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 3163 struct ice_sq_cd *cd) 3164 { 3165 struct ice_aqc_set_port_id_led *cmd; 3166 struct ice_hw *hw = pi->hw; 3167 struct ice_aq_desc desc; 3168 3169 cmd = &desc.params.set_port_id_led; 3170 3171 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 3172 3173 if (is_orig_mode) 3174 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 3175 else 3176 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 3177 3178 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3179 } 3180 3181 /** 3182 * ice_aq_sff_eeprom 3183 * @hw: pointer to the HW struct 3184 * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3185 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3186 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3187 * @page: QSFP page 3188 * @set_page: set or ignore the page 3189 * @data: pointer to data buffer to be read/written to the I2C device. 3190 * @length: 1-16 for read, 1 for write. 3191 * @write: 0 read, 1 for write. 3192 * @cd: pointer to command details structure or NULL 3193 * 3194 * Read/Write SFF EEPROM (0x06EE) 3195 */ 3196 enum ice_status 3197 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3198 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3199 bool write, struct ice_sq_cd *cd) 3200 { 3201 struct ice_aqc_sff_eeprom *cmd; 3202 struct ice_aq_desc desc; 3203 enum ice_status status; 3204 3205 if (!data || (mem_addr & 0xff00)) 3206 return ICE_ERR_PARAM; 3207 3208 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3209 cmd = &desc.params.read_write_sff_param; 3210 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF); 3211 cmd->lport_num = (u8)(lport & 0xff); 3212 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3213 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 3214 ICE_AQC_SFF_I2CBUS_7BIT_M) | 3215 ((set_page << 3216 ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3217 ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3218 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3219 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3220 if (write) 3221 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 3222 3223 status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3224 return status; 3225 } 3226 3227 /** 3228 * __ice_aq_get_set_rss_lut 3229 * @hw: pointer to the hardware structure 3230 * @vsi_id: VSI FW index 3231 * @lut_type: LUT table type 3232 * @lut: pointer to the LUT buffer provided by the caller 3233 * @lut_size: size of the LUT buffer 3234 * @glob_lut_idx: global LUT index 3235 * @set: set true to set the table, false to get the table 3236 * 3237 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3238 */ 3239 static enum ice_status 3240 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 3241 u16 lut_size, u8 glob_lut_idx, bool set) 3242 { 3243 struct ice_aqc_get_set_rss_lut *cmd_resp; 3244 struct ice_aq_desc desc; 3245 enum ice_status status; 3246 u16 flags = 0; 3247 3248 cmd_resp = &desc.params.get_set_rss_lut; 3249 3250 if (set) { 3251 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3252 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3253 } else { 3254 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3255 } 3256 3257 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3258 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3259 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3260 ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3261 3262 switch (lut_type) { 3263 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3264 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3265 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3266 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3267 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3268 break; 3269 default: 3270 status = ICE_ERR_PARAM; 3271 goto ice_aq_get_set_rss_lut_exit; 3272 } 3273 3274 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3275 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3276 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3277 3278 if (!set) 3279 goto ice_aq_get_set_rss_lut_send; 3280 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3281 if (!set) 3282 goto ice_aq_get_set_rss_lut_send; 3283 } else { 3284 goto ice_aq_get_set_rss_lut_send; 3285 } 3286 3287 /* LUT size is only valid for Global and PF table types */ 3288 switch (lut_size) { 3289 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 3290 break; 3291 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3292 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3293 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3294 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3295 break; 3296 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 3297 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3298 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3299 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3300 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 3301 break; 3302 } 3303 fallthrough; 3304 default: 3305 status = ICE_ERR_PARAM; 3306 goto ice_aq_get_set_rss_lut_exit; 3307 } 3308 3309 ice_aq_get_set_rss_lut_send: 3310 cmd_resp->flags = cpu_to_le16(flags); 3311 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3312 3313 ice_aq_get_set_rss_lut_exit: 3314 return status; 3315 } 3316 3317 /** 3318 * ice_aq_get_rss_lut 3319 * @hw: pointer to the hardware structure 3320 * @vsi_handle: software VSI handle 3321 * @lut_type: LUT table type 3322 * @lut: pointer to the LUT buffer provided by the caller 3323 * @lut_size: size of the LUT buffer 3324 * 3325 * get the RSS lookup table, PF or VSI type 3326 */ 3327 enum ice_status 3328 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 3329 u8 *lut, u16 lut_size) 3330 { 3331 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3332 return ICE_ERR_PARAM; 3333 3334 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3335 lut_type, lut, lut_size, 0, false); 3336 } 3337 3338 /** 3339 * ice_aq_set_rss_lut 3340 * @hw: pointer to the hardware structure 3341 * @vsi_handle: software VSI handle 3342 * @lut_type: LUT table type 3343 * @lut: pointer to the LUT buffer provided by the caller 3344 * @lut_size: size of the LUT buffer 3345 * 3346 * set the RSS lookup table, PF or VSI type 3347 */ 3348 enum ice_status 3349 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 3350 u8 *lut, u16 lut_size) 3351 { 3352 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3353 return ICE_ERR_PARAM; 3354 3355 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3356 lut_type, lut, lut_size, 0, true); 3357 } 3358 3359 /** 3360 * __ice_aq_get_set_rss_key 3361 * @hw: pointer to the HW struct 3362 * @vsi_id: VSI FW index 3363 * @key: pointer to key info struct 3364 * @set: set true to set the key, false to get the key 3365 * 3366 * get (0x0B04) or set (0x0B02) the RSS key per VSI 3367 */ 3368 static enum 3369 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3370 struct ice_aqc_get_set_rss_keys *key, 3371 bool set) 3372 { 3373 struct ice_aqc_get_set_rss_key *cmd_resp; 3374 u16 key_size = sizeof(*key); 3375 struct ice_aq_desc desc; 3376 3377 cmd_resp = &desc.params.get_set_rss_key; 3378 3379 if (set) { 3380 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3381 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3382 } else { 3383 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3384 } 3385 3386 cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3387 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3388 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3389 ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3390 3391 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3392 } 3393 3394 /** 3395 * ice_aq_get_rss_key 3396 * @hw: pointer to the HW struct 3397 * @vsi_handle: software VSI handle 3398 * @key: pointer to key info struct 3399 * 3400 * get the RSS key per VSI 3401 */ 3402 enum ice_status 3403 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3404 struct ice_aqc_get_set_rss_keys *key) 3405 { 3406 if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 3407 return ICE_ERR_PARAM; 3408 3409 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3410 key, false); 3411 } 3412 3413 /** 3414 * ice_aq_set_rss_key 3415 * @hw: pointer to the HW struct 3416 * @vsi_handle: software VSI handle 3417 * @keys: pointer to key info struct 3418 * 3419 * set the RSS key per VSI 3420 */ 3421 enum ice_status 3422 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3423 struct ice_aqc_get_set_rss_keys *keys) 3424 { 3425 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 3426 return ICE_ERR_PARAM; 3427 3428 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 3429 keys, true); 3430 } 3431 3432 /** 3433 * ice_aq_add_lan_txq 3434 * @hw: pointer to the hardware structure 3435 * @num_qgrps: Number of added queue groups 3436 * @qg_list: list of queue groups to be added 3437 * @buf_size: size of buffer for indirect command 3438 * @cd: pointer to command details structure or NULL 3439 * 3440 * Add Tx LAN queue (0x0C30) 3441 * 3442 * NOTE: 3443 * Prior to calling add Tx LAN queue: 3444 * Initialize the following as part of the Tx queue context: 3445 * Completion queue ID if the queue uses Completion queue, Quanta profile, 3446 * Cache profile and Packet shaper profile. 3447 * 3448 * After add Tx LAN queue AQ command is completed: 3449 * Interrupts should be associated with specific queues, 3450 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3451 * flow. 3452 */ 3453 static enum ice_status 3454 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3455 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3456 struct ice_sq_cd *cd) 3457 { 3458 struct ice_aqc_add_tx_qgrp *list; 3459 struct ice_aqc_add_txqs *cmd; 3460 struct ice_aq_desc desc; 3461 u16 i, sum_size = 0; 3462 3463 cmd = &desc.params.add_txqs; 3464 3465 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3466 3467 if (!qg_list) 3468 return ICE_ERR_PARAM; 3469 3470 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3471 return ICE_ERR_PARAM; 3472 3473 for (i = 0, list = qg_list; i < num_qgrps; i++) { 3474 sum_size += struct_size(list, txqs, list->num_txqs); 3475 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 3476 list->num_txqs); 3477 } 3478 3479 if (buf_size != sum_size) 3480 return ICE_ERR_PARAM; 3481 3482 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3483 3484 cmd->num_qgrps = num_qgrps; 3485 3486 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3487 } 3488 3489 /** 3490 * ice_aq_dis_lan_txq 3491 * @hw: pointer to the hardware structure 3492 * @num_qgrps: number of groups in the list 3493 * @qg_list: the list of groups to disable 3494 * @buf_size: the total size of the qg_list buffer in bytes 3495 * @rst_src: if called due to reset, specifies the reset source 3496 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3497 * @cd: pointer to command details structure or NULL 3498 * 3499 * Disable LAN Tx queue (0x0C31) 3500 */ 3501 static enum ice_status 3502 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3503 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3504 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3505 struct ice_sq_cd *cd) 3506 { 3507 struct ice_aqc_dis_txq_item *item; 3508 struct ice_aqc_dis_txqs *cmd; 3509 struct ice_aq_desc desc; 3510 enum ice_status status; 3511 u16 i, sz = 0; 3512 3513 cmd = &desc.params.dis_txqs; 3514 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3515 3516 /* qg_list can be NULL only in VM/VF reset flow */ 3517 if (!qg_list && !rst_src) 3518 return ICE_ERR_PARAM; 3519 3520 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3521 return ICE_ERR_PARAM; 3522 3523 cmd->num_entries = num_qgrps; 3524 3525 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3526 ICE_AQC_Q_DIS_TIMEOUT_M); 3527 3528 switch (rst_src) { 3529 case ICE_VM_RESET: 3530 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3531 cmd->vmvf_and_timeout |= 3532 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3533 break; 3534 case ICE_VF_RESET: 3535 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 3536 /* In this case, FW expects vmvf_num to be absolute VF ID */ 3537 cmd->vmvf_and_timeout |= 3538 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 3539 ICE_AQC_Q_DIS_VMVF_NUM_M); 3540 break; 3541 case ICE_NO_RESET: 3542 default: 3543 break; 3544 } 3545 3546 /* flush pipe on time out */ 3547 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3548 /* If no queue group info, we are in a reset flow. Issue the AQ */ 3549 if (!qg_list) 3550 goto do_aq; 3551 3552 /* set RD bit to indicate that command buffer is provided by the driver 3553 * and it needs to be read by the firmware 3554 */ 3555 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3556 3557 for (i = 0, item = qg_list; i < num_qgrps; i++) { 3558 u16 item_size = struct_size(item, q_id, item->num_qs); 3559 3560 /* If the num of queues is even, add 2 bytes of padding */ 3561 if ((item->num_qs % 2) == 0) 3562 item_size += 2; 3563 3564 sz += item_size; 3565 3566 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 3567 } 3568 3569 if (buf_size != sz) 3570 return ICE_ERR_PARAM; 3571 3572 do_aq: 3573 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3574 if (status) { 3575 if (!qg_list) 3576 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 3577 vmvf_num, hw->adminq.sq_last_status); 3578 else 3579 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 3580 le16_to_cpu(qg_list[0].q_id[0]), 3581 hw->adminq.sq_last_status); 3582 } 3583 return status; 3584 } 3585 3586 /* End of FW Admin Queue command wrappers */ 3587 3588 /** 3589 * ice_write_byte - write a byte to a packed context structure 3590 * @src_ctx: the context structure to read from 3591 * @dest_ctx: the context to be written to 3592 * @ce_info: a description of the struct to be filled 3593 */ 3594 static void 3595 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3596 { 3597 u8 src_byte, dest_byte, mask; 3598 u8 *from, *dest; 3599 u16 shift_width; 3600 3601 /* copy from the next struct field */ 3602 from = src_ctx + ce_info->offset; 3603 3604 /* prepare the bits and mask */ 3605 shift_width = ce_info->lsb % 8; 3606 mask = (u8)(BIT(ce_info->width) - 1); 3607 3608 src_byte = *from; 3609 src_byte &= mask; 3610 3611 /* shift to correct alignment */ 3612 mask <<= shift_width; 3613 src_byte <<= shift_width; 3614 3615 /* get the current bits from the target bit string */ 3616 dest = dest_ctx + (ce_info->lsb / 8); 3617 3618 memcpy(&dest_byte, dest, sizeof(dest_byte)); 3619 3620 dest_byte &= ~mask; /* get the bits not changing */ 3621 dest_byte |= src_byte; /* add in the new bits */ 3622 3623 /* put it all back */ 3624 memcpy(dest, &dest_byte, sizeof(dest_byte)); 3625 } 3626 3627 /** 3628 * ice_write_word - write a word to a packed context structure 3629 * @src_ctx: the context structure to read from 3630 * @dest_ctx: the context to be written to 3631 * @ce_info: a description of the struct to be filled 3632 */ 3633 static void 3634 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3635 { 3636 u16 src_word, mask; 3637 __le16 dest_word; 3638 u8 *from, *dest; 3639 u16 shift_width; 3640 3641 /* copy from the next struct field */ 3642 from = src_ctx + ce_info->offset; 3643 3644 /* prepare the bits and mask */ 3645 shift_width = ce_info->lsb % 8; 3646 mask = BIT(ce_info->width) - 1; 3647 3648 /* don't swizzle the bits until after the mask because the mask bits 3649 * will be in a different bit position on big endian machines 3650 */ 3651 src_word = *(u16 *)from; 3652 src_word &= mask; 3653 3654 /* shift to correct alignment */ 3655 mask <<= shift_width; 3656 src_word <<= shift_width; 3657 3658 /* get the current bits from the target bit string */ 3659 dest = dest_ctx + (ce_info->lsb / 8); 3660 3661 memcpy(&dest_word, dest, sizeof(dest_word)); 3662 3663 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 3664 dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 3665 3666 /* put it all back */ 3667 memcpy(dest, &dest_word, sizeof(dest_word)); 3668 } 3669 3670 /** 3671 * ice_write_dword - write a dword to a packed context structure 3672 * @src_ctx: the context structure to read from 3673 * @dest_ctx: the context to be written to 3674 * @ce_info: a description of the struct to be filled 3675 */ 3676 static void 3677 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3678 { 3679 u32 src_dword, mask; 3680 __le32 dest_dword; 3681 u8 *from, *dest; 3682 u16 shift_width; 3683 3684 /* copy from the next struct field */ 3685 from = src_ctx + ce_info->offset; 3686 3687 /* prepare the bits and mask */ 3688 shift_width = ce_info->lsb % 8; 3689 3690 /* if the field width is exactly 32 on an x86 machine, then the shift 3691 * operation will not work because the SHL instructions count is masked 3692 * to 5 bits so the shift will do nothing 3693 */ 3694 if (ce_info->width < 32) 3695 mask = BIT(ce_info->width) - 1; 3696 else 3697 mask = (u32)~0; 3698 3699 /* don't swizzle the bits until after the mask because the mask bits 3700 * will be in a different bit position on big endian machines 3701 */ 3702 src_dword = *(u32 *)from; 3703 src_dword &= mask; 3704 3705 /* shift to correct alignment */ 3706 mask <<= shift_width; 3707 src_dword <<= shift_width; 3708 3709 /* get the current bits from the target bit string */ 3710 dest = dest_ctx + (ce_info->lsb / 8); 3711 3712 memcpy(&dest_dword, dest, sizeof(dest_dword)); 3713 3714 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 3715 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 3716 3717 /* put it all back */ 3718 memcpy(dest, &dest_dword, sizeof(dest_dword)); 3719 } 3720 3721 /** 3722 * ice_write_qword - write a qword to a packed context structure 3723 * @src_ctx: the context structure to read from 3724 * @dest_ctx: the context to be written to 3725 * @ce_info: a description of the struct to be filled 3726 */ 3727 static void 3728 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3729 { 3730 u64 src_qword, mask; 3731 __le64 dest_qword; 3732 u8 *from, *dest; 3733 u16 shift_width; 3734 3735 /* copy from the next struct field */ 3736 from = src_ctx + ce_info->offset; 3737 3738 /* prepare the bits and mask */ 3739 shift_width = ce_info->lsb % 8; 3740 3741 /* if the field width is exactly 64 on an x86 machine, then the shift 3742 * operation will not work because the SHL instructions count is masked 3743 * to 6 bits so the shift will do nothing 3744 */ 3745 if (ce_info->width < 64) 3746 mask = BIT_ULL(ce_info->width) - 1; 3747 else 3748 mask = (u64)~0; 3749 3750 /* don't swizzle the bits until after the mask because the mask bits 3751 * will be in a different bit position on big endian machines 3752 */ 3753 src_qword = *(u64 *)from; 3754 src_qword &= mask; 3755 3756 /* shift to correct alignment */ 3757 mask <<= shift_width; 3758 src_qword <<= shift_width; 3759 3760 /* get the current bits from the target bit string */ 3761 dest = dest_ctx + (ce_info->lsb / 8); 3762 3763 memcpy(&dest_qword, dest, sizeof(dest_qword)); 3764 3765 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 3766 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 3767 3768 /* put it all back */ 3769 memcpy(dest, &dest_qword, sizeof(dest_qword)); 3770 } 3771 3772 /** 3773 * ice_set_ctx - set context bits in packed structure 3774 * @hw: pointer to the hardware structure 3775 * @src_ctx: pointer to a generic non-packed context structure 3776 * @dest_ctx: pointer to memory for the packed structure 3777 * @ce_info: a description of the structure to be transformed 3778 */ 3779 enum ice_status 3780 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 3781 const struct ice_ctx_ele *ce_info) 3782 { 3783 int f; 3784 3785 for (f = 0; ce_info[f].width; f++) { 3786 /* We have to deal with each element of the FW response 3787 * using the correct size so that we are correct regardless 3788 * of the endianness of the machine. 3789 */ 3790 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 3791 ice_debug(hw, ICE_DBG_QCTX, 3792 "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 3793 f, ce_info[f].width, ce_info[f].size_of); 3794 continue; 3795 } 3796 switch (ce_info[f].size_of) { 3797 case sizeof(u8): 3798 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 3799 break; 3800 case sizeof(u16): 3801 ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 3802 break; 3803 case sizeof(u32): 3804 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 3805 break; 3806 case sizeof(u64): 3807 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 3808 break; 3809 default: 3810 return ICE_ERR_INVAL_SIZE; 3811 } 3812 } 3813 3814 return 0; 3815 } 3816 3817 /** 3818 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 3819 * @hw: pointer to the HW struct 3820 * @vsi_handle: software VSI handle 3821 * @tc: TC number 3822 * @q_handle: software queue handle 3823 */ 3824 struct ice_q_ctx * 3825 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 3826 { 3827 struct ice_vsi_ctx *vsi; 3828 struct ice_q_ctx *q_ctx; 3829 3830 vsi = ice_get_vsi_ctx(hw, vsi_handle); 3831 if (!vsi) 3832 return NULL; 3833 if (q_handle >= vsi->num_lan_q_entries[tc]) 3834 return NULL; 3835 if (!vsi->lan_q_ctx[tc]) 3836 return NULL; 3837 q_ctx = vsi->lan_q_ctx[tc]; 3838 return &q_ctx[q_handle]; 3839 } 3840 3841 /** 3842 * ice_ena_vsi_txq 3843 * @pi: port information structure 3844 * @vsi_handle: software VSI handle 3845 * @tc: TC number 3846 * @q_handle: software queue handle 3847 * @num_qgrps: Number of added queue groups 3848 * @buf: list of queue groups to be added 3849 * @buf_size: size of buffer for indirect command 3850 * @cd: pointer to command details structure or NULL 3851 * 3852 * This function adds one LAN queue 3853 */ 3854 enum ice_status 3855 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 3856 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 3857 struct ice_sq_cd *cd) 3858 { 3859 struct ice_aqc_txsched_elem_data node = { 0 }; 3860 struct ice_sched_node *parent; 3861 struct ice_q_ctx *q_ctx; 3862 enum ice_status status; 3863 struct ice_hw *hw; 3864 3865 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3866 return ICE_ERR_CFG; 3867 3868 if (num_qgrps > 1 || buf->num_txqs > 1) 3869 return ICE_ERR_MAX_LIMIT; 3870 3871 hw = pi->hw; 3872 3873 if (!ice_is_vsi_valid(hw, vsi_handle)) 3874 return ICE_ERR_PARAM; 3875 3876 mutex_lock(&pi->sched_lock); 3877 3878 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 3879 if (!q_ctx) { 3880 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 3881 q_handle); 3882 status = ICE_ERR_PARAM; 3883 goto ena_txq_exit; 3884 } 3885 3886 /* find a parent node */ 3887 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 3888 ICE_SCHED_NODE_OWNER_LAN); 3889 if (!parent) { 3890 status = ICE_ERR_PARAM; 3891 goto ena_txq_exit; 3892 } 3893 3894 buf->parent_teid = parent->info.node_teid; 3895 node.parent_teid = parent->info.node_teid; 3896 /* Mark that the values in the "generic" section as valid. The default 3897 * value in the "generic" section is zero. This means that : 3898 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 3899 * - 0 priority among siblings, indicated by Bit 1-3. 3900 * - WFQ, indicated by Bit 4. 3901 * - 0 Adjustment value is used in PSM credit update flow, indicated by 3902 * Bit 5-6. 3903 * - Bit 7 is reserved. 3904 * Without setting the generic section as valid in valid_sections, the 3905 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 3906 */ 3907 buf->txqs[0].info.valid_sections = 3908 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 3909 ICE_AQC_ELEM_VALID_EIR; 3910 buf->txqs[0].info.generic = 0; 3911 buf->txqs[0].info.cir_bw.bw_profile_idx = 3912 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 3913 buf->txqs[0].info.cir_bw.bw_alloc = 3914 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 3915 buf->txqs[0].info.eir_bw.bw_profile_idx = 3916 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 3917 buf->txqs[0].info.eir_bw.bw_alloc = 3918 cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 3919 3920 /* add the LAN queue */ 3921 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 3922 if (status) { 3923 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 3924 le16_to_cpu(buf->txqs[0].txq_id), 3925 hw->adminq.sq_last_status); 3926 goto ena_txq_exit; 3927 } 3928 3929 node.node_teid = buf->txqs[0].q_teid; 3930 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 3931 q_ctx->q_handle = q_handle; 3932 q_ctx->q_teid = le32_to_cpu(node.node_teid); 3933 3934 /* add a leaf node into scheduler tree queue layer */ 3935 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 3936 if (!status) 3937 status = ice_sched_replay_q_bw(pi, q_ctx); 3938 3939 ena_txq_exit: 3940 mutex_unlock(&pi->sched_lock); 3941 return status; 3942 } 3943 3944 /** 3945 * ice_dis_vsi_txq 3946 * @pi: port information structure 3947 * @vsi_handle: software VSI handle 3948 * @tc: TC number 3949 * @num_queues: number of queues 3950 * @q_handles: pointer to software queue handle array 3951 * @q_ids: pointer to the q_id array 3952 * @q_teids: pointer to queue node teids 3953 * @rst_src: if called due to reset, specifies the reset source 3954 * @vmvf_num: the relative VM or VF number that is undergoing the reset 3955 * @cd: pointer to command details structure or NULL 3956 * 3957 * This function removes queues and their corresponding nodes in SW DB 3958 */ 3959 enum ice_status 3960 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 3961 u16 *q_handles, u16 *q_ids, u32 *q_teids, 3962 enum ice_disq_rst_src rst_src, u16 vmvf_num, 3963 struct ice_sq_cd *cd) 3964 { 3965 enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 3966 struct ice_aqc_dis_txq_item *qg_list; 3967 struct ice_q_ctx *q_ctx; 3968 struct ice_hw *hw; 3969 u16 i, buf_size; 3970 3971 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3972 return ICE_ERR_CFG; 3973 3974 hw = pi->hw; 3975 3976 if (!num_queues) { 3977 /* if queue is disabled already yet the disable queue command 3978 * has to be sent to complete the VF reset, then call 3979 * ice_aq_dis_lan_txq without any queue information 3980 */ 3981 if (rst_src) 3982 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 3983 vmvf_num, NULL); 3984 return ICE_ERR_CFG; 3985 } 3986 3987 buf_size = struct_size(qg_list, q_id, 1); 3988 qg_list = kzalloc(buf_size, GFP_KERNEL); 3989 if (!qg_list) 3990 return ICE_ERR_NO_MEMORY; 3991 3992 mutex_lock(&pi->sched_lock); 3993 3994 for (i = 0; i < num_queues; i++) { 3995 struct ice_sched_node *node; 3996 3997 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 3998 if (!node) 3999 continue; 4000 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 4001 if (!q_ctx) { 4002 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 4003 q_handles[i]); 4004 continue; 4005 } 4006 if (q_ctx->q_handle != q_handles[i]) { 4007 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 4008 q_ctx->q_handle, q_handles[i]); 4009 continue; 4010 } 4011 qg_list->parent_teid = node->info.parent_teid; 4012 qg_list->num_qs = 1; 4013 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 4014 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 4015 vmvf_num, cd); 4016 4017 if (status) 4018 break; 4019 ice_free_sched_node(pi, node); 4020 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 4021 } 4022 mutex_unlock(&pi->sched_lock); 4023 kfree(qg_list); 4024 return status; 4025 } 4026 4027 /** 4028 * ice_cfg_vsi_qs - configure the new/existing VSI queues 4029 * @pi: port information structure 4030 * @vsi_handle: software VSI handle 4031 * @tc_bitmap: TC bitmap 4032 * @maxqs: max queues array per TC 4033 * @owner: LAN or RDMA 4034 * 4035 * This function adds/updates the VSI queues per TC. 4036 */ 4037 static enum ice_status 4038 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4039 u16 *maxqs, u8 owner) 4040 { 4041 enum ice_status status = 0; 4042 u8 i; 4043 4044 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 4045 return ICE_ERR_CFG; 4046 4047 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4048 return ICE_ERR_PARAM; 4049 4050 mutex_lock(&pi->sched_lock); 4051 4052 ice_for_each_traffic_class(i) { 4053 /* configuration is possible only if TC node is present */ 4054 if (!ice_sched_get_tc_node(pi, i)) 4055 continue; 4056 4057 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 4058 ice_is_tc_ena(tc_bitmap, i)); 4059 if (status) 4060 break; 4061 } 4062 4063 mutex_unlock(&pi->sched_lock); 4064 return status; 4065 } 4066 4067 /** 4068 * ice_cfg_vsi_lan - configure VSI LAN queues 4069 * @pi: port information structure 4070 * @vsi_handle: software VSI handle 4071 * @tc_bitmap: TC bitmap 4072 * @max_lanqs: max LAN queues array per TC 4073 * 4074 * This function adds/updates the VSI LAN queues per TC. 4075 */ 4076 enum ice_status 4077 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 4078 u16 *max_lanqs) 4079 { 4080 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 4081 ICE_SCHED_NODE_OWNER_LAN); 4082 } 4083 4084 /** 4085 * ice_replay_pre_init - replay pre initialization 4086 * @hw: pointer to the HW struct 4087 * 4088 * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4089 */ 4090 static enum ice_status ice_replay_pre_init(struct ice_hw *hw) 4091 { 4092 struct ice_switch_info *sw = hw->switch_info; 4093 u8 i; 4094 4095 /* Delete old entries from replay filter list head if there is any */ 4096 ice_rm_all_sw_replay_rule_info(hw); 4097 /* In start of replay, move entries into replay_rules list, it 4098 * will allow adding rules entries back to filt_rules list, 4099 * which is operational list. 4100 */ 4101 for (i = 0; i < ICE_SW_LKUP_LAST; i++) 4102 list_replace_init(&sw->recp_list[i].filt_rules, 4103 &sw->recp_list[i].filt_replay_rules); 4104 4105 return 0; 4106 } 4107 4108 /** 4109 * ice_replay_vsi - replay VSI configuration 4110 * @hw: pointer to the HW struct 4111 * @vsi_handle: driver VSI handle 4112 * 4113 * Restore all VSI configuration after reset. It is required to call this 4114 * function with main VSI first. 4115 */ 4116 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4117 { 4118 enum ice_status status; 4119 4120 if (!ice_is_vsi_valid(hw, vsi_handle)) 4121 return ICE_ERR_PARAM; 4122 4123 /* Replay pre-initialization if there is any */ 4124 if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 4125 status = ice_replay_pre_init(hw); 4126 if (status) 4127 return status; 4128 } 4129 /* Replay per VSI all RSS configurations */ 4130 status = ice_replay_rss_cfg(hw, vsi_handle); 4131 if (status) 4132 return status; 4133 /* Replay per VSI all filters */ 4134 status = ice_replay_vsi_all_fltr(hw, vsi_handle); 4135 return status; 4136 } 4137 4138 /** 4139 * ice_replay_post - post replay configuration cleanup 4140 * @hw: pointer to the HW struct 4141 * 4142 * Post replay cleanup. 4143 */ 4144 void ice_replay_post(struct ice_hw *hw) 4145 { 4146 /* Delete old entries from replay filter list head */ 4147 ice_rm_all_sw_replay_rule_info(hw); 4148 } 4149 4150 /** 4151 * ice_stat_update40 - read 40 bit stat from the chip and update stat values 4152 * @hw: ptr to the hardware info 4153 * @reg: offset of 64 bit HW register to read from 4154 * @prev_stat_loaded: bool to specify if previous stats are loaded 4155 * @prev_stat: ptr to previous loaded stat value 4156 * @cur_stat: ptr to current stat value 4157 */ 4158 void 4159 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4160 u64 *prev_stat, u64 *cur_stat) 4161 { 4162 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 4163 4164 /* device stats are not reset at PFR, they likely will not be zeroed 4165 * when the driver starts. Thus, save the value from the first read 4166 * without adding to the statistic value so that we report stats which 4167 * count up from zero. 4168 */ 4169 if (!prev_stat_loaded) { 4170 *prev_stat = new_data; 4171 return; 4172 } 4173 4174 /* Calculate the difference between the new and old values, and then 4175 * add it to the software stat value. 4176 */ 4177 if (new_data >= *prev_stat) 4178 *cur_stat += new_data - *prev_stat; 4179 else 4180 /* to manage the potential roll-over */ 4181 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 4182 4183 /* Update the previously stored value to prepare for next read */ 4184 *prev_stat = new_data; 4185 } 4186 4187 /** 4188 * ice_stat_update32 - read 32 bit stat from the chip and update stat values 4189 * @hw: ptr to the hardware info 4190 * @reg: offset of HW register to read from 4191 * @prev_stat_loaded: bool to specify if previous stats are loaded 4192 * @prev_stat: ptr to previous loaded stat value 4193 * @cur_stat: ptr to current stat value 4194 */ 4195 void 4196 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 4197 u64 *prev_stat, u64 *cur_stat) 4198 { 4199 u32 new_data; 4200 4201 new_data = rd32(hw, reg); 4202 4203 /* device stats are not reset at PFR, they likely will not be zeroed 4204 * when the driver starts. Thus, save the value from the first read 4205 * without adding to the statistic value so that we report stats which 4206 * count up from zero. 4207 */ 4208 if (!prev_stat_loaded) { 4209 *prev_stat = new_data; 4210 return; 4211 } 4212 4213 /* Calculate the difference between the new and old values, and then 4214 * add it to the software stat value. 4215 */ 4216 if (new_data >= *prev_stat) 4217 *cur_stat += new_data - *prev_stat; 4218 else 4219 /* to manage the potential roll-over */ 4220 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 4221 4222 /* Update the previously stored value to prepare for next read */ 4223 *prev_stat = new_data; 4224 } 4225 4226 /** 4227 * ice_sched_query_elem - query element information from HW 4228 * @hw: pointer to the HW struct 4229 * @node_teid: node TEID to be queried 4230 * @buf: buffer to element information 4231 * 4232 * This function queries HW element information 4233 */ 4234 enum ice_status 4235 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4236 struct ice_aqc_txsched_elem_data *buf) 4237 { 4238 u16 buf_size, num_elem_ret = 0; 4239 enum ice_status status; 4240 4241 buf_size = sizeof(*buf); 4242 memset(buf, 0, buf_size); 4243 buf->node_teid = cpu_to_le32(node_teid); 4244 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 4245 NULL); 4246 if (status || num_elem_ret != 1) 4247 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 4248 return status; 4249 } 4250 4251 /** 4252 * ice_fw_supports_link_override 4253 * @hw: pointer to the hardware structure 4254 * 4255 * Checks if the firmware supports link override 4256 */ 4257 bool ice_fw_supports_link_override(struct ice_hw *hw) 4258 { 4259 /* Currently, only supported for E810 devices */ 4260 if (hw->mac_type != ICE_MAC_E810) 4261 return false; 4262 4263 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 4264 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 4265 return true; 4266 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 4267 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 4268 return true; 4269 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 4270 return true; 4271 } 4272 4273 return false; 4274 } 4275 4276 /** 4277 * ice_get_link_default_override 4278 * @ldo: pointer to the link default override struct 4279 * @pi: pointer to the port info struct 4280 * 4281 * Gets the link default override for a port 4282 */ 4283 enum ice_status 4284 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 4285 struct ice_port_info *pi) 4286 { 4287 u16 i, tlv, tlv_len, tlv_start, buf, offset; 4288 struct ice_hw *hw = pi->hw; 4289 enum ice_status status; 4290 4291 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 4292 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 4293 if (status) { 4294 ice_debug(hw, ICE_DBG_INIT, 4295 "Failed to read link override TLV.\n"); 4296 return status; 4297 } 4298 4299 /* Each port has its own config; calculate for our port */ 4300 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 4301 ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 4302 4303 /* link options first */ 4304 status = ice_read_sr_word(hw, tlv_start, &buf); 4305 if (status) { 4306 ice_debug(hw, ICE_DBG_INIT, 4307 "Failed to read override link options.\n"); 4308 return status; 4309 } 4310 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 4311 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 4312 ICE_LINK_OVERRIDE_PHY_CFG_S; 4313 4314 /* link PHY config */ 4315 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 4316 status = ice_read_sr_word(hw, offset, &buf); 4317 if (status) { 4318 ice_debug(hw, ICE_DBG_INIT, 4319 "Failed to read override phy config.\n"); 4320 return status; 4321 } 4322 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 4323 4324 /* PHY types low */ 4325 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 4326 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4327 status = ice_read_sr_word(hw, (offset + i), &buf); 4328 if (status) { 4329 ice_debug(hw, ICE_DBG_INIT, 4330 "Failed to read override link options.\n"); 4331 return status; 4332 } 4333 /* shift 16 bits at a time to fill 64 bits */ 4334 ldo->phy_type_low |= ((u64)buf << (i * 16)); 4335 } 4336 4337 /* PHY types high */ 4338 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 4339 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 4340 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4341 status = ice_read_sr_word(hw, (offset + i), &buf); 4342 if (status) { 4343 ice_debug(hw, ICE_DBG_INIT, 4344 "Failed to read override link options.\n"); 4345 return status; 4346 } 4347 /* shift 16 bits at a time to fill 64 bits */ 4348 ldo->phy_type_high |= ((u64)buf << (i * 16)); 4349 } 4350 4351 return status; 4352 } 4353 4354 /** 4355 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 4356 * @caps: get PHY capability data 4357 */ 4358 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 4359 { 4360 if (caps->caps & ICE_AQC_PHY_AN_MODE || 4361 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 4362 ICE_AQC_PHY_AN_EN_CLAUSE73 | 4363 ICE_AQC_PHY_AN_EN_CLAUSE37)) 4364 return true; 4365 4366 return false; 4367 } 4368 4369 /** 4370 * ice_aq_set_lldp_mib - Set the LLDP MIB 4371 * @hw: pointer to the HW struct 4372 * @mib_type: Local, Remote or both Local and Remote MIBs 4373 * @buf: pointer to the caller-supplied buffer to store the MIB block 4374 * @buf_size: size of the buffer (in bytes) 4375 * @cd: pointer to command details structure or NULL 4376 * 4377 * Set the LLDP MIB. (0x0A08) 4378 */ 4379 enum ice_status 4380 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 4381 struct ice_sq_cd *cd) 4382 { 4383 struct ice_aqc_lldp_set_local_mib *cmd; 4384 struct ice_aq_desc desc; 4385 4386 cmd = &desc.params.lldp_set_mib; 4387 4388 if (buf_size == 0 || !buf) 4389 return ICE_ERR_PARAM; 4390 4391 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 4392 4393 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 4394 desc.datalen = cpu_to_le16(buf_size); 4395 4396 cmd->type = mib_type; 4397 cmd->length = cpu_to_le16(buf_size); 4398 4399 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 4400 } 4401