17ec59eeaSAnirudh Venkataramanan // SPDX-License-Identifier: GPL-2.0 27ec59eeaSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 37ec59eeaSAnirudh Venkataramanan 47ec59eeaSAnirudh Venkataramanan #include "ice_common.h" 59c20346bSAnirudh Venkataramanan #include "ice_sched.h" 67ec59eeaSAnirudh Venkataramanan #include "ice_adminq_cmd.h" 7c90ed40cSTony Nguyen #include "ice_flow.h" 87ec59eeaSAnirudh Venkataramanan 971245072SJacob Keller #define ICE_PF_RESET_WAIT_COUNT 300 10f31e4b6fSAnirudh Venkataramanan 11f31e4b6fSAnirudh Venkataramanan /** 12f31e4b6fSAnirudh Venkataramanan * ice_set_mac_type - Sets MAC type 13f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the HW structure 14f31e4b6fSAnirudh Venkataramanan * 15f31e4b6fSAnirudh Venkataramanan * This function sets the MAC type of the adapter based on the 16f9867df6SAnirudh Venkataramanan * vendor ID and device ID stored in the HW structure. 17f31e4b6fSAnirudh Venkataramanan */ 18f31e4b6fSAnirudh Venkataramanan static enum ice_status ice_set_mac_type(struct ice_hw *hw) 19f31e4b6fSAnirudh Venkataramanan { 20f31e4b6fSAnirudh Venkataramanan if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 21f31e4b6fSAnirudh Venkataramanan return ICE_ERR_DEVICE_NOT_SUPPORTED; 22f31e4b6fSAnirudh Venkataramanan 23ea78ce4dSPaul Greenwalt switch (hw->device_id) { 24ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E810C_BACKPLANE: 25ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E810C_QSFP: 26ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E810C_SFP: 27ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E810_XXV_SFP: 28ea78ce4dSPaul Greenwalt hw->mac_type = ICE_MAC_E810; 29ea78ce4dSPaul Greenwalt break; 30ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_10G_BASE_T: 31ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_BACKPLANE: 32ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_QSFP: 33ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_SFP: 34ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_SGMII: 35ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_10G_BASE_T: 36ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_BACKPLANE: 37ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_QSFP: 38ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_SFP: 39ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_SGMII: 40ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822L_10G_BASE_T: 41ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822L_BACKPLANE: 42ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822L_SFP: 43ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822L_SGMII: 44ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_10G_BASE_T: 45ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_1GBE: 46ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_BACKPLANE: 47ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_QSFP: 48ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_SFP: 49f31e4b6fSAnirudh Venkataramanan hw->mac_type = ICE_MAC_GENERIC; 50ea78ce4dSPaul Greenwalt break; 51ea78ce4dSPaul Greenwalt default: 52ea78ce4dSPaul Greenwalt hw->mac_type = ICE_MAC_UNKNOWN; 53ea78ce4dSPaul Greenwalt break; 54ea78ce4dSPaul Greenwalt } 55ea78ce4dSPaul Greenwalt 56ea78ce4dSPaul Greenwalt ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 57f31e4b6fSAnirudh Venkataramanan return 0; 58f31e4b6fSAnirudh Venkataramanan } 59f31e4b6fSAnirudh Venkataramanan 60f31e4b6fSAnirudh Venkataramanan /** 61f31e4b6fSAnirudh Venkataramanan * ice_clear_pf_cfg - Clear PF configuration 62f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure 633968540bSAnirudh Venkataramanan * 643968540bSAnirudh Venkataramanan * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 653968540bSAnirudh Venkataramanan * configuration, flow director filters, etc.). 66f31e4b6fSAnirudh Venkataramanan */ 67f31e4b6fSAnirudh Venkataramanan enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 68f31e4b6fSAnirudh Venkataramanan { 69f31e4b6fSAnirudh Venkataramanan struct ice_aq_desc desc; 70f31e4b6fSAnirudh Venkataramanan 71f31e4b6fSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 72f31e4b6fSAnirudh Venkataramanan 73f31e4b6fSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 74f31e4b6fSAnirudh Venkataramanan } 75f31e4b6fSAnirudh Venkataramanan 76f31e4b6fSAnirudh Venkataramanan /** 77dc49c772SAnirudh Venkataramanan * ice_aq_manage_mac_read - manage MAC address read command 78f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 79dc49c772SAnirudh Venkataramanan * @buf: a virtual buffer to hold the manage MAC read response 80dc49c772SAnirudh Venkataramanan * @buf_size: Size of the virtual buffer 81dc49c772SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 82dc49c772SAnirudh Venkataramanan * 83dc49c772SAnirudh Venkataramanan * This function is used to return per PF station MAC address (0x0107). 84dc49c772SAnirudh Venkataramanan * NOTE: Upon successful completion of this command, MAC address information 85dc49c772SAnirudh Venkataramanan * is returned in user specified buffer. Please interpret user specified 86dc49c772SAnirudh Venkataramanan * buffer as "manage_mac_read" response. 87dc49c772SAnirudh Venkataramanan * Response such as various MAC addresses are stored in HW struct (port.mac) 8881aed647SJacob Keller * ice_discover_dev_caps is expected to be called before this function is 8981aed647SJacob Keller * called. 90dc49c772SAnirudh Venkataramanan */ 91dc49c772SAnirudh Venkataramanan static enum ice_status 92dc49c772SAnirudh Venkataramanan ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 93dc49c772SAnirudh Venkataramanan struct ice_sq_cd *cd) 94dc49c772SAnirudh Venkataramanan { 95dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read_resp *resp; 96dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read *cmd; 97dc49c772SAnirudh Venkataramanan struct ice_aq_desc desc; 98dc49c772SAnirudh Venkataramanan enum ice_status status; 99dc49c772SAnirudh Venkataramanan u16 flags; 100d6fef10cSMd Fahad Iqbal Polash u8 i; 101dc49c772SAnirudh Venkataramanan 102dc49c772SAnirudh Venkataramanan cmd = &desc.params.mac_read; 103dc49c772SAnirudh Venkataramanan 104dc49c772SAnirudh Venkataramanan if (buf_size < sizeof(*resp)) 105dc49c772SAnirudh Venkataramanan return ICE_ERR_BUF_TOO_SHORT; 106dc49c772SAnirudh Venkataramanan 107dc49c772SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 108dc49c772SAnirudh Venkataramanan 109dc49c772SAnirudh Venkataramanan status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 110dc49c772SAnirudh Venkataramanan if (status) 111dc49c772SAnirudh Venkataramanan return status; 112dc49c772SAnirudh Venkataramanan 113dc49c772SAnirudh Venkataramanan resp = (struct ice_aqc_manage_mac_read_resp *)buf; 114dc49c772SAnirudh Venkataramanan flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 115dc49c772SAnirudh Venkataramanan 116dc49c772SAnirudh Venkataramanan if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 117dc49c772SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 118dc49c772SAnirudh Venkataramanan return ICE_ERR_CFG; 119dc49c772SAnirudh Venkataramanan } 120dc49c772SAnirudh Venkataramanan 121d6fef10cSMd Fahad Iqbal Polash /* A single port can report up to two (LAN and WoL) addresses */ 122d6fef10cSMd Fahad Iqbal Polash for (i = 0; i < cmd->num_addr; i++) 123d6fef10cSMd Fahad Iqbal Polash if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 124d6fef10cSMd Fahad Iqbal Polash ether_addr_copy(hw->port_info->mac.lan_addr, 125d6fef10cSMd Fahad Iqbal Polash resp[i].mac_addr); 126d6fef10cSMd Fahad Iqbal Polash ether_addr_copy(hw->port_info->mac.perm_addr, 127d6fef10cSMd Fahad Iqbal Polash resp[i].mac_addr); 128d6fef10cSMd Fahad Iqbal Polash break; 129d6fef10cSMd Fahad Iqbal Polash } 130d6fef10cSMd Fahad Iqbal Polash 131dc49c772SAnirudh Venkataramanan return 0; 132dc49c772SAnirudh Venkataramanan } 133dc49c772SAnirudh Venkataramanan 134dc49c772SAnirudh Venkataramanan /** 135dc49c772SAnirudh Venkataramanan * ice_aq_get_phy_caps - returns PHY capabilities 136dc49c772SAnirudh Venkataramanan * @pi: port information structure 137dc49c772SAnirudh Venkataramanan * @qual_mods: report qualified modules 138dc49c772SAnirudh Venkataramanan * @report_mode: report mode capabilities 139dc49c772SAnirudh Venkataramanan * @pcaps: structure for PHY capabilities to be filled 140dc49c772SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 141dc49c772SAnirudh Venkataramanan * 142dc49c772SAnirudh Venkataramanan * Returns the various PHY capabilities supported on the Port (0x0600) 143dc49c772SAnirudh Venkataramanan */ 14448cb27f2SChinh Cao enum ice_status 145dc49c772SAnirudh Venkataramanan ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 146dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps_data *pcaps, 147dc49c772SAnirudh Venkataramanan struct ice_sq_cd *cd) 148dc49c772SAnirudh Venkataramanan { 149dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps *cmd; 150dc49c772SAnirudh Venkataramanan u16 pcaps_size = sizeof(*pcaps); 151dc49c772SAnirudh Venkataramanan struct ice_aq_desc desc; 152dc49c772SAnirudh Venkataramanan enum ice_status status; 15355df52a0SPaul Greenwalt struct ice_hw *hw; 154dc49c772SAnirudh Venkataramanan 155dc49c772SAnirudh Venkataramanan cmd = &desc.params.get_phy; 156dc49c772SAnirudh Venkataramanan 157dc49c772SAnirudh Venkataramanan if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 158dc49c772SAnirudh Venkataramanan return ICE_ERR_PARAM; 15955df52a0SPaul Greenwalt hw = pi->hw; 160dc49c772SAnirudh Venkataramanan 161dc49c772SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 162dc49c772SAnirudh Venkataramanan 163dc49c772SAnirudh Venkataramanan if (qual_mods) 164dc49c772SAnirudh Venkataramanan cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 165dc49c772SAnirudh Venkataramanan 166dc49c772SAnirudh Venkataramanan cmd->param0 |= cpu_to_le16(report_mode); 16755df52a0SPaul Greenwalt status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 16855df52a0SPaul Greenwalt 16955df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 17055df52a0SPaul Greenwalt report_mode); 17155df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 17255df52a0SPaul Greenwalt (unsigned long long)le64_to_cpu(pcaps->phy_type_low)); 17355df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 17455df52a0SPaul Greenwalt (unsigned long long)le64_to_cpu(pcaps->phy_type_high)); 17555df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 176bdeff971SLev Faerman ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 177bdeff971SLev Faerman pcaps->low_power_ctrl_an); 17855df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 17955df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 18055df52a0SPaul Greenwalt pcaps->eeer_value); 18155df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 18255df52a0SPaul Greenwalt pcaps->link_fec_options); 18355df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 18455df52a0SPaul Greenwalt pcaps->module_compliance_enforcement); 18555df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 18655df52a0SPaul Greenwalt pcaps->extended_compliance_code); 18755df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 18855df52a0SPaul Greenwalt pcaps->module_type[0]); 18955df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 19055df52a0SPaul Greenwalt pcaps->module_type[1]); 19155df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 19255df52a0SPaul Greenwalt pcaps->module_type[2]); 193dc49c772SAnirudh Venkataramanan 194aef74145SAnirudh Venkataramanan if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) { 195dc49c772SAnirudh Venkataramanan pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 196aef74145SAnirudh Venkataramanan pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 197aef74145SAnirudh Venkataramanan } 198dc49c772SAnirudh Venkataramanan 199dc49c772SAnirudh Venkataramanan return status; 200dc49c772SAnirudh Venkataramanan } 201dc49c772SAnirudh Venkataramanan 202dc49c772SAnirudh Venkataramanan /** 2038ea1da59SPaul Greenwalt * ice_aq_get_link_topo_handle - get link topology node return status 2048ea1da59SPaul Greenwalt * @pi: port information structure 2058ea1da59SPaul Greenwalt * @node_type: requested node type 2068ea1da59SPaul Greenwalt * @cd: pointer to command details structure or NULL 2078ea1da59SPaul Greenwalt * 2088ea1da59SPaul Greenwalt * Get link topology node return status for specified node type (0x06E0) 2098ea1da59SPaul Greenwalt * 2108ea1da59SPaul Greenwalt * Node type cage can be used to determine if cage is present. If AQC 2118ea1da59SPaul Greenwalt * returns error (ENOENT), then no cage present. If no cage present, then 2128ea1da59SPaul Greenwalt * connection type is backplane or BASE-T. 2138ea1da59SPaul Greenwalt */ 2148ea1da59SPaul Greenwalt static enum ice_status 2158ea1da59SPaul Greenwalt ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 2168ea1da59SPaul Greenwalt struct ice_sq_cd *cd) 2178ea1da59SPaul Greenwalt { 2188ea1da59SPaul Greenwalt struct ice_aqc_get_link_topo *cmd; 2198ea1da59SPaul Greenwalt struct ice_aq_desc desc; 2208ea1da59SPaul Greenwalt 2218ea1da59SPaul Greenwalt cmd = &desc.params.get_link_topo; 2228ea1da59SPaul Greenwalt 2238ea1da59SPaul Greenwalt ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 2248ea1da59SPaul Greenwalt 2258ea1da59SPaul Greenwalt cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 2268ea1da59SPaul Greenwalt ICE_AQC_LINK_TOPO_NODE_CTX_S); 2278ea1da59SPaul Greenwalt 2288ea1da59SPaul Greenwalt /* set node type */ 2298ea1da59SPaul Greenwalt cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 2308ea1da59SPaul Greenwalt 2318ea1da59SPaul Greenwalt return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 2328ea1da59SPaul Greenwalt } 2338ea1da59SPaul Greenwalt 2348ea1da59SPaul Greenwalt /** 2358ea1da59SPaul Greenwalt * ice_is_media_cage_present 2368ea1da59SPaul Greenwalt * @pi: port information structure 2378ea1da59SPaul Greenwalt * 2388ea1da59SPaul Greenwalt * Returns true if media cage is present, else false. If no cage, then 2398ea1da59SPaul Greenwalt * media type is backplane or BASE-T. 2408ea1da59SPaul Greenwalt */ 2418ea1da59SPaul Greenwalt static bool ice_is_media_cage_present(struct ice_port_info *pi) 2428ea1da59SPaul Greenwalt { 2438ea1da59SPaul Greenwalt /* Node type cage can be used to determine if cage is present. If AQC 2448ea1da59SPaul Greenwalt * returns error (ENOENT), then no cage present. If no cage present then 2458ea1da59SPaul Greenwalt * connection type is backplane or BASE-T. 2468ea1da59SPaul Greenwalt */ 2478ea1da59SPaul Greenwalt return !ice_aq_get_link_topo_handle(pi, 2488ea1da59SPaul Greenwalt ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 2498ea1da59SPaul Greenwalt NULL); 2508ea1da59SPaul Greenwalt } 2518ea1da59SPaul Greenwalt 2528ea1da59SPaul Greenwalt /** 253dc49c772SAnirudh Venkataramanan * ice_get_media_type - Gets media type 254dc49c772SAnirudh Venkataramanan * @pi: port information structure 255dc49c772SAnirudh Venkataramanan */ 256dc49c772SAnirudh Venkataramanan static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 257dc49c772SAnirudh Venkataramanan { 258dc49c772SAnirudh Venkataramanan struct ice_link_status *hw_link_info; 259dc49c772SAnirudh Venkataramanan 260dc49c772SAnirudh Venkataramanan if (!pi) 261dc49c772SAnirudh Venkataramanan return ICE_MEDIA_UNKNOWN; 262dc49c772SAnirudh Venkataramanan 263dc49c772SAnirudh Venkataramanan hw_link_info = &pi->phy.link_info; 264aef74145SAnirudh Venkataramanan if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 265aef74145SAnirudh Venkataramanan /* If more than one media type is selected, report unknown */ 266aef74145SAnirudh Venkataramanan return ICE_MEDIA_UNKNOWN; 267dc49c772SAnirudh Venkataramanan 268dc49c772SAnirudh Venkataramanan if (hw_link_info->phy_type_low) { 269dc49c772SAnirudh Venkataramanan switch (hw_link_info->phy_type_low) { 270dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_1000BASE_SX: 271dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_1000BASE_LX: 272dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10GBASE_SR: 273dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10GBASE_LR: 274dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 275dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_SR: 276dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_LR: 277dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_40GBASE_SR4: 278dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_40GBASE_LR4: 279aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_SR2: 280aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_LR2: 281aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_SR: 282aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_FR: 283aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_LR: 284aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_SR4: 285aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_LR4: 286aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_SR2: 287aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_DR: 288dc49c772SAnirudh Venkataramanan return ICE_MEDIA_FIBER; 289dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100BASE_TX: 290dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_1000BASE_T: 291dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_2500BASE_T: 292dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_5GBASE_T: 293dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10GBASE_T: 294dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_T: 295dc49c772SAnirudh Venkataramanan return ICE_MEDIA_BASET; 296dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10G_SFI_DA: 297dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_CR: 298dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 299dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_CR1: 300dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_40GBASE_CR4: 301aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_CR2: 302aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_CP: 303aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CR4: 304aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 305aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CP2: 306dc49c772SAnirudh Venkataramanan return ICE_MEDIA_DA; 3078ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3088ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_40G_XLAUI: 3098ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_50G_LAUI2: 3108ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_50G_AUI2: 3118ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_50G_AUI1: 3128ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_100G_AUI4: 3138ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_100G_CAUI4: 3148ea1da59SPaul Greenwalt if (ice_is_media_cage_present(pi)) 3158ea1da59SPaul Greenwalt return ICE_MEDIA_DA; 3168ea1da59SPaul Greenwalt fallthrough; 317dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_1000BASE_KX: 318dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_2500BASE_KX: 319dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_2500BASE_X: 320dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_5GBASE_KR: 321dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 322dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_KR: 323dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_KR1: 324dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 325dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_40GBASE_KR4: 326aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 327aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_KR2: 328aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_KR4: 329aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 330aef74145SAnirudh Venkataramanan return ICE_MEDIA_BACKPLANE; 331aef74145SAnirudh Venkataramanan } 332aef74145SAnirudh Venkataramanan } else { 333aef74145SAnirudh Venkataramanan switch (hw_link_info->phy_type_high) { 3348ea1da59SPaul Greenwalt case ICE_PHY_TYPE_HIGH_100G_AUI2: 3358ea1da59SPaul Greenwalt case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3368ea1da59SPaul Greenwalt if (ice_is_media_cage_present(pi)) 3378ea1da59SPaul Greenwalt return ICE_MEDIA_DA; 3388ea1da59SPaul Greenwalt fallthrough; 339aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 340dc49c772SAnirudh Venkataramanan return ICE_MEDIA_BACKPLANE; 341dc49c772SAnirudh Venkataramanan } 342dc49c772SAnirudh Venkataramanan } 343dc49c772SAnirudh Venkataramanan return ICE_MEDIA_UNKNOWN; 344dc49c772SAnirudh Venkataramanan } 345dc49c772SAnirudh Venkataramanan 346dc49c772SAnirudh Venkataramanan /** 347dc49c772SAnirudh Venkataramanan * ice_aq_get_link_info 348dc49c772SAnirudh Venkataramanan * @pi: port information structure 349dc49c772SAnirudh Venkataramanan * @ena_lse: enable/disable LinkStatusEvent reporting 350dc49c772SAnirudh Venkataramanan * @link: pointer to link status structure - optional 351dc49c772SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 352dc49c772SAnirudh Venkataramanan * 353dc49c772SAnirudh Venkataramanan * Get Link Status (0x607). Returns the link status of the adapter. 354dc49c772SAnirudh Venkataramanan */ 355250c3b3eSBrett Creeley enum ice_status 356dc49c772SAnirudh Venkataramanan ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 357dc49c772SAnirudh Venkataramanan struct ice_link_status *link, struct ice_sq_cd *cd) 358dc49c772SAnirudh Venkataramanan { 359dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status_data link_data = { 0 }; 360dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status *resp; 361dc67039bSJesse Brandeburg struct ice_link_status *li_old, *li; 362dc49c772SAnirudh Venkataramanan enum ice_media_type *hw_media_type; 363dc49c772SAnirudh Venkataramanan struct ice_fc_info *hw_fc_info; 364dc49c772SAnirudh Venkataramanan bool tx_pause, rx_pause; 365dc49c772SAnirudh Venkataramanan struct ice_aq_desc desc; 366dc49c772SAnirudh Venkataramanan enum ice_status status; 367dc67039bSJesse Brandeburg struct ice_hw *hw; 368dc49c772SAnirudh Venkataramanan u16 cmd_flags; 369dc49c772SAnirudh Venkataramanan 370dc49c772SAnirudh Venkataramanan if (!pi) 371dc49c772SAnirudh Venkataramanan return ICE_ERR_PARAM; 372dc67039bSJesse Brandeburg hw = pi->hw; 373dc67039bSJesse Brandeburg li_old = &pi->phy.link_info_old; 374dc49c772SAnirudh Venkataramanan hw_media_type = &pi->phy.media_type; 375dc67039bSJesse Brandeburg li = &pi->phy.link_info; 376dc49c772SAnirudh Venkataramanan hw_fc_info = &pi->fc; 377dc49c772SAnirudh Venkataramanan 378dc49c772SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 379dc49c772SAnirudh Venkataramanan cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 380dc49c772SAnirudh Venkataramanan resp = &desc.params.get_link_status; 381dc49c772SAnirudh Venkataramanan resp->cmd_flags = cpu_to_le16(cmd_flags); 382dc49c772SAnirudh Venkataramanan resp->lport_num = pi->lport; 383dc49c772SAnirudh Venkataramanan 384dc67039bSJesse Brandeburg status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 385dc49c772SAnirudh Venkataramanan 386dc49c772SAnirudh Venkataramanan if (status) 387dc49c772SAnirudh Venkataramanan return status; 388dc49c772SAnirudh Venkataramanan 389dc49c772SAnirudh Venkataramanan /* save off old link status information */ 390dc67039bSJesse Brandeburg *li_old = *li; 391dc49c772SAnirudh Venkataramanan 392dc49c772SAnirudh Venkataramanan /* update current link status information */ 393dc67039bSJesse Brandeburg li->link_speed = le16_to_cpu(link_data.link_speed); 394dc67039bSJesse Brandeburg li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 395dc67039bSJesse Brandeburg li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 396dc49c772SAnirudh Venkataramanan *hw_media_type = ice_get_media_type(pi); 397dc67039bSJesse Brandeburg li->link_info = link_data.link_info; 398dc67039bSJesse Brandeburg li->an_info = link_data.an_info; 399dc67039bSJesse Brandeburg li->ext_info = link_data.ext_info; 400dc67039bSJesse Brandeburg li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 401dc67039bSJesse Brandeburg li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 402dc67039bSJesse Brandeburg li->topo_media_conflict = link_data.topo_media_conflict; 403dc67039bSJesse Brandeburg li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 404dc67039bSJesse Brandeburg ICE_AQ_CFG_PACING_TYPE_M); 405dc49c772SAnirudh Venkataramanan 406dc49c772SAnirudh Venkataramanan /* update fc info */ 407dc49c772SAnirudh Venkataramanan tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 408dc49c772SAnirudh Venkataramanan rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 409dc49c772SAnirudh Venkataramanan if (tx_pause && rx_pause) 410dc49c772SAnirudh Venkataramanan hw_fc_info->current_mode = ICE_FC_FULL; 411dc49c772SAnirudh Venkataramanan else if (tx_pause) 412dc49c772SAnirudh Venkataramanan hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 413dc49c772SAnirudh Venkataramanan else if (rx_pause) 414dc49c772SAnirudh Venkataramanan hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 415dc49c772SAnirudh Venkataramanan else 416dc49c772SAnirudh Venkataramanan hw_fc_info->current_mode = ICE_FC_NONE; 417dc49c772SAnirudh Venkataramanan 418dc67039bSJesse Brandeburg li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 419dc67039bSJesse Brandeburg 42055df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 421dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 422dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 423dc67039bSJesse Brandeburg (unsigned long long)li->phy_type_low); 424dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 425dc67039bSJesse Brandeburg (unsigned long long)li->phy_type_high); 426dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 427dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 428dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 429dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 43055df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 431dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 43255df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 43355df52a0SPaul Greenwalt li->max_frame_size); 434dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 435dc49c772SAnirudh Venkataramanan 436dc49c772SAnirudh Venkataramanan /* save link status information */ 437dc49c772SAnirudh Venkataramanan if (link) 438dc67039bSJesse Brandeburg *link = *li; 439dc49c772SAnirudh Venkataramanan 440dc49c772SAnirudh Venkataramanan /* flag cleared so calling functions don't call AQ again */ 441dc49c772SAnirudh Venkataramanan pi->phy.get_link_info = false; 442dc49c772SAnirudh Venkataramanan 4431b5c19c7SBruce Allan return 0; 444dc49c772SAnirudh Venkataramanan } 445dc49c772SAnirudh Venkataramanan 446dc49c772SAnirudh Venkataramanan /** 44742449105SAnirudh Venkataramanan * ice_fill_tx_timer_and_fc_thresh 44842449105SAnirudh Venkataramanan * @hw: pointer to the HW struct 44942449105SAnirudh Venkataramanan * @cmd: pointer to MAC cfg structure 45042449105SAnirudh Venkataramanan * 45142449105SAnirudh Venkataramanan * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 45242449105SAnirudh Venkataramanan * descriptor 45342449105SAnirudh Venkataramanan */ 45442449105SAnirudh Venkataramanan static void 45542449105SAnirudh Venkataramanan ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 45642449105SAnirudh Venkataramanan struct ice_aqc_set_mac_cfg *cmd) 45742449105SAnirudh Venkataramanan { 45842449105SAnirudh Venkataramanan u16 fc_thres_val, tx_timer_val; 45942449105SAnirudh Venkataramanan u32 val; 46042449105SAnirudh Venkataramanan 46142449105SAnirudh Venkataramanan /* We read back the transmit timer and FC threshold value of 46242449105SAnirudh Venkataramanan * LFC. Thus, we will use index = 46342449105SAnirudh Venkataramanan * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 46442449105SAnirudh Venkataramanan * 46542449105SAnirudh Venkataramanan * Also, because we are operating on transmit timer and FC 46642449105SAnirudh Venkataramanan * threshold of LFC, we don't turn on any bit in tx_tmr_priority 46742449105SAnirudh Venkataramanan */ 46842449105SAnirudh Venkataramanan #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 46942449105SAnirudh Venkataramanan 47042449105SAnirudh Venkataramanan /* Retrieve the transmit timer */ 47142449105SAnirudh Venkataramanan val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 47242449105SAnirudh Venkataramanan tx_timer_val = val & 47342449105SAnirudh Venkataramanan PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 47442449105SAnirudh Venkataramanan cmd->tx_tmr_value = cpu_to_le16(tx_timer_val); 47542449105SAnirudh Venkataramanan 47642449105SAnirudh Venkataramanan /* Retrieve the FC threshold */ 47742449105SAnirudh Venkataramanan val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 47842449105SAnirudh Venkataramanan fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 47942449105SAnirudh Venkataramanan 48042449105SAnirudh Venkataramanan cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val); 48142449105SAnirudh Venkataramanan } 48242449105SAnirudh Venkataramanan 48342449105SAnirudh Venkataramanan /** 48442449105SAnirudh Venkataramanan * ice_aq_set_mac_cfg 48542449105SAnirudh Venkataramanan * @hw: pointer to the HW struct 48642449105SAnirudh Venkataramanan * @max_frame_size: Maximum Frame Size to be supported 48742449105SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 48842449105SAnirudh Venkataramanan * 48942449105SAnirudh Venkataramanan * Set MAC configuration (0x0603) 49042449105SAnirudh Venkataramanan */ 49142449105SAnirudh Venkataramanan enum ice_status 49242449105SAnirudh Venkataramanan ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 49342449105SAnirudh Venkataramanan { 49442449105SAnirudh Venkataramanan struct ice_aqc_set_mac_cfg *cmd; 49542449105SAnirudh Venkataramanan struct ice_aq_desc desc; 49642449105SAnirudh Venkataramanan 49742449105SAnirudh Venkataramanan cmd = &desc.params.set_mac_cfg; 49842449105SAnirudh Venkataramanan 49942449105SAnirudh Venkataramanan if (max_frame_size == 0) 50042449105SAnirudh Venkataramanan return ICE_ERR_PARAM; 50142449105SAnirudh Venkataramanan 50242449105SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 50342449105SAnirudh Venkataramanan 50442449105SAnirudh Venkataramanan cmd->max_frame_size = cpu_to_le16(max_frame_size); 50542449105SAnirudh Venkataramanan 50642449105SAnirudh Venkataramanan ice_fill_tx_timer_and_fc_thresh(hw, cmd); 50742449105SAnirudh Venkataramanan 50842449105SAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 50942449105SAnirudh Venkataramanan } 51042449105SAnirudh Venkataramanan 51142449105SAnirudh Venkataramanan /** 5129daf8208SAnirudh Venkataramanan * ice_init_fltr_mgmt_struct - initializes filter management list and locks 513f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 5149daf8208SAnirudh Venkataramanan */ 5159daf8208SAnirudh Venkataramanan static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 5169daf8208SAnirudh Venkataramanan { 5179daf8208SAnirudh Venkataramanan struct ice_switch_info *sw; 5181aaef2bcSSurabhi Boob enum ice_status status; 5199daf8208SAnirudh Venkataramanan 5209daf8208SAnirudh Venkataramanan hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 5219daf8208SAnirudh Venkataramanan sizeof(*hw->switch_info), GFP_KERNEL); 5229daf8208SAnirudh Venkataramanan sw = hw->switch_info; 5239daf8208SAnirudh Venkataramanan 5249daf8208SAnirudh Venkataramanan if (!sw) 5259daf8208SAnirudh Venkataramanan return ICE_ERR_NO_MEMORY; 5269daf8208SAnirudh Venkataramanan 5279daf8208SAnirudh Venkataramanan INIT_LIST_HEAD(&sw->vsi_list_map_head); 5289daf8208SAnirudh Venkataramanan 5291aaef2bcSSurabhi Boob status = ice_init_def_sw_recp(hw); 5301aaef2bcSSurabhi Boob if (status) { 5311aaef2bcSSurabhi Boob devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 5321aaef2bcSSurabhi Boob return status; 5331aaef2bcSSurabhi Boob } 5341aaef2bcSSurabhi Boob return 0; 5359daf8208SAnirudh Venkataramanan } 5369daf8208SAnirudh Venkataramanan 5379daf8208SAnirudh Venkataramanan /** 5389daf8208SAnirudh Venkataramanan * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 539f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 5409daf8208SAnirudh Venkataramanan */ 5419daf8208SAnirudh Venkataramanan static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 5429daf8208SAnirudh Venkataramanan { 5439daf8208SAnirudh Venkataramanan struct ice_switch_info *sw = hw->switch_info; 5449daf8208SAnirudh Venkataramanan struct ice_vsi_list_map_info *v_pos_map; 5459daf8208SAnirudh Venkataramanan struct ice_vsi_list_map_info *v_tmp_map; 54680d144c9SAnirudh Venkataramanan struct ice_sw_recipe *recps; 54780d144c9SAnirudh Venkataramanan u8 i; 5489daf8208SAnirudh Venkataramanan 5499daf8208SAnirudh Venkataramanan list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 5509daf8208SAnirudh Venkataramanan list_entry) { 5519daf8208SAnirudh Venkataramanan list_del(&v_pos_map->list_entry); 5529daf8208SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), v_pos_map); 5539daf8208SAnirudh Venkataramanan } 55480d144c9SAnirudh Venkataramanan recps = hw->switch_info->recp_list; 55580d144c9SAnirudh Venkataramanan for (i = 0; i < ICE_SW_LKUP_LAST; i++) { 55680d144c9SAnirudh Venkataramanan struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 5579daf8208SAnirudh Venkataramanan 55880d144c9SAnirudh Venkataramanan recps[i].root_rid = i; 55980d144c9SAnirudh Venkataramanan mutex_destroy(&recps[i].filt_rule_lock); 56080d144c9SAnirudh Venkataramanan list_for_each_entry_safe(lst_itr, tmp_entry, 56180d144c9SAnirudh Venkataramanan &recps[i].filt_rules, list_entry) { 56280d144c9SAnirudh Venkataramanan list_del(&lst_itr->list_entry); 56380d144c9SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), lst_itr); 56480d144c9SAnirudh Venkataramanan } 56580d144c9SAnirudh Venkataramanan } 566334cb062SAnirudh Venkataramanan ice_rm_all_sw_replay_rule_info(hw); 56780d144c9SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 5689daf8208SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), sw); 5699daf8208SAnirudh Venkataramanan } 5709daf8208SAnirudh Venkataramanan 5718b97ceb1SHieu Tran /** 57211fe1b3aSDan Nowlin * ice_get_fw_log_cfg - get FW logging configuration 57311fe1b3aSDan Nowlin * @hw: pointer to the HW struct 57411fe1b3aSDan Nowlin */ 57511fe1b3aSDan Nowlin static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw) 57611fe1b3aSDan Nowlin { 57711fe1b3aSDan Nowlin struct ice_aq_desc desc; 57811fe1b3aSDan Nowlin enum ice_status status; 579b3c38904SBruce Allan __le16 *config; 58011fe1b3aSDan Nowlin u16 size; 58111fe1b3aSDan Nowlin 582b3c38904SBruce Allan size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX; 58311fe1b3aSDan Nowlin config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL); 58411fe1b3aSDan Nowlin if (!config) 58511fe1b3aSDan Nowlin return ICE_ERR_NO_MEMORY; 58611fe1b3aSDan Nowlin 58711fe1b3aSDan Nowlin ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 58811fe1b3aSDan Nowlin 58911fe1b3aSDan Nowlin desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 59011fe1b3aSDan Nowlin 59111fe1b3aSDan Nowlin status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 59211fe1b3aSDan Nowlin if (!status) { 59311fe1b3aSDan Nowlin u16 i; 59411fe1b3aSDan Nowlin 5952f2da36eSAnirudh Venkataramanan /* Save FW logging information into the HW structure */ 59611fe1b3aSDan Nowlin for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 59711fe1b3aSDan Nowlin u16 v, m, flgs; 59811fe1b3aSDan Nowlin 599b3c38904SBruce Allan v = le16_to_cpu(config[i]); 60011fe1b3aSDan Nowlin m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 60111fe1b3aSDan Nowlin flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 60211fe1b3aSDan Nowlin 60311fe1b3aSDan Nowlin if (m < ICE_AQC_FW_LOG_ID_MAX) 60411fe1b3aSDan Nowlin hw->fw_log.evnts[m].cur = flgs; 60511fe1b3aSDan Nowlin } 60611fe1b3aSDan Nowlin } 60711fe1b3aSDan Nowlin 60811fe1b3aSDan Nowlin devm_kfree(ice_hw_to_dev(hw), config); 60911fe1b3aSDan Nowlin 61011fe1b3aSDan Nowlin return status; 61111fe1b3aSDan Nowlin } 61211fe1b3aSDan Nowlin 61311fe1b3aSDan Nowlin /** 6148b97ceb1SHieu Tran * ice_cfg_fw_log - configure FW logging 615f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 6168b97ceb1SHieu Tran * @enable: enable certain FW logging events if true, disable all if false 6178b97ceb1SHieu Tran * 6188b97ceb1SHieu Tran * This function enables/disables the FW logging via Rx CQ events and a UART 6198b97ceb1SHieu Tran * port based on predetermined configurations. FW logging via the Rx CQ can be 6208b97ceb1SHieu Tran * enabled/disabled for individual PF's. However, FW logging via the UART can 6218b97ceb1SHieu Tran * only be enabled/disabled for all PFs on the same device. 6228b97ceb1SHieu Tran * 6238b97ceb1SHieu Tran * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 6248b97ceb1SHieu Tran * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 6258b97ceb1SHieu Tran * before initializing the device. 6268b97ceb1SHieu Tran * 6278b97ceb1SHieu Tran * When re/configuring FW logging, callers need to update the "cfg" elements of 6288b97ceb1SHieu Tran * the hw->fw_log.evnts array with the desired logging event configurations for 6298b97ceb1SHieu Tran * modules of interest. When disabling FW logging completely, the callers can 6308b97ceb1SHieu Tran * just pass false in the "enable" parameter. On completion, the function will 6318b97ceb1SHieu Tran * update the "cur" element of the hw->fw_log.evnts array with the resulting 6328b97ceb1SHieu Tran * logging event configurations of the modules that are being re/configured. FW 6338b97ceb1SHieu Tran * logging modules that are not part of a reconfiguration operation retain their 6348b97ceb1SHieu Tran * previous states. 6358b97ceb1SHieu Tran * 6368b97ceb1SHieu Tran * Before resetting the device, it is recommended that the driver disables FW 6378b97ceb1SHieu Tran * logging before shutting down the control queue. When disabling FW logging 6388b97ceb1SHieu Tran * ("enable" = false), the latest configurations of FW logging events stored in 6398b97ceb1SHieu Tran * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 6408b97ceb1SHieu Tran * a device reset. 6418b97ceb1SHieu Tran * 6428b97ceb1SHieu Tran * When enabling FW logging to emit log messages via the Rx CQ during the 6438b97ceb1SHieu Tran * device's initialization phase, a mechanism alternative to interrupt handlers 6448b97ceb1SHieu Tran * needs to be used to extract FW log messages from the Rx CQ periodically and 6458b97ceb1SHieu Tran * to prevent the Rx CQ from being full and stalling other types of control 6468b97ceb1SHieu Tran * messages from FW to SW. Interrupts are typically disabled during the device's 6478b97ceb1SHieu Tran * initialization phase. 6488b97ceb1SHieu Tran */ 6498b97ceb1SHieu Tran static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable) 6508b97ceb1SHieu Tran { 6518b97ceb1SHieu Tran struct ice_aqc_fw_logging *cmd; 6528b97ceb1SHieu Tran enum ice_status status = 0; 6538b97ceb1SHieu Tran u16 i, chgs = 0, len = 0; 6548b97ceb1SHieu Tran struct ice_aq_desc desc; 655b3c38904SBruce Allan __le16 *data = NULL; 6568b97ceb1SHieu Tran u8 actv_evnts = 0; 6578b97ceb1SHieu Tran void *buf = NULL; 6588b97ceb1SHieu Tran 6598b97ceb1SHieu Tran if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 6608b97ceb1SHieu Tran return 0; 6618b97ceb1SHieu Tran 6628b97ceb1SHieu Tran /* Disable FW logging only when the control queue is still responsive */ 6638b97ceb1SHieu Tran if (!enable && 6648b97ceb1SHieu Tran (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 6658b97ceb1SHieu Tran return 0; 6668b97ceb1SHieu Tran 66711fe1b3aSDan Nowlin /* Get current FW log settings */ 66811fe1b3aSDan Nowlin status = ice_get_fw_log_cfg(hw); 66911fe1b3aSDan Nowlin if (status) 67011fe1b3aSDan Nowlin return status; 67111fe1b3aSDan Nowlin 6728b97ceb1SHieu Tran ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 6738b97ceb1SHieu Tran cmd = &desc.params.fw_logging; 6748b97ceb1SHieu Tran 6758b97ceb1SHieu Tran /* Indicate which controls are valid */ 6768b97ceb1SHieu Tran if (hw->fw_log.cq_en) 6778b97ceb1SHieu Tran cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 6788b97ceb1SHieu Tran 6798b97ceb1SHieu Tran if (hw->fw_log.uart_en) 6808b97ceb1SHieu Tran cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 6818b97ceb1SHieu Tran 6828b97ceb1SHieu Tran if (enable) { 6838b97ceb1SHieu Tran /* Fill in an array of entries with FW logging modules and 6848b97ceb1SHieu Tran * logging events being reconfigured. 6858b97ceb1SHieu Tran */ 6868b97ceb1SHieu Tran for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 6878b97ceb1SHieu Tran u16 val; 6888b97ceb1SHieu Tran 6898b97ceb1SHieu Tran /* Keep track of enabled event types */ 6908b97ceb1SHieu Tran actv_evnts |= hw->fw_log.evnts[i].cfg; 6918b97ceb1SHieu Tran 6928b97ceb1SHieu Tran if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 6938b97ceb1SHieu Tran continue; 6948b97ceb1SHieu Tran 6958b97ceb1SHieu Tran if (!data) { 696b3c38904SBruce Allan data = devm_kcalloc(ice_hw_to_dev(hw), 697b3c38904SBruce Allan sizeof(*data), 698b3c38904SBruce Allan ICE_AQC_FW_LOG_ID_MAX, 6998b97ceb1SHieu Tran GFP_KERNEL); 7008b97ceb1SHieu Tran if (!data) 7018b97ceb1SHieu Tran return ICE_ERR_NO_MEMORY; 7028b97ceb1SHieu Tran } 7038b97ceb1SHieu Tran 7048b97ceb1SHieu Tran val = i << ICE_AQC_FW_LOG_ID_S; 7058b97ceb1SHieu Tran val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 706b3c38904SBruce Allan data[chgs++] = cpu_to_le16(val); 7078b97ceb1SHieu Tran } 7088b97ceb1SHieu Tran 7098b97ceb1SHieu Tran /* Only enable FW logging if at least one module is specified. 7108b97ceb1SHieu Tran * If FW logging is currently enabled but all modules are not 7118b97ceb1SHieu Tran * enabled to emit log messages, disable FW logging altogether. 7128b97ceb1SHieu Tran */ 7138b97ceb1SHieu Tran if (actv_evnts) { 7148b97ceb1SHieu Tran /* Leave if there is effectively no change */ 7158b97ceb1SHieu Tran if (!chgs) 7168b97ceb1SHieu Tran goto out; 7178b97ceb1SHieu Tran 7188b97ceb1SHieu Tran if (hw->fw_log.cq_en) 7198b97ceb1SHieu Tran cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 7208b97ceb1SHieu Tran 7218b97ceb1SHieu Tran if (hw->fw_log.uart_en) 7228b97ceb1SHieu Tran cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 7238b97ceb1SHieu Tran 7248b97ceb1SHieu Tran buf = data; 725b3c38904SBruce Allan len = sizeof(*data) * chgs; 7268b97ceb1SHieu Tran desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 7278b97ceb1SHieu Tran } 7288b97ceb1SHieu Tran } 7298b97ceb1SHieu Tran 7308b97ceb1SHieu Tran status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 7318b97ceb1SHieu Tran if (!status) { 7328b97ceb1SHieu Tran /* Update the current configuration to reflect events enabled. 7338b97ceb1SHieu Tran * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 7348b97ceb1SHieu Tran * logging mode is enabled for the device. They do not reflect 7358b97ceb1SHieu Tran * actual modules being enabled to emit log messages. So, their 7368b97ceb1SHieu Tran * values remain unchanged even when all modules are disabled. 7378b97ceb1SHieu Tran */ 7388b97ceb1SHieu Tran u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 7398b97ceb1SHieu Tran 7408b97ceb1SHieu Tran hw->fw_log.actv_evnts = actv_evnts; 7418b97ceb1SHieu Tran for (i = 0; i < cnt; i++) { 7428b97ceb1SHieu Tran u16 v, m; 7438b97ceb1SHieu Tran 7448b97ceb1SHieu Tran if (!enable) { 7458b97ceb1SHieu Tran /* When disabling all FW logging events as part 7468b97ceb1SHieu Tran * of device's de-initialization, the original 7478b97ceb1SHieu Tran * configurations are retained, and can be used 7488b97ceb1SHieu Tran * to reconfigure FW logging later if the device 7498b97ceb1SHieu Tran * is re-initialized. 7508b97ceb1SHieu Tran */ 7518b97ceb1SHieu Tran hw->fw_log.evnts[i].cur = 0; 7528b97ceb1SHieu Tran continue; 7538b97ceb1SHieu Tran } 7548b97ceb1SHieu Tran 755b3c38904SBruce Allan v = le16_to_cpu(data[i]); 7568b97ceb1SHieu Tran m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 7578b97ceb1SHieu Tran hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 7588b97ceb1SHieu Tran } 7598b97ceb1SHieu Tran } 7608b97ceb1SHieu Tran 7618b97ceb1SHieu Tran out: 7628b97ceb1SHieu Tran if (data) 7638b97ceb1SHieu Tran devm_kfree(ice_hw_to_dev(hw), data); 7648b97ceb1SHieu Tran 7658b97ceb1SHieu Tran return status; 7668b97ceb1SHieu Tran } 7678b97ceb1SHieu Tran 7688b97ceb1SHieu Tran /** 7698b97ceb1SHieu Tran * ice_output_fw_log 770f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 7718b97ceb1SHieu Tran * @desc: pointer to the AQ message descriptor 7728b97ceb1SHieu Tran * @buf: pointer to the buffer accompanying the AQ message 7738b97ceb1SHieu Tran * 7748b97ceb1SHieu Tran * Formats a FW Log message and outputs it via the standard driver logs. 7758b97ceb1SHieu Tran */ 7768b97ceb1SHieu Tran void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 7778b97ceb1SHieu Tran { 7784f70daa0SJacob Keller ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 7794f70daa0SJacob Keller ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 7808b97ceb1SHieu Tran le16_to_cpu(desc->datalen)); 7814f70daa0SJacob Keller ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 7828b97ceb1SHieu Tran } 7838b97ceb1SHieu Tran 7849daf8208SAnirudh Venkataramanan /** 7854ee656bbSTony Nguyen * ice_get_itr_intrl_gran 786f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 7879e4ab4c2SBrett Creeley * 7884ee656bbSTony Nguyen * Determines the ITR/INTRL granularities based on the maximum aggregate 7899e4ab4c2SBrett Creeley * bandwidth according to the device's configuration during power-on. 7909e4ab4c2SBrett Creeley */ 791fe7219faSBruce Allan static void ice_get_itr_intrl_gran(struct ice_hw *hw) 7929e4ab4c2SBrett Creeley { 7939e4ab4c2SBrett Creeley u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 7949e4ab4c2SBrett Creeley GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 7959e4ab4c2SBrett Creeley GL_PWR_MODE_CTL_CAR_MAX_BW_S; 7969e4ab4c2SBrett Creeley 7979e4ab4c2SBrett Creeley switch (max_agg_bw) { 7989e4ab4c2SBrett Creeley case ICE_MAX_AGG_BW_200G: 7999e4ab4c2SBrett Creeley case ICE_MAX_AGG_BW_100G: 8009e4ab4c2SBrett Creeley case ICE_MAX_AGG_BW_50G: 8019e4ab4c2SBrett Creeley hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 8029e4ab4c2SBrett Creeley hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 8039e4ab4c2SBrett Creeley break; 8049e4ab4c2SBrett Creeley case ICE_MAX_AGG_BW_25G: 8059e4ab4c2SBrett Creeley hw->itr_gran = ICE_ITR_GRAN_MAX_25; 8069e4ab4c2SBrett Creeley hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 8079e4ab4c2SBrett Creeley break; 8089e4ab4c2SBrett Creeley } 8099e4ab4c2SBrett Creeley } 8109e4ab4c2SBrett Creeley 8119e4ab4c2SBrett Creeley /** 812f31e4b6fSAnirudh Venkataramanan * ice_init_hw - main hardware initialization routine 813f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure 814f31e4b6fSAnirudh Venkataramanan */ 815f31e4b6fSAnirudh Venkataramanan enum ice_status ice_init_hw(struct ice_hw *hw) 816f31e4b6fSAnirudh Venkataramanan { 817dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps_data *pcaps; 818f31e4b6fSAnirudh Venkataramanan enum ice_status status; 819dc49c772SAnirudh Venkataramanan u16 mac_buf_len; 820dc49c772SAnirudh Venkataramanan void *mac_buf; 821f31e4b6fSAnirudh Venkataramanan 822f31e4b6fSAnirudh Venkataramanan /* Set MAC type based on DeviceID */ 823f31e4b6fSAnirudh Venkataramanan status = ice_set_mac_type(hw); 824f31e4b6fSAnirudh Venkataramanan if (status) 825f31e4b6fSAnirudh Venkataramanan return status; 826f31e4b6fSAnirudh Venkataramanan 827f31e4b6fSAnirudh Venkataramanan hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 828f31e4b6fSAnirudh Venkataramanan PF_FUNC_RID_FUNC_NUM_M) >> 829f31e4b6fSAnirudh Venkataramanan PF_FUNC_RID_FUNC_NUM_S; 830f31e4b6fSAnirudh Venkataramanan 831f31e4b6fSAnirudh Venkataramanan status = ice_reset(hw, ICE_RESET_PFR); 832f31e4b6fSAnirudh Venkataramanan if (status) 833f31e4b6fSAnirudh Venkataramanan return status; 834f31e4b6fSAnirudh Venkataramanan 835fe7219faSBruce Allan ice_get_itr_intrl_gran(hw); 836940b61afSAnirudh Venkataramanan 8375c91ecfdSJacob Keller status = ice_create_all_ctrlq(hw); 838f31e4b6fSAnirudh Venkataramanan if (status) 839f31e4b6fSAnirudh Venkataramanan goto err_unroll_cqinit; 840f31e4b6fSAnirudh Venkataramanan 8418b97ceb1SHieu Tran /* Enable FW logging. Not fatal if this fails. */ 8428b97ceb1SHieu Tran status = ice_cfg_fw_log(hw, true); 8438b97ceb1SHieu Tran if (status) 8448b97ceb1SHieu Tran ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 8458b97ceb1SHieu Tran 846f31e4b6fSAnirudh Venkataramanan status = ice_clear_pf_cfg(hw); 847f31e4b6fSAnirudh Venkataramanan if (status) 848f31e4b6fSAnirudh Venkataramanan goto err_unroll_cqinit; 849f31e4b6fSAnirudh Venkataramanan 850148beb61SHenry Tieman /* Set bit to enable Flow Director filters */ 851148beb61SHenry Tieman wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 852148beb61SHenry Tieman INIT_LIST_HEAD(&hw->fdir_list_head); 853148beb61SHenry Tieman 854f31e4b6fSAnirudh Venkataramanan ice_clear_pxe_mode(hw); 855f31e4b6fSAnirudh Venkataramanan 856f31e4b6fSAnirudh Venkataramanan status = ice_init_nvm(hw); 857f31e4b6fSAnirudh Venkataramanan if (status) 858f31e4b6fSAnirudh Venkataramanan goto err_unroll_cqinit; 859f31e4b6fSAnirudh Venkataramanan 8609c20346bSAnirudh Venkataramanan status = ice_get_caps(hw); 8619c20346bSAnirudh Venkataramanan if (status) 8629c20346bSAnirudh Venkataramanan goto err_unroll_cqinit; 8639c20346bSAnirudh Venkataramanan 8649c20346bSAnirudh Venkataramanan hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 8659c20346bSAnirudh Venkataramanan sizeof(*hw->port_info), GFP_KERNEL); 8669c20346bSAnirudh Venkataramanan if (!hw->port_info) { 8679c20346bSAnirudh Venkataramanan status = ICE_ERR_NO_MEMORY; 8689c20346bSAnirudh Venkataramanan goto err_unroll_cqinit; 8699c20346bSAnirudh Venkataramanan } 8709c20346bSAnirudh Venkataramanan 871f9867df6SAnirudh Venkataramanan /* set the back pointer to HW */ 8729c20346bSAnirudh Venkataramanan hw->port_info->hw = hw; 8739c20346bSAnirudh Venkataramanan 8749c20346bSAnirudh Venkataramanan /* Initialize port_info struct with switch configuration data */ 8759c20346bSAnirudh Venkataramanan status = ice_get_initial_sw_cfg(hw); 8769c20346bSAnirudh Venkataramanan if (status) 8779c20346bSAnirudh Venkataramanan goto err_unroll_alloc; 8789c20346bSAnirudh Venkataramanan 8799daf8208SAnirudh Venkataramanan hw->evb_veb = true; 8809daf8208SAnirudh Venkataramanan 881d337f2afSAnirudh Venkataramanan /* Query the allocated resources for Tx scheduler */ 8829c20346bSAnirudh Venkataramanan status = ice_sched_query_res_alloc(hw); 8839c20346bSAnirudh Venkataramanan if (status) { 8849c20346bSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, 8859c20346bSAnirudh Venkataramanan "Failed to get scheduler allocated resources\n"); 8869c20346bSAnirudh Venkataramanan goto err_unroll_alloc; 8879c20346bSAnirudh Venkataramanan } 8889c20346bSAnirudh Venkataramanan 889dc49c772SAnirudh Venkataramanan /* Initialize port_info struct with scheduler data */ 890dc49c772SAnirudh Venkataramanan status = ice_sched_init_port(hw->port_info); 891dc49c772SAnirudh Venkataramanan if (status) 892dc49c772SAnirudh Venkataramanan goto err_unroll_sched; 893dc49c772SAnirudh Venkataramanan 894dc49c772SAnirudh Venkataramanan pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 895dc49c772SAnirudh Venkataramanan if (!pcaps) { 896dc49c772SAnirudh Venkataramanan status = ICE_ERR_NO_MEMORY; 897dc49c772SAnirudh Venkataramanan goto err_unroll_sched; 898dc49c772SAnirudh Venkataramanan } 899dc49c772SAnirudh Venkataramanan 900dc49c772SAnirudh Venkataramanan /* Initialize port_info struct with PHY capabilities */ 901dc49c772SAnirudh Venkataramanan status = ice_aq_get_phy_caps(hw->port_info, false, 902dc49c772SAnirudh Venkataramanan ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); 903dc49c772SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), pcaps); 904dc49c772SAnirudh Venkataramanan if (status) 905dc49c772SAnirudh Venkataramanan goto err_unroll_sched; 906dc49c772SAnirudh Venkataramanan 907dc49c772SAnirudh Venkataramanan /* Initialize port_info struct with link information */ 908dc49c772SAnirudh Venkataramanan status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 909dc49c772SAnirudh Venkataramanan if (status) 910dc49c772SAnirudh Venkataramanan goto err_unroll_sched; 911dc49c772SAnirudh Venkataramanan 912b36c598cSAnirudh Venkataramanan /* need a valid SW entry point to build a Tx tree */ 913b36c598cSAnirudh Venkataramanan if (!hw->sw_entry_point_layer) { 914b36c598cSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 915b36c598cSAnirudh Venkataramanan status = ICE_ERR_CFG; 916b36c598cSAnirudh Venkataramanan goto err_unroll_sched; 917b36c598cSAnirudh Venkataramanan } 9189be1d6f8SAnirudh Venkataramanan INIT_LIST_HEAD(&hw->agg_list); 9191ddef455SUsha Ketineni /* Initialize max burst size */ 9201ddef455SUsha Ketineni if (!hw->max_burst_size) 9211ddef455SUsha Ketineni ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 922b36c598cSAnirudh Venkataramanan 9239daf8208SAnirudh Venkataramanan status = ice_init_fltr_mgmt_struct(hw); 9249daf8208SAnirudh Venkataramanan if (status) 9259daf8208SAnirudh Venkataramanan goto err_unroll_sched; 9269daf8208SAnirudh Venkataramanan 927d6fef10cSMd Fahad Iqbal Polash /* Get MAC information */ 928d6fef10cSMd Fahad Iqbal Polash /* A single port can report up to two (LAN and WoL) addresses */ 929d6fef10cSMd Fahad Iqbal Polash mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 930d6fef10cSMd Fahad Iqbal Polash sizeof(struct ice_aqc_manage_mac_read_resp), 931d6fef10cSMd Fahad Iqbal Polash GFP_KERNEL); 932d6fef10cSMd Fahad Iqbal Polash mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 933dc49c772SAnirudh Venkataramanan 93463bb4e1eSWei Yongjun if (!mac_buf) { 93563bb4e1eSWei Yongjun status = ICE_ERR_NO_MEMORY; 9369daf8208SAnirudh Venkataramanan goto err_unroll_fltr_mgmt_struct; 93763bb4e1eSWei Yongjun } 938dc49c772SAnirudh Venkataramanan 939dc49c772SAnirudh Venkataramanan status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 940dc49c772SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), mac_buf); 941dc49c772SAnirudh Venkataramanan 942dc49c772SAnirudh Venkataramanan if (status) 9439daf8208SAnirudh Venkataramanan goto err_unroll_fltr_mgmt_struct; 94442449105SAnirudh Venkataramanan /* enable jumbo frame support at MAC level */ 94542449105SAnirudh Venkataramanan status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 94642449105SAnirudh Venkataramanan if (status) 94742449105SAnirudh Venkataramanan goto err_unroll_fltr_mgmt_struct; 948148beb61SHenry Tieman /* Obtain counter base index which would be used by flow director */ 949148beb61SHenry Tieman status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 950148beb61SHenry Tieman if (status) 951148beb61SHenry Tieman goto err_unroll_fltr_mgmt_struct; 95232d63fa1STony Nguyen status = ice_init_hw_tbls(hw); 95332d63fa1STony Nguyen if (status) 95432d63fa1STony Nguyen goto err_unroll_fltr_mgmt_struct; 955a4e82a81STony Nguyen mutex_init(&hw->tnl_lock); 956f31e4b6fSAnirudh Venkataramanan return 0; 957f31e4b6fSAnirudh Venkataramanan 9589daf8208SAnirudh Venkataramanan err_unroll_fltr_mgmt_struct: 9599daf8208SAnirudh Venkataramanan ice_cleanup_fltr_mgmt_struct(hw); 960dc49c772SAnirudh Venkataramanan err_unroll_sched: 961dc49c772SAnirudh Venkataramanan ice_sched_cleanup_all(hw); 9629c20346bSAnirudh Venkataramanan err_unroll_alloc: 9639c20346bSAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), hw->port_info); 964f31e4b6fSAnirudh Venkataramanan err_unroll_cqinit: 9655c91ecfdSJacob Keller ice_destroy_all_ctrlq(hw); 966f31e4b6fSAnirudh Venkataramanan return status; 967f31e4b6fSAnirudh Venkataramanan } 968f31e4b6fSAnirudh Venkataramanan 969f31e4b6fSAnirudh Venkataramanan /** 970f31e4b6fSAnirudh Venkataramanan * ice_deinit_hw - unroll initialization operations done by ice_init_hw 971f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure 972ed14245aSAnirudh Venkataramanan * 973ed14245aSAnirudh Venkataramanan * This should be called only during nominal operation, not as a result of 974ed14245aSAnirudh Venkataramanan * ice_init_hw() failing since ice_init_hw() will take care of unrolling 975ed14245aSAnirudh Venkataramanan * applicable initializations if it fails for any reason. 976f31e4b6fSAnirudh Venkataramanan */ 977f31e4b6fSAnirudh Venkataramanan void ice_deinit_hw(struct ice_hw *hw) 978f31e4b6fSAnirudh Venkataramanan { 979148beb61SHenry Tieman ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 9808b97ceb1SHieu Tran ice_cleanup_fltr_mgmt_struct(hw); 9818b97ceb1SHieu Tran 9829c20346bSAnirudh Venkataramanan ice_sched_cleanup_all(hw); 9839be1d6f8SAnirudh Venkataramanan ice_sched_clear_agg(hw); 984c7648810STony Nguyen ice_free_seg(hw); 98532d63fa1STony Nguyen ice_free_hw_tbls(hw); 986a4e82a81STony Nguyen mutex_destroy(&hw->tnl_lock); 987dc49c772SAnirudh Venkataramanan 9889c20346bSAnirudh Venkataramanan if (hw->port_info) { 9899c20346bSAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), hw->port_info); 9909c20346bSAnirudh Venkataramanan hw->port_info = NULL; 9919c20346bSAnirudh Venkataramanan } 9929daf8208SAnirudh Venkataramanan 9938b97ceb1SHieu Tran /* Attempt to disable FW logging before shutting down control queues */ 9948b97ceb1SHieu Tran ice_cfg_fw_log(hw, false); 9955c91ecfdSJacob Keller ice_destroy_all_ctrlq(hw); 99633e055fcSVictor Raj 99733e055fcSVictor Raj /* Clear VSI contexts if not already cleared */ 99833e055fcSVictor Raj ice_clear_all_vsi_ctx(hw); 999f31e4b6fSAnirudh Venkataramanan } 1000f31e4b6fSAnirudh Venkataramanan 1001f31e4b6fSAnirudh Venkataramanan /** 1002f31e4b6fSAnirudh Venkataramanan * ice_check_reset - Check to see if a global reset is complete 1003f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure 1004f31e4b6fSAnirudh Venkataramanan */ 1005f31e4b6fSAnirudh Venkataramanan enum ice_status ice_check_reset(struct ice_hw *hw) 1006f31e4b6fSAnirudh Venkataramanan { 1007cf8fc2a0SBruce Allan u32 cnt, reg = 0, grst_delay, uld_mask; 1008f31e4b6fSAnirudh Venkataramanan 1009f31e4b6fSAnirudh Venkataramanan /* Poll for Device Active state in case a recent CORER, GLOBR, 1010f31e4b6fSAnirudh Venkataramanan * or EMPR has occurred. The grst delay value is in 100ms units. 1011f31e4b6fSAnirudh Venkataramanan * Add 1sec for outstanding AQ commands that can take a long time. 1012f31e4b6fSAnirudh Venkataramanan */ 1013f31e4b6fSAnirudh Venkataramanan grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1014f31e4b6fSAnirudh Venkataramanan GLGEN_RSTCTL_GRSTDEL_S) + 10; 1015f31e4b6fSAnirudh Venkataramanan 1016f31e4b6fSAnirudh Venkataramanan for (cnt = 0; cnt < grst_delay; cnt++) { 1017f31e4b6fSAnirudh Venkataramanan mdelay(100); 1018f31e4b6fSAnirudh Venkataramanan reg = rd32(hw, GLGEN_RSTAT); 1019f31e4b6fSAnirudh Venkataramanan if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1020f31e4b6fSAnirudh Venkataramanan break; 1021f31e4b6fSAnirudh Venkataramanan } 1022f31e4b6fSAnirudh Venkataramanan 1023f31e4b6fSAnirudh Venkataramanan if (cnt == grst_delay) { 1024f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 1025f31e4b6fSAnirudh Venkataramanan "Global reset polling failed to complete.\n"); 1026f31e4b6fSAnirudh Venkataramanan return ICE_ERR_RESET_FAILED; 1027f31e4b6fSAnirudh Venkataramanan } 1028f31e4b6fSAnirudh Venkataramanan 1029cf8fc2a0SBruce Allan #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1030cf8fc2a0SBruce Allan GLNVM_ULD_PCIER_DONE_1_M |\ 1031cf8fc2a0SBruce Allan GLNVM_ULD_CORER_DONE_M |\ 1032cf8fc2a0SBruce Allan GLNVM_ULD_GLOBR_DONE_M |\ 1033cf8fc2a0SBruce Allan GLNVM_ULD_POR_DONE_M |\ 1034cf8fc2a0SBruce Allan GLNVM_ULD_POR_DONE_1_M |\ 1035cf8fc2a0SBruce Allan GLNVM_ULD_PCIER_DONE_2_M) 1036cf8fc2a0SBruce Allan 1037cf8fc2a0SBruce Allan uld_mask = ICE_RESET_DONE_MASK; 1038f31e4b6fSAnirudh Venkataramanan 1039f31e4b6fSAnirudh Venkataramanan /* Device is Active; check Global Reset processes are done */ 1040f31e4b6fSAnirudh Venkataramanan for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1041cf8fc2a0SBruce Allan reg = rd32(hw, GLNVM_ULD) & uld_mask; 1042cf8fc2a0SBruce Allan if (reg == uld_mask) { 1043f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 1044f31e4b6fSAnirudh Venkataramanan "Global reset processes done. %d\n", cnt); 1045f31e4b6fSAnirudh Venkataramanan break; 1046f31e4b6fSAnirudh Venkataramanan } 1047f31e4b6fSAnirudh Venkataramanan mdelay(10); 1048f31e4b6fSAnirudh Venkataramanan } 1049f31e4b6fSAnirudh Venkataramanan 1050f31e4b6fSAnirudh Venkataramanan if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1051f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 1052f31e4b6fSAnirudh Venkataramanan "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1053f31e4b6fSAnirudh Venkataramanan reg); 1054f31e4b6fSAnirudh Venkataramanan return ICE_ERR_RESET_FAILED; 1055f31e4b6fSAnirudh Venkataramanan } 1056f31e4b6fSAnirudh Venkataramanan 1057f31e4b6fSAnirudh Venkataramanan return 0; 1058f31e4b6fSAnirudh Venkataramanan } 1059f31e4b6fSAnirudh Venkataramanan 1060f31e4b6fSAnirudh Venkataramanan /** 1061f31e4b6fSAnirudh Venkataramanan * ice_pf_reset - Reset the PF 1062f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure 1063f31e4b6fSAnirudh Venkataramanan * 1064f31e4b6fSAnirudh Venkataramanan * If a global reset has been triggered, this function checks 1065f31e4b6fSAnirudh Venkataramanan * for its completion and then issues the PF reset 1066f31e4b6fSAnirudh Venkataramanan */ 1067f31e4b6fSAnirudh Venkataramanan static enum ice_status ice_pf_reset(struct ice_hw *hw) 1068f31e4b6fSAnirudh Venkataramanan { 1069f31e4b6fSAnirudh Venkataramanan u32 cnt, reg; 1070f31e4b6fSAnirudh Venkataramanan 1071f31e4b6fSAnirudh Venkataramanan /* If at function entry a global reset was already in progress, i.e. 1072f31e4b6fSAnirudh Venkataramanan * state is not 'device active' or any of the reset done bits are not 1073f31e4b6fSAnirudh Venkataramanan * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1074f31e4b6fSAnirudh Venkataramanan * global reset is done. 1075f31e4b6fSAnirudh Venkataramanan */ 1076f31e4b6fSAnirudh Venkataramanan if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1077f31e4b6fSAnirudh Venkataramanan (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1078f31e4b6fSAnirudh Venkataramanan /* poll on global reset currently in progress until done */ 1079f31e4b6fSAnirudh Venkataramanan if (ice_check_reset(hw)) 1080f31e4b6fSAnirudh Venkataramanan return ICE_ERR_RESET_FAILED; 1081f31e4b6fSAnirudh Venkataramanan 1082f31e4b6fSAnirudh Venkataramanan return 0; 1083f31e4b6fSAnirudh Venkataramanan } 1084f31e4b6fSAnirudh Venkataramanan 1085f31e4b6fSAnirudh Venkataramanan /* Reset the PF */ 1086f31e4b6fSAnirudh Venkataramanan reg = rd32(hw, PFGEN_CTRL); 1087f31e4b6fSAnirudh Venkataramanan 1088f31e4b6fSAnirudh Venkataramanan wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1089f31e4b6fSAnirudh Venkataramanan 1090c9a12d6dSDan Nowlin /* Wait for the PFR to complete. The wait time is the global config lock 1091c9a12d6dSDan Nowlin * timeout plus the PFR timeout which will account for a possible reset 1092c9a12d6dSDan Nowlin * that is occurring during a download package operation. 1093c9a12d6dSDan Nowlin */ 1094c9a12d6dSDan Nowlin for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1095c9a12d6dSDan Nowlin ICE_PF_RESET_WAIT_COUNT; cnt++) { 1096f31e4b6fSAnirudh Venkataramanan reg = rd32(hw, PFGEN_CTRL); 1097f31e4b6fSAnirudh Venkataramanan if (!(reg & PFGEN_CTRL_PFSWR_M)) 1098f31e4b6fSAnirudh Venkataramanan break; 1099f31e4b6fSAnirudh Venkataramanan 1100f31e4b6fSAnirudh Venkataramanan mdelay(1); 1101f31e4b6fSAnirudh Venkataramanan } 1102f31e4b6fSAnirudh Venkataramanan 1103f31e4b6fSAnirudh Venkataramanan if (cnt == ICE_PF_RESET_WAIT_COUNT) { 1104f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 1105f31e4b6fSAnirudh Venkataramanan "PF reset polling failed to complete.\n"); 1106f31e4b6fSAnirudh Venkataramanan return ICE_ERR_RESET_FAILED; 1107f31e4b6fSAnirudh Venkataramanan } 1108f31e4b6fSAnirudh Venkataramanan 1109f31e4b6fSAnirudh Venkataramanan return 0; 1110f31e4b6fSAnirudh Venkataramanan } 1111f31e4b6fSAnirudh Venkataramanan 1112f31e4b6fSAnirudh Venkataramanan /** 1113f31e4b6fSAnirudh Venkataramanan * ice_reset - Perform different types of reset 1114f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure 1115f31e4b6fSAnirudh Venkataramanan * @req: reset request 1116f31e4b6fSAnirudh Venkataramanan * 1117f31e4b6fSAnirudh Venkataramanan * This function triggers a reset as specified by the req parameter. 1118f31e4b6fSAnirudh Venkataramanan * 1119f31e4b6fSAnirudh Venkataramanan * Note: 1120f31e4b6fSAnirudh Venkataramanan * If anything other than a PF reset is triggered, PXE mode is restored. 1121f31e4b6fSAnirudh Venkataramanan * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1122f31e4b6fSAnirudh Venkataramanan * interface has been restored in the rebuild flow. 1123f31e4b6fSAnirudh Venkataramanan */ 1124f31e4b6fSAnirudh Venkataramanan enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1125f31e4b6fSAnirudh Venkataramanan { 1126f31e4b6fSAnirudh Venkataramanan u32 val = 0; 1127f31e4b6fSAnirudh Venkataramanan 1128f31e4b6fSAnirudh Venkataramanan switch (req) { 1129f31e4b6fSAnirudh Venkataramanan case ICE_RESET_PFR: 1130f31e4b6fSAnirudh Venkataramanan return ice_pf_reset(hw); 1131f31e4b6fSAnirudh Venkataramanan case ICE_RESET_CORER: 1132f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1133f31e4b6fSAnirudh Venkataramanan val = GLGEN_RTRIG_CORER_M; 1134f31e4b6fSAnirudh Venkataramanan break; 1135f31e4b6fSAnirudh Venkataramanan case ICE_RESET_GLOBR: 1136f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1137f31e4b6fSAnirudh Venkataramanan val = GLGEN_RTRIG_GLOBR_M; 1138f31e4b6fSAnirudh Venkataramanan break; 11390f9d5027SAnirudh Venkataramanan default: 11400f9d5027SAnirudh Venkataramanan return ICE_ERR_PARAM; 1141f31e4b6fSAnirudh Venkataramanan } 1142f31e4b6fSAnirudh Venkataramanan 1143f31e4b6fSAnirudh Venkataramanan val |= rd32(hw, GLGEN_RTRIG); 1144f31e4b6fSAnirudh Venkataramanan wr32(hw, GLGEN_RTRIG, val); 1145f31e4b6fSAnirudh Venkataramanan ice_flush(hw); 1146f31e4b6fSAnirudh Venkataramanan 1147f31e4b6fSAnirudh Venkataramanan /* wait for the FW to be ready */ 1148f31e4b6fSAnirudh Venkataramanan return ice_check_reset(hw); 1149f31e4b6fSAnirudh Venkataramanan } 1150f31e4b6fSAnirudh Venkataramanan 11517ec59eeaSAnirudh Venkataramanan /** 1152cdedef59SAnirudh Venkataramanan * ice_copy_rxq_ctx_to_hw 1153cdedef59SAnirudh Venkataramanan * @hw: pointer to the hardware structure 1154cdedef59SAnirudh Venkataramanan * @ice_rxq_ctx: pointer to the rxq context 1155d337f2afSAnirudh Venkataramanan * @rxq_index: the index of the Rx queue 1156cdedef59SAnirudh Venkataramanan * 1157f9867df6SAnirudh Venkataramanan * Copies rxq context from dense structure to HW register space 1158cdedef59SAnirudh Venkataramanan */ 1159cdedef59SAnirudh Venkataramanan static enum ice_status 1160cdedef59SAnirudh Venkataramanan ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1161cdedef59SAnirudh Venkataramanan { 1162cdedef59SAnirudh Venkataramanan u8 i; 1163cdedef59SAnirudh Venkataramanan 1164cdedef59SAnirudh Venkataramanan if (!ice_rxq_ctx) 1165cdedef59SAnirudh Venkataramanan return ICE_ERR_BAD_PTR; 1166cdedef59SAnirudh Venkataramanan 1167cdedef59SAnirudh Venkataramanan if (rxq_index > QRX_CTRL_MAX_INDEX) 1168cdedef59SAnirudh Venkataramanan return ICE_ERR_PARAM; 1169cdedef59SAnirudh Venkataramanan 1170f9867df6SAnirudh Venkataramanan /* Copy each dword separately to HW */ 1171cdedef59SAnirudh Venkataramanan for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1172cdedef59SAnirudh Venkataramanan wr32(hw, QRX_CONTEXT(i, rxq_index), 1173cdedef59SAnirudh Venkataramanan *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1174cdedef59SAnirudh Venkataramanan 1175cdedef59SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1176cdedef59SAnirudh Venkataramanan *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1177cdedef59SAnirudh Venkataramanan } 1178cdedef59SAnirudh Venkataramanan 1179cdedef59SAnirudh Venkataramanan return 0; 1180cdedef59SAnirudh Venkataramanan } 1181cdedef59SAnirudh Venkataramanan 1182cdedef59SAnirudh Venkataramanan /* LAN Rx Queue Context */ 1183cdedef59SAnirudh Venkataramanan static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1184cdedef59SAnirudh Venkataramanan /* Field Width LSB */ 1185cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1186cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1187cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1188cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1189cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1190cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1191cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1192cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1193cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1194cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1195cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1196cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1197cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1198cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1199cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1200cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1201cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1202cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1203cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1204c31a5c25SBrett Creeley ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1205cdedef59SAnirudh Venkataramanan { 0 } 1206cdedef59SAnirudh Venkataramanan }; 1207cdedef59SAnirudh Venkataramanan 1208cdedef59SAnirudh Venkataramanan /** 1209cdedef59SAnirudh Venkataramanan * ice_write_rxq_ctx 1210cdedef59SAnirudh Venkataramanan * @hw: pointer to the hardware structure 1211cdedef59SAnirudh Venkataramanan * @rlan_ctx: pointer to the rxq context 1212d337f2afSAnirudh Venkataramanan * @rxq_index: the index of the Rx queue 1213cdedef59SAnirudh Venkataramanan * 1214cdedef59SAnirudh Venkataramanan * Converts rxq context from sparse to dense structure and then writes 1215c31a5c25SBrett Creeley * it to HW register space and enables the hardware to prefetch descriptors 1216c31a5c25SBrett Creeley * instead of only fetching them on demand 1217cdedef59SAnirudh Venkataramanan */ 1218cdedef59SAnirudh Venkataramanan enum ice_status 1219cdedef59SAnirudh Venkataramanan ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1220cdedef59SAnirudh Venkataramanan u32 rxq_index) 1221cdedef59SAnirudh Venkataramanan { 1222cdedef59SAnirudh Venkataramanan u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1223cdedef59SAnirudh Venkataramanan 1224c31a5c25SBrett Creeley if (!rlan_ctx) 1225c31a5c25SBrett Creeley return ICE_ERR_BAD_PTR; 1226c31a5c25SBrett Creeley 1227c31a5c25SBrett Creeley rlan_ctx->prefena = 1; 1228c31a5c25SBrett Creeley 12297e34786aSBruce Allan ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1230cdedef59SAnirudh Venkataramanan return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1231cdedef59SAnirudh Venkataramanan } 1232cdedef59SAnirudh Venkataramanan 1233cdedef59SAnirudh Venkataramanan /* LAN Tx Queue Context */ 1234cdedef59SAnirudh Venkataramanan const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1235cdedef59SAnirudh Venkataramanan /* Field Width LSB */ 1236cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1237cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1238cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1239cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1240cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1241cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1242cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1243cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1244201beeb7SAshish Shah ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1245cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1246cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1247cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1248cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1249cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1250cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1251cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1252cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1253cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1254cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1255cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1256cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1257cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1258cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1259cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1260cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1261cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1262cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1263201beeb7SAshish Shah ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1264cdedef59SAnirudh Venkataramanan { 0 } 1265cdedef59SAnirudh Venkataramanan }; 1266cdedef59SAnirudh Venkataramanan 12677ec59eeaSAnirudh Venkataramanan /* FW Admin Queue command wrappers */ 12687ec59eeaSAnirudh Venkataramanan 1269c7648810STony Nguyen /* Software lock/mutex that is meant to be held while the Global Config Lock 1270c7648810STony Nguyen * in firmware is acquired by the software to prevent most (but not all) types 1271c7648810STony Nguyen * of AQ commands from being sent to FW 1272c7648810STony Nguyen */ 1273c7648810STony Nguyen DEFINE_MUTEX(ice_global_cfg_lock_sw); 1274c7648810STony Nguyen 12757ec59eeaSAnirudh Venkataramanan /** 12767ec59eeaSAnirudh Venkataramanan * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1277f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 12787ec59eeaSAnirudh Venkataramanan * @desc: descriptor describing the command 12797ec59eeaSAnirudh Venkataramanan * @buf: buffer to use for indirect commands (NULL for direct commands) 12807ec59eeaSAnirudh Venkataramanan * @buf_size: size of buffer for indirect commands (0 for direct commands) 12817ec59eeaSAnirudh Venkataramanan * @cd: pointer to command details structure 12827ec59eeaSAnirudh Venkataramanan * 12837ec59eeaSAnirudh Venkataramanan * Helper function to send FW Admin Queue commands to the FW Admin Queue. 12847ec59eeaSAnirudh Venkataramanan */ 12857ec59eeaSAnirudh Venkataramanan enum ice_status 12867ec59eeaSAnirudh Venkataramanan ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 12877ec59eeaSAnirudh Venkataramanan u16 buf_size, struct ice_sq_cd *cd) 12887ec59eeaSAnirudh Venkataramanan { 1289c7648810STony Nguyen struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1290c7648810STony Nguyen bool lock_acquired = false; 1291c7648810STony Nguyen enum ice_status status; 1292c7648810STony Nguyen 1293c7648810STony Nguyen /* When a package download is in process (i.e. when the firmware's 1294c7648810STony Nguyen * Global Configuration Lock resource is held), only the Download 1295c7648810STony Nguyen * Package, Get Version, Get Package Info List and Release Resource 1296c7648810STony Nguyen * (with resource ID set to Global Config Lock) AdminQ commands are 1297c7648810STony Nguyen * allowed; all others must block until the package download completes 1298c7648810STony Nguyen * and the Global Config Lock is released. See also 1299c7648810STony Nguyen * ice_acquire_global_cfg_lock(). 1300c7648810STony Nguyen */ 1301c7648810STony Nguyen switch (le16_to_cpu(desc->opcode)) { 1302c7648810STony Nguyen case ice_aqc_opc_download_pkg: 1303c7648810STony Nguyen case ice_aqc_opc_get_pkg_info_list: 1304c7648810STony Nguyen case ice_aqc_opc_get_ver: 1305c7648810STony Nguyen break; 1306c7648810STony Nguyen case ice_aqc_opc_release_res: 1307c7648810STony Nguyen if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1308c7648810STony Nguyen break; 13094e83fc93SBruce Allan fallthrough; 1310c7648810STony Nguyen default: 1311c7648810STony Nguyen mutex_lock(&ice_global_cfg_lock_sw); 1312c7648810STony Nguyen lock_acquired = true; 1313c7648810STony Nguyen break; 1314c7648810STony Nguyen } 1315c7648810STony Nguyen 1316c7648810STony Nguyen status = ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); 1317c7648810STony Nguyen if (lock_acquired) 1318c7648810STony Nguyen mutex_unlock(&ice_global_cfg_lock_sw); 1319c7648810STony Nguyen 1320c7648810STony Nguyen return status; 13217ec59eeaSAnirudh Venkataramanan } 13227ec59eeaSAnirudh Venkataramanan 13237ec59eeaSAnirudh Venkataramanan /** 13247ec59eeaSAnirudh Venkataramanan * ice_aq_get_fw_ver 1325f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 13267ec59eeaSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 13277ec59eeaSAnirudh Venkataramanan * 13287ec59eeaSAnirudh Venkataramanan * Get the firmware version (0x0001) from the admin queue commands 13297ec59eeaSAnirudh Venkataramanan */ 13307ec59eeaSAnirudh Venkataramanan enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 13317ec59eeaSAnirudh Venkataramanan { 13327ec59eeaSAnirudh Venkataramanan struct ice_aqc_get_ver *resp; 13337ec59eeaSAnirudh Venkataramanan struct ice_aq_desc desc; 13347ec59eeaSAnirudh Venkataramanan enum ice_status status; 13357ec59eeaSAnirudh Venkataramanan 13367ec59eeaSAnirudh Venkataramanan resp = &desc.params.get_ver; 13377ec59eeaSAnirudh Venkataramanan 13387ec59eeaSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 13397ec59eeaSAnirudh Venkataramanan 13407ec59eeaSAnirudh Venkataramanan status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 13417ec59eeaSAnirudh Venkataramanan 13427ec59eeaSAnirudh Venkataramanan if (!status) { 13437ec59eeaSAnirudh Venkataramanan hw->fw_branch = resp->fw_branch; 13447ec59eeaSAnirudh Venkataramanan hw->fw_maj_ver = resp->fw_major; 13457ec59eeaSAnirudh Venkataramanan hw->fw_min_ver = resp->fw_minor; 13467ec59eeaSAnirudh Venkataramanan hw->fw_patch = resp->fw_patch; 13477ec59eeaSAnirudh Venkataramanan hw->fw_build = le32_to_cpu(resp->fw_build); 13487ec59eeaSAnirudh Venkataramanan hw->api_branch = resp->api_branch; 13497ec59eeaSAnirudh Venkataramanan hw->api_maj_ver = resp->api_major; 13507ec59eeaSAnirudh Venkataramanan hw->api_min_ver = resp->api_minor; 13517ec59eeaSAnirudh Venkataramanan hw->api_patch = resp->api_patch; 13527ec59eeaSAnirudh Venkataramanan } 13537ec59eeaSAnirudh Venkataramanan 13547ec59eeaSAnirudh Venkataramanan return status; 13557ec59eeaSAnirudh Venkataramanan } 13567ec59eeaSAnirudh Venkataramanan 13577ec59eeaSAnirudh Venkataramanan /** 1358e3710a01SPaul M Stillwell Jr * ice_aq_send_driver_ver 1359e3710a01SPaul M Stillwell Jr * @hw: pointer to the HW struct 1360e3710a01SPaul M Stillwell Jr * @dv: driver's major, minor version 1361e3710a01SPaul M Stillwell Jr * @cd: pointer to command details structure or NULL 1362e3710a01SPaul M Stillwell Jr * 1363e3710a01SPaul M Stillwell Jr * Send the driver version (0x0002) to the firmware 1364e3710a01SPaul M Stillwell Jr */ 1365e3710a01SPaul M Stillwell Jr enum ice_status 1366e3710a01SPaul M Stillwell Jr ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1367e3710a01SPaul M Stillwell Jr struct ice_sq_cd *cd) 1368e3710a01SPaul M Stillwell Jr { 1369e3710a01SPaul M Stillwell Jr struct ice_aqc_driver_ver *cmd; 1370e3710a01SPaul M Stillwell Jr struct ice_aq_desc desc; 1371e3710a01SPaul M Stillwell Jr u16 len; 1372e3710a01SPaul M Stillwell Jr 1373e3710a01SPaul M Stillwell Jr cmd = &desc.params.driver_ver; 1374e3710a01SPaul M Stillwell Jr 1375e3710a01SPaul M Stillwell Jr if (!dv) 1376e3710a01SPaul M Stillwell Jr return ICE_ERR_PARAM; 1377e3710a01SPaul M Stillwell Jr 1378e3710a01SPaul M Stillwell Jr ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1379e3710a01SPaul M Stillwell Jr 1380e3710a01SPaul M Stillwell Jr desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1381e3710a01SPaul M Stillwell Jr cmd->major_ver = dv->major_ver; 1382e3710a01SPaul M Stillwell Jr cmd->minor_ver = dv->minor_ver; 1383e3710a01SPaul M Stillwell Jr cmd->build_ver = dv->build_ver; 1384e3710a01SPaul M Stillwell Jr cmd->subbuild_ver = dv->subbuild_ver; 1385e3710a01SPaul M Stillwell Jr 1386e3710a01SPaul M Stillwell Jr len = 0; 1387e3710a01SPaul M Stillwell Jr while (len < sizeof(dv->driver_string) && 1388e3710a01SPaul M Stillwell Jr isascii(dv->driver_string[len]) && dv->driver_string[len]) 1389e3710a01SPaul M Stillwell Jr len++; 1390e3710a01SPaul M Stillwell Jr 1391e3710a01SPaul M Stillwell Jr return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1392e3710a01SPaul M Stillwell Jr } 1393e3710a01SPaul M Stillwell Jr 1394e3710a01SPaul M Stillwell Jr /** 13957ec59eeaSAnirudh Venkataramanan * ice_aq_q_shutdown 1396f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 13977ec59eeaSAnirudh Venkataramanan * @unloading: is the driver unloading itself 13987ec59eeaSAnirudh Venkataramanan * 13997ec59eeaSAnirudh Venkataramanan * Tell the Firmware that we're shutting down the AdminQ and whether 14007ec59eeaSAnirudh Venkataramanan * or not the driver is unloading as well (0x0003). 14017ec59eeaSAnirudh Venkataramanan */ 14027ec59eeaSAnirudh Venkataramanan enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 14037ec59eeaSAnirudh Venkataramanan { 14047ec59eeaSAnirudh Venkataramanan struct ice_aqc_q_shutdown *cmd; 14057ec59eeaSAnirudh Venkataramanan struct ice_aq_desc desc; 14067ec59eeaSAnirudh Venkataramanan 14077ec59eeaSAnirudh Venkataramanan cmd = &desc.params.q_shutdown; 14087ec59eeaSAnirudh Venkataramanan 14097ec59eeaSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 14107ec59eeaSAnirudh Venkataramanan 14117ec59eeaSAnirudh Venkataramanan if (unloading) 14127404e84aSBruce Allan cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 14137ec59eeaSAnirudh Venkataramanan 14147ec59eeaSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 14157ec59eeaSAnirudh Venkataramanan } 1416f31e4b6fSAnirudh Venkataramanan 1417f31e4b6fSAnirudh Venkataramanan /** 1418f31e4b6fSAnirudh Venkataramanan * ice_aq_req_res 1419f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 1420f9867df6SAnirudh Venkataramanan * @res: resource ID 1421f31e4b6fSAnirudh Venkataramanan * @access: access type 1422f31e4b6fSAnirudh Venkataramanan * @sdp_number: resource number 1423f31e4b6fSAnirudh Venkataramanan * @timeout: the maximum time in ms that the driver may hold the resource 1424f31e4b6fSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 1425f31e4b6fSAnirudh Venkataramanan * 1426ff2b1321SDan Nowlin * Requests common resource using the admin queue commands (0x0008). 1427ff2b1321SDan Nowlin * When attempting to acquire the Global Config Lock, the driver can 1428ff2b1321SDan Nowlin * learn of three states: 1429ff2b1321SDan Nowlin * 1) ICE_SUCCESS - acquired lock, and can perform download package 1430ff2b1321SDan Nowlin * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1431ff2b1321SDan Nowlin * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1432ff2b1321SDan Nowlin * successfully downloaded the package; the driver does 1433ff2b1321SDan Nowlin * not have to download the package and can continue 1434ff2b1321SDan Nowlin * loading 1435ff2b1321SDan Nowlin * 1436ff2b1321SDan Nowlin * Note that if the caller is in an acquire lock, perform action, release lock 1437ff2b1321SDan Nowlin * phase of operation, it is possible that the FW may detect a timeout and issue 1438ff2b1321SDan Nowlin * a CORER. In this case, the driver will receive a CORER interrupt and will 1439ff2b1321SDan Nowlin * have to determine its cause. The calling thread that is handling this flow 1440ff2b1321SDan Nowlin * will likely get an error propagated back to it indicating the Download 1441ff2b1321SDan Nowlin * Package, Update Package or the Release Resource AQ commands timed out. 1442f31e4b6fSAnirudh Venkataramanan */ 1443f31e4b6fSAnirudh Venkataramanan static enum ice_status 1444f31e4b6fSAnirudh Venkataramanan ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1445f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1446f31e4b6fSAnirudh Venkataramanan struct ice_sq_cd *cd) 1447f31e4b6fSAnirudh Venkataramanan { 1448f31e4b6fSAnirudh Venkataramanan struct ice_aqc_req_res *cmd_resp; 1449f31e4b6fSAnirudh Venkataramanan struct ice_aq_desc desc; 1450f31e4b6fSAnirudh Venkataramanan enum ice_status status; 1451f31e4b6fSAnirudh Venkataramanan 1452f31e4b6fSAnirudh Venkataramanan cmd_resp = &desc.params.res_owner; 1453f31e4b6fSAnirudh Venkataramanan 1454f31e4b6fSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1455f31e4b6fSAnirudh Venkataramanan 1456f31e4b6fSAnirudh Venkataramanan cmd_resp->res_id = cpu_to_le16(res); 1457f31e4b6fSAnirudh Venkataramanan cmd_resp->access_type = cpu_to_le16(access); 1458f31e4b6fSAnirudh Venkataramanan cmd_resp->res_number = cpu_to_le32(sdp_number); 1459ff2b1321SDan Nowlin cmd_resp->timeout = cpu_to_le32(*timeout); 1460ff2b1321SDan Nowlin *timeout = 0; 1461f31e4b6fSAnirudh Venkataramanan 1462f31e4b6fSAnirudh Venkataramanan status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1463ff2b1321SDan Nowlin 1464f31e4b6fSAnirudh Venkataramanan /* The completion specifies the maximum time in ms that the driver 1465f31e4b6fSAnirudh Venkataramanan * may hold the resource in the Timeout field. 1466ff2b1321SDan Nowlin */ 1467ff2b1321SDan Nowlin 1468ff2b1321SDan Nowlin /* Global config lock response utilizes an additional status field. 1469ff2b1321SDan Nowlin * 1470ff2b1321SDan Nowlin * If the Global config lock resource is held by some other driver, the 1471ff2b1321SDan Nowlin * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1472ff2b1321SDan Nowlin * and the timeout field indicates the maximum time the current owner 1473ff2b1321SDan Nowlin * of the resource has to free it. 1474ff2b1321SDan Nowlin */ 1475ff2b1321SDan Nowlin if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1476ff2b1321SDan Nowlin if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1477ff2b1321SDan Nowlin *timeout = le32_to_cpu(cmd_resp->timeout); 1478ff2b1321SDan Nowlin return 0; 1479ff2b1321SDan Nowlin } else if (le16_to_cpu(cmd_resp->status) == 1480ff2b1321SDan Nowlin ICE_AQ_RES_GLBL_IN_PROG) { 1481ff2b1321SDan Nowlin *timeout = le32_to_cpu(cmd_resp->timeout); 1482ff2b1321SDan Nowlin return ICE_ERR_AQ_ERROR; 1483ff2b1321SDan Nowlin } else if (le16_to_cpu(cmd_resp->status) == 1484ff2b1321SDan Nowlin ICE_AQ_RES_GLBL_DONE) { 1485ff2b1321SDan Nowlin return ICE_ERR_AQ_NO_WORK; 1486ff2b1321SDan Nowlin } 1487ff2b1321SDan Nowlin 1488ff2b1321SDan Nowlin /* invalid FW response, force a timeout immediately */ 1489ff2b1321SDan Nowlin *timeout = 0; 1490ff2b1321SDan Nowlin return ICE_ERR_AQ_ERROR; 1491ff2b1321SDan Nowlin } 1492ff2b1321SDan Nowlin 1493ff2b1321SDan Nowlin /* If the resource is held by some other driver, the command completes 1494ff2b1321SDan Nowlin * with a busy return value and the timeout field indicates the maximum 1495ff2b1321SDan Nowlin * time the current owner of the resource has to free it. 1496f31e4b6fSAnirudh Venkataramanan */ 1497f31e4b6fSAnirudh Venkataramanan if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1498f31e4b6fSAnirudh Venkataramanan *timeout = le32_to_cpu(cmd_resp->timeout); 1499f31e4b6fSAnirudh Venkataramanan 1500f31e4b6fSAnirudh Venkataramanan return status; 1501f31e4b6fSAnirudh Venkataramanan } 1502f31e4b6fSAnirudh Venkataramanan 1503f31e4b6fSAnirudh Venkataramanan /** 1504f31e4b6fSAnirudh Venkataramanan * ice_aq_release_res 1505f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 1506f9867df6SAnirudh Venkataramanan * @res: resource ID 1507f31e4b6fSAnirudh Venkataramanan * @sdp_number: resource number 1508f31e4b6fSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 1509f31e4b6fSAnirudh Venkataramanan * 1510f31e4b6fSAnirudh Venkataramanan * release common resource using the admin queue commands (0x0009) 1511f31e4b6fSAnirudh Venkataramanan */ 1512f31e4b6fSAnirudh Venkataramanan static enum ice_status 1513f31e4b6fSAnirudh Venkataramanan ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1514f31e4b6fSAnirudh Venkataramanan struct ice_sq_cd *cd) 1515f31e4b6fSAnirudh Venkataramanan { 1516f31e4b6fSAnirudh Venkataramanan struct ice_aqc_req_res *cmd; 1517f31e4b6fSAnirudh Venkataramanan struct ice_aq_desc desc; 1518f31e4b6fSAnirudh Venkataramanan 1519f31e4b6fSAnirudh Venkataramanan cmd = &desc.params.res_owner; 1520f31e4b6fSAnirudh Venkataramanan 1521f31e4b6fSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1522f31e4b6fSAnirudh Venkataramanan 1523f31e4b6fSAnirudh Venkataramanan cmd->res_id = cpu_to_le16(res); 1524f31e4b6fSAnirudh Venkataramanan cmd->res_number = cpu_to_le32(sdp_number); 1525f31e4b6fSAnirudh Venkataramanan 1526f31e4b6fSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1527f31e4b6fSAnirudh Venkataramanan } 1528f31e4b6fSAnirudh Venkataramanan 1529f31e4b6fSAnirudh Venkataramanan /** 1530f31e4b6fSAnirudh Venkataramanan * ice_acquire_res 1531f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the HW structure 1532f9867df6SAnirudh Venkataramanan * @res: resource ID 1533f31e4b6fSAnirudh Venkataramanan * @access: access type (read or write) 1534ff2b1321SDan Nowlin * @timeout: timeout in milliseconds 1535f31e4b6fSAnirudh Venkataramanan * 1536f31e4b6fSAnirudh Venkataramanan * This function will attempt to acquire the ownership of a resource. 1537f31e4b6fSAnirudh Venkataramanan */ 1538f31e4b6fSAnirudh Venkataramanan enum ice_status 1539f31e4b6fSAnirudh Venkataramanan ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1540ff2b1321SDan Nowlin enum ice_aq_res_access_type access, u32 timeout) 1541f31e4b6fSAnirudh Venkataramanan { 1542f31e4b6fSAnirudh Venkataramanan #define ICE_RES_POLLING_DELAY_MS 10 1543f31e4b6fSAnirudh Venkataramanan u32 delay = ICE_RES_POLLING_DELAY_MS; 1544ff2b1321SDan Nowlin u32 time_left = timeout; 1545f31e4b6fSAnirudh Venkataramanan enum ice_status status; 1546f31e4b6fSAnirudh Venkataramanan 1547f31e4b6fSAnirudh Venkataramanan status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1548f31e4b6fSAnirudh Venkataramanan 1549ff2b1321SDan Nowlin /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1550ff2b1321SDan Nowlin * previously acquired the resource and performed any necessary updates; 1551ff2b1321SDan Nowlin * in this case the caller does not obtain the resource and has no 1552ff2b1321SDan Nowlin * further work to do. 1553f31e4b6fSAnirudh Venkataramanan */ 1554ff2b1321SDan Nowlin if (status == ICE_ERR_AQ_NO_WORK) 1555f31e4b6fSAnirudh Venkataramanan goto ice_acquire_res_exit; 1556f31e4b6fSAnirudh Venkataramanan 1557f31e4b6fSAnirudh Venkataramanan if (status) 1558f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_RES, 1559f31e4b6fSAnirudh Venkataramanan "resource %d acquire type %d failed.\n", res, access); 1560f31e4b6fSAnirudh Venkataramanan 1561f31e4b6fSAnirudh Venkataramanan /* If necessary, poll until the current lock owner timeouts */ 1562f31e4b6fSAnirudh Venkataramanan timeout = time_left; 1563f31e4b6fSAnirudh Venkataramanan while (status && timeout && time_left) { 1564f31e4b6fSAnirudh Venkataramanan mdelay(delay); 1565f31e4b6fSAnirudh Venkataramanan timeout = (timeout > delay) ? timeout - delay : 0; 1566f31e4b6fSAnirudh Venkataramanan status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1567f31e4b6fSAnirudh Venkataramanan 1568ff2b1321SDan Nowlin if (status == ICE_ERR_AQ_NO_WORK) 1569f31e4b6fSAnirudh Venkataramanan /* lock free, but no work to do */ 1570f31e4b6fSAnirudh Venkataramanan break; 1571f31e4b6fSAnirudh Venkataramanan 1572f31e4b6fSAnirudh Venkataramanan if (!status) 1573f31e4b6fSAnirudh Venkataramanan /* lock acquired */ 1574f31e4b6fSAnirudh Venkataramanan break; 1575f31e4b6fSAnirudh Venkataramanan } 1576f31e4b6fSAnirudh Venkataramanan if (status && status != ICE_ERR_AQ_NO_WORK) 1577f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1578f31e4b6fSAnirudh Venkataramanan 1579f31e4b6fSAnirudh Venkataramanan ice_acquire_res_exit: 1580f31e4b6fSAnirudh Venkataramanan if (status == ICE_ERR_AQ_NO_WORK) { 1581f31e4b6fSAnirudh Venkataramanan if (access == ICE_RES_WRITE) 1582f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_RES, 1583f31e4b6fSAnirudh Venkataramanan "resource indicates no work to do.\n"); 1584f31e4b6fSAnirudh Venkataramanan else 1585f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_RES, 1586f31e4b6fSAnirudh Venkataramanan "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1587f31e4b6fSAnirudh Venkataramanan } 1588f31e4b6fSAnirudh Venkataramanan return status; 1589f31e4b6fSAnirudh Venkataramanan } 1590f31e4b6fSAnirudh Venkataramanan 1591f31e4b6fSAnirudh Venkataramanan /** 1592f31e4b6fSAnirudh Venkataramanan * ice_release_res 1593f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the HW structure 1594f9867df6SAnirudh Venkataramanan * @res: resource ID 1595f31e4b6fSAnirudh Venkataramanan * 1596f31e4b6fSAnirudh Venkataramanan * This function will release a resource using the proper Admin Command. 1597f31e4b6fSAnirudh Venkataramanan */ 1598f31e4b6fSAnirudh Venkataramanan void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1599f31e4b6fSAnirudh Venkataramanan { 1600f31e4b6fSAnirudh Venkataramanan enum ice_status status; 1601f31e4b6fSAnirudh Venkataramanan u32 total_delay = 0; 1602f31e4b6fSAnirudh Venkataramanan 1603f31e4b6fSAnirudh Venkataramanan status = ice_aq_release_res(hw, res, 0, NULL); 1604f31e4b6fSAnirudh Venkataramanan 1605f31e4b6fSAnirudh Venkataramanan /* there are some rare cases when trying to release the resource 1606f9867df6SAnirudh Venkataramanan * results in an admin queue timeout, so handle them correctly 1607f31e4b6fSAnirudh Venkataramanan */ 1608f31e4b6fSAnirudh Venkataramanan while ((status == ICE_ERR_AQ_TIMEOUT) && 1609f31e4b6fSAnirudh Venkataramanan (total_delay < hw->adminq.sq_cmd_timeout)) { 1610f31e4b6fSAnirudh Venkataramanan mdelay(1); 1611f31e4b6fSAnirudh Venkataramanan status = ice_aq_release_res(hw, res, 0, NULL); 1612f31e4b6fSAnirudh Venkataramanan total_delay++; 1613f31e4b6fSAnirudh Venkataramanan } 1614f31e4b6fSAnirudh Venkataramanan } 1615f31e4b6fSAnirudh Venkataramanan 1616f31e4b6fSAnirudh Venkataramanan /** 161731ad4e4eSTony Nguyen * ice_aq_alloc_free_res - command to allocate/free resources 161831ad4e4eSTony Nguyen * @hw: pointer to the HW struct 161931ad4e4eSTony Nguyen * @num_entries: number of resource entries in buffer 162031ad4e4eSTony Nguyen * @buf: Indirect buffer to hold data parameters and response 162131ad4e4eSTony Nguyen * @buf_size: size of buffer for indirect commands 162231ad4e4eSTony Nguyen * @opc: pass in the command opcode 162331ad4e4eSTony Nguyen * @cd: pointer to command details structure or NULL 162431ad4e4eSTony Nguyen * 162531ad4e4eSTony Nguyen * Helper function to allocate/free resources using the admin queue commands 162631ad4e4eSTony Nguyen */ 162731ad4e4eSTony Nguyen enum ice_status 162831ad4e4eSTony Nguyen ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 162931ad4e4eSTony Nguyen struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 163031ad4e4eSTony Nguyen enum ice_adminq_opc opc, struct ice_sq_cd *cd) 163131ad4e4eSTony Nguyen { 163231ad4e4eSTony Nguyen struct ice_aqc_alloc_free_res_cmd *cmd; 163331ad4e4eSTony Nguyen struct ice_aq_desc desc; 163431ad4e4eSTony Nguyen 163531ad4e4eSTony Nguyen cmd = &desc.params.sw_res_ctrl; 163631ad4e4eSTony Nguyen 163731ad4e4eSTony Nguyen if (!buf) 163831ad4e4eSTony Nguyen return ICE_ERR_PARAM; 163931ad4e4eSTony Nguyen 164031ad4e4eSTony Nguyen if (buf_size < (num_entries * sizeof(buf->elem[0]))) 164131ad4e4eSTony Nguyen return ICE_ERR_PARAM; 164231ad4e4eSTony Nguyen 164331ad4e4eSTony Nguyen ice_fill_dflt_direct_cmd_desc(&desc, opc); 164431ad4e4eSTony Nguyen 164531ad4e4eSTony Nguyen desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 164631ad4e4eSTony Nguyen 164731ad4e4eSTony Nguyen cmd->num_entries = cpu_to_le16(num_entries); 164831ad4e4eSTony Nguyen 164931ad4e4eSTony Nguyen return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 165031ad4e4eSTony Nguyen } 165131ad4e4eSTony Nguyen 165231ad4e4eSTony Nguyen /** 165331ad4e4eSTony Nguyen * ice_alloc_hw_res - allocate resource 165431ad4e4eSTony Nguyen * @hw: pointer to the HW struct 165531ad4e4eSTony Nguyen * @type: type of resource 165631ad4e4eSTony Nguyen * @num: number of resources to allocate 165731ad4e4eSTony Nguyen * @btm: allocate from bottom 165831ad4e4eSTony Nguyen * @res: pointer to array that will receive the resources 165931ad4e4eSTony Nguyen */ 166031ad4e4eSTony Nguyen enum ice_status 166131ad4e4eSTony Nguyen ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 166231ad4e4eSTony Nguyen { 166331ad4e4eSTony Nguyen struct ice_aqc_alloc_free_res_elem *buf; 166431ad4e4eSTony Nguyen enum ice_status status; 166531ad4e4eSTony Nguyen u16 buf_len; 166631ad4e4eSTony Nguyen 166766486d89SBruce Allan buf_len = struct_size(buf, elem, num); 166831ad4e4eSTony Nguyen buf = kzalloc(buf_len, GFP_KERNEL); 166931ad4e4eSTony Nguyen if (!buf) 167031ad4e4eSTony Nguyen return ICE_ERR_NO_MEMORY; 167131ad4e4eSTony Nguyen 167231ad4e4eSTony Nguyen /* Prepare buffer to allocate resource. */ 167331ad4e4eSTony Nguyen buf->num_elems = cpu_to_le16(num); 167431ad4e4eSTony Nguyen buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 167531ad4e4eSTony Nguyen ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 167631ad4e4eSTony Nguyen if (btm) 167731ad4e4eSTony Nguyen buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 167831ad4e4eSTony Nguyen 167931ad4e4eSTony Nguyen status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 168031ad4e4eSTony Nguyen ice_aqc_opc_alloc_res, NULL); 168131ad4e4eSTony Nguyen if (status) 168231ad4e4eSTony Nguyen goto ice_alloc_res_exit; 168331ad4e4eSTony Nguyen 168466486d89SBruce Allan memcpy(res, buf->elem, sizeof(*buf->elem) * num); 168531ad4e4eSTony Nguyen 168631ad4e4eSTony Nguyen ice_alloc_res_exit: 168731ad4e4eSTony Nguyen kfree(buf); 168831ad4e4eSTony Nguyen return status; 168931ad4e4eSTony Nguyen } 169031ad4e4eSTony Nguyen 169131ad4e4eSTony Nguyen /** 1692451f2c44STony Nguyen * ice_free_hw_res - free allocated HW resource 1693451f2c44STony Nguyen * @hw: pointer to the HW struct 1694451f2c44STony Nguyen * @type: type of resource to free 1695451f2c44STony Nguyen * @num: number of resources 1696451f2c44STony Nguyen * @res: pointer to array that contains the resources to free 1697451f2c44STony Nguyen */ 1698451f2c44STony Nguyen enum ice_status 1699451f2c44STony Nguyen ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1700451f2c44STony Nguyen { 1701451f2c44STony Nguyen struct ice_aqc_alloc_free_res_elem *buf; 1702451f2c44STony Nguyen enum ice_status status; 1703451f2c44STony Nguyen u16 buf_len; 1704451f2c44STony Nguyen 170566486d89SBruce Allan buf_len = struct_size(buf, elem, num); 1706451f2c44STony Nguyen buf = kzalloc(buf_len, GFP_KERNEL); 1707451f2c44STony Nguyen if (!buf) 1708451f2c44STony Nguyen return ICE_ERR_NO_MEMORY; 1709451f2c44STony Nguyen 1710451f2c44STony Nguyen /* Prepare buffer to free resource. */ 1711451f2c44STony Nguyen buf->num_elems = cpu_to_le16(num); 1712451f2c44STony Nguyen buf->res_type = cpu_to_le16(type); 171366486d89SBruce Allan memcpy(buf->elem, res, sizeof(*buf->elem) * num); 1714451f2c44STony Nguyen 1715451f2c44STony Nguyen status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1716451f2c44STony Nguyen ice_aqc_opc_free_res, NULL); 1717451f2c44STony Nguyen if (status) 1718451f2c44STony Nguyen ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1719451f2c44STony Nguyen 1720451f2c44STony Nguyen kfree(buf); 1721451f2c44STony Nguyen return status; 1722451f2c44STony Nguyen } 1723451f2c44STony Nguyen 1724451f2c44STony Nguyen /** 17257a1f7111SBrett Creeley * ice_get_num_per_func - determine number of resources per PF 1726f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW structure 17277a1f7111SBrett Creeley * @max: value to be evenly split between each PF 1728995c90f2SAnirudh Venkataramanan * 1729995c90f2SAnirudh Venkataramanan * Determine the number of valid functions by going through the bitmap returned 17307a1f7111SBrett Creeley * from parsing capabilities and use this to calculate the number of resources 17317a1f7111SBrett Creeley * per PF based on the max value passed in. 1732995c90f2SAnirudh Venkataramanan */ 17337a1f7111SBrett Creeley static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1734995c90f2SAnirudh Venkataramanan { 1735995c90f2SAnirudh Venkataramanan u8 funcs; 1736995c90f2SAnirudh Venkataramanan 1737995c90f2SAnirudh Venkataramanan #define ICE_CAPS_VALID_FUNCS_M 0xFF 1738995c90f2SAnirudh Venkataramanan funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 1739995c90f2SAnirudh Venkataramanan ICE_CAPS_VALID_FUNCS_M); 1740995c90f2SAnirudh Venkataramanan 1741995c90f2SAnirudh Venkataramanan if (!funcs) 1742995c90f2SAnirudh Venkataramanan return 0; 1743995c90f2SAnirudh Venkataramanan 17447a1f7111SBrett Creeley return max / funcs; 1745995c90f2SAnirudh Venkataramanan } 1746995c90f2SAnirudh Venkataramanan 1747995c90f2SAnirudh Venkataramanan /** 1748595b13e2SJacob Keller * ice_parse_common_caps - parse common device/function capabilities 1749f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 1750595b13e2SJacob Keller * @caps: pointer to common capabilities structure 1751595b13e2SJacob Keller * @elem: the capability element to parse 1752595b13e2SJacob Keller * @prefix: message prefix for tracing capabilities 17539c20346bSAnirudh Venkataramanan * 1754595b13e2SJacob Keller * Given a capability element, extract relevant details into the common 1755595b13e2SJacob Keller * capability structure. 1756595b13e2SJacob Keller * 1757595b13e2SJacob Keller * Returns: true if the capability matches one of the common capability ids, 1758595b13e2SJacob Keller * false otherwise. 17599c20346bSAnirudh Venkataramanan */ 1760595b13e2SJacob Keller static bool 1761595b13e2SJacob Keller ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1762595b13e2SJacob Keller struct ice_aqc_list_caps_elem *elem, const char *prefix) 17639c20346bSAnirudh Venkataramanan { 1764595b13e2SJacob Keller u32 logical_id = le32_to_cpu(elem->logical_id); 1765595b13e2SJacob Keller u32 phys_id = le32_to_cpu(elem->phys_id); 1766595b13e2SJacob Keller u32 number = le32_to_cpu(elem->number); 1767595b13e2SJacob Keller u16 cap = le16_to_cpu(elem->cap); 1768595b13e2SJacob Keller bool found = true; 17699c20346bSAnirudh Venkataramanan 17709c20346bSAnirudh Venkataramanan switch (cap) { 1771995c90f2SAnirudh Venkataramanan case ICE_AQC_CAPS_VALID_FUNCTIONS: 1772995c90f2SAnirudh Venkataramanan caps->valid_functions = number; 1773995c90f2SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 17745c875c1aSAnirudh Venkataramanan "%s: valid_functions (bitmap) = %d\n", prefix, 1775995c90f2SAnirudh Venkataramanan caps->valid_functions); 1776995c90f2SAnirudh Venkataramanan break; 177775d2b253SAnirudh Venkataramanan case ICE_AQC_CAPS_SRIOV: 177875d2b253SAnirudh Venkataramanan caps->sr_iov_1_1 = (number == 1); 177975d2b253SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 17805c875c1aSAnirudh Venkataramanan "%s: sr_iov_1_1 = %d\n", prefix, 1781a84db525SAnirudh Venkataramanan caps->sr_iov_1_1); 178275d2b253SAnirudh Venkataramanan break; 1783a257f188SUsha Ketineni case ICE_AQC_CAPS_DCB: 1784a257f188SUsha Ketineni caps->dcb = (number == 1); 1785a257f188SUsha Ketineni caps->active_tc_bitmap = logical_id; 1786a257f188SUsha Ketineni caps->maxtc = phys_id; 1787a257f188SUsha Ketineni ice_debug(hw, ICE_DBG_INIT, 17885c875c1aSAnirudh Venkataramanan "%s: dcb = %d\n", prefix, caps->dcb); 1789a257f188SUsha Ketineni ice_debug(hw, ICE_DBG_INIT, 17905c875c1aSAnirudh Venkataramanan "%s: active_tc_bitmap = %d\n", prefix, 1791a257f188SUsha Ketineni caps->active_tc_bitmap); 1792a257f188SUsha Ketineni ice_debug(hw, ICE_DBG_INIT, 17935c875c1aSAnirudh Venkataramanan "%s: maxtc = %d\n", prefix, caps->maxtc); 1794a257f188SUsha Ketineni break; 17959c20346bSAnirudh Venkataramanan case ICE_AQC_CAPS_RSS: 17969c20346bSAnirudh Venkataramanan caps->rss_table_size = number; 17979c20346bSAnirudh Venkataramanan caps->rss_table_entry_width = logical_id; 17989c20346bSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 17995c875c1aSAnirudh Venkataramanan "%s: rss_table_size = %d\n", prefix, 18009c20346bSAnirudh Venkataramanan caps->rss_table_size); 18019c20346bSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 18025c875c1aSAnirudh Venkataramanan "%s: rss_table_entry_width = %d\n", prefix, 18039c20346bSAnirudh Venkataramanan caps->rss_table_entry_width); 18049c20346bSAnirudh Venkataramanan break; 18059c20346bSAnirudh Venkataramanan case ICE_AQC_CAPS_RXQS: 18069c20346bSAnirudh Venkataramanan caps->num_rxq = number; 18079c20346bSAnirudh Venkataramanan caps->rxq_first_id = phys_id; 18089c20346bSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 18095c875c1aSAnirudh Venkataramanan "%s: num_rxq = %d\n", prefix, 1810a84db525SAnirudh Venkataramanan caps->num_rxq); 18119c20346bSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 18125c875c1aSAnirudh Venkataramanan "%s: rxq_first_id = %d\n", prefix, 18139c20346bSAnirudh Venkataramanan caps->rxq_first_id); 18149c20346bSAnirudh Venkataramanan break; 18159c20346bSAnirudh Venkataramanan case ICE_AQC_CAPS_TXQS: 18169c20346bSAnirudh Venkataramanan caps->num_txq = number; 18179c20346bSAnirudh Venkataramanan caps->txq_first_id = phys_id; 18189c20346bSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 18195c875c1aSAnirudh Venkataramanan "%s: num_txq = %d\n", prefix, 1820a84db525SAnirudh Venkataramanan caps->num_txq); 18219c20346bSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 18225c875c1aSAnirudh Venkataramanan "%s: txq_first_id = %d\n", prefix, 18239c20346bSAnirudh Venkataramanan caps->txq_first_id); 18249c20346bSAnirudh Venkataramanan break; 18259c20346bSAnirudh Venkataramanan case ICE_AQC_CAPS_MSIX: 18269c20346bSAnirudh Venkataramanan caps->num_msix_vectors = number; 18279c20346bSAnirudh Venkataramanan caps->msix_vector_first_id = phys_id; 18289c20346bSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 18295c875c1aSAnirudh Venkataramanan "%s: num_msix_vectors = %d\n", prefix, 18309c20346bSAnirudh Venkataramanan caps->num_msix_vectors); 18319c20346bSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 18325c875c1aSAnirudh Venkataramanan "%s: msix_vector_first_id = %d\n", prefix, 18339c20346bSAnirudh Venkataramanan caps->msix_vector_first_id); 18349c20346bSAnirudh Venkataramanan break; 1835595b13e2SJacob Keller case ICE_AQC_CAPS_MAX_MTU: 1836595b13e2SJacob Keller caps->max_mtu = number; 1837595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 1838595b13e2SJacob Keller prefix, caps->max_mtu); 1839595b13e2SJacob Keller break; 1840595b13e2SJacob Keller default: 1841595b13e2SJacob Keller /* Not one of the recognized common capabilities */ 1842595b13e2SJacob Keller found = false; 1843148beb61SHenry Tieman } 1844595b13e2SJacob Keller 1845595b13e2SJacob Keller return found; 1846595b13e2SJacob Keller } 1847595b13e2SJacob Keller 1848595b13e2SJacob Keller /** 1849595b13e2SJacob Keller * ice_recalc_port_limited_caps - Recalculate port limited capabilities 1850595b13e2SJacob Keller * @hw: pointer to the HW structure 1851595b13e2SJacob Keller * @caps: pointer to capabilities structure to fix 1852595b13e2SJacob Keller * 1853595b13e2SJacob Keller * Re-calculate the capabilities that are dependent on the number of physical 1854595b13e2SJacob Keller * ports; i.e. some features are not supported or function differently on 1855595b13e2SJacob Keller * devices with more than 4 ports. 1856595b13e2SJacob Keller */ 1857595b13e2SJacob Keller static void 1858595b13e2SJacob Keller ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 1859595b13e2SJacob Keller { 1860595b13e2SJacob Keller /* This assumes device capabilities are always scanned before function 1861595b13e2SJacob Keller * capabilities during the initialization flow. 1862595b13e2SJacob Keller */ 1863595b13e2SJacob Keller if (hw->dev_caps.num_funcs > 4) { 1864595b13e2SJacob Keller /* Max 4 TCs per port */ 1865595b13e2SJacob Keller caps->maxtc = 4; 1866595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, 1867595b13e2SJacob Keller "reducing maxtc to %d (based on #ports)\n", 1868595b13e2SJacob Keller caps->maxtc); 1869595b13e2SJacob Keller } 1870595b13e2SJacob Keller } 1871595b13e2SJacob Keller 1872595b13e2SJacob Keller /** 1873595b13e2SJacob Keller * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 1874595b13e2SJacob Keller * @hw: pointer to the HW struct 1875595b13e2SJacob Keller * @func_p: pointer to function capabilities structure 1876595b13e2SJacob Keller * @cap: pointer to the capability element to parse 1877595b13e2SJacob Keller * 1878595b13e2SJacob Keller * Extract function capabilities for ICE_AQC_CAPS_VF. 1879595b13e2SJacob Keller */ 1880595b13e2SJacob Keller static void 1881595b13e2SJacob Keller ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 1882595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap) 1883595b13e2SJacob Keller { 1884595b13e2SJacob Keller u32 logical_id = le32_to_cpu(cap->logical_id); 1885595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number); 1886595b13e2SJacob Keller 1887595b13e2SJacob Keller func_p->num_allocd_vfs = number; 1888595b13e2SJacob Keller func_p->vf_base_id = logical_id; 1889595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 1890595b13e2SJacob Keller func_p->num_allocd_vfs); 1891595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 1892595b13e2SJacob Keller func_p->vf_base_id); 1893595b13e2SJacob Keller } 1894595b13e2SJacob Keller 1895595b13e2SJacob Keller /** 1896595b13e2SJacob Keller * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 1897595b13e2SJacob Keller * @hw: pointer to the HW struct 1898595b13e2SJacob Keller * @func_p: pointer to function capabilities structure 1899595b13e2SJacob Keller * @cap: pointer to the capability element to parse 1900595b13e2SJacob Keller * 1901595b13e2SJacob Keller * Extract function capabilities for ICE_AQC_CAPS_VSI. 1902595b13e2SJacob Keller */ 1903595b13e2SJacob Keller static void 1904595b13e2SJacob Keller ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 1905595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap) 1906595b13e2SJacob Keller { 1907595b13e2SJacob Keller func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 1908595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 1909595b13e2SJacob Keller le32_to_cpu(cap->number)); 1910595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 1911595b13e2SJacob Keller func_p->guar_num_vsi); 1912595b13e2SJacob Keller } 1913595b13e2SJacob Keller 1914595b13e2SJacob Keller /** 1915595b13e2SJacob Keller * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 1916595b13e2SJacob Keller * @hw: pointer to the HW struct 1917595b13e2SJacob Keller * @func_p: pointer to function capabilities structure 1918595b13e2SJacob Keller * 1919595b13e2SJacob Keller * Extract function capabilities for ICE_AQC_CAPS_FD. 1920595b13e2SJacob Keller */ 1921595b13e2SJacob Keller static void 1922595b13e2SJacob Keller ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 1923595b13e2SJacob Keller { 1924148beb61SHenry Tieman u32 reg_val, val; 1925148beb61SHenry Tieman 1926148beb61SHenry Tieman reg_val = rd32(hw, GLQF_FD_SIZE); 1927148beb61SHenry Tieman val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 1928148beb61SHenry Tieman GLQF_FD_SIZE_FD_GSIZE_S; 1929148beb61SHenry Tieman func_p->fd_fltr_guar = 1930148beb61SHenry Tieman ice_get_num_per_func(hw, val); 1931148beb61SHenry Tieman val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 1932148beb61SHenry Tieman GLQF_FD_SIZE_FD_BSIZE_S; 1933148beb61SHenry Tieman func_p->fd_fltr_best_effort = val; 1934595b13e2SJacob Keller 1935148beb61SHenry Tieman ice_debug(hw, ICE_DBG_INIT, 1936595b13e2SJacob Keller "func caps: fd_fltr_guar = %d\n", 1937595b13e2SJacob Keller func_p->fd_fltr_guar); 1938148beb61SHenry Tieman ice_debug(hw, ICE_DBG_INIT, 1939595b13e2SJacob Keller "func caps: fd_fltr_best_effort = %d\n", 1940595b13e2SJacob Keller func_p->fd_fltr_best_effort); 1941148beb61SHenry Tieman } 1942595b13e2SJacob Keller 1943595b13e2SJacob Keller /** 1944595b13e2SJacob Keller * ice_parse_func_caps - Parse function capabilities 1945595b13e2SJacob Keller * @hw: pointer to the HW struct 1946595b13e2SJacob Keller * @func_p: pointer to function capabilities structure 1947595b13e2SJacob Keller * @buf: buffer containing the function capability records 1948595b13e2SJacob Keller * @cap_count: the number of capabilities 1949595b13e2SJacob Keller * 1950595b13e2SJacob Keller * Helper function to parse function (0x000A) capabilities list. For 1951595b13e2SJacob Keller * capabilities shared between device and function, this relies on 1952595b13e2SJacob Keller * ice_parse_common_caps. 1953595b13e2SJacob Keller * 1954595b13e2SJacob Keller * Loop through the list of provided capabilities and extract the relevant 1955595b13e2SJacob Keller * data into the function capabilities structured. 1956595b13e2SJacob Keller */ 1957595b13e2SJacob Keller static void 1958595b13e2SJacob Keller ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 1959595b13e2SJacob Keller void *buf, u32 cap_count) 1960595b13e2SJacob Keller { 1961595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap_resp; 1962595b13e2SJacob Keller u32 i; 1963595b13e2SJacob Keller 1964595b13e2SJacob Keller cap_resp = (struct ice_aqc_list_caps_elem *)buf; 1965595b13e2SJacob Keller 1966595b13e2SJacob Keller memset(func_p, 0, sizeof(*func_p)); 1967595b13e2SJacob Keller 1968595b13e2SJacob Keller for (i = 0; i < cap_count; i++) { 1969595b13e2SJacob Keller u16 cap = le16_to_cpu(cap_resp[i].cap); 1970595b13e2SJacob Keller bool found; 1971595b13e2SJacob Keller 1972595b13e2SJacob Keller found = ice_parse_common_caps(hw, &func_p->common_cap, 1973595b13e2SJacob Keller &cap_resp[i], "func caps"); 1974595b13e2SJacob Keller 1975595b13e2SJacob Keller switch (cap) { 1976595b13e2SJacob Keller case ICE_AQC_CAPS_VF: 1977595b13e2SJacob Keller ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 1978148beb61SHenry Tieman break; 1979595b13e2SJacob Keller case ICE_AQC_CAPS_VSI: 1980595b13e2SJacob Keller ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 1981595b13e2SJacob Keller break; 1982595b13e2SJacob Keller case ICE_AQC_CAPS_FD: 1983595b13e2SJacob Keller ice_parse_fdir_func_caps(hw, func_p); 19849c20346bSAnirudh Venkataramanan break; 19859c20346bSAnirudh Venkataramanan default: 1986595b13e2SJacob Keller /* Don't list common capabilities as unknown */ 1987595b13e2SJacob Keller if (!found) 19889c20346bSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, 1989595b13e2SJacob Keller "func caps: unknown capability[%d]: 0x%x\n", 1990a84db525SAnirudh Venkataramanan i, cap); 19919c20346bSAnirudh Venkataramanan break; 19929c20346bSAnirudh Venkataramanan } 19939c20346bSAnirudh Venkataramanan } 19949164f761SBruce Allan 1995595b13e2SJacob Keller ice_recalc_port_limited_caps(hw, &func_p->common_cap); 19969164f761SBruce Allan } 1997595b13e2SJacob Keller 1998595b13e2SJacob Keller /** 1999595b13e2SJacob Keller * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2000595b13e2SJacob Keller * @hw: pointer to the HW struct 2001595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure 2002595b13e2SJacob Keller * @cap: capability element to parse 2003595b13e2SJacob Keller * 2004595b13e2SJacob Keller * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2005595b13e2SJacob Keller */ 2006595b13e2SJacob Keller static void 2007595b13e2SJacob Keller ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2008595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap) 2009595b13e2SJacob Keller { 2010595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number); 2011595b13e2SJacob Keller 2012595b13e2SJacob Keller dev_p->num_funcs = hweight32(number); 2013595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2014595b13e2SJacob Keller dev_p->num_funcs); 2015595b13e2SJacob Keller } 2016595b13e2SJacob Keller 2017595b13e2SJacob Keller /** 2018595b13e2SJacob Keller * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2019595b13e2SJacob Keller * @hw: pointer to the HW struct 2020595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure 2021595b13e2SJacob Keller * @cap: capability element to parse 2022595b13e2SJacob Keller * 2023595b13e2SJacob Keller * Parse ICE_AQC_CAPS_VF for device capabilities. 2024595b13e2SJacob Keller */ 2025595b13e2SJacob Keller static void 2026595b13e2SJacob Keller ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2027595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap) 2028595b13e2SJacob Keller { 2029595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number); 2030595b13e2SJacob Keller 2031595b13e2SJacob Keller dev_p->num_vfs_exposed = number; 2032595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2033595b13e2SJacob Keller dev_p->num_vfs_exposed); 2034595b13e2SJacob Keller } 2035595b13e2SJacob Keller 2036595b13e2SJacob Keller /** 2037595b13e2SJacob Keller * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2038595b13e2SJacob Keller * @hw: pointer to the HW struct 2039595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure 2040595b13e2SJacob Keller * @cap: capability element to parse 2041595b13e2SJacob Keller * 2042595b13e2SJacob Keller * Parse ICE_AQC_CAPS_VSI for device capabilities. 2043595b13e2SJacob Keller */ 2044595b13e2SJacob Keller static void 2045595b13e2SJacob Keller ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2046595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap) 2047595b13e2SJacob Keller { 2048595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number); 2049595b13e2SJacob Keller 2050595b13e2SJacob Keller dev_p->num_vsi_allocd_to_host = number; 2051595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2052595b13e2SJacob Keller dev_p->num_vsi_allocd_to_host); 2053595b13e2SJacob Keller } 2054595b13e2SJacob Keller 2055595b13e2SJacob Keller /** 2056595b13e2SJacob Keller * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2057595b13e2SJacob Keller * @hw: pointer to the HW struct 2058595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure 2059595b13e2SJacob Keller * @cap: capability element to parse 2060595b13e2SJacob Keller * 2061595b13e2SJacob Keller * Parse ICE_AQC_CAPS_FD for device capabilities. 2062595b13e2SJacob Keller */ 2063595b13e2SJacob Keller static void 2064595b13e2SJacob Keller ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2065595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap) 2066595b13e2SJacob Keller { 2067595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number); 2068595b13e2SJacob Keller 2069595b13e2SJacob Keller dev_p->num_flow_director_fltr = number; 2070595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2071595b13e2SJacob Keller dev_p->num_flow_director_fltr); 2072595b13e2SJacob Keller } 2073595b13e2SJacob Keller 2074595b13e2SJacob Keller /** 2075595b13e2SJacob Keller * ice_parse_dev_caps - Parse device capabilities 2076595b13e2SJacob Keller * @hw: pointer to the HW struct 2077595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure 2078595b13e2SJacob Keller * @buf: buffer containing the device capability records 2079595b13e2SJacob Keller * @cap_count: the number of capabilities 2080595b13e2SJacob Keller * 2081595b13e2SJacob Keller * Helper device to parse device (0x000B) capabilities list. For 2082595b13e2SJacob Keller * capabilities shared between device and device, this relies on 2083595b13e2SJacob Keller * ice_parse_common_caps. 2084595b13e2SJacob Keller * 2085595b13e2SJacob Keller * Loop through the list of provided capabilities and extract the relevant 2086595b13e2SJacob Keller * data into the device capabilities structured. 2087595b13e2SJacob Keller */ 2088595b13e2SJacob Keller static void 2089595b13e2SJacob Keller ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2090595b13e2SJacob Keller void *buf, u32 cap_count) 2091595b13e2SJacob Keller { 2092595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap_resp; 2093595b13e2SJacob Keller u32 i; 2094595b13e2SJacob Keller 2095595b13e2SJacob Keller cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2096595b13e2SJacob Keller 2097595b13e2SJacob Keller memset(dev_p, 0, sizeof(*dev_p)); 2098595b13e2SJacob Keller 2099595b13e2SJacob Keller for (i = 0; i < cap_count; i++) { 2100595b13e2SJacob Keller u16 cap = le16_to_cpu(cap_resp[i].cap); 2101595b13e2SJacob Keller bool found; 2102595b13e2SJacob Keller 2103595b13e2SJacob Keller found = ice_parse_common_caps(hw, &dev_p->common_cap, 2104595b13e2SJacob Keller &cap_resp[i], "dev caps"); 2105595b13e2SJacob Keller 2106595b13e2SJacob Keller switch (cap) { 2107595b13e2SJacob Keller case ICE_AQC_CAPS_VALID_FUNCTIONS: 2108595b13e2SJacob Keller ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2109595b13e2SJacob Keller break; 2110595b13e2SJacob Keller case ICE_AQC_CAPS_VF: 2111595b13e2SJacob Keller ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2112595b13e2SJacob Keller break; 2113595b13e2SJacob Keller case ICE_AQC_CAPS_VSI: 2114595b13e2SJacob Keller ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2115595b13e2SJacob Keller break; 2116595b13e2SJacob Keller case ICE_AQC_CAPS_FD: 2117595b13e2SJacob Keller ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2118595b13e2SJacob Keller break; 2119595b13e2SJacob Keller default: 2120595b13e2SJacob Keller /* Don't list common capabilities as unknown */ 2121595b13e2SJacob Keller if (!found) 2122595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, 2123595b13e2SJacob Keller "dev caps: unknown capability[%d]: 0x%x\n", 2124595b13e2SJacob Keller i, cap); 2125595b13e2SJacob Keller break; 2126595b13e2SJacob Keller } 2127595b13e2SJacob Keller } 2128595b13e2SJacob Keller 2129595b13e2SJacob Keller ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2130595b13e2SJacob Keller } 2131595b13e2SJacob Keller 2132595b13e2SJacob Keller /** 21338d7aab35SJacob Keller * ice_aq_list_caps - query function/device capabilities 2134f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 21358d7aab35SJacob Keller * @buf: a buffer to hold the capabilities 21368d7aab35SJacob Keller * @buf_size: size of the buffer 21378d7aab35SJacob Keller * @cap_count: if not NULL, set to the number of capabilities reported 21388d7aab35SJacob Keller * @opc: capabilities type to discover, device or function 21399c20346bSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 21409c20346bSAnirudh Venkataramanan * 21418d7aab35SJacob Keller * Get the function (0x000A) or device (0x000B) capabilities description from 21428d7aab35SJacob Keller * firmware and store it in the buffer. 21438d7aab35SJacob Keller * 21448d7aab35SJacob Keller * If the cap_count pointer is not NULL, then it is set to the number of 21458d7aab35SJacob Keller * capabilities firmware will report. Note that if the buffer size is too 21468d7aab35SJacob Keller * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 21478d7aab35SJacob Keller * cap_count will still be updated in this case. It is recommended that the 21488d7aab35SJacob Keller * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 21498d7aab35SJacob Keller * firmware could return) to avoid this. 21509c20346bSAnirudh Venkataramanan */ 21518d7aab35SJacob Keller enum ice_status 21528d7aab35SJacob Keller ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 21539c20346bSAnirudh Venkataramanan enum ice_adminq_opc opc, struct ice_sq_cd *cd) 21549c20346bSAnirudh Venkataramanan { 21559c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps *cmd; 21569c20346bSAnirudh Venkataramanan struct ice_aq_desc desc; 21579c20346bSAnirudh Venkataramanan enum ice_status status; 21589c20346bSAnirudh Venkataramanan 21599c20346bSAnirudh Venkataramanan cmd = &desc.params.get_cap; 21609c20346bSAnirudh Venkataramanan 21619c20346bSAnirudh Venkataramanan if (opc != ice_aqc_opc_list_func_caps && 21629c20346bSAnirudh Venkataramanan opc != ice_aqc_opc_list_dev_caps) 21639c20346bSAnirudh Venkataramanan return ICE_ERR_PARAM; 21649c20346bSAnirudh Venkataramanan 21659c20346bSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, opc); 21669c20346bSAnirudh Venkataramanan status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 21678d7aab35SJacob Keller 21688d7aab35SJacob Keller if (cap_count) 216999189e8bSAnirudh Venkataramanan *cap_count = le32_to_cpu(cmd->count); 21708d7aab35SJacob Keller 21718d7aab35SJacob Keller return status; 21728d7aab35SJacob Keller } 21738d7aab35SJacob Keller 21748d7aab35SJacob Keller /** 217581aed647SJacob Keller * ice_discover_dev_caps - Read and extract device capabilities 21767d86cf38SAnirudh Venkataramanan * @hw: pointer to the hardware structure 217781aed647SJacob Keller * @dev_caps: pointer to device capabilities structure 217881aed647SJacob Keller * 217981aed647SJacob Keller * Read the device capabilities and extract them into the dev_caps structure 218081aed647SJacob Keller * for later use. 21817d86cf38SAnirudh Venkataramanan */ 2182c8b7abddSBruce Allan static enum ice_status 218381aed647SJacob Keller ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 21847d86cf38SAnirudh Venkataramanan { 21857d86cf38SAnirudh Venkataramanan enum ice_status status; 218681aed647SJacob Keller u32 cap_count = 0; 21877d86cf38SAnirudh Venkataramanan void *cbuf; 21887d86cf38SAnirudh Venkataramanan 21891082b360SJacob Keller cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 21907d86cf38SAnirudh Venkataramanan if (!cbuf) 21917d86cf38SAnirudh Venkataramanan return ICE_ERR_NO_MEMORY; 21927d86cf38SAnirudh Venkataramanan 21931082b360SJacob Keller /* Although the driver doesn't know the number of capabilities the 21941082b360SJacob Keller * device will return, we can simply send a 4KB buffer, the maximum 21951082b360SJacob Keller * possible size that firmware can return. 21961082b360SJacob Keller */ 21971082b360SJacob Keller cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 21981082b360SJacob Keller 219981aed647SJacob Keller status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 220081aed647SJacob Keller ice_aqc_opc_list_dev_caps, NULL); 220181aed647SJacob Keller if (!status) 220281aed647SJacob Keller ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 220381aed647SJacob Keller kfree(cbuf); 220481aed647SJacob Keller 220581aed647SJacob Keller return status; 220681aed647SJacob Keller } 220781aed647SJacob Keller 220881aed647SJacob Keller /** 220981aed647SJacob Keller * ice_discover_func_caps - Read and extract function capabilities 221081aed647SJacob Keller * @hw: pointer to the hardware structure 221181aed647SJacob Keller * @func_caps: pointer to function capabilities structure 221281aed647SJacob Keller * 221381aed647SJacob Keller * Read the function capabilities and extract them into the func_caps structure 221481aed647SJacob Keller * for later use. 221581aed647SJacob Keller */ 221681aed647SJacob Keller static enum ice_status 221781aed647SJacob Keller ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 221881aed647SJacob Keller { 221981aed647SJacob Keller enum ice_status status; 222081aed647SJacob Keller u32 cap_count = 0; 222181aed647SJacob Keller void *cbuf; 222281aed647SJacob Keller 222381aed647SJacob Keller cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 222481aed647SJacob Keller if (!cbuf) 222581aed647SJacob Keller return ICE_ERR_NO_MEMORY; 222681aed647SJacob Keller 222781aed647SJacob Keller /* Although the driver doesn't know the number of capabilities the 222881aed647SJacob Keller * device will return, we can simply send a 4KB buffer, the maximum 222981aed647SJacob Keller * possible size that firmware can return. 223081aed647SJacob Keller */ 223181aed647SJacob Keller cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 223281aed647SJacob Keller 223381aed647SJacob Keller status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 223481aed647SJacob Keller ice_aqc_opc_list_func_caps, NULL); 223581aed647SJacob Keller if (!status) 223681aed647SJacob Keller ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 22371082b360SJacob Keller kfree(cbuf); 22389c20346bSAnirudh Venkataramanan 22399c20346bSAnirudh Venkataramanan return status; 22409c20346bSAnirudh Venkataramanan } 22419c20346bSAnirudh Venkataramanan 22429c20346bSAnirudh Venkataramanan /** 2243462acf6aSTony Nguyen * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2244462acf6aSTony Nguyen * @hw: pointer to the hardware structure 2245462acf6aSTony Nguyen */ 2246462acf6aSTony Nguyen void ice_set_safe_mode_caps(struct ice_hw *hw) 2247462acf6aSTony Nguyen { 2248462acf6aSTony Nguyen struct ice_hw_func_caps *func_caps = &hw->func_caps; 2249462acf6aSTony Nguyen struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2250462acf6aSTony Nguyen u32 valid_func, rxq_first_id, txq_first_id; 2251462acf6aSTony Nguyen u32 msix_vector_first_id, max_mtu; 2252eae1bbb2SBruce Allan u32 num_funcs; 2253462acf6aSTony Nguyen 2254462acf6aSTony Nguyen /* cache some func_caps values that should be restored after memset */ 2255462acf6aSTony Nguyen valid_func = func_caps->common_cap.valid_functions; 2256462acf6aSTony Nguyen txq_first_id = func_caps->common_cap.txq_first_id; 2257462acf6aSTony Nguyen rxq_first_id = func_caps->common_cap.rxq_first_id; 2258462acf6aSTony Nguyen msix_vector_first_id = func_caps->common_cap.msix_vector_first_id; 2259462acf6aSTony Nguyen max_mtu = func_caps->common_cap.max_mtu; 2260462acf6aSTony Nguyen 2261462acf6aSTony Nguyen /* unset func capabilities */ 2262462acf6aSTony Nguyen memset(func_caps, 0, sizeof(*func_caps)); 2263462acf6aSTony Nguyen 2264462acf6aSTony Nguyen /* restore cached values */ 2265462acf6aSTony Nguyen func_caps->common_cap.valid_functions = valid_func; 2266462acf6aSTony Nguyen func_caps->common_cap.txq_first_id = txq_first_id; 2267462acf6aSTony Nguyen func_caps->common_cap.rxq_first_id = rxq_first_id; 2268462acf6aSTony Nguyen func_caps->common_cap.msix_vector_first_id = msix_vector_first_id; 2269462acf6aSTony Nguyen func_caps->common_cap.max_mtu = max_mtu; 2270462acf6aSTony Nguyen 2271462acf6aSTony Nguyen /* one Tx and one Rx queue in safe mode */ 2272462acf6aSTony Nguyen func_caps->common_cap.num_rxq = 1; 2273462acf6aSTony Nguyen func_caps->common_cap.num_txq = 1; 2274462acf6aSTony Nguyen 2275462acf6aSTony Nguyen /* two MSIX vectors, one for traffic and one for misc causes */ 2276462acf6aSTony Nguyen func_caps->common_cap.num_msix_vectors = 2; 2277462acf6aSTony Nguyen func_caps->guar_num_vsi = 1; 2278462acf6aSTony Nguyen 2279462acf6aSTony Nguyen /* cache some dev_caps values that should be restored after memset */ 2280462acf6aSTony Nguyen valid_func = dev_caps->common_cap.valid_functions; 2281462acf6aSTony Nguyen txq_first_id = dev_caps->common_cap.txq_first_id; 2282462acf6aSTony Nguyen rxq_first_id = dev_caps->common_cap.rxq_first_id; 2283462acf6aSTony Nguyen msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id; 2284462acf6aSTony Nguyen max_mtu = dev_caps->common_cap.max_mtu; 2285eae1bbb2SBruce Allan num_funcs = dev_caps->num_funcs; 2286462acf6aSTony Nguyen 2287462acf6aSTony Nguyen /* unset dev capabilities */ 2288462acf6aSTony Nguyen memset(dev_caps, 0, sizeof(*dev_caps)); 2289462acf6aSTony Nguyen 2290462acf6aSTony Nguyen /* restore cached values */ 2291462acf6aSTony Nguyen dev_caps->common_cap.valid_functions = valid_func; 2292462acf6aSTony Nguyen dev_caps->common_cap.txq_first_id = txq_first_id; 2293462acf6aSTony Nguyen dev_caps->common_cap.rxq_first_id = rxq_first_id; 2294462acf6aSTony Nguyen dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id; 2295462acf6aSTony Nguyen dev_caps->common_cap.max_mtu = max_mtu; 2296eae1bbb2SBruce Allan dev_caps->num_funcs = num_funcs; 2297462acf6aSTony Nguyen 2298462acf6aSTony Nguyen /* one Tx and one Rx queue per function in safe mode */ 2299eae1bbb2SBruce Allan dev_caps->common_cap.num_rxq = num_funcs; 2300eae1bbb2SBruce Allan dev_caps->common_cap.num_txq = num_funcs; 2301462acf6aSTony Nguyen 2302462acf6aSTony Nguyen /* two MSIX vectors per function */ 2303eae1bbb2SBruce Allan dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2304462acf6aSTony Nguyen } 2305462acf6aSTony Nguyen 2306462acf6aSTony Nguyen /** 23079c20346bSAnirudh Venkataramanan * ice_get_caps - get info about the HW 23089c20346bSAnirudh Venkataramanan * @hw: pointer to the hardware structure 23099c20346bSAnirudh Venkataramanan */ 23109c20346bSAnirudh Venkataramanan enum ice_status ice_get_caps(struct ice_hw *hw) 23119c20346bSAnirudh Venkataramanan { 23129c20346bSAnirudh Venkataramanan enum ice_status status; 23139c20346bSAnirudh Venkataramanan 231481aed647SJacob Keller status = ice_discover_dev_caps(hw, &hw->dev_caps); 231581aed647SJacob Keller if (status) 23169c20346bSAnirudh Venkataramanan return status; 231781aed647SJacob Keller 231881aed647SJacob Keller return ice_discover_func_caps(hw, &hw->func_caps); 23199c20346bSAnirudh Venkataramanan } 23209c20346bSAnirudh Venkataramanan 23219c20346bSAnirudh Venkataramanan /** 2322e94d4478SAnirudh Venkataramanan * ice_aq_manage_mac_write - manage MAC address write command 2323f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 2324e94d4478SAnirudh Venkataramanan * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2325e94d4478SAnirudh Venkataramanan * @flags: flags to control write behavior 2326e94d4478SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 2327e94d4478SAnirudh Venkataramanan * 2328e94d4478SAnirudh Venkataramanan * This function is used to write MAC address to the NVM (0x0108). 2329e94d4478SAnirudh Venkataramanan */ 2330e94d4478SAnirudh Venkataramanan enum ice_status 2331d671e3e0SJacob Keller ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2332e94d4478SAnirudh Venkataramanan struct ice_sq_cd *cd) 2333e94d4478SAnirudh Venkataramanan { 2334e94d4478SAnirudh Venkataramanan struct ice_aqc_manage_mac_write *cmd; 2335e94d4478SAnirudh Venkataramanan struct ice_aq_desc desc; 2336e94d4478SAnirudh Venkataramanan 2337e94d4478SAnirudh Venkataramanan cmd = &desc.params.mac_write; 2338e94d4478SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2339e94d4478SAnirudh Venkataramanan 2340e94d4478SAnirudh Venkataramanan cmd->flags = flags; 23415df42c82SJesse Brandeburg ether_addr_copy(cmd->mac_addr, mac_addr); 2342e94d4478SAnirudh Venkataramanan 2343e94d4478SAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2344e94d4478SAnirudh Venkataramanan } 2345e94d4478SAnirudh Venkataramanan 2346e94d4478SAnirudh Venkataramanan /** 2347f31e4b6fSAnirudh Venkataramanan * ice_aq_clear_pxe_mode 2348f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 2349f31e4b6fSAnirudh Venkataramanan * 2350f31e4b6fSAnirudh Venkataramanan * Tell the firmware that the driver is taking over from PXE (0x0110). 2351f31e4b6fSAnirudh Venkataramanan */ 2352f31e4b6fSAnirudh Venkataramanan static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2353f31e4b6fSAnirudh Venkataramanan { 2354f31e4b6fSAnirudh Venkataramanan struct ice_aq_desc desc; 2355f31e4b6fSAnirudh Venkataramanan 2356f31e4b6fSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2357f31e4b6fSAnirudh Venkataramanan desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2358f31e4b6fSAnirudh Venkataramanan 2359f31e4b6fSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2360f31e4b6fSAnirudh Venkataramanan } 2361f31e4b6fSAnirudh Venkataramanan 2362f31e4b6fSAnirudh Venkataramanan /** 2363f31e4b6fSAnirudh Venkataramanan * ice_clear_pxe_mode - clear pxe operations mode 2364f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 2365f31e4b6fSAnirudh Venkataramanan * 2366f31e4b6fSAnirudh Venkataramanan * Make sure all PXE mode settings are cleared, including things 2367f31e4b6fSAnirudh Venkataramanan * like descriptor fetch/write-back mode. 2368f31e4b6fSAnirudh Venkataramanan */ 2369f31e4b6fSAnirudh Venkataramanan void ice_clear_pxe_mode(struct ice_hw *hw) 2370f31e4b6fSAnirudh Venkataramanan { 2371f31e4b6fSAnirudh Venkataramanan if (ice_check_sq_alive(hw, &hw->adminq)) 2372f31e4b6fSAnirudh Venkataramanan ice_aq_clear_pxe_mode(hw); 2373f31e4b6fSAnirudh Venkataramanan } 2374cdedef59SAnirudh Venkataramanan 2375cdedef59SAnirudh Venkataramanan /** 237648cb27f2SChinh Cao * ice_get_link_speed_based_on_phy_type - returns link speed 237748cb27f2SChinh Cao * @phy_type_low: lower part of phy_type 2378aef74145SAnirudh Venkataramanan * @phy_type_high: higher part of phy_type 237948cb27f2SChinh Cao * 2380f9867df6SAnirudh Venkataramanan * This helper function will convert an entry in PHY type structure 2381aef74145SAnirudh Venkataramanan * [phy_type_low, phy_type_high] to its corresponding link speed. 2382aef74145SAnirudh Venkataramanan * Note: In the structure of [phy_type_low, phy_type_high], there should 2383f9867df6SAnirudh Venkataramanan * be one bit set, as this function will convert one PHY type to its 238448cb27f2SChinh Cao * speed. 238548cb27f2SChinh Cao * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 238648cb27f2SChinh Cao * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 238748cb27f2SChinh Cao */ 2388aef74145SAnirudh Venkataramanan static u16 2389aef74145SAnirudh Venkataramanan ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 239048cb27f2SChinh Cao { 2391aef74145SAnirudh Venkataramanan u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 239248cb27f2SChinh Cao u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 239348cb27f2SChinh Cao 239448cb27f2SChinh Cao switch (phy_type_low) { 239548cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_100BASE_TX: 239648cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_100M_SGMII: 239748cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 239848cb27f2SChinh Cao break; 239948cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1000BASE_T: 240048cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1000BASE_SX: 240148cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1000BASE_LX: 240248cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1000BASE_KX: 240348cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1G_SGMII: 240448cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 240548cb27f2SChinh Cao break; 240648cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_2500BASE_T: 240748cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_2500BASE_X: 240848cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_2500BASE_KX: 240948cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 241048cb27f2SChinh Cao break; 241148cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_5GBASE_T: 241248cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_5GBASE_KR: 241348cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 241448cb27f2SChinh Cao break; 241548cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10GBASE_T: 241648cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10G_SFI_DA: 241748cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10GBASE_SR: 241848cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10GBASE_LR: 241948cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 242048cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 242148cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 242248cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 242348cb27f2SChinh Cao break; 242448cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_T: 242548cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_CR: 242648cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 242748cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_CR1: 242848cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_SR: 242948cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_LR: 243048cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_KR: 243148cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 243248cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_KR1: 243348cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 243448cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 243548cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 243648cb27f2SChinh Cao break; 243748cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40GBASE_CR4: 243848cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40GBASE_SR4: 243948cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40GBASE_LR4: 244048cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40GBASE_KR4: 244148cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 244248cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40G_XLAUI: 244348cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 244448cb27f2SChinh Cao break; 2445aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2446aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2447aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2448aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2449aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2450aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_LAUI2: 2451aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2452aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_AUI2: 2453aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_CP: 2454aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_SR: 2455aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_FR: 2456aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_LR: 2457aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2458aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2459aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_AUI1: 2460aef74145SAnirudh Venkataramanan speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2461aef74145SAnirudh Venkataramanan break; 2462aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2463aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2464aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2465aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2466aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2467aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100G_CAUI4: 2468aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2469aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100G_AUI4: 2470aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2471aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2472aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2473aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2474aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_DR: 2475aef74145SAnirudh Venkataramanan speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2476aef74145SAnirudh Venkataramanan break; 247748cb27f2SChinh Cao default: 247848cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 247948cb27f2SChinh Cao break; 248048cb27f2SChinh Cao } 248148cb27f2SChinh Cao 2482aef74145SAnirudh Venkataramanan switch (phy_type_high) { 2483aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2484aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2485aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2486aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2487aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100G_AUI2: 2488aef74145SAnirudh Venkataramanan speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2489aef74145SAnirudh Venkataramanan break; 2490aef74145SAnirudh Venkataramanan default: 2491aef74145SAnirudh Venkataramanan speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2492aef74145SAnirudh Venkataramanan break; 2493aef74145SAnirudh Venkataramanan } 2494aef74145SAnirudh Venkataramanan 2495aef74145SAnirudh Venkataramanan if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2496aef74145SAnirudh Venkataramanan speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2497aef74145SAnirudh Venkataramanan return ICE_AQ_LINK_SPEED_UNKNOWN; 2498aef74145SAnirudh Venkataramanan else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2499aef74145SAnirudh Venkataramanan speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2500aef74145SAnirudh Venkataramanan return ICE_AQ_LINK_SPEED_UNKNOWN; 2501aef74145SAnirudh Venkataramanan else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2502aef74145SAnirudh Venkataramanan speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 250348cb27f2SChinh Cao return speed_phy_type_low; 2504aef74145SAnirudh Venkataramanan else 2505aef74145SAnirudh Venkataramanan return speed_phy_type_high; 250648cb27f2SChinh Cao } 250748cb27f2SChinh Cao 250848cb27f2SChinh Cao /** 250948cb27f2SChinh Cao * ice_update_phy_type 251048cb27f2SChinh Cao * @phy_type_low: pointer to the lower part of phy_type 2511aef74145SAnirudh Venkataramanan * @phy_type_high: pointer to the higher part of phy_type 251248cb27f2SChinh Cao * @link_speeds_bitmap: targeted link speeds bitmap 251348cb27f2SChinh Cao * 251448cb27f2SChinh Cao * Note: For the link_speeds_bitmap structure, you can check it at 251548cb27f2SChinh Cao * [ice_aqc_get_link_status->link_speed]. Caller can pass in 251648cb27f2SChinh Cao * link_speeds_bitmap include multiple speeds. 251748cb27f2SChinh Cao * 2518aef74145SAnirudh Venkataramanan * Each entry in this [phy_type_low, phy_type_high] structure will 2519aef74145SAnirudh Venkataramanan * present a certain link speed. This helper function will turn on bits 2520aef74145SAnirudh Venkataramanan * in [phy_type_low, phy_type_high] structure based on the value of 252148cb27f2SChinh Cao * link_speeds_bitmap input parameter. 252248cb27f2SChinh Cao */ 2523aef74145SAnirudh Venkataramanan void 2524aef74145SAnirudh Venkataramanan ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2525aef74145SAnirudh Venkataramanan u16 link_speeds_bitmap) 252648cb27f2SChinh Cao { 2527aef74145SAnirudh Venkataramanan u64 pt_high; 252848cb27f2SChinh Cao u64 pt_low; 252948cb27f2SChinh Cao int index; 2530207e3721SBruce Allan u16 speed; 253148cb27f2SChinh Cao 253248cb27f2SChinh Cao /* We first check with low part of phy_type */ 253348cb27f2SChinh Cao for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 253448cb27f2SChinh Cao pt_low = BIT_ULL(index); 2535aef74145SAnirudh Venkataramanan speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 253648cb27f2SChinh Cao 253748cb27f2SChinh Cao if (link_speeds_bitmap & speed) 253848cb27f2SChinh Cao *phy_type_low |= BIT_ULL(index); 253948cb27f2SChinh Cao } 2540aef74145SAnirudh Venkataramanan 2541aef74145SAnirudh Venkataramanan /* We then check with high part of phy_type */ 2542aef74145SAnirudh Venkataramanan for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2543aef74145SAnirudh Venkataramanan pt_high = BIT_ULL(index); 2544aef74145SAnirudh Venkataramanan speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2545aef74145SAnirudh Venkataramanan 2546aef74145SAnirudh Venkataramanan if (link_speeds_bitmap & speed) 2547aef74145SAnirudh Venkataramanan *phy_type_high |= BIT_ULL(index); 2548aef74145SAnirudh Venkataramanan } 254948cb27f2SChinh Cao } 255048cb27f2SChinh Cao 255148cb27f2SChinh Cao /** 2552fcea6f3dSAnirudh Venkataramanan * ice_aq_set_phy_cfg 2553f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 25541a3571b5SPaul Greenwalt * @pi: port info structure of the interested logical port 2555fcea6f3dSAnirudh Venkataramanan * @cfg: structure with PHY configuration data to be set 2556fcea6f3dSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 2557fcea6f3dSAnirudh Venkataramanan * 2558fcea6f3dSAnirudh Venkataramanan * Set the various PHY configuration parameters supported on the Port. 2559fcea6f3dSAnirudh Venkataramanan * One or more of the Set PHY config parameters may be ignored in an MFP 2560fcea6f3dSAnirudh Venkataramanan * mode as the PF may not have the privilege to set some of the PHY Config 2561fcea6f3dSAnirudh Venkataramanan * parameters. This status will be indicated by the command response (0x0601). 2562fcea6f3dSAnirudh Venkataramanan */ 256348cb27f2SChinh Cao enum ice_status 25641a3571b5SPaul Greenwalt ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2565fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2566fcea6f3dSAnirudh Venkataramanan { 2567fcea6f3dSAnirudh Venkataramanan struct ice_aq_desc desc; 2568b5e19a64SChinh T Cao enum ice_status status; 2569fcea6f3dSAnirudh Venkataramanan 2570fcea6f3dSAnirudh Venkataramanan if (!cfg) 2571fcea6f3dSAnirudh Venkataramanan return ICE_ERR_PARAM; 2572fcea6f3dSAnirudh Venkataramanan 2573d8df260aSChinh T Cao /* Ensure that only valid bits of cfg->caps can be turned on. */ 2574d8df260aSChinh T Cao if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 2575d8df260aSChinh T Cao ice_debug(hw, ICE_DBG_PHY, 2576d8df260aSChinh T Cao "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2577d8df260aSChinh T Cao cfg->caps); 2578d8df260aSChinh T Cao 2579d8df260aSChinh T Cao cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2580d8df260aSChinh T Cao } 2581d8df260aSChinh T Cao 2582fcea6f3dSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 25831a3571b5SPaul Greenwalt desc.params.set_phy.lport_num = pi->lport; 258448cb27f2SChinh Cao desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2585fcea6f3dSAnirudh Venkataramanan 258655df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 2587dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 2588dc67039bSJesse Brandeburg (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 2589dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 2590dc67039bSJesse Brandeburg (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 2591dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 2592bdeff971SLev Faerman ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 2593bdeff971SLev Faerman cfg->low_power_ctrl_an); 2594dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 2595dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 259655df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 259755df52a0SPaul Greenwalt cfg->link_fec_opt); 2598dc67039bSJesse Brandeburg 2599b5e19a64SChinh T Cao status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2600b5e19a64SChinh T Cao if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 2601b5e19a64SChinh T Cao status = 0; 2602b5e19a64SChinh T Cao 26031a3571b5SPaul Greenwalt if (!status) 26041a3571b5SPaul Greenwalt pi->phy.curr_user_phy_cfg = *cfg; 26051a3571b5SPaul Greenwalt 2606b5e19a64SChinh T Cao return status; 2607fcea6f3dSAnirudh Venkataramanan } 2608fcea6f3dSAnirudh Venkataramanan 2609fcea6f3dSAnirudh Venkataramanan /** 2610fcea6f3dSAnirudh Venkataramanan * ice_update_link_info - update status of the HW network link 2611fcea6f3dSAnirudh Venkataramanan * @pi: port info structure of the interested logical port 2612fcea6f3dSAnirudh Venkataramanan */ 26135755143dSDave Ertman enum ice_status ice_update_link_info(struct ice_port_info *pi) 2614fcea6f3dSAnirudh Venkataramanan { 2615092a33d4SBruce Allan struct ice_link_status *li; 2616fcea6f3dSAnirudh Venkataramanan enum ice_status status; 2617fcea6f3dSAnirudh Venkataramanan 2618fcea6f3dSAnirudh Venkataramanan if (!pi) 2619fcea6f3dSAnirudh Venkataramanan return ICE_ERR_PARAM; 2620fcea6f3dSAnirudh Venkataramanan 2621092a33d4SBruce Allan li = &pi->phy.link_info; 2622fcea6f3dSAnirudh Venkataramanan 2623092a33d4SBruce Allan status = ice_aq_get_link_info(pi, true, NULL, NULL); 2624092a33d4SBruce Allan if (status) 2625092a33d4SBruce Allan return status; 2626092a33d4SBruce Allan 2627092a33d4SBruce Allan if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2628092a33d4SBruce Allan struct ice_aqc_get_phy_caps_data *pcaps; 2629092a33d4SBruce Allan struct ice_hw *hw; 2630092a33d4SBruce Allan 2631092a33d4SBruce Allan hw = pi->hw; 2632092a33d4SBruce Allan pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 2633092a33d4SBruce Allan GFP_KERNEL); 2634fcea6f3dSAnirudh Venkataramanan if (!pcaps) 2635fcea6f3dSAnirudh Venkataramanan return ICE_ERR_NO_MEMORY; 2636fcea6f3dSAnirudh Venkataramanan 2637057911baSChinh T Cao status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, 2638fcea6f3dSAnirudh Venkataramanan pcaps, NULL); 2639092a33d4SBruce Allan if (!status) 2640092a33d4SBruce Allan memcpy(li->module_type, &pcaps->module_type, 2641092a33d4SBruce Allan sizeof(li->module_type)); 2642fcea6f3dSAnirudh Venkataramanan 2643fcea6f3dSAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), pcaps); 2644092a33d4SBruce Allan } 2645092a33d4SBruce Allan 2646fcea6f3dSAnirudh Venkataramanan return status; 2647fcea6f3dSAnirudh Venkataramanan } 2648fcea6f3dSAnirudh Venkataramanan 2649fcea6f3dSAnirudh Venkataramanan /** 26501a3571b5SPaul Greenwalt * ice_cache_phy_user_req 26511a3571b5SPaul Greenwalt * @pi: port information structure 26521a3571b5SPaul Greenwalt * @cache_data: PHY logging data 26531a3571b5SPaul Greenwalt * @cache_mode: PHY logging mode 26541a3571b5SPaul Greenwalt * 26551a3571b5SPaul Greenwalt * Log the user request on (FC, FEC, SPEED) for later use. 26561a3571b5SPaul Greenwalt */ 26571a3571b5SPaul Greenwalt static void 26581a3571b5SPaul Greenwalt ice_cache_phy_user_req(struct ice_port_info *pi, 26591a3571b5SPaul Greenwalt struct ice_phy_cache_mode_data cache_data, 26601a3571b5SPaul Greenwalt enum ice_phy_cache_mode cache_mode) 26611a3571b5SPaul Greenwalt { 26621a3571b5SPaul Greenwalt if (!pi) 26631a3571b5SPaul Greenwalt return; 26641a3571b5SPaul Greenwalt 26651a3571b5SPaul Greenwalt switch (cache_mode) { 26661a3571b5SPaul Greenwalt case ICE_FC_MODE: 26671a3571b5SPaul Greenwalt pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 26681a3571b5SPaul Greenwalt break; 26691a3571b5SPaul Greenwalt case ICE_SPEED_MODE: 26701a3571b5SPaul Greenwalt pi->phy.curr_user_speed_req = 26711a3571b5SPaul Greenwalt cache_data.data.curr_user_speed_req; 26721a3571b5SPaul Greenwalt break; 26731a3571b5SPaul Greenwalt case ICE_FEC_MODE: 26741a3571b5SPaul Greenwalt pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 26751a3571b5SPaul Greenwalt break; 26761a3571b5SPaul Greenwalt default: 26771a3571b5SPaul Greenwalt break; 26781a3571b5SPaul Greenwalt } 26791a3571b5SPaul Greenwalt } 26801a3571b5SPaul Greenwalt 26811a3571b5SPaul Greenwalt /** 26821a3571b5SPaul Greenwalt * ice_caps_to_fc_mode 26831a3571b5SPaul Greenwalt * @caps: PHY capabilities 26841a3571b5SPaul Greenwalt * 26851a3571b5SPaul Greenwalt * Convert PHY FC capabilities to ice FC mode 26861a3571b5SPaul Greenwalt */ 26871a3571b5SPaul Greenwalt enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 26881a3571b5SPaul Greenwalt { 26891a3571b5SPaul Greenwalt if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 26901a3571b5SPaul Greenwalt caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 26911a3571b5SPaul Greenwalt return ICE_FC_FULL; 26921a3571b5SPaul Greenwalt 26931a3571b5SPaul Greenwalt if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 26941a3571b5SPaul Greenwalt return ICE_FC_TX_PAUSE; 26951a3571b5SPaul Greenwalt 26961a3571b5SPaul Greenwalt if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 26971a3571b5SPaul Greenwalt return ICE_FC_RX_PAUSE; 26981a3571b5SPaul Greenwalt 26991a3571b5SPaul Greenwalt return ICE_FC_NONE; 27001a3571b5SPaul Greenwalt } 27011a3571b5SPaul Greenwalt 27021a3571b5SPaul Greenwalt /** 27031a3571b5SPaul Greenwalt * ice_caps_to_fec_mode 27041a3571b5SPaul Greenwalt * @caps: PHY capabilities 27051a3571b5SPaul Greenwalt * @fec_options: Link FEC options 27061a3571b5SPaul Greenwalt * 27071a3571b5SPaul Greenwalt * Convert PHY FEC capabilities to ice FEC mode 27081a3571b5SPaul Greenwalt */ 27091a3571b5SPaul Greenwalt enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 27101a3571b5SPaul Greenwalt { 27111a3571b5SPaul Greenwalt if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 27121a3571b5SPaul Greenwalt return ICE_FEC_AUTO; 27131a3571b5SPaul Greenwalt 27141a3571b5SPaul Greenwalt if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 27151a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 27161a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 27171a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_25G_KR_REQ)) 27181a3571b5SPaul Greenwalt return ICE_FEC_BASER; 27191a3571b5SPaul Greenwalt 27201a3571b5SPaul Greenwalt if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 27211a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_25G_RS_544_REQ | 27221a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 27231a3571b5SPaul Greenwalt return ICE_FEC_RS; 27241a3571b5SPaul Greenwalt 27251a3571b5SPaul Greenwalt return ICE_FEC_NONE; 27261a3571b5SPaul Greenwalt } 27271a3571b5SPaul Greenwalt 27281a3571b5SPaul Greenwalt /** 27292ffb6085SPaul Greenwalt * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 27301a3571b5SPaul Greenwalt * @pi: port information structure 27312ffb6085SPaul Greenwalt * @cfg: PHY configuration data to set FC mode 27322ffb6085SPaul Greenwalt * @req_mode: FC mode to configure 2733fcea6f3dSAnirudh Venkataramanan */ 27341a3571b5SPaul Greenwalt enum ice_status 27351a3571b5SPaul Greenwalt ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 27361a3571b5SPaul Greenwalt enum ice_fc_mode req_mode) 2737fcea6f3dSAnirudh Venkataramanan { 27381a3571b5SPaul Greenwalt struct ice_phy_cache_mode_data cache_data; 2739fcea6f3dSAnirudh Venkataramanan u8 pause_mask = 0x0; 2740fcea6f3dSAnirudh Venkataramanan 27411a3571b5SPaul Greenwalt if (!pi || !cfg) 27422ffb6085SPaul Greenwalt return ICE_ERR_BAD_PTR; 2743fcea6f3dSAnirudh Venkataramanan 27442ffb6085SPaul Greenwalt switch (req_mode) { 2745fcea6f3dSAnirudh Venkataramanan case ICE_FC_FULL: 2746fcea6f3dSAnirudh Venkataramanan pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2747fcea6f3dSAnirudh Venkataramanan pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2748fcea6f3dSAnirudh Venkataramanan break; 2749fcea6f3dSAnirudh Venkataramanan case ICE_FC_RX_PAUSE: 2750fcea6f3dSAnirudh Venkataramanan pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2751fcea6f3dSAnirudh Venkataramanan break; 2752fcea6f3dSAnirudh Venkataramanan case ICE_FC_TX_PAUSE: 2753fcea6f3dSAnirudh Venkataramanan pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2754fcea6f3dSAnirudh Venkataramanan break; 2755fcea6f3dSAnirudh Venkataramanan default: 2756fcea6f3dSAnirudh Venkataramanan break; 2757fcea6f3dSAnirudh Venkataramanan } 2758fcea6f3dSAnirudh Venkataramanan 27592ffb6085SPaul Greenwalt /* clear the old pause settings */ 27602ffb6085SPaul Greenwalt cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 27612ffb6085SPaul Greenwalt ICE_AQC_PHY_EN_RX_LINK_PAUSE); 27622ffb6085SPaul Greenwalt 27632ffb6085SPaul Greenwalt /* set the new capabilities */ 27642ffb6085SPaul Greenwalt cfg->caps |= pause_mask; 27652ffb6085SPaul Greenwalt 27661a3571b5SPaul Greenwalt /* Cache user FC request */ 27671a3571b5SPaul Greenwalt cache_data.data.curr_user_fc_req = req_mode; 27681a3571b5SPaul Greenwalt ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 27691a3571b5SPaul Greenwalt 27702ffb6085SPaul Greenwalt return 0; 27712ffb6085SPaul Greenwalt } 27722ffb6085SPaul Greenwalt 27732ffb6085SPaul Greenwalt /** 27742ffb6085SPaul Greenwalt * ice_set_fc 27752ffb6085SPaul Greenwalt * @pi: port information structure 27762ffb6085SPaul Greenwalt * @aq_failures: pointer to status code, specific to ice_set_fc routine 27772ffb6085SPaul Greenwalt * @ena_auto_link_update: enable automatic link update 27782ffb6085SPaul Greenwalt * 27792ffb6085SPaul Greenwalt * Set the requested flow control mode. 27802ffb6085SPaul Greenwalt */ 27812ffb6085SPaul Greenwalt enum ice_status 27822ffb6085SPaul Greenwalt ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 27832ffb6085SPaul Greenwalt { 27842ffb6085SPaul Greenwalt struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 27852ffb6085SPaul Greenwalt struct ice_aqc_get_phy_caps_data *pcaps; 27862ffb6085SPaul Greenwalt enum ice_status status; 27872ffb6085SPaul Greenwalt struct ice_hw *hw; 27882ffb6085SPaul Greenwalt 27891a3571b5SPaul Greenwalt if (!pi || !aq_failures) 27902ffb6085SPaul Greenwalt return ICE_ERR_BAD_PTR; 27912ffb6085SPaul Greenwalt 27922ffb6085SPaul Greenwalt *aq_failures = 0; 27932ffb6085SPaul Greenwalt hw = pi->hw; 27942ffb6085SPaul Greenwalt 2795fcea6f3dSAnirudh Venkataramanan pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 2796fcea6f3dSAnirudh Venkataramanan if (!pcaps) 2797fcea6f3dSAnirudh Venkataramanan return ICE_ERR_NO_MEMORY; 2798fcea6f3dSAnirudh Venkataramanan 2799f9867df6SAnirudh Venkataramanan /* Get the current PHY config */ 2800fcea6f3dSAnirudh Venkataramanan status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 2801fcea6f3dSAnirudh Venkataramanan NULL); 2802fcea6f3dSAnirudh Venkataramanan if (status) { 2803fcea6f3dSAnirudh Venkataramanan *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2804fcea6f3dSAnirudh Venkataramanan goto out; 2805fcea6f3dSAnirudh Venkataramanan } 2806fcea6f3dSAnirudh Venkataramanan 2807ea78ce4dSPaul Greenwalt ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 2808d8df260aSChinh T Cao 28092ffb6085SPaul Greenwalt /* Configure the set PHY data */ 28101a3571b5SPaul Greenwalt status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 28112ffb6085SPaul Greenwalt if (status) 28122ffb6085SPaul Greenwalt goto out; 2813d8df260aSChinh T Cao 2814fcea6f3dSAnirudh Venkataramanan /* If the capabilities have changed, then set the new config */ 2815fcea6f3dSAnirudh Venkataramanan if (cfg.caps != pcaps->caps) { 2816fcea6f3dSAnirudh Venkataramanan int retry_count, retry_max = 10; 2817fcea6f3dSAnirudh Venkataramanan 2818fcea6f3dSAnirudh Venkataramanan /* Auto restart link so settings take effect */ 281948cb27f2SChinh Cao if (ena_auto_link_update) 282048cb27f2SChinh Cao cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2821fcea6f3dSAnirudh Venkataramanan 28221a3571b5SPaul Greenwalt status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 2823fcea6f3dSAnirudh Venkataramanan if (status) { 2824fcea6f3dSAnirudh Venkataramanan *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 2825fcea6f3dSAnirudh Venkataramanan goto out; 2826fcea6f3dSAnirudh Venkataramanan } 2827fcea6f3dSAnirudh Venkataramanan 2828fcea6f3dSAnirudh Venkataramanan /* Update the link info 2829fcea6f3dSAnirudh Venkataramanan * It sometimes takes a really long time for link to 2830fcea6f3dSAnirudh Venkataramanan * come back from the atomic reset. Thus, we wait a 2831fcea6f3dSAnirudh Venkataramanan * little bit. 2832fcea6f3dSAnirudh Venkataramanan */ 2833fcea6f3dSAnirudh Venkataramanan for (retry_count = 0; retry_count < retry_max; retry_count++) { 2834fcea6f3dSAnirudh Venkataramanan status = ice_update_link_info(pi); 2835fcea6f3dSAnirudh Venkataramanan 2836fcea6f3dSAnirudh Venkataramanan if (!status) 2837fcea6f3dSAnirudh Venkataramanan break; 2838fcea6f3dSAnirudh Venkataramanan 2839fcea6f3dSAnirudh Venkataramanan mdelay(100); 2840fcea6f3dSAnirudh Venkataramanan } 2841fcea6f3dSAnirudh Venkataramanan 2842fcea6f3dSAnirudh Venkataramanan if (status) 2843fcea6f3dSAnirudh Venkataramanan *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 2844fcea6f3dSAnirudh Venkataramanan } 2845fcea6f3dSAnirudh Venkataramanan 2846fcea6f3dSAnirudh Venkataramanan out: 2847fcea6f3dSAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), pcaps); 2848fcea6f3dSAnirudh Venkataramanan return status; 2849fcea6f3dSAnirudh Venkataramanan } 2850fcea6f3dSAnirudh Venkataramanan 2851fcea6f3dSAnirudh Venkataramanan /** 28521a3571b5SPaul Greenwalt * ice_phy_caps_equals_cfg 28531a3571b5SPaul Greenwalt * @phy_caps: PHY capabilities 28541a3571b5SPaul Greenwalt * @phy_cfg: PHY configuration 28551a3571b5SPaul Greenwalt * 28561a3571b5SPaul Greenwalt * Helper function to determine if PHY capabilities matches PHY 28571a3571b5SPaul Greenwalt * configuration 28581a3571b5SPaul Greenwalt */ 28591a3571b5SPaul Greenwalt bool 28601a3571b5SPaul Greenwalt ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 28611a3571b5SPaul Greenwalt struct ice_aqc_set_phy_cfg_data *phy_cfg) 28621a3571b5SPaul Greenwalt { 28631a3571b5SPaul Greenwalt u8 caps_mask, cfg_mask; 28641a3571b5SPaul Greenwalt 28651a3571b5SPaul Greenwalt if (!phy_caps || !phy_cfg) 28661a3571b5SPaul Greenwalt return false; 28671a3571b5SPaul Greenwalt 28681a3571b5SPaul Greenwalt /* These bits are not common between capabilities and configuration. 28691a3571b5SPaul Greenwalt * Do not use them to determine equality. 28701a3571b5SPaul Greenwalt */ 28711a3571b5SPaul Greenwalt caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 28721a3571b5SPaul Greenwalt ICE_AQC_GET_PHY_EN_MOD_QUAL); 28731a3571b5SPaul Greenwalt cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 28741a3571b5SPaul Greenwalt 28751a3571b5SPaul Greenwalt if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 28761a3571b5SPaul Greenwalt phy_caps->phy_type_high != phy_cfg->phy_type_high || 28771a3571b5SPaul Greenwalt ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 2878bdeff971SLev Faerman phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 28791a3571b5SPaul Greenwalt phy_caps->eee_cap != phy_cfg->eee_cap || 28801a3571b5SPaul Greenwalt phy_caps->eeer_value != phy_cfg->eeer_value || 28811a3571b5SPaul Greenwalt phy_caps->link_fec_options != phy_cfg->link_fec_opt) 28821a3571b5SPaul Greenwalt return false; 28831a3571b5SPaul Greenwalt 28841a3571b5SPaul Greenwalt return true; 28851a3571b5SPaul Greenwalt } 28861a3571b5SPaul Greenwalt 28871a3571b5SPaul Greenwalt /** 2888f776b3acSPaul Greenwalt * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 2889ea78ce4dSPaul Greenwalt * @pi: port information structure 2890f776b3acSPaul Greenwalt * @caps: PHY ability structure to copy date from 2891f776b3acSPaul Greenwalt * @cfg: PHY configuration structure to copy data to 2892f776b3acSPaul Greenwalt * 2893f776b3acSPaul Greenwalt * Helper function to copy AQC PHY get ability data to PHY set configuration 2894f776b3acSPaul Greenwalt * data structure 2895f776b3acSPaul Greenwalt */ 2896f776b3acSPaul Greenwalt void 2897ea78ce4dSPaul Greenwalt ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 2898ea78ce4dSPaul Greenwalt struct ice_aqc_get_phy_caps_data *caps, 2899f776b3acSPaul Greenwalt struct ice_aqc_set_phy_cfg_data *cfg) 2900f776b3acSPaul Greenwalt { 2901ea78ce4dSPaul Greenwalt if (!pi || !caps || !cfg) 2902f776b3acSPaul Greenwalt return; 2903f776b3acSPaul Greenwalt 29042ffb6085SPaul Greenwalt memset(cfg, 0, sizeof(*cfg)); 2905f776b3acSPaul Greenwalt cfg->phy_type_low = caps->phy_type_low; 2906f776b3acSPaul Greenwalt cfg->phy_type_high = caps->phy_type_high; 2907f776b3acSPaul Greenwalt cfg->caps = caps->caps; 2908bdeff971SLev Faerman cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 2909f776b3acSPaul Greenwalt cfg->eee_cap = caps->eee_cap; 2910f776b3acSPaul Greenwalt cfg->eeer_value = caps->eeer_value; 2911f776b3acSPaul Greenwalt cfg->link_fec_opt = caps->link_fec_options; 2912ea78ce4dSPaul Greenwalt cfg->module_compliance_enforcement = 2913ea78ce4dSPaul Greenwalt caps->module_compliance_enforcement; 2914ea78ce4dSPaul Greenwalt 2915ea78ce4dSPaul Greenwalt if (ice_fw_supports_link_override(pi->hw)) { 2916ea78ce4dSPaul Greenwalt struct ice_link_default_override_tlv tlv; 2917ea78ce4dSPaul Greenwalt 2918ea78ce4dSPaul Greenwalt if (ice_get_link_default_override(&tlv, pi)) 2919ea78ce4dSPaul Greenwalt return; 2920ea78ce4dSPaul Greenwalt 2921ea78ce4dSPaul Greenwalt if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) 2922ea78ce4dSPaul Greenwalt cfg->module_compliance_enforcement |= 2923ea78ce4dSPaul Greenwalt ICE_LINK_OVERRIDE_STRICT_MODE; 2924ea78ce4dSPaul Greenwalt } 2925f776b3acSPaul Greenwalt } 2926f776b3acSPaul Greenwalt 2927f776b3acSPaul Greenwalt /** 2928f776b3acSPaul Greenwalt * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 292961cf42e7SPaul Greenwalt * @pi: port information structure 2930f776b3acSPaul Greenwalt * @cfg: PHY configuration data to set FEC mode 2931f776b3acSPaul Greenwalt * @fec: FEC mode to configure 2932f776b3acSPaul Greenwalt */ 293361cf42e7SPaul Greenwalt enum ice_status 293461cf42e7SPaul Greenwalt ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 293561cf42e7SPaul Greenwalt enum ice_fec_mode fec) 2936f776b3acSPaul Greenwalt { 293761cf42e7SPaul Greenwalt struct ice_aqc_get_phy_caps_data *pcaps; 293861cf42e7SPaul Greenwalt enum ice_status status; 293961cf42e7SPaul Greenwalt 294061cf42e7SPaul Greenwalt if (!pi || !cfg) 294161cf42e7SPaul Greenwalt return ICE_ERR_BAD_PTR; 294261cf42e7SPaul Greenwalt 294361cf42e7SPaul Greenwalt pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 294461cf42e7SPaul Greenwalt if (!pcaps) 294561cf42e7SPaul Greenwalt return ICE_ERR_NO_MEMORY; 294661cf42e7SPaul Greenwalt 294761cf42e7SPaul Greenwalt status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps, 294861cf42e7SPaul Greenwalt NULL); 294961cf42e7SPaul Greenwalt if (status) 295061cf42e7SPaul Greenwalt goto out; 295161cf42e7SPaul Greenwalt 295261cf42e7SPaul Greenwalt cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 295361cf42e7SPaul Greenwalt cfg->link_fec_opt = pcaps->link_fec_options; 295461cf42e7SPaul Greenwalt 2955f776b3acSPaul Greenwalt switch (fec) { 2956f776b3acSPaul Greenwalt case ICE_FEC_BASER: 29573747f031SChinh T Cao /* Clear RS bits, and AND BASE-R ability 2958f776b3acSPaul Greenwalt * bits and OR request bits. 2959f776b3acSPaul Greenwalt */ 2960f776b3acSPaul Greenwalt cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2961f776b3acSPaul Greenwalt ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 2962f776b3acSPaul Greenwalt cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2963f776b3acSPaul Greenwalt ICE_AQC_PHY_FEC_25G_KR_REQ; 2964f776b3acSPaul Greenwalt break; 2965f776b3acSPaul Greenwalt case ICE_FEC_RS: 29663747f031SChinh T Cao /* Clear BASE-R bits, and AND RS ability 2967f776b3acSPaul Greenwalt * bits and OR request bits. 2968f776b3acSPaul Greenwalt */ 2969f776b3acSPaul Greenwalt cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 2970f776b3acSPaul Greenwalt cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2971f776b3acSPaul Greenwalt ICE_AQC_PHY_FEC_25G_RS_544_REQ; 2972f776b3acSPaul Greenwalt break; 2973f776b3acSPaul Greenwalt case ICE_FEC_NONE: 29743747f031SChinh T Cao /* Clear all FEC option bits. */ 2975f776b3acSPaul Greenwalt cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 2976f776b3acSPaul Greenwalt break; 2977f776b3acSPaul Greenwalt case ICE_FEC_AUTO: 2978f776b3acSPaul Greenwalt /* AND auto FEC bit, and all caps bits. */ 2979f776b3acSPaul Greenwalt cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 298061cf42e7SPaul Greenwalt cfg->link_fec_opt |= pcaps->link_fec_options; 298161cf42e7SPaul Greenwalt break; 298261cf42e7SPaul Greenwalt default: 298361cf42e7SPaul Greenwalt status = ICE_ERR_PARAM; 2984f776b3acSPaul Greenwalt break; 2985f776b3acSPaul Greenwalt } 298661cf42e7SPaul Greenwalt 2987ea78ce4dSPaul Greenwalt if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) { 2988ea78ce4dSPaul Greenwalt struct ice_link_default_override_tlv tlv; 2989ea78ce4dSPaul Greenwalt 2990ea78ce4dSPaul Greenwalt if (ice_get_link_default_override(&tlv, pi)) 2991ea78ce4dSPaul Greenwalt goto out; 2992ea78ce4dSPaul Greenwalt 2993ea78ce4dSPaul Greenwalt if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 2994ea78ce4dSPaul Greenwalt (tlv.options & ICE_LINK_OVERRIDE_EN)) 2995ea78ce4dSPaul Greenwalt cfg->link_fec_opt = tlv.fec_options; 2996ea78ce4dSPaul Greenwalt } 2997ea78ce4dSPaul Greenwalt 299861cf42e7SPaul Greenwalt out: 299961cf42e7SPaul Greenwalt kfree(pcaps); 300061cf42e7SPaul Greenwalt 300161cf42e7SPaul Greenwalt return status; 3002f776b3acSPaul Greenwalt } 3003f776b3acSPaul Greenwalt 3004f776b3acSPaul Greenwalt /** 30050b28b702SAnirudh Venkataramanan * ice_get_link_status - get status of the HW network link 30060b28b702SAnirudh Venkataramanan * @pi: port information structure 30070b28b702SAnirudh Venkataramanan * @link_up: pointer to bool (true/false = linkup/linkdown) 30080b28b702SAnirudh Venkataramanan * 30090b28b702SAnirudh Venkataramanan * Variable link_up is true if link is up, false if link is down. 30100b28b702SAnirudh Venkataramanan * The variable link_up is invalid if status is non zero. As a 30110b28b702SAnirudh Venkataramanan * result of this call, link status reporting becomes enabled 30120b28b702SAnirudh Venkataramanan */ 30130b28b702SAnirudh Venkataramanan enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 30140b28b702SAnirudh Venkataramanan { 30150b28b702SAnirudh Venkataramanan struct ice_phy_info *phy_info; 30160b28b702SAnirudh Venkataramanan enum ice_status status = 0; 30170b28b702SAnirudh Venkataramanan 3018c7f2c42bSAnirudh Venkataramanan if (!pi || !link_up) 30190b28b702SAnirudh Venkataramanan return ICE_ERR_PARAM; 30200b28b702SAnirudh Venkataramanan 30210b28b702SAnirudh Venkataramanan phy_info = &pi->phy; 30220b28b702SAnirudh Venkataramanan 30230b28b702SAnirudh Venkataramanan if (phy_info->get_link_info) { 30240b28b702SAnirudh Venkataramanan status = ice_update_link_info(pi); 30250b28b702SAnirudh Venkataramanan 30260b28b702SAnirudh Venkataramanan if (status) 30270b28b702SAnirudh Venkataramanan ice_debug(pi->hw, ICE_DBG_LINK, 30280b28b702SAnirudh Venkataramanan "get link status error, status = %d\n", 30290b28b702SAnirudh Venkataramanan status); 30300b28b702SAnirudh Venkataramanan } 30310b28b702SAnirudh Venkataramanan 30320b28b702SAnirudh Venkataramanan *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 30330b28b702SAnirudh Venkataramanan 30340b28b702SAnirudh Venkataramanan return status; 30350b28b702SAnirudh Venkataramanan } 30360b28b702SAnirudh Venkataramanan 30370b28b702SAnirudh Venkataramanan /** 3038fcea6f3dSAnirudh Venkataramanan * ice_aq_set_link_restart_an 3039fcea6f3dSAnirudh Venkataramanan * @pi: pointer to the port information structure 3040fcea6f3dSAnirudh Venkataramanan * @ena_link: if true: enable link, if false: disable link 3041fcea6f3dSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 3042fcea6f3dSAnirudh Venkataramanan * 3043fcea6f3dSAnirudh Venkataramanan * Sets up the link and restarts the Auto-Negotiation over the link. 3044fcea6f3dSAnirudh Venkataramanan */ 3045fcea6f3dSAnirudh Venkataramanan enum ice_status 3046fcea6f3dSAnirudh Venkataramanan ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3047fcea6f3dSAnirudh Venkataramanan struct ice_sq_cd *cd) 3048fcea6f3dSAnirudh Venkataramanan { 3049fcea6f3dSAnirudh Venkataramanan struct ice_aqc_restart_an *cmd; 3050fcea6f3dSAnirudh Venkataramanan struct ice_aq_desc desc; 3051fcea6f3dSAnirudh Venkataramanan 3052fcea6f3dSAnirudh Venkataramanan cmd = &desc.params.restart_an; 3053fcea6f3dSAnirudh Venkataramanan 3054fcea6f3dSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3055fcea6f3dSAnirudh Venkataramanan 3056fcea6f3dSAnirudh Venkataramanan cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3057fcea6f3dSAnirudh Venkataramanan cmd->lport_num = pi->lport; 3058fcea6f3dSAnirudh Venkataramanan if (ena_link) 3059fcea6f3dSAnirudh Venkataramanan cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3060fcea6f3dSAnirudh Venkataramanan else 3061fcea6f3dSAnirudh Venkataramanan cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3062fcea6f3dSAnirudh Venkataramanan 3063fcea6f3dSAnirudh Venkataramanan return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3064fcea6f3dSAnirudh Venkataramanan } 3065fcea6f3dSAnirudh Venkataramanan 3066fcea6f3dSAnirudh Venkataramanan /** 3067250c3b3eSBrett Creeley * ice_aq_set_event_mask 3068250c3b3eSBrett Creeley * @hw: pointer to the HW struct 3069250c3b3eSBrett Creeley * @port_num: port number of the physical function 3070250c3b3eSBrett Creeley * @mask: event mask to be set 3071250c3b3eSBrett Creeley * @cd: pointer to command details structure or NULL 3072250c3b3eSBrett Creeley * 3073250c3b3eSBrett Creeley * Set event mask (0x0613) 3074250c3b3eSBrett Creeley */ 3075250c3b3eSBrett Creeley enum ice_status 3076250c3b3eSBrett Creeley ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3077250c3b3eSBrett Creeley struct ice_sq_cd *cd) 3078250c3b3eSBrett Creeley { 3079250c3b3eSBrett Creeley struct ice_aqc_set_event_mask *cmd; 3080250c3b3eSBrett Creeley struct ice_aq_desc desc; 3081250c3b3eSBrett Creeley 3082250c3b3eSBrett Creeley cmd = &desc.params.set_event_mask; 3083250c3b3eSBrett Creeley 3084250c3b3eSBrett Creeley ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3085250c3b3eSBrett Creeley 3086250c3b3eSBrett Creeley cmd->lport_num = port_num; 3087250c3b3eSBrett Creeley 3088250c3b3eSBrett Creeley cmd->event_mask = cpu_to_le16(mask); 3089250c3b3eSBrett Creeley return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3090250c3b3eSBrett Creeley } 3091250c3b3eSBrett Creeley 3092250c3b3eSBrett Creeley /** 30930e674aebSAnirudh Venkataramanan * ice_aq_set_mac_loopback 30940e674aebSAnirudh Venkataramanan * @hw: pointer to the HW struct 30950e674aebSAnirudh Venkataramanan * @ena_lpbk: Enable or Disable loopback 30960e674aebSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 30970e674aebSAnirudh Venkataramanan * 30980e674aebSAnirudh Venkataramanan * Enable/disable loopback on a given port 30990e674aebSAnirudh Venkataramanan */ 31000e674aebSAnirudh Venkataramanan enum ice_status 31010e674aebSAnirudh Venkataramanan ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 31020e674aebSAnirudh Venkataramanan { 31030e674aebSAnirudh Venkataramanan struct ice_aqc_set_mac_lb *cmd; 31040e674aebSAnirudh Venkataramanan struct ice_aq_desc desc; 31050e674aebSAnirudh Venkataramanan 31060e674aebSAnirudh Venkataramanan cmd = &desc.params.set_mac_lb; 31070e674aebSAnirudh Venkataramanan 31080e674aebSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 31090e674aebSAnirudh Venkataramanan if (ena_lpbk) 31100e674aebSAnirudh Venkataramanan cmd->lb_mode = ICE_AQ_MAC_LB_EN; 31110e674aebSAnirudh Venkataramanan 31120e674aebSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 31130e674aebSAnirudh Venkataramanan } 31140e674aebSAnirudh Venkataramanan 31150e674aebSAnirudh Venkataramanan /** 31168e151d50SAnirudh Venkataramanan * ice_aq_set_port_id_led 31178e151d50SAnirudh Venkataramanan * @pi: pointer to the port information 31188e151d50SAnirudh Venkataramanan * @is_orig_mode: is this LED set to original mode (by the net-list) 31198e151d50SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 31208e151d50SAnirudh Venkataramanan * 31218e151d50SAnirudh Venkataramanan * Set LED value for the given port (0x06e9) 31228e151d50SAnirudh Venkataramanan */ 31238e151d50SAnirudh Venkataramanan enum ice_status 31248e151d50SAnirudh Venkataramanan ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 31258e151d50SAnirudh Venkataramanan struct ice_sq_cd *cd) 31268e151d50SAnirudh Venkataramanan { 31278e151d50SAnirudh Venkataramanan struct ice_aqc_set_port_id_led *cmd; 31288e151d50SAnirudh Venkataramanan struct ice_hw *hw = pi->hw; 31298e151d50SAnirudh Venkataramanan struct ice_aq_desc desc; 31308e151d50SAnirudh Venkataramanan 31318e151d50SAnirudh Venkataramanan cmd = &desc.params.set_port_id_led; 31328e151d50SAnirudh Venkataramanan 31338e151d50SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 31348e151d50SAnirudh Venkataramanan 31358e151d50SAnirudh Venkataramanan if (is_orig_mode) 31368e151d50SAnirudh Venkataramanan cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 31378e151d50SAnirudh Venkataramanan else 31388e151d50SAnirudh Venkataramanan cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 31398e151d50SAnirudh Venkataramanan 31408e151d50SAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 31418e151d50SAnirudh Venkataramanan } 31428e151d50SAnirudh Venkataramanan 31438e151d50SAnirudh Venkataramanan /** 3144a012dca9SScott W Taylor * ice_aq_sff_eeprom 3145a012dca9SScott W Taylor * @hw: pointer to the HW struct 3146a012dca9SScott W Taylor * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3147a012dca9SScott W Taylor * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3148a012dca9SScott W Taylor * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3149a012dca9SScott W Taylor * @page: QSFP page 3150a012dca9SScott W Taylor * @set_page: set or ignore the page 3151a012dca9SScott W Taylor * @data: pointer to data buffer to be read/written to the I2C device. 3152a012dca9SScott W Taylor * @length: 1-16 for read, 1 for write. 3153a012dca9SScott W Taylor * @write: 0 read, 1 for write. 3154a012dca9SScott W Taylor * @cd: pointer to command details structure or NULL 3155a012dca9SScott W Taylor * 3156a012dca9SScott W Taylor * Read/Write SFF EEPROM (0x06EE) 3157a012dca9SScott W Taylor */ 3158a012dca9SScott W Taylor enum ice_status 3159a012dca9SScott W Taylor ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3160a012dca9SScott W Taylor u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3161a012dca9SScott W Taylor bool write, struct ice_sq_cd *cd) 3162a012dca9SScott W Taylor { 3163a012dca9SScott W Taylor struct ice_aqc_sff_eeprom *cmd; 3164a012dca9SScott W Taylor struct ice_aq_desc desc; 3165a012dca9SScott W Taylor enum ice_status status; 3166a012dca9SScott W Taylor 3167a012dca9SScott W Taylor if (!data || (mem_addr & 0xff00)) 3168a012dca9SScott W Taylor return ICE_ERR_PARAM; 3169a012dca9SScott W Taylor 3170a012dca9SScott W Taylor ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3171a012dca9SScott W Taylor cmd = &desc.params.read_write_sff_param; 3172a012dca9SScott W Taylor desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF); 3173a012dca9SScott W Taylor cmd->lport_num = (u8)(lport & 0xff); 3174a012dca9SScott W Taylor cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3175a012dca9SScott W Taylor cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 3176a012dca9SScott W Taylor ICE_AQC_SFF_I2CBUS_7BIT_M) | 3177a012dca9SScott W Taylor ((set_page << 3178a012dca9SScott W Taylor ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3179a012dca9SScott W Taylor ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3180a012dca9SScott W Taylor cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3181a012dca9SScott W Taylor cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3182a012dca9SScott W Taylor if (write) 3183a012dca9SScott W Taylor cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 3184a012dca9SScott W Taylor 3185a012dca9SScott W Taylor status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3186a012dca9SScott W Taylor return status; 3187a012dca9SScott W Taylor } 3188a012dca9SScott W Taylor 3189a012dca9SScott W Taylor /** 3190d76a60baSAnirudh Venkataramanan * __ice_aq_get_set_rss_lut 3191d76a60baSAnirudh Venkataramanan * @hw: pointer to the hardware structure 3192d76a60baSAnirudh Venkataramanan * @vsi_id: VSI FW index 3193d76a60baSAnirudh Venkataramanan * @lut_type: LUT table type 3194d76a60baSAnirudh Venkataramanan * @lut: pointer to the LUT buffer provided by the caller 3195d76a60baSAnirudh Venkataramanan * @lut_size: size of the LUT buffer 3196d76a60baSAnirudh Venkataramanan * @glob_lut_idx: global LUT index 3197d76a60baSAnirudh Venkataramanan * @set: set true to set the table, false to get the table 3198d76a60baSAnirudh Venkataramanan * 3199d76a60baSAnirudh Venkataramanan * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3200d76a60baSAnirudh Venkataramanan */ 3201d76a60baSAnirudh Venkataramanan static enum ice_status 3202d76a60baSAnirudh Venkataramanan __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 3203d76a60baSAnirudh Venkataramanan u16 lut_size, u8 glob_lut_idx, bool set) 3204d76a60baSAnirudh Venkataramanan { 3205d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_lut *cmd_resp; 3206d76a60baSAnirudh Venkataramanan struct ice_aq_desc desc; 3207d76a60baSAnirudh Venkataramanan enum ice_status status; 3208d76a60baSAnirudh Venkataramanan u16 flags = 0; 3209d76a60baSAnirudh Venkataramanan 3210d76a60baSAnirudh Venkataramanan cmd_resp = &desc.params.get_set_rss_lut; 3211d76a60baSAnirudh Venkataramanan 3212d76a60baSAnirudh Venkataramanan if (set) { 3213d76a60baSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3214d76a60baSAnirudh Venkataramanan desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3215d76a60baSAnirudh Venkataramanan } else { 3216d76a60baSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3217d76a60baSAnirudh Venkataramanan } 3218d76a60baSAnirudh Venkataramanan 3219d76a60baSAnirudh Venkataramanan cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3220d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3221d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3222d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3223d76a60baSAnirudh Venkataramanan 3224d76a60baSAnirudh Venkataramanan switch (lut_type) { 3225d76a60baSAnirudh Venkataramanan case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3226d76a60baSAnirudh Venkataramanan case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3227d76a60baSAnirudh Venkataramanan case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3228d76a60baSAnirudh Venkataramanan flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3229d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3230d76a60baSAnirudh Venkataramanan break; 3231d76a60baSAnirudh Venkataramanan default: 3232d76a60baSAnirudh Venkataramanan status = ICE_ERR_PARAM; 3233d76a60baSAnirudh Venkataramanan goto ice_aq_get_set_rss_lut_exit; 3234d76a60baSAnirudh Venkataramanan } 3235d76a60baSAnirudh Venkataramanan 3236d76a60baSAnirudh Venkataramanan if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3237d76a60baSAnirudh Venkataramanan flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3238d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3239d76a60baSAnirudh Venkataramanan 3240d76a60baSAnirudh Venkataramanan if (!set) 3241d76a60baSAnirudh Venkataramanan goto ice_aq_get_set_rss_lut_send; 3242d76a60baSAnirudh Venkataramanan } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3243d76a60baSAnirudh Venkataramanan if (!set) 3244d76a60baSAnirudh Venkataramanan goto ice_aq_get_set_rss_lut_send; 3245d76a60baSAnirudh Venkataramanan } else { 3246d76a60baSAnirudh Venkataramanan goto ice_aq_get_set_rss_lut_send; 3247d76a60baSAnirudh Venkataramanan } 3248d76a60baSAnirudh Venkataramanan 3249d76a60baSAnirudh Venkataramanan /* LUT size is only valid for Global and PF table types */ 32504381147dSAnirudh Venkataramanan switch (lut_size) { 32514381147dSAnirudh Venkataramanan case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 32524381147dSAnirudh Venkataramanan break; 32534381147dSAnirudh Venkataramanan case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3254d76a60baSAnirudh Venkataramanan flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3255d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3256d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 32574381147dSAnirudh Venkataramanan break; 32584381147dSAnirudh Venkataramanan case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 32594381147dSAnirudh Venkataramanan if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3260d76a60baSAnirudh Venkataramanan flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3261d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3262d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 32634381147dSAnirudh Venkataramanan break; 32644381147dSAnirudh Venkataramanan } 32654e83fc93SBruce Allan fallthrough; 32664381147dSAnirudh Venkataramanan default: 3267d76a60baSAnirudh Venkataramanan status = ICE_ERR_PARAM; 3268d76a60baSAnirudh Venkataramanan goto ice_aq_get_set_rss_lut_exit; 3269d76a60baSAnirudh Venkataramanan } 3270d76a60baSAnirudh Venkataramanan 3271d76a60baSAnirudh Venkataramanan ice_aq_get_set_rss_lut_send: 3272d76a60baSAnirudh Venkataramanan cmd_resp->flags = cpu_to_le16(flags); 3273d76a60baSAnirudh Venkataramanan status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3274d76a60baSAnirudh Venkataramanan 3275d76a60baSAnirudh Venkataramanan ice_aq_get_set_rss_lut_exit: 3276d76a60baSAnirudh Venkataramanan return status; 3277d76a60baSAnirudh Venkataramanan } 3278d76a60baSAnirudh Venkataramanan 3279d76a60baSAnirudh Venkataramanan /** 3280d76a60baSAnirudh Venkataramanan * ice_aq_get_rss_lut 3281d76a60baSAnirudh Venkataramanan * @hw: pointer to the hardware structure 32824fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle 3283d76a60baSAnirudh Venkataramanan * @lut_type: LUT table type 3284d76a60baSAnirudh Venkataramanan * @lut: pointer to the LUT buffer provided by the caller 3285d76a60baSAnirudh Venkataramanan * @lut_size: size of the LUT buffer 3286d76a60baSAnirudh Venkataramanan * 3287d76a60baSAnirudh Venkataramanan * get the RSS lookup table, PF or VSI type 3288d76a60baSAnirudh Venkataramanan */ 3289d76a60baSAnirudh Venkataramanan enum ice_status 32904fb33f31SAnirudh Venkataramanan ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 32914fb33f31SAnirudh Venkataramanan u8 *lut, u16 lut_size) 3292d76a60baSAnirudh Venkataramanan { 32934fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 32944fb33f31SAnirudh Venkataramanan return ICE_ERR_PARAM; 32954fb33f31SAnirudh Venkataramanan 32964fb33f31SAnirudh Venkataramanan return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 32974fb33f31SAnirudh Venkataramanan lut_type, lut, lut_size, 0, false); 3298d76a60baSAnirudh Venkataramanan } 3299d76a60baSAnirudh Venkataramanan 3300d76a60baSAnirudh Venkataramanan /** 3301d76a60baSAnirudh Venkataramanan * ice_aq_set_rss_lut 3302d76a60baSAnirudh Venkataramanan * @hw: pointer to the hardware structure 33034fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle 3304d76a60baSAnirudh Venkataramanan * @lut_type: LUT table type 3305d76a60baSAnirudh Venkataramanan * @lut: pointer to the LUT buffer provided by the caller 3306d76a60baSAnirudh Venkataramanan * @lut_size: size of the LUT buffer 3307d76a60baSAnirudh Venkataramanan * 3308d76a60baSAnirudh Venkataramanan * set the RSS lookup table, PF or VSI type 3309d76a60baSAnirudh Venkataramanan */ 3310d76a60baSAnirudh Venkataramanan enum ice_status 33114fb33f31SAnirudh Venkataramanan ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 33124fb33f31SAnirudh Venkataramanan u8 *lut, u16 lut_size) 3313d76a60baSAnirudh Venkataramanan { 33144fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 33154fb33f31SAnirudh Venkataramanan return ICE_ERR_PARAM; 33164fb33f31SAnirudh Venkataramanan 33174fb33f31SAnirudh Venkataramanan return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 33184fb33f31SAnirudh Venkataramanan lut_type, lut, lut_size, 0, true); 3319d76a60baSAnirudh Venkataramanan } 3320d76a60baSAnirudh Venkataramanan 3321d76a60baSAnirudh Venkataramanan /** 3322d76a60baSAnirudh Venkataramanan * __ice_aq_get_set_rss_key 3323f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 3324d76a60baSAnirudh Venkataramanan * @vsi_id: VSI FW index 3325d76a60baSAnirudh Venkataramanan * @key: pointer to key info struct 3326d76a60baSAnirudh Venkataramanan * @set: set true to set the key, false to get the key 3327d76a60baSAnirudh Venkataramanan * 3328d76a60baSAnirudh Venkataramanan * get (0x0B04) or set (0x0B02) the RSS key per VSI 3329d76a60baSAnirudh Venkataramanan */ 3330d76a60baSAnirudh Venkataramanan static enum 3331d76a60baSAnirudh Venkataramanan ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3332d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_keys *key, 3333d76a60baSAnirudh Venkataramanan bool set) 3334d76a60baSAnirudh Venkataramanan { 3335d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_key *cmd_resp; 3336d76a60baSAnirudh Venkataramanan u16 key_size = sizeof(*key); 3337d76a60baSAnirudh Venkataramanan struct ice_aq_desc desc; 3338d76a60baSAnirudh Venkataramanan 3339d76a60baSAnirudh Venkataramanan cmd_resp = &desc.params.get_set_rss_key; 3340d76a60baSAnirudh Venkataramanan 3341d76a60baSAnirudh Venkataramanan if (set) { 3342d76a60baSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3343d76a60baSAnirudh Venkataramanan desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3344d76a60baSAnirudh Venkataramanan } else { 3345d76a60baSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3346d76a60baSAnirudh Venkataramanan } 3347d76a60baSAnirudh Venkataramanan 3348d76a60baSAnirudh Venkataramanan cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3349d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3350d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3351d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3352d76a60baSAnirudh Venkataramanan 3353d76a60baSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3354d76a60baSAnirudh Venkataramanan } 3355d76a60baSAnirudh Venkataramanan 3356d76a60baSAnirudh Venkataramanan /** 3357d76a60baSAnirudh Venkataramanan * ice_aq_get_rss_key 3358f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 33594fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle 3360d76a60baSAnirudh Venkataramanan * @key: pointer to key info struct 3361d76a60baSAnirudh Venkataramanan * 3362d76a60baSAnirudh Venkataramanan * get the RSS key per VSI 3363d76a60baSAnirudh Venkataramanan */ 3364d76a60baSAnirudh Venkataramanan enum ice_status 33654fb33f31SAnirudh Venkataramanan ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3366d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_keys *key) 3367d76a60baSAnirudh Venkataramanan { 33684fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 33694fb33f31SAnirudh Venkataramanan return ICE_ERR_PARAM; 33704fb33f31SAnirudh Venkataramanan 33714fb33f31SAnirudh Venkataramanan return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 33724fb33f31SAnirudh Venkataramanan key, false); 3373d76a60baSAnirudh Venkataramanan } 3374d76a60baSAnirudh Venkataramanan 3375d76a60baSAnirudh Venkataramanan /** 3376d76a60baSAnirudh Venkataramanan * ice_aq_set_rss_key 3377f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 33784fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle 3379d76a60baSAnirudh Venkataramanan * @keys: pointer to key info struct 3380d76a60baSAnirudh Venkataramanan * 3381d76a60baSAnirudh Venkataramanan * set the RSS key per VSI 3382d76a60baSAnirudh Venkataramanan */ 3383d76a60baSAnirudh Venkataramanan enum ice_status 33844fb33f31SAnirudh Venkataramanan ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3385d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_keys *keys) 3386d76a60baSAnirudh Venkataramanan { 33874fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 33884fb33f31SAnirudh Venkataramanan return ICE_ERR_PARAM; 33894fb33f31SAnirudh Venkataramanan 33904fb33f31SAnirudh Venkataramanan return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 33914fb33f31SAnirudh Venkataramanan keys, true); 3392d76a60baSAnirudh Venkataramanan } 3393d76a60baSAnirudh Venkataramanan 3394d76a60baSAnirudh Venkataramanan /** 3395cdedef59SAnirudh Venkataramanan * ice_aq_add_lan_txq 3396cdedef59SAnirudh Venkataramanan * @hw: pointer to the hardware structure 3397cdedef59SAnirudh Venkataramanan * @num_qgrps: Number of added queue groups 3398cdedef59SAnirudh Venkataramanan * @qg_list: list of queue groups to be added 3399cdedef59SAnirudh Venkataramanan * @buf_size: size of buffer for indirect command 3400cdedef59SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 3401cdedef59SAnirudh Venkataramanan * 3402cdedef59SAnirudh Venkataramanan * Add Tx LAN queue (0x0C30) 3403cdedef59SAnirudh Venkataramanan * 3404cdedef59SAnirudh Venkataramanan * NOTE: 3405cdedef59SAnirudh Venkataramanan * Prior to calling add Tx LAN queue: 3406cdedef59SAnirudh Venkataramanan * Initialize the following as part of the Tx queue context: 3407cdedef59SAnirudh Venkataramanan * Completion queue ID if the queue uses Completion queue, Quanta profile, 3408cdedef59SAnirudh Venkataramanan * Cache profile and Packet shaper profile. 3409cdedef59SAnirudh Venkataramanan * 3410cdedef59SAnirudh Venkataramanan * After add Tx LAN queue AQ command is completed: 3411cdedef59SAnirudh Venkataramanan * Interrupts should be associated with specific queues, 3412cdedef59SAnirudh Venkataramanan * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3413cdedef59SAnirudh Venkataramanan * flow. 3414cdedef59SAnirudh Venkataramanan */ 3415cdedef59SAnirudh Venkataramanan static enum ice_status 3416cdedef59SAnirudh Venkataramanan ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3417cdedef59SAnirudh Venkataramanan struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3418cdedef59SAnirudh Venkataramanan struct ice_sq_cd *cd) 3419cdedef59SAnirudh Venkataramanan { 3420cdedef59SAnirudh Venkataramanan struct ice_aqc_add_tx_qgrp *list; 3421cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs *cmd; 3422cdedef59SAnirudh Venkataramanan struct ice_aq_desc desc; 342366486d89SBruce Allan u16 i, sum_size = 0; 3424cdedef59SAnirudh Venkataramanan 3425cdedef59SAnirudh Venkataramanan cmd = &desc.params.add_txqs; 3426cdedef59SAnirudh Venkataramanan 3427cdedef59SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3428cdedef59SAnirudh Venkataramanan 3429cdedef59SAnirudh Venkataramanan if (!qg_list) 3430cdedef59SAnirudh Venkataramanan return ICE_ERR_PARAM; 3431cdedef59SAnirudh Venkataramanan 3432cdedef59SAnirudh Venkataramanan if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3433cdedef59SAnirudh Venkataramanan return ICE_ERR_PARAM; 3434cdedef59SAnirudh Venkataramanan 343566486d89SBruce Allan for (i = 0, list = qg_list; i < num_qgrps; i++) { 343666486d89SBruce Allan sum_size += struct_size(list, txqs, list->num_txqs); 343766486d89SBruce Allan list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 343866486d89SBruce Allan list->num_txqs); 3439cdedef59SAnirudh Venkataramanan } 3440cdedef59SAnirudh Venkataramanan 344166486d89SBruce Allan if (buf_size != sum_size) 3442cdedef59SAnirudh Venkataramanan return ICE_ERR_PARAM; 3443cdedef59SAnirudh Venkataramanan 3444cdedef59SAnirudh Venkataramanan desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3445cdedef59SAnirudh Venkataramanan 3446cdedef59SAnirudh Venkataramanan cmd->num_qgrps = num_qgrps; 3447cdedef59SAnirudh Venkataramanan 3448cdedef59SAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3449cdedef59SAnirudh Venkataramanan } 3450cdedef59SAnirudh Venkataramanan 3451cdedef59SAnirudh Venkataramanan /** 3452cdedef59SAnirudh Venkataramanan * ice_aq_dis_lan_txq 3453cdedef59SAnirudh Venkataramanan * @hw: pointer to the hardware structure 3454cdedef59SAnirudh Venkataramanan * @num_qgrps: number of groups in the list 3455cdedef59SAnirudh Venkataramanan * @qg_list: the list of groups to disable 3456cdedef59SAnirudh Venkataramanan * @buf_size: the total size of the qg_list buffer in bytes 345794c4441bSAnirudh Venkataramanan * @rst_src: if called due to reset, specifies the reset source 3458ddf30f7fSAnirudh Venkataramanan * @vmvf_num: the relative VM or VF number that is undergoing the reset 3459cdedef59SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 3460cdedef59SAnirudh Venkataramanan * 3461cdedef59SAnirudh Venkataramanan * Disable LAN Tx queue (0x0C31) 3462cdedef59SAnirudh Venkataramanan */ 3463cdedef59SAnirudh Venkataramanan static enum ice_status 3464cdedef59SAnirudh Venkataramanan ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3465cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3466ddf30f7fSAnirudh Venkataramanan enum ice_disq_rst_src rst_src, u16 vmvf_num, 3467cdedef59SAnirudh Venkataramanan struct ice_sq_cd *cd) 3468cdedef59SAnirudh Venkataramanan { 346966486d89SBruce Allan struct ice_aqc_dis_txq_item *item; 3470cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txqs *cmd; 3471cdedef59SAnirudh Venkataramanan struct ice_aq_desc desc; 34726e9650d5SVictor Raj enum ice_status status; 3473cdedef59SAnirudh Venkataramanan u16 i, sz = 0; 3474cdedef59SAnirudh Venkataramanan 3475cdedef59SAnirudh Venkataramanan cmd = &desc.params.dis_txqs; 3476cdedef59SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3477cdedef59SAnirudh Venkataramanan 3478ddf30f7fSAnirudh Venkataramanan /* qg_list can be NULL only in VM/VF reset flow */ 3479ddf30f7fSAnirudh Venkataramanan if (!qg_list && !rst_src) 3480cdedef59SAnirudh Venkataramanan return ICE_ERR_PARAM; 3481cdedef59SAnirudh Venkataramanan 3482cdedef59SAnirudh Venkataramanan if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3483cdedef59SAnirudh Venkataramanan return ICE_ERR_PARAM; 3484ddf30f7fSAnirudh Venkataramanan 3485cdedef59SAnirudh Venkataramanan cmd->num_entries = num_qgrps; 3486cdedef59SAnirudh Venkataramanan 3487ddf30f7fSAnirudh Venkataramanan cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3488ddf30f7fSAnirudh Venkataramanan ICE_AQC_Q_DIS_TIMEOUT_M); 3489ddf30f7fSAnirudh Venkataramanan 3490ddf30f7fSAnirudh Venkataramanan switch (rst_src) { 3491ddf30f7fSAnirudh Venkataramanan case ICE_VM_RESET: 3492ddf30f7fSAnirudh Venkataramanan cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3493ddf30f7fSAnirudh Venkataramanan cmd->vmvf_and_timeout |= 3494ddf30f7fSAnirudh Venkataramanan cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3495ddf30f7fSAnirudh Venkataramanan break; 3496ddf30f7fSAnirudh Venkataramanan case ICE_VF_RESET: 3497ddf30f7fSAnirudh Venkataramanan cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 3498f9867df6SAnirudh Venkataramanan /* In this case, FW expects vmvf_num to be absolute VF ID */ 3499ddf30f7fSAnirudh Venkataramanan cmd->vmvf_and_timeout |= 3500ddf30f7fSAnirudh Venkataramanan cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 3501ddf30f7fSAnirudh Venkataramanan ICE_AQC_Q_DIS_VMVF_NUM_M); 3502ddf30f7fSAnirudh Venkataramanan break; 3503ddf30f7fSAnirudh Venkataramanan case ICE_NO_RESET: 3504ddf30f7fSAnirudh Venkataramanan default: 3505ddf30f7fSAnirudh Venkataramanan break; 3506ddf30f7fSAnirudh Venkataramanan } 3507ddf30f7fSAnirudh Venkataramanan 35086e9650d5SVictor Raj /* flush pipe on time out */ 35096e9650d5SVictor Raj cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3510ddf30f7fSAnirudh Venkataramanan /* If no queue group info, we are in a reset flow. Issue the AQ */ 3511ddf30f7fSAnirudh Venkataramanan if (!qg_list) 3512ddf30f7fSAnirudh Venkataramanan goto do_aq; 3513ddf30f7fSAnirudh Venkataramanan 3514ddf30f7fSAnirudh Venkataramanan /* set RD bit to indicate that command buffer is provided by the driver 3515ddf30f7fSAnirudh Venkataramanan * and it needs to be read by the firmware 3516ddf30f7fSAnirudh Venkataramanan */ 3517ddf30f7fSAnirudh Venkataramanan desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3518ddf30f7fSAnirudh Venkataramanan 351966486d89SBruce Allan for (i = 0, item = qg_list; i < num_qgrps; i++) { 352066486d89SBruce Allan u16 item_size = struct_size(item, q_id, item->num_qs); 3521cdedef59SAnirudh Venkataramanan 3522cdedef59SAnirudh Venkataramanan /* If the num of queues is even, add 2 bytes of padding */ 352366486d89SBruce Allan if ((item->num_qs % 2) == 0) 352466486d89SBruce Allan item_size += 2; 352566486d89SBruce Allan 352666486d89SBruce Allan sz += item_size; 352766486d89SBruce Allan 352866486d89SBruce Allan item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 3529cdedef59SAnirudh Venkataramanan } 3530cdedef59SAnirudh Venkataramanan 3531cdedef59SAnirudh Venkataramanan if (buf_size != sz) 3532cdedef59SAnirudh Venkataramanan return ICE_ERR_PARAM; 3533cdedef59SAnirudh Venkataramanan 3534ddf30f7fSAnirudh Venkataramanan do_aq: 35356e9650d5SVictor Raj status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 35366e9650d5SVictor Raj if (status) { 35376e9650d5SVictor Raj if (!qg_list) 35386e9650d5SVictor Raj ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 35396e9650d5SVictor Raj vmvf_num, hw->adminq.sq_last_status); 35406e9650d5SVictor Raj else 35412f2da36eSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 35426e9650d5SVictor Raj le16_to_cpu(qg_list[0].q_id[0]), 35436e9650d5SVictor Raj hw->adminq.sq_last_status); 35446e9650d5SVictor Raj } 35456e9650d5SVictor Raj return status; 3546cdedef59SAnirudh Venkataramanan } 3547cdedef59SAnirudh Venkataramanan 3548cdedef59SAnirudh Venkataramanan /* End of FW Admin Queue command wrappers */ 3549cdedef59SAnirudh Venkataramanan 3550cdedef59SAnirudh Venkataramanan /** 3551cdedef59SAnirudh Venkataramanan * ice_write_byte - write a byte to a packed context structure 3552cdedef59SAnirudh Venkataramanan * @src_ctx: the context structure to read from 3553cdedef59SAnirudh Venkataramanan * @dest_ctx: the context to be written to 3554cdedef59SAnirudh Venkataramanan * @ce_info: a description of the struct to be filled 3555cdedef59SAnirudh Venkataramanan */ 3556c8b7abddSBruce Allan static void 3557c8b7abddSBruce Allan ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3558cdedef59SAnirudh Venkataramanan { 3559cdedef59SAnirudh Venkataramanan u8 src_byte, dest_byte, mask; 3560cdedef59SAnirudh Venkataramanan u8 *from, *dest; 3561cdedef59SAnirudh Venkataramanan u16 shift_width; 3562cdedef59SAnirudh Venkataramanan 3563cdedef59SAnirudh Venkataramanan /* copy from the next struct field */ 3564cdedef59SAnirudh Venkataramanan from = src_ctx + ce_info->offset; 3565cdedef59SAnirudh Venkataramanan 3566cdedef59SAnirudh Venkataramanan /* prepare the bits and mask */ 3567cdedef59SAnirudh Venkataramanan shift_width = ce_info->lsb % 8; 3568cdedef59SAnirudh Venkataramanan mask = (u8)(BIT(ce_info->width) - 1); 3569cdedef59SAnirudh Venkataramanan 3570cdedef59SAnirudh Venkataramanan src_byte = *from; 3571cdedef59SAnirudh Venkataramanan src_byte &= mask; 3572cdedef59SAnirudh Venkataramanan 3573cdedef59SAnirudh Venkataramanan /* shift to correct alignment */ 3574cdedef59SAnirudh Venkataramanan mask <<= shift_width; 3575cdedef59SAnirudh Venkataramanan src_byte <<= shift_width; 3576cdedef59SAnirudh Venkataramanan 3577cdedef59SAnirudh Venkataramanan /* get the current bits from the target bit string */ 3578cdedef59SAnirudh Venkataramanan dest = dest_ctx + (ce_info->lsb / 8); 3579cdedef59SAnirudh Venkataramanan 3580cdedef59SAnirudh Venkataramanan memcpy(&dest_byte, dest, sizeof(dest_byte)); 3581cdedef59SAnirudh Venkataramanan 3582cdedef59SAnirudh Venkataramanan dest_byte &= ~mask; /* get the bits not changing */ 3583cdedef59SAnirudh Venkataramanan dest_byte |= src_byte; /* add in the new bits */ 3584cdedef59SAnirudh Venkataramanan 3585cdedef59SAnirudh Venkataramanan /* put it all back */ 3586cdedef59SAnirudh Venkataramanan memcpy(dest, &dest_byte, sizeof(dest_byte)); 3587cdedef59SAnirudh Venkataramanan } 3588cdedef59SAnirudh Venkataramanan 3589cdedef59SAnirudh Venkataramanan /** 3590cdedef59SAnirudh Venkataramanan * ice_write_word - write a word to a packed context structure 3591cdedef59SAnirudh Venkataramanan * @src_ctx: the context structure to read from 3592cdedef59SAnirudh Venkataramanan * @dest_ctx: the context to be written to 3593cdedef59SAnirudh Venkataramanan * @ce_info: a description of the struct to be filled 3594cdedef59SAnirudh Venkataramanan */ 3595c8b7abddSBruce Allan static void 3596c8b7abddSBruce Allan ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3597cdedef59SAnirudh Venkataramanan { 3598cdedef59SAnirudh Venkataramanan u16 src_word, mask; 3599cdedef59SAnirudh Venkataramanan __le16 dest_word; 3600cdedef59SAnirudh Venkataramanan u8 *from, *dest; 3601cdedef59SAnirudh Venkataramanan u16 shift_width; 3602cdedef59SAnirudh Venkataramanan 3603cdedef59SAnirudh Venkataramanan /* copy from the next struct field */ 3604cdedef59SAnirudh Venkataramanan from = src_ctx + ce_info->offset; 3605cdedef59SAnirudh Venkataramanan 3606cdedef59SAnirudh Venkataramanan /* prepare the bits and mask */ 3607cdedef59SAnirudh Venkataramanan shift_width = ce_info->lsb % 8; 3608cdedef59SAnirudh Venkataramanan mask = BIT(ce_info->width) - 1; 3609cdedef59SAnirudh Venkataramanan 3610cdedef59SAnirudh Venkataramanan /* don't swizzle the bits until after the mask because the mask bits 3611cdedef59SAnirudh Venkataramanan * will be in a different bit position on big endian machines 3612cdedef59SAnirudh Venkataramanan */ 3613cdedef59SAnirudh Venkataramanan src_word = *(u16 *)from; 3614cdedef59SAnirudh Venkataramanan src_word &= mask; 3615cdedef59SAnirudh Venkataramanan 3616cdedef59SAnirudh Venkataramanan /* shift to correct alignment */ 3617cdedef59SAnirudh Venkataramanan mask <<= shift_width; 3618cdedef59SAnirudh Venkataramanan src_word <<= shift_width; 3619cdedef59SAnirudh Venkataramanan 3620cdedef59SAnirudh Venkataramanan /* get the current bits from the target bit string */ 3621cdedef59SAnirudh Venkataramanan dest = dest_ctx + (ce_info->lsb / 8); 3622cdedef59SAnirudh Venkataramanan 3623cdedef59SAnirudh Venkataramanan memcpy(&dest_word, dest, sizeof(dest_word)); 3624cdedef59SAnirudh Venkataramanan 3625cdedef59SAnirudh Venkataramanan dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 3626cdedef59SAnirudh Venkataramanan dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 3627cdedef59SAnirudh Venkataramanan 3628cdedef59SAnirudh Venkataramanan /* put it all back */ 3629cdedef59SAnirudh Venkataramanan memcpy(dest, &dest_word, sizeof(dest_word)); 3630cdedef59SAnirudh Venkataramanan } 3631cdedef59SAnirudh Venkataramanan 3632cdedef59SAnirudh Venkataramanan /** 3633cdedef59SAnirudh Venkataramanan * ice_write_dword - write a dword to a packed context structure 3634cdedef59SAnirudh Venkataramanan * @src_ctx: the context structure to read from 3635cdedef59SAnirudh Venkataramanan * @dest_ctx: the context to be written to 3636cdedef59SAnirudh Venkataramanan * @ce_info: a description of the struct to be filled 3637cdedef59SAnirudh Venkataramanan */ 3638c8b7abddSBruce Allan static void 3639c8b7abddSBruce Allan ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3640cdedef59SAnirudh Venkataramanan { 3641cdedef59SAnirudh Venkataramanan u32 src_dword, mask; 3642cdedef59SAnirudh Venkataramanan __le32 dest_dword; 3643cdedef59SAnirudh Venkataramanan u8 *from, *dest; 3644cdedef59SAnirudh Venkataramanan u16 shift_width; 3645cdedef59SAnirudh Venkataramanan 3646cdedef59SAnirudh Venkataramanan /* copy from the next struct field */ 3647cdedef59SAnirudh Venkataramanan from = src_ctx + ce_info->offset; 3648cdedef59SAnirudh Venkataramanan 3649cdedef59SAnirudh Venkataramanan /* prepare the bits and mask */ 3650cdedef59SAnirudh Venkataramanan shift_width = ce_info->lsb % 8; 3651cdedef59SAnirudh Venkataramanan 3652cdedef59SAnirudh Venkataramanan /* if the field width is exactly 32 on an x86 machine, then the shift 3653cdedef59SAnirudh Venkataramanan * operation will not work because the SHL instructions count is masked 3654cdedef59SAnirudh Venkataramanan * to 5 bits so the shift will do nothing 3655cdedef59SAnirudh Venkataramanan */ 3656cdedef59SAnirudh Venkataramanan if (ce_info->width < 32) 3657cdedef59SAnirudh Venkataramanan mask = BIT(ce_info->width) - 1; 3658cdedef59SAnirudh Venkataramanan else 3659cdedef59SAnirudh Venkataramanan mask = (u32)~0; 3660cdedef59SAnirudh Venkataramanan 3661cdedef59SAnirudh Venkataramanan /* don't swizzle the bits until after the mask because the mask bits 3662cdedef59SAnirudh Venkataramanan * will be in a different bit position on big endian machines 3663cdedef59SAnirudh Venkataramanan */ 3664cdedef59SAnirudh Venkataramanan src_dword = *(u32 *)from; 3665cdedef59SAnirudh Venkataramanan src_dword &= mask; 3666cdedef59SAnirudh Venkataramanan 3667cdedef59SAnirudh Venkataramanan /* shift to correct alignment */ 3668cdedef59SAnirudh Venkataramanan mask <<= shift_width; 3669cdedef59SAnirudh Venkataramanan src_dword <<= shift_width; 3670cdedef59SAnirudh Venkataramanan 3671cdedef59SAnirudh Venkataramanan /* get the current bits from the target bit string */ 3672cdedef59SAnirudh Venkataramanan dest = dest_ctx + (ce_info->lsb / 8); 3673cdedef59SAnirudh Venkataramanan 3674cdedef59SAnirudh Venkataramanan memcpy(&dest_dword, dest, sizeof(dest_dword)); 3675cdedef59SAnirudh Venkataramanan 3676cdedef59SAnirudh Venkataramanan dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 3677cdedef59SAnirudh Venkataramanan dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 3678cdedef59SAnirudh Venkataramanan 3679cdedef59SAnirudh Venkataramanan /* put it all back */ 3680cdedef59SAnirudh Venkataramanan memcpy(dest, &dest_dword, sizeof(dest_dword)); 3681cdedef59SAnirudh Venkataramanan } 3682cdedef59SAnirudh Venkataramanan 3683cdedef59SAnirudh Venkataramanan /** 3684cdedef59SAnirudh Venkataramanan * ice_write_qword - write a qword to a packed context structure 3685cdedef59SAnirudh Venkataramanan * @src_ctx: the context structure to read from 3686cdedef59SAnirudh Venkataramanan * @dest_ctx: the context to be written to 3687cdedef59SAnirudh Venkataramanan * @ce_info: a description of the struct to be filled 3688cdedef59SAnirudh Venkataramanan */ 3689c8b7abddSBruce Allan static void 3690c8b7abddSBruce Allan ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3691cdedef59SAnirudh Venkataramanan { 3692cdedef59SAnirudh Venkataramanan u64 src_qword, mask; 3693cdedef59SAnirudh Venkataramanan __le64 dest_qword; 3694cdedef59SAnirudh Venkataramanan u8 *from, *dest; 3695cdedef59SAnirudh Venkataramanan u16 shift_width; 3696cdedef59SAnirudh Venkataramanan 3697cdedef59SAnirudh Venkataramanan /* copy from the next struct field */ 3698cdedef59SAnirudh Venkataramanan from = src_ctx + ce_info->offset; 3699cdedef59SAnirudh Venkataramanan 3700cdedef59SAnirudh Venkataramanan /* prepare the bits and mask */ 3701cdedef59SAnirudh Venkataramanan shift_width = ce_info->lsb % 8; 3702cdedef59SAnirudh Venkataramanan 3703cdedef59SAnirudh Venkataramanan /* if the field width is exactly 64 on an x86 machine, then the shift 3704cdedef59SAnirudh Venkataramanan * operation will not work because the SHL instructions count is masked 3705cdedef59SAnirudh Venkataramanan * to 6 bits so the shift will do nothing 3706cdedef59SAnirudh Venkataramanan */ 3707cdedef59SAnirudh Venkataramanan if (ce_info->width < 64) 3708cdedef59SAnirudh Venkataramanan mask = BIT_ULL(ce_info->width) - 1; 3709cdedef59SAnirudh Venkataramanan else 3710cdedef59SAnirudh Venkataramanan mask = (u64)~0; 3711cdedef59SAnirudh Venkataramanan 3712cdedef59SAnirudh Venkataramanan /* don't swizzle the bits until after the mask because the mask bits 3713cdedef59SAnirudh Venkataramanan * will be in a different bit position on big endian machines 3714cdedef59SAnirudh Venkataramanan */ 3715cdedef59SAnirudh Venkataramanan src_qword = *(u64 *)from; 3716cdedef59SAnirudh Venkataramanan src_qword &= mask; 3717cdedef59SAnirudh Venkataramanan 3718cdedef59SAnirudh Venkataramanan /* shift to correct alignment */ 3719cdedef59SAnirudh Venkataramanan mask <<= shift_width; 3720cdedef59SAnirudh Venkataramanan src_qword <<= shift_width; 3721cdedef59SAnirudh Venkataramanan 3722cdedef59SAnirudh Venkataramanan /* get the current bits from the target bit string */ 3723cdedef59SAnirudh Venkataramanan dest = dest_ctx + (ce_info->lsb / 8); 3724cdedef59SAnirudh Venkataramanan 3725cdedef59SAnirudh Venkataramanan memcpy(&dest_qword, dest, sizeof(dest_qword)); 3726cdedef59SAnirudh Venkataramanan 3727cdedef59SAnirudh Venkataramanan dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 3728cdedef59SAnirudh Venkataramanan dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 3729cdedef59SAnirudh Venkataramanan 3730cdedef59SAnirudh Venkataramanan /* put it all back */ 3731cdedef59SAnirudh Venkataramanan memcpy(dest, &dest_qword, sizeof(dest_qword)); 3732cdedef59SAnirudh Venkataramanan } 3733cdedef59SAnirudh Venkataramanan 3734cdedef59SAnirudh Venkataramanan /** 3735cdedef59SAnirudh Venkataramanan * ice_set_ctx - set context bits in packed structure 37367e34786aSBruce Allan * @hw: pointer to the hardware structure 3737cdedef59SAnirudh Venkataramanan * @src_ctx: pointer to a generic non-packed context structure 3738cdedef59SAnirudh Venkataramanan * @dest_ctx: pointer to memory for the packed structure 3739cdedef59SAnirudh Venkataramanan * @ce_info: a description of the structure to be transformed 3740cdedef59SAnirudh Venkataramanan */ 3741cdedef59SAnirudh Venkataramanan enum ice_status 37427e34786aSBruce Allan ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 37437e34786aSBruce Allan const struct ice_ctx_ele *ce_info) 3744cdedef59SAnirudh Venkataramanan { 3745cdedef59SAnirudh Venkataramanan int f; 3746cdedef59SAnirudh Venkataramanan 3747cdedef59SAnirudh Venkataramanan for (f = 0; ce_info[f].width; f++) { 3748cdedef59SAnirudh Venkataramanan /* We have to deal with each element of the FW response 3749cdedef59SAnirudh Venkataramanan * using the correct size so that we are correct regardless 3750cdedef59SAnirudh Venkataramanan * of the endianness of the machine. 3751cdedef59SAnirudh Venkataramanan */ 37527e34786aSBruce Allan if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 37537e34786aSBruce Allan ice_debug(hw, ICE_DBG_QCTX, 37547e34786aSBruce Allan "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 37557e34786aSBruce Allan f, ce_info[f].width, ce_info[f].size_of); 37567e34786aSBruce Allan continue; 37577e34786aSBruce Allan } 3758cdedef59SAnirudh Venkataramanan switch (ce_info[f].size_of) { 3759cdedef59SAnirudh Venkataramanan case sizeof(u8): 3760cdedef59SAnirudh Venkataramanan ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 3761cdedef59SAnirudh Venkataramanan break; 3762cdedef59SAnirudh Venkataramanan case sizeof(u16): 3763cdedef59SAnirudh Venkataramanan ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 3764cdedef59SAnirudh Venkataramanan break; 3765cdedef59SAnirudh Venkataramanan case sizeof(u32): 3766cdedef59SAnirudh Venkataramanan ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 3767cdedef59SAnirudh Venkataramanan break; 3768cdedef59SAnirudh Venkataramanan case sizeof(u64): 3769cdedef59SAnirudh Venkataramanan ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 3770cdedef59SAnirudh Venkataramanan break; 3771cdedef59SAnirudh Venkataramanan default: 3772cdedef59SAnirudh Venkataramanan return ICE_ERR_INVAL_SIZE; 3773cdedef59SAnirudh Venkataramanan } 3774cdedef59SAnirudh Venkataramanan } 3775cdedef59SAnirudh Venkataramanan 3776cdedef59SAnirudh Venkataramanan return 0; 3777cdedef59SAnirudh Venkataramanan } 3778cdedef59SAnirudh Venkataramanan 3779cdedef59SAnirudh Venkataramanan /** 3780bb87ee0eSAnirudh Venkataramanan * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 3781bb87ee0eSAnirudh Venkataramanan * @hw: pointer to the HW struct 3782bb87ee0eSAnirudh Venkataramanan * @vsi_handle: software VSI handle 3783bb87ee0eSAnirudh Venkataramanan * @tc: TC number 3784bb87ee0eSAnirudh Venkataramanan * @q_handle: software queue handle 3785bb87ee0eSAnirudh Venkataramanan */ 37861ddef455SUsha Ketineni struct ice_q_ctx * 3787bb87ee0eSAnirudh Venkataramanan ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 3788bb87ee0eSAnirudh Venkataramanan { 3789bb87ee0eSAnirudh Venkataramanan struct ice_vsi_ctx *vsi; 3790bb87ee0eSAnirudh Venkataramanan struct ice_q_ctx *q_ctx; 3791bb87ee0eSAnirudh Venkataramanan 3792bb87ee0eSAnirudh Venkataramanan vsi = ice_get_vsi_ctx(hw, vsi_handle); 3793bb87ee0eSAnirudh Venkataramanan if (!vsi) 3794bb87ee0eSAnirudh Venkataramanan return NULL; 3795bb87ee0eSAnirudh Venkataramanan if (q_handle >= vsi->num_lan_q_entries[tc]) 3796bb87ee0eSAnirudh Venkataramanan return NULL; 3797bb87ee0eSAnirudh Venkataramanan if (!vsi->lan_q_ctx[tc]) 3798bb87ee0eSAnirudh Venkataramanan return NULL; 3799bb87ee0eSAnirudh Venkataramanan q_ctx = vsi->lan_q_ctx[tc]; 3800bb87ee0eSAnirudh Venkataramanan return &q_ctx[q_handle]; 3801bb87ee0eSAnirudh Venkataramanan } 3802bb87ee0eSAnirudh Venkataramanan 3803bb87ee0eSAnirudh Venkataramanan /** 3804cdedef59SAnirudh Venkataramanan * ice_ena_vsi_txq 3805cdedef59SAnirudh Venkataramanan * @pi: port information structure 38064fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle 3807f9867df6SAnirudh Venkataramanan * @tc: TC number 3808bb87ee0eSAnirudh Venkataramanan * @q_handle: software queue handle 3809cdedef59SAnirudh Venkataramanan * @num_qgrps: Number of added queue groups 3810cdedef59SAnirudh Venkataramanan * @buf: list of queue groups to be added 3811cdedef59SAnirudh Venkataramanan * @buf_size: size of buffer for indirect command 3812cdedef59SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 3813cdedef59SAnirudh Venkataramanan * 3814f9867df6SAnirudh Venkataramanan * This function adds one LAN queue 3815cdedef59SAnirudh Venkataramanan */ 3816cdedef59SAnirudh Venkataramanan enum ice_status 3817bb87ee0eSAnirudh Venkataramanan ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 3818bb87ee0eSAnirudh Venkataramanan u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 3819cdedef59SAnirudh Venkataramanan struct ice_sq_cd *cd) 3820cdedef59SAnirudh Venkataramanan { 3821cdedef59SAnirudh Venkataramanan struct ice_aqc_txsched_elem_data node = { 0 }; 3822cdedef59SAnirudh Venkataramanan struct ice_sched_node *parent; 3823bb87ee0eSAnirudh Venkataramanan struct ice_q_ctx *q_ctx; 3824cdedef59SAnirudh Venkataramanan enum ice_status status; 3825cdedef59SAnirudh Venkataramanan struct ice_hw *hw; 3826cdedef59SAnirudh Venkataramanan 3827cdedef59SAnirudh Venkataramanan if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3828cdedef59SAnirudh Venkataramanan return ICE_ERR_CFG; 3829cdedef59SAnirudh Venkataramanan 3830cdedef59SAnirudh Venkataramanan if (num_qgrps > 1 || buf->num_txqs > 1) 3831cdedef59SAnirudh Venkataramanan return ICE_ERR_MAX_LIMIT; 3832cdedef59SAnirudh Venkataramanan 3833cdedef59SAnirudh Venkataramanan hw = pi->hw; 3834cdedef59SAnirudh Venkataramanan 38354fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle)) 38364fb33f31SAnirudh Venkataramanan return ICE_ERR_PARAM; 38374fb33f31SAnirudh Venkataramanan 3838cdedef59SAnirudh Venkataramanan mutex_lock(&pi->sched_lock); 3839cdedef59SAnirudh Venkataramanan 3840bb87ee0eSAnirudh Venkataramanan q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 3841bb87ee0eSAnirudh Venkataramanan if (!q_ctx) { 3842bb87ee0eSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 3843bb87ee0eSAnirudh Venkataramanan q_handle); 3844bb87ee0eSAnirudh Venkataramanan status = ICE_ERR_PARAM; 3845bb87ee0eSAnirudh Venkataramanan goto ena_txq_exit; 3846bb87ee0eSAnirudh Venkataramanan } 3847bb87ee0eSAnirudh Venkataramanan 3848cdedef59SAnirudh Venkataramanan /* find a parent node */ 38494fb33f31SAnirudh Venkataramanan parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 3850cdedef59SAnirudh Venkataramanan ICE_SCHED_NODE_OWNER_LAN); 3851cdedef59SAnirudh Venkataramanan if (!parent) { 3852cdedef59SAnirudh Venkataramanan status = ICE_ERR_PARAM; 3853cdedef59SAnirudh Venkataramanan goto ena_txq_exit; 3854cdedef59SAnirudh Venkataramanan } 38554fb33f31SAnirudh Venkataramanan 3856cdedef59SAnirudh Venkataramanan buf->parent_teid = parent->info.node_teid; 3857cdedef59SAnirudh Venkataramanan node.parent_teid = parent->info.node_teid; 3858cdedef59SAnirudh Venkataramanan /* Mark that the values in the "generic" section as valid. The default 3859cdedef59SAnirudh Venkataramanan * value in the "generic" section is zero. This means that : 3860cdedef59SAnirudh Venkataramanan * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 3861cdedef59SAnirudh Venkataramanan * - 0 priority among siblings, indicated by Bit 1-3. 3862cdedef59SAnirudh Venkataramanan * - WFQ, indicated by Bit 4. 3863cdedef59SAnirudh Venkataramanan * - 0 Adjustment value is used in PSM credit update flow, indicated by 3864cdedef59SAnirudh Venkataramanan * Bit 5-6. 3865cdedef59SAnirudh Venkataramanan * - Bit 7 is reserved. 3866cdedef59SAnirudh Venkataramanan * Without setting the generic section as valid in valid_sections, the 3867f9867df6SAnirudh Venkataramanan * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 3868cdedef59SAnirudh Venkataramanan */ 3869cdedef59SAnirudh Venkataramanan buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC; 3870cdedef59SAnirudh Venkataramanan 3871f9867df6SAnirudh Venkataramanan /* add the LAN queue */ 3872cdedef59SAnirudh Venkataramanan status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 38736e9650d5SVictor Raj if (status) { 3874bb87ee0eSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 38756e9650d5SVictor Raj le16_to_cpu(buf->txqs[0].txq_id), 38766e9650d5SVictor Raj hw->adminq.sq_last_status); 3877cdedef59SAnirudh Venkataramanan goto ena_txq_exit; 38786e9650d5SVictor Raj } 3879cdedef59SAnirudh Venkataramanan 3880cdedef59SAnirudh Venkataramanan node.node_teid = buf->txqs[0].q_teid; 3881cdedef59SAnirudh Venkataramanan node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 3882bb87ee0eSAnirudh Venkataramanan q_ctx->q_handle = q_handle; 38831ddef455SUsha Ketineni q_ctx->q_teid = le32_to_cpu(node.node_teid); 3884cdedef59SAnirudh Venkataramanan 38851ddef455SUsha Ketineni /* add a leaf node into scheduler tree queue layer */ 3886cdedef59SAnirudh Venkataramanan status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 38871ddef455SUsha Ketineni if (!status) 38881ddef455SUsha Ketineni status = ice_sched_replay_q_bw(pi, q_ctx); 3889cdedef59SAnirudh Venkataramanan 3890cdedef59SAnirudh Venkataramanan ena_txq_exit: 3891cdedef59SAnirudh Venkataramanan mutex_unlock(&pi->sched_lock); 3892cdedef59SAnirudh Venkataramanan return status; 3893cdedef59SAnirudh Venkataramanan } 3894cdedef59SAnirudh Venkataramanan 3895cdedef59SAnirudh Venkataramanan /** 3896cdedef59SAnirudh Venkataramanan * ice_dis_vsi_txq 3897cdedef59SAnirudh Venkataramanan * @pi: port information structure 3898bb87ee0eSAnirudh Venkataramanan * @vsi_handle: software VSI handle 3899bb87ee0eSAnirudh Venkataramanan * @tc: TC number 3900cdedef59SAnirudh Venkataramanan * @num_queues: number of queues 3901bb87ee0eSAnirudh Venkataramanan * @q_handles: pointer to software queue handle array 3902cdedef59SAnirudh Venkataramanan * @q_ids: pointer to the q_id array 3903cdedef59SAnirudh Venkataramanan * @q_teids: pointer to queue node teids 390494c4441bSAnirudh Venkataramanan * @rst_src: if called due to reset, specifies the reset source 3905ddf30f7fSAnirudh Venkataramanan * @vmvf_num: the relative VM or VF number that is undergoing the reset 3906cdedef59SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 3907cdedef59SAnirudh Venkataramanan * 3908cdedef59SAnirudh Venkataramanan * This function removes queues and their corresponding nodes in SW DB 3909cdedef59SAnirudh Venkataramanan */ 3910cdedef59SAnirudh Venkataramanan enum ice_status 3911bb87ee0eSAnirudh Venkataramanan ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 3912bb87ee0eSAnirudh Venkataramanan u16 *q_handles, u16 *q_ids, u32 *q_teids, 3913bb87ee0eSAnirudh Venkataramanan enum ice_disq_rst_src rst_src, u16 vmvf_num, 3914ddf30f7fSAnirudh Venkataramanan struct ice_sq_cd *cd) 3915cdedef59SAnirudh Venkataramanan { 3916cdedef59SAnirudh Venkataramanan enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 391766486d89SBruce Allan struct ice_aqc_dis_txq_item *qg_list; 3918bb87ee0eSAnirudh Venkataramanan struct ice_q_ctx *q_ctx; 391966486d89SBruce Allan struct ice_hw *hw; 392066486d89SBruce Allan u16 i, buf_size; 3921cdedef59SAnirudh Venkataramanan 3922cdedef59SAnirudh Venkataramanan if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3923cdedef59SAnirudh Venkataramanan return ICE_ERR_CFG; 3924cdedef59SAnirudh Venkataramanan 392566486d89SBruce Allan hw = pi->hw; 392666486d89SBruce Allan 392785796d6eSAkeem G Abodunrin if (!num_queues) { 392885796d6eSAkeem G Abodunrin /* if queue is disabled already yet the disable queue command 392985796d6eSAkeem G Abodunrin * has to be sent to complete the VF reset, then call 393085796d6eSAkeem G Abodunrin * ice_aq_dis_lan_txq without any queue information 393185796d6eSAkeem G Abodunrin */ 393285796d6eSAkeem G Abodunrin if (rst_src) 393366486d89SBruce Allan return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 393485796d6eSAkeem G Abodunrin vmvf_num, NULL); 393585796d6eSAkeem G Abodunrin return ICE_ERR_CFG; 393685796d6eSAkeem G Abodunrin } 3937ddf30f7fSAnirudh Venkataramanan 393866486d89SBruce Allan buf_size = struct_size(qg_list, q_id, 1); 393966486d89SBruce Allan qg_list = kzalloc(buf_size, GFP_KERNEL); 394066486d89SBruce Allan if (!qg_list) 394166486d89SBruce Allan return ICE_ERR_NO_MEMORY; 394266486d89SBruce Allan 3943cdedef59SAnirudh Venkataramanan mutex_lock(&pi->sched_lock); 3944cdedef59SAnirudh Venkataramanan 3945cdedef59SAnirudh Venkataramanan for (i = 0; i < num_queues; i++) { 3946cdedef59SAnirudh Venkataramanan struct ice_sched_node *node; 3947cdedef59SAnirudh Venkataramanan 3948cdedef59SAnirudh Venkataramanan node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 3949cdedef59SAnirudh Venkataramanan if (!node) 3950cdedef59SAnirudh Venkataramanan continue; 395166486d89SBruce Allan q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 3952bb87ee0eSAnirudh Venkataramanan if (!q_ctx) { 395366486d89SBruce Allan ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 3954bb87ee0eSAnirudh Venkataramanan q_handles[i]); 3955bb87ee0eSAnirudh Venkataramanan continue; 3956bb87ee0eSAnirudh Venkataramanan } 3957bb87ee0eSAnirudh Venkataramanan if (q_ctx->q_handle != q_handles[i]) { 395866486d89SBruce Allan ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 3959bb87ee0eSAnirudh Venkataramanan q_ctx->q_handle, q_handles[i]); 3960bb87ee0eSAnirudh Venkataramanan continue; 3961bb87ee0eSAnirudh Venkataramanan } 396266486d89SBruce Allan qg_list->parent_teid = node->info.parent_teid; 396366486d89SBruce Allan qg_list->num_qs = 1; 396466486d89SBruce Allan qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 396566486d89SBruce Allan status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 396666486d89SBruce Allan vmvf_num, cd); 3967cdedef59SAnirudh Venkataramanan 3968cdedef59SAnirudh Venkataramanan if (status) 3969cdedef59SAnirudh Venkataramanan break; 3970cdedef59SAnirudh Venkataramanan ice_free_sched_node(pi, node); 3971bb87ee0eSAnirudh Venkataramanan q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 3972cdedef59SAnirudh Venkataramanan } 3973cdedef59SAnirudh Venkataramanan mutex_unlock(&pi->sched_lock); 397466486d89SBruce Allan kfree(qg_list); 3975cdedef59SAnirudh Venkataramanan return status; 3976cdedef59SAnirudh Venkataramanan } 39775513b920SAnirudh Venkataramanan 39785513b920SAnirudh Venkataramanan /** 397994c4441bSAnirudh Venkataramanan * ice_cfg_vsi_qs - configure the new/existing VSI queues 39805513b920SAnirudh Venkataramanan * @pi: port information structure 39814fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle 39825513b920SAnirudh Venkataramanan * @tc_bitmap: TC bitmap 39835513b920SAnirudh Venkataramanan * @maxqs: max queues array per TC 3984f9867df6SAnirudh Venkataramanan * @owner: LAN or RDMA 39855513b920SAnirudh Venkataramanan * 39865513b920SAnirudh Venkataramanan * This function adds/updates the VSI queues per TC. 39875513b920SAnirudh Venkataramanan */ 39885513b920SAnirudh Venkataramanan static enum ice_status 39894fb33f31SAnirudh Venkataramanan ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 39905513b920SAnirudh Venkataramanan u16 *maxqs, u8 owner) 39915513b920SAnirudh Venkataramanan { 39925513b920SAnirudh Venkataramanan enum ice_status status = 0; 39935513b920SAnirudh Venkataramanan u8 i; 39945513b920SAnirudh Venkataramanan 39955513b920SAnirudh Venkataramanan if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 39965513b920SAnirudh Venkataramanan return ICE_ERR_CFG; 39975513b920SAnirudh Venkataramanan 39984fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 39994fb33f31SAnirudh Venkataramanan return ICE_ERR_PARAM; 40004fb33f31SAnirudh Venkataramanan 40015513b920SAnirudh Venkataramanan mutex_lock(&pi->sched_lock); 40025513b920SAnirudh Venkataramanan 40032bdc97beSBruce Allan ice_for_each_traffic_class(i) { 40045513b920SAnirudh Venkataramanan /* configuration is possible only if TC node is present */ 40055513b920SAnirudh Venkataramanan if (!ice_sched_get_tc_node(pi, i)) 40065513b920SAnirudh Venkataramanan continue; 40075513b920SAnirudh Venkataramanan 40084fb33f31SAnirudh Venkataramanan status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 40095513b920SAnirudh Venkataramanan ice_is_tc_ena(tc_bitmap, i)); 40105513b920SAnirudh Venkataramanan if (status) 40115513b920SAnirudh Venkataramanan break; 40125513b920SAnirudh Venkataramanan } 40135513b920SAnirudh Venkataramanan 40145513b920SAnirudh Venkataramanan mutex_unlock(&pi->sched_lock); 40155513b920SAnirudh Venkataramanan return status; 40165513b920SAnirudh Venkataramanan } 40175513b920SAnirudh Venkataramanan 40185513b920SAnirudh Venkataramanan /** 4019f9867df6SAnirudh Venkataramanan * ice_cfg_vsi_lan - configure VSI LAN queues 40205513b920SAnirudh Venkataramanan * @pi: port information structure 40214fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle 40225513b920SAnirudh Venkataramanan * @tc_bitmap: TC bitmap 4023f9867df6SAnirudh Venkataramanan * @max_lanqs: max LAN queues array per TC 40245513b920SAnirudh Venkataramanan * 4025f9867df6SAnirudh Venkataramanan * This function adds/updates the VSI LAN queues per TC. 40265513b920SAnirudh Venkataramanan */ 40275513b920SAnirudh Venkataramanan enum ice_status 40284fb33f31SAnirudh Venkataramanan ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 40295513b920SAnirudh Venkataramanan u16 *max_lanqs) 40305513b920SAnirudh Venkataramanan { 40314fb33f31SAnirudh Venkataramanan return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 40325513b920SAnirudh Venkataramanan ICE_SCHED_NODE_OWNER_LAN); 40335513b920SAnirudh Venkataramanan } 403445d3d428SAnirudh Venkataramanan 403545d3d428SAnirudh Venkataramanan /** 4036334cb062SAnirudh Venkataramanan * ice_replay_pre_init - replay pre initialization 4037f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 4038334cb062SAnirudh Venkataramanan * 4039334cb062SAnirudh Venkataramanan * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4040334cb062SAnirudh Venkataramanan */ 4041334cb062SAnirudh Venkataramanan static enum ice_status ice_replay_pre_init(struct ice_hw *hw) 4042334cb062SAnirudh Venkataramanan { 4043334cb062SAnirudh Venkataramanan struct ice_switch_info *sw = hw->switch_info; 4044334cb062SAnirudh Venkataramanan u8 i; 4045334cb062SAnirudh Venkataramanan 4046334cb062SAnirudh Venkataramanan /* Delete old entries from replay filter list head if there is any */ 4047334cb062SAnirudh Venkataramanan ice_rm_all_sw_replay_rule_info(hw); 4048334cb062SAnirudh Venkataramanan /* In start of replay, move entries into replay_rules list, it 4049334cb062SAnirudh Venkataramanan * will allow adding rules entries back to filt_rules list, 4050334cb062SAnirudh Venkataramanan * which is operational list. 4051334cb062SAnirudh Venkataramanan */ 4052334cb062SAnirudh Venkataramanan for (i = 0; i < ICE_SW_LKUP_LAST; i++) 4053334cb062SAnirudh Venkataramanan list_replace_init(&sw->recp_list[i].filt_rules, 4054334cb062SAnirudh Venkataramanan &sw->recp_list[i].filt_replay_rules); 4055334cb062SAnirudh Venkataramanan 4056334cb062SAnirudh Venkataramanan return 0; 4057334cb062SAnirudh Venkataramanan } 4058334cb062SAnirudh Venkataramanan 4059334cb062SAnirudh Venkataramanan /** 4060334cb062SAnirudh Venkataramanan * ice_replay_vsi - replay VSI configuration 4061f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 4062334cb062SAnirudh Venkataramanan * @vsi_handle: driver VSI handle 4063334cb062SAnirudh Venkataramanan * 4064334cb062SAnirudh Venkataramanan * Restore all VSI configuration after reset. It is required to call this 4065334cb062SAnirudh Venkataramanan * function with main VSI first. 4066334cb062SAnirudh Venkataramanan */ 4067334cb062SAnirudh Venkataramanan enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4068334cb062SAnirudh Venkataramanan { 4069334cb062SAnirudh Venkataramanan enum ice_status status; 4070334cb062SAnirudh Venkataramanan 4071334cb062SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle)) 4072334cb062SAnirudh Venkataramanan return ICE_ERR_PARAM; 4073334cb062SAnirudh Venkataramanan 4074334cb062SAnirudh Venkataramanan /* Replay pre-initialization if there is any */ 4075334cb062SAnirudh Venkataramanan if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 4076334cb062SAnirudh Venkataramanan status = ice_replay_pre_init(hw); 4077334cb062SAnirudh Venkataramanan if (status) 4078334cb062SAnirudh Venkataramanan return status; 4079334cb062SAnirudh Venkataramanan } 4080c90ed40cSTony Nguyen /* Replay per VSI all RSS configurations */ 4081c90ed40cSTony Nguyen status = ice_replay_rss_cfg(hw, vsi_handle); 4082c90ed40cSTony Nguyen if (status) 4083c90ed40cSTony Nguyen return status; 4084334cb062SAnirudh Venkataramanan /* Replay per VSI all filters */ 4085334cb062SAnirudh Venkataramanan status = ice_replay_vsi_all_fltr(hw, vsi_handle); 4086334cb062SAnirudh Venkataramanan return status; 4087334cb062SAnirudh Venkataramanan } 4088334cb062SAnirudh Venkataramanan 4089334cb062SAnirudh Venkataramanan /** 4090334cb062SAnirudh Venkataramanan * ice_replay_post - post replay configuration cleanup 4091f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 4092334cb062SAnirudh Venkataramanan * 4093334cb062SAnirudh Venkataramanan * Post replay cleanup. 4094334cb062SAnirudh Venkataramanan */ 4095334cb062SAnirudh Venkataramanan void ice_replay_post(struct ice_hw *hw) 4096334cb062SAnirudh Venkataramanan { 4097334cb062SAnirudh Venkataramanan /* Delete old entries from replay filter list head */ 4098334cb062SAnirudh Venkataramanan ice_rm_all_sw_replay_rule_info(hw); 4099334cb062SAnirudh Venkataramanan } 4100334cb062SAnirudh Venkataramanan 4101334cb062SAnirudh Venkataramanan /** 410245d3d428SAnirudh Venkataramanan * ice_stat_update40 - read 40 bit stat from the chip and update stat values 410345d3d428SAnirudh Venkataramanan * @hw: ptr to the hardware info 410436517fd3SJacob Keller * @reg: offset of 64 bit HW register to read from 410545d3d428SAnirudh Venkataramanan * @prev_stat_loaded: bool to specify if previous stats are loaded 410645d3d428SAnirudh Venkataramanan * @prev_stat: ptr to previous loaded stat value 410745d3d428SAnirudh Venkataramanan * @cur_stat: ptr to current stat value 410845d3d428SAnirudh Venkataramanan */ 4109c8b7abddSBruce Allan void 411036517fd3SJacob Keller ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 411136517fd3SJacob Keller u64 *prev_stat, u64 *cur_stat) 411245d3d428SAnirudh Venkataramanan { 411336517fd3SJacob Keller u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 411445d3d428SAnirudh Venkataramanan 411545d3d428SAnirudh Venkataramanan /* device stats are not reset at PFR, they likely will not be zeroed 411636517fd3SJacob Keller * when the driver starts. Thus, save the value from the first read 411736517fd3SJacob Keller * without adding to the statistic value so that we report stats which 411836517fd3SJacob Keller * count up from zero. 411945d3d428SAnirudh Venkataramanan */ 412036517fd3SJacob Keller if (!prev_stat_loaded) { 412145d3d428SAnirudh Venkataramanan *prev_stat = new_data; 412236517fd3SJacob Keller return; 412336517fd3SJacob Keller } 412436517fd3SJacob Keller 412536517fd3SJacob Keller /* Calculate the difference between the new and old values, and then 412636517fd3SJacob Keller * add it to the software stat value. 412736517fd3SJacob Keller */ 412845d3d428SAnirudh Venkataramanan if (new_data >= *prev_stat) 412936517fd3SJacob Keller *cur_stat += new_data - *prev_stat; 413045d3d428SAnirudh Venkataramanan else 413145d3d428SAnirudh Venkataramanan /* to manage the potential roll-over */ 413236517fd3SJacob Keller *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 413336517fd3SJacob Keller 413436517fd3SJacob Keller /* Update the previously stored value to prepare for next read */ 413536517fd3SJacob Keller *prev_stat = new_data; 413645d3d428SAnirudh Venkataramanan } 413745d3d428SAnirudh Venkataramanan 413845d3d428SAnirudh Venkataramanan /** 413945d3d428SAnirudh Venkataramanan * ice_stat_update32 - read 32 bit stat from the chip and update stat values 414045d3d428SAnirudh Venkataramanan * @hw: ptr to the hardware info 414136517fd3SJacob Keller * @reg: offset of HW register to read from 414245d3d428SAnirudh Venkataramanan * @prev_stat_loaded: bool to specify if previous stats are loaded 414345d3d428SAnirudh Venkataramanan * @prev_stat: ptr to previous loaded stat value 414445d3d428SAnirudh Venkataramanan * @cur_stat: ptr to current stat value 414545d3d428SAnirudh Venkataramanan */ 4146c8b7abddSBruce Allan void 4147c8b7abddSBruce Allan ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 414845d3d428SAnirudh Venkataramanan u64 *prev_stat, u64 *cur_stat) 414945d3d428SAnirudh Venkataramanan { 415045d3d428SAnirudh Venkataramanan u32 new_data; 415145d3d428SAnirudh Venkataramanan 415245d3d428SAnirudh Venkataramanan new_data = rd32(hw, reg); 415345d3d428SAnirudh Venkataramanan 415445d3d428SAnirudh Venkataramanan /* device stats are not reset at PFR, they likely will not be zeroed 415536517fd3SJacob Keller * when the driver starts. Thus, save the value from the first read 415636517fd3SJacob Keller * without adding to the statistic value so that we report stats which 415736517fd3SJacob Keller * count up from zero. 415845d3d428SAnirudh Venkataramanan */ 415936517fd3SJacob Keller if (!prev_stat_loaded) { 416045d3d428SAnirudh Venkataramanan *prev_stat = new_data; 416136517fd3SJacob Keller return; 416236517fd3SJacob Keller } 416336517fd3SJacob Keller 416436517fd3SJacob Keller /* Calculate the difference between the new and old values, and then 416536517fd3SJacob Keller * add it to the software stat value. 416636517fd3SJacob Keller */ 416745d3d428SAnirudh Venkataramanan if (new_data >= *prev_stat) 416836517fd3SJacob Keller *cur_stat += new_data - *prev_stat; 416945d3d428SAnirudh Venkataramanan else 417045d3d428SAnirudh Venkataramanan /* to manage the potential roll-over */ 417136517fd3SJacob Keller *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 417236517fd3SJacob Keller 417336517fd3SJacob Keller /* Update the previously stored value to prepare for next read */ 417436517fd3SJacob Keller *prev_stat = new_data; 417545d3d428SAnirudh Venkataramanan } 41767b9ffc76SAnirudh Venkataramanan 41777b9ffc76SAnirudh Venkataramanan /** 41787b9ffc76SAnirudh Venkataramanan * ice_sched_query_elem - query element information from HW 41797b9ffc76SAnirudh Venkataramanan * @hw: pointer to the HW struct 41807b9ffc76SAnirudh Venkataramanan * @node_teid: node TEID to be queried 41817b9ffc76SAnirudh Venkataramanan * @buf: buffer to element information 41827b9ffc76SAnirudh Venkataramanan * 41837b9ffc76SAnirudh Venkataramanan * This function queries HW element information 41847b9ffc76SAnirudh Venkataramanan */ 41857b9ffc76SAnirudh Venkataramanan enum ice_status 41867b9ffc76SAnirudh Venkataramanan ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4187b3c38904SBruce Allan struct ice_aqc_txsched_elem_data *buf) 41887b9ffc76SAnirudh Venkataramanan { 41897b9ffc76SAnirudh Venkataramanan u16 buf_size, num_elem_ret = 0; 41907b9ffc76SAnirudh Venkataramanan enum ice_status status; 41917b9ffc76SAnirudh Venkataramanan 41927b9ffc76SAnirudh Venkataramanan buf_size = sizeof(*buf); 41937b9ffc76SAnirudh Venkataramanan memset(buf, 0, buf_size); 4194b3c38904SBruce Allan buf->node_teid = cpu_to_le32(node_teid); 41957b9ffc76SAnirudh Venkataramanan status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 41967b9ffc76SAnirudh Venkataramanan NULL); 41977b9ffc76SAnirudh Venkataramanan if (status || num_elem_ret != 1) 41987b9ffc76SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 41997b9ffc76SAnirudh Venkataramanan return status; 42007b9ffc76SAnirudh Venkataramanan } 4201ea78ce4dSPaul Greenwalt 4202ea78ce4dSPaul Greenwalt /** 4203ea78ce4dSPaul Greenwalt * ice_fw_supports_link_override 4204ea78ce4dSPaul Greenwalt * @hw: pointer to the hardware structure 4205ea78ce4dSPaul Greenwalt * 4206ea78ce4dSPaul Greenwalt * Checks if the firmware supports link override 4207ea78ce4dSPaul Greenwalt */ 4208ea78ce4dSPaul Greenwalt bool ice_fw_supports_link_override(struct ice_hw *hw) 4209ea78ce4dSPaul Greenwalt { 4210ea78ce4dSPaul Greenwalt /* Currently, only supported for E810 devices */ 4211ea78ce4dSPaul Greenwalt if (hw->mac_type != ICE_MAC_E810) 4212ea78ce4dSPaul Greenwalt return false; 4213ea78ce4dSPaul Greenwalt 4214ea78ce4dSPaul Greenwalt if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 4215ea78ce4dSPaul Greenwalt if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 4216ea78ce4dSPaul Greenwalt return true; 4217ea78ce4dSPaul Greenwalt if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 4218ea78ce4dSPaul Greenwalt hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 4219ea78ce4dSPaul Greenwalt return true; 4220ea78ce4dSPaul Greenwalt } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 4221ea78ce4dSPaul Greenwalt return true; 4222ea78ce4dSPaul Greenwalt } 4223ea78ce4dSPaul Greenwalt 4224ea78ce4dSPaul Greenwalt return false; 4225ea78ce4dSPaul Greenwalt } 4226ea78ce4dSPaul Greenwalt 4227ea78ce4dSPaul Greenwalt /** 4228ea78ce4dSPaul Greenwalt * ice_get_link_default_override 4229ea78ce4dSPaul Greenwalt * @ldo: pointer to the link default override struct 4230ea78ce4dSPaul Greenwalt * @pi: pointer to the port info struct 4231ea78ce4dSPaul Greenwalt * 4232ea78ce4dSPaul Greenwalt * Gets the link default override for a port 4233ea78ce4dSPaul Greenwalt */ 4234ea78ce4dSPaul Greenwalt enum ice_status 4235ea78ce4dSPaul Greenwalt ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 4236ea78ce4dSPaul Greenwalt struct ice_port_info *pi) 4237ea78ce4dSPaul Greenwalt { 4238ea78ce4dSPaul Greenwalt u16 i, tlv, tlv_len, tlv_start, buf, offset; 4239ea78ce4dSPaul Greenwalt struct ice_hw *hw = pi->hw; 4240ea78ce4dSPaul Greenwalt enum ice_status status; 4241ea78ce4dSPaul Greenwalt 4242ea78ce4dSPaul Greenwalt status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 4243ea78ce4dSPaul Greenwalt ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 4244ea78ce4dSPaul Greenwalt if (status) { 4245ea78ce4dSPaul Greenwalt ice_debug(hw, ICE_DBG_INIT, 4246ea78ce4dSPaul Greenwalt "Failed to read link override TLV.\n"); 4247ea78ce4dSPaul Greenwalt return status; 4248ea78ce4dSPaul Greenwalt } 4249ea78ce4dSPaul Greenwalt 4250ea78ce4dSPaul Greenwalt /* Each port has its own config; calculate for our port */ 4251ea78ce4dSPaul Greenwalt tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 4252ea78ce4dSPaul Greenwalt ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 4253ea78ce4dSPaul Greenwalt 4254ea78ce4dSPaul Greenwalt /* link options first */ 4255ea78ce4dSPaul Greenwalt status = ice_read_sr_word(hw, tlv_start, &buf); 4256ea78ce4dSPaul Greenwalt if (status) { 4257ea78ce4dSPaul Greenwalt ice_debug(hw, ICE_DBG_INIT, 4258ea78ce4dSPaul Greenwalt "Failed to read override link options.\n"); 4259ea78ce4dSPaul Greenwalt return status; 4260ea78ce4dSPaul Greenwalt } 4261ea78ce4dSPaul Greenwalt ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 4262ea78ce4dSPaul Greenwalt ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 4263ea78ce4dSPaul Greenwalt ICE_LINK_OVERRIDE_PHY_CFG_S; 4264ea78ce4dSPaul Greenwalt 4265ea78ce4dSPaul Greenwalt /* link PHY config */ 4266ea78ce4dSPaul Greenwalt offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 4267ea78ce4dSPaul Greenwalt status = ice_read_sr_word(hw, offset, &buf); 4268ea78ce4dSPaul Greenwalt if (status) { 4269ea78ce4dSPaul Greenwalt ice_debug(hw, ICE_DBG_INIT, 4270ea78ce4dSPaul Greenwalt "Failed to read override phy config.\n"); 4271ea78ce4dSPaul Greenwalt return status; 4272ea78ce4dSPaul Greenwalt } 4273ea78ce4dSPaul Greenwalt ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 4274ea78ce4dSPaul Greenwalt 4275ea78ce4dSPaul Greenwalt /* PHY types low */ 4276ea78ce4dSPaul Greenwalt offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 4277ea78ce4dSPaul Greenwalt for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4278ea78ce4dSPaul Greenwalt status = ice_read_sr_word(hw, (offset + i), &buf); 4279ea78ce4dSPaul Greenwalt if (status) { 4280ea78ce4dSPaul Greenwalt ice_debug(hw, ICE_DBG_INIT, 4281ea78ce4dSPaul Greenwalt "Failed to read override link options.\n"); 4282ea78ce4dSPaul Greenwalt return status; 4283ea78ce4dSPaul Greenwalt } 4284ea78ce4dSPaul Greenwalt /* shift 16 bits at a time to fill 64 bits */ 4285ea78ce4dSPaul Greenwalt ldo->phy_type_low |= ((u64)buf << (i * 16)); 4286ea78ce4dSPaul Greenwalt } 4287ea78ce4dSPaul Greenwalt 4288ea78ce4dSPaul Greenwalt /* PHY types high */ 4289ea78ce4dSPaul Greenwalt offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 4290ea78ce4dSPaul Greenwalt ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 4291ea78ce4dSPaul Greenwalt for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4292ea78ce4dSPaul Greenwalt status = ice_read_sr_word(hw, (offset + i), &buf); 4293ea78ce4dSPaul Greenwalt if (status) { 4294ea78ce4dSPaul Greenwalt ice_debug(hw, ICE_DBG_INIT, 4295ea78ce4dSPaul Greenwalt "Failed to read override link options.\n"); 4296ea78ce4dSPaul Greenwalt return status; 4297ea78ce4dSPaul Greenwalt } 4298ea78ce4dSPaul Greenwalt /* shift 16 bits at a time to fill 64 bits */ 4299ea78ce4dSPaul Greenwalt ldo->phy_type_high |= ((u64)buf << (i * 16)); 4300ea78ce4dSPaul Greenwalt } 4301ea78ce4dSPaul Greenwalt 4302ea78ce4dSPaul Greenwalt return status; 4303ea78ce4dSPaul Greenwalt } 43045ee30564SPaul Greenwalt 43055ee30564SPaul Greenwalt /** 43065ee30564SPaul Greenwalt * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 43075ee30564SPaul Greenwalt * @caps: get PHY capability data 43085ee30564SPaul Greenwalt */ 43095ee30564SPaul Greenwalt bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 43105ee30564SPaul Greenwalt { 43115ee30564SPaul Greenwalt if (caps->caps & ICE_AQC_PHY_AN_MODE || 4312bdeff971SLev Faerman caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 43135ee30564SPaul Greenwalt ICE_AQC_PHY_AN_EN_CLAUSE73 | 43145ee30564SPaul Greenwalt ICE_AQC_PHY_AN_EN_CLAUSE37)) 43155ee30564SPaul Greenwalt return true; 43165ee30564SPaul Greenwalt 43175ee30564SPaul Greenwalt return false; 43185ee30564SPaul Greenwalt } 4319