17ec59eeaSAnirudh Venkataramanan // SPDX-License-Identifier: GPL-2.0 27ec59eeaSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 37ec59eeaSAnirudh Venkataramanan 47ec59eeaSAnirudh Venkataramanan #include "ice_common.h" 59c20346bSAnirudh Venkataramanan #include "ice_sched.h" 67ec59eeaSAnirudh Venkataramanan #include "ice_adminq_cmd.h" 7c90ed40cSTony Nguyen #include "ice_flow.h" 87ec59eeaSAnirudh Venkataramanan 971245072SJacob Keller #define ICE_PF_RESET_WAIT_COUNT 300 10f31e4b6fSAnirudh Venkataramanan 11f31e4b6fSAnirudh Venkataramanan /** 12f31e4b6fSAnirudh Venkataramanan * ice_set_mac_type - Sets MAC type 13f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the HW structure 14f31e4b6fSAnirudh Venkataramanan * 15f31e4b6fSAnirudh Venkataramanan * This function sets the MAC type of the adapter based on the 16f9867df6SAnirudh Venkataramanan * vendor ID and device ID stored in the HW structure. 17f31e4b6fSAnirudh Venkataramanan */ 18f31e4b6fSAnirudh Venkataramanan static enum ice_status ice_set_mac_type(struct ice_hw *hw) 19f31e4b6fSAnirudh Venkataramanan { 20f31e4b6fSAnirudh Venkataramanan if (hw->vendor_id != PCI_VENDOR_ID_INTEL) 21f31e4b6fSAnirudh Venkataramanan return ICE_ERR_DEVICE_NOT_SUPPORTED; 22f31e4b6fSAnirudh Venkataramanan 23ea78ce4dSPaul Greenwalt switch (hw->device_id) { 24ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E810C_BACKPLANE: 25ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E810C_QSFP: 26ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E810C_SFP: 27ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E810_XXV_SFP: 28ea78ce4dSPaul Greenwalt hw->mac_type = ICE_MAC_E810; 29ea78ce4dSPaul Greenwalt break; 30ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_10G_BASE_T: 31ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_BACKPLANE: 32ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_QSFP: 33ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_SFP: 34ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823C_SGMII: 35ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_10G_BASE_T: 36ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_BACKPLANE: 37ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_QSFP: 38ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_SFP: 39ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822C_SGMII: 40ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822L_10G_BASE_T: 41ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822L_BACKPLANE: 42ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822L_SFP: 43ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E822L_SGMII: 44ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_10G_BASE_T: 45ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_1GBE: 46ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_BACKPLANE: 47ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_QSFP: 48ea78ce4dSPaul Greenwalt case ICE_DEV_ID_E823L_SFP: 49f31e4b6fSAnirudh Venkataramanan hw->mac_type = ICE_MAC_GENERIC; 50ea78ce4dSPaul Greenwalt break; 51ea78ce4dSPaul Greenwalt default: 52ea78ce4dSPaul Greenwalt hw->mac_type = ICE_MAC_UNKNOWN; 53ea78ce4dSPaul Greenwalt break; 54ea78ce4dSPaul Greenwalt } 55ea78ce4dSPaul Greenwalt 56ea78ce4dSPaul Greenwalt ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 57f31e4b6fSAnirudh Venkataramanan return 0; 58f31e4b6fSAnirudh Venkataramanan } 59f31e4b6fSAnirudh Venkataramanan 60f31e4b6fSAnirudh Venkataramanan /** 61f31e4b6fSAnirudh Venkataramanan * ice_clear_pf_cfg - Clear PF configuration 62f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure 633968540bSAnirudh Venkataramanan * 643968540bSAnirudh Venkataramanan * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 653968540bSAnirudh Venkataramanan * configuration, flow director filters, etc.). 66f31e4b6fSAnirudh Venkataramanan */ 67f31e4b6fSAnirudh Venkataramanan enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 68f31e4b6fSAnirudh Venkataramanan { 69f31e4b6fSAnirudh Venkataramanan struct ice_aq_desc desc; 70f31e4b6fSAnirudh Venkataramanan 71f31e4b6fSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 72f31e4b6fSAnirudh Venkataramanan 73f31e4b6fSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 74f31e4b6fSAnirudh Venkataramanan } 75f31e4b6fSAnirudh Venkataramanan 76f31e4b6fSAnirudh Venkataramanan /** 77dc49c772SAnirudh Venkataramanan * ice_aq_manage_mac_read - manage MAC address read command 78f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 79dc49c772SAnirudh Venkataramanan * @buf: a virtual buffer to hold the manage MAC read response 80dc49c772SAnirudh Venkataramanan * @buf_size: Size of the virtual buffer 81dc49c772SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 82dc49c772SAnirudh Venkataramanan * 83dc49c772SAnirudh Venkataramanan * This function is used to return per PF station MAC address (0x0107). 84dc49c772SAnirudh Venkataramanan * NOTE: Upon successful completion of this command, MAC address information 85dc49c772SAnirudh Venkataramanan * is returned in user specified buffer. Please interpret user specified 86dc49c772SAnirudh Venkataramanan * buffer as "manage_mac_read" response. 87dc49c772SAnirudh Venkataramanan * Response such as various MAC addresses are stored in HW struct (port.mac) 8881aed647SJacob Keller * ice_discover_dev_caps is expected to be called before this function is 8981aed647SJacob Keller * called. 90dc49c772SAnirudh Venkataramanan */ 91dc49c772SAnirudh Venkataramanan static enum ice_status 92dc49c772SAnirudh Venkataramanan ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 93dc49c772SAnirudh Venkataramanan struct ice_sq_cd *cd) 94dc49c772SAnirudh Venkataramanan { 95dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read_resp *resp; 96dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read *cmd; 97dc49c772SAnirudh Venkataramanan struct ice_aq_desc desc; 98dc49c772SAnirudh Venkataramanan enum ice_status status; 99dc49c772SAnirudh Venkataramanan u16 flags; 100d6fef10cSMd Fahad Iqbal Polash u8 i; 101dc49c772SAnirudh Venkataramanan 102dc49c772SAnirudh Venkataramanan cmd = &desc.params.mac_read; 103dc49c772SAnirudh Venkataramanan 104dc49c772SAnirudh Venkataramanan if (buf_size < sizeof(*resp)) 105dc49c772SAnirudh Venkataramanan return ICE_ERR_BUF_TOO_SHORT; 106dc49c772SAnirudh Venkataramanan 107dc49c772SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 108dc49c772SAnirudh Venkataramanan 109dc49c772SAnirudh Venkataramanan status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 110dc49c772SAnirudh Venkataramanan if (status) 111dc49c772SAnirudh Venkataramanan return status; 112dc49c772SAnirudh Venkataramanan 113dc49c772SAnirudh Venkataramanan resp = (struct ice_aqc_manage_mac_read_resp *)buf; 114dc49c772SAnirudh Venkataramanan flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 115dc49c772SAnirudh Venkataramanan 116dc49c772SAnirudh Venkataramanan if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 117dc49c772SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 118dc49c772SAnirudh Venkataramanan return ICE_ERR_CFG; 119dc49c772SAnirudh Venkataramanan } 120dc49c772SAnirudh Venkataramanan 121d6fef10cSMd Fahad Iqbal Polash /* A single port can report up to two (LAN and WoL) addresses */ 122d6fef10cSMd Fahad Iqbal Polash for (i = 0; i < cmd->num_addr; i++) 123d6fef10cSMd Fahad Iqbal Polash if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 124d6fef10cSMd Fahad Iqbal Polash ether_addr_copy(hw->port_info->mac.lan_addr, 125d6fef10cSMd Fahad Iqbal Polash resp[i].mac_addr); 126d6fef10cSMd Fahad Iqbal Polash ether_addr_copy(hw->port_info->mac.perm_addr, 127d6fef10cSMd Fahad Iqbal Polash resp[i].mac_addr); 128d6fef10cSMd Fahad Iqbal Polash break; 129d6fef10cSMd Fahad Iqbal Polash } 130d6fef10cSMd Fahad Iqbal Polash 131dc49c772SAnirudh Venkataramanan return 0; 132dc49c772SAnirudh Venkataramanan } 133dc49c772SAnirudh Venkataramanan 134dc49c772SAnirudh Venkataramanan /** 135dc49c772SAnirudh Venkataramanan * ice_aq_get_phy_caps - returns PHY capabilities 136dc49c772SAnirudh Venkataramanan * @pi: port information structure 137dc49c772SAnirudh Venkataramanan * @qual_mods: report qualified modules 138dc49c772SAnirudh Venkataramanan * @report_mode: report mode capabilities 139dc49c772SAnirudh Venkataramanan * @pcaps: structure for PHY capabilities to be filled 140dc49c772SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 141dc49c772SAnirudh Venkataramanan * 142dc49c772SAnirudh Venkataramanan * Returns the various PHY capabilities supported on the Port (0x0600) 143dc49c772SAnirudh Venkataramanan */ 14448cb27f2SChinh Cao enum ice_status 145dc49c772SAnirudh Venkataramanan ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 146dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps_data *pcaps, 147dc49c772SAnirudh Venkataramanan struct ice_sq_cd *cd) 148dc49c772SAnirudh Venkataramanan { 149dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps *cmd; 150dc49c772SAnirudh Venkataramanan u16 pcaps_size = sizeof(*pcaps); 151dc49c772SAnirudh Venkataramanan struct ice_aq_desc desc; 152dc49c772SAnirudh Venkataramanan enum ice_status status; 15355df52a0SPaul Greenwalt struct ice_hw *hw; 154dc49c772SAnirudh Venkataramanan 155dc49c772SAnirudh Venkataramanan cmd = &desc.params.get_phy; 156dc49c772SAnirudh Venkataramanan 157dc49c772SAnirudh Venkataramanan if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 158dc49c772SAnirudh Venkataramanan return ICE_ERR_PARAM; 15955df52a0SPaul Greenwalt hw = pi->hw; 160dc49c772SAnirudh Venkataramanan 161dc49c772SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 162dc49c772SAnirudh Venkataramanan 163dc49c772SAnirudh Venkataramanan if (qual_mods) 164dc49c772SAnirudh Venkataramanan cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); 165dc49c772SAnirudh Venkataramanan 166dc49c772SAnirudh Venkataramanan cmd->param0 |= cpu_to_le16(report_mode); 16755df52a0SPaul Greenwalt status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 16855df52a0SPaul Greenwalt 16955df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 17055df52a0SPaul Greenwalt report_mode); 17155df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 17255df52a0SPaul Greenwalt (unsigned long long)le64_to_cpu(pcaps->phy_type_low)); 17355df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 17455df52a0SPaul Greenwalt (unsigned long long)le64_to_cpu(pcaps->phy_type_high)); 17555df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 176bdeff971SLev Faerman ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 177bdeff971SLev Faerman pcaps->low_power_ctrl_an); 17855df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 17955df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 18055df52a0SPaul Greenwalt pcaps->eeer_value); 18155df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 18255df52a0SPaul Greenwalt pcaps->link_fec_options); 18355df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 18455df52a0SPaul Greenwalt pcaps->module_compliance_enforcement); 18555df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 18655df52a0SPaul Greenwalt pcaps->extended_compliance_code); 18755df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 18855df52a0SPaul Greenwalt pcaps->module_type[0]); 18955df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 19055df52a0SPaul Greenwalt pcaps->module_type[1]); 19155df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 19255df52a0SPaul Greenwalt pcaps->module_type[2]); 193dc49c772SAnirudh Venkataramanan 194aef74145SAnirudh Venkataramanan if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) { 195dc49c772SAnirudh Venkataramanan pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); 196aef74145SAnirudh Venkataramanan pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); 197c2b35226SPaul M Stillwell Jr memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 198c2b35226SPaul M Stillwell Jr sizeof(pi->phy.link_info.module_type)); 199aef74145SAnirudh Venkataramanan } 200dc49c772SAnirudh Venkataramanan 201dc49c772SAnirudh Venkataramanan return status; 202dc49c772SAnirudh Venkataramanan } 203dc49c772SAnirudh Venkataramanan 204dc49c772SAnirudh Venkataramanan /** 2058ea1da59SPaul Greenwalt * ice_aq_get_link_topo_handle - get link topology node return status 2068ea1da59SPaul Greenwalt * @pi: port information structure 2078ea1da59SPaul Greenwalt * @node_type: requested node type 2088ea1da59SPaul Greenwalt * @cd: pointer to command details structure or NULL 2098ea1da59SPaul Greenwalt * 2108ea1da59SPaul Greenwalt * Get link topology node return status for specified node type (0x06E0) 2118ea1da59SPaul Greenwalt * 2128ea1da59SPaul Greenwalt * Node type cage can be used to determine if cage is present. If AQC 2138ea1da59SPaul Greenwalt * returns error (ENOENT), then no cage present. If no cage present, then 2148ea1da59SPaul Greenwalt * connection type is backplane or BASE-T. 2158ea1da59SPaul Greenwalt */ 2168ea1da59SPaul Greenwalt static enum ice_status 2178ea1da59SPaul Greenwalt ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 2188ea1da59SPaul Greenwalt struct ice_sq_cd *cd) 2198ea1da59SPaul Greenwalt { 2208ea1da59SPaul Greenwalt struct ice_aqc_get_link_topo *cmd; 2218ea1da59SPaul Greenwalt struct ice_aq_desc desc; 2228ea1da59SPaul Greenwalt 2238ea1da59SPaul Greenwalt cmd = &desc.params.get_link_topo; 2248ea1da59SPaul Greenwalt 2258ea1da59SPaul Greenwalt ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 2268ea1da59SPaul Greenwalt 2278ea1da59SPaul Greenwalt cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 2288ea1da59SPaul Greenwalt ICE_AQC_LINK_TOPO_NODE_CTX_S); 2298ea1da59SPaul Greenwalt 2308ea1da59SPaul Greenwalt /* set node type */ 2318ea1da59SPaul Greenwalt cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 2328ea1da59SPaul Greenwalt 2338ea1da59SPaul Greenwalt return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 2348ea1da59SPaul Greenwalt } 2358ea1da59SPaul Greenwalt 2368ea1da59SPaul Greenwalt /** 2378ea1da59SPaul Greenwalt * ice_is_media_cage_present 2388ea1da59SPaul Greenwalt * @pi: port information structure 2398ea1da59SPaul Greenwalt * 2408ea1da59SPaul Greenwalt * Returns true if media cage is present, else false. If no cage, then 2418ea1da59SPaul Greenwalt * media type is backplane or BASE-T. 2428ea1da59SPaul Greenwalt */ 2438ea1da59SPaul Greenwalt static bool ice_is_media_cage_present(struct ice_port_info *pi) 2448ea1da59SPaul Greenwalt { 2458ea1da59SPaul Greenwalt /* Node type cage can be used to determine if cage is present. If AQC 2468ea1da59SPaul Greenwalt * returns error (ENOENT), then no cage present. If no cage present then 2478ea1da59SPaul Greenwalt * connection type is backplane or BASE-T. 2488ea1da59SPaul Greenwalt */ 2498ea1da59SPaul Greenwalt return !ice_aq_get_link_topo_handle(pi, 2508ea1da59SPaul Greenwalt ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 2518ea1da59SPaul Greenwalt NULL); 2528ea1da59SPaul Greenwalt } 2538ea1da59SPaul Greenwalt 2548ea1da59SPaul Greenwalt /** 255dc49c772SAnirudh Venkataramanan * ice_get_media_type - Gets media type 256dc49c772SAnirudh Venkataramanan * @pi: port information structure 257dc49c772SAnirudh Venkataramanan */ 258dc49c772SAnirudh Venkataramanan static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 259dc49c772SAnirudh Venkataramanan { 260dc49c772SAnirudh Venkataramanan struct ice_link_status *hw_link_info; 261dc49c772SAnirudh Venkataramanan 262dc49c772SAnirudh Venkataramanan if (!pi) 263dc49c772SAnirudh Venkataramanan return ICE_MEDIA_UNKNOWN; 264dc49c772SAnirudh Venkataramanan 265dc49c772SAnirudh Venkataramanan hw_link_info = &pi->phy.link_info; 266aef74145SAnirudh Venkataramanan if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 267aef74145SAnirudh Venkataramanan /* If more than one media type is selected, report unknown */ 268aef74145SAnirudh Venkataramanan return ICE_MEDIA_UNKNOWN; 269dc49c772SAnirudh Venkataramanan 270dc49c772SAnirudh Venkataramanan if (hw_link_info->phy_type_low) { 271c2b35226SPaul M Stillwell Jr /* 1G SGMII is a special case where some DA cable PHYs 272c2b35226SPaul M Stillwell Jr * may show this as an option when it really shouldn't 273c2b35226SPaul M Stillwell Jr * be since SGMII is meant to be between a MAC and a PHY 274c2b35226SPaul M Stillwell Jr * in a backplane. Try to detect this case and handle it 275c2b35226SPaul M Stillwell Jr */ 276c2b35226SPaul M Stillwell Jr if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 277c2b35226SPaul M Stillwell Jr (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 278c2b35226SPaul M Stillwell Jr ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 279c2b35226SPaul M Stillwell Jr hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 280c2b35226SPaul M Stillwell Jr ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 281c2b35226SPaul M Stillwell Jr return ICE_MEDIA_DA; 282c2b35226SPaul M Stillwell Jr 283dc49c772SAnirudh Venkataramanan switch (hw_link_info->phy_type_low) { 284dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_1000BASE_SX: 285dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_1000BASE_LX: 286dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10GBASE_SR: 287dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10GBASE_LR: 288dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 289dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_SR: 290dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_LR: 291dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_40GBASE_SR4: 292dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_40GBASE_LR4: 293aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_SR2: 294aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_LR2: 295aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_SR: 296aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_FR: 297aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_LR: 298aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_SR4: 299aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_LR4: 300aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_SR2: 301aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_DR: 302c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 303c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 304c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 305c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 306c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 307c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 308c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 309c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 310dc49c772SAnirudh Venkataramanan return ICE_MEDIA_FIBER; 311dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100BASE_TX: 312dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_1000BASE_T: 313dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_2500BASE_T: 314dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_5GBASE_T: 315dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10GBASE_T: 316dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_T: 317dc49c772SAnirudh Venkataramanan return ICE_MEDIA_BASET; 318dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10G_SFI_DA: 319dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_CR: 320dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 321dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_CR1: 322dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_40GBASE_CR4: 323aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_CR2: 324aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_CP: 325aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CR4: 326aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 327aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CP2: 328dc49c772SAnirudh Venkataramanan return ICE_MEDIA_DA; 3298ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 3308ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_40G_XLAUI: 3318ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_50G_LAUI2: 3328ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_50G_AUI2: 3338ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_50G_AUI1: 3348ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_100G_AUI4: 3358ea1da59SPaul Greenwalt case ICE_PHY_TYPE_LOW_100G_CAUI4: 3368ea1da59SPaul Greenwalt if (ice_is_media_cage_present(pi)) 3378ea1da59SPaul Greenwalt return ICE_MEDIA_DA; 3388ea1da59SPaul Greenwalt fallthrough; 339dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_1000BASE_KX: 340dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_2500BASE_KX: 341dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_2500BASE_X: 342dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_5GBASE_KR: 343dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 344dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_KR: 345dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_KR1: 346dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 347dc49c772SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_40GBASE_KR4: 348aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 349aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_KR2: 350aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_KR4: 351aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 352aef74145SAnirudh Venkataramanan return ICE_MEDIA_BACKPLANE; 353aef74145SAnirudh Venkataramanan } 354aef74145SAnirudh Venkataramanan } else { 355aef74145SAnirudh Venkataramanan switch (hw_link_info->phy_type_high) { 3568ea1da59SPaul Greenwalt case ICE_PHY_TYPE_HIGH_100G_AUI2: 3578ea1da59SPaul Greenwalt case ICE_PHY_TYPE_HIGH_100G_CAUI2: 3588ea1da59SPaul Greenwalt if (ice_is_media_cage_present(pi)) 3598ea1da59SPaul Greenwalt return ICE_MEDIA_DA; 3608ea1da59SPaul Greenwalt fallthrough; 361aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 362dc49c772SAnirudh Venkataramanan return ICE_MEDIA_BACKPLANE; 363c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 364c1eb3b6bSDoug Dziggel case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 365c1eb3b6bSDoug Dziggel return ICE_MEDIA_FIBER; 366dc49c772SAnirudh Venkataramanan } 367dc49c772SAnirudh Venkataramanan } 368dc49c772SAnirudh Venkataramanan return ICE_MEDIA_UNKNOWN; 369dc49c772SAnirudh Venkataramanan } 370dc49c772SAnirudh Venkataramanan 371dc49c772SAnirudh Venkataramanan /** 372dc49c772SAnirudh Venkataramanan * ice_aq_get_link_info 373dc49c772SAnirudh Venkataramanan * @pi: port information structure 374dc49c772SAnirudh Venkataramanan * @ena_lse: enable/disable LinkStatusEvent reporting 375dc49c772SAnirudh Venkataramanan * @link: pointer to link status structure - optional 376dc49c772SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 377dc49c772SAnirudh Venkataramanan * 378dc49c772SAnirudh Venkataramanan * Get Link Status (0x607). Returns the link status of the adapter. 379dc49c772SAnirudh Venkataramanan */ 380250c3b3eSBrett Creeley enum ice_status 381dc49c772SAnirudh Venkataramanan ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 382dc49c772SAnirudh Venkataramanan struct ice_link_status *link, struct ice_sq_cd *cd) 383dc49c772SAnirudh Venkataramanan { 384dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status_data link_data = { 0 }; 385dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status *resp; 386dc67039bSJesse Brandeburg struct ice_link_status *li_old, *li; 387dc49c772SAnirudh Venkataramanan enum ice_media_type *hw_media_type; 388dc49c772SAnirudh Venkataramanan struct ice_fc_info *hw_fc_info; 389dc49c772SAnirudh Venkataramanan bool tx_pause, rx_pause; 390dc49c772SAnirudh Venkataramanan struct ice_aq_desc desc; 391dc49c772SAnirudh Venkataramanan enum ice_status status; 392dc67039bSJesse Brandeburg struct ice_hw *hw; 393dc49c772SAnirudh Venkataramanan u16 cmd_flags; 394dc49c772SAnirudh Venkataramanan 395dc49c772SAnirudh Venkataramanan if (!pi) 396dc49c772SAnirudh Venkataramanan return ICE_ERR_PARAM; 397dc67039bSJesse Brandeburg hw = pi->hw; 398dc67039bSJesse Brandeburg li_old = &pi->phy.link_info_old; 399dc49c772SAnirudh Venkataramanan hw_media_type = &pi->phy.media_type; 400dc67039bSJesse Brandeburg li = &pi->phy.link_info; 401dc49c772SAnirudh Venkataramanan hw_fc_info = &pi->fc; 402dc49c772SAnirudh Venkataramanan 403dc49c772SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 404dc49c772SAnirudh Venkataramanan cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 405dc49c772SAnirudh Venkataramanan resp = &desc.params.get_link_status; 406dc49c772SAnirudh Venkataramanan resp->cmd_flags = cpu_to_le16(cmd_flags); 407dc49c772SAnirudh Venkataramanan resp->lport_num = pi->lport; 408dc49c772SAnirudh Venkataramanan 409dc67039bSJesse Brandeburg status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 410dc49c772SAnirudh Venkataramanan 411dc49c772SAnirudh Venkataramanan if (status) 412dc49c772SAnirudh Venkataramanan return status; 413dc49c772SAnirudh Venkataramanan 414dc49c772SAnirudh Venkataramanan /* save off old link status information */ 415dc67039bSJesse Brandeburg *li_old = *li; 416dc49c772SAnirudh Venkataramanan 417dc49c772SAnirudh Venkataramanan /* update current link status information */ 418dc67039bSJesse Brandeburg li->link_speed = le16_to_cpu(link_data.link_speed); 419dc67039bSJesse Brandeburg li->phy_type_low = le64_to_cpu(link_data.phy_type_low); 420dc67039bSJesse Brandeburg li->phy_type_high = le64_to_cpu(link_data.phy_type_high); 421dc49c772SAnirudh Venkataramanan *hw_media_type = ice_get_media_type(pi); 422dc67039bSJesse Brandeburg li->link_info = link_data.link_info; 423dc67039bSJesse Brandeburg li->an_info = link_data.an_info; 424dc67039bSJesse Brandeburg li->ext_info = link_data.ext_info; 425dc67039bSJesse Brandeburg li->max_frame_size = le16_to_cpu(link_data.max_frame_size); 426dc67039bSJesse Brandeburg li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 427dc67039bSJesse Brandeburg li->topo_media_conflict = link_data.topo_media_conflict; 428dc67039bSJesse Brandeburg li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 429dc67039bSJesse Brandeburg ICE_AQ_CFG_PACING_TYPE_M); 430dc49c772SAnirudh Venkataramanan 431dc49c772SAnirudh Venkataramanan /* update fc info */ 432dc49c772SAnirudh Venkataramanan tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 433dc49c772SAnirudh Venkataramanan rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 434dc49c772SAnirudh Venkataramanan if (tx_pause && rx_pause) 435dc49c772SAnirudh Venkataramanan hw_fc_info->current_mode = ICE_FC_FULL; 436dc49c772SAnirudh Venkataramanan else if (tx_pause) 437dc49c772SAnirudh Venkataramanan hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 438dc49c772SAnirudh Venkataramanan else if (rx_pause) 439dc49c772SAnirudh Venkataramanan hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 440dc49c772SAnirudh Venkataramanan else 441dc49c772SAnirudh Venkataramanan hw_fc_info->current_mode = ICE_FC_NONE; 442dc49c772SAnirudh Venkataramanan 443dc67039bSJesse Brandeburg li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); 444dc67039bSJesse Brandeburg 44555df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 446dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 447dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 448dc67039bSJesse Brandeburg (unsigned long long)li->phy_type_low); 449dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 450dc67039bSJesse Brandeburg (unsigned long long)li->phy_type_high); 451dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 452dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 453dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 454dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 45555df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 456dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 45755df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 45855df52a0SPaul Greenwalt li->max_frame_size); 459dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 460dc49c772SAnirudh Venkataramanan 461dc49c772SAnirudh Venkataramanan /* save link status information */ 462dc49c772SAnirudh Venkataramanan if (link) 463dc67039bSJesse Brandeburg *link = *li; 464dc49c772SAnirudh Venkataramanan 465dc49c772SAnirudh Venkataramanan /* flag cleared so calling functions don't call AQ again */ 466dc49c772SAnirudh Venkataramanan pi->phy.get_link_info = false; 467dc49c772SAnirudh Venkataramanan 4681b5c19c7SBruce Allan return 0; 469dc49c772SAnirudh Venkataramanan } 470dc49c772SAnirudh Venkataramanan 471dc49c772SAnirudh Venkataramanan /** 47242449105SAnirudh Venkataramanan * ice_fill_tx_timer_and_fc_thresh 47342449105SAnirudh Venkataramanan * @hw: pointer to the HW struct 47442449105SAnirudh Venkataramanan * @cmd: pointer to MAC cfg structure 47542449105SAnirudh Venkataramanan * 47642449105SAnirudh Venkataramanan * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 47742449105SAnirudh Venkataramanan * descriptor 47842449105SAnirudh Venkataramanan */ 47942449105SAnirudh Venkataramanan static void 48042449105SAnirudh Venkataramanan ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 48142449105SAnirudh Venkataramanan struct ice_aqc_set_mac_cfg *cmd) 48242449105SAnirudh Venkataramanan { 48342449105SAnirudh Venkataramanan u16 fc_thres_val, tx_timer_val; 48442449105SAnirudh Venkataramanan u32 val; 48542449105SAnirudh Venkataramanan 48642449105SAnirudh Venkataramanan /* We read back the transmit timer and FC threshold value of 48742449105SAnirudh Venkataramanan * LFC. Thus, we will use index = 48842449105SAnirudh Venkataramanan * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 48942449105SAnirudh Venkataramanan * 49042449105SAnirudh Venkataramanan * Also, because we are operating on transmit timer and FC 49142449105SAnirudh Venkataramanan * threshold of LFC, we don't turn on any bit in tx_tmr_priority 49242449105SAnirudh Venkataramanan */ 49342449105SAnirudh Venkataramanan #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 49442449105SAnirudh Venkataramanan 49542449105SAnirudh Venkataramanan /* Retrieve the transmit timer */ 49642449105SAnirudh Venkataramanan val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 49742449105SAnirudh Venkataramanan tx_timer_val = val & 49842449105SAnirudh Venkataramanan PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 49942449105SAnirudh Venkataramanan cmd->tx_tmr_value = cpu_to_le16(tx_timer_val); 50042449105SAnirudh Venkataramanan 50142449105SAnirudh Venkataramanan /* Retrieve the FC threshold */ 50242449105SAnirudh Venkataramanan val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 50342449105SAnirudh Venkataramanan fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 50442449105SAnirudh Venkataramanan 50542449105SAnirudh Venkataramanan cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val); 50642449105SAnirudh Venkataramanan } 50742449105SAnirudh Venkataramanan 50842449105SAnirudh Venkataramanan /** 50942449105SAnirudh Venkataramanan * ice_aq_set_mac_cfg 51042449105SAnirudh Venkataramanan * @hw: pointer to the HW struct 51142449105SAnirudh Venkataramanan * @max_frame_size: Maximum Frame Size to be supported 51242449105SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 51342449105SAnirudh Venkataramanan * 51442449105SAnirudh Venkataramanan * Set MAC configuration (0x0603) 51542449105SAnirudh Venkataramanan */ 51642449105SAnirudh Venkataramanan enum ice_status 51742449105SAnirudh Venkataramanan ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 51842449105SAnirudh Venkataramanan { 51942449105SAnirudh Venkataramanan struct ice_aqc_set_mac_cfg *cmd; 52042449105SAnirudh Venkataramanan struct ice_aq_desc desc; 52142449105SAnirudh Venkataramanan 52242449105SAnirudh Venkataramanan cmd = &desc.params.set_mac_cfg; 52342449105SAnirudh Venkataramanan 52442449105SAnirudh Venkataramanan if (max_frame_size == 0) 52542449105SAnirudh Venkataramanan return ICE_ERR_PARAM; 52642449105SAnirudh Venkataramanan 52742449105SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 52842449105SAnirudh Venkataramanan 52942449105SAnirudh Venkataramanan cmd->max_frame_size = cpu_to_le16(max_frame_size); 53042449105SAnirudh Venkataramanan 53142449105SAnirudh Venkataramanan ice_fill_tx_timer_and_fc_thresh(hw, cmd); 53242449105SAnirudh Venkataramanan 53342449105SAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 53442449105SAnirudh Venkataramanan } 53542449105SAnirudh Venkataramanan 53642449105SAnirudh Venkataramanan /** 5379daf8208SAnirudh Venkataramanan * ice_init_fltr_mgmt_struct - initializes filter management list and locks 538f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 5399daf8208SAnirudh Venkataramanan */ 5409daf8208SAnirudh Venkataramanan static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 5419daf8208SAnirudh Venkataramanan { 5429daf8208SAnirudh Venkataramanan struct ice_switch_info *sw; 5431aaef2bcSSurabhi Boob enum ice_status status; 5449daf8208SAnirudh Venkataramanan 5459daf8208SAnirudh Venkataramanan hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), 5469daf8208SAnirudh Venkataramanan sizeof(*hw->switch_info), GFP_KERNEL); 5479daf8208SAnirudh Venkataramanan sw = hw->switch_info; 5489daf8208SAnirudh Venkataramanan 5499daf8208SAnirudh Venkataramanan if (!sw) 5509daf8208SAnirudh Venkataramanan return ICE_ERR_NO_MEMORY; 5519daf8208SAnirudh Venkataramanan 5529daf8208SAnirudh Venkataramanan INIT_LIST_HEAD(&sw->vsi_list_map_head); 5539daf8208SAnirudh Venkataramanan 5541aaef2bcSSurabhi Boob status = ice_init_def_sw_recp(hw); 5551aaef2bcSSurabhi Boob if (status) { 5561aaef2bcSSurabhi Boob devm_kfree(ice_hw_to_dev(hw), hw->switch_info); 5571aaef2bcSSurabhi Boob return status; 5581aaef2bcSSurabhi Boob } 5591aaef2bcSSurabhi Boob return 0; 5609daf8208SAnirudh Venkataramanan } 5619daf8208SAnirudh Venkataramanan 5629daf8208SAnirudh Venkataramanan /** 5639daf8208SAnirudh Venkataramanan * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks 564f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 5659daf8208SAnirudh Venkataramanan */ 5669daf8208SAnirudh Venkataramanan static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 5679daf8208SAnirudh Venkataramanan { 5689daf8208SAnirudh Venkataramanan struct ice_switch_info *sw = hw->switch_info; 5699daf8208SAnirudh Venkataramanan struct ice_vsi_list_map_info *v_pos_map; 5709daf8208SAnirudh Venkataramanan struct ice_vsi_list_map_info *v_tmp_map; 57180d144c9SAnirudh Venkataramanan struct ice_sw_recipe *recps; 57280d144c9SAnirudh Venkataramanan u8 i; 5739daf8208SAnirudh Venkataramanan 5749daf8208SAnirudh Venkataramanan list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 5759daf8208SAnirudh Venkataramanan list_entry) { 5769daf8208SAnirudh Venkataramanan list_del(&v_pos_map->list_entry); 5779daf8208SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), v_pos_map); 5789daf8208SAnirudh Venkataramanan } 57980d144c9SAnirudh Venkataramanan recps = hw->switch_info->recp_list; 58080d144c9SAnirudh Venkataramanan for (i = 0; i < ICE_SW_LKUP_LAST; i++) { 58180d144c9SAnirudh Venkataramanan struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 5829daf8208SAnirudh Venkataramanan 58380d144c9SAnirudh Venkataramanan recps[i].root_rid = i; 58480d144c9SAnirudh Venkataramanan mutex_destroy(&recps[i].filt_rule_lock); 58580d144c9SAnirudh Venkataramanan list_for_each_entry_safe(lst_itr, tmp_entry, 58680d144c9SAnirudh Venkataramanan &recps[i].filt_rules, list_entry) { 58780d144c9SAnirudh Venkataramanan list_del(&lst_itr->list_entry); 58880d144c9SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), lst_itr); 58980d144c9SAnirudh Venkataramanan } 59080d144c9SAnirudh Venkataramanan } 591334cb062SAnirudh Venkataramanan ice_rm_all_sw_replay_rule_info(hw); 59280d144c9SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), sw->recp_list); 5939daf8208SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), sw); 5949daf8208SAnirudh Venkataramanan } 5959daf8208SAnirudh Venkataramanan 5968b97ceb1SHieu Tran /** 59711fe1b3aSDan Nowlin * ice_get_fw_log_cfg - get FW logging configuration 59811fe1b3aSDan Nowlin * @hw: pointer to the HW struct 59911fe1b3aSDan Nowlin */ 60011fe1b3aSDan Nowlin static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw) 60111fe1b3aSDan Nowlin { 60211fe1b3aSDan Nowlin struct ice_aq_desc desc; 60311fe1b3aSDan Nowlin enum ice_status status; 604b3c38904SBruce Allan __le16 *config; 60511fe1b3aSDan Nowlin u16 size; 60611fe1b3aSDan Nowlin 607b3c38904SBruce Allan size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX; 60811fe1b3aSDan Nowlin config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL); 60911fe1b3aSDan Nowlin if (!config) 61011fe1b3aSDan Nowlin return ICE_ERR_NO_MEMORY; 61111fe1b3aSDan Nowlin 61211fe1b3aSDan Nowlin ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info); 61311fe1b3aSDan Nowlin 61411fe1b3aSDan Nowlin status = ice_aq_send_cmd(hw, &desc, config, size, NULL); 61511fe1b3aSDan Nowlin if (!status) { 61611fe1b3aSDan Nowlin u16 i; 61711fe1b3aSDan Nowlin 6182f2da36eSAnirudh Venkataramanan /* Save FW logging information into the HW structure */ 61911fe1b3aSDan Nowlin for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 62011fe1b3aSDan Nowlin u16 v, m, flgs; 62111fe1b3aSDan Nowlin 622b3c38904SBruce Allan v = le16_to_cpu(config[i]); 62311fe1b3aSDan Nowlin m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 62411fe1b3aSDan Nowlin flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S; 62511fe1b3aSDan Nowlin 62611fe1b3aSDan Nowlin if (m < ICE_AQC_FW_LOG_ID_MAX) 62711fe1b3aSDan Nowlin hw->fw_log.evnts[m].cur = flgs; 62811fe1b3aSDan Nowlin } 62911fe1b3aSDan Nowlin } 63011fe1b3aSDan Nowlin 63111fe1b3aSDan Nowlin devm_kfree(ice_hw_to_dev(hw), config); 63211fe1b3aSDan Nowlin 63311fe1b3aSDan Nowlin return status; 63411fe1b3aSDan Nowlin } 63511fe1b3aSDan Nowlin 63611fe1b3aSDan Nowlin /** 6378b97ceb1SHieu Tran * ice_cfg_fw_log - configure FW logging 638f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 6398b97ceb1SHieu Tran * @enable: enable certain FW logging events if true, disable all if false 6408b97ceb1SHieu Tran * 6418b97ceb1SHieu Tran * This function enables/disables the FW logging via Rx CQ events and a UART 6428b97ceb1SHieu Tran * port based on predetermined configurations. FW logging via the Rx CQ can be 6438b97ceb1SHieu Tran * enabled/disabled for individual PF's. However, FW logging via the UART can 6448b97ceb1SHieu Tran * only be enabled/disabled for all PFs on the same device. 6458b97ceb1SHieu Tran * 6468b97ceb1SHieu Tran * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in 6478b97ceb1SHieu Tran * hw->fw_log need to be set accordingly, e.g. based on user-provided input, 6488b97ceb1SHieu Tran * before initializing the device. 6498b97ceb1SHieu Tran * 6508b97ceb1SHieu Tran * When re/configuring FW logging, callers need to update the "cfg" elements of 6518b97ceb1SHieu Tran * the hw->fw_log.evnts array with the desired logging event configurations for 6528b97ceb1SHieu Tran * modules of interest. When disabling FW logging completely, the callers can 6538b97ceb1SHieu Tran * just pass false in the "enable" parameter. On completion, the function will 6548b97ceb1SHieu Tran * update the "cur" element of the hw->fw_log.evnts array with the resulting 6558b97ceb1SHieu Tran * logging event configurations of the modules that are being re/configured. FW 6568b97ceb1SHieu Tran * logging modules that are not part of a reconfiguration operation retain their 6578b97ceb1SHieu Tran * previous states. 6588b97ceb1SHieu Tran * 6598b97ceb1SHieu Tran * Before resetting the device, it is recommended that the driver disables FW 6608b97ceb1SHieu Tran * logging before shutting down the control queue. When disabling FW logging 6618b97ceb1SHieu Tran * ("enable" = false), the latest configurations of FW logging events stored in 6628b97ceb1SHieu Tran * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after 6638b97ceb1SHieu Tran * a device reset. 6648b97ceb1SHieu Tran * 6658b97ceb1SHieu Tran * When enabling FW logging to emit log messages via the Rx CQ during the 6668b97ceb1SHieu Tran * device's initialization phase, a mechanism alternative to interrupt handlers 6678b97ceb1SHieu Tran * needs to be used to extract FW log messages from the Rx CQ periodically and 6688b97ceb1SHieu Tran * to prevent the Rx CQ from being full and stalling other types of control 6698b97ceb1SHieu Tran * messages from FW to SW. Interrupts are typically disabled during the device's 6708b97ceb1SHieu Tran * initialization phase. 6718b97ceb1SHieu Tran */ 6728b97ceb1SHieu Tran static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable) 6738b97ceb1SHieu Tran { 6748b97ceb1SHieu Tran struct ice_aqc_fw_logging *cmd; 6758b97ceb1SHieu Tran enum ice_status status = 0; 6768b97ceb1SHieu Tran u16 i, chgs = 0, len = 0; 6778b97ceb1SHieu Tran struct ice_aq_desc desc; 678b3c38904SBruce Allan __le16 *data = NULL; 6798b97ceb1SHieu Tran u8 actv_evnts = 0; 6808b97ceb1SHieu Tran void *buf = NULL; 6818b97ceb1SHieu Tran 6828b97ceb1SHieu Tran if (!hw->fw_log.cq_en && !hw->fw_log.uart_en) 6838b97ceb1SHieu Tran return 0; 6848b97ceb1SHieu Tran 6858b97ceb1SHieu Tran /* Disable FW logging only when the control queue is still responsive */ 6868b97ceb1SHieu Tran if (!enable && 6878b97ceb1SHieu Tran (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq))) 6888b97ceb1SHieu Tran return 0; 6898b97ceb1SHieu Tran 69011fe1b3aSDan Nowlin /* Get current FW log settings */ 69111fe1b3aSDan Nowlin status = ice_get_fw_log_cfg(hw); 69211fe1b3aSDan Nowlin if (status) 69311fe1b3aSDan Nowlin return status; 69411fe1b3aSDan Nowlin 6958b97ceb1SHieu Tran ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging); 6968b97ceb1SHieu Tran cmd = &desc.params.fw_logging; 6978b97ceb1SHieu Tran 6988b97ceb1SHieu Tran /* Indicate which controls are valid */ 6998b97ceb1SHieu Tran if (hw->fw_log.cq_en) 7008b97ceb1SHieu Tran cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID; 7018b97ceb1SHieu Tran 7028b97ceb1SHieu Tran if (hw->fw_log.uart_en) 7038b97ceb1SHieu Tran cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID; 7048b97ceb1SHieu Tran 7058b97ceb1SHieu Tran if (enable) { 7068b97ceb1SHieu Tran /* Fill in an array of entries with FW logging modules and 7078b97ceb1SHieu Tran * logging events being reconfigured. 7088b97ceb1SHieu Tran */ 7098b97ceb1SHieu Tran for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) { 7108b97ceb1SHieu Tran u16 val; 7118b97ceb1SHieu Tran 7128b97ceb1SHieu Tran /* Keep track of enabled event types */ 7138b97ceb1SHieu Tran actv_evnts |= hw->fw_log.evnts[i].cfg; 7148b97ceb1SHieu Tran 7158b97ceb1SHieu Tran if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur) 7168b97ceb1SHieu Tran continue; 7178b97ceb1SHieu Tran 7188b97ceb1SHieu Tran if (!data) { 719b3c38904SBruce Allan data = devm_kcalloc(ice_hw_to_dev(hw), 720b3c38904SBruce Allan sizeof(*data), 721b3c38904SBruce Allan ICE_AQC_FW_LOG_ID_MAX, 7228b97ceb1SHieu Tran GFP_KERNEL); 7238b97ceb1SHieu Tran if (!data) 7248b97ceb1SHieu Tran return ICE_ERR_NO_MEMORY; 7258b97ceb1SHieu Tran } 7268b97ceb1SHieu Tran 7278b97ceb1SHieu Tran val = i << ICE_AQC_FW_LOG_ID_S; 7288b97ceb1SHieu Tran val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S; 729b3c38904SBruce Allan data[chgs++] = cpu_to_le16(val); 7308b97ceb1SHieu Tran } 7318b97ceb1SHieu Tran 7328b97ceb1SHieu Tran /* Only enable FW logging if at least one module is specified. 7338b97ceb1SHieu Tran * If FW logging is currently enabled but all modules are not 7348b97ceb1SHieu Tran * enabled to emit log messages, disable FW logging altogether. 7358b97ceb1SHieu Tran */ 7368b97ceb1SHieu Tran if (actv_evnts) { 7378b97ceb1SHieu Tran /* Leave if there is effectively no change */ 7388b97ceb1SHieu Tran if (!chgs) 7398b97ceb1SHieu Tran goto out; 7408b97ceb1SHieu Tran 7418b97ceb1SHieu Tran if (hw->fw_log.cq_en) 7428b97ceb1SHieu Tran cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN; 7438b97ceb1SHieu Tran 7448b97ceb1SHieu Tran if (hw->fw_log.uart_en) 7458b97ceb1SHieu Tran cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN; 7468b97ceb1SHieu Tran 7478b97ceb1SHieu Tran buf = data; 748b3c38904SBruce Allan len = sizeof(*data) * chgs; 7498b97ceb1SHieu Tran desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 7508b97ceb1SHieu Tran } 7518b97ceb1SHieu Tran } 7528b97ceb1SHieu Tran 7538b97ceb1SHieu Tran status = ice_aq_send_cmd(hw, &desc, buf, len, NULL); 7548b97ceb1SHieu Tran if (!status) { 7558b97ceb1SHieu Tran /* Update the current configuration to reflect events enabled. 7568b97ceb1SHieu Tran * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW 7578b97ceb1SHieu Tran * logging mode is enabled for the device. They do not reflect 7588b97ceb1SHieu Tran * actual modules being enabled to emit log messages. So, their 7598b97ceb1SHieu Tran * values remain unchanged even when all modules are disabled. 7608b97ceb1SHieu Tran */ 7618b97ceb1SHieu Tran u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX; 7628b97ceb1SHieu Tran 7638b97ceb1SHieu Tran hw->fw_log.actv_evnts = actv_evnts; 7648b97ceb1SHieu Tran for (i = 0; i < cnt; i++) { 7658b97ceb1SHieu Tran u16 v, m; 7668b97ceb1SHieu Tran 7678b97ceb1SHieu Tran if (!enable) { 7688b97ceb1SHieu Tran /* When disabling all FW logging events as part 7698b97ceb1SHieu Tran * of device's de-initialization, the original 7708b97ceb1SHieu Tran * configurations are retained, and can be used 7718b97ceb1SHieu Tran * to reconfigure FW logging later if the device 7728b97ceb1SHieu Tran * is re-initialized. 7738b97ceb1SHieu Tran */ 7748b97ceb1SHieu Tran hw->fw_log.evnts[i].cur = 0; 7758b97ceb1SHieu Tran continue; 7768b97ceb1SHieu Tran } 7778b97ceb1SHieu Tran 778b3c38904SBruce Allan v = le16_to_cpu(data[i]); 7798b97ceb1SHieu Tran m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S; 7808b97ceb1SHieu Tran hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg; 7818b97ceb1SHieu Tran } 7828b97ceb1SHieu Tran } 7838b97ceb1SHieu Tran 7848b97ceb1SHieu Tran out: 7858b97ceb1SHieu Tran if (data) 7868b97ceb1SHieu Tran devm_kfree(ice_hw_to_dev(hw), data); 7878b97ceb1SHieu Tran 7888b97ceb1SHieu Tran return status; 7898b97ceb1SHieu Tran } 7908b97ceb1SHieu Tran 7918b97ceb1SHieu Tran /** 7928b97ceb1SHieu Tran * ice_output_fw_log 793f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 7948b97ceb1SHieu Tran * @desc: pointer to the AQ message descriptor 7958b97ceb1SHieu Tran * @buf: pointer to the buffer accompanying the AQ message 7968b97ceb1SHieu Tran * 7978b97ceb1SHieu Tran * Formats a FW Log message and outputs it via the standard driver logs. 7988b97ceb1SHieu Tran */ 7998b97ceb1SHieu Tran void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf) 8008b97ceb1SHieu Tran { 8014f70daa0SJacob Keller ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n"); 8024f70daa0SJacob Keller ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf, 8038b97ceb1SHieu Tran le16_to_cpu(desc->datalen)); 8044f70daa0SJacob Keller ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n"); 8058b97ceb1SHieu Tran } 8068b97ceb1SHieu Tran 8079daf8208SAnirudh Venkataramanan /** 8084ee656bbSTony Nguyen * ice_get_itr_intrl_gran 809f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 8109e4ab4c2SBrett Creeley * 8114ee656bbSTony Nguyen * Determines the ITR/INTRL granularities based on the maximum aggregate 8129e4ab4c2SBrett Creeley * bandwidth according to the device's configuration during power-on. 8139e4ab4c2SBrett Creeley */ 814fe7219faSBruce Allan static void ice_get_itr_intrl_gran(struct ice_hw *hw) 8159e4ab4c2SBrett Creeley { 8169e4ab4c2SBrett Creeley u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 8179e4ab4c2SBrett Creeley GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 8189e4ab4c2SBrett Creeley GL_PWR_MODE_CTL_CAR_MAX_BW_S; 8199e4ab4c2SBrett Creeley 8209e4ab4c2SBrett Creeley switch (max_agg_bw) { 8219e4ab4c2SBrett Creeley case ICE_MAX_AGG_BW_200G: 8229e4ab4c2SBrett Creeley case ICE_MAX_AGG_BW_100G: 8239e4ab4c2SBrett Creeley case ICE_MAX_AGG_BW_50G: 8249e4ab4c2SBrett Creeley hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 8259e4ab4c2SBrett Creeley hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 8269e4ab4c2SBrett Creeley break; 8279e4ab4c2SBrett Creeley case ICE_MAX_AGG_BW_25G: 8289e4ab4c2SBrett Creeley hw->itr_gran = ICE_ITR_GRAN_MAX_25; 8299e4ab4c2SBrett Creeley hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 8309e4ab4c2SBrett Creeley break; 8319e4ab4c2SBrett Creeley } 8329e4ab4c2SBrett Creeley } 8339e4ab4c2SBrett Creeley 8349e4ab4c2SBrett Creeley /** 835f31e4b6fSAnirudh Venkataramanan * ice_init_hw - main hardware initialization routine 836f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure 837f31e4b6fSAnirudh Venkataramanan */ 838f31e4b6fSAnirudh Venkataramanan enum ice_status ice_init_hw(struct ice_hw *hw) 839f31e4b6fSAnirudh Venkataramanan { 840dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps_data *pcaps; 841f31e4b6fSAnirudh Venkataramanan enum ice_status status; 842dc49c772SAnirudh Venkataramanan u16 mac_buf_len; 843dc49c772SAnirudh Venkataramanan void *mac_buf; 844f31e4b6fSAnirudh Venkataramanan 845f31e4b6fSAnirudh Venkataramanan /* Set MAC type based on DeviceID */ 846f31e4b6fSAnirudh Venkataramanan status = ice_set_mac_type(hw); 847f31e4b6fSAnirudh Venkataramanan if (status) 848f31e4b6fSAnirudh Venkataramanan return status; 849f31e4b6fSAnirudh Venkataramanan 850f31e4b6fSAnirudh Venkataramanan hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 851f31e4b6fSAnirudh Venkataramanan PF_FUNC_RID_FUNC_NUM_M) >> 852f31e4b6fSAnirudh Venkataramanan PF_FUNC_RID_FUNC_NUM_S; 853f31e4b6fSAnirudh Venkataramanan 854f31e4b6fSAnirudh Venkataramanan status = ice_reset(hw, ICE_RESET_PFR); 855f31e4b6fSAnirudh Venkataramanan if (status) 856f31e4b6fSAnirudh Venkataramanan return status; 857f31e4b6fSAnirudh Venkataramanan 858fe7219faSBruce Allan ice_get_itr_intrl_gran(hw); 859940b61afSAnirudh Venkataramanan 8605c91ecfdSJacob Keller status = ice_create_all_ctrlq(hw); 861f31e4b6fSAnirudh Venkataramanan if (status) 862f31e4b6fSAnirudh Venkataramanan goto err_unroll_cqinit; 863f31e4b6fSAnirudh Venkataramanan 8648b97ceb1SHieu Tran /* Enable FW logging. Not fatal if this fails. */ 8658b97ceb1SHieu Tran status = ice_cfg_fw_log(hw, true); 8668b97ceb1SHieu Tran if (status) 8678b97ceb1SHieu Tran ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n"); 8688b97ceb1SHieu Tran 869f31e4b6fSAnirudh Venkataramanan status = ice_clear_pf_cfg(hw); 870f31e4b6fSAnirudh Venkataramanan if (status) 871f31e4b6fSAnirudh Venkataramanan goto err_unroll_cqinit; 872f31e4b6fSAnirudh Venkataramanan 873148beb61SHenry Tieman /* Set bit to enable Flow Director filters */ 874148beb61SHenry Tieman wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M); 875148beb61SHenry Tieman INIT_LIST_HEAD(&hw->fdir_list_head); 876148beb61SHenry Tieman 877f31e4b6fSAnirudh Venkataramanan ice_clear_pxe_mode(hw); 878f31e4b6fSAnirudh Venkataramanan 879f31e4b6fSAnirudh Venkataramanan status = ice_init_nvm(hw); 880f31e4b6fSAnirudh Venkataramanan if (status) 881f31e4b6fSAnirudh Venkataramanan goto err_unroll_cqinit; 882f31e4b6fSAnirudh Venkataramanan 8839c20346bSAnirudh Venkataramanan status = ice_get_caps(hw); 8849c20346bSAnirudh Venkataramanan if (status) 8859c20346bSAnirudh Venkataramanan goto err_unroll_cqinit; 8869c20346bSAnirudh Venkataramanan 8879c20346bSAnirudh Venkataramanan hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), 8889c20346bSAnirudh Venkataramanan sizeof(*hw->port_info), GFP_KERNEL); 8899c20346bSAnirudh Venkataramanan if (!hw->port_info) { 8909c20346bSAnirudh Venkataramanan status = ICE_ERR_NO_MEMORY; 8919c20346bSAnirudh Venkataramanan goto err_unroll_cqinit; 8929c20346bSAnirudh Venkataramanan } 8939c20346bSAnirudh Venkataramanan 894f9867df6SAnirudh Venkataramanan /* set the back pointer to HW */ 8959c20346bSAnirudh Venkataramanan hw->port_info->hw = hw; 8969c20346bSAnirudh Venkataramanan 8979c20346bSAnirudh Venkataramanan /* Initialize port_info struct with switch configuration data */ 8989c20346bSAnirudh Venkataramanan status = ice_get_initial_sw_cfg(hw); 8999c20346bSAnirudh Venkataramanan if (status) 9009c20346bSAnirudh Venkataramanan goto err_unroll_alloc; 9019c20346bSAnirudh Venkataramanan 9029daf8208SAnirudh Venkataramanan hw->evb_veb = true; 9039daf8208SAnirudh Venkataramanan 904d337f2afSAnirudh Venkataramanan /* Query the allocated resources for Tx scheduler */ 9059c20346bSAnirudh Venkataramanan status = ice_sched_query_res_alloc(hw); 9069c20346bSAnirudh Venkataramanan if (status) { 9079228d8b2SJacob Keller ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 9089c20346bSAnirudh Venkataramanan goto err_unroll_alloc; 9099c20346bSAnirudh Venkataramanan } 9109c20346bSAnirudh Venkataramanan 911dc49c772SAnirudh Venkataramanan /* Initialize port_info struct with scheduler data */ 912dc49c772SAnirudh Venkataramanan status = ice_sched_init_port(hw->port_info); 913dc49c772SAnirudh Venkataramanan if (status) 914dc49c772SAnirudh Venkataramanan goto err_unroll_sched; 915dc49c772SAnirudh Venkataramanan 916dc49c772SAnirudh Venkataramanan pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 917dc49c772SAnirudh Venkataramanan if (!pcaps) { 918dc49c772SAnirudh Venkataramanan status = ICE_ERR_NO_MEMORY; 919dc49c772SAnirudh Venkataramanan goto err_unroll_sched; 920dc49c772SAnirudh Venkataramanan } 921dc49c772SAnirudh Venkataramanan 922dc49c772SAnirudh Venkataramanan /* Initialize port_info struct with PHY capabilities */ 923dc49c772SAnirudh Venkataramanan status = ice_aq_get_phy_caps(hw->port_info, false, 924dc49c772SAnirudh Venkataramanan ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); 925dc49c772SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), pcaps); 926dc49c772SAnirudh Venkataramanan if (status) 927f2651a91SPaul M Stillwell Jr dev_warn(ice_hw_to_dev(hw), "Get PHY capabilities failed status = %d, continuing anyway\n", 928f2651a91SPaul M Stillwell Jr status); 929dc49c772SAnirudh Venkataramanan 930dc49c772SAnirudh Venkataramanan /* Initialize port_info struct with link information */ 931dc49c772SAnirudh Venkataramanan status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 932dc49c772SAnirudh Venkataramanan if (status) 933dc49c772SAnirudh Venkataramanan goto err_unroll_sched; 934dc49c772SAnirudh Venkataramanan 935b36c598cSAnirudh Venkataramanan /* need a valid SW entry point to build a Tx tree */ 936b36c598cSAnirudh Venkataramanan if (!hw->sw_entry_point_layer) { 937b36c598cSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 938b36c598cSAnirudh Venkataramanan status = ICE_ERR_CFG; 939b36c598cSAnirudh Venkataramanan goto err_unroll_sched; 940b36c598cSAnirudh Venkataramanan } 9419be1d6f8SAnirudh Venkataramanan INIT_LIST_HEAD(&hw->agg_list); 9421ddef455SUsha Ketineni /* Initialize max burst size */ 9431ddef455SUsha Ketineni if (!hw->max_burst_size) 9441ddef455SUsha Ketineni ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 945b36c598cSAnirudh Venkataramanan 9469daf8208SAnirudh Venkataramanan status = ice_init_fltr_mgmt_struct(hw); 9479daf8208SAnirudh Venkataramanan if (status) 9489daf8208SAnirudh Venkataramanan goto err_unroll_sched; 9499daf8208SAnirudh Venkataramanan 950d6fef10cSMd Fahad Iqbal Polash /* Get MAC information */ 951d6fef10cSMd Fahad Iqbal Polash /* A single port can report up to two (LAN and WoL) addresses */ 952d6fef10cSMd Fahad Iqbal Polash mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2, 953d6fef10cSMd Fahad Iqbal Polash sizeof(struct ice_aqc_manage_mac_read_resp), 954d6fef10cSMd Fahad Iqbal Polash GFP_KERNEL); 955d6fef10cSMd Fahad Iqbal Polash mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 956dc49c772SAnirudh Venkataramanan 95763bb4e1eSWei Yongjun if (!mac_buf) { 95863bb4e1eSWei Yongjun status = ICE_ERR_NO_MEMORY; 9599daf8208SAnirudh Venkataramanan goto err_unroll_fltr_mgmt_struct; 96063bb4e1eSWei Yongjun } 961dc49c772SAnirudh Venkataramanan 962dc49c772SAnirudh Venkataramanan status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 963dc49c772SAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), mac_buf); 964dc49c772SAnirudh Venkataramanan 965dc49c772SAnirudh Venkataramanan if (status) 9669daf8208SAnirudh Venkataramanan goto err_unroll_fltr_mgmt_struct; 96742449105SAnirudh Venkataramanan /* enable jumbo frame support at MAC level */ 96842449105SAnirudh Venkataramanan status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 96942449105SAnirudh Venkataramanan if (status) 97042449105SAnirudh Venkataramanan goto err_unroll_fltr_mgmt_struct; 971148beb61SHenry Tieman /* Obtain counter base index which would be used by flow director */ 972148beb61SHenry Tieman status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); 973148beb61SHenry Tieman if (status) 974148beb61SHenry Tieman goto err_unroll_fltr_mgmt_struct; 97532d63fa1STony Nguyen status = ice_init_hw_tbls(hw); 97632d63fa1STony Nguyen if (status) 97732d63fa1STony Nguyen goto err_unroll_fltr_mgmt_struct; 978a4e82a81STony Nguyen mutex_init(&hw->tnl_lock); 979f31e4b6fSAnirudh Venkataramanan return 0; 980f31e4b6fSAnirudh Venkataramanan 9819daf8208SAnirudh Venkataramanan err_unroll_fltr_mgmt_struct: 9829daf8208SAnirudh Venkataramanan ice_cleanup_fltr_mgmt_struct(hw); 983dc49c772SAnirudh Venkataramanan err_unroll_sched: 984dc49c772SAnirudh Venkataramanan ice_sched_cleanup_all(hw); 9859c20346bSAnirudh Venkataramanan err_unroll_alloc: 9869c20346bSAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), hw->port_info); 987f31e4b6fSAnirudh Venkataramanan err_unroll_cqinit: 9885c91ecfdSJacob Keller ice_destroy_all_ctrlq(hw); 989f31e4b6fSAnirudh Venkataramanan return status; 990f31e4b6fSAnirudh Venkataramanan } 991f31e4b6fSAnirudh Venkataramanan 992f31e4b6fSAnirudh Venkataramanan /** 993f31e4b6fSAnirudh Venkataramanan * ice_deinit_hw - unroll initialization operations done by ice_init_hw 994f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure 995ed14245aSAnirudh Venkataramanan * 996ed14245aSAnirudh Venkataramanan * This should be called only during nominal operation, not as a result of 997ed14245aSAnirudh Venkataramanan * ice_init_hw() failing since ice_init_hw() will take care of unrolling 998ed14245aSAnirudh Venkataramanan * applicable initializations if it fails for any reason. 999f31e4b6fSAnirudh Venkataramanan */ 1000f31e4b6fSAnirudh Venkataramanan void ice_deinit_hw(struct ice_hw *hw) 1001f31e4b6fSAnirudh Venkataramanan { 1002148beb61SHenry Tieman ice_free_fd_res_cntr(hw, hw->fd_ctr_base); 10038b97ceb1SHieu Tran ice_cleanup_fltr_mgmt_struct(hw); 10048b97ceb1SHieu Tran 10059c20346bSAnirudh Venkataramanan ice_sched_cleanup_all(hw); 10069be1d6f8SAnirudh Venkataramanan ice_sched_clear_agg(hw); 1007c7648810STony Nguyen ice_free_seg(hw); 100832d63fa1STony Nguyen ice_free_hw_tbls(hw); 1009a4e82a81STony Nguyen mutex_destroy(&hw->tnl_lock); 1010dc49c772SAnirudh Venkataramanan 10119c20346bSAnirudh Venkataramanan if (hw->port_info) { 10129c20346bSAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), hw->port_info); 10139c20346bSAnirudh Venkataramanan hw->port_info = NULL; 10149c20346bSAnirudh Venkataramanan } 10159daf8208SAnirudh Venkataramanan 10168b97ceb1SHieu Tran /* Attempt to disable FW logging before shutting down control queues */ 10178b97ceb1SHieu Tran ice_cfg_fw_log(hw, false); 10185c91ecfdSJacob Keller ice_destroy_all_ctrlq(hw); 101933e055fcSVictor Raj 102033e055fcSVictor Raj /* Clear VSI contexts if not already cleared */ 102133e055fcSVictor Raj ice_clear_all_vsi_ctx(hw); 1022f31e4b6fSAnirudh Venkataramanan } 1023f31e4b6fSAnirudh Venkataramanan 1024f31e4b6fSAnirudh Venkataramanan /** 1025f31e4b6fSAnirudh Venkataramanan * ice_check_reset - Check to see if a global reset is complete 1026f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure 1027f31e4b6fSAnirudh Venkataramanan */ 1028f31e4b6fSAnirudh Venkataramanan enum ice_status ice_check_reset(struct ice_hw *hw) 1029f31e4b6fSAnirudh Venkataramanan { 1030585cdabdSNick Nunley u32 cnt, reg = 0, grst_timeout, uld_mask; 1031f31e4b6fSAnirudh Venkataramanan 1032f31e4b6fSAnirudh Venkataramanan /* Poll for Device Active state in case a recent CORER, GLOBR, 1033f31e4b6fSAnirudh Venkataramanan * or EMPR has occurred. The grst delay value is in 100ms units. 1034f31e4b6fSAnirudh Venkataramanan * Add 1sec for outstanding AQ commands that can take a long time. 1035f31e4b6fSAnirudh Venkataramanan */ 1036585cdabdSNick Nunley grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 1037f31e4b6fSAnirudh Venkataramanan GLGEN_RSTCTL_GRSTDEL_S) + 10; 1038f31e4b6fSAnirudh Venkataramanan 1039585cdabdSNick Nunley for (cnt = 0; cnt < grst_timeout; cnt++) { 1040f31e4b6fSAnirudh Venkataramanan mdelay(100); 1041f31e4b6fSAnirudh Venkataramanan reg = rd32(hw, GLGEN_RSTAT); 1042f31e4b6fSAnirudh Venkataramanan if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 1043f31e4b6fSAnirudh Venkataramanan break; 1044f31e4b6fSAnirudh Venkataramanan } 1045f31e4b6fSAnirudh Venkataramanan 1046585cdabdSNick Nunley if (cnt == grst_timeout) { 10479228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 1048f31e4b6fSAnirudh Venkataramanan return ICE_ERR_RESET_FAILED; 1049f31e4b6fSAnirudh Venkataramanan } 1050f31e4b6fSAnirudh Venkataramanan 1051cf8fc2a0SBruce Allan #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 1052cf8fc2a0SBruce Allan GLNVM_ULD_PCIER_DONE_1_M |\ 1053cf8fc2a0SBruce Allan GLNVM_ULD_CORER_DONE_M |\ 1054cf8fc2a0SBruce Allan GLNVM_ULD_GLOBR_DONE_M |\ 1055cf8fc2a0SBruce Allan GLNVM_ULD_POR_DONE_M |\ 1056cf8fc2a0SBruce Allan GLNVM_ULD_POR_DONE_1_M |\ 1057cf8fc2a0SBruce Allan GLNVM_ULD_PCIER_DONE_2_M) 1058cf8fc2a0SBruce Allan 1059cf8fc2a0SBruce Allan uld_mask = ICE_RESET_DONE_MASK; 1060f31e4b6fSAnirudh Venkataramanan 1061f31e4b6fSAnirudh Venkataramanan /* Device is Active; check Global Reset processes are done */ 1062f31e4b6fSAnirudh Venkataramanan for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 1063cf8fc2a0SBruce Allan reg = rd32(hw, GLNVM_ULD) & uld_mask; 1064cf8fc2a0SBruce Allan if (reg == uld_mask) { 10659228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 1066f31e4b6fSAnirudh Venkataramanan break; 1067f31e4b6fSAnirudh Venkataramanan } 1068f31e4b6fSAnirudh Venkataramanan mdelay(10); 1069f31e4b6fSAnirudh Venkataramanan } 1070f31e4b6fSAnirudh Venkataramanan 1071f31e4b6fSAnirudh Venkataramanan if (cnt == ICE_PF_RESET_WAIT_COUNT) { 10729228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 1073f31e4b6fSAnirudh Venkataramanan reg); 1074f31e4b6fSAnirudh Venkataramanan return ICE_ERR_RESET_FAILED; 1075f31e4b6fSAnirudh Venkataramanan } 1076f31e4b6fSAnirudh Venkataramanan 1077f31e4b6fSAnirudh Venkataramanan return 0; 1078f31e4b6fSAnirudh Venkataramanan } 1079f31e4b6fSAnirudh Venkataramanan 1080f31e4b6fSAnirudh Venkataramanan /** 1081f31e4b6fSAnirudh Venkataramanan * ice_pf_reset - Reset the PF 1082f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure 1083f31e4b6fSAnirudh Venkataramanan * 1084f31e4b6fSAnirudh Venkataramanan * If a global reset has been triggered, this function checks 1085f31e4b6fSAnirudh Venkataramanan * for its completion and then issues the PF reset 1086f31e4b6fSAnirudh Venkataramanan */ 1087f31e4b6fSAnirudh Venkataramanan static enum ice_status ice_pf_reset(struct ice_hw *hw) 1088f31e4b6fSAnirudh Venkataramanan { 1089f31e4b6fSAnirudh Venkataramanan u32 cnt, reg; 1090f31e4b6fSAnirudh Venkataramanan 1091f31e4b6fSAnirudh Venkataramanan /* If at function entry a global reset was already in progress, i.e. 1092f31e4b6fSAnirudh Venkataramanan * state is not 'device active' or any of the reset done bits are not 1093f31e4b6fSAnirudh Venkataramanan * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 1094f31e4b6fSAnirudh Venkataramanan * global reset is done. 1095f31e4b6fSAnirudh Venkataramanan */ 1096f31e4b6fSAnirudh Venkataramanan if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 1097f31e4b6fSAnirudh Venkataramanan (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 1098f31e4b6fSAnirudh Venkataramanan /* poll on global reset currently in progress until done */ 1099f31e4b6fSAnirudh Venkataramanan if (ice_check_reset(hw)) 1100f31e4b6fSAnirudh Venkataramanan return ICE_ERR_RESET_FAILED; 1101f31e4b6fSAnirudh Venkataramanan 1102f31e4b6fSAnirudh Venkataramanan return 0; 1103f31e4b6fSAnirudh Venkataramanan } 1104f31e4b6fSAnirudh Venkataramanan 1105f31e4b6fSAnirudh Venkataramanan /* Reset the PF */ 1106f31e4b6fSAnirudh Venkataramanan reg = rd32(hw, PFGEN_CTRL); 1107f31e4b6fSAnirudh Venkataramanan 1108f31e4b6fSAnirudh Venkataramanan wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 1109f31e4b6fSAnirudh Venkataramanan 1110c9a12d6dSDan Nowlin /* Wait for the PFR to complete. The wait time is the global config lock 1111c9a12d6dSDan Nowlin * timeout plus the PFR timeout which will account for a possible reset 1112c9a12d6dSDan Nowlin * that is occurring during a download package operation. 1113c9a12d6dSDan Nowlin */ 1114c9a12d6dSDan Nowlin for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 1115c9a12d6dSDan Nowlin ICE_PF_RESET_WAIT_COUNT; cnt++) { 1116f31e4b6fSAnirudh Venkataramanan reg = rd32(hw, PFGEN_CTRL); 1117f31e4b6fSAnirudh Venkataramanan if (!(reg & PFGEN_CTRL_PFSWR_M)) 1118f31e4b6fSAnirudh Venkataramanan break; 1119f31e4b6fSAnirudh Venkataramanan 1120f31e4b6fSAnirudh Venkataramanan mdelay(1); 1121f31e4b6fSAnirudh Venkataramanan } 1122f31e4b6fSAnirudh Venkataramanan 1123f31e4b6fSAnirudh Venkataramanan if (cnt == ICE_PF_RESET_WAIT_COUNT) { 11249228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 1125f31e4b6fSAnirudh Venkataramanan return ICE_ERR_RESET_FAILED; 1126f31e4b6fSAnirudh Venkataramanan } 1127f31e4b6fSAnirudh Venkataramanan 1128f31e4b6fSAnirudh Venkataramanan return 0; 1129f31e4b6fSAnirudh Venkataramanan } 1130f31e4b6fSAnirudh Venkataramanan 1131f31e4b6fSAnirudh Venkataramanan /** 1132f31e4b6fSAnirudh Venkataramanan * ice_reset - Perform different types of reset 1133f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the hardware structure 1134f31e4b6fSAnirudh Venkataramanan * @req: reset request 1135f31e4b6fSAnirudh Venkataramanan * 1136f31e4b6fSAnirudh Venkataramanan * This function triggers a reset as specified by the req parameter. 1137f31e4b6fSAnirudh Venkataramanan * 1138f31e4b6fSAnirudh Venkataramanan * Note: 1139f31e4b6fSAnirudh Venkataramanan * If anything other than a PF reset is triggered, PXE mode is restored. 1140f31e4b6fSAnirudh Venkataramanan * This has to be cleared using ice_clear_pxe_mode again, once the AQ 1141f31e4b6fSAnirudh Venkataramanan * interface has been restored in the rebuild flow. 1142f31e4b6fSAnirudh Venkataramanan */ 1143f31e4b6fSAnirudh Venkataramanan enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 1144f31e4b6fSAnirudh Venkataramanan { 1145f31e4b6fSAnirudh Venkataramanan u32 val = 0; 1146f31e4b6fSAnirudh Venkataramanan 1147f31e4b6fSAnirudh Venkataramanan switch (req) { 1148f31e4b6fSAnirudh Venkataramanan case ICE_RESET_PFR: 1149f31e4b6fSAnirudh Venkataramanan return ice_pf_reset(hw); 1150f31e4b6fSAnirudh Venkataramanan case ICE_RESET_CORER: 1151f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 1152f31e4b6fSAnirudh Venkataramanan val = GLGEN_RTRIG_CORER_M; 1153f31e4b6fSAnirudh Venkataramanan break; 1154f31e4b6fSAnirudh Venkataramanan case ICE_RESET_GLOBR: 1155f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 1156f31e4b6fSAnirudh Venkataramanan val = GLGEN_RTRIG_GLOBR_M; 1157f31e4b6fSAnirudh Venkataramanan break; 11580f9d5027SAnirudh Venkataramanan default: 11590f9d5027SAnirudh Venkataramanan return ICE_ERR_PARAM; 1160f31e4b6fSAnirudh Venkataramanan } 1161f31e4b6fSAnirudh Venkataramanan 1162f31e4b6fSAnirudh Venkataramanan val |= rd32(hw, GLGEN_RTRIG); 1163f31e4b6fSAnirudh Venkataramanan wr32(hw, GLGEN_RTRIG, val); 1164f31e4b6fSAnirudh Venkataramanan ice_flush(hw); 1165f31e4b6fSAnirudh Venkataramanan 1166f31e4b6fSAnirudh Venkataramanan /* wait for the FW to be ready */ 1167f31e4b6fSAnirudh Venkataramanan return ice_check_reset(hw); 1168f31e4b6fSAnirudh Venkataramanan } 1169f31e4b6fSAnirudh Venkataramanan 11707ec59eeaSAnirudh Venkataramanan /** 1171cdedef59SAnirudh Venkataramanan * ice_copy_rxq_ctx_to_hw 1172cdedef59SAnirudh Venkataramanan * @hw: pointer to the hardware structure 1173cdedef59SAnirudh Venkataramanan * @ice_rxq_ctx: pointer to the rxq context 1174d337f2afSAnirudh Venkataramanan * @rxq_index: the index of the Rx queue 1175cdedef59SAnirudh Venkataramanan * 1176f9867df6SAnirudh Venkataramanan * Copies rxq context from dense structure to HW register space 1177cdedef59SAnirudh Venkataramanan */ 1178cdedef59SAnirudh Venkataramanan static enum ice_status 1179cdedef59SAnirudh Venkataramanan ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 1180cdedef59SAnirudh Venkataramanan { 1181cdedef59SAnirudh Venkataramanan u8 i; 1182cdedef59SAnirudh Venkataramanan 1183cdedef59SAnirudh Venkataramanan if (!ice_rxq_ctx) 1184cdedef59SAnirudh Venkataramanan return ICE_ERR_BAD_PTR; 1185cdedef59SAnirudh Venkataramanan 1186cdedef59SAnirudh Venkataramanan if (rxq_index > QRX_CTRL_MAX_INDEX) 1187cdedef59SAnirudh Venkataramanan return ICE_ERR_PARAM; 1188cdedef59SAnirudh Venkataramanan 1189f9867df6SAnirudh Venkataramanan /* Copy each dword separately to HW */ 1190cdedef59SAnirudh Venkataramanan for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 1191cdedef59SAnirudh Venkataramanan wr32(hw, QRX_CONTEXT(i, rxq_index), 1192cdedef59SAnirudh Venkataramanan *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1193cdedef59SAnirudh Venkataramanan 1194cdedef59SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 1195cdedef59SAnirudh Venkataramanan *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 1196cdedef59SAnirudh Venkataramanan } 1197cdedef59SAnirudh Venkataramanan 1198cdedef59SAnirudh Venkataramanan return 0; 1199cdedef59SAnirudh Venkataramanan } 1200cdedef59SAnirudh Venkataramanan 1201cdedef59SAnirudh Venkataramanan /* LAN Rx Queue Context */ 1202cdedef59SAnirudh Venkataramanan static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 1203cdedef59SAnirudh Venkataramanan /* Field Width LSB */ 1204cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 1205cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 1206cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 1207cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 1208cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 1209cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 1210cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 1211cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 1212cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 1213cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 1214cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 1215cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 1216cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 1217cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 1218cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 1219cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 1220cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 1221cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 1222cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 1223c31a5c25SBrett Creeley ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 1224cdedef59SAnirudh Venkataramanan { 0 } 1225cdedef59SAnirudh Venkataramanan }; 1226cdedef59SAnirudh Venkataramanan 1227cdedef59SAnirudh Venkataramanan /** 1228cdedef59SAnirudh Venkataramanan * ice_write_rxq_ctx 1229cdedef59SAnirudh Venkataramanan * @hw: pointer to the hardware structure 1230cdedef59SAnirudh Venkataramanan * @rlan_ctx: pointer to the rxq context 1231d337f2afSAnirudh Venkataramanan * @rxq_index: the index of the Rx queue 1232cdedef59SAnirudh Venkataramanan * 1233cdedef59SAnirudh Venkataramanan * Converts rxq context from sparse to dense structure and then writes 1234c31a5c25SBrett Creeley * it to HW register space and enables the hardware to prefetch descriptors 1235c31a5c25SBrett Creeley * instead of only fetching them on demand 1236cdedef59SAnirudh Venkataramanan */ 1237cdedef59SAnirudh Venkataramanan enum ice_status 1238cdedef59SAnirudh Venkataramanan ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 1239cdedef59SAnirudh Venkataramanan u32 rxq_index) 1240cdedef59SAnirudh Venkataramanan { 1241cdedef59SAnirudh Venkataramanan u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 1242cdedef59SAnirudh Venkataramanan 1243c31a5c25SBrett Creeley if (!rlan_ctx) 1244c31a5c25SBrett Creeley return ICE_ERR_BAD_PTR; 1245c31a5c25SBrett Creeley 1246c31a5c25SBrett Creeley rlan_ctx->prefena = 1; 1247c31a5c25SBrett Creeley 12487e34786aSBruce Allan ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 1249cdedef59SAnirudh Venkataramanan return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 1250cdedef59SAnirudh Venkataramanan } 1251cdedef59SAnirudh Venkataramanan 1252cdedef59SAnirudh Venkataramanan /* LAN Tx Queue Context */ 1253cdedef59SAnirudh Venkataramanan const struct ice_ctx_ele ice_tlan_ctx_info[] = { 1254cdedef59SAnirudh Venkataramanan /* Field Width LSB */ 1255cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 1256cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 1257cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 1258cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 1259cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 1260cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 1261cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 1262cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 1263201beeb7SAshish Shah ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 1264cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 1265cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 1266cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 1267cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 1268cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 1269cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 1270cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 1271cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 1272cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 1273cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 1274cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 1275cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 1276cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 1277cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 1278cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 1279cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 1280cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 1281cdedef59SAnirudh Venkataramanan ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 1282201beeb7SAshish Shah ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 1283cdedef59SAnirudh Venkataramanan { 0 } 1284cdedef59SAnirudh Venkataramanan }; 1285cdedef59SAnirudh Venkataramanan 12867ec59eeaSAnirudh Venkataramanan /* FW Admin Queue command wrappers */ 12877ec59eeaSAnirudh Venkataramanan 1288c7648810STony Nguyen /* Software lock/mutex that is meant to be held while the Global Config Lock 1289c7648810STony Nguyen * in firmware is acquired by the software to prevent most (but not all) types 1290c7648810STony Nguyen * of AQ commands from being sent to FW 1291c7648810STony Nguyen */ 1292c7648810STony Nguyen DEFINE_MUTEX(ice_global_cfg_lock_sw); 1293c7648810STony Nguyen 12947ec59eeaSAnirudh Venkataramanan /** 12957ec59eeaSAnirudh Venkataramanan * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 1296f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 12977ec59eeaSAnirudh Venkataramanan * @desc: descriptor describing the command 12987ec59eeaSAnirudh Venkataramanan * @buf: buffer to use for indirect commands (NULL for direct commands) 12997ec59eeaSAnirudh Venkataramanan * @buf_size: size of buffer for indirect commands (0 for direct commands) 13007ec59eeaSAnirudh Venkataramanan * @cd: pointer to command details structure 13017ec59eeaSAnirudh Venkataramanan * 13027ec59eeaSAnirudh Venkataramanan * Helper function to send FW Admin Queue commands to the FW Admin Queue. 13037ec59eeaSAnirudh Venkataramanan */ 13047ec59eeaSAnirudh Venkataramanan enum ice_status 13057ec59eeaSAnirudh Venkataramanan ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 13067ec59eeaSAnirudh Venkataramanan u16 buf_size, struct ice_sq_cd *cd) 13077ec59eeaSAnirudh Venkataramanan { 1308c7648810STony Nguyen struct ice_aqc_req_res *cmd = &desc->params.res_owner; 1309c7648810STony Nguyen bool lock_acquired = false; 1310c7648810STony Nguyen enum ice_status status; 1311c7648810STony Nguyen 1312c7648810STony Nguyen /* When a package download is in process (i.e. when the firmware's 1313c7648810STony Nguyen * Global Configuration Lock resource is held), only the Download 1314c7648810STony Nguyen * Package, Get Version, Get Package Info List and Release Resource 1315c7648810STony Nguyen * (with resource ID set to Global Config Lock) AdminQ commands are 1316c7648810STony Nguyen * allowed; all others must block until the package download completes 1317c7648810STony Nguyen * and the Global Config Lock is released. See also 1318c7648810STony Nguyen * ice_acquire_global_cfg_lock(). 1319c7648810STony Nguyen */ 1320c7648810STony Nguyen switch (le16_to_cpu(desc->opcode)) { 1321c7648810STony Nguyen case ice_aqc_opc_download_pkg: 1322c7648810STony Nguyen case ice_aqc_opc_get_pkg_info_list: 1323c7648810STony Nguyen case ice_aqc_opc_get_ver: 1324c7648810STony Nguyen break; 1325c7648810STony Nguyen case ice_aqc_opc_release_res: 1326c7648810STony Nguyen if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) 1327c7648810STony Nguyen break; 13284e83fc93SBruce Allan fallthrough; 1329c7648810STony Nguyen default: 1330c7648810STony Nguyen mutex_lock(&ice_global_cfg_lock_sw); 1331c7648810STony Nguyen lock_acquired = true; 1332c7648810STony Nguyen break; 1333c7648810STony Nguyen } 1334c7648810STony Nguyen 1335c7648810STony Nguyen status = ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd); 1336c7648810STony Nguyen if (lock_acquired) 1337c7648810STony Nguyen mutex_unlock(&ice_global_cfg_lock_sw); 1338c7648810STony Nguyen 1339c7648810STony Nguyen return status; 13407ec59eeaSAnirudh Venkataramanan } 13417ec59eeaSAnirudh Venkataramanan 13427ec59eeaSAnirudh Venkataramanan /** 13437ec59eeaSAnirudh Venkataramanan * ice_aq_get_fw_ver 1344f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 13457ec59eeaSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 13467ec59eeaSAnirudh Venkataramanan * 13477ec59eeaSAnirudh Venkataramanan * Get the firmware version (0x0001) from the admin queue commands 13487ec59eeaSAnirudh Venkataramanan */ 13497ec59eeaSAnirudh Venkataramanan enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 13507ec59eeaSAnirudh Venkataramanan { 13517ec59eeaSAnirudh Venkataramanan struct ice_aqc_get_ver *resp; 13527ec59eeaSAnirudh Venkataramanan struct ice_aq_desc desc; 13537ec59eeaSAnirudh Venkataramanan enum ice_status status; 13547ec59eeaSAnirudh Venkataramanan 13557ec59eeaSAnirudh Venkataramanan resp = &desc.params.get_ver; 13567ec59eeaSAnirudh Venkataramanan 13577ec59eeaSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 13587ec59eeaSAnirudh Venkataramanan 13597ec59eeaSAnirudh Venkataramanan status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 13607ec59eeaSAnirudh Venkataramanan 13617ec59eeaSAnirudh Venkataramanan if (!status) { 13627ec59eeaSAnirudh Venkataramanan hw->fw_branch = resp->fw_branch; 13637ec59eeaSAnirudh Venkataramanan hw->fw_maj_ver = resp->fw_major; 13647ec59eeaSAnirudh Venkataramanan hw->fw_min_ver = resp->fw_minor; 13657ec59eeaSAnirudh Venkataramanan hw->fw_patch = resp->fw_patch; 13667ec59eeaSAnirudh Venkataramanan hw->fw_build = le32_to_cpu(resp->fw_build); 13677ec59eeaSAnirudh Venkataramanan hw->api_branch = resp->api_branch; 13687ec59eeaSAnirudh Venkataramanan hw->api_maj_ver = resp->api_major; 13697ec59eeaSAnirudh Venkataramanan hw->api_min_ver = resp->api_minor; 13707ec59eeaSAnirudh Venkataramanan hw->api_patch = resp->api_patch; 13717ec59eeaSAnirudh Venkataramanan } 13727ec59eeaSAnirudh Venkataramanan 13737ec59eeaSAnirudh Venkataramanan return status; 13747ec59eeaSAnirudh Venkataramanan } 13757ec59eeaSAnirudh Venkataramanan 13767ec59eeaSAnirudh Venkataramanan /** 1377e3710a01SPaul M Stillwell Jr * ice_aq_send_driver_ver 1378e3710a01SPaul M Stillwell Jr * @hw: pointer to the HW struct 1379e3710a01SPaul M Stillwell Jr * @dv: driver's major, minor version 1380e3710a01SPaul M Stillwell Jr * @cd: pointer to command details structure or NULL 1381e3710a01SPaul M Stillwell Jr * 1382e3710a01SPaul M Stillwell Jr * Send the driver version (0x0002) to the firmware 1383e3710a01SPaul M Stillwell Jr */ 1384e3710a01SPaul M Stillwell Jr enum ice_status 1385e3710a01SPaul M Stillwell Jr ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 1386e3710a01SPaul M Stillwell Jr struct ice_sq_cd *cd) 1387e3710a01SPaul M Stillwell Jr { 1388e3710a01SPaul M Stillwell Jr struct ice_aqc_driver_ver *cmd; 1389e3710a01SPaul M Stillwell Jr struct ice_aq_desc desc; 1390e3710a01SPaul M Stillwell Jr u16 len; 1391e3710a01SPaul M Stillwell Jr 1392e3710a01SPaul M Stillwell Jr cmd = &desc.params.driver_ver; 1393e3710a01SPaul M Stillwell Jr 1394e3710a01SPaul M Stillwell Jr if (!dv) 1395e3710a01SPaul M Stillwell Jr return ICE_ERR_PARAM; 1396e3710a01SPaul M Stillwell Jr 1397e3710a01SPaul M Stillwell Jr ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 1398e3710a01SPaul M Stillwell Jr 1399e3710a01SPaul M Stillwell Jr desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 1400e3710a01SPaul M Stillwell Jr cmd->major_ver = dv->major_ver; 1401e3710a01SPaul M Stillwell Jr cmd->minor_ver = dv->minor_ver; 1402e3710a01SPaul M Stillwell Jr cmd->build_ver = dv->build_ver; 1403e3710a01SPaul M Stillwell Jr cmd->subbuild_ver = dv->subbuild_ver; 1404e3710a01SPaul M Stillwell Jr 1405e3710a01SPaul M Stillwell Jr len = 0; 1406e3710a01SPaul M Stillwell Jr while (len < sizeof(dv->driver_string) && 1407e3710a01SPaul M Stillwell Jr isascii(dv->driver_string[len]) && dv->driver_string[len]) 1408e3710a01SPaul M Stillwell Jr len++; 1409e3710a01SPaul M Stillwell Jr 1410e3710a01SPaul M Stillwell Jr return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 1411e3710a01SPaul M Stillwell Jr } 1412e3710a01SPaul M Stillwell Jr 1413e3710a01SPaul M Stillwell Jr /** 14147ec59eeaSAnirudh Venkataramanan * ice_aq_q_shutdown 1415f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 14167ec59eeaSAnirudh Venkataramanan * @unloading: is the driver unloading itself 14177ec59eeaSAnirudh Venkataramanan * 14187ec59eeaSAnirudh Venkataramanan * Tell the Firmware that we're shutting down the AdminQ and whether 14197ec59eeaSAnirudh Venkataramanan * or not the driver is unloading as well (0x0003). 14207ec59eeaSAnirudh Venkataramanan */ 14217ec59eeaSAnirudh Venkataramanan enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 14227ec59eeaSAnirudh Venkataramanan { 14237ec59eeaSAnirudh Venkataramanan struct ice_aqc_q_shutdown *cmd; 14247ec59eeaSAnirudh Venkataramanan struct ice_aq_desc desc; 14257ec59eeaSAnirudh Venkataramanan 14267ec59eeaSAnirudh Venkataramanan cmd = &desc.params.q_shutdown; 14277ec59eeaSAnirudh Venkataramanan 14287ec59eeaSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 14297ec59eeaSAnirudh Venkataramanan 14307ec59eeaSAnirudh Venkataramanan if (unloading) 14317404e84aSBruce Allan cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 14327ec59eeaSAnirudh Venkataramanan 14337ec59eeaSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 14347ec59eeaSAnirudh Venkataramanan } 1435f31e4b6fSAnirudh Venkataramanan 1436f31e4b6fSAnirudh Venkataramanan /** 1437f31e4b6fSAnirudh Venkataramanan * ice_aq_req_res 1438f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 1439f9867df6SAnirudh Venkataramanan * @res: resource ID 1440f31e4b6fSAnirudh Venkataramanan * @access: access type 1441f31e4b6fSAnirudh Venkataramanan * @sdp_number: resource number 1442f31e4b6fSAnirudh Venkataramanan * @timeout: the maximum time in ms that the driver may hold the resource 1443f31e4b6fSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 1444f31e4b6fSAnirudh Venkataramanan * 1445ff2b1321SDan Nowlin * Requests common resource using the admin queue commands (0x0008). 1446ff2b1321SDan Nowlin * When attempting to acquire the Global Config Lock, the driver can 1447ff2b1321SDan Nowlin * learn of three states: 1448ff2b1321SDan Nowlin * 1) ICE_SUCCESS - acquired lock, and can perform download package 1449ff2b1321SDan Nowlin * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 1450ff2b1321SDan Nowlin * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 1451ff2b1321SDan Nowlin * successfully downloaded the package; the driver does 1452ff2b1321SDan Nowlin * not have to download the package and can continue 1453ff2b1321SDan Nowlin * loading 1454ff2b1321SDan Nowlin * 1455ff2b1321SDan Nowlin * Note that if the caller is in an acquire lock, perform action, release lock 1456ff2b1321SDan Nowlin * phase of operation, it is possible that the FW may detect a timeout and issue 1457ff2b1321SDan Nowlin * a CORER. In this case, the driver will receive a CORER interrupt and will 1458ff2b1321SDan Nowlin * have to determine its cause. The calling thread that is handling this flow 1459ff2b1321SDan Nowlin * will likely get an error propagated back to it indicating the Download 1460ff2b1321SDan Nowlin * Package, Update Package or the Release Resource AQ commands timed out. 1461f31e4b6fSAnirudh Venkataramanan */ 1462f31e4b6fSAnirudh Venkataramanan static enum ice_status 1463f31e4b6fSAnirudh Venkataramanan ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1464f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 1465f31e4b6fSAnirudh Venkataramanan struct ice_sq_cd *cd) 1466f31e4b6fSAnirudh Venkataramanan { 1467f31e4b6fSAnirudh Venkataramanan struct ice_aqc_req_res *cmd_resp; 1468f31e4b6fSAnirudh Venkataramanan struct ice_aq_desc desc; 1469f31e4b6fSAnirudh Venkataramanan enum ice_status status; 1470f31e4b6fSAnirudh Venkataramanan 1471f31e4b6fSAnirudh Venkataramanan cmd_resp = &desc.params.res_owner; 1472f31e4b6fSAnirudh Venkataramanan 1473f31e4b6fSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 1474f31e4b6fSAnirudh Venkataramanan 1475f31e4b6fSAnirudh Venkataramanan cmd_resp->res_id = cpu_to_le16(res); 1476f31e4b6fSAnirudh Venkataramanan cmd_resp->access_type = cpu_to_le16(access); 1477f31e4b6fSAnirudh Venkataramanan cmd_resp->res_number = cpu_to_le32(sdp_number); 1478ff2b1321SDan Nowlin cmd_resp->timeout = cpu_to_le32(*timeout); 1479ff2b1321SDan Nowlin *timeout = 0; 1480f31e4b6fSAnirudh Venkataramanan 1481f31e4b6fSAnirudh Venkataramanan status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1482ff2b1321SDan Nowlin 1483f31e4b6fSAnirudh Venkataramanan /* The completion specifies the maximum time in ms that the driver 1484f31e4b6fSAnirudh Venkataramanan * may hold the resource in the Timeout field. 1485ff2b1321SDan Nowlin */ 1486ff2b1321SDan Nowlin 1487ff2b1321SDan Nowlin /* Global config lock response utilizes an additional status field. 1488ff2b1321SDan Nowlin * 1489ff2b1321SDan Nowlin * If the Global config lock resource is held by some other driver, the 1490ff2b1321SDan Nowlin * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 1491ff2b1321SDan Nowlin * and the timeout field indicates the maximum time the current owner 1492ff2b1321SDan Nowlin * of the resource has to free it. 1493ff2b1321SDan Nowlin */ 1494ff2b1321SDan Nowlin if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 1495ff2b1321SDan Nowlin if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 1496ff2b1321SDan Nowlin *timeout = le32_to_cpu(cmd_resp->timeout); 1497ff2b1321SDan Nowlin return 0; 1498ff2b1321SDan Nowlin } else if (le16_to_cpu(cmd_resp->status) == 1499ff2b1321SDan Nowlin ICE_AQ_RES_GLBL_IN_PROG) { 1500ff2b1321SDan Nowlin *timeout = le32_to_cpu(cmd_resp->timeout); 1501ff2b1321SDan Nowlin return ICE_ERR_AQ_ERROR; 1502ff2b1321SDan Nowlin } else if (le16_to_cpu(cmd_resp->status) == 1503ff2b1321SDan Nowlin ICE_AQ_RES_GLBL_DONE) { 1504ff2b1321SDan Nowlin return ICE_ERR_AQ_NO_WORK; 1505ff2b1321SDan Nowlin } 1506ff2b1321SDan Nowlin 1507ff2b1321SDan Nowlin /* invalid FW response, force a timeout immediately */ 1508ff2b1321SDan Nowlin *timeout = 0; 1509ff2b1321SDan Nowlin return ICE_ERR_AQ_ERROR; 1510ff2b1321SDan Nowlin } 1511ff2b1321SDan Nowlin 1512ff2b1321SDan Nowlin /* If the resource is held by some other driver, the command completes 1513ff2b1321SDan Nowlin * with a busy return value and the timeout field indicates the maximum 1514ff2b1321SDan Nowlin * time the current owner of the resource has to free it. 1515f31e4b6fSAnirudh Venkataramanan */ 1516f31e4b6fSAnirudh Venkataramanan if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 1517f31e4b6fSAnirudh Venkataramanan *timeout = le32_to_cpu(cmd_resp->timeout); 1518f31e4b6fSAnirudh Venkataramanan 1519f31e4b6fSAnirudh Venkataramanan return status; 1520f31e4b6fSAnirudh Venkataramanan } 1521f31e4b6fSAnirudh Venkataramanan 1522f31e4b6fSAnirudh Venkataramanan /** 1523f31e4b6fSAnirudh Venkataramanan * ice_aq_release_res 1524f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 1525f9867df6SAnirudh Venkataramanan * @res: resource ID 1526f31e4b6fSAnirudh Venkataramanan * @sdp_number: resource number 1527f31e4b6fSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 1528f31e4b6fSAnirudh Venkataramanan * 1529f31e4b6fSAnirudh Venkataramanan * release common resource using the admin queue commands (0x0009) 1530f31e4b6fSAnirudh Venkataramanan */ 1531f31e4b6fSAnirudh Venkataramanan static enum ice_status 1532f31e4b6fSAnirudh Venkataramanan ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 1533f31e4b6fSAnirudh Venkataramanan struct ice_sq_cd *cd) 1534f31e4b6fSAnirudh Venkataramanan { 1535f31e4b6fSAnirudh Venkataramanan struct ice_aqc_req_res *cmd; 1536f31e4b6fSAnirudh Venkataramanan struct ice_aq_desc desc; 1537f31e4b6fSAnirudh Venkataramanan 1538f31e4b6fSAnirudh Venkataramanan cmd = &desc.params.res_owner; 1539f31e4b6fSAnirudh Venkataramanan 1540f31e4b6fSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 1541f31e4b6fSAnirudh Venkataramanan 1542f31e4b6fSAnirudh Venkataramanan cmd->res_id = cpu_to_le16(res); 1543f31e4b6fSAnirudh Venkataramanan cmd->res_number = cpu_to_le32(sdp_number); 1544f31e4b6fSAnirudh Venkataramanan 1545f31e4b6fSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 1546f31e4b6fSAnirudh Venkataramanan } 1547f31e4b6fSAnirudh Venkataramanan 1548f31e4b6fSAnirudh Venkataramanan /** 1549f31e4b6fSAnirudh Venkataramanan * ice_acquire_res 1550f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the HW structure 1551f9867df6SAnirudh Venkataramanan * @res: resource ID 1552f31e4b6fSAnirudh Venkataramanan * @access: access type (read or write) 1553ff2b1321SDan Nowlin * @timeout: timeout in milliseconds 1554f31e4b6fSAnirudh Venkataramanan * 1555f31e4b6fSAnirudh Venkataramanan * This function will attempt to acquire the ownership of a resource. 1556f31e4b6fSAnirudh Venkataramanan */ 1557f31e4b6fSAnirudh Venkataramanan enum ice_status 1558f31e4b6fSAnirudh Venkataramanan ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 1559ff2b1321SDan Nowlin enum ice_aq_res_access_type access, u32 timeout) 1560f31e4b6fSAnirudh Venkataramanan { 1561f31e4b6fSAnirudh Venkataramanan #define ICE_RES_POLLING_DELAY_MS 10 1562f31e4b6fSAnirudh Venkataramanan u32 delay = ICE_RES_POLLING_DELAY_MS; 1563ff2b1321SDan Nowlin u32 time_left = timeout; 1564f31e4b6fSAnirudh Venkataramanan enum ice_status status; 1565f31e4b6fSAnirudh Venkataramanan 1566f31e4b6fSAnirudh Venkataramanan status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1567f31e4b6fSAnirudh Venkataramanan 1568ff2b1321SDan Nowlin /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 1569ff2b1321SDan Nowlin * previously acquired the resource and performed any necessary updates; 1570ff2b1321SDan Nowlin * in this case the caller does not obtain the resource and has no 1571ff2b1321SDan Nowlin * further work to do. 1572f31e4b6fSAnirudh Venkataramanan */ 1573ff2b1321SDan Nowlin if (status == ICE_ERR_AQ_NO_WORK) 1574f31e4b6fSAnirudh Venkataramanan goto ice_acquire_res_exit; 1575f31e4b6fSAnirudh Venkataramanan 1576f31e4b6fSAnirudh Venkataramanan if (status) 15779228d8b2SJacob Keller ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 1578f31e4b6fSAnirudh Venkataramanan 1579f31e4b6fSAnirudh Venkataramanan /* If necessary, poll until the current lock owner timeouts */ 1580f31e4b6fSAnirudh Venkataramanan timeout = time_left; 1581f31e4b6fSAnirudh Venkataramanan while (status && timeout && time_left) { 1582f31e4b6fSAnirudh Venkataramanan mdelay(delay); 1583f31e4b6fSAnirudh Venkataramanan timeout = (timeout > delay) ? timeout - delay : 0; 1584f31e4b6fSAnirudh Venkataramanan status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 1585f31e4b6fSAnirudh Venkataramanan 1586ff2b1321SDan Nowlin if (status == ICE_ERR_AQ_NO_WORK) 1587f31e4b6fSAnirudh Venkataramanan /* lock free, but no work to do */ 1588f31e4b6fSAnirudh Venkataramanan break; 1589f31e4b6fSAnirudh Venkataramanan 1590f31e4b6fSAnirudh Venkataramanan if (!status) 1591f31e4b6fSAnirudh Venkataramanan /* lock acquired */ 1592f31e4b6fSAnirudh Venkataramanan break; 1593f31e4b6fSAnirudh Venkataramanan } 1594f31e4b6fSAnirudh Venkataramanan if (status && status != ICE_ERR_AQ_NO_WORK) 1595f31e4b6fSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 1596f31e4b6fSAnirudh Venkataramanan 1597f31e4b6fSAnirudh Venkataramanan ice_acquire_res_exit: 1598f31e4b6fSAnirudh Venkataramanan if (status == ICE_ERR_AQ_NO_WORK) { 1599f31e4b6fSAnirudh Venkataramanan if (access == ICE_RES_WRITE) 16009228d8b2SJacob Keller ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 1601f31e4b6fSAnirudh Venkataramanan else 16029228d8b2SJacob Keller ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 1603f31e4b6fSAnirudh Venkataramanan } 1604f31e4b6fSAnirudh Venkataramanan return status; 1605f31e4b6fSAnirudh Venkataramanan } 1606f31e4b6fSAnirudh Venkataramanan 1607f31e4b6fSAnirudh Venkataramanan /** 1608f31e4b6fSAnirudh Venkataramanan * ice_release_res 1609f31e4b6fSAnirudh Venkataramanan * @hw: pointer to the HW structure 1610f9867df6SAnirudh Venkataramanan * @res: resource ID 1611f31e4b6fSAnirudh Venkataramanan * 1612f31e4b6fSAnirudh Venkataramanan * This function will release a resource using the proper Admin Command. 1613f31e4b6fSAnirudh Venkataramanan */ 1614f31e4b6fSAnirudh Venkataramanan void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 1615f31e4b6fSAnirudh Venkataramanan { 1616f31e4b6fSAnirudh Venkataramanan enum ice_status status; 1617f31e4b6fSAnirudh Venkataramanan u32 total_delay = 0; 1618f31e4b6fSAnirudh Venkataramanan 1619f31e4b6fSAnirudh Venkataramanan status = ice_aq_release_res(hw, res, 0, NULL); 1620f31e4b6fSAnirudh Venkataramanan 1621f31e4b6fSAnirudh Venkataramanan /* there are some rare cases when trying to release the resource 1622f9867df6SAnirudh Venkataramanan * results in an admin queue timeout, so handle them correctly 1623f31e4b6fSAnirudh Venkataramanan */ 1624f31e4b6fSAnirudh Venkataramanan while ((status == ICE_ERR_AQ_TIMEOUT) && 1625f31e4b6fSAnirudh Venkataramanan (total_delay < hw->adminq.sq_cmd_timeout)) { 1626f31e4b6fSAnirudh Venkataramanan mdelay(1); 1627f31e4b6fSAnirudh Venkataramanan status = ice_aq_release_res(hw, res, 0, NULL); 1628f31e4b6fSAnirudh Venkataramanan total_delay++; 1629f31e4b6fSAnirudh Venkataramanan } 1630f31e4b6fSAnirudh Venkataramanan } 1631f31e4b6fSAnirudh Venkataramanan 1632f31e4b6fSAnirudh Venkataramanan /** 163331ad4e4eSTony Nguyen * ice_aq_alloc_free_res - command to allocate/free resources 163431ad4e4eSTony Nguyen * @hw: pointer to the HW struct 163531ad4e4eSTony Nguyen * @num_entries: number of resource entries in buffer 163631ad4e4eSTony Nguyen * @buf: Indirect buffer to hold data parameters and response 163731ad4e4eSTony Nguyen * @buf_size: size of buffer for indirect commands 163831ad4e4eSTony Nguyen * @opc: pass in the command opcode 163931ad4e4eSTony Nguyen * @cd: pointer to command details structure or NULL 164031ad4e4eSTony Nguyen * 164131ad4e4eSTony Nguyen * Helper function to allocate/free resources using the admin queue commands 164231ad4e4eSTony Nguyen */ 164331ad4e4eSTony Nguyen enum ice_status 164431ad4e4eSTony Nguyen ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 164531ad4e4eSTony Nguyen struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 164631ad4e4eSTony Nguyen enum ice_adminq_opc opc, struct ice_sq_cd *cd) 164731ad4e4eSTony Nguyen { 164831ad4e4eSTony Nguyen struct ice_aqc_alloc_free_res_cmd *cmd; 164931ad4e4eSTony Nguyen struct ice_aq_desc desc; 165031ad4e4eSTony Nguyen 165131ad4e4eSTony Nguyen cmd = &desc.params.sw_res_ctrl; 165231ad4e4eSTony Nguyen 165331ad4e4eSTony Nguyen if (!buf) 165431ad4e4eSTony Nguyen return ICE_ERR_PARAM; 165531ad4e4eSTony Nguyen 165611404310SBruce Allan if (buf_size < flex_array_size(buf, elem, num_entries)) 165731ad4e4eSTony Nguyen return ICE_ERR_PARAM; 165831ad4e4eSTony Nguyen 165931ad4e4eSTony Nguyen ice_fill_dflt_direct_cmd_desc(&desc, opc); 166031ad4e4eSTony Nguyen 166131ad4e4eSTony Nguyen desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 166231ad4e4eSTony Nguyen 166331ad4e4eSTony Nguyen cmd->num_entries = cpu_to_le16(num_entries); 166431ad4e4eSTony Nguyen 166531ad4e4eSTony Nguyen return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 166631ad4e4eSTony Nguyen } 166731ad4e4eSTony Nguyen 166831ad4e4eSTony Nguyen /** 166931ad4e4eSTony Nguyen * ice_alloc_hw_res - allocate resource 167031ad4e4eSTony Nguyen * @hw: pointer to the HW struct 167131ad4e4eSTony Nguyen * @type: type of resource 167231ad4e4eSTony Nguyen * @num: number of resources to allocate 167331ad4e4eSTony Nguyen * @btm: allocate from bottom 167431ad4e4eSTony Nguyen * @res: pointer to array that will receive the resources 167531ad4e4eSTony Nguyen */ 167631ad4e4eSTony Nguyen enum ice_status 167731ad4e4eSTony Nguyen ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 167831ad4e4eSTony Nguyen { 167931ad4e4eSTony Nguyen struct ice_aqc_alloc_free_res_elem *buf; 168031ad4e4eSTony Nguyen enum ice_status status; 168131ad4e4eSTony Nguyen u16 buf_len; 168231ad4e4eSTony Nguyen 168366486d89SBruce Allan buf_len = struct_size(buf, elem, num); 168431ad4e4eSTony Nguyen buf = kzalloc(buf_len, GFP_KERNEL); 168531ad4e4eSTony Nguyen if (!buf) 168631ad4e4eSTony Nguyen return ICE_ERR_NO_MEMORY; 168731ad4e4eSTony Nguyen 168831ad4e4eSTony Nguyen /* Prepare buffer to allocate resource. */ 168931ad4e4eSTony Nguyen buf->num_elems = cpu_to_le16(num); 169031ad4e4eSTony Nguyen buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 169131ad4e4eSTony Nguyen ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 169231ad4e4eSTony Nguyen if (btm) 169331ad4e4eSTony Nguyen buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 169431ad4e4eSTony Nguyen 169531ad4e4eSTony Nguyen status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 169631ad4e4eSTony Nguyen ice_aqc_opc_alloc_res, NULL); 169731ad4e4eSTony Nguyen if (status) 169831ad4e4eSTony Nguyen goto ice_alloc_res_exit; 169931ad4e4eSTony Nguyen 170066486d89SBruce Allan memcpy(res, buf->elem, sizeof(*buf->elem) * num); 170131ad4e4eSTony Nguyen 170231ad4e4eSTony Nguyen ice_alloc_res_exit: 170331ad4e4eSTony Nguyen kfree(buf); 170431ad4e4eSTony Nguyen return status; 170531ad4e4eSTony Nguyen } 170631ad4e4eSTony Nguyen 170731ad4e4eSTony Nguyen /** 1708451f2c44STony Nguyen * ice_free_hw_res - free allocated HW resource 1709451f2c44STony Nguyen * @hw: pointer to the HW struct 1710451f2c44STony Nguyen * @type: type of resource to free 1711451f2c44STony Nguyen * @num: number of resources 1712451f2c44STony Nguyen * @res: pointer to array that contains the resources to free 1713451f2c44STony Nguyen */ 17147dbc63f0STony Nguyen enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 1715451f2c44STony Nguyen { 1716451f2c44STony Nguyen struct ice_aqc_alloc_free_res_elem *buf; 1717451f2c44STony Nguyen enum ice_status status; 1718451f2c44STony Nguyen u16 buf_len; 1719451f2c44STony Nguyen 172066486d89SBruce Allan buf_len = struct_size(buf, elem, num); 1721451f2c44STony Nguyen buf = kzalloc(buf_len, GFP_KERNEL); 1722451f2c44STony Nguyen if (!buf) 1723451f2c44STony Nguyen return ICE_ERR_NO_MEMORY; 1724451f2c44STony Nguyen 1725451f2c44STony Nguyen /* Prepare buffer to free resource. */ 1726451f2c44STony Nguyen buf->num_elems = cpu_to_le16(num); 1727451f2c44STony Nguyen buf->res_type = cpu_to_le16(type); 172866486d89SBruce Allan memcpy(buf->elem, res, sizeof(*buf->elem) * num); 1729451f2c44STony Nguyen 1730451f2c44STony Nguyen status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 1731451f2c44STony Nguyen ice_aqc_opc_free_res, NULL); 1732451f2c44STony Nguyen if (status) 1733451f2c44STony Nguyen ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 1734451f2c44STony Nguyen 1735451f2c44STony Nguyen kfree(buf); 1736451f2c44STony Nguyen return status; 1737451f2c44STony Nguyen } 1738451f2c44STony Nguyen 1739451f2c44STony Nguyen /** 17407a1f7111SBrett Creeley * ice_get_num_per_func - determine number of resources per PF 1741f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW structure 17427a1f7111SBrett Creeley * @max: value to be evenly split between each PF 1743995c90f2SAnirudh Venkataramanan * 1744995c90f2SAnirudh Venkataramanan * Determine the number of valid functions by going through the bitmap returned 17457a1f7111SBrett Creeley * from parsing capabilities and use this to calculate the number of resources 17467a1f7111SBrett Creeley * per PF based on the max value passed in. 1747995c90f2SAnirudh Venkataramanan */ 17487a1f7111SBrett Creeley static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 1749995c90f2SAnirudh Venkataramanan { 1750995c90f2SAnirudh Venkataramanan u8 funcs; 1751995c90f2SAnirudh Venkataramanan 1752995c90f2SAnirudh Venkataramanan #define ICE_CAPS_VALID_FUNCS_M 0xFF 1753995c90f2SAnirudh Venkataramanan funcs = hweight8(hw->dev_caps.common_cap.valid_functions & 1754995c90f2SAnirudh Venkataramanan ICE_CAPS_VALID_FUNCS_M); 1755995c90f2SAnirudh Venkataramanan 1756995c90f2SAnirudh Venkataramanan if (!funcs) 1757995c90f2SAnirudh Venkataramanan return 0; 1758995c90f2SAnirudh Venkataramanan 17597a1f7111SBrett Creeley return max / funcs; 1760995c90f2SAnirudh Venkataramanan } 1761995c90f2SAnirudh Venkataramanan 1762995c90f2SAnirudh Venkataramanan /** 1763595b13e2SJacob Keller * ice_parse_common_caps - parse common device/function capabilities 1764f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 1765595b13e2SJacob Keller * @caps: pointer to common capabilities structure 1766595b13e2SJacob Keller * @elem: the capability element to parse 1767595b13e2SJacob Keller * @prefix: message prefix for tracing capabilities 17689c20346bSAnirudh Venkataramanan * 1769595b13e2SJacob Keller * Given a capability element, extract relevant details into the common 1770595b13e2SJacob Keller * capability structure. 1771595b13e2SJacob Keller * 1772595b13e2SJacob Keller * Returns: true if the capability matches one of the common capability ids, 1773595b13e2SJacob Keller * false otherwise. 17749c20346bSAnirudh Venkataramanan */ 1775595b13e2SJacob Keller static bool 1776595b13e2SJacob Keller ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1777595b13e2SJacob Keller struct ice_aqc_list_caps_elem *elem, const char *prefix) 17789c20346bSAnirudh Venkataramanan { 1779595b13e2SJacob Keller u32 logical_id = le32_to_cpu(elem->logical_id); 1780595b13e2SJacob Keller u32 phys_id = le32_to_cpu(elem->phys_id); 1781595b13e2SJacob Keller u32 number = le32_to_cpu(elem->number); 1782595b13e2SJacob Keller u16 cap = le16_to_cpu(elem->cap); 1783595b13e2SJacob Keller bool found = true; 17849c20346bSAnirudh Venkataramanan 17859c20346bSAnirudh Venkataramanan switch (cap) { 1786995c90f2SAnirudh Venkataramanan case ICE_AQC_CAPS_VALID_FUNCTIONS: 1787995c90f2SAnirudh Venkataramanan caps->valid_functions = number; 17889228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 1789995c90f2SAnirudh Venkataramanan caps->valid_functions); 1790995c90f2SAnirudh Venkataramanan break; 179175d2b253SAnirudh Venkataramanan case ICE_AQC_CAPS_SRIOV: 179275d2b253SAnirudh Venkataramanan caps->sr_iov_1_1 = (number == 1); 17939228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 1794a84db525SAnirudh Venkataramanan caps->sr_iov_1_1); 179575d2b253SAnirudh Venkataramanan break; 1796a257f188SUsha Ketineni case ICE_AQC_CAPS_DCB: 1797a257f188SUsha Ketineni caps->dcb = (number == 1); 1798a257f188SUsha Ketineni caps->active_tc_bitmap = logical_id; 1799a257f188SUsha Ketineni caps->maxtc = phys_id; 18009228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 18019228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 1802a257f188SUsha Ketineni caps->active_tc_bitmap); 18039228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 1804a257f188SUsha Ketineni break; 18059c20346bSAnirudh Venkataramanan case ICE_AQC_CAPS_RSS: 18069c20346bSAnirudh Venkataramanan caps->rss_table_size = number; 18079c20346bSAnirudh Venkataramanan caps->rss_table_entry_width = logical_id; 18089228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 18099c20346bSAnirudh Venkataramanan caps->rss_table_size); 18109228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 18119c20346bSAnirudh Venkataramanan caps->rss_table_entry_width); 18129c20346bSAnirudh Venkataramanan break; 18139c20346bSAnirudh Venkataramanan case ICE_AQC_CAPS_RXQS: 18149c20346bSAnirudh Venkataramanan caps->num_rxq = number; 18159c20346bSAnirudh Venkataramanan caps->rxq_first_id = phys_id; 18169228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 1817a84db525SAnirudh Venkataramanan caps->num_rxq); 18189228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 18199c20346bSAnirudh Venkataramanan caps->rxq_first_id); 18209c20346bSAnirudh Venkataramanan break; 18219c20346bSAnirudh Venkataramanan case ICE_AQC_CAPS_TXQS: 18229c20346bSAnirudh Venkataramanan caps->num_txq = number; 18239c20346bSAnirudh Venkataramanan caps->txq_first_id = phys_id; 18249228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 1825a84db525SAnirudh Venkataramanan caps->num_txq); 18269228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 18279c20346bSAnirudh Venkataramanan caps->txq_first_id); 18289c20346bSAnirudh Venkataramanan break; 18299c20346bSAnirudh Venkataramanan case ICE_AQC_CAPS_MSIX: 18309c20346bSAnirudh Venkataramanan caps->num_msix_vectors = number; 18319c20346bSAnirudh Venkataramanan caps->msix_vector_first_id = phys_id; 18329228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 18339c20346bSAnirudh Venkataramanan caps->num_msix_vectors); 18349228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 18359c20346bSAnirudh Venkataramanan caps->msix_vector_first_id); 18369c20346bSAnirudh Venkataramanan break; 18372ab560a7SJacob Keller case ICE_AQC_CAPS_PENDING_NVM_VER: 18382ab560a7SJacob Keller caps->nvm_update_pending_nvm = true; 18392ab560a7SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix); 18402ab560a7SJacob Keller break; 18412ab560a7SJacob Keller case ICE_AQC_CAPS_PENDING_OROM_VER: 18422ab560a7SJacob Keller caps->nvm_update_pending_orom = true; 18432ab560a7SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix); 18442ab560a7SJacob Keller break; 18452ab560a7SJacob Keller case ICE_AQC_CAPS_PENDING_NET_VER: 18462ab560a7SJacob Keller caps->nvm_update_pending_netlist = true; 18472ab560a7SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix); 18482ab560a7SJacob Keller break; 1849de9b277eSJacek Naczyk case ICE_AQC_CAPS_NVM_MGMT: 1850de9b277eSJacek Naczyk caps->nvm_unified_update = 1851de9b277eSJacek Naczyk (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 1852de9b277eSJacek Naczyk true : false; 1853de9b277eSJacek Naczyk ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 1854de9b277eSJacek Naczyk caps->nvm_unified_update); 1855de9b277eSJacek Naczyk break; 1856595b13e2SJacob Keller case ICE_AQC_CAPS_MAX_MTU: 1857595b13e2SJacob Keller caps->max_mtu = number; 1858595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 1859595b13e2SJacob Keller prefix, caps->max_mtu); 1860595b13e2SJacob Keller break; 1861595b13e2SJacob Keller default: 1862595b13e2SJacob Keller /* Not one of the recognized common capabilities */ 1863595b13e2SJacob Keller found = false; 1864148beb61SHenry Tieman } 1865595b13e2SJacob Keller 1866595b13e2SJacob Keller return found; 1867595b13e2SJacob Keller } 1868595b13e2SJacob Keller 1869595b13e2SJacob Keller /** 1870595b13e2SJacob Keller * ice_recalc_port_limited_caps - Recalculate port limited capabilities 1871595b13e2SJacob Keller * @hw: pointer to the HW structure 1872595b13e2SJacob Keller * @caps: pointer to capabilities structure to fix 1873595b13e2SJacob Keller * 1874595b13e2SJacob Keller * Re-calculate the capabilities that are dependent on the number of physical 1875595b13e2SJacob Keller * ports; i.e. some features are not supported or function differently on 1876595b13e2SJacob Keller * devices with more than 4 ports. 1877595b13e2SJacob Keller */ 1878595b13e2SJacob Keller static void 1879595b13e2SJacob Keller ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 1880595b13e2SJacob Keller { 1881595b13e2SJacob Keller /* This assumes device capabilities are always scanned before function 1882595b13e2SJacob Keller * capabilities during the initialization flow. 1883595b13e2SJacob Keller */ 1884595b13e2SJacob Keller if (hw->dev_caps.num_funcs > 4) { 1885595b13e2SJacob Keller /* Max 4 TCs per port */ 1886595b13e2SJacob Keller caps->maxtc = 4; 18879228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 1888595b13e2SJacob Keller caps->maxtc); 1889595b13e2SJacob Keller } 1890595b13e2SJacob Keller } 1891595b13e2SJacob Keller 1892595b13e2SJacob Keller /** 1893595b13e2SJacob Keller * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 1894595b13e2SJacob Keller * @hw: pointer to the HW struct 1895595b13e2SJacob Keller * @func_p: pointer to function capabilities structure 1896595b13e2SJacob Keller * @cap: pointer to the capability element to parse 1897595b13e2SJacob Keller * 1898595b13e2SJacob Keller * Extract function capabilities for ICE_AQC_CAPS_VF. 1899595b13e2SJacob Keller */ 1900595b13e2SJacob Keller static void 1901595b13e2SJacob Keller ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 1902595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap) 1903595b13e2SJacob Keller { 1904595b13e2SJacob Keller u32 logical_id = le32_to_cpu(cap->logical_id); 1905595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number); 1906595b13e2SJacob Keller 1907595b13e2SJacob Keller func_p->num_allocd_vfs = number; 1908595b13e2SJacob Keller func_p->vf_base_id = logical_id; 1909595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 1910595b13e2SJacob Keller func_p->num_allocd_vfs); 1911595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 1912595b13e2SJacob Keller func_p->vf_base_id); 1913595b13e2SJacob Keller } 1914595b13e2SJacob Keller 1915595b13e2SJacob Keller /** 1916595b13e2SJacob Keller * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 1917595b13e2SJacob Keller * @hw: pointer to the HW struct 1918595b13e2SJacob Keller * @func_p: pointer to function capabilities structure 1919595b13e2SJacob Keller * @cap: pointer to the capability element to parse 1920595b13e2SJacob Keller * 1921595b13e2SJacob Keller * Extract function capabilities for ICE_AQC_CAPS_VSI. 1922595b13e2SJacob Keller */ 1923595b13e2SJacob Keller static void 1924595b13e2SJacob Keller ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 1925595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap) 1926595b13e2SJacob Keller { 1927595b13e2SJacob Keller func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 1928595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 1929595b13e2SJacob Keller le32_to_cpu(cap->number)); 1930595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 1931595b13e2SJacob Keller func_p->guar_num_vsi); 1932595b13e2SJacob Keller } 1933595b13e2SJacob Keller 1934595b13e2SJacob Keller /** 1935595b13e2SJacob Keller * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps 1936595b13e2SJacob Keller * @hw: pointer to the HW struct 1937595b13e2SJacob Keller * @func_p: pointer to function capabilities structure 1938595b13e2SJacob Keller * 1939595b13e2SJacob Keller * Extract function capabilities for ICE_AQC_CAPS_FD. 1940595b13e2SJacob Keller */ 1941595b13e2SJacob Keller static void 1942595b13e2SJacob Keller ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p) 1943595b13e2SJacob Keller { 1944148beb61SHenry Tieman u32 reg_val, val; 1945148beb61SHenry Tieman 1946148beb61SHenry Tieman reg_val = rd32(hw, GLQF_FD_SIZE); 1947148beb61SHenry Tieman val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> 1948148beb61SHenry Tieman GLQF_FD_SIZE_FD_GSIZE_S; 1949148beb61SHenry Tieman func_p->fd_fltr_guar = 1950148beb61SHenry Tieman ice_get_num_per_func(hw, val); 1951148beb61SHenry Tieman val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >> 1952148beb61SHenry Tieman GLQF_FD_SIZE_FD_BSIZE_S; 1953148beb61SHenry Tieman func_p->fd_fltr_best_effort = val; 1954595b13e2SJacob Keller 19559228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_guar = %d\n", 1956595b13e2SJacob Keller func_p->fd_fltr_guar); 19579228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: fd_fltr_best_effort = %d\n", 1958595b13e2SJacob Keller func_p->fd_fltr_best_effort); 1959148beb61SHenry Tieman } 1960595b13e2SJacob Keller 1961595b13e2SJacob Keller /** 1962595b13e2SJacob Keller * ice_parse_func_caps - Parse function capabilities 1963595b13e2SJacob Keller * @hw: pointer to the HW struct 1964595b13e2SJacob Keller * @func_p: pointer to function capabilities structure 1965595b13e2SJacob Keller * @buf: buffer containing the function capability records 1966595b13e2SJacob Keller * @cap_count: the number of capabilities 1967595b13e2SJacob Keller * 1968595b13e2SJacob Keller * Helper function to parse function (0x000A) capabilities list. For 1969595b13e2SJacob Keller * capabilities shared between device and function, this relies on 1970595b13e2SJacob Keller * ice_parse_common_caps. 1971595b13e2SJacob Keller * 1972595b13e2SJacob Keller * Loop through the list of provided capabilities and extract the relevant 1973595b13e2SJacob Keller * data into the function capabilities structured. 1974595b13e2SJacob Keller */ 1975595b13e2SJacob Keller static void 1976595b13e2SJacob Keller ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 1977595b13e2SJacob Keller void *buf, u32 cap_count) 1978595b13e2SJacob Keller { 1979595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap_resp; 1980595b13e2SJacob Keller u32 i; 1981595b13e2SJacob Keller 1982595b13e2SJacob Keller cap_resp = (struct ice_aqc_list_caps_elem *)buf; 1983595b13e2SJacob Keller 1984595b13e2SJacob Keller memset(func_p, 0, sizeof(*func_p)); 1985595b13e2SJacob Keller 1986595b13e2SJacob Keller for (i = 0; i < cap_count; i++) { 1987595b13e2SJacob Keller u16 cap = le16_to_cpu(cap_resp[i].cap); 1988595b13e2SJacob Keller bool found; 1989595b13e2SJacob Keller 1990595b13e2SJacob Keller found = ice_parse_common_caps(hw, &func_p->common_cap, 1991595b13e2SJacob Keller &cap_resp[i], "func caps"); 1992595b13e2SJacob Keller 1993595b13e2SJacob Keller switch (cap) { 1994595b13e2SJacob Keller case ICE_AQC_CAPS_VF: 1995595b13e2SJacob Keller ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 1996148beb61SHenry Tieman break; 1997595b13e2SJacob Keller case ICE_AQC_CAPS_VSI: 1998595b13e2SJacob Keller ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 1999595b13e2SJacob Keller break; 2000595b13e2SJacob Keller case ICE_AQC_CAPS_FD: 2001595b13e2SJacob Keller ice_parse_fdir_func_caps(hw, func_p); 20029c20346bSAnirudh Venkataramanan break; 20039c20346bSAnirudh Venkataramanan default: 2004595b13e2SJacob Keller /* Don't list common capabilities as unknown */ 2005595b13e2SJacob Keller if (!found) 20069228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 2007a84db525SAnirudh Venkataramanan i, cap); 20089c20346bSAnirudh Venkataramanan break; 20099c20346bSAnirudh Venkataramanan } 20109c20346bSAnirudh Venkataramanan } 20119164f761SBruce Allan 2012595b13e2SJacob Keller ice_recalc_port_limited_caps(hw, &func_p->common_cap); 20139164f761SBruce Allan } 2014595b13e2SJacob Keller 2015595b13e2SJacob Keller /** 2016595b13e2SJacob Keller * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 2017595b13e2SJacob Keller * @hw: pointer to the HW struct 2018595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure 2019595b13e2SJacob Keller * @cap: capability element to parse 2020595b13e2SJacob Keller * 2021595b13e2SJacob Keller * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 2022595b13e2SJacob Keller */ 2023595b13e2SJacob Keller static void 2024595b13e2SJacob Keller ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2025595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap) 2026595b13e2SJacob Keller { 2027595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number); 2028595b13e2SJacob Keller 2029595b13e2SJacob Keller dev_p->num_funcs = hweight32(number); 2030595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 2031595b13e2SJacob Keller dev_p->num_funcs); 2032595b13e2SJacob Keller } 2033595b13e2SJacob Keller 2034595b13e2SJacob Keller /** 2035595b13e2SJacob Keller * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 2036595b13e2SJacob Keller * @hw: pointer to the HW struct 2037595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure 2038595b13e2SJacob Keller * @cap: capability element to parse 2039595b13e2SJacob Keller * 2040595b13e2SJacob Keller * Parse ICE_AQC_CAPS_VF for device capabilities. 2041595b13e2SJacob Keller */ 2042595b13e2SJacob Keller static void 2043595b13e2SJacob Keller ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2044595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap) 2045595b13e2SJacob Keller { 2046595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number); 2047595b13e2SJacob Keller 2048595b13e2SJacob Keller dev_p->num_vfs_exposed = number; 2049595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 2050595b13e2SJacob Keller dev_p->num_vfs_exposed); 2051595b13e2SJacob Keller } 2052595b13e2SJacob Keller 2053595b13e2SJacob Keller /** 2054595b13e2SJacob Keller * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 2055595b13e2SJacob Keller * @hw: pointer to the HW struct 2056595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure 2057595b13e2SJacob Keller * @cap: capability element to parse 2058595b13e2SJacob Keller * 2059595b13e2SJacob Keller * Parse ICE_AQC_CAPS_VSI for device capabilities. 2060595b13e2SJacob Keller */ 2061595b13e2SJacob Keller static void 2062595b13e2SJacob Keller ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2063595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap) 2064595b13e2SJacob Keller { 2065595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number); 2066595b13e2SJacob Keller 2067595b13e2SJacob Keller dev_p->num_vsi_allocd_to_host = number; 2068595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 2069595b13e2SJacob Keller dev_p->num_vsi_allocd_to_host); 2070595b13e2SJacob Keller } 2071595b13e2SJacob Keller 2072595b13e2SJacob Keller /** 2073595b13e2SJacob Keller * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps 2074595b13e2SJacob Keller * @hw: pointer to the HW struct 2075595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure 2076595b13e2SJacob Keller * @cap: capability element to parse 2077595b13e2SJacob Keller * 2078595b13e2SJacob Keller * Parse ICE_AQC_CAPS_FD for device capabilities. 2079595b13e2SJacob Keller */ 2080595b13e2SJacob Keller static void 2081595b13e2SJacob Keller ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2082595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap) 2083595b13e2SJacob Keller { 2084595b13e2SJacob Keller u32 number = le32_to_cpu(cap->number); 2085595b13e2SJacob Keller 2086595b13e2SJacob Keller dev_p->num_flow_director_fltr = number; 2087595b13e2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n", 2088595b13e2SJacob Keller dev_p->num_flow_director_fltr); 2089595b13e2SJacob Keller } 2090595b13e2SJacob Keller 2091595b13e2SJacob Keller /** 2092595b13e2SJacob Keller * ice_parse_dev_caps - Parse device capabilities 2093595b13e2SJacob Keller * @hw: pointer to the HW struct 2094595b13e2SJacob Keller * @dev_p: pointer to device capabilities structure 2095595b13e2SJacob Keller * @buf: buffer containing the device capability records 2096595b13e2SJacob Keller * @cap_count: the number of capabilities 2097595b13e2SJacob Keller * 2098595b13e2SJacob Keller * Helper device to parse device (0x000B) capabilities list. For 20997dbc63f0STony Nguyen * capabilities shared between device and function, this relies on 2100595b13e2SJacob Keller * ice_parse_common_caps. 2101595b13e2SJacob Keller * 2102595b13e2SJacob Keller * Loop through the list of provided capabilities and extract the relevant 2103595b13e2SJacob Keller * data into the device capabilities structured. 2104595b13e2SJacob Keller */ 2105595b13e2SJacob Keller static void 2106595b13e2SJacob Keller ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 2107595b13e2SJacob Keller void *buf, u32 cap_count) 2108595b13e2SJacob Keller { 2109595b13e2SJacob Keller struct ice_aqc_list_caps_elem *cap_resp; 2110595b13e2SJacob Keller u32 i; 2111595b13e2SJacob Keller 2112595b13e2SJacob Keller cap_resp = (struct ice_aqc_list_caps_elem *)buf; 2113595b13e2SJacob Keller 2114595b13e2SJacob Keller memset(dev_p, 0, sizeof(*dev_p)); 2115595b13e2SJacob Keller 2116595b13e2SJacob Keller for (i = 0; i < cap_count; i++) { 2117595b13e2SJacob Keller u16 cap = le16_to_cpu(cap_resp[i].cap); 2118595b13e2SJacob Keller bool found; 2119595b13e2SJacob Keller 2120595b13e2SJacob Keller found = ice_parse_common_caps(hw, &dev_p->common_cap, 2121595b13e2SJacob Keller &cap_resp[i], "dev caps"); 2122595b13e2SJacob Keller 2123595b13e2SJacob Keller switch (cap) { 2124595b13e2SJacob Keller case ICE_AQC_CAPS_VALID_FUNCTIONS: 2125595b13e2SJacob Keller ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 2126595b13e2SJacob Keller break; 2127595b13e2SJacob Keller case ICE_AQC_CAPS_VF: 2128595b13e2SJacob Keller ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 2129595b13e2SJacob Keller break; 2130595b13e2SJacob Keller case ICE_AQC_CAPS_VSI: 2131595b13e2SJacob Keller ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 2132595b13e2SJacob Keller break; 2133595b13e2SJacob Keller case ICE_AQC_CAPS_FD: 2134595b13e2SJacob Keller ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]); 2135595b13e2SJacob Keller break; 2136595b13e2SJacob Keller default: 2137595b13e2SJacob Keller /* Don't list common capabilities as unknown */ 2138595b13e2SJacob Keller if (!found) 21399228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 2140595b13e2SJacob Keller i, cap); 2141595b13e2SJacob Keller break; 2142595b13e2SJacob Keller } 2143595b13e2SJacob Keller } 2144595b13e2SJacob Keller 2145595b13e2SJacob Keller ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 2146595b13e2SJacob Keller } 2147595b13e2SJacob Keller 2148595b13e2SJacob Keller /** 21498d7aab35SJacob Keller * ice_aq_list_caps - query function/device capabilities 2150f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 21518d7aab35SJacob Keller * @buf: a buffer to hold the capabilities 21528d7aab35SJacob Keller * @buf_size: size of the buffer 21538d7aab35SJacob Keller * @cap_count: if not NULL, set to the number of capabilities reported 21548d7aab35SJacob Keller * @opc: capabilities type to discover, device or function 21559c20346bSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 21569c20346bSAnirudh Venkataramanan * 21578d7aab35SJacob Keller * Get the function (0x000A) or device (0x000B) capabilities description from 21588d7aab35SJacob Keller * firmware and store it in the buffer. 21598d7aab35SJacob Keller * 21608d7aab35SJacob Keller * If the cap_count pointer is not NULL, then it is set to the number of 21618d7aab35SJacob Keller * capabilities firmware will report. Note that if the buffer size is too 21628d7aab35SJacob Keller * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 21638d7aab35SJacob Keller * cap_count will still be updated in this case. It is recommended that the 21648d7aab35SJacob Keller * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 21658d7aab35SJacob Keller * firmware could return) to avoid this. 21669c20346bSAnirudh Venkataramanan */ 21678d7aab35SJacob Keller enum ice_status 21688d7aab35SJacob Keller ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 21699c20346bSAnirudh Venkataramanan enum ice_adminq_opc opc, struct ice_sq_cd *cd) 21709c20346bSAnirudh Venkataramanan { 21719c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps *cmd; 21729c20346bSAnirudh Venkataramanan struct ice_aq_desc desc; 21739c20346bSAnirudh Venkataramanan enum ice_status status; 21749c20346bSAnirudh Venkataramanan 21759c20346bSAnirudh Venkataramanan cmd = &desc.params.get_cap; 21769c20346bSAnirudh Venkataramanan 21779c20346bSAnirudh Venkataramanan if (opc != ice_aqc_opc_list_func_caps && 21789c20346bSAnirudh Venkataramanan opc != ice_aqc_opc_list_dev_caps) 21799c20346bSAnirudh Venkataramanan return ICE_ERR_PARAM; 21809c20346bSAnirudh Venkataramanan 21819c20346bSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, opc); 21829c20346bSAnirudh Venkataramanan status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 21838d7aab35SJacob Keller 21848d7aab35SJacob Keller if (cap_count) 218599189e8bSAnirudh Venkataramanan *cap_count = le32_to_cpu(cmd->count); 21868d7aab35SJacob Keller 21878d7aab35SJacob Keller return status; 21888d7aab35SJacob Keller } 21898d7aab35SJacob Keller 21908d7aab35SJacob Keller /** 219181aed647SJacob Keller * ice_discover_dev_caps - Read and extract device capabilities 21927d86cf38SAnirudh Venkataramanan * @hw: pointer to the hardware structure 219381aed647SJacob Keller * @dev_caps: pointer to device capabilities structure 219481aed647SJacob Keller * 219581aed647SJacob Keller * Read the device capabilities and extract them into the dev_caps structure 219681aed647SJacob Keller * for later use. 21977d86cf38SAnirudh Venkataramanan */ 2198d69ea414SJacob Keller enum ice_status 219981aed647SJacob Keller ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 22007d86cf38SAnirudh Venkataramanan { 22017d86cf38SAnirudh Venkataramanan enum ice_status status; 220281aed647SJacob Keller u32 cap_count = 0; 22037d86cf38SAnirudh Venkataramanan void *cbuf; 22047d86cf38SAnirudh Venkataramanan 22051082b360SJacob Keller cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 22067d86cf38SAnirudh Venkataramanan if (!cbuf) 22077d86cf38SAnirudh Venkataramanan return ICE_ERR_NO_MEMORY; 22087d86cf38SAnirudh Venkataramanan 22091082b360SJacob Keller /* Although the driver doesn't know the number of capabilities the 22101082b360SJacob Keller * device will return, we can simply send a 4KB buffer, the maximum 22111082b360SJacob Keller * possible size that firmware can return. 22121082b360SJacob Keller */ 22131082b360SJacob Keller cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 22141082b360SJacob Keller 221581aed647SJacob Keller status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 221681aed647SJacob Keller ice_aqc_opc_list_dev_caps, NULL); 221781aed647SJacob Keller if (!status) 221881aed647SJacob Keller ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 221981aed647SJacob Keller kfree(cbuf); 222081aed647SJacob Keller 222181aed647SJacob Keller return status; 222281aed647SJacob Keller } 222381aed647SJacob Keller 222481aed647SJacob Keller /** 222581aed647SJacob Keller * ice_discover_func_caps - Read and extract function capabilities 222681aed647SJacob Keller * @hw: pointer to the hardware structure 222781aed647SJacob Keller * @func_caps: pointer to function capabilities structure 222881aed647SJacob Keller * 222981aed647SJacob Keller * Read the function capabilities and extract them into the func_caps structure 223081aed647SJacob Keller * for later use. 223181aed647SJacob Keller */ 223281aed647SJacob Keller static enum ice_status 223381aed647SJacob Keller ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 223481aed647SJacob Keller { 223581aed647SJacob Keller enum ice_status status; 223681aed647SJacob Keller u32 cap_count = 0; 223781aed647SJacob Keller void *cbuf; 223881aed647SJacob Keller 223981aed647SJacob Keller cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL); 224081aed647SJacob Keller if (!cbuf) 224181aed647SJacob Keller return ICE_ERR_NO_MEMORY; 224281aed647SJacob Keller 224381aed647SJacob Keller /* Although the driver doesn't know the number of capabilities the 224481aed647SJacob Keller * device will return, we can simply send a 4KB buffer, the maximum 224581aed647SJacob Keller * possible size that firmware can return. 224681aed647SJacob Keller */ 224781aed647SJacob Keller cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 224881aed647SJacob Keller 224981aed647SJacob Keller status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 225081aed647SJacob Keller ice_aqc_opc_list_func_caps, NULL); 225181aed647SJacob Keller if (!status) 225281aed647SJacob Keller ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 22531082b360SJacob Keller kfree(cbuf); 22549c20346bSAnirudh Venkataramanan 22559c20346bSAnirudh Venkataramanan return status; 22569c20346bSAnirudh Venkataramanan } 22579c20346bSAnirudh Venkataramanan 22589c20346bSAnirudh Venkataramanan /** 2259462acf6aSTony Nguyen * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 2260462acf6aSTony Nguyen * @hw: pointer to the hardware structure 2261462acf6aSTony Nguyen */ 2262462acf6aSTony Nguyen void ice_set_safe_mode_caps(struct ice_hw *hw) 2263462acf6aSTony Nguyen { 2264462acf6aSTony Nguyen struct ice_hw_func_caps *func_caps = &hw->func_caps; 2265462acf6aSTony Nguyen struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2266be49b1adSJacob Keller struct ice_hw_common_caps cached_caps; 2267eae1bbb2SBruce Allan u32 num_funcs; 2268462acf6aSTony Nguyen 2269462acf6aSTony Nguyen /* cache some func_caps values that should be restored after memset */ 2270be49b1adSJacob Keller cached_caps = func_caps->common_cap; 2271462acf6aSTony Nguyen 2272462acf6aSTony Nguyen /* unset func capabilities */ 2273462acf6aSTony Nguyen memset(func_caps, 0, sizeof(*func_caps)); 2274462acf6aSTony Nguyen 2275be49b1adSJacob Keller #define ICE_RESTORE_FUNC_CAP(name) \ 2276be49b1adSJacob Keller func_caps->common_cap.name = cached_caps.name 2277be49b1adSJacob Keller 2278462acf6aSTony Nguyen /* restore cached values */ 2279be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(valid_functions); 2280be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(txq_first_id); 2281be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(rxq_first_id); 2282be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2283be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(max_mtu); 2284be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(nvm_unified_update); 2285be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm); 2286be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom); 2287be49b1adSJacob Keller ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist); 2288462acf6aSTony Nguyen 2289462acf6aSTony Nguyen /* one Tx and one Rx queue in safe mode */ 2290462acf6aSTony Nguyen func_caps->common_cap.num_rxq = 1; 2291462acf6aSTony Nguyen func_caps->common_cap.num_txq = 1; 2292462acf6aSTony Nguyen 2293462acf6aSTony Nguyen /* two MSIX vectors, one for traffic and one for misc causes */ 2294462acf6aSTony Nguyen func_caps->common_cap.num_msix_vectors = 2; 2295462acf6aSTony Nguyen func_caps->guar_num_vsi = 1; 2296462acf6aSTony Nguyen 2297462acf6aSTony Nguyen /* cache some dev_caps values that should be restored after memset */ 2298be49b1adSJacob Keller cached_caps = dev_caps->common_cap; 2299eae1bbb2SBruce Allan num_funcs = dev_caps->num_funcs; 2300462acf6aSTony Nguyen 2301462acf6aSTony Nguyen /* unset dev capabilities */ 2302462acf6aSTony Nguyen memset(dev_caps, 0, sizeof(*dev_caps)); 2303462acf6aSTony Nguyen 2304be49b1adSJacob Keller #define ICE_RESTORE_DEV_CAP(name) \ 2305be49b1adSJacob Keller dev_caps->common_cap.name = cached_caps.name 2306be49b1adSJacob Keller 2307462acf6aSTony Nguyen /* restore cached values */ 2308be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(valid_functions); 2309be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(txq_first_id); 2310be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(rxq_first_id); 2311be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2312be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(max_mtu); 2313be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(nvm_unified_update); 2314be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm); 2315be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(nvm_update_pending_orom); 2316be49b1adSJacob Keller ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist); 2317eae1bbb2SBruce Allan dev_caps->num_funcs = num_funcs; 2318462acf6aSTony Nguyen 2319462acf6aSTony Nguyen /* one Tx and one Rx queue per function in safe mode */ 2320eae1bbb2SBruce Allan dev_caps->common_cap.num_rxq = num_funcs; 2321eae1bbb2SBruce Allan dev_caps->common_cap.num_txq = num_funcs; 2322462acf6aSTony Nguyen 2323462acf6aSTony Nguyen /* two MSIX vectors per function */ 2324eae1bbb2SBruce Allan dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 2325462acf6aSTony Nguyen } 2326462acf6aSTony Nguyen 2327462acf6aSTony Nguyen /** 23289c20346bSAnirudh Venkataramanan * ice_get_caps - get info about the HW 23299c20346bSAnirudh Venkataramanan * @hw: pointer to the hardware structure 23309c20346bSAnirudh Venkataramanan */ 23319c20346bSAnirudh Venkataramanan enum ice_status ice_get_caps(struct ice_hw *hw) 23329c20346bSAnirudh Venkataramanan { 23339c20346bSAnirudh Venkataramanan enum ice_status status; 23349c20346bSAnirudh Venkataramanan 233581aed647SJacob Keller status = ice_discover_dev_caps(hw, &hw->dev_caps); 233681aed647SJacob Keller if (status) 23379c20346bSAnirudh Venkataramanan return status; 233881aed647SJacob Keller 233981aed647SJacob Keller return ice_discover_func_caps(hw, &hw->func_caps); 23409c20346bSAnirudh Venkataramanan } 23419c20346bSAnirudh Venkataramanan 23429c20346bSAnirudh Venkataramanan /** 2343e94d4478SAnirudh Venkataramanan * ice_aq_manage_mac_write - manage MAC address write command 2344f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 2345e94d4478SAnirudh Venkataramanan * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 2346e94d4478SAnirudh Venkataramanan * @flags: flags to control write behavior 2347e94d4478SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 2348e94d4478SAnirudh Venkataramanan * 2349e94d4478SAnirudh Venkataramanan * This function is used to write MAC address to the NVM (0x0108). 2350e94d4478SAnirudh Venkataramanan */ 2351e94d4478SAnirudh Venkataramanan enum ice_status 2352d671e3e0SJacob Keller ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 2353e94d4478SAnirudh Venkataramanan struct ice_sq_cd *cd) 2354e94d4478SAnirudh Venkataramanan { 2355e94d4478SAnirudh Venkataramanan struct ice_aqc_manage_mac_write *cmd; 2356e94d4478SAnirudh Venkataramanan struct ice_aq_desc desc; 2357e94d4478SAnirudh Venkataramanan 2358e94d4478SAnirudh Venkataramanan cmd = &desc.params.mac_write; 2359e94d4478SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 2360e94d4478SAnirudh Venkataramanan 2361e94d4478SAnirudh Venkataramanan cmd->flags = flags; 23625df42c82SJesse Brandeburg ether_addr_copy(cmd->mac_addr, mac_addr); 2363e94d4478SAnirudh Venkataramanan 2364e94d4478SAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 2365e94d4478SAnirudh Venkataramanan } 2366e94d4478SAnirudh Venkataramanan 2367e94d4478SAnirudh Venkataramanan /** 2368f31e4b6fSAnirudh Venkataramanan * ice_aq_clear_pxe_mode 2369f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 2370f31e4b6fSAnirudh Venkataramanan * 2371f31e4b6fSAnirudh Venkataramanan * Tell the firmware that the driver is taking over from PXE (0x0110). 2372f31e4b6fSAnirudh Venkataramanan */ 2373f31e4b6fSAnirudh Venkataramanan static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 2374f31e4b6fSAnirudh Venkataramanan { 2375f31e4b6fSAnirudh Venkataramanan struct ice_aq_desc desc; 2376f31e4b6fSAnirudh Venkataramanan 2377f31e4b6fSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 2378f31e4b6fSAnirudh Venkataramanan desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 2379f31e4b6fSAnirudh Venkataramanan 2380f31e4b6fSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2381f31e4b6fSAnirudh Venkataramanan } 2382f31e4b6fSAnirudh Venkataramanan 2383f31e4b6fSAnirudh Venkataramanan /** 2384f31e4b6fSAnirudh Venkataramanan * ice_clear_pxe_mode - clear pxe operations mode 2385f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 2386f31e4b6fSAnirudh Venkataramanan * 2387f31e4b6fSAnirudh Venkataramanan * Make sure all PXE mode settings are cleared, including things 2388f31e4b6fSAnirudh Venkataramanan * like descriptor fetch/write-back mode. 2389f31e4b6fSAnirudh Venkataramanan */ 2390f31e4b6fSAnirudh Venkataramanan void ice_clear_pxe_mode(struct ice_hw *hw) 2391f31e4b6fSAnirudh Venkataramanan { 2392f31e4b6fSAnirudh Venkataramanan if (ice_check_sq_alive(hw, &hw->adminq)) 2393f31e4b6fSAnirudh Venkataramanan ice_aq_clear_pxe_mode(hw); 2394f31e4b6fSAnirudh Venkataramanan } 2395cdedef59SAnirudh Venkataramanan 2396cdedef59SAnirudh Venkataramanan /** 239748cb27f2SChinh Cao * ice_get_link_speed_based_on_phy_type - returns link speed 239848cb27f2SChinh Cao * @phy_type_low: lower part of phy_type 2399aef74145SAnirudh Venkataramanan * @phy_type_high: higher part of phy_type 240048cb27f2SChinh Cao * 2401f9867df6SAnirudh Venkataramanan * This helper function will convert an entry in PHY type structure 2402aef74145SAnirudh Venkataramanan * [phy_type_low, phy_type_high] to its corresponding link speed. 2403aef74145SAnirudh Venkataramanan * Note: In the structure of [phy_type_low, phy_type_high], there should 2404f9867df6SAnirudh Venkataramanan * be one bit set, as this function will convert one PHY type to its 240548cb27f2SChinh Cao * speed. 240648cb27f2SChinh Cao * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 240748cb27f2SChinh Cao * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 240848cb27f2SChinh Cao */ 2409aef74145SAnirudh Venkataramanan static u16 2410aef74145SAnirudh Venkataramanan ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 241148cb27f2SChinh Cao { 2412aef74145SAnirudh Venkataramanan u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 241348cb27f2SChinh Cao u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 241448cb27f2SChinh Cao 241548cb27f2SChinh Cao switch (phy_type_low) { 241648cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_100BASE_TX: 241748cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_100M_SGMII: 241848cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 241948cb27f2SChinh Cao break; 242048cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1000BASE_T: 242148cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1000BASE_SX: 242248cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1000BASE_LX: 242348cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1000BASE_KX: 242448cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_1G_SGMII: 242548cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 242648cb27f2SChinh Cao break; 242748cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_2500BASE_T: 242848cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_2500BASE_X: 242948cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_2500BASE_KX: 243048cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 243148cb27f2SChinh Cao break; 243248cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_5GBASE_T: 243348cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_5GBASE_KR: 243448cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 243548cb27f2SChinh Cao break; 243648cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10GBASE_T: 243748cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10G_SFI_DA: 243848cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10GBASE_SR: 243948cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10GBASE_LR: 244048cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 244148cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 244248cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 244348cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 244448cb27f2SChinh Cao break; 244548cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_T: 244648cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_CR: 244748cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 244848cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_CR1: 244948cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_SR: 245048cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_LR: 245148cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_KR: 245248cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 245348cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25GBASE_KR1: 245448cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 245548cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 245648cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 245748cb27f2SChinh Cao break; 245848cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40GBASE_CR4: 245948cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40GBASE_SR4: 246048cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40GBASE_LR4: 246148cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40GBASE_KR4: 246248cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 246348cb27f2SChinh Cao case ICE_PHY_TYPE_LOW_40G_XLAUI: 246448cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 246548cb27f2SChinh Cao break; 2466aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_CR2: 2467aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_SR2: 2468aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_LR2: 2469aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_KR2: 2470aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 2471aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_LAUI2: 2472aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 2473aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_AUI2: 2474aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_CP: 2475aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_SR: 2476aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_FR: 2477aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_LR: 2478aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 2479aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 2480aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_50G_AUI1: 2481aef74145SAnirudh Venkataramanan speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 2482aef74145SAnirudh Venkataramanan break; 2483aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CR4: 2484aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_SR4: 2485aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_LR4: 2486aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_KR4: 2487aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 2488aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100G_CAUI4: 2489aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 2490aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100G_AUI4: 2491aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 2492aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 2493aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_CP2: 2494aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_SR2: 2495aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_LOW_100GBASE_DR: 2496aef74145SAnirudh Venkataramanan speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 2497aef74145SAnirudh Venkataramanan break; 249848cb27f2SChinh Cao default: 249948cb27f2SChinh Cao speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 250048cb27f2SChinh Cao break; 250148cb27f2SChinh Cao } 250248cb27f2SChinh Cao 2503aef74145SAnirudh Venkataramanan switch (phy_type_high) { 2504aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 2505aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 2506aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100G_CAUI2: 2507aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 2508aef74145SAnirudh Venkataramanan case ICE_PHY_TYPE_HIGH_100G_AUI2: 2509aef74145SAnirudh Venkataramanan speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 2510aef74145SAnirudh Venkataramanan break; 2511aef74145SAnirudh Venkataramanan default: 2512aef74145SAnirudh Venkataramanan speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 2513aef74145SAnirudh Venkataramanan break; 2514aef74145SAnirudh Venkataramanan } 2515aef74145SAnirudh Venkataramanan 2516aef74145SAnirudh Venkataramanan if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 2517aef74145SAnirudh Venkataramanan speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 2518aef74145SAnirudh Venkataramanan return ICE_AQ_LINK_SPEED_UNKNOWN; 2519aef74145SAnirudh Venkataramanan else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2520aef74145SAnirudh Venkataramanan speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 2521aef74145SAnirudh Venkataramanan return ICE_AQ_LINK_SPEED_UNKNOWN; 2522aef74145SAnirudh Venkataramanan else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 2523aef74145SAnirudh Venkataramanan speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 252448cb27f2SChinh Cao return speed_phy_type_low; 2525aef74145SAnirudh Venkataramanan else 2526aef74145SAnirudh Venkataramanan return speed_phy_type_high; 252748cb27f2SChinh Cao } 252848cb27f2SChinh Cao 252948cb27f2SChinh Cao /** 253048cb27f2SChinh Cao * ice_update_phy_type 253148cb27f2SChinh Cao * @phy_type_low: pointer to the lower part of phy_type 2532aef74145SAnirudh Venkataramanan * @phy_type_high: pointer to the higher part of phy_type 253348cb27f2SChinh Cao * @link_speeds_bitmap: targeted link speeds bitmap 253448cb27f2SChinh Cao * 253548cb27f2SChinh Cao * Note: For the link_speeds_bitmap structure, you can check it at 253648cb27f2SChinh Cao * [ice_aqc_get_link_status->link_speed]. Caller can pass in 253748cb27f2SChinh Cao * link_speeds_bitmap include multiple speeds. 253848cb27f2SChinh Cao * 2539aef74145SAnirudh Venkataramanan * Each entry in this [phy_type_low, phy_type_high] structure will 2540aef74145SAnirudh Venkataramanan * present a certain link speed. This helper function will turn on bits 2541aef74145SAnirudh Venkataramanan * in [phy_type_low, phy_type_high] structure based on the value of 254248cb27f2SChinh Cao * link_speeds_bitmap input parameter. 254348cb27f2SChinh Cao */ 2544aef74145SAnirudh Venkataramanan void 2545aef74145SAnirudh Venkataramanan ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 2546aef74145SAnirudh Venkataramanan u16 link_speeds_bitmap) 254748cb27f2SChinh Cao { 2548aef74145SAnirudh Venkataramanan u64 pt_high; 254948cb27f2SChinh Cao u64 pt_low; 255048cb27f2SChinh Cao int index; 2551207e3721SBruce Allan u16 speed; 255248cb27f2SChinh Cao 255348cb27f2SChinh Cao /* We first check with low part of phy_type */ 255448cb27f2SChinh Cao for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 255548cb27f2SChinh Cao pt_low = BIT_ULL(index); 2556aef74145SAnirudh Venkataramanan speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 255748cb27f2SChinh Cao 255848cb27f2SChinh Cao if (link_speeds_bitmap & speed) 255948cb27f2SChinh Cao *phy_type_low |= BIT_ULL(index); 256048cb27f2SChinh Cao } 2561aef74145SAnirudh Venkataramanan 2562aef74145SAnirudh Venkataramanan /* We then check with high part of phy_type */ 2563aef74145SAnirudh Venkataramanan for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 2564aef74145SAnirudh Venkataramanan pt_high = BIT_ULL(index); 2565aef74145SAnirudh Venkataramanan speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 2566aef74145SAnirudh Venkataramanan 2567aef74145SAnirudh Venkataramanan if (link_speeds_bitmap & speed) 2568aef74145SAnirudh Venkataramanan *phy_type_high |= BIT_ULL(index); 2569aef74145SAnirudh Venkataramanan } 257048cb27f2SChinh Cao } 257148cb27f2SChinh Cao 257248cb27f2SChinh Cao /** 2573fcea6f3dSAnirudh Venkataramanan * ice_aq_set_phy_cfg 2574f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 25751a3571b5SPaul Greenwalt * @pi: port info structure of the interested logical port 2576fcea6f3dSAnirudh Venkataramanan * @cfg: structure with PHY configuration data to be set 2577fcea6f3dSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 2578fcea6f3dSAnirudh Venkataramanan * 2579fcea6f3dSAnirudh Venkataramanan * Set the various PHY configuration parameters supported on the Port. 2580fcea6f3dSAnirudh Venkataramanan * One or more of the Set PHY config parameters may be ignored in an MFP 2581fcea6f3dSAnirudh Venkataramanan * mode as the PF may not have the privilege to set some of the PHY Config 2582fcea6f3dSAnirudh Venkataramanan * parameters. This status will be indicated by the command response (0x0601). 2583fcea6f3dSAnirudh Venkataramanan */ 258448cb27f2SChinh Cao enum ice_status 25851a3571b5SPaul Greenwalt ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 2586fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 2587fcea6f3dSAnirudh Venkataramanan { 2588fcea6f3dSAnirudh Venkataramanan struct ice_aq_desc desc; 2589b5e19a64SChinh T Cao enum ice_status status; 2590fcea6f3dSAnirudh Venkataramanan 2591fcea6f3dSAnirudh Venkataramanan if (!cfg) 2592fcea6f3dSAnirudh Venkataramanan return ICE_ERR_PARAM; 2593fcea6f3dSAnirudh Venkataramanan 2594d8df260aSChinh T Cao /* Ensure that only valid bits of cfg->caps can be turned on. */ 2595d8df260aSChinh T Cao if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 25969228d8b2SJacob Keller ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 2597d8df260aSChinh T Cao cfg->caps); 2598d8df260aSChinh T Cao 2599d8df260aSChinh T Cao cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 2600d8df260aSChinh T Cao } 2601d8df260aSChinh T Cao 2602fcea6f3dSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 26031a3571b5SPaul Greenwalt desc.params.set_phy.lport_num = pi->lport; 260448cb27f2SChinh Cao desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 2605fcea6f3dSAnirudh Venkataramanan 260655df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 2607dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 2608dc67039bSJesse Brandeburg (unsigned long long)le64_to_cpu(cfg->phy_type_low)); 2609dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 2610dc67039bSJesse Brandeburg (unsigned long long)le64_to_cpu(cfg->phy_type_high)); 2611dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 2612bdeff971SLev Faerman ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 2613bdeff971SLev Faerman cfg->low_power_ctrl_an); 2614dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 2615dc67039bSJesse Brandeburg ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 261655df52a0SPaul Greenwalt ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 261755df52a0SPaul Greenwalt cfg->link_fec_opt); 2618dc67039bSJesse Brandeburg 2619b5e19a64SChinh T Cao status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 2620b5e19a64SChinh T Cao if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 2621b5e19a64SChinh T Cao status = 0; 2622b5e19a64SChinh T Cao 26231a3571b5SPaul Greenwalt if (!status) 26241a3571b5SPaul Greenwalt pi->phy.curr_user_phy_cfg = *cfg; 26251a3571b5SPaul Greenwalt 2626b5e19a64SChinh T Cao return status; 2627fcea6f3dSAnirudh Venkataramanan } 2628fcea6f3dSAnirudh Venkataramanan 2629fcea6f3dSAnirudh Venkataramanan /** 2630fcea6f3dSAnirudh Venkataramanan * ice_update_link_info - update status of the HW network link 2631fcea6f3dSAnirudh Venkataramanan * @pi: port info structure of the interested logical port 2632fcea6f3dSAnirudh Venkataramanan */ 26335755143dSDave Ertman enum ice_status ice_update_link_info(struct ice_port_info *pi) 2634fcea6f3dSAnirudh Venkataramanan { 2635092a33d4SBruce Allan struct ice_link_status *li; 2636fcea6f3dSAnirudh Venkataramanan enum ice_status status; 2637fcea6f3dSAnirudh Venkataramanan 2638fcea6f3dSAnirudh Venkataramanan if (!pi) 2639fcea6f3dSAnirudh Venkataramanan return ICE_ERR_PARAM; 2640fcea6f3dSAnirudh Venkataramanan 2641092a33d4SBruce Allan li = &pi->phy.link_info; 2642fcea6f3dSAnirudh Venkataramanan 2643092a33d4SBruce Allan status = ice_aq_get_link_info(pi, true, NULL, NULL); 2644092a33d4SBruce Allan if (status) 2645092a33d4SBruce Allan return status; 2646092a33d4SBruce Allan 2647092a33d4SBruce Allan if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 2648092a33d4SBruce Allan struct ice_aqc_get_phy_caps_data *pcaps; 2649092a33d4SBruce Allan struct ice_hw *hw; 2650092a33d4SBruce Allan 2651092a33d4SBruce Allan hw = pi->hw; 2652092a33d4SBruce Allan pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), 2653092a33d4SBruce Allan GFP_KERNEL); 2654fcea6f3dSAnirudh Venkataramanan if (!pcaps) 2655fcea6f3dSAnirudh Venkataramanan return ICE_ERR_NO_MEMORY; 2656fcea6f3dSAnirudh Venkataramanan 2657057911baSChinh T Cao status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, 2658fcea6f3dSAnirudh Venkataramanan pcaps, NULL); 2659fcea6f3dSAnirudh Venkataramanan 2660fcea6f3dSAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), pcaps); 2661092a33d4SBruce Allan } 2662092a33d4SBruce Allan 2663fcea6f3dSAnirudh Venkataramanan return status; 2664fcea6f3dSAnirudh Venkataramanan } 2665fcea6f3dSAnirudh Venkataramanan 2666fcea6f3dSAnirudh Venkataramanan /** 26671a3571b5SPaul Greenwalt * ice_cache_phy_user_req 26681a3571b5SPaul Greenwalt * @pi: port information structure 26691a3571b5SPaul Greenwalt * @cache_data: PHY logging data 26701a3571b5SPaul Greenwalt * @cache_mode: PHY logging mode 26711a3571b5SPaul Greenwalt * 26721a3571b5SPaul Greenwalt * Log the user request on (FC, FEC, SPEED) for later use. 26731a3571b5SPaul Greenwalt */ 26741a3571b5SPaul Greenwalt static void 26751a3571b5SPaul Greenwalt ice_cache_phy_user_req(struct ice_port_info *pi, 26761a3571b5SPaul Greenwalt struct ice_phy_cache_mode_data cache_data, 26771a3571b5SPaul Greenwalt enum ice_phy_cache_mode cache_mode) 26781a3571b5SPaul Greenwalt { 26791a3571b5SPaul Greenwalt if (!pi) 26801a3571b5SPaul Greenwalt return; 26811a3571b5SPaul Greenwalt 26821a3571b5SPaul Greenwalt switch (cache_mode) { 26831a3571b5SPaul Greenwalt case ICE_FC_MODE: 26841a3571b5SPaul Greenwalt pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 26851a3571b5SPaul Greenwalt break; 26861a3571b5SPaul Greenwalt case ICE_SPEED_MODE: 26871a3571b5SPaul Greenwalt pi->phy.curr_user_speed_req = 26881a3571b5SPaul Greenwalt cache_data.data.curr_user_speed_req; 26891a3571b5SPaul Greenwalt break; 26901a3571b5SPaul Greenwalt case ICE_FEC_MODE: 26911a3571b5SPaul Greenwalt pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 26921a3571b5SPaul Greenwalt break; 26931a3571b5SPaul Greenwalt default: 26941a3571b5SPaul Greenwalt break; 26951a3571b5SPaul Greenwalt } 26961a3571b5SPaul Greenwalt } 26971a3571b5SPaul Greenwalt 26981a3571b5SPaul Greenwalt /** 26991a3571b5SPaul Greenwalt * ice_caps_to_fc_mode 27001a3571b5SPaul Greenwalt * @caps: PHY capabilities 27011a3571b5SPaul Greenwalt * 27021a3571b5SPaul Greenwalt * Convert PHY FC capabilities to ice FC mode 27031a3571b5SPaul Greenwalt */ 27041a3571b5SPaul Greenwalt enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 27051a3571b5SPaul Greenwalt { 27061a3571b5SPaul Greenwalt if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 27071a3571b5SPaul Greenwalt caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 27081a3571b5SPaul Greenwalt return ICE_FC_FULL; 27091a3571b5SPaul Greenwalt 27101a3571b5SPaul Greenwalt if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 27111a3571b5SPaul Greenwalt return ICE_FC_TX_PAUSE; 27121a3571b5SPaul Greenwalt 27131a3571b5SPaul Greenwalt if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 27141a3571b5SPaul Greenwalt return ICE_FC_RX_PAUSE; 27151a3571b5SPaul Greenwalt 27161a3571b5SPaul Greenwalt return ICE_FC_NONE; 27171a3571b5SPaul Greenwalt } 27181a3571b5SPaul Greenwalt 27191a3571b5SPaul Greenwalt /** 27201a3571b5SPaul Greenwalt * ice_caps_to_fec_mode 27211a3571b5SPaul Greenwalt * @caps: PHY capabilities 27221a3571b5SPaul Greenwalt * @fec_options: Link FEC options 27231a3571b5SPaul Greenwalt * 27241a3571b5SPaul Greenwalt * Convert PHY FEC capabilities to ice FEC mode 27251a3571b5SPaul Greenwalt */ 27261a3571b5SPaul Greenwalt enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 27271a3571b5SPaul Greenwalt { 27281a3571b5SPaul Greenwalt if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 27291a3571b5SPaul Greenwalt return ICE_FEC_AUTO; 27301a3571b5SPaul Greenwalt 27311a3571b5SPaul Greenwalt if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 27321a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 27331a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 27341a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_25G_KR_REQ)) 27351a3571b5SPaul Greenwalt return ICE_FEC_BASER; 27361a3571b5SPaul Greenwalt 27371a3571b5SPaul Greenwalt if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 27381a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_25G_RS_544_REQ | 27391a3571b5SPaul Greenwalt ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 27401a3571b5SPaul Greenwalt return ICE_FEC_RS; 27411a3571b5SPaul Greenwalt 27421a3571b5SPaul Greenwalt return ICE_FEC_NONE; 27431a3571b5SPaul Greenwalt } 27441a3571b5SPaul Greenwalt 27451a3571b5SPaul Greenwalt /** 27462ffb6085SPaul Greenwalt * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 27471a3571b5SPaul Greenwalt * @pi: port information structure 27482ffb6085SPaul Greenwalt * @cfg: PHY configuration data to set FC mode 27492ffb6085SPaul Greenwalt * @req_mode: FC mode to configure 2750fcea6f3dSAnirudh Venkataramanan */ 27511a3571b5SPaul Greenwalt enum ice_status 27521a3571b5SPaul Greenwalt ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 27531a3571b5SPaul Greenwalt enum ice_fc_mode req_mode) 2754fcea6f3dSAnirudh Venkataramanan { 27551a3571b5SPaul Greenwalt struct ice_phy_cache_mode_data cache_data; 2756fcea6f3dSAnirudh Venkataramanan u8 pause_mask = 0x0; 2757fcea6f3dSAnirudh Venkataramanan 27581a3571b5SPaul Greenwalt if (!pi || !cfg) 27592ffb6085SPaul Greenwalt return ICE_ERR_BAD_PTR; 2760fcea6f3dSAnirudh Venkataramanan 27612ffb6085SPaul Greenwalt switch (req_mode) { 2762fcea6f3dSAnirudh Venkataramanan case ICE_FC_FULL: 2763fcea6f3dSAnirudh Venkataramanan pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2764fcea6f3dSAnirudh Venkataramanan pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2765fcea6f3dSAnirudh Venkataramanan break; 2766fcea6f3dSAnirudh Venkataramanan case ICE_FC_RX_PAUSE: 2767fcea6f3dSAnirudh Venkataramanan pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 2768fcea6f3dSAnirudh Venkataramanan break; 2769fcea6f3dSAnirudh Venkataramanan case ICE_FC_TX_PAUSE: 2770fcea6f3dSAnirudh Venkataramanan pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 2771fcea6f3dSAnirudh Venkataramanan break; 2772fcea6f3dSAnirudh Venkataramanan default: 2773fcea6f3dSAnirudh Venkataramanan break; 2774fcea6f3dSAnirudh Venkataramanan } 2775fcea6f3dSAnirudh Venkataramanan 27762ffb6085SPaul Greenwalt /* clear the old pause settings */ 27772ffb6085SPaul Greenwalt cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 27782ffb6085SPaul Greenwalt ICE_AQC_PHY_EN_RX_LINK_PAUSE); 27792ffb6085SPaul Greenwalt 27802ffb6085SPaul Greenwalt /* set the new capabilities */ 27812ffb6085SPaul Greenwalt cfg->caps |= pause_mask; 27822ffb6085SPaul Greenwalt 27831a3571b5SPaul Greenwalt /* Cache user FC request */ 27841a3571b5SPaul Greenwalt cache_data.data.curr_user_fc_req = req_mode; 27851a3571b5SPaul Greenwalt ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 27861a3571b5SPaul Greenwalt 27872ffb6085SPaul Greenwalt return 0; 27882ffb6085SPaul Greenwalt } 27892ffb6085SPaul Greenwalt 27902ffb6085SPaul Greenwalt /** 27912ffb6085SPaul Greenwalt * ice_set_fc 27922ffb6085SPaul Greenwalt * @pi: port information structure 27932ffb6085SPaul Greenwalt * @aq_failures: pointer to status code, specific to ice_set_fc routine 27942ffb6085SPaul Greenwalt * @ena_auto_link_update: enable automatic link update 27952ffb6085SPaul Greenwalt * 27962ffb6085SPaul Greenwalt * Set the requested flow control mode. 27972ffb6085SPaul Greenwalt */ 27982ffb6085SPaul Greenwalt enum ice_status 27992ffb6085SPaul Greenwalt ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 28002ffb6085SPaul Greenwalt { 28012ffb6085SPaul Greenwalt struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 28022ffb6085SPaul Greenwalt struct ice_aqc_get_phy_caps_data *pcaps; 28032ffb6085SPaul Greenwalt enum ice_status status; 28042ffb6085SPaul Greenwalt struct ice_hw *hw; 28052ffb6085SPaul Greenwalt 28061a3571b5SPaul Greenwalt if (!pi || !aq_failures) 28072ffb6085SPaul Greenwalt return ICE_ERR_BAD_PTR; 28082ffb6085SPaul Greenwalt 28092ffb6085SPaul Greenwalt *aq_failures = 0; 28102ffb6085SPaul Greenwalt hw = pi->hw; 28112ffb6085SPaul Greenwalt 2812fcea6f3dSAnirudh Venkataramanan pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL); 2813fcea6f3dSAnirudh Venkataramanan if (!pcaps) 2814fcea6f3dSAnirudh Venkataramanan return ICE_ERR_NO_MEMORY; 2815fcea6f3dSAnirudh Venkataramanan 2816f9867df6SAnirudh Venkataramanan /* Get the current PHY config */ 2817fcea6f3dSAnirudh Venkataramanan status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps, 2818fcea6f3dSAnirudh Venkataramanan NULL); 2819fcea6f3dSAnirudh Venkataramanan if (status) { 2820fcea6f3dSAnirudh Venkataramanan *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 2821fcea6f3dSAnirudh Venkataramanan goto out; 2822fcea6f3dSAnirudh Venkataramanan } 2823fcea6f3dSAnirudh Venkataramanan 2824ea78ce4dSPaul Greenwalt ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 2825d8df260aSChinh T Cao 28262ffb6085SPaul Greenwalt /* Configure the set PHY data */ 28271a3571b5SPaul Greenwalt status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 28282ffb6085SPaul Greenwalt if (status) 28292ffb6085SPaul Greenwalt goto out; 2830d8df260aSChinh T Cao 2831fcea6f3dSAnirudh Venkataramanan /* If the capabilities have changed, then set the new config */ 2832fcea6f3dSAnirudh Venkataramanan if (cfg.caps != pcaps->caps) { 2833fcea6f3dSAnirudh Venkataramanan int retry_count, retry_max = 10; 2834fcea6f3dSAnirudh Venkataramanan 2835fcea6f3dSAnirudh Venkataramanan /* Auto restart link so settings take effect */ 283648cb27f2SChinh Cao if (ena_auto_link_update) 283748cb27f2SChinh Cao cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 2838fcea6f3dSAnirudh Venkataramanan 28391a3571b5SPaul Greenwalt status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 2840fcea6f3dSAnirudh Venkataramanan if (status) { 2841fcea6f3dSAnirudh Venkataramanan *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 2842fcea6f3dSAnirudh Venkataramanan goto out; 2843fcea6f3dSAnirudh Venkataramanan } 2844fcea6f3dSAnirudh Venkataramanan 2845fcea6f3dSAnirudh Venkataramanan /* Update the link info 2846fcea6f3dSAnirudh Venkataramanan * It sometimes takes a really long time for link to 2847fcea6f3dSAnirudh Venkataramanan * come back from the atomic reset. Thus, we wait a 2848fcea6f3dSAnirudh Venkataramanan * little bit. 2849fcea6f3dSAnirudh Venkataramanan */ 2850fcea6f3dSAnirudh Venkataramanan for (retry_count = 0; retry_count < retry_max; retry_count++) { 2851fcea6f3dSAnirudh Venkataramanan status = ice_update_link_info(pi); 2852fcea6f3dSAnirudh Venkataramanan 2853fcea6f3dSAnirudh Venkataramanan if (!status) 2854fcea6f3dSAnirudh Venkataramanan break; 2855fcea6f3dSAnirudh Venkataramanan 2856fcea6f3dSAnirudh Venkataramanan mdelay(100); 2857fcea6f3dSAnirudh Venkataramanan } 2858fcea6f3dSAnirudh Venkataramanan 2859fcea6f3dSAnirudh Venkataramanan if (status) 2860fcea6f3dSAnirudh Venkataramanan *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 2861fcea6f3dSAnirudh Venkataramanan } 2862fcea6f3dSAnirudh Venkataramanan 2863fcea6f3dSAnirudh Venkataramanan out: 2864fcea6f3dSAnirudh Venkataramanan devm_kfree(ice_hw_to_dev(hw), pcaps); 2865fcea6f3dSAnirudh Venkataramanan return status; 2866fcea6f3dSAnirudh Venkataramanan } 2867fcea6f3dSAnirudh Venkataramanan 2868fcea6f3dSAnirudh Venkataramanan /** 28691a3571b5SPaul Greenwalt * ice_phy_caps_equals_cfg 28701a3571b5SPaul Greenwalt * @phy_caps: PHY capabilities 28711a3571b5SPaul Greenwalt * @phy_cfg: PHY configuration 28721a3571b5SPaul Greenwalt * 28731a3571b5SPaul Greenwalt * Helper function to determine if PHY capabilities matches PHY 28741a3571b5SPaul Greenwalt * configuration 28751a3571b5SPaul Greenwalt */ 28761a3571b5SPaul Greenwalt bool 28771a3571b5SPaul Greenwalt ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 28781a3571b5SPaul Greenwalt struct ice_aqc_set_phy_cfg_data *phy_cfg) 28791a3571b5SPaul Greenwalt { 28801a3571b5SPaul Greenwalt u8 caps_mask, cfg_mask; 28811a3571b5SPaul Greenwalt 28821a3571b5SPaul Greenwalt if (!phy_caps || !phy_cfg) 28831a3571b5SPaul Greenwalt return false; 28841a3571b5SPaul Greenwalt 28851a3571b5SPaul Greenwalt /* These bits are not common between capabilities and configuration. 28861a3571b5SPaul Greenwalt * Do not use them to determine equality. 28871a3571b5SPaul Greenwalt */ 28881a3571b5SPaul Greenwalt caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 28891a3571b5SPaul Greenwalt ICE_AQC_GET_PHY_EN_MOD_QUAL); 28901a3571b5SPaul Greenwalt cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 28911a3571b5SPaul Greenwalt 28921a3571b5SPaul Greenwalt if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 28931a3571b5SPaul Greenwalt phy_caps->phy_type_high != phy_cfg->phy_type_high || 28941a3571b5SPaul Greenwalt ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 2895bdeff971SLev Faerman phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 28961a3571b5SPaul Greenwalt phy_caps->eee_cap != phy_cfg->eee_cap || 28971a3571b5SPaul Greenwalt phy_caps->eeer_value != phy_cfg->eeer_value || 28981a3571b5SPaul Greenwalt phy_caps->link_fec_options != phy_cfg->link_fec_opt) 28991a3571b5SPaul Greenwalt return false; 29001a3571b5SPaul Greenwalt 29011a3571b5SPaul Greenwalt return true; 29021a3571b5SPaul Greenwalt } 29031a3571b5SPaul Greenwalt 29041a3571b5SPaul Greenwalt /** 2905f776b3acSPaul Greenwalt * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 2906ea78ce4dSPaul Greenwalt * @pi: port information structure 2907f776b3acSPaul Greenwalt * @caps: PHY ability structure to copy date from 2908f776b3acSPaul Greenwalt * @cfg: PHY configuration structure to copy data to 2909f776b3acSPaul Greenwalt * 2910f776b3acSPaul Greenwalt * Helper function to copy AQC PHY get ability data to PHY set configuration 2911f776b3acSPaul Greenwalt * data structure 2912f776b3acSPaul Greenwalt */ 2913f776b3acSPaul Greenwalt void 2914ea78ce4dSPaul Greenwalt ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 2915ea78ce4dSPaul Greenwalt struct ice_aqc_get_phy_caps_data *caps, 2916f776b3acSPaul Greenwalt struct ice_aqc_set_phy_cfg_data *cfg) 2917f776b3acSPaul Greenwalt { 2918ea78ce4dSPaul Greenwalt if (!pi || !caps || !cfg) 2919f776b3acSPaul Greenwalt return; 2920f776b3acSPaul Greenwalt 29212ffb6085SPaul Greenwalt memset(cfg, 0, sizeof(*cfg)); 2922f776b3acSPaul Greenwalt cfg->phy_type_low = caps->phy_type_low; 2923f776b3acSPaul Greenwalt cfg->phy_type_high = caps->phy_type_high; 2924f776b3acSPaul Greenwalt cfg->caps = caps->caps; 2925bdeff971SLev Faerman cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 2926f776b3acSPaul Greenwalt cfg->eee_cap = caps->eee_cap; 2927f776b3acSPaul Greenwalt cfg->eeer_value = caps->eeer_value; 2928f776b3acSPaul Greenwalt cfg->link_fec_opt = caps->link_fec_options; 2929ea78ce4dSPaul Greenwalt cfg->module_compliance_enforcement = 2930ea78ce4dSPaul Greenwalt caps->module_compliance_enforcement; 2931ea78ce4dSPaul Greenwalt 2932ea78ce4dSPaul Greenwalt if (ice_fw_supports_link_override(pi->hw)) { 2933ea78ce4dSPaul Greenwalt struct ice_link_default_override_tlv tlv; 2934ea78ce4dSPaul Greenwalt 2935ea78ce4dSPaul Greenwalt if (ice_get_link_default_override(&tlv, pi)) 2936ea78ce4dSPaul Greenwalt return; 2937ea78ce4dSPaul Greenwalt 2938ea78ce4dSPaul Greenwalt if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) 2939ea78ce4dSPaul Greenwalt cfg->module_compliance_enforcement |= 2940ea78ce4dSPaul Greenwalt ICE_LINK_OVERRIDE_STRICT_MODE; 2941ea78ce4dSPaul Greenwalt } 2942f776b3acSPaul Greenwalt } 2943f776b3acSPaul Greenwalt 2944f776b3acSPaul Greenwalt /** 2945f776b3acSPaul Greenwalt * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 294661cf42e7SPaul Greenwalt * @pi: port information structure 2947f776b3acSPaul Greenwalt * @cfg: PHY configuration data to set FEC mode 2948f776b3acSPaul Greenwalt * @fec: FEC mode to configure 2949f776b3acSPaul Greenwalt */ 295061cf42e7SPaul Greenwalt enum ice_status 295161cf42e7SPaul Greenwalt ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 295261cf42e7SPaul Greenwalt enum ice_fec_mode fec) 2953f776b3acSPaul Greenwalt { 295461cf42e7SPaul Greenwalt struct ice_aqc_get_phy_caps_data *pcaps; 295561cf42e7SPaul Greenwalt enum ice_status status; 295661cf42e7SPaul Greenwalt 295761cf42e7SPaul Greenwalt if (!pi || !cfg) 295861cf42e7SPaul Greenwalt return ICE_ERR_BAD_PTR; 295961cf42e7SPaul Greenwalt 296061cf42e7SPaul Greenwalt pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL); 296161cf42e7SPaul Greenwalt if (!pcaps) 296261cf42e7SPaul Greenwalt return ICE_ERR_NO_MEMORY; 296361cf42e7SPaul Greenwalt 296461cf42e7SPaul Greenwalt status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, pcaps, 296561cf42e7SPaul Greenwalt NULL); 296661cf42e7SPaul Greenwalt if (status) 296761cf42e7SPaul Greenwalt goto out; 296861cf42e7SPaul Greenwalt 296961cf42e7SPaul Greenwalt cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; 297061cf42e7SPaul Greenwalt cfg->link_fec_opt = pcaps->link_fec_options; 297161cf42e7SPaul Greenwalt 2972f776b3acSPaul Greenwalt switch (fec) { 2973f776b3acSPaul Greenwalt case ICE_FEC_BASER: 29743747f031SChinh T Cao /* Clear RS bits, and AND BASE-R ability 2975f776b3acSPaul Greenwalt * bits and OR request bits. 2976f776b3acSPaul Greenwalt */ 2977f776b3acSPaul Greenwalt cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 2978f776b3acSPaul Greenwalt ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 2979f776b3acSPaul Greenwalt cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 2980f776b3acSPaul Greenwalt ICE_AQC_PHY_FEC_25G_KR_REQ; 2981f776b3acSPaul Greenwalt break; 2982f776b3acSPaul Greenwalt case ICE_FEC_RS: 29833747f031SChinh T Cao /* Clear BASE-R bits, and AND RS ability 2984f776b3acSPaul Greenwalt * bits and OR request bits. 2985f776b3acSPaul Greenwalt */ 2986f776b3acSPaul Greenwalt cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 2987f776b3acSPaul Greenwalt cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 2988f776b3acSPaul Greenwalt ICE_AQC_PHY_FEC_25G_RS_544_REQ; 2989f776b3acSPaul Greenwalt break; 2990f776b3acSPaul Greenwalt case ICE_FEC_NONE: 29913747f031SChinh T Cao /* Clear all FEC option bits. */ 2992f776b3acSPaul Greenwalt cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 2993f776b3acSPaul Greenwalt break; 2994f776b3acSPaul Greenwalt case ICE_FEC_AUTO: 2995f776b3acSPaul Greenwalt /* AND auto FEC bit, and all caps bits. */ 2996f776b3acSPaul Greenwalt cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 299761cf42e7SPaul Greenwalt cfg->link_fec_opt |= pcaps->link_fec_options; 299861cf42e7SPaul Greenwalt break; 299961cf42e7SPaul Greenwalt default: 300061cf42e7SPaul Greenwalt status = ICE_ERR_PARAM; 3001f776b3acSPaul Greenwalt break; 3002f776b3acSPaul Greenwalt } 300361cf42e7SPaul Greenwalt 3004ea78ce4dSPaul Greenwalt if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) { 3005ea78ce4dSPaul Greenwalt struct ice_link_default_override_tlv tlv; 3006ea78ce4dSPaul Greenwalt 3007ea78ce4dSPaul Greenwalt if (ice_get_link_default_override(&tlv, pi)) 3008ea78ce4dSPaul Greenwalt goto out; 3009ea78ce4dSPaul Greenwalt 3010ea78ce4dSPaul Greenwalt if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 3011ea78ce4dSPaul Greenwalt (tlv.options & ICE_LINK_OVERRIDE_EN)) 3012ea78ce4dSPaul Greenwalt cfg->link_fec_opt = tlv.fec_options; 3013ea78ce4dSPaul Greenwalt } 3014ea78ce4dSPaul Greenwalt 301561cf42e7SPaul Greenwalt out: 301661cf42e7SPaul Greenwalt kfree(pcaps); 301761cf42e7SPaul Greenwalt 301861cf42e7SPaul Greenwalt return status; 3019f776b3acSPaul Greenwalt } 3020f776b3acSPaul Greenwalt 3021f776b3acSPaul Greenwalt /** 30220b28b702SAnirudh Venkataramanan * ice_get_link_status - get status of the HW network link 30230b28b702SAnirudh Venkataramanan * @pi: port information structure 30240b28b702SAnirudh Venkataramanan * @link_up: pointer to bool (true/false = linkup/linkdown) 30250b28b702SAnirudh Venkataramanan * 30260b28b702SAnirudh Venkataramanan * Variable link_up is true if link is up, false if link is down. 30270b28b702SAnirudh Venkataramanan * The variable link_up is invalid if status is non zero. As a 30280b28b702SAnirudh Venkataramanan * result of this call, link status reporting becomes enabled 30290b28b702SAnirudh Venkataramanan */ 30300b28b702SAnirudh Venkataramanan enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 30310b28b702SAnirudh Venkataramanan { 30320b28b702SAnirudh Venkataramanan struct ice_phy_info *phy_info; 30330b28b702SAnirudh Venkataramanan enum ice_status status = 0; 30340b28b702SAnirudh Venkataramanan 3035c7f2c42bSAnirudh Venkataramanan if (!pi || !link_up) 30360b28b702SAnirudh Venkataramanan return ICE_ERR_PARAM; 30370b28b702SAnirudh Venkataramanan 30380b28b702SAnirudh Venkataramanan phy_info = &pi->phy; 30390b28b702SAnirudh Venkataramanan 30400b28b702SAnirudh Venkataramanan if (phy_info->get_link_info) { 30410b28b702SAnirudh Venkataramanan status = ice_update_link_info(pi); 30420b28b702SAnirudh Venkataramanan 30430b28b702SAnirudh Venkataramanan if (status) 30449228d8b2SJacob Keller ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 30450b28b702SAnirudh Venkataramanan status); 30460b28b702SAnirudh Venkataramanan } 30470b28b702SAnirudh Venkataramanan 30480b28b702SAnirudh Venkataramanan *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 30490b28b702SAnirudh Venkataramanan 30500b28b702SAnirudh Venkataramanan return status; 30510b28b702SAnirudh Venkataramanan } 30520b28b702SAnirudh Venkataramanan 30530b28b702SAnirudh Venkataramanan /** 3054fcea6f3dSAnirudh Venkataramanan * ice_aq_set_link_restart_an 3055fcea6f3dSAnirudh Venkataramanan * @pi: pointer to the port information structure 3056fcea6f3dSAnirudh Venkataramanan * @ena_link: if true: enable link, if false: disable link 3057fcea6f3dSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 3058fcea6f3dSAnirudh Venkataramanan * 3059fcea6f3dSAnirudh Venkataramanan * Sets up the link and restarts the Auto-Negotiation over the link. 3060fcea6f3dSAnirudh Venkataramanan */ 3061fcea6f3dSAnirudh Venkataramanan enum ice_status 3062fcea6f3dSAnirudh Venkataramanan ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 3063fcea6f3dSAnirudh Venkataramanan struct ice_sq_cd *cd) 3064fcea6f3dSAnirudh Venkataramanan { 3065fcea6f3dSAnirudh Venkataramanan struct ice_aqc_restart_an *cmd; 3066fcea6f3dSAnirudh Venkataramanan struct ice_aq_desc desc; 3067fcea6f3dSAnirudh Venkataramanan 3068fcea6f3dSAnirudh Venkataramanan cmd = &desc.params.restart_an; 3069fcea6f3dSAnirudh Venkataramanan 3070fcea6f3dSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 3071fcea6f3dSAnirudh Venkataramanan 3072fcea6f3dSAnirudh Venkataramanan cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 3073fcea6f3dSAnirudh Venkataramanan cmd->lport_num = pi->lport; 3074fcea6f3dSAnirudh Venkataramanan if (ena_link) 3075fcea6f3dSAnirudh Venkataramanan cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 3076fcea6f3dSAnirudh Venkataramanan else 3077fcea6f3dSAnirudh Venkataramanan cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 3078fcea6f3dSAnirudh Venkataramanan 3079fcea6f3dSAnirudh Venkataramanan return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 3080fcea6f3dSAnirudh Venkataramanan } 3081fcea6f3dSAnirudh Venkataramanan 3082fcea6f3dSAnirudh Venkataramanan /** 3083250c3b3eSBrett Creeley * ice_aq_set_event_mask 3084250c3b3eSBrett Creeley * @hw: pointer to the HW struct 3085250c3b3eSBrett Creeley * @port_num: port number of the physical function 3086250c3b3eSBrett Creeley * @mask: event mask to be set 3087250c3b3eSBrett Creeley * @cd: pointer to command details structure or NULL 3088250c3b3eSBrett Creeley * 3089250c3b3eSBrett Creeley * Set event mask (0x0613) 3090250c3b3eSBrett Creeley */ 3091250c3b3eSBrett Creeley enum ice_status 3092250c3b3eSBrett Creeley ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 3093250c3b3eSBrett Creeley struct ice_sq_cd *cd) 3094250c3b3eSBrett Creeley { 3095250c3b3eSBrett Creeley struct ice_aqc_set_event_mask *cmd; 3096250c3b3eSBrett Creeley struct ice_aq_desc desc; 3097250c3b3eSBrett Creeley 3098250c3b3eSBrett Creeley cmd = &desc.params.set_event_mask; 3099250c3b3eSBrett Creeley 3100250c3b3eSBrett Creeley ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 3101250c3b3eSBrett Creeley 3102250c3b3eSBrett Creeley cmd->lport_num = port_num; 3103250c3b3eSBrett Creeley 3104250c3b3eSBrett Creeley cmd->event_mask = cpu_to_le16(mask); 3105250c3b3eSBrett Creeley return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 3106250c3b3eSBrett Creeley } 3107250c3b3eSBrett Creeley 3108250c3b3eSBrett Creeley /** 31090e674aebSAnirudh Venkataramanan * ice_aq_set_mac_loopback 31100e674aebSAnirudh Venkataramanan * @hw: pointer to the HW struct 31110e674aebSAnirudh Venkataramanan * @ena_lpbk: Enable or Disable loopback 31120e674aebSAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 31130e674aebSAnirudh Venkataramanan * 31140e674aebSAnirudh Venkataramanan * Enable/disable loopback on a given port 31150e674aebSAnirudh Venkataramanan */ 31160e674aebSAnirudh Venkataramanan enum ice_status 31170e674aebSAnirudh Venkataramanan ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 31180e674aebSAnirudh Venkataramanan { 31190e674aebSAnirudh Venkataramanan struct ice_aqc_set_mac_lb *cmd; 31200e674aebSAnirudh Venkataramanan struct ice_aq_desc desc; 31210e674aebSAnirudh Venkataramanan 31220e674aebSAnirudh Venkataramanan cmd = &desc.params.set_mac_lb; 31230e674aebSAnirudh Venkataramanan 31240e674aebSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 31250e674aebSAnirudh Venkataramanan if (ena_lpbk) 31260e674aebSAnirudh Venkataramanan cmd->lb_mode = ICE_AQ_MAC_LB_EN; 31270e674aebSAnirudh Venkataramanan 31280e674aebSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 31290e674aebSAnirudh Venkataramanan } 31300e674aebSAnirudh Venkataramanan 31310e674aebSAnirudh Venkataramanan /** 31328e151d50SAnirudh Venkataramanan * ice_aq_set_port_id_led 31338e151d50SAnirudh Venkataramanan * @pi: pointer to the port information 31348e151d50SAnirudh Venkataramanan * @is_orig_mode: is this LED set to original mode (by the net-list) 31358e151d50SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 31368e151d50SAnirudh Venkataramanan * 31378e151d50SAnirudh Venkataramanan * Set LED value for the given port (0x06e9) 31388e151d50SAnirudh Venkataramanan */ 31398e151d50SAnirudh Venkataramanan enum ice_status 31408e151d50SAnirudh Venkataramanan ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 31418e151d50SAnirudh Venkataramanan struct ice_sq_cd *cd) 31428e151d50SAnirudh Venkataramanan { 31438e151d50SAnirudh Venkataramanan struct ice_aqc_set_port_id_led *cmd; 31448e151d50SAnirudh Venkataramanan struct ice_hw *hw = pi->hw; 31458e151d50SAnirudh Venkataramanan struct ice_aq_desc desc; 31468e151d50SAnirudh Venkataramanan 31478e151d50SAnirudh Venkataramanan cmd = &desc.params.set_port_id_led; 31488e151d50SAnirudh Venkataramanan 31498e151d50SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 31508e151d50SAnirudh Venkataramanan 31518e151d50SAnirudh Venkataramanan if (is_orig_mode) 31528e151d50SAnirudh Venkataramanan cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 31538e151d50SAnirudh Venkataramanan else 31548e151d50SAnirudh Venkataramanan cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 31558e151d50SAnirudh Venkataramanan 31568e151d50SAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 31578e151d50SAnirudh Venkataramanan } 31588e151d50SAnirudh Venkataramanan 31598e151d50SAnirudh Venkataramanan /** 3160a012dca9SScott W Taylor * ice_aq_sff_eeprom 3161a012dca9SScott W Taylor * @hw: pointer to the HW struct 3162a012dca9SScott W Taylor * @lport: bits [7:0] = logical port, bit [8] = logical port valid 3163a012dca9SScott W Taylor * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 3164a012dca9SScott W Taylor * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 3165a012dca9SScott W Taylor * @page: QSFP page 3166a012dca9SScott W Taylor * @set_page: set or ignore the page 3167a012dca9SScott W Taylor * @data: pointer to data buffer to be read/written to the I2C device. 3168a012dca9SScott W Taylor * @length: 1-16 for read, 1 for write. 3169a012dca9SScott W Taylor * @write: 0 read, 1 for write. 3170a012dca9SScott W Taylor * @cd: pointer to command details structure or NULL 3171a012dca9SScott W Taylor * 3172a012dca9SScott W Taylor * Read/Write SFF EEPROM (0x06EE) 3173a012dca9SScott W Taylor */ 3174a012dca9SScott W Taylor enum ice_status 3175a012dca9SScott W Taylor ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 3176a012dca9SScott W Taylor u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 3177a012dca9SScott W Taylor bool write, struct ice_sq_cd *cd) 3178a012dca9SScott W Taylor { 3179a012dca9SScott W Taylor struct ice_aqc_sff_eeprom *cmd; 3180a012dca9SScott W Taylor struct ice_aq_desc desc; 3181a012dca9SScott W Taylor enum ice_status status; 3182a012dca9SScott W Taylor 3183a012dca9SScott W Taylor if (!data || (mem_addr & 0xff00)) 3184a012dca9SScott W Taylor return ICE_ERR_PARAM; 3185a012dca9SScott W Taylor 3186a012dca9SScott W Taylor ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 3187a012dca9SScott W Taylor cmd = &desc.params.read_write_sff_param; 3188a012dca9SScott W Taylor desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF); 3189a012dca9SScott W Taylor cmd->lport_num = (u8)(lport & 0xff); 3190a012dca9SScott W Taylor cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 3191a012dca9SScott W Taylor cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) & 3192a012dca9SScott W Taylor ICE_AQC_SFF_I2CBUS_7BIT_M) | 3193a012dca9SScott W Taylor ((set_page << 3194a012dca9SScott W Taylor ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 3195a012dca9SScott W Taylor ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 3196a012dca9SScott W Taylor cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); 3197a012dca9SScott W Taylor cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 3198a012dca9SScott W Taylor if (write) 3199a012dca9SScott W Taylor cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE); 3200a012dca9SScott W Taylor 3201a012dca9SScott W Taylor status = ice_aq_send_cmd(hw, &desc, data, length, cd); 3202a012dca9SScott W Taylor return status; 3203a012dca9SScott W Taylor } 3204a012dca9SScott W Taylor 3205a012dca9SScott W Taylor /** 3206d76a60baSAnirudh Venkataramanan * __ice_aq_get_set_rss_lut 3207d76a60baSAnirudh Venkataramanan * @hw: pointer to the hardware structure 3208d76a60baSAnirudh Venkataramanan * @vsi_id: VSI FW index 3209d76a60baSAnirudh Venkataramanan * @lut_type: LUT table type 3210d76a60baSAnirudh Venkataramanan * @lut: pointer to the LUT buffer provided by the caller 3211d76a60baSAnirudh Venkataramanan * @lut_size: size of the LUT buffer 3212d76a60baSAnirudh Venkataramanan * @glob_lut_idx: global LUT index 3213d76a60baSAnirudh Venkataramanan * @set: set true to set the table, false to get the table 3214d76a60baSAnirudh Venkataramanan * 3215d76a60baSAnirudh Venkataramanan * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 3216d76a60baSAnirudh Venkataramanan */ 3217d76a60baSAnirudh Venkataramanan static enum ice_status 3218d76a60baSAnirudh Venkataramanan __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, 3219d76a60baSAnirudh Venkataramanan u16 lut_size, u8 glob_lut_idx, bool set) 3220d76a60baSAnirudh Venkataramanan { 3221d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_lut *cmd_resp; 3222d76a60baSAnirudh Venkataramanan struct ice_aq_desc desc; 3223d76a60baSAnirudh Venkataramanan enum ice_status status; 3224d76a60baSAnirudh Venkataramanan u16 flags = 0; 3225d76a60baSAnirudh Venkataramanan 3226d76a60baSAnirudh Venkataramanan cmd_resp = &desc.params.get_set_rss_lut; 3227d76a60baSAnirudh Venkataramanan 3228d76a60baSAnirudh Venkataramanan if (set) { 3229d76a60baSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 3230d76a60baSAnirudh Venkataramanan desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3231d76a60baSAnirudh Venkataramanan } else { 3232d76a60baSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 3233d76a60baSAnirudh Venkataramanan } 3234d76a60baSAnirudh Venkataramanan 3235d76a60baSAnirudh Venkataramanan cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3236d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 3237d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 3238d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_VSI_VALID); 3239d76a60baSAnirudh Venkataramanan 3240d76a60baSAnirudh Venkataramanan switch (lut_type) { 3241d76a60baSAnirudh Venkataramanan case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 3242d76a60baSAnirudh Venkataramanan case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 3243d76a60baSAnirudh Venkataramanan case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 3244d76a60baSAnirudh Venkataramanan flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 3245d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 3246d76a60baSAnirudh Venkataramanan break; 3247d76a60baSAnirudh Venkataramanan default: 3248d76a60baSAnirudh Venkataramanan status = ICE_ERR_PARAM; 3249d76a60baSAnirudh Venkataramanan goto ice_aq_get_set_rss_lut_exit; 3250d76a60baSAnirudh Venkataramanan } 3251d76a60baSAnirudh Venkataramanan 3252d76a60baSAnirudh Venkataramanan if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 3253d76a60baSAnirudh Venkataramanan flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 3254d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 3255d76a60baSAnirudh Venkataramanan 3256d76a60baSAnirudh Venkataramanan if (!set) 3257d76a60baSAnirudh Venkataramanan goto ice_aq_get_set_rss_lut_send; 3258d76a60baSAnirudh Venkataramanan } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3259d76a60baSAnirudh Venkataramanan if (!set) 3260d76a60baSAnirudh Venkataramanan goto ice_aq_get_set_rss_lut_send; 3261d76a60baSAnirudh Venkataramanan } else { 3262d76a60baSAnirudh Venkataramanan goto ice_aq_get_set_rss_lut_send; 3263d76a60baSAnirudh Venkataramanan } 3264d76a60baSAnirudh Venkataramanan 3265d76a60baSAnirudh Venkataramanan /* LUT size is only valid for Global and PF table types */ 32664381147dSAnirudh Venkataramanan switch (lut_size) { 32674381147dSAnirudh Venkataramanan case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 32684381147dSAnirudh Venkataramanan break; 32694381147dSAnirudh Venkataramanan case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 3270d76a60baSAnirudh Venkataramanan flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 3271d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3272d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 32734381147dSAnirudh Venkataramanan break; 32744381147dSAnirudh Venkataramanan case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 32754381147dSAnirudh Venkataramanan if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 3276d76a60baSAnirudh Venkataramanan flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 3277d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 3278d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 32794381147dSAnirudh Venkataramanan break; 32804381147dSAnirudh Venkataramanan } 32814e83fc93SBruce Allan fallthrough; 32824381147dSAnirudh Venkataramanan default: 3283d76a60baSAnirudh Venkataramanan status = ICE_ERR_PARAM; 3284d76a60baSAnirudh Venkataramanan goto ice_aq_get_set_rss_lut_exit; 3285d76a60baSAnirudh Venkataramanan } 3286d76a60baSAnirudh Venkataramanan 3287d76a60baSAnirudh Venkataramanan ice_aq_get_set_rss_lut_send: 3288d76a60baSAnirudh Venkataramanan cmd_resp->flags = cpu_to_le16(flags); 3289d76a60baSAnirudh Venkataramanan status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 3290d76a60baSAnirudh Venkataramanan 3291d76a60baSAnirudh Venkataramanan ice_aq_get_set_rss_lut_exit: 3292d76a60baSAnirudh Venkataramanan return status; 3293d76a60baSAnirudh Venkataramanan } 3294d76a60baSAnirudh Venkataramanan 3295d76a60baSAnirudh Venkataramanan /** 3296d76a60baSAnirudh Venkataramanan * ice_aq_get_rss_lut 3297d76a60baSAnirudh Venkataramanan * @hw: pointer to the hardware structure 32984fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle 3299d76a60baSAnirudh Venkataramanan * @lut_type: LUT table type 3300d76a60baSAnirudh Venkataramanan * @lut: pointer to the LUT buffer provided by the caller 3301d76a60baSAnirudh Venkataramanan * @lut_size: size of the LUT buffer 3302d76a60baSAnirudh Venkataramanan * 3303d76a60baSAnirudh Venkataramanan * get the RSS lookup table, PF or VSI type 3304d76a60baSAnirudh Venkataramanan */ 3305d76a60baSAnirudh Venkataramanan enum ice_status 33064fb33f31SAnirudh Venkataramanan ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 33074fb33f31SAnirudh Venkataramanan u8 *lut, u16 lut_size) 3308d76a60baSAnirudh Venkataramanan { 33094fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 33104fb33f31SAnirudh Venkataramanan return ICE_ERR_PARAM; 33114fb33f31SAnirudh Venkataramanan 33124fb33f31SAnirudh Venkataramanan return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 33134fb33f31SAnirudh Venkataramanan lut_type, lut, lut_size, 0, false); 3314d76a60baSAnirudh Venkataramanan } 3315d76a60baSAnirudh Venkataramanan 3316d76a60baSAnirudh Venkataramanan /** 3317d76a60baSAnirudh Venkataramanan * ice_aq_set_rss_lut 3318d76a60baSAnirudh Venkataramanan * @hw: pointer to the hardware structure 33194fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle 3320d76a60baSAnirudh Venkataramanan * @lut_type: LUT table type 3321d76a60baSAnirudh Venkataramanan * @lut: pointer to the LUT buffer provided by the caller 3322d76a60baSAnirudh Venkataramanan * @lut_size: size of the LUT buffer 3323d76a60baSAnirudh Venkataramanan * 3324d76a60baSAnirudh Venkataramanan * set the RSS lookup table, PF or VSI type 3325d76a60baSAnirudh Venkataramanan */ 3326d76a60baSAnirudh Venkataramanan enum ice_status 33274fb33f31SAnirudh Venkataramanan ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, 33284fb33f31SAnirudh Venkataramanan u8 *lut, u16 lut_size) 3329d76a60baSAnirudh Venkataramanan { 33304fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 33314fb33f31SAnirudh Venkataramanan return ICE_ERR_PARAM; 33324fb33f31SAnirudh Venkataramanan 33334fb33f31SAnirudh Venkataramanan return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), 33344fb33f31SAnirudh Venkataramanan lut_type, lut, lut_size, 0, true); 3335d76a60baSAnirudh Venkataramanan } 3336d76a60baSAnirudh Venkataramanan 3337d76a60baSAnirudh Venkataramanan /** 3338d76a60baSAnirudh Venkataramanan * __ice_aq_get_set_rss_key 3339f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 3340d76a60baSAnirudh Venkataramanan * @vsi_id: VSI FW index 3341d76a60baSAnirudh Venkataramanan * @key: pointer to key info struct 3342d76a60baSAnirudh Venkataramanan * @set: set true to set the key, false to get the key 3343d76a60baSAnirudh Venkataramanan * 3344d76a60baSAnirudh Venkataramanan * get (0x0B04) or set (0x0B02) the RSS key per VSI 3345d76a60baSAnirudh Venkataramanan */ 3346d76a60baSAnirudh Venkataramanan static enum 3347d76a60baSAnirudh Venkataramanan ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 3348d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_keys *key, 3349d76a60baSAnirudh Venkataramanan bool set) 3350d76a60baSAnirudh Venkataramanan { 3351d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_key *cmd_resp; 3352d76a60baSAnirudh Venkataramanan u16 key_size = sizeof(*key); 3353d76a60baSAnirudh Venkataramanan struct ice_aq_desc desc; 3354d76a60baSAnirudh Venkataramanan 3355d76a60baSAnirudh Venkataramanan cmd_resp = &desc.params.get_set_rss_key; 3356d76a60baSAnirudh Venkataramanan 3357d76a60baSAnirudh Venkataramanan if (set) { 3358d76a60baSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 3359d76a60baSAnirudh Venkataramanan desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3360d76a60baSAnirudh Venkataramanan } else { 3361d76a60baSAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 3362d76a60baSAnirudh Venkataramanan } 3363d76a60baSAnirudh Venkataramanan 3364d76a60baSAnirudh Venkataramanan cmd_resp->vsi_id = cpu_to_le16(((vsi_id << 3365d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 3366d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 3367d76a60baSAnirudh Venkataramanan ICE_AQC_GSET_RSS_KEY_VSI_VALID); 3368d76a60baSAnirudh Venkataramanan 3369d76a60baSAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 3370d76a60baSAnirudh Venkataramanan } 3371d76a60baSAnirudh Venkataramanan 3372d76a60baSAnirudh Venkataramanan /** 3373d76a60baSAnirudh Venkataramanan * ice_aq_get_rss_key 3374f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 33754fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle 3376d76a60baSAnirudh Venkataramanan * @key: pointer to key info struct 3377d76a60baSAnirudh Venkataramanan * 3378d76a60baSAnirudh Venkataramanan * get the RSS key per VSI 3379d76a60baSAnirudh Venkataramanan */ 3380d76a60baSAnirudh Venkataramanan enum ice_status 33814fb33f31SAnirudh Venkataramanan ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 3382d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_keys *key) 3383d76a60baSAnirudh Venkataramanan { 33844fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 33854fb33f31SAnirudh Venkataramanan return ICE_ERR_PARAM; 33864fb33f31SAnirudh Venkataramanan 33874fb33f31SAnirudh Venkataramanan return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 33884fb33f31SAnirudh Venkataramanan key, false); 3389d76a60baSAnirudh Venkataramanan } 3390d76a60baSAnirudh Venkataramanan 3391d76a60baSAnirudh Venkataramanan /** 3392d76a60baSAnirudh Venkataramanan * ice_aq_set_rss_key 3393f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 33944fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle 3395d76a60baSAnirudh Venkataramanan * @keys: pointer to key info struct 3396d76a60baSAnirudh Venkataramanan * 3397d76a60baSAnirudh Venkataramanan * set the RSS key per VSI 3398d76a60baSAnirudh Venkataramanan */ 3399d76a60baSAnirudh Venkataramanan enum ice_status 34004fb33f31SAnirudh Venkataramanan ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 3401d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_keys *keys) 3402d76a60baSAnirudh Venkataramanan { 34034fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 34044fb33f31SAnirudh Venkataramanan return ICE_ERR_PARAM; 34054fb33f31SAnirudh Venkataramanan 34064fb33f31SAnirudh Venkataramanan return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 34074fb33f31SAnirudh Venkataramanan keys, true); 3408d76a60baSAnirudh Venkataramanan } 3409d76a60baSAnirudh Venkataramanan 3410d76a60baSAnirudh Venkataramanan /** 3411cdedef59SAnirudh Venkataramanan * ice_aq_add_lan_txq 3412cdedef59SAnirudh Venkataramanan * @hw: pointer to the hardware structure 3413cdedef59SAnirudh Venkataramanan * @num_qgrps: Number of added queue groups 3414cdedef59SAnirudh Venkataramanan * @qg_list: list of queue groups to be added 3415cdedef59SAnirudh Venkataramanan * @buf_size: size of buffer for indirect command 3416cdedef59SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 3417cdedef59SAnirudh Venkataramanan * 3418cdedef59SAnirudh Venkataramanan * Add Tx LAN queue (0x0C30) 3419cdedef59SAnirudh Venkataramanan * 3420cdedef59SAnirudh Venkataramanan * NOTE: 3421cdedef59SAnirudh Venkataramanan * Prior to calling add Tx LAN queue: 3422cdedef59SAnirudh Venkataramanan * Initialize the following as part of the Tx queue context: 3423cdedef59SAnirudh Venkataramanan * Completion queue ID if the queue uses Completion queue, Quanta profile, 3424cdedef59SAnirudh Venkataramanan * Cache profile and Packet shaper profile. 3425cdedef59SAnirudh Venkataramanan * 3426cdedef59SAnirudh Venkataramanan * After add Tx LAN queue AQ command is completed: 3427cdedef59SAnirudh Venkataramanan * Interrupts should be associated with specific queues, 3428cdedef59SAnirudh Venkataramanan * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 3429cdedef59SAnirudh Venkataramanan * flow. 3430cdedef59SAnirudh Venkataramanan */ 3431cdedef59SAnirudh Venkataramanan static enum ice_status 3432cdedef59SAnirudh Venkataramanan ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3433cdedef59SAnirudh Venkataramanan struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 3434cdedef59SAnirudh Venkataramanan struct ice_sq_cd *cd) 3435cdedef59SAnirudh Venkataramanan { 3436cdedef59SAnirudh Venkataramanan struct ice_aqc_add_tx_qgrp *list; 3437cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs *cmd; 3438cdedef59SAnirudh Venkataramanan struct ice_aq_desc desc; 343966486d89SBruce Allan u16 i, sum_size = 0; 3440cdedef59SAnirudh Venkataramanan 3441cdedef59SAnirudh Venkataramanan cmd = &desc.params.add_txqs; 3442cdedef59SAnirudh Venkataramanan 3443cdedef59SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 3444cdedef59SAnirudh Venkataramanan 3445cdedef59SAnirudh Venkataramanan if (!qg_list) 3446cdedef59SAnirudh Venkataramanan return ICE_ERR_PARAM; 3447cdedef59SAnirudh Venkataramanan 3448cdedef59SAnirudh Venkataramanan if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3449cdedef59SAnirudh Venkataramanan return ICE_ERR_PARAM; 3450cdedef59SAnirudh Venkataramanan 345166486d89SBruce Allan for (i = 0, list = qg_list; i < num_qgrps; i++) { 345266486d89SBruce Allan sum_size += struct_size(list, txqs, list->num_txqs); 345366486d89SBruce Allan list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 345466486d89SBruce Allan list->num_txqs); 3455cdedef59SAnirudh Venkataramanan } 3456cdedef59SAnirudh Venkataramanan 345766486d89SBruce Allan if (buf_size != sum_size) 3458cdedef59SAnirudh Venkataramanan return ICE_ERR_PARAM; 3459cdedef59SAnirudh Venkataramanan 3460cdedef59SAnirudh Venkataramanan desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3461cdedef59SAnirudh Venkataramanan 3462cdedef59SAnirudh Venkataramanan cmd->num_qgrps = num_qgrps; 3463cdedef59SAnirudh Venkataramanan 3464cdedef59SAnirudh Venkataramanan return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 3465cdedef59SAnirudh Venkataramanan } 3466cdedef59SAnirudh Venkataramanan 3467cdedef59SAnirudh Venkataramanan /** 3468cdedef59SAnirudh Venkataramanan * ice_aq_dis_lan_txq 3469cdedef59SAnirudh Venkataramanan * @hw: pointer to the hardware structure 3470cdedef59SAnirudh Venkataramanan * @num_qgrps: number of groups in the list 3471cdedef59SAnirudh Venkataramanan * @qg_list: the list of groups to disable 3472cdedef59SAnirudh Venkataramanan * @buf_size: the total size of the qg_list buffer in bytes 347394c4441bSAnirudh Venkataramanan * @rst_src: if called due to reset, specifies the reset source 3474ddf30f7fSAnirudh Venkataramanan * @vmvf_num: the relative VM or VF number that is undergoing the reset 3475cdedef59SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 3476cdedef59SAnirudh Venkataramanan * 3477cdedef59SAnirudh Venkataramanan * Disable LAN Tx queue (0x0C31) 3478cdedef59SAnirudh Venkataramanan */ 3479cdedef59SAnirudh Venkataramanan static enum ice_status 3480cdedef59SAnirudh Venkataramanan ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 3481cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 3482ddf30f7fSAnirudh Venkataramanan enum ice_disq_rst_src rst_src, u16 vmvf_num, 3483cdedef59SAnirudh Venkataramanan struct ice_sq_cd *cd) 3484cdedef59SAnirudh Venkataramanan { 348566486d89SBruce Allan struct ice_aqc_dis_txq_item *item; 3486cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txqs *cmd; 3487cdedef59SAnirudh Venkataramanan struct ice_aq_desc desc; 34886e9650d5SVictor Raj enum ice_status status; 3489cdedef59SAnirudh Venkataramanan u16 i, sz = 0; 3490cdedef59SAnirudh Venkataramanan 3491cdedef59SAnirudh Venkataramanan cmd = &desc.params.dis_txqs; 3492cdedef59SAnirudh Venkataramanan ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 3493cdedef59SAnirudh Venkataramanan 3494ddf30f7fSAnirudh Venkataramanan /* qg_list can be NULL only in VM/VF reset flow */ 3495ddf30f7fSAnirudh Venkataramanan if (!qg_list && !rst_src) 3496cdedef59SAnirudh Venkataramanan return ICE_ERR_PARAM; 3497cdedef59SAnirudh Venkataramanan 3498cdedef59SAnirudh Venkataramanan if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 3499cdedef59SAnirudh Venkataramanan return ICE_ERR_PARAM; 3500ddf30f7fSAnirudh Venkataramanan 3501cdedef59SAnirudh Venkataramanan cmd->num_entries = num_qgrps; 3502cdedef59SAnirudh Venkataramanan 3503ddf30f7fSAnirudh Venkataramanan cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 3504ddf30f7fSAnirudh Venkataramanan ICE_AQC_Q_DIS_TIMEOUT_M); 3505ddf30f7fSAnirudh Venkataramanan 3506ddf30f7fSAnirudh Venkataramanan switch (rst_src) { 3507ddf30f7fSAnirudh Venkataramanan case ICE_VM_RESET: 3508ddf30f7fSAnirudh Venkataramanan cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 3509ddf30f7fSAnirudh Venkataramanan cmd->vmvf_and_timeout |= 3510ddf30f7fSAnirudh Venkataramanan cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 3511ddf30f7fSAnirudh Venkataramanan break; 3512ddf30f7fSAnirudh Venkataramanan case ICE_VF_RESET: 3513ddf30f7fSAnirudh Venkataramanan cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 3514f9867df6SAnirudh Venkataramanan /* In this case, FW expects vmvf_num to be absolute VF ID */ 3515ddf30f7fSAnirudh Venkataramanan cmd->vmvf_and_timeout |= 3516ddf30f7fSAnirudh Venkataramanan cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) & 3517ddf30f7fSAnirudh Venkataramanan ICE_AQC_Q_DIS_VMVF_NUM_M); 3518ddf30f7fSAnirudh Venkataramanan break; 3519ddf30f7fSAnirudh Venkataramanan case ICE_NO_RESET: 3520ddf30f7fSAnirudh Venkataramanan default: 3521ddf30f7fSAnirudh Venkataramanan break; 3522ddf30f7fSAnirudh Venkataramanan } 3523ddf30f7fSAnirudh Venkataramanan 35246e9650d5SVictor Raj /* flush pipe on time out */ 35256e9650d5SVictor Raj cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 3526ddf30f7fSAnirudh Venkataramanan /* If no queue group info, we are in a reset flow. Issue the AQ */ 3527ddf30f7fSAnirudh Venkataramanan if (!qg_list) 3528ddf30f7fSAnirudh Venkataramanan goto do_aq; 3529ddf30f7fSAnirudh Venkataramanan 3530ddf30f7fSAnirudh Venkataramanan /* set RD bit to indicate that command buffer is provided by the driver 3531ddf30f7fSAnirudh Venkataramanan * and it needs to be read by the firmware 3532ddf30f7fSAnirudh Venkataramanan */ 3533ddf30f7fSAnirudh Venkataramanan desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD); 3534ddf30f7fSAnirudh Venkataramanan 353566486d89SBruce Allan for (i = 0, item = qg_list; i < num_qgrps; i++) { 353666486d89SBruce Allan u16 item_size = struct_size(item, q_id, item->num_qs); 3537cdedef59SAnirudh Venkataramanan 3538cdedef59SAnirudh Venkataramanan /* If the num of queues is even, add 2 bytes of padding */ 353966486d89SBruce Allan if ((item->num_qs % 2) == 0) 354066486d89SBruce Allan item_size += 2; 354166486d89SBruce Allan 354266486d89SBruce Allan sz += item_size; 354366486d89SBruce Allan 354466486d89SBruce Allan item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 3545cdedef59SAnirudh Venkataramanan } 3546cdedef59SAnirudh Venkataramanan 3547cdedef59SAnirudh Venkataramanan if (buf_size != sz) 3548cdedef59SAnirudh Venkataramanan return ICE_ERR_PARAM; 3549cdedef59SAnirudh Venkataramanan 3550ddf30f7fSAnirudh Venkataramanan do_aq: 35516e9650d5SVictor Raj status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 35526e9650d5SVictor Raj if (status) { 35536e9650d5SVictor Raj if (!qg_list) 35546e9650d5SVictor Raj ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 35556e9650d5SVictor Raj vmvf_num, hw->adminq.sq_last_status); 35566e9650d5SVictor Raj else 35572f2da36eSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 35586e9650d5SVictor Raj le16_to_cpu(qg_list[0].q_id[0]), 35596e9650d5SVictor Raj hw->adminq.sq_last_status); 35606e9650d5SVictor Raj } 35616e9650d5SVictor Raj return status; 3562cdedef59SAnirudh Venkataramanan } 3563cdedef59SAnirudh Venkataramanan 3564cdedef59SAnirudh Venkataramanan /* End of FW Admin Queue command wrappers */ 3565cdedef59SAnirudh Venkataramanan 3566cdedef59SAnirudh Venkataramanan /** 3567cdedef59SAnirudh Venkataramanan * ice_write_byte - write a byte to a packed context structure 3568cdedef59SAnirudh Venkataramanan * @src_ctx: the context structure to read from 3569cdedef59SAnirudh Venkataramanan * @dest_ctx: the context to be written to 3570cdedef59SAnirudh Venkataramanan * @ce_info: a description of the struct to be filled 3571cdedef59SAnirudh Venkataramanan */ 3572c8b7abddSBruce Allan static void 3573c8b7abddSBruce Allan ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3574cdedef59SAnirudh Venkataramanan { 3575cdedef59SAnirudh Venkataramanan u8 src_byte, dest_byte, mask; 3576cdedef59SAnirudh Venkataramanan u8 *from, *dest; 3577cdedef59SAnirudh Venkataramanan u16 shift_width; 3578cdedef59SAnirudh Venkataramanan 3579cdedef59SAnirudh Venkataramanan /* copy from the next struct field */ 3580cdedef59SAnirudh Venkataramanan from = src_ctx + ce_info->offset; 3581cdedef59SAnirudh Venkataramanan 3582cdedef59SAnirudh Venkataramanan /* prepare the bits and mask */ 3583cdedef59SAnirudh Venkataramanan shift_width = ce_info->lsb % 8; 3584cdedef59SAnirudh Venkataramanan mask = (u8)(BIT(ce_info->width) - 1); 3585cdedef59SAnirudh Venkataramanan 3586cdedef59SAnirudh Venkataramanan src_byte = *from; 3587cdedef59SAnirudh Venkataramanan src_byte &= mask; 3588cdedef59SAnirudh Venkataramanan 3589cdedef59SAnirudh Venkataramanan /* shift to correct alignment */ 3590cdedef59SAnirudh Venkataramanan mask <<= shift_width; 3591cdedef59SAnirudh Venkataramanan src_byte <<= shift_width; 3592cdedef59SAnirudh Venkataramanan 3593cdedef59SAnirudh Venkataramanan /* get the current bits from the target bit string */ 3594cdedef59SAnirudh Venkataramanan dest = dest_ctx + (ce_info->lsb / 8); 3595cdedef59SAnirudh Venkataramanan 3596cdedef59SAnirudh Venkataramanan memcpy(&dest_byte, dest, sizeof(dest_byte)); 3597cdedef59SAnirudh Venkataramanan 3598cdedef59SAnirudh Venkataramanan dest_byte &= ~mask; /* get the bits not changing */ 3599cdedef59SAnirudh Venkataramanan dest_byte |= src_byte; /* add in the new bits */ 3600cdedef59SAnirudh Venkataramanan 3601cdedef59SAnirudh Venkataramanan /* put it all back */ 3602cdedef59SAnirudh Venkataramanan memcpy(dest, &dest_byte, sizeof(dest_byte)); 3603cdedef59SAnirudh Venkataramanan } 3604cdedef59SAnirudh Venkataramanan 3605cdedef59SAnirudh Venkataramanan /** 3606cdedef59SAnirudh Venkataramanan * ice_write_word - write a word to a packed context structure 3607cdedef59SAnirudh Venkataramanan * @src_ctx: the context structure to read from 3608cdedef59SAnirudh Venkataramanan * @dest_ctx: the context to be written to 3609cdedef59SAnirudh Venkataramanan * @ce_info: a description of the struct to be filled 3610cdedef59SAnirudh Venkataramanan */ 3611c8b7abddSBruce Allan static void 3612c8b7abddSBruce Allan ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3613cdedef59SAnirudh Venkataramanan { 3614cdedef59SAnirudh Venkataramanan u16 src_word, mask; 3615cdedef59SAnirudh Venkataramanan __le16 dest_word; 3616cdedef59SAnirudh Venkataramanan u8 *from, *dest; 3617cdedef59SAnirudh Venkataramanan u16 shift_width; 3618cdedef59SAnirudh Venkataramanan 3619cdedef59SAnirudh Venkataramanan /* copy from the next struct field */ 3620cdedef59SAnirudh Venkataramanan from = src_ctx + ce_info->offset; 3621cdedef59SAnirudh Venkataramanan 3622cdedef59SAnirudh Venkataramanan /* prepare the bits and mask */ 3623cdedef59SAnirudh Venkataramanan shift_width = ce_info->lsb % 8; 3624cdedef59SAnirudh Venkataramanan mask = BIT(ce_info->width) - 1; 3625cdedef59SAnirudh Venkataramanan 3626cdedef59SAnirudh Venkataramanan /* don't swizzle the bits until after the mask because the mask bits 3627cdedef59SAnirudh Venkataramanan * will be in a different bit position on big endian machines 3628cdedef59SAnirudh Venkataramanan */ 3629cdedef59SAnirudh Venkataramanan src_word = *(u16 *)from; 3630cdedef59SAnirudh Venkataramanan src_word &= mask; 3631cdedef59SAnirudh Venkataramanan 3632cdedef59SAnirudh Venkataramanan /* shift to correct alignment */ 3633cdedef59SAnirudh Venkataramanan mask <<= shift_width; 3634cdedef59SAnirudh Venkataramanan src_word <<= shift_width; 3635cdedef59SAnirudh Venkataramanan 3636cdedef59SAnirudh Venkataramanan /* get the current bits from the target bit string */ 3637cdedef59SAnirudh Venkataramanan dest = dest_ctx + (ce_info->lsb / 8); 3638cdedef59SAnirudh Venkataramanan 3639cdedef59SAnirudh Venkataramanan memcpy(&dest_word, dest, sizeof(dest_word)); 3640cdedef59SAnirudh Venkataramanan 3641cdedef59SAnirudh Venkataramanan dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */ 3642cdedef59SAnirudh Venkataramanan dest_word |= cpu_to_le16(src_word); /* add in the new bits */ 3643cdedef59SAnirudh Venkataramanan 3644cdedef59SAnirudh Venkataramanan /* put it all back */ 3645cdedef59SAnirudh Venkataramanan memcpy(dest, &dest_word, sizeof(dest_word)); 3646cdedef59SAnirudh Venkataramanan } 3647cdedef59SAnirudh Venkataramanan 3648cdedef59SAnirudh Venkataramanan /** 3649cdedef59SAnirudh Venkataramanan * ice_write_dword - write a dword to a packed context structure 3650cdedef59SAnirudh Venkataramanan * @src_ctx: the context structure to read from 3651cdedef59SAnirudh Venkataramanan * @dest_ctx: the context to be written to 3652cdedef59SAnirudh Venkataramanan * @ce_info: a description of the struct to be filled 3653cdedef59SAnirudh Venkataramanan */ 3654c8b7abddSBruce Allan static void 3655c8b7abddSBruce Allan ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3656cdedef59SAnirudh Venkataramanan { 3657cdedef59SAnirudh Venkataramanan u32 src_dword, mask; 3658cdedef59SAnirudh Venkataramanan __le32 dest_dword; 3659cdedef59SAnirudh Venkataramanan u8 *from, *dest; 3660cdedef59SAnirudh Venkataramanan u16 shift_width; 3661cdedef59SAnirudh Venkataramanan 3662cdedef59SAnirudh Venkataramanan /* copy from the next struct field */ 3663cdedef59SAnirudh Venkataramanan from = src_ctx + ce_info->offset; 3664cdedef59SAnirudh Venkataramanan 3665cdedef59SAnirudh Venkataramanan /* prepare the bits and mask */ 3666cdedef59SAnirudh Venkataramanan shift_width = ce_info->lsb % 8; 3667cdedef59SAnirudh Venkataramanan 3668cdedef59SAnirudh Venkataramanan /* if the field width is exactly 32 on an x86 machine, then the shift 3669cdedef59SAnirudh Venkataramanan * operation will not work because the SHL instructions count is masked 3670cdedef59SAnirudh Venkataramanan * to 5 bits so the shift will do nothing 3671cdedef59SAnirudh Venkataramanan */ 3672cdedef59SAnirudh Venkataramanan if (ce_info->width < 32) 3673cdedef59SAnirudh Venkataramanan mask = BIT(ce_info->width) - 1; 3674cdedef59SAnirudh Venkataramanan else 3675cdedef59SAnirudh Venkataramanan mask = (u32)~0; 3676cdedef59SAnirudh Venkataramanan 3677cdedef59SAnirudh Venkataramanan /* don't swizzle the bits until after the mask because the mask bits 3678cdedef59SAnirudh Venkataramanan * will be in a different bit position on big endian machines 3679cdedef59SAnirudh Venkataramanan */ 3680cdedef59SAnirudh Venkataramanan src_dword = *(u32 *)from; 3681cdedef59SAnirudh Venkataramanan src_dword &= mask; 3682cdedef59SAnirudh Venkataramanan 3683cdedef59SAnirudh Venkataramanan /* shift to correct alignment */ 3684cdedef59SAnirudh Venkataramanan mask <<= shift_width; 3685cdedef59SAnirudh Venkataramanan src_dword <<= shift_width; 3686cdedef59SAnirudh Venkataramanan 3687cdedef59SAnirudh Venkataramanan /* get the current bits from the target bit string */ 3688cdedef59SAnirudh Venkataramanan dest = dest_ctx + (ce_info->lsb / 8); 3689cdedef59SAnirudh Venkataramanan 3690cdedef59SAnirudh Venkataramanan memcpy(&dest_dword, dest, sizeof(dest_dword)); 3691cdedef59SAnirudh Venkataramanan 3692cdedef59SAnirudh Venkataramanan dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */ 3693cdedef59SAnirudh Venkataramanan dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */ 3694cdedef59SAnirudh Venkataramanan 3695cdedef59SAnirudh Venkataramanan /* put it all back */ 3696cdedef59SAnirudh Venkataramanan memcpy(dest, &dest_dword, sizeof(dest_dword)); 3697cdedef59SAnirudh Venkataramanan } 3698cdedef59SAnirudh Venkataramanan 3699cdedef59SAnirudh Venkataramanan /** 3700cdedef59SAnirudh Venkataramanan * ice_write_qword - write a qword to a packed context structure 3701cdedef59SAnirudh Venkataramanan * @src_ctx: the context structure to read from 3702cdedef59SAnirudh Venkataramanan * @dest_ctx: the context to be written to 3703cdedef59SAnirudh Venkataramanan * @ce_info: a description of the struct to be filled 3704cdedef59SAnirudh Venkataramanan */ 3705c8b7abddSBruce Allan static void 3706c8b7abddSBruce Allan ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 3707cdedef59SAnirudh Venkataramanan { 3708cdedef59SAnirudh Venkataramanan u64 src_qword, mask; 3709cdedef59SAnirudh Venkataramanan __le64 dest_qword; 3710cdedef59SAnirudh Venkataramanan u8 *from, *dest; 3711cdedef59SAnirudh Venkataramanan u16 shift_width; 3712cdedef59SAnirudh Venkataramanan 3713cdedef59SAnirudh Venkataramanan /* copy from the next struct field */ 3714cdedef59SAnirudh Venkataramanan from = src_ctx + ce_info->offset; 3715cdedef59SAnirudh Venkataramanan 3716cdedef59SAnirudh Venkataramanan /* prepare the bits and mask */ 3717cdedef59SAnirudh Venkataramanan shift_width = ce_info->lsb % 8; 3718cdedef59SAnirudh Venkataramanan 3719cdedef59SAnirudh Venkataramanan /* if the field width is exactly 64 on an x86 machine, then the shift 3720cdedef59SAnirudh Venkataramanan * operation will not work because the SHL instructions count is masked 3721cdedef59SAnirudh Venkataramanan * to 6 bits so the shift will do nothing 3722cdedef59SAnirudh Venkataramanan */ 3723cdedef59SAnirudh Venkataramanan if (ce_info->width < 64) 3724cdedef59SAnirudh Venkataramanan mask = BIT_ULL(ce_info->width) - 1; 3725cdedef59SAnirudh Venkataramanan else 3726cdedef59SAnirudh Venkataramanan mask = (u64)~0; 3727cdedef59SAnirudh Venkataramanan 3728cdedef59SAnirudh Venkataramanan /* don't swizzle the bits until after the mask because the mask bits 3729cdedef59SAnirudh Venkataramanan * will be in a different bit position on big endian machines 3730cdedef59SAnirudh Venkataramanan */ 3731cdedef59SAnirudh Venkataramanan src_qword = *(u64 *)from; 3732cdedef59SAnirudh Venkataramanan src_qword &= mask; 3733cdedef59SAnirudh Venkataramanan 3734cdedef59SAnirudh Venkataramanan /* shift to correct alignment */ 3735cdedef59SAnirudh Venkataramanan mask <<= shift_width; 3736cdedef59SAnirudh Venkataramanan src_qword <<= shift_width; 3737cdedef59SAnirudh Venkataramanan 3738cdedef59SAnirudh Venkataramanan /* get the current bits from the target bit string */ 3739cdedef59SAnirudh Venkataramanan dest = dest_ctx + (ce_info->lsb / 8); 3740cdedef59SAnirudh Venkataramanan 3741cdedef59SAnirudh Venkataramanan memcpy(&dest_qword, dest, sizeof(dest_qword)); 3742cdedef59SAnirudh Venkataramanan 3743cdedef59SAnirudh Venkataramanan dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */ 3744cdedef59SAnirudh Venkataramanan dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */ 3745cdedef59SAnirudh Venkataramanan 3746cdedef59SAnirudh Venkataramanan /* put it all back */ 3747cdedef59SAnirudh Venkataramanan memcpy(dest, &dest_qword, sizeof(dest_qword)); 3748cdedef59SAnirudh Venkataramanan } 3749cdedef59SAnirudh Venkataramanan 3750cdedef59SAnirudh Venkataramanan /** 3751cdedef59SAnirudh Venkataramanan * ice_set_ctx - set context bits in packed structure 37527e34786aSBruce Allan * @hw: pointer to the hardware structure 3753cdedef59SAnirudh Venkataramanan * @src_ctx: pointer to a generic non-packed context structure 3754cdedef59SAnirudh Venkataramanan * @dest_ctx: pointer to memory for the packed structure 3755cdedef59SAnirudh Venkataramanan * @ce_info: a description of the structure to be transformed 3756cdedef59SAnirudh Venkataramanan */ 3757cdedef59SAnirudh Venkataramanan enum ice_status 37587e34786aSBruce Allan ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 37597e34786aSBruce Allan const struct ice_ctx_ele *ce_info) 3760cdedef59SAnirudh Venkataramanan { 3761cdedef59SAnirudh Venkataramanan int f; 3762cdedef59SAnirudh Venkataramanan 3763cdedef59SAnirudh Venkataramanan for (f = 0; ce_info[f].width; f++) { 3764cdedef59SAnirudh Venkataramanan /* We have to deal with each element of the FW response 3765cdedef59SAnirudh Venkataramanan * using the correct size so that we are correct regardless 3766cdedef59SAnirudh Venkataramanan * of the endianness of the machine. 3767cdedef59SAnirudh Venkataramanan */ 37687e34786aSBruce Allan if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 37699228d8b2SJacob Keller ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 37707e34786aSBruce Allan f, ce_info[f].width, ce_info[f].size_of); 37717e34786aSBruce Allan continue; 37727e34786aSBruce Allan } 3773cdedef59SAnirudh Venkataramanan switch (ce_info[f].size_of) { 3774cdedef59SAnirudh Venkataramanan case sizeof(u8): 3775cdedef59SAnirudh Venkataramanan ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 3776cdedef59SAnirudh Venkataramanan break; 3777cdedef59SAnirudh Venkataramanan case sizeof(u16): 3778cdedef59SAnirudh Venkataramanan ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 3779cdedef59SAnirudh Venkataramanan break; 3780cdedef59SAnirudh Venkataramanan case sizeof(u32): 3781cdedef59SAnirudh Venkataramanan ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 3782cdedef59SAnirudh Venkataramanan break; 3783cdedef59SAnirudh Venkataramanan case sizeof(u64): 3784cdedef59SAnirudh Venkataramanan ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 3785cdedef59SAnirudh Venkataramanan break; 3786cdedef59SAnirudh Venkataramanan default: 3787cdedef59SAnirudh Venkataramanan return ICE_ERR_INVAL_SIZE; 3788cdedef59SAnirudh Venkataramanan } 3789cdedef59SAnirudh Venkataramanan } 3790cdedef59SAnirudh Venkataramanan 3791cdedef59SAnirudh Venkataramanan return 0; 3792cdedef59SAnirudh Venkataramanan } 3793cdedef59SAnirudh Venkataramanan 3794cdedef59SAnirudh Venkataramanan /** 3795bb87ee0eSAnirudh Venkataramanan * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 3796bb87ee0eSAnirudh Venkataramanan * @hw: pointer to the HW struct 3797bb87ee0eSAnirudh Venkataramanan * @vsi_handle: software VSI handle 3798bb87ee0eSAnirudh Venkataramanan * @tc: TC number 3799bb87ee0eSAnirudh Venkataramanan * @q_handle: software queue handle 3800bb87ee0eSAnirudh Venkataramanan */ 38011ddef455SUsha Ketineni struct ice_q_ctx * 3802bb87ee0eSAnirudh Venkataramanan ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 3803bb87ee0eSAnirudh Venkataramanan { 3804bb87ee0eSAnirudh Venkataramanan struct ice_vsi_ctx *vsi; 3805bb87ee0eSAnirudh Venkataramanan struct ice_q_ctx *q_ctx; 3806bb87ee0eSAnirudh Venkataramanan 3807bb87ee0eSAnirudh Venkataramanan vsi = ice_get_vsi_ctx(hw, vsi_handle); 3808bb87ee0eSAnirudh Venkataramanan if (!vsi) 3809bb87ee0eSAnirudh Venkataramanan return NULL; 3810bb87ee0eSAnirudh Venkataramanan if (q_handle >= vsi->num_lan_q_entries[tc]) 3811bb87ee0eSAnirudh Venkataramanan return NULL; 3812bb87ee0eSAnirudh Venkataramanan if (!vsi->lan_q_ctx[tc]) 3813bb87ee0eSAnirudh Venkataramanan return NULL; 3814bb87ee0eSAnirudh Venkataramanan q_ctx = vsi->lan_q_ctx[tc]; 3815bb87ee0eSAnirudh Venkataramanan return &q_ctx[q_handle]; 3816bb87ee0eSAnirudh Venkataramanan } 3817bb87ee0eSAnirudh Venkataramanan 3818bb87ee0eSAnirudh Venkataramanan /** 3819cdedef59SAnirudh Venkataramanan * ice_ena_vsi_txq 3820cdedef59SAnirudh Venkataramanan * @pi: port information structure 38214fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle 3822f9867df6SAnirudh Venkataramanan * @tc: TC number 3823bb87ee0eSAnirudh Venkataramanan * @q_handle: software queue handle 3824cdedef59SAnirudh Venkataramanan * @num_qgrps: Number of added queue groups 3825cdedef59SAnirudh Venkataramanan * @buf: list of queue groups to be added 3826cdedef59SAnirudh Venkataramanan * @buf_size: size of buffer for indirect command 3827cdedef59SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 3828cdedef59SAnirudh Venkataramanan * 3829f9867df6SAnirudh Venkataramanan * This function adds one LAN queue 3830cdedef59SAnirudh Venkataramanan */ 3831cdedef59SAnirudh Venkataramanan enum ice_status 3832bb87ee0eSAnirudh Venkataramanan ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 3833bb87ee0eSAnirudh Venkataramanan u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 3834cdedef59SAnirudh Venkataramanan struct ice_sq_cd *cd) 3835cdedef59SAnirudh Venkataramanan { 3836cdedef59SAnirudh Venkataramanan struct ice_aqc_txsched_elem_data node = { 0 }; 3837cdedef59SAnirudh Venkataramanan struct ice_sched_node *parent; 3838bb87ee0eSAnirudh Venkataramanan struct ice_q_ctx *q_ctx; 3839cdedef59SAnirudh Venkataramanan enum ice_status status; 3840cdedef59SAnirudh Venkataramanan struct ice_hw *hw; 3841cdedef59SAnirudh Venkataramanan 3842cdedef59SAnirudh Venkataramanan if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3843cdedef59SAnirudh Venkataramanan return ICE_ERR_CFG; 3844cdedef59SAnirudh Venkataramanan 3845cdedef59SAnirudh Venkataramanan if (num_qgrps > 1 || buf->num_txqs > 1) 3846cdedef59SAnirudh Venkataramanan return ICE_ERR_MAX_LIMIT; 3847cdedef59SAnirudh Venkataramanan 3848cdedef59SAnirudh Venkataramanan hw = pi->hw; 3849cdedef59SAnirudh Venkataramanan 38504fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle)) 38514fb33f31SAnirudh Venkataramanan return ICE_ERR_PARAM; 38524fb33f31SAnirudh Venkataramanan 3853cdedef59SAnirudh Venkataramanan mutex_lock(&pi->sched_lock); 3854cdedef59SAnirudh Venkataramanan 3855bb87ee0eSAnirudh Venkataramanan q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 3856bb87ee0eSAnirudh Venkataramanan if (!q_ctx) { 3857bb87ee0eSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 3858bb87ee0eSAnirudh Venkataramanan q_handle); 3859bb87ee0eSAnirudh Venkataramanan status = ICE_ERR_PARAM; 3860bb87ee0eSAnirudh Venkataramanan goto ena_txq_exit; 3861bb87ee0eSAnirudh Venkataramanan } 3862bb87ee0eSAnirudh Venkataramanan 3863cdedef59SAnirudh Venkataramanan /* find a parent node */ 38644fb33f31SAnirudh Venkataramanan parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 3865cdedef59SAnirudh Venkataramanan ICE_SCHED_NODE_OWNER_LAN); 3866cdedef59SAnirudh Venkataramanan if (!parent) { 3867cdedef59SAnirudh Venkataramanan status = ICE_ERR_PARAM; 3868cdedef59SAnirudh Venkataramanan goto ena_txq_exit; 3869cdedef59SAnirudh Venkataramanan } 38704fb33f31SAnirudh Venkataramanan 3871cdedef59SAnirudh Venkataramanan buf->parent_teid = parent->info.node_teid; 3872cdedef59SAnirudh Venkataramanan node.parent_teid = parent->info.node_teid; 3873cdedef59SAnirudh Venkataramanan /* Mark that the values in the "generic" section as valid. The default 3874cdedef59SAnirudh Venkataramanan * value in the "generic" section is zero. This means that : 3875cdedef59SAnirudh Venkataramanan * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 3876cdedef59SAnirudh Venkataramanan * - 0 priority among siblings, indicated by Bit 1-3. 3877cdedef59SAnirudh Venkataramanan * - WFQ, indicated by Bit 4. 3878cdedef59SAnirudh Venkataramanan * - 0 Adjustment value is used in PSM credit update flow, indicated by 3879cdedef59SAnirudh Venkataramanan * Bit 5-6. 3880cdedef59SAnirudh Venkataramanan * - Bit 7 is reserved. 3881cdedef59SAnirudh Venkataramanan * Without setting the generic section as valid in valid_sections, the 3882f9867df6SAnirudh Venkataramanan * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 3883cdedef59SAnirudh Venkataramanan */ 3884984824a2STarun Singh buf->txqs[0].info.valid_sections = 3885984824a2STarun Singh ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 3886984824a2STarun Singh ICE_AQC_ELEM_VALID_EIR; 3887984824a2STarun Singh buf->txqs[0].info.generic = 0; 3888984824a2STarun Singh buf->txqs[0].info.cir_bw.bw_profile_idx = 3889984824a2STarun Singh cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 3890984824a2STarun Singh buf->txqs[0].info.cir_bw.bw_alloc = 3891984824a2STarun Singh cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 3892984824a2STarun Singh buf->txqs[0].info.eir_bw.bw_profile_idx = 3893984824a2STarun Singh cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID); 3894984824a2STarun Singh buf->txqs[0].info.eir_bw.bw_alloc = 3895984824a2STarun Singh cpu_to_le16(ICE_SCHED_DFLT_BW_WT); 3896cdedef59SAnirudh Venkataramanan 3897f9867df6SAnirudh Venkataramanan /* add the LAN queue */ 3898cdedef59SAnirudh Venkataramanan status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 38996e9650d5SVictor Raj if (status) { 3900bb87ee0eSAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 39016e9650d5SVictor Raj le16_to_cpu(buf->txqs[0].txq_id), 39026e9650d5SVictor Raj hw->adminq.sq_last_status); 3903cdedef59SAnirudh Venkataramanan goto ena_txq_exit; 39046e9650d5SVictor Raj } 3905cdedef59SAnirudh Venkataramanan 3906cdedef59SAnirudh Venkataramanan node.node_teid = buf->txqs[0].q_teid; 3907cdedef59SAnirudh Venkataramanan node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 3908bb87ee0eSAnirudh Venkataramanan q_ctx->q_handle = q_handle; 39091ddef455SUsha Ketineni q_ctx->q_teid = le32_to_cpu(node.node_teid); 3910cdedef59SAnirudh Venkataramanan 39111ddef455SUsha Ketineni /* add a leaf node into scheduler tree queue layer */ 3912cdedef59SAnirudh Venkataramanan status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 39131ddef455SUsha Ketineni if (!status) 39141ddef455SUsha Ketineni status = ice_sched_replay_q_bw(pi, q_ctx); 3915cdedef59SAnirudh Venkataramanan 3916cdedef59SAnirudh Venkataramanan ena_txq_exit: 3917cdedef59SAnirudh Venkataramanan mutex_unlock(&pi->sched_lock); 3918cdedef59SAnirudh Venkataramanan return status; 3919cdedef59SAnirudh Venkataramanan } 3920cdedef59SAnirudh Venkataramanan 3921cdedef59SAnirudh Venkataramanan /** 3922cdedef59SAnirudh Venkataramanan * ice_dis_vsi_txq 3923cdedef59SAnirudh Venkataramanan * @pi: port information structure 3924bb87ee0eSAnirudh Venkataramanan * @vsi_handle: software VSI handle 3925bb87ee0eSAnirudh Venkataramanan * @tc: TC number 3926cdedef59SAnirudh Venkataramanan * @num_queues: number of queues 3927bb87ee0eSAnirudh Venkataramanan * @q_handles: pointer to software queue handle array 3928cdedef59SAnirudh Venkataramanan * @q_ids: pointer to the q_id array 3929cdedef59SAnirudh Venkataramanan * @q_teids: pointer to queue node teids 393094c4441bSAnirudh Venkataramanan * @rst_src: if called due to reset, specifies the reset source 3931ddf30f7fSAnirudh Venkataramanan * @vmvf_num: the relative VM or VF number that is undergoing the reset 3932cdedef59SAnirudh Venkataramanan * @cd: pointer to command details structure or NULL 3933cdedef59SAnirudh Venkataramanan * 3934cdedef59SAnirudh Venkataramanan * This function removes queues and their corresponding nodes in SW DB 3935cdedef59SAnirudh Venkataramanan */ 3936cdedef59SAnirudh Venkataramanan enum ice_status 3937bb87ee0eSAnirudh Venkataramanan ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 3938bb87ee0eSAnirudh Venkataramanan u16 *q_handles, u16 *q_ids, u32 *q_teids, 3939bb87ee0eSAnirudh Venkataramanan enum ice_disq_rst_src rst_src, u16 vmvf_num, 3940ddf30f7fSAnirudh Venkataramanan struct ice_sq_cd *cd) 3941cdedef59SAnirudh Venkataramanan { 3942cdedef59SAnirudh Venkataramanan enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 394366486d89SBruce Allan struct ice_aqc_dis_txq_item *qg_list; 3944bb87ee0eSAnirudh Venkataramanan struct ice_q_ctx *q_ctx; 394566486d89SBruce Allan struct ice_hw *hw; 394666486d89SBruce Allan u16 i, buf_size; 3947cdedef59SAnirudh Venkataramanan 3948cdedef59SAnirudh Venkataramanan if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 3949cdedef59SAnirudh Venkataramanan return ICE_ERR_CFG; 3950cdedef59SAnirudh Venkataramanan 395166486d89SBruce Allan hw = pi->hw; 395266486d89SBruce Allan 395385796d6eSAkeem G Abodunrin if (!num_queues) { 395485796d6eSAkeem G Abodunrin /* if queue is disabled already yet the disable queue command 395585796d6eSAkeem G Abodunrin * has to be sent to complete the VF reset, then call 395685796d6eSAkeem G Abodunrin * ice_aq_dis_lan_txq without any queue information 395785796d6eSAkeem G Abodunrin */ 395885796d6eSAkeem G Abodunrin if (rst_src) 395966486d89SBruce Allan return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 396085796d6eSAkeem G Abodunrin vmvf_num, NULL); 396185796d6eSAkeem G Abodunrin return ICE_ERR_CFG; 396285796d6eSAkeem G Abodunrin } 3963ddf30f7fSAnirudh Venkataramanan 396466486d89SBruce Allan buf_size = struct_size(qg_list, q_id, 1); 396566486d89SBruce Allan qg_list = kzalloc(buf_size, GFP_KERNEL); 396666486d89SBruce Allan if (!qg_list) 396766486d89SBruce Allan return ICE_ERR_NO_MEMORY; 396866486d89SBruce Allan 3969cdedef59SAnirudh Venkataramanan mutex_lock(&pi->sched_lock); 3970cdedef59SAnirudh Venkataramanan 3971cdedef59SAnirudh Venkataramanan for (i = 0; i < num_queues; i++) { 3972cdedef59SAnirudh Venkataramanan struct ice_sched_node *node; 3973cdedef59SAnirudh Venkataramanan 3974cdedef59SAnirudh Venkataramanan node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 3975cdedef59SAnirudh Venkataramanan if (!node) 3976cdedef59SAnirudh Venkataramanan continue; 397766486d89SBruce Allan q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 3978bb87ee0eSAnirudh Venkataramanan if (!q_ctx) { 397966486d89SBruce Allan ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 3980bb87ee0eSAnirudh Venkataramanan q_handles[i]); 3981bb87ee0eSAnirudh Venkataramanan continue; 3982bb87ee0eSAnirudh Venkataramanan } 3983bb87ee0eSAnirudh Venkataramanan if (q_ctx->q_handle != q_handles[i]) { 398466486d89SBruce Allan ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 3985bb87ee0eSAnirudh Venkataramanan q_ctx->q_handle, q_handles[i]); 3986bb87ee0eSAnirudh Venkataramanan continue; 3987bb87ee0eSAnirudh Venkataramanan } 398866486d89SBruce Allan qg_list->parent_teid = node->info.parent_teid; 398966486d89SBruce Allan qg_list->num_qs = 1; 399066486d89SBruce Allan qg_list->q_id[0] = cpu_to_le16(q_ids[i]); 399166486d89SBruce Allan status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 399266486d89SBruce Allan vmvf_num, cd); 3993cdedef59SAnirudh Venkataramanan 3994cdedef59SAnirudh Venkataramanan if (status) 3995cdedef59SAnirudh Venkataramanan break; 3996cdedef59SAnirudh Venkataramanan ice_free_sched_node(pi, node); 3997bb87ee0eSAnirudh Venkataramanan q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 3998cdedef59SAnirudh Venkataramanan } 3999cdedef59SAnirudh Venkataramanan mutex_unlock(&pi->sched_lock); 400066486d89SBruce Allan kfree(qg_list); 4001cdedef59SAnirudh Venkataramanan return status; 4002cdedef59SAnirudh Venkataramanan } 40035513b920SAnirudh Venkataramanan 40045513b920SAnirudh Venkataramanan /** 400594c4441bSAnirudh Venkataramanan * ice_cfg_vsi_qs - configure the new/existing VSI queues 40065513b920SAnirudh Venkataramanan * @pi: port information structure 40074fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle 40085513b920SAnirudh Venkataramanan * @tc_bitmap: TC bitmap 40095513b920SAnirudh Venkataramanan * @maxqs: max queues array per TC 4010f9867df6SAnirudh Venkataramanan * @owner: LAN or RDMA 40115513b920SAnirudh Venkataramanan * 40125513b920SAnirudh Venkataramanan * This function adds/updates the VSI queues per TC. 40135513b920SAnirudh Venkataramanan */ 40145513b920SAnirudh Venkataramanan static enum ice_status 40154fb33f31SAnirudh Venkataramanan ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 40165513b920SAnirudh Venkataramanan u16 *maxqs, u8 owner) 40175513b920SAnirudh Venkataramanan { 40185513b920SAnirudh Venkataramanan enum ice_status status = 0; 40195513b920SAnirudh Venkataramanan u8 i; 40205513b920SAnirudh Venkataramanan 40215513b920SAnirudh Venkataramanan if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 40225513b920SAnirudh Venkataramanan return ICE_ERR_CFG; 40235513b920SAnirudh Venkataramanan 40244fb33f31SAnirudh Venkataramanan if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 40254fb33f31SAnirudh Venkataramanan return ICE_ERR_PARAM; 40264fb33f31SAnirudh Venkataramanan 40275513b920SAnirudh Venkataramanan mutex_lock(&pi->sched_lock); 40285513b920SAnirudh Venkataramanan 40292bdc97beSBruce Allan ice_for_each_traffic_class(i) { 40305513b920SAnirudh Venkataramanan /* configuration is possible only if TC node is present */ 40315513b920SAnirudh Venkataramanan if (!ice_sched_get_tc_node(pi, i)) 40325513b920SAnirudh Venkataramanan continue; 40335513b920SAnirudh Venkataramanan 40344fb33f31SAnirudh Venkataramanan status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 40355513b920SAnirudh Venkataramanan ice_is_tc_ena(tc_bitmap, i)); 40365513b920SAnirudh Venkataramanan if (status) 40375513b920SAnirudh Venkataramanan break; 40385513b920SAnirudh Venkataramanan } 40395513b920SAnirudh Venkataramanan 40405513b920SAnirudh Venkataramanan mutex_unlock(&pi->sched_lock); 40415513b920SAnirudh Venkataramanan return status; 40425513b920SAnirudh Venkataramanan } 40435513b920SAnirudh Venkataramanan 40445513b920SAnirudh Venkataramanan /** 4045f9867df6SAnirudh Venkataramanan * ice_cfg_vsi_lan - configure VSI LAN queues 40465513b920SAnirudh Venkataramanan * @pi: port information structure 40474fb33f31SAnirudh Venkataramanan * @vsi_handle: software VSI handle 40485513b920SAnirudh Venkataramanan * @tc_bitmap: TC bitmap 4049f9867df6SAnirudh Venkataramanan * @max_lanqs: max LAN queues array per TC 40505513b920SAnirudh Venkataramanan * 4051f9867df6SAnirudh Venkataramanan * This function adds/updates the VSI LAN queues per TC. 40525513b920SAnirudh Venkataramanan */ 40535513b920SAnirudh Venkataramanan enum ice_status 40544fb33f31SAnirudh Venkataramanan ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap, 40555513b920SAnirudh Venkataramanan u16 *max_lanqs) 40565513b920SAnirudh Venkataramanan { 40574fb33f31SAnirudh Venkataramanan return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 40585513b920SAnirudh Venkataramanan ICE_SCHED_NODE_OWNER_LAN); 40595513b920SAnirudh Venkataramanan } 406045d3d428SAnirudh Venkataramanan 406145d3d428SAnirudh Venkataramanan /** 4062334cb062SAnirudh Venkataramanan * ice_replay_pre_init - replay pre initialization 4063f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 4064334cb062SAnirudh Venkataramanan * 4065334cb062SAnirudh Venkataramanan * Initializes required config data for VSI, FD, ACL, and RSS before replay. 4066334cb062SAnirudh Venkataramanan */ 4067334cb062SAnirudh Venkataramanan static enum ice_status ice_replay_pre_init(struct ice_hw *hw) 4068334cb062SAnirudh Venkataramanan { 4069334cb062SAnirudh Venkataramanan struct ice_switch_info *sw = hw->switch_info; 4070334cb062SAnirudh Venkataramanan u8 i; 4071334cb062SAnirudh Venkataramanan 4072334cb062SAnirudh Venkataramanan /* Delete old entries from replay filter list head if there is any */ 4073334cb062SAnirudh Venkataramanan ice_rm_all_sw_replay_rule_info(hw); 4074334cb062SAnirudh Venkataramanan /* In start of replay, move entries into replay_rules list, it 4075334cb062SAnirudh Venkataramanan * will allow adding rules entries back to filt_rules list, 4076334cb062SAnirudh Venkataramanan * which is operational list. 4077334cb062SAnirudh Venkataramanan */ 4078334cb062SAnirudh Venkataramanan for (i = 0; i < ICE_SW_LKUP_LAST; i++) 4079334cb062SAnirudh Venkataramanan list_replace_init(&sw->recp_list[i].filt_rules, 4080334cb062SAnirudh Venkataramanan &sw->recp_list[i].filt_replay_rules); 4081334cb062SAnirudh Venkataramanan 4082334cb062SAnirudh Venkataramanan return 0; 4083334cb062SAnirudh Venkataramanan } 4084334cb062SAnirudh Venkataramanan 4085334cb062SAnirudh Venkataramanan /** 4086334cb062SAnirudh Venkataramanan * ice_replay_vsi - replay VSI configuration 4087f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 4088334cb062SAnirudh Venkataramanan * @vsi_handle: driver VSI handle 4089334cb062SAnirudh Venkataramanan * 4090334cb062SAnirudh Venkataramanan * Restore all VSI configuration after reset. It is required to call this 4091334cb062SAnirudh Venkataramanan * function with main VSI first. 4092334cb062SAnirudh Venkataramanan */ 4093334cb062SAnirudh Venkataramanan enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 4094334cb062SAnirudh Venkataramanan { 4095334cb062SAnirudh Venkataramanan enum ice_status status; 4096334cb062SAnirudh Venkataramanan 4097334cb062SAnirudh Venkataramanan if (!ice_is_vsi_valid(hw, vsi_handle)) 4098334cb062SAnirudh Venkataramanan return ICE_ERR_PARAM; 4099334cb062SAnirudh Venkataramanan 4100334cb062SAnirudh Venkataramanan /* Replay pre-initialization if there is any */ 4101334cb062SAnirudh Venkataramanan if (vsi_handle == ICE_MAIN_VSI_HANDLE) { 4102334cb062SAnirudh Venkataramanan status = ice_replay_pre_init(hw); 4103334cb062SAnirudh Venkataramanan if (status) 4104334cb062SAnirudh Venkataramanan return status; 4105334cb062SAnirudh Venkataramanan } 4106c90ed40cSTony Nguyen /* Replay per VSI all RSS configurations */ 4107c90ed40cSTony Nguyen status = ice_replay_rss_cfg(hw, vsi_handle); 4108c90ed40cSTony Nguyen if (status) 4109c90ed40cSTony Nguyen return status; 4110334cb062SAnirudh Venkataramanan /* Replay per VSI all filters */ 4111334cb062SAnirudh Venkataramanan status = ice_replay_vsi_all_fltr(hw, vsi_handle); 4112334cb062SAnirudh Venkataramanan return status; 4113334cb062SAnirudh Venkataramanan } 4114334cb062SAnirudh Venkataramanan 4115334cb062SAnirudh Venkataramanan /** 4116334cb062SAnirudh Venkataramanan * ice_replay_post - post replay configuration cleanup 4117f9867df6SAnirudh Venkataramanan * @hw: pointer to the HW struct 4118334cb062SAnirudh Venkataramanan * 4119334cb062SAnirudh Venkataramanan * Post replay cleanup. 4120334cb062SAnirudh Venkataramanan */ 4121334cb062SAnirudh Venkataramanan void ice_replay_post(struct ice_hw *hw) 4122334cb062SAnirudh Venkataramanan { 4123334cb062SAnirudh Venkataramanan /* Delete old entries from replay filter list head */ 4124334cb062SAnirudh Venkataramanan ice_rm_all_sw_replay_rule_info(hw); 4125334cb062SAnirudh Venkataramanan } 4126334cb062SAnirudh Venkataramanan 4127334cb062SAnirudh Venkataramanan /** 412845d3d428SAnirudh Venkataramanan * ice_stat_update40 - read 40 bit stat from the chip and update stat values 412945d3d428SAnirudh Venkataramanan * @hw: ptr to the hardware info 413036517fd3SJacob Keller * @reg: offset of 64 bit HW register to read from 413145d3d428SAnirudh Venkataramanan * @prev_stat_loaded: bool to specify if previous stats are loaded 413245d3d428SAnirudh Venkataramanan * @prev_stat: ptr to previous loaded stat value 413345d3d428SAnirudh Venkataramanan * @cur_stat: ptr to current stat value 413445d3d428SAnirudh Venkataramanan */ 4135c8b7abddSBruce Allan void 413636517fd3SJacob Keller ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 413736517fd3SJacob Keller u64 *prev_stat, u64 *cur_stat) 413845d3d428SAnirudh Venkataramanan { 413936517fd3SJacob Keller u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 414045d3d428SAnirudh Venkataramanan 414145d3d428SAnirudh Venkataramanan /* device stats are not reset at PFR, they likely will not be zeroed 414236517fd3SJacob Keller * when the driver starts. Thus, save the value from the first read 414336517fd3SJacob Keller * without adding to the statistic value so that we report stats which 414436517fd3SJacob Keller * count up from zero. 414545d3d428SAnirudh Venkataramanan */ 414636517fd3SJacob Keller if (!prev_stat_loaded) { 414745d3d428SAnirudh Venkataramanan *prev_stat = new_data; 414836517fd3SJacob Keller return; 414936517fd3SJacob Keller } 415036517fd3SJacob Keller 415136517fd3SJacob Keller /* Calculate the difference between the new and old values, and then 415236517fd3SJacob Keller * add it to the software stat value. 415336517fd3SJacob Keller */ 415445d3d428SAnirudh Venkataramanan if (new_data >= *prev_stat) 415536517fd3SJacob Keller *cur_stat += new_data - *prev_stat; 415645d3d428SAnirudh Venkataramanan else 415745d3d428SAnirudh Venkataramanan /* to manage the potential roll-over */ 415836517fd3SJacob Keller *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 415936517fd3SJacob Keller 416036517fd3SJacob Keller /* Update the previously stored value to prepare for next read */ 416136517fd3SJacob Keller *prev_stat = new_data; 416245d3d428SAnirudh Venkataramanan } 416345d3d428SAnirudh Venkataramanan 416445d3d428SAnirudh Venkataramanan /** 416545d3d428SAnirudh Venkataramanan * ice_stat_update32 - read 32 bit stat from the chip and update stat values 416645d3d428SAnirudh Venkataramanan * @hw: ptr to the hardware info 416736517fd3SJacob Keller * @reg: offset of HW register to read from 416845d3d428SAnirudh Venkataramanan * @prev_stat_loaded: bool to specify if previous stats are loaded 416945d3d428SAnirudh Venkataramanan * @prev_stat: ptr to previous loaded stat value 417045d3d428SAnirudh Venkataramanan * @cur_stat: ptr to current stat value 417145d3d428SAnirudh Venkataramanan */ 4172c8b7abddSBruce Allan void 4173c8b7abddSBruce Allan ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 417445d3d428SAnirudh Venkataramanan u64 *prev_stat, u64 *cur_stat) 417545d3d428SAnirudh Venkataramanan { 417645d3d428SAnirudh Venkataramanan u32 new_data; 417745d3d428SAnirudh Venkataramanan 417845d3d428SAnirudh Venkataramanan new_data = rd32(hw, reg); 417945d3d428SAnirudh Venkataramanan 418045d3d428SAnirudh Venkataramanan /* device stats are not reset at PFR, they likely will not be zeroed 418136517fd3SJacob Keller * when the driver starts. Thus, save the value from the first read 418236517fd3SJacob Keller * without adding to the statistic value so that we report stats which 418336517fd3SJacob Keller * count up from zero. 418445d3d428SAnirudh Venkataramanan */ 418536517fd3SJacob Keller if (!prev_stat_loaded) { 418645d3d428SAnirudh Venkataramanan *prev_stat = new_data; 418736517fd3SJacob Keller return; 418836517fd3SJacob Keller } 418936517fd3SJacob Keller 419036517fd3SJacob Keller /* Calculate the difference between the new and old values, and then 419136517fd3SJacob Keller * add it to the software stat value. 419236517fd3SJacob Keller */ 419345d3d428SAnirudh Venkataramanan if (new_data >= *prev_stat) 419436517fd3SJacob Keller *cur_stat += new_data - *prev_stat; 419545d3d428SAnirudh Venkataramanan else 419645d3d428SAnirudh Venkataramanan /* to manage the potential roll-over */ 419736517fd3SJacob Keller *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 419836517fd3SJacob Keller 419936517fd3SJacob Keller /* Update the previously stored value to prepare for next read */ 420036517fd3SJacob Keller *prev_stat = new_data; 420145d3d428SAnirudh Venkataramanan } 42027b9ffc76SAnirudh Venkataramanan 42037b9ffc76SAnirudh Venkataramanan /** 42047b9ffc76SAnirudh Venkataramanan * ice_sched_query_elem - query element information from HW 42057b9ffc76SAnirudh Venkataramanan * @hw: pointer to the HW struct 42067b9ffc76SAnirudh Venkataramanan * @node_teid: node TEID to be queried 42077b9ffc76SAnirudh Venkataramanan * @buf: buffer to element information 42087b9ffc76SAnirudh Venkataramanan * 42097b9ffc76SAnirudh Venkataramanan * This function queries HW element information 42107b9ffc76SAnirudh Venkataramanan */ 42117b9ffc76SAnirudh Venkataramanan enum ice_status 42127b9ffc76SAnirudh Venkataramanan ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 4213b3c38904SBruce Allan struct ice_aqc_txsched_elem_data *buf) 42147b9ffc76SAnirudh Venkataramanan { 42157b9ffc76SAnirudh Venkataramanan u16 buf_size, num_elem_ret = 0; 42167b9ffc76SAnirudh Venkataramanan enum ice_status status; 42177b9ffc76SAnirudh Venkataramanan 42187b9ffc76SAnirudh Venkataramanan buf_size = sizeof(*buf); 42197b9ffc76SAnirudh Venkataramanan memset(buf, 0, buf_size); 4220b3c38904SBruce Allan buf->node_teid = cpu_to_le32(node_teid); 42217b9ffc76SAnirudh Venkataramanan status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 42227b9ffc76SAnirudh Venkataramanan NULL); 42237b9ffc76SAnirudh Venkataramanan if (status || num_elem_ret != 1) 42247b9ffc76SAnirudh Venkataramanan ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 42257b9ffc76SAnirudh Venkataramanan return status; 42267b9ffc76SAnirudh Venkataramanan } 4227ea78ce4dSPaul Greenwalt 4228ea78ce4dSPaul Greenwalt /** 4229ea78ce4dSPaul Greenwalt * ice_fw_supports_link_override 4230ea78ce4dSPaul Greenwalt * @hw: pointer to the hardware structure 4231ea78ce4dSPaul Greenwalt * 4232ea78ce4dSPaul Greenwalt * Checks if the firmware supports link override 4233ea78ce4dSPaul Greenwalt */ 4234ea78ce4dSPaul Greenwalt bool ice_fw_supports_link_override(struct ice_hw *hw) 4235ea78ce4dSPaul Greenwalt { 4236ea78ce4dSPaul Greenwalt if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 4237ea78ce4dSPaul Greenwalt if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 4238ea78ce4dSPaul Greenwalt return true; 4239ea78ce4dSPaul Greenwalt if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 4240ea78ce4dSPaul Greenwalt hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 4241ea78ce4dSPaul Greenwalt return true; 4242ea78ce4dSPaul Greenwalt } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 4243ea78ce4dSPaul Greenwalt return true; 4244ea78ce4dSPaul Greenwalt } 4245ea78ce4dSPaul Greenwalt 4246ea78ce4dSPaul Greenwalt return false; 4247ea78ce4dSPaul Greenwalt } 4248ea78ce4dSPaul Greenwalt 4249ea78ce4dSPaul Greenwalt /** 4250ea78ce4dSPaul Greenwalt * ice_get_link_default_override 4251ea78ce4dSPaul Greenwalt * @ldo: pointer to the link default override struct 4252ea78ce4dSPaul Greenwalt * @pi: pointer to the port info struct 4253ea78ce4dSPaul Greenwalt * 4254ea78ce4dSPaul Greenwalt * Gets the link default override for a port 4255ea78ce4dSPaul Greenwalt */ 4256ea78ce4dSPaul Greenwalt enum ice_status 4257ea78ce4dSPaul Greenwalt ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 4258ea78ce4dSPaul Greenwalt struct ice_port_info *pi) 4259ea78ce4dSPaul Greenwalt { 4260ea78ce4dSPaul Greenwalt u16 i, tlv, tlv_len, tlv_start, buf, offset; 4261ea78ce4dSPaul Greenwalt struct ice_hw *hw = pi->hw; 4262ea78ce4dSPaul Greenwalt enum ice_status status; 4263ea78ce4dSPaul Greenwalt 4264ea78ce4dSPaul Greenwalt status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 4265ea78ce4dSPaul Greenwalt ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 4266ea78ce4dSPaul Greenwalt if (status) { 42679228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 4268ea78ce4dSPaul Greenwalt return status; 4269ea78ce4dSPaul Greenwalt } 4270ea78ce4dSPaul Greenwalt 4271ea78ce4dSPaul Greenwalt /* Each port has its own config; calculate for our port */ 4272ea78ce4dSPaul Greenwalt tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 4273ea78ce4dSPaul Greenwalt ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 4274ea78ce4dSPaul Greenwalt 4275ea78ce4dSPaul Greenwalt /* link options first */ 4276ea78ce4dSPaul Greenwalt status = ice_read_sr_word(hw, tlv_start, &buf); 4277ea78ce4dSPaul Greenwalt if (status) { 42789228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4279ea78ce4dSPaul Greenwalt return status; 4280ea78ce4dSPaul Greenwalt } 4281ea78ce4dSPaul Greenwalt ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 4282ea78ce4dSPaul Greenwalt ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 4283ea78ce4dSPaul Greenwalt ICE_LINK_OVERRIDE_PHY_CFG_S; 4284ea78ce4dSPaul Greenwalt 4285ea78ce4dSPaul Greenwalt /* link PHY config */ 4286ea78ce4dSPaul Greenwalt offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 4287ea78ce4dSPaul Greenwalt status = ice_read_sr_word(hw, offset, &buf); 4288ea78ce4dSPaul Greenwalt if (status) { 42899228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 4290ea78ce4dSPaul Greenwalt return status; 4291ea78ce4dSPaul Greenwalt } 4292ea78ce4dSPaul Greenwalt ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 4293ea78ce4dSPaul Greenwalt 4294ea78ce4dSPaul Greenwalt /* PHY types low */ 4295ea78ce4dSPaul Greenwalt offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 4296ea78ce4dSPaul Greenwalt for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4297ea78ce4dSPaul Greenwalt status = ice_read_sr_word(hw, (offset + i), &buf); 4298ea78ce4dSPaul Greenwalt if (status) { 42999228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4300ea78ce4dSPaul Greenwalt return status; 4301ea78ce4dSPaul Greenwalt } 4302ea78ce4dSPaul Greenwalt /* shift 16 bits at a time to fill 64 bits */ 4303ea78ce4dSPaul Greenwalt ldo->phy_type_low |= ((u64)buf << (i * 16)); 4304ea78ce4dSPaul Greenwalt } 4305ea78ce4dSPaul Greenwalt 4306ea78ce4dSPaul Greenwalt /* PHY types high */ 4307ea78ce4dSPaul Greenwalt offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 4308ea78ce4dSPaul Greenwalt ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 4309ea78ce4dSPaul Greenwalt for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 4310ea78ce4dSPaul Greenwalt status = ice_read_sr_word(hw, (offset + i), &buf); 4311ea78ce4dSPaul Greenwalt if (status) { 43129228d8b2SJacob Keller ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 4313ea78ce4dSPaul Greenwalt return status; 4314ea78ce4dSPaul Greenwalt } 4315ea78ce4dSPaul Greenwalt /* shift 16 bits at a time to fill 64 bits */ 4316ea78ce4dSPaul Greenwalt ldo->phy_type_high |= ((u64)buf << (i * 16)); 4317ea78ce4dSPaul Greenwalt } 4318ea78ce4dSPaul Greenwalt 4319ea78ce4dSPaul Greenwalt return status; 4320ea78ce4dSPaul Greenwalt } 43215ee30564SPaul Greenwalt 43225ee30564SPaul Greenwalt /** 43235ee30564SPaul Greenwalt * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 43245ee30564SPaul Greenwalt * @caps: get PHY capability data 43255ee30564SPaul Greenwalt */ 43265ee30564SPaul Greenwalt bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 43275ee30564SPaul Greenwalt { 43285ee30564SPaul Greenwalt if (caps->caps & ICE_AQC_PHY_AN_MODE || 4329bdeff971SLev Faerman caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 43305ee30564SPaul Greenwalt ICE_AQC_PHY_AN_EN_CLAUSE73 | 43315ee30564SPaul Greenwalt ICE_AQC_PHY_AN_EN_CLAUSE37)) 43325ee30564SPaul Greenwalt return true; 43335ee30564SPaul Greenwalt 43345ee30564SPaul Greenwalt return false; 43355ee30564SPaul Greenwalt } 43367d9c9b79SDave Ertman 43377d9c9b79SDave Ertman /** 43387d9c9b79SDave Ertman * ice_aq_set_lldp_mib - Set the LLDP MIB 43397d9c9b79SDave Ertman * @hw: pointer to the HW struct 43407d9c9b79SDave Ertman * @mib_type: Local, Remote or both Local and Remote MIBs 43417d9c9b79SDave Ertman * @buf: pointer to the caller-supplied buffer to store the MIB block 43427d9c9b79SDave Ertman * @buf_size: size of the buffer (in bytes) 43437d9c9b79SDave Ertman * @cd: pointer to command details structure or NULL 43447d9c9b79SDave Ertman * 43457d9c9b79SDave Ertman * Set the LLDP MIB. (0x0A08) 43467d9c9b79SDave Ertman */ 43477d9c9b79SDave Ertman enum ice_status 43487d9c9b79SDave Ertman ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 43497d9c9b79SDave Ertman struct ice_sq_cd *cd) 43507d9c9b79SDave Ertman { 43517d9c9b79SDave Ertman struct ice_aqc_lldp_set_local_mib *cmd; 43527d9c9b79SDave Ertman struct ice_aq_desc desc; 43537d9c9b79SDave Ertman 43547d9c9b79SDave Ertman cmd = &desc.params.lldp_set_mib; 43557d9c9b79SDave Ertman 43567d9c9b79SDave Ertman if (buf_size == 0 || !buf) 43577d9c9b79SDave Ertman return ICE_ERR_PARAM; 43587d9c9b79SDave Ertman 43597d9c9b79SDave Ertman ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 43607d9c9b79SDave Ertman 43617d9c9b79SDave Ertman desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD); 43627d9c9b79SDave Ertman desc.datalen = cpu_to_le16(buf_size); 43637d9c9b79SDave Ertman 43647d9c9b79SDave Ertman cmd->type = mib_type; 43657d9c9b79SDave Ertman cmd->length = cpu_to_le16(buf_size); 43667d9c9b79SDave Ertman 43677d9c9b79SDave Ertman return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 43687d9c9b79SDave Ertman } 4369*34295a36SDave Ertman 4370*34295a36SDave Ertman /** 4371*34295a36SDave Ertman * ice_fw_supports_lldp_fltr - check NVM version supports lldp_fltr_ctrl 4372*34295a36SDave Ertman * @hw: pointer to HW struct 4373*34295a36SDave Ertman */ 4374*34295a36SDave Ertman bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 4375*34295a36SDave Ertman { 4376*34295a36SDave Ertman if (hw->mac_type != ICE_MAC_E810) 4377*34295a36SDave Ertman return false; 4378*34295a36SDave Ertman 4379*34295a36SDave Ertman if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) { 4380*34295a36SDave Ertman if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN) 4381*34295a36SDave Ertman return true; 4382*34295a36SDave Ertman if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN && 4383*34295a36SDave Ertman hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH) 4384*34295a36SDave Ertman return true; 4385*34295a36SDave Ertman } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) { 4386*34295a36SDave Ertman return true; 4387*34295a36SDave Ertman } 4388*34295a36SDave Ertman return false; 4389*34295a36SDave Ertman } 4390*34295a36SDave Ertman 4391*34295a36SDave Ertman /** 4392*34295a36SDave Ertman * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 4393*34295a36SDave Ertman * @hw: pointer to HW struct 4394*34295a36SDave Ertman * @vsi_num: absolute HW index for VSI 4395*34295a36SDave Ertman * @add: boolean for if adding or removing a filter 4396*34295a36SDave Ertman */ 4397*34295a36SDave Ertman enum ice_status 4398*34295a36SDave Ertman ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 4399*34295a36SDave Ertman { 4400*34295a36SDave Ertman struct ice_aqc_lldp_filter_ctrl *cmd; 4401*34295a36SDave Ertman struct ice_aq_desc desc; 4402*34295a36SDave Ertman 4403*34295a36SDave Ertman cmd = &desc.params.lldp_filter_ctrl; 4404*34295a36SDave Ertman 4405*34295a36SDave Ertman ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 4406*34295a36SDave Ertman 4407*34295a36SDave Ertman if (add) 4408*34295a36SDave Ertman cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 4409*34295a36SDave Ertman else 4410*34295a36SDave Ertman cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 4411*34295a36SDave Ertman 4412*34295a36SDave Ertman cmd->vsi_num = cpu_to_le16(vsi_num); 4413*34295a36SDave Ertman 4414*34295a36SDave Ertman return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 4415*34295a36SDave Ertman } 4416