1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019, Intel Corporation. */ 3 4 #include "ice_base.h" 5 #include "ice_dcb_lib.h" 6 7 /** 8 * __ice_vsi_get_qs_contig - Assign a contiguous chunk of queues to VSI 9 * @qs_cfg: gathered variables needed for PF->VSI queues assignment 10 * 11 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 12 */ 13 static int __ice_vsi_get_qs_contig(struct ice_qs_cfg *qs_cfg) 14 { 15 int offset, i; 16 17 mutex_lock(qs_cfg->qs_mutex); 18 offset = bitmap_find_next_zero_area(qs_cfg->pf_map, qs_cfg->pf_map_size, 19 0, qs_cfg->q_count, 0); 20 if (offset >= qs_cfg->pf_map_size) { 21 mutex_unlock(qs_cfg->qs_mutex); 22 return -ENOMEM; 23 } 24 25 bitmap_set(qs_cfg->pf_map, offset, qs_cfg->q_count); 26 for (i = 0; i < qs_cfg->q_count; i++) 27 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = i + offset; 28 mutex_unlock(qs_cfg->qs_mutex); 29 30 return 0; 31 } 32 33 /** 34 * __ice_vsi_get_qs_sc - Assign a scattered queues from PF to VSI 35 * @qs_cfg: gathered variables needed for pf->vsi queues assignment 36 * 37 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 38 */ 39 static int __ice_vsi_get_qs_sc(struct ice_qs_cfg *qs_cfg) 40 { 41 int i, index = 0; 42 43 mutex_lock(qs_cfg->qs_mutex); 44 for (i = 0; i < qs_cfg->q_count; i++) { 45 index = find_next_zero_bit(qs_cfg->pf_map, 46 qs_cfg->pf_map_size, index); 47 if (index >= qs_cfg->pf_map_size) 48 goto err_scatter; 49 set_bit(index, qs_cfg->pf_map); 50 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = index; 51 } 52 mutex_unlock(qs_cfg->qs_mutex); 53 54 return 0; 55 err_scatter: 56 for (index = 0; index < i; index++) { 57 clear_bit(qs_cfg->vsi_map[index], qs_cfg->pf_map); 58 qs_cfg->vsi_map[index + qs_cfg->vsi_map_offset] = 0; 59 } 60 mutex_unlock(qs_cfg->qs_mutex); 61 62 return -ENOMEM; 63 } 64 65 /** 66 * ice_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled 67 * @pf: the PF being configured 68 * @pf_q: the PF queue 69 * @ena: enable or disable state of the queue 70 * 71 * This routine will wait for the given Rx queue of the PF to reach the 72 * enabled or disabled state. 73 * Returns -ETIMEDOUT in case of failing to reach the requested state after 74 * multiple retries; else will return 0 in case of success. 75 */ 76 static int ice_pf_rxq_wait(struct ice_pf *pf, int pf_q, bool ena) 77 { 78 int i; 79 80 for (i = 0; i < ICE_Q_WAIT_MAX_RETRY; i++) { 81 if (ena == !!(rd32(&pf->hw, QRX_CTRL(pf_q)) & 82 QRX_CTRL_QENA_STAT_M)) 83 return 0; 84 85 usleep_range(20, 40); 86 } 87 88 return -ETIMEDOUT; 89 } 90 91 /** 92 * ice_vsi_alloc_q_vector - Allocate memory for a single interrupt vector 93 * @vsi: the VSI being configured 94 * @v_idx: index of the vector in the VSI struct 95 * 96 * We allocate one q_vector and set default value for ITR setting associated 97 * with this q_vector. If allocation fails we return -ENOMEM. 98 */ 99 static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, int v_idx) 100 { 101 struct ice_pf *pf = vsi->back; 102 struct ice_q_vector *q_vector; 103 104 /* allocate q_vector */ 105 q_vector = devm_kzalloc(ice_pf_to_dev(pf), sizeof(*q_vector), 106 GFP_KERNEL); 107 if (!q_vector) 108 return -ENOMEM; 109 110 q_vector->vsi = vsi; 111 q_vector->v_idx = v_idx; 112 q_vector->tx.itr_setting = ICE_DFLT_TX_ITR; 113 q_vector->rx.itr_setting = ICE_DFLT_RX_ITR; 114 if (vsi->type == ICE_VSI_VF) 115 goto out; 116 /* only set affinity_mask if the CPU is online */ 117 if (cpu_online(v_idx)) 118 cpumask_set_cpu(v_idx, &q_vector->affinity_mask); 119 120 /* This will not be called in the driver load path because the netdev 121 * will not be created yet. All other cases with register the NAPI 122 * handler here (i.e. resume, reset/rebuild, etc.) 123 */ 124 if (vsi->netdev) 125 netif_napi_add(vsi->netdev, &q_vector->napi, ice_napi_poll, 126 NAPI_POLL_WEIGHT); 127 128 out: 129 /* tie q_vector and VSI together */ 130 vsi->q_vectors[v_idx] = q_vector; 131 132 return 0; 133 } 134 135 /** 136 * ice_free_q_vector - Free memory allocated for a specific interrupt vector 137 * @vsi: VSI having the memory freed 138 * @v_idx: index of the vector to be freed 139 */ 140 static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx) 141 { 142 struct ice_q_vector *q_vector; 143 struct ice_pf *pf = vsi->back; 144 struct ice_ring *ring; 145 struct device *dev; 146 147 dev = ice_pf_to_dev(pf); 148 if (!vsi->q_vectors[v_idx]) { 149 dev_dbg(dev, "Queue vector at index %d not found\n", v_idx); 150 return; 151 } 152 q_vector = vsi->q_vectors[v_idx]; 153 154 ice_for_each_ring(ring, q_vector->tx) 155 ring->q_vector = NULL; 156 ice_for_each_ring(ring, q_vector->rx) 157 ring->q_vector = NULL; 158 159 /* only VSI with an associated netdev is set up with NAPI */ 160 if (vsi->netdev) 161 netif_napi_del(&q_vector->napi); 162 163 devm_kfree(dev, q_vector); 164 vsi->q_vectors[v_idx] = NULL; 165 } 166 167 /** 168 * ice_cfg_itr_gran - set the ITR granularity to 2 usecs if not already set 169 * @hw: board specific structure 170 */ 171 static void ice_cfg_itr_gran(struct ice_hw *hw) 172 { 173 u32 regval = rd32(hw, GLINT_CTL); 174 175 /* no need to update global register if ITR gran is already set */ 176 if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) && 177 (((regval & GLINT_CTL_ITR_GRAN_200_M) >> 178 GLINT_CTL_ITR_GRAN_200_S) == ICE_ITR_GRAN_US) && 179 (((regval & GLINT_CTL_ITR_GRAN_100_M) >> 180 GLINT_CTL_ITR_GRAN_100_S) == ICE_ITR_GRAN_US) && 181 (((regval & GLINT_CTL_ITR_GRAN_50_M) >> 182 GLINT_CTL_ITR_GRAN_50_S) == ICE_ITR_GRAN_US) && 183 (((regval & GLINT_CTL_ITR_GRAN_25_M) >> 184 GLINT_CTL_ITR_GRAN_25_S) == ICE_ITR_GRAN_US)) 185 return; 186 187 regval = ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_200_S) & 188 GLINT_CTL_ITR_GRAN_200_M) | 189 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_100_S) & 190 GLINT_CTL_ITR_GRAN_100_M) | 191 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_50_S) & 192 GLINT_CTL_ITR_GRAN_50_M) | 193 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_25_S) & 194 GLINT_CTL_ITR_GRAN_25_M); 195 wr32(hw, GLINT_CTL, regval); 196 } 197 198 /** 199 * ice_calc_q_handle - calculate the queue handle 200 * @vsi: VSI that ring belongs to 201 * @ring: ring to get the absolute queue index 202 * @tc: traffic class number 203 */ 204 static u16 ice_calc_q_handle(struct ice_vsi *vsi, struct ice_ring *ring, u8 tc) 205 { 206 WARN_ONCE(ice_ring_is_xdp(ring) && tc, 207 "XDP ring can't belong to TC other than 0"); 208 209 /* Idea here for calculation is that we subtract the number of queue 210 * count from TC that ring belongs to from it's absolute queue index 211 * and as a result we get the queue's index within TC. 212 */ 213 return ring->q_index - vsi->tc_cfg.tc_info[tc].qoffset; 214 } 215 216 /** 217 * ice_setup_tx_ctx - setup a struct ice_tlan_ctx instance 218 * @ring: The Tx ring to configure 219 * @tlan_ctx: Pointer to the Tx LAN queue context structure to be initialized 220 * @pf_q: queue index in the PF space 221 * 222 * Configure the Tx descriptor ring in TLAN context. 223 */ 224 static void 225 ice_setup_tx_ctx(struct ice_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q) 226 { 227 struct ice_vsi *vsi = ring->vsi; 228 struct ice_hw *hw = &vsi->back->hw; 229 230 tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S; 231 232 tlan_ctx->port_num = vsi->port_info->lport; 233 234 /* Transmit Queue Length */ 235 tlan_ctx->qlen = ring->count; 236 237 ice_set_cgd_num(tlan_ctx, ring); 238 239 /* PF number */ 240 tlan_ctx->pf_num = hw->pf_id; 241 242 /* queue belongs to a specific VSI type 243 * VF / VM index should be programmed per vmvf_type setting: 244 * for vmvf_type = VF, it is VF number between 0-256 245 * for vmvf_type = VM, it is VM number between 0-767 246 * for PF or EMP this field should be set to zero 247 */ 248 switch (vsi->type) { 249 case ICE_VSI_LB: 250 /* fall through */ 251 case ICE_VSI_PF: 252 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF; 253 break; 254 case ICE_VSI_VF: 255 /* Firmware expects vmvf_num to be absolute VF ID */ 256 tlan_ctx->vmvf_num = hw->func_caps.vf_base_id + vsi->vf_id; 257 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF; 258 break; 259 default: 260 return; 261 } 262 263 /* make sure the context is associated with the right VSI */ 264 tlan_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx); 265 266 tlan_ctx->tso_ena = ICE_TX_LEGACY; 267 tlan_ctx->tso_qnum = pf_q; 268 269 /* Legacy or Advanced Host Interface: 270 * 0: Advanced Host Interface 271 * 1: Legacy Host Interface 272 */ 273 tlan_ctx->legacy_int = ICE_TX_LEGACY; 274 } 275 276 /** 277 * ice_setup_rx_ctx - Configure a receive ring context 278 * @ring: The Rx ring to configure 279 * 280 * Configure the Rx descriptor ring in RLAN context. 281 */ 282 int ice_setup_rx_ctx(struct ice_ring *ring) 283 { 284 int chain_len = ICE_MAX_CHAINED_RX_BUFS; 285 struct ice_vsi *vsi = ring->vsi; 286 u32 rxdid = ICE_RXDID_FLEX_NIC; 287 struct ice_rlan_ctx rlan_ctx; 288 struct ice_hw *hw; 289 u32 regval; 290 u16 pf_q; 291 int err; 292 293 hw = &vsi->back->hw; 294 295 /* what is Rx queue number in global space of 2K Rx queues */ 296 pf_q = vsi->rxq_map[ring->q_index]; 297 298 /* clear the context structure first */ 299 memset(&rlan_ctx, 0, sizeof(rlan_ctx)); 300 301 ring->rx_buf_len = vsi->rx_buf_len; 302 303 if (ring->vsi->type == ICE_VSI_PF) { 304 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) 305 /* coverity[check_return] */ 306 xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev, 307 ring->q_index); 308 309 ring->xsk_umem = ice_xsk_umem(ring); 310 if (ring->xsk_umem) { 311 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 312 313 ring->rx_buf_len = ring->xsk_umem->chunk_size_nohr - 314 XDP_PACKET_HEADROOM; 315 /* For AF_XDP ZC, we disallow packets to span on 316 * multiple buffers, thus letting us skip that 317 * handling in the fast-path. 318 */ 319 chain_len = 1; 320 ring->zca.free = ice_zca_free; 321 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 322 MEM_TYPE_ZERO_COPY, 323 &ring->zca); 324 if (err) 325 return err; 326 327 dev_info(ice_pf_to_dev(vsi->back), "Registered XDP mem model MEM_TYPE_ZERO_COPY on Rx ring %d\n", 328 ring->q_index); 329 } else { 330 ring->zca.free = NULL; 331 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) 332 /* coverity[check_return] */ 333 xdp_rxq_info_reg(&ring->xdp_rxq, 334 ring->netdev, 335 ring->q_index); 336 337 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 338 MEM_TYPE_PAGE_SHARED, 339 NULL); 340 if (err) 341 return err; 342 } 343 } 344 /* Receive Queue Base Address. 345 * Indicates the starting address of the descriptor queue defined in 346 * 128 Byte units. 347 */ 348 rlan_ctx.base = ring->dma >> 7; 349 350 rlan_ctx.qlen = ring->count; 351 352 /* Receive Packet Data Buffer Size. 353 * The Packet Data Buffer Size is defined in 128 byte units. 354 */ 355 rlan_ctx.dbuf = ring->rx_buf_len >> ICE_RLAN_CTX_DBUF_S; 356 357 /* use 32 byte descriptors */ 358 rlan_ctx.dsize = 1; 359 360 /* Strip the Ethernet CRC bytes before the packet is posted to host 361 * memory. 362 */ 363 rlan_ctx.crcstrip = 1; 364 365 /* L2TSEL flag defines the reported L2 Tags in the receive descriptor */ 366 rlan_ctx.l2tsel = 1; 367 368 rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT; 369 rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_NO_SPLIT; 370 rlan_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_NO_SPLIT; 371 372 /* This controls whether VLAN is stripped from inner headers 373 * The VLAN in the inner L2 header is stripped to the receive 374 * descriptor if enabled by this flag. 375 */ 376 rlan_ctx.showiv = 0; 377 378 /* Max packet size for this queue - must not be set to a larger value 379 * than 5 x DBUF 380 */ 381 rlan_ctx.rxmax = min_t(u16, vsi->max_frame, 382 chain_len * ring->rx_buf_len); 383 384 /* Rx queue threshold in units of 64 */ 385 rlan_ctx.lrxqthresh = 1; 386 387 /* Enable Flexible Descriptors in the queue context which 388 * allows this driver to select a specific receive descriptor format 389 */ 390 if (vsi->type != ICE_VSI_VF) { 391 regval = rd32(hw, QRXFLXP_CNTXT(pf_q)); 392 regval |= (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) & 393 QRXFLXP_CNTXT_RXDID_IDX_M; 394 395 /* increasing context priority to pick up profile ID; 396 * default is 0x01; setting to 0x03 to ensure profile 397 * is programming if prev context is of same priority 398 */ 399 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) & 400 QRXFLXP_CNTXT_RXDID_PRIO_M; 401 402 wr32(hw, QRXFLXP_CNTXT(pf_q), regval); 403 } 404 405 /* Absolute queue number out of 2K needs to be passed */ 406 err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q); 407 if (err) { 408 dev_err(ice_pf_to_dev(vsi->back), "Failed to set LAN Rx queue context for absolute Rx queue %d error: %d\n", 409 pf_q, err); 410 return -EIO; 411 } 412 413 if (vsi->type == ICE_VSI_VF) 414 return 0; 415 416 /* configure Rx buffer alignment */ 417 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags)) 418 ice_clear_ring_build_skb_ena(ring); 419 else 420 ice_set_ring_build_skb_ena(ring); 421 422 /* init queue specific tail register */ 423 ring->tail = hw->hw_addr + QRX_TAIL(pf_q); 424 writel(0, ring->tail); 425 426 err = ring->xsk_umem ? 427 ice_alloc_rx_bufs_slow_zc(ring, ICE_DESC_UNUSED(ring)) : 428 ice_alloc_rx_bufs(ring, ICE_DESC_UNUSED(ring)); 429 if (err) 430 dev_info(ice_pf_to_dev(vsi->back), "Failed allocate some buffers on %sRx ring %d (pf_q %d)\n", 431 ring->xsk_umem ? "UMEM enabled " : "", 432 ring->q_index, pf_q); 433 434 return 0; 435 } 436 437 /** 438 * __ice_vsi_get_qs - helper function for assigning queues from PF to VSI 439 * @qs_cfg: gathered variables needed for pf->vsi queues assignment 440 * 441 * This function first tries to find contiguous space. If it is not successful, 442 * it tries with the scatter approach. 443 * 444 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 445 */ 446 int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg) 447 { 448 int ret = 0; 449 450 ret = __ice_vsi_get_qs_contig(qs_cfg); 451 if (ret) { 452 /* contig failed, so try with scatter approach */ 453 qs_cfg->mapping_mode = ICE_VSI_MAP_SCATTER; 454 qs_cfg->q_count = min_t(u16, qs_cfg->q_count, 455 qs_cfg->scatter_count); 456 ret = __ice_vsi_get_qs_sc(qs_cfg); 457 } 458 return ret; 459 } 460 461 /** 462 * ice_vsi_ctrl_rx_ring - Start or stop a VSI's Rx ring 463 * @vsi: the VSI being configured 464 * @ena: start or stop the Rx rings 465 * @rxq_idx: Rx queue index 466 */ 467 int ice_vsi_ctrl_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx) 468 { 469 int pf_q = vsi->rxq_map[rxq_idx]; 470 struct ice_pf *pf = vsi->back; 471 struct ice_hw *hw = &pf->hw; 472 int ret = 0; 473 u32 rx_reg; 474 475 rx_reg = rd32(hw, QRX_CTRL(pf_q)); 476 477 /* Skip if the queue is already in the requested state */ 478 if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M)) 479 return 0; 480 481 /* turn on/off the queue */ 482 if (ena) 483 rx_reg |= QRX_CTRL_QENA_REQ_M; 484 else 485 rx_reg &= ~QRX_CTRL_QENA_REQ_M; 486 wr32(hw, QRX_CTRL(pf_q), rx_reg); 487 488 /* wait for the change to finish */ 489 ret = ice_pf_rxq_wait(pf, pf_q, ena); 490 if (ret) 491 dev_err(ice_pf_to_dev(pf), "VSI idx %d Rx ring %d %sable timeout\n", 492 vsi->idx, pf_q, (ena ? "en" : "dis")); 493 494 return ret; 495 } 496 497 /** 498 * ice_vsi_alloc_q_vectors - Allocate memory for interrupt vectors 499 * @vsi: the VSI being configured 500 * 501 * We allocate one q_vector per queue interrupt. If allocation fails we 502 * return -ENOMEM. 503 */ 504 int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi) 505 { 506 struct device *dev = ice_pf_to_dev(vsi->back); 507 int v_idx, err; 508 509 if (vsi->q_vectors[0]) { 510 dev_dbg(dev, "VSI %d has existing q_vectors\n", vsi->vsi_num); 511 return -EEXIST; 512 } 513 514 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) { 515 err = ice_vsi_alloc_q_vector(vsi, v_idx); 516 if (err) 517 goto err_out; 518 } 519 520 return 0; 521 522 err_out: 523 while (v_idx--) 524 ice_free_q_vector(vsi, v_idx); 525 526 dev_err(dev, "Failed to allocate %d q_vector for VSI %d, ret=%d\n", 527 vsi->num_q_vectors, vsi->vsi_num, err); 528 vsi->num_q_vectors = 0; 529 return err; 530 } 531 532 /** 533 * ice_vsi_map_rings_to_vectors - Map VSI rings to interrupt vectors 534 * @vsi: the VSI being configured 535 * 536 * This function maps descriptor rings to the queue-specific vectors allotted 537 * through the MSI-X enabling code. On a constrained vector budget, we map Tx 538 * and Rx rings to the vector as "efficiently" as possible. 539 */ 540 void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi) 541 { 542 int q_vectors = vsi->num_q_vectors; 543 int tx_rings_rem, rx_rings_rem; 544 int v_id; 545 546 /* initially assigning remaining rings count to VSIs num queue value */ 547 tx_rings_rem = vsi->num_txq; 548 rx_rings_rem = vsi->num_rxq; 549 550 for (v_id = 0; v_id < q_vectors; v_id++) { 551 struct ice_q_vector *q_vector = vsi->q_vectors[v_id]; 552 int tx_rings_per_v, rx_rings_per_v, q_id, q_base; 553 554 /* Tx rings mapping to vector */ 555 tx_rings_per_v = DIV_ROUND_UP(tx_rings_rem, q_vectors - v_id); 556 q_vector->num_ring_tx = tx_rings_per_v; 557 q_vector->tx.ring = NULL; 558 q_vector->tx.itr_idx = ICE_TX_ITR; 559 q_base = vsi->num_txq - tx_rings_rem; 560 561 for (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) { 562 struct ice_ring *tx_ring = vsi->tx_rings[q_id]; 563 564 tx_ring->q_vector = q_vector; 565 tx_ring->next = q_vector->tx.ring; 566 q_vector->tx.ring = tx_ring; 567 } 568 tx_rings_rem -= tx_rings_per_v; 569 570 /* Rx rings mapping to vector */ 571 rx_rings_per_v = DIV_ROUND_UP(rx_rings_rem, q_vectors - v_id); 572 q_vector->num_ring_rx = rx_rings_per_v; 573 q_vector->rx.ring = NULL; 574 q_vector->rx.itr_idx = ICE_RX_ITR; 575 q_base = vsi->num_rxq - rx_rings_rem; 576 577 for (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) { 578 struct ice_ring *rx_ring = vsi->rx_rings[q_id]; 579 580 rx_ring->q_vector = q_vector; 581 rx_ring->next = q_vector->rx.ring; 582 q_vector->rx.ring = rx_ring; 583 } 584 rx_rings_rem -= rx_rings_per_v; 585 } 586 } 587 588 /** 589 * ice_vsi_free_q_vectors - Free memory allocated for interrupt vectors 590 * @vsi: the VSI having memory freed 591 */ 592 void ice_vsi_free_q_vectors(struct ice_vsi *vsi) 593 { 594 int v_idx; 595 596 ice_for_each_q_vector(vsi, v_idx) 597 ice_free_q_vector(vsi, v_idx); 598 } 599 600 /** 601 * ice_vsi_cfg_txq - Configure single Tx queue 602 * @vsi: the VSI that queue belongs to 603 * @ring: Tx ring to be configured 604 * @qg_buf: queue group buffer 605 */ 606 int 607 ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_ring *ring, 608 struct ice_aqc_add_tx_qgrp *qg_buf) 609 { 610 struct ice_tlan_ctx tlan_ctx = { 0 }; 611 struct ice_aqc_add_txqs_perq *txq; 612 struct ice_pf *pf = vsi->back; 613 u8 buf_len = sizeof(*qg_buf); 614 enum ice_status status; 615 u16 pf_q; 616 u8 tc; 617 618 pf_q = ring->reg_idx; 619 ice_setup_tx_ctx(ring, &tlan_ctx, pf_q); 620 /* copy context contents into the qg_buf */ 621 qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q); 622 ice_set_ctx((u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx, 623 ice_tlan_ctx_info); 624 625 /* init queue specific tail reg. It is referred as 626 * transmit comm scheduler queue doorbell. 627 */ 628 ring->tail = pf->hw.hw_addr + QTX_COMM_DBELL(pf_q); 629 630 if (IS_ENABLED(CONFIG_DCB)) 631 tc = ring->dcb_tc; 632 else 633 tc = 0; 634 635 /* Add unique software queue handle of the Tx queue per 636 * TC into the VSI Tx ring 637 */ 638 ring->q_handle = ice_calc_q_handle(vsi, ring, tc); 639 640 status = ice_ena_vsi_txq(vsi->port_info, vsi->idx, tc, ring->q_handle, 641 1, qg_buf, buf_len, NULL); 642 if (status) { 643 dev_err(ice_pf_to_dev(pf), "Failed to set LAN Tx queue context, error: %d\n", 644 status); 645 return -ENODEV; 646 } 647 648 /* Add Tx Queue TEID into the VSI Tx ring from the 649 * response. This will complete configuring and 650 * enabling the queue. 651 */ 652 txq = &qg_buf->txqs[0]; 653 if (pf_q == le16_to_cpu(txq->txq_id)) 654 ring->txq_teid = le32_to_cpu(txq->q_teid); 655 656 return 0; 657 } 658 659 /** 660 * ice_cfg_itr - configure the initial interrupt throttle values 661 * @hw: pointer to the HW structure 662 * @q_vector: interrupt vector that's being configured 663 * 664 * Configure interrupt throttling values for the ring containers that are 665 * associated with the interrupt vector passed in. 666 */ 667 void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector) 668 { 669 ice_cfg_itr_gran(hw); 670 671 if (q_vector->num_ring_rx) { 672 struct ice_ring_container *rc = &q_vector->rx; 673 674 rc->target_itr = ITR_TO_REG(rc->itr_setting); 675 rc->next_update = jiffies + 1; 676 rc->current_itr = rc->target_itr; 677 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx), 678 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S); 679 } 680 681 if (q_vector->num_ring_tx) { 682 struct ice_ring_container *rc = &q_vector->tx; 683 684 rc->target_itr = ITR_TO_REG(rc->itr_setting); 685 rc->next_update = jiffies + 1; 686 rc->current_itr = rc->target_itr; 687 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx), 688 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S); 689 } 690 } 691 692 /** 693 * ice_cfg_txq_interrupt - configure interrupt on Tx queue 694 * @vsi: the VSI being configured 695 * @txq: Tx queue being mapped to MSI-X vector 696 * @msix_idx: MSI-X vector index within the function 697 * @itr_idx: ITR index of the interrupt cause 698 * 699 * Configure interrupt on Tx queue by associating Tx queue to MSI-X vector 700 * within the function space. 701 */ 702 void 703 ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx) 704 { 705 struct ice_pf *pf = vsi->back; 706 struct ice_hw *hw = &pf->hw; 707 u32 val; 708 709 itr_idx = (itr_idx << QINT_TQCTL_ITR_INDX_S) & QINT_TQCTL_ITR_INDX_M; 710 711 val = QINT_TQCTL_CAUSE_ENA_M | itr_idx | 712 ((msix_idx << QINT_TQCTL_MSIX_INDX_S) & QINT_TQCTL_MSIX_INDX_M); 713 714 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val); 715 if (ice_is_xdp_ena_vsi(vsi)) { 716 u32 xdp_txq = txq + vsi->num_xdp_txq; 717 718 wr32(hw, QINT_TQCTL(vsi->txq_map[xdp_txq]), 719 val); 720 } 721 ice_flush(hw); 722 } 723 724 /** 725 * ice_cfg_rxq_interrupt - configure interrupt on Rx queue 726 * @vsi: the VSI being configured 727 * @rxq: Rx queue being mapped to MSI-X vector 728 * @msix_idx: MSI-X vector index within the function 729 * @itr_idx: ITR index of the interrupt cause 730 * 731 * Configure interrupt on Rx queue by associating Rx queue to MSI-X vector 732 * within the function space. 733 */ 734 void 735 ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx) 736 { 737 struct ice_pf *pf = vsi->back; 738 struct ice_hw *hw = &pf->hw; 739 u32 val; 740 741 itr_idx = (itr_idx << QINT_RQCTL_ITR_INDX_S) & QINT_RQCTL_ITR_INDX_M; 742 743 val = QINT_RQCTL_CAUSE_ENA_M | itr_idx | 744 ((msix_idx << QINT_RQCTL_MSIX_INDX_S) & QINT_RQCTL_MSIX_INDX_M); 745 746 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val); 747 748 ice_flush(hw); 749 } 750 751 /** 752 * ice_trigger_sw_intr - trigger a software interrupt 753 * @hw: pointer to the HW structure 754 * @q_vector: interrupt vector to trigger the software interrupt for 755 */ 756 void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector) 757 { 758 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx), 759 (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) | 760 GLINT_DYN_CTL_SWINT_TRIG_M | 761 GLINT_DYN_CTL_INTENA_M); 762 } 763 764 /** 765 * ice_vsi_stop_tx_ring - Disable single Tx ring 766 * @vsi: the VSI being configured 767 * @rst_src: reset source 768 * @rel_vmvf_num: Relative ID of VF/VM 769 * @ring: Tx ring to be stopped 770 * @txq_meta: Meta data of Tx ring to be stopped 771 */ 772 int 773 ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src, 774 u16 rel_vmvf_num, struct ice_ring *ring, 775 struct ice_txq_meta *txq_meta) 776 { 777 struct ice_pf *pf = vsi->back; 778 struct ice_q_vector *q_vector; 779 struct ice_hw *hw = &pf->hw; 780 enum ice_status status; 781 u32 val; 782 783 /* clear cause_ena bit for disabled queues */ 784 val = rd32(hw, QINT_TQCTL(ring->reg_idx)); 785 val &= ~QINT_TQCTL_CAUSE_ENA_M; 786 wr32(hw, QINT_TQCTL(ring->reg_idx), val); 787 788 /* software is expected to wait for 100 ns */ 789 ndelay(100); 790 791 /* trigger a software interrupt for the vector 792 * associated to the queue to schedule NAPI handler 793 */ 794 q_vector = ring->q_vector; 795 if (q_vector) 796 ice_trigger_sw_intr(hw, q_vector); 797 798 status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx, 799 txq_meta->tc, 1, &txq_meta->q_handle, 800 &txq_meta->q_id, &txq_meta->q_teid, rst_src, 801 rel_vmvf_num, NULL); 802 803 /* if the disable queue command was exercised during an 804 * active reset flow, ICE_ERR_RESET_ONGOING is returned. 805 * This is not an error as the reset operation disables 806 * queues at the hardware level anyway. 807 */ 808 if (status == ICE_ERR_RESET_ONGOING) { 809 dev_dbg(ice_pf_to_dev(vsi->back), "Reset in progress. LAN Tx queues already disabled\n"); 810 } else if (status == ICE_ERR_DOES_NOT_EXIST) { 811 dev_dbg(ice_pf_to_dev(vsi->back), "LAN Tx queues do not exist, nothing to disable\n"); 812 } else if (status) { 813 dev_err(ice_pf_to_dev(vsi->back), "Failed to disable LAN Tx queues, error: %d\n", 814 status); 815 return -ENODEV; 816 } 817 818 return 0; 819 } 820 821 /** 822 * ice_fill_txq_meta - Prepare the Tx queue's meta data 823 * @vsi: VSI that ring belongs to 824 * @ring: ring that txq_meta will be based on 825 * @txq_meta: a helper struct that wraps Tx queue's information 826 * 827 * Set up a helper struct that will contain all the necessary fields that 828 * are needed for stopping Tx queue 829 */ 830 void 831 ice_fill_txq_meta(struct ice_vsi *vsi, struct ice_ring *ring, 832 struct ice_txq_meta *txq_meta) 833 { 834 u8 tc; 835 836 if (IS_ENABLED(CONFIG_DCB)) 837 tc = ring->dcb_tc; 838 else 839 tc = 0; 840 841 txq_meta->q_id = ring->reg_idx; 842 txq_meta->q_teid = ring->txq_teid; 843 txq_meta->q_handle = ring->q_handle; 844 txq_meta->vsi_idx = vsi->idx; 845 txq_meta->tc = tc; 846 } 847