1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019, Intel Corporation. */ 3 4 #include <net/xdp_sock_drv.h> 5 #include "ice_base.h" 6 #include "ice_lib.h" 7 #include "ice_dcb_lib.h" 8 9 /** 10 * __ice_vsi_get_qs_contig - Assign a contiguous chunk of queues to VSI 11 * @qs_cfg: gathered variables needed for PF->VSI queues assignment 12 * 13 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 14 */ 15 static int __ice_vsi_get_qs_contig(struct ice_qs_cfg *qs_cfg) 16 { 17 unsigned int offset, i; 18 19 mutex_lock(qs_cfg->qs_mutex); 20 offset = bitmap_find_next_zero_area(qs_cfg->pf_map, qs_cfg->pf_map_size, 21 0, qs_cfg->q_count, 0); 22 if (offset >= qs_cfg->pf_map_size) { 23 mutex_unlock(qs_cfg->qs_mutex); 24 return -ENOMEM; 25 } 26 27 bitmap_set(qs_cfg->pf_map, offset, qs_cfg->q_count); 28 for (i = 0; i < qs_cfg->q_count; i++) 29 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)(i + offset); 30 mutex_unlock(qs_cfg->qs_mutex); 31 32 return 0; 33 } 34 35 /** 36 * __ice_vsi_get_qs_sc - Assign a scattered queues from PF to VSI 37 * @qs_cfg: gathered variables needed for pf->vsi queues assignment 38 * 39 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 40 */ 41 static int __ice_vsi_get_qs_sc(struct ice_qs_cfg *qs_cfg) 42 { 43 unsigned int i, index = 0; 44 45 mutex_lock(qs_cfg->qs_mutex); 46 for (i = 0; i < qs_cfg->q_count; i++) { 47 index = find_next_zero_bit(qs_cfg->pf_map, 48 qs_cfg->pf_map_size, index); 49 if (index >= qs_cfg->pf_map_size) 50 goto err_scatter; 51 set_bit(index, qs_cfg->pf_map); 52 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)index; 53 } 54 mutex_unlock(qs_cfg->qs_mutex); 55 56 return 0; 57 err_scatter: 58 for (index = 0; index < i; index++) { 59 clear_bit(qs_cfg->vsi_map[index], qs_cfg->pf_map); 60 qs_cfg->vsi_map[index + qs_cfg->vsi_map_offset] = 0; 61 } 62 mutex_unlock(qs_cfg->qs_mutex); 63 64 return -ENOMEM; 65 } 66 67 /** 68 * ice_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled 69 * @pf: the PF being configured 70 * @pf_q: the PF queue 71 * @ena: enable or disable state of the queue 72 * 73 * This routine will wait for the given Rx queue of the PF to reach the 74 * enabled or disabled state. 75 * Returns -ETIMEDOUT in case of failing to reach the requested state after 76 * multiple retries; else will return 0 in case of success. 77 */ 78 static int ice_pf_rxq_wait(struct ice_pf *pf, int pf_q, bool ena) 79 { 80 int i; 81 82 for (i = 0; i < ICE_Q_WAIT_MAX_RETRY; i++) { 83 if (ena == !!(rd32(&pf->hw, QRX_CTRL(pf_q)) & 84 QRX_CTRL_QENA_STAT_M)) 85 return 0; 86 87 usleep_range(20, 40); 88 } 89 90 return -ETIMEDOUT; 91 } 92 93 /** 94 * ice_vsi_alloc_q_vector - Allocate memory for a single interrupt vector 95 * @vsi: the VSI being configured 96 * @v_idx: index of the vector in the VSI struct 97 * 98 * We allocate one q_vector and set default value for ITR setting associated 99 * with this q_vector. If allocation fails we return -ENOMEM. 100 */ 101 static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, u16 v_idx) 102 { 103 struct ice_pf *pf = vsi->back; 104 struct ice_q_vector *q_vector; 105 106 /* allocate q_vector */ 107 q_vector = devm_kzalloc(ice_pf_to_dev(pf), sizeof(*q_vector), 108 GFP_KERNEL); 109 if (!q_vector) 110 return -ENOMEM; 111 112 q_vector->vsi = vsi; 113 q_vector->v_idx = v_idx; 114 q_vector->tx.itr_setting = ICE_DFLT_TX_ITR; 115 q_vector->rx.itr_setting = ICE_DFLT_RX_ITR; 116 q_vector->tx.itr_mode = ITR_DYNAMIC; 117 q_vector->rx.itr_mode = ITR_DYNAMIC; 118 q_vector->tx.type = ICE_TX_CONTAINER; 119 q_vector->rx.type = ICE_RX_CONTAINER; 120 121 if (vsi->type == ICE_VSI_VF) 122 goto out; 123 /* only set affinity_mask if the CPU is online */ 124 if (cpu_online(v_idx)) 125 cpumask_set_cpu(v_idx, &q_vector->affinity_mask); 126 127 /* This will not be called in the driver load path because the netdev 128 * will not be created yet. All other cases with register the NAPI 129 * handler here (i.e. resume, reset/rebuild, etc.) 130 */ 131 if (vsi->netdev) 132 netif_napi_add(vsi->netdev, &q_vector->napi, ice_napi_poll, 133 NAPI_POLL_WEIGHT); 134 135 out: 136 /* tie q_vector and VSI together */ 137 vsi->q_vectors[v_idx] = q_vector; 138 139 return 0; 140 } 141 142 /** 143 * ice_free_q_vector - Free memory allocated for a specific interrupt vector 144 * @vsi: VSI having the memory freed 145 * @v_idx: index of the vector to be freed 146 */ 147 static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx) 148 { 149 struct ice_q_vector *q_vector; 150 struct ice_pf *pf = vsi->back; 151 struct ice_tx_ring *tx_ring; 152 struct ice_rx_ring *rx_ring; 153 struct device *dev; 154 155 dev = ice_pf_to_dev(pf); 156 if (!vsi->q_vectors[v_idx]) { 157 dev_dbg(dev, "Queue vector at index %d not found\n", v_idx); 158 return; 159 } 160 q_vector = vsi->q_vectors[v_idx]; 161 162 ice_for_each_tx_ring(tx_ring, q_vector->tx) 163 tx_ring->q_vector = NULL; 164 ice_for_each_rx_ring(rx_ring, q_vector->rx) 165 rx_ring->q_vector = NULL; 166 167 /* only VSI with an associated netdev is set up with NAPI */ 168 if (vsi->netdev) 169 netif_napi_del(&q_vector->napi); 170 171 devm_kfree(dev, q_vector); 172 vsi->q_vectors[v_idx] = NULL; 173 } 174 175 /** 176 * ice_cfg_itr_gran - set the ITR granularity to 2 usecs if not already set 177 * @hw: board specific structure 178 */ 179 static void ice_cfg_itr_gran(struct ice_hw *hw) 180 { 181 u32 regval = rd32(hw, GLINT_CTL); 182 183 /* no need to update global register if ITR gran is already set */ 184 if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) && 185 (((regval & GLINT_CTL_ITR_GRAN_200_M) >> 186 GLINT_CTL_ITR_GRAN_200_S) == ICE_ITR_GRAN_US) && 187 (((regval & GLINT_CTL_ITR_GRAN_100_M) >> 188 GLINT_CTL_ITR_GRAN_100_S) == ICE_ITR_GRAN_US) && 189 (((regval & GLINT_CTL_ITR_GRAN_50_M) >> 190 GLINT_CTL_ITR_GRAN_50_S) == ICE_ITR_GRAN_US) && 191 (((regval & GLINT_CTL_ITR_GRAN_25_M) >> 192 GLINT_CTL_ITR_GRAN_25_S) == ICE_ITR_GRAN_US)) 193 return; 194 195 regval = ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_200_S) & 196 GLINT_CTL_ITR_GRAN_200_M) | 197 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_100_S) & 198 GLINT_CTL_ITR_GRAN_100_M) | 199 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_50_S) & 200 GLINT_CTL_ITR_GRAN_50_M) | 201 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_25_S) & 202 GLINT_CTL_ITR_GRAN_25_M); 203 wr32(hw, GLINT_CTL, regval); 204 } 205 206 /** 207 * ice_calc_txq_handle - calculate the queue handle 208 * @vsi: VSI that ring belongs to 209 * @ring: ring to get the absolute queue index 210 * @tc: traffic class number 211 */ 212 static u16 ice_calc_txq_handle(struct ice_vsi *vsi, struct ice_tx_ring *ring, u8 tc) 213 { 214 WARN_ONCE(ice_ring_is_xdp(ring) && tc, "XDP ring can't belong to TC other than 0\n"); 215 216 if (ring->ch) 217 return ring->q_index - ring->ch->base_q; 218 219 /* Idea here for calculation is that we subtract the number of queue 220 * count from TC that ring belongs to from it's absolute queue index 221 * and as a result we get the queue's index within TC. 222 */ 223 return ring->q_index - vsi->tc_cfg.tc_info[tc].qoffset; 224 } 225 226 /** 227 * ice_eswitch_calc_txq_handle 228 * @ring: pointer to ring which unique index is needed 229 * 230 * To correctly work with many netdevs ring->q_index of Tx rings on switchdev 231 * VSI can repeat. Hardware ring setup requires unique q_index. Calculate it 232 * here by finding index in vsi->tx_rings of this ring. 233 * 234 * Return ICE_INVAL_Q_INDEX when index wasn't found. Should never happen, 235 * because VSI is get from ring->vsi, so it has to be present in this VSI. 236 */ 237 static u16 ice_eswitch_calc_txq_handle(struct ice_tx_ring *ring) 238 { 239 struct ice_vsi *vsi = ring->vsi; 240 int i; 241 242 ice_for_each_txq(vsi, i) { 243 if (vsi->tx_rings[i] == ring) 244 return i; 245 } 246 247 return ICE_INVAL_Q_INDEX; 248 } 249 250 /** 251 * ice_cfg_xps_tx_ring - Configure XPS for a Tx ring 252 * @ring: The Tx ring to configure 253 * 254 * This enables/disables XPS for a given Tx descriptor ring 255 * based on the TCs enabled for the VSI that ring belongs to. 256 */ 257 static void ice_cfg_xps_tx_ring(struct ice_tx_ring *ring) 258 { 259 if (!ring->q_vector || !ring->netdev) 260 return; 261 262 /* We only initialize XPS once, so as not to overwrite user settings */ 263 if (test_and_set_bit(ICE_TX_XPS_INIT_DONE, ring->xps_state)) 264 return; 265 266 netif_set_xps_queue(ring->netdev, &ring->q_vector->affinity_mask, 267 ring->q_index); 268 } 269 270 /** 271 * ice_setup_tx_ctx - setup a struct ice_tlan_ctx instance 272 * @ring: The Tx ring to configure 273 * @tlan_ctx: Pointer to the Tx LAN queue context structure to be initialized 274 * @pf_q: queue index in the PF space 275 * 276 * Configure the Tx descriptor ring in TLAN context. 277 */ 278 static void 279 ice_setup_tx_ctx(struct ice_tx_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q) 280 { 281 struct ice_vsi *vsi = ring->vsi; 282 struct ice_hw *hw = &vsi->back->hw; 283 284 tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S; 285 286 tlan_ctx->port_num = vsi->port_info->lport; 287 288 /* Transmit Queue Length */ 289 tlan_ctx->qlen = ring->count; 290 291 ice_set_cgd_num(tlan_ctx, ring->dcb_tc); 292 293 /* PF number */ 294 tlan_ctx->pf_num = hw->pf_id; 295 296 /* queue belongs to a specific VSI type 297 * VF / VM index should be programmed per vmvf_type setting: 298 * for vmvf_type = VF, it is VF number between 0-256 299 * for vmvf_type = VM, it is VM number between 0-767 300 * for PF or EMP this field should be set to zero 301 */ 302 switch (vsi->type) { 303 case ICE_VSI_LB: 304 case ICE_VSI_CTRL: 305 case ICE_VSI_PF: 306 if (ring->ch) 307 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VMQ; 308 else 309 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF; 310 break; 311 case ICE_VSI_VF: 312 /* Firmware expects vmvf_num to be absolute VF ID */ 313 tlan_ctx->vmvf_num = hw->func_caps.vf_base_id + vsi->vf_id; 314 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF; 315 break; 316 case ICE_VSI_SWITCHDEV_CTRL: 317 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VMQ; 318 break; 319 default: 320 return; 321 } 322 323 /* make sure the context is associated with the right VSI */ 324 if (ring->ch) 325 tlan_ctx->src_vsi = ring->ch->vsi_num; 326 else 327 tlan_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx); 328 329 /* Restrict Tx timestamps to the PF VSI */ 330 switch (vsi->type) { 331 case ICE_VSI_PF: 332 tlan_ctx->tsyn_ena = 1; 333 break; 334 default: 335 break; 336 } 337 338 tlan_ctx->tso_ena = ICE_TX_LEGACY; 339 tlan_ctx->tso_qnum = pf_q; 340 341 /* Legacy or Advanced Host Interface: 342 * 0: Advanced Host Interface 343 * 1: Legacy Host Interface 344 */ 345 tlan_ctx->legacy_int = ICE_TX_LEGACY; 346 } 347 348 /** 349 * ice_rx_offset - Return expected offset into page to access data 350 * @rx_ring: Ring we are requesting offset of 351 * 352 * Returns the offset value for ring into the data buffer. 353 */ 354 static unsigned int ice_rx_offset(struct ice_rx_ring *rx_ring) 355 { 356 if (ice_ring_uses_build_skb(rx_ring)) 357 return ICE_SKB_PAD; 358 else if (ice_is_xdp_ena_vsi(rx_ring->vsi)) 359 return XDP_PACKET_HEADROOM; 360 361 return 0; 362 } 363 364 /** 365 * ice_setup_rx_ctx - Configure a receive ring context 366 * @ring: The Rx ring to configure 367 * 368 * Configure the Rx descriptor ring in RLAN context. 369 */ 370 static int ice_setup_rx_ctx(struct ice_rx_ring *ring) 371 { 372 int chain_len = ICE_MAX_CHAINED_RX_BUFS; 373 struct ice_vsi *vsi = ring->vsi; 374 u32 rxdid = ICE_RXDID_FLEX_NIC; 375 struct ice_rlan_ctx rlan_ctx; 376 struct ice_hw *hw; 377 u16 pf_q; 378 int err; 379 380 hw = &vsi->back->hw; 381 382 /* what is Rx queue number in global space of 2K Rx queues */ 383 pf_q = vsi->rxq_map[ring->q_index]; 384 385 /* clear the context structure first */ 386 memset(&rlan_ctx, 0, sizeof(rlan_ctx)); 387 388 /* Receive Queue Base Address. 389 * Indicates the starting address of the descriptor queue defined in 390 * 128 Byte units. 391 */ 392 rlan_ctx.base = ring->dma >> 7; 393 394 rlan_ctx.qlen = ring->count; 395 396 /* Receive Packet Data Buffer Size. 397 * The Packet Data Buffer Size is defined in 128 byte units. 398 */ 399 rlan_ctx.dbuf = ring->rx_buf_len >> ICE_RLAN_CTX_DBUF_S; 400 401 /* use 32 byte descriptors */ 402 rlan_ctx.dsize = 1; 403 404 /* Strip the Ethernet CRC bytes before the packet is posted to host 405 * memory. 406 */ 407 rlan_ctx.crcstrip = 1; 408 409 /* L2TSEL flag defines the reported L2 Tags in the receive descriptor */ 410 rlan_ctx.l2tsel = 1; 411 412 rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT; 413 rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_NO_SPLIT; 414 rlan_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_NO_SPLIT; 415 416 /* This controls whether VLAN is stripped from inner headers 417 * The VLAN in the inner L2 header is stripped to the receive 418 * descriptor if enabled by this flag. 419 */ 420 rlan_ctx.showiv = 0; 421 422 /* For AF_XDP ZC, we disallow packets to span on 423 * multiple buffers, thus letting us skip that 424 * handling in the fast-path. 425 */ 426 if (ring->xsk_pool) 427 chain_len = 1; 428 /* Max packet size for this queue - must not be set to a larger value 429 * than 5 x DBUF 430 */ 431 rlan_ctx.rxmax = min_t(u32, vsi->max_frame, 432 chain_len * ring->rx_buf_len); 433 434 /* Rx queue threshold in units of 64 */ 435 rlan_ctx.lrxqthresh = 1; 436 437 /* Enable Flexible Descriptors in the queue context which 438 * allows this driver to select a specific receive descriptor format 439 * increasing context priority to pick up profile ID; default is 0x01; 440 * setting to 0x03 to ensure profile is programming if prev context is 441 * of same priority 442 */ 443 if (vsi->type != ICE_VSI_VF) 444 ice_write_qrxflxp_cntxt(hw, pf_q, rxdid, 0x3, true); 445 else 446 ice_write_qrxflxp_cntxt(hw, pf_q, ICE_RXDID_LEGACY_1, 0x3, 447 false); 448 449 /* Absolute queue number out of 2K needs to be passed */ 450 err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q); 451 if (err) { 452 dev_err(ice_pf_to_dev(vsi->back), "Failed to set LAN Rx queue context for absolute Rx queue %d error: %d\n", 453 pf_q, err); 454 return -EIO; 455 } 456 457 if (vsi->type == ICE_VSI_VF) 458 return 0; 459 460 /* configure Rx buffer alignment */ 461 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags)) 462 ice_clear_ring_build_skb_ena(ring); 463 else 464 ice_set_ring_build_skb_ena(ring); 465 466 ring->rx_offset = ice_rx_offset(ring); 467 468 /* init queue specific tail register */ 469 ring->tail = hw->hw_addr + QRX_TAIL(pf_q); 470 writel(0, ring->tail); 471 472 return 0; 473 } 474 475 /** 476 * ice_vsi_cfg_rxq - Configure an Rx queue 477 * @ring: the ring being configured 478 * 479 * Return 0 on success and a negative value on error. 480 */ 481 int ice_vsi_cfg_rxq(struct ice_rx_ring *ring) 482 { 483 struct device *dev = ice_pf_to_dev(ring->vsi->back); 484 u16 num_bufs = ICE_DESC_UNUSED(ring); 485 int err; 486 487 ring->rx_buf_len = ring->vsi->rx_buf_len; 488 489 if (ring->vsi->type == ICE_VSI_PF) { 490 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) 491 /* coverity[check_return] */ 492 xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev, 493 ring->q_index, ring->q_vector->napi.napi_id); 494 495 ring->xsk_pool = ice_xsk_pool(ring); 496 if (ring->xsk_pool) { 497 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 498 499 ring->rx_buf_len = 500 xsk_pool_get_rx_frame_size(ring->xsk_pool); 501 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 502 MEM_TYPE_XSK_BUFF_POOL, 503 NULL); 504 if (err) 505 return err; 506 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 507 508 dev_info(dev, "Registered XDP mem model MEM_TYPE_XSK_BUFF_POOL on Rx ring %d\n", 509 ring->q_index); 510 } else { 511 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) 512 /* coverity[check_return] */ 513 xdp_rxq_info_reg(&ring->xdp_rxq, 514 ring->netdev, 515 ring->q_index, ring->q_vector->napi.napi_id); 516 517 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 518 MEM_TYPE_PAGE_SHARED, 519 NULL); 520 if (err) 521 return err; 522 } 523 } 524 525 err = ice_setup_rx_ctx(ring); 526 if (err) { 527 dev_err(dev, "ice_setup_rx_ctx failed for RxQ %d, err %d\n", 528 ring->q_index, err); 529 return err; 530 } 531 532 if (ring->xsk_pool) { 533 bool ok; 534 535 if (!xsk_buff_can_alloc(ring->xsk_pool, num_bufs)) { 536 dev_warn(dev, "XSK buffer pool does not provide enough addresses to fill %d buffers on Rx ring %d\n", 537 num_bufs, ring->q_index); 538 dev_warn(dev, "Change Rx ring/fill queue size to avoid performance issues\n"); 539 540 return 0; 541 } 542 543 ok = ice_alloc_rx_bufs_zc(ring, num_bufs); 544 if (!ok) { 545 u16 pf_q = ring->vsi->rxq_map[ring->q_index]; 546 547 dev_info(dev, "Failed to allocate some buffers on XSK buffer pool enabled Rx ring %d (pf_q %d)\n", 548 ring->q_index, pf_q); 549 } 550 551 return 0; 552 } 553 554 ice_alloc_rx_bufs(ring, num_bufs); 555 556 return 0; 557 } 558 559 /** 560 * __ice_vsi_get_qs - helper function for assigning queues from PF to VSI 561 * @qs_cfg: gathered variables needed for pf->vsi queues assignment 562 * 563 * This function first tries to find contiguous space. If it is not successful, 564 * it tries with the scatter approach. 565 * 566 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 567 */ 568 int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg) 569 { 570 int ret = 0; 571 572 ret = __ice_vsi_get_qs_contig(qs_cfg); 573 if (ret) { 574 /* contig failed, so try with scatter approach */ 575 qs_cfg->mapping_mode = ICE_VSI_MAP_SCATTER; 576 qs_cfg->q_count = min_t(unsigned int, qs_cfg->q_count, 577 qs_cfg->scatter_count); 578 ret = __ice_vsi_get_qs_sc(qs_cfg); 579 } 580 return ret; 581 } 582 583 /** 584 * ice_vsi_ctrl_one_rx_ring - start/stop VSI's Rx ring with no busy wait 585 * @vsi: the VSI being configured 586 * @ena: start or stop the Rx ring 587 * @rxq_idx: 0-based Rx queue index for the VSI passed in 588 * @wait: wait or don't wait for configuration to finish in hardware 589 * 590 * Return 0 on success and negative on error. 591 */ 592 int 593 ice_vsi_ctrl_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx, bool wait) 594 { 595 int pf_q = vsi->rxq_map[rxq_idx]; 596 struct ice_pf *pf = vsi->back; 597 struct ice_hw *hw = &pf->hw; 598 u32 rx_reg; 599 600 rx_reg = rd32(hw, QRX_CTRL(pf_q)); 601 602 /* Skip if the queue is already in the requested state */ 603 if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M)) 604 return 0; 605 606 /* turn on/off the queue */ 607 if (ena) 608 rx_reg |= QRX_CTRL_QENA_REQ_M; 609 else 610 rx_reg &= ~QRX_CTRL_QENA_REQ_M; 611 wr32(hw, QRX_CTRL(pf_q), rx_reg); 612 613 if (!wait) 614 return 0; 615 616 ice_flush(hw); 617 return ice_pf_rxq_wait(pf, pf_q, ena); 618 } 619 620 /** 621 * ice_vsi_wait_one_rx_ring - wait for a VSI's Rx ring to be stopped/started 622 * @vsi: the VSI being configured 623 * @ena: true/false to verify Rx ring has been enabled/disabled respectively 624 * @rxq_idx: 0-based Rx queue index for the VSI passed in 625 * 626 * This routine will wait for the given Rx queue of the VSI to reach the 627 * enabled or disabled state. Returns -ETIMEDOUT in case of failing to reach 628 * the requested state after multiple retries; else will return 0 in case of 629 * success. 630 */ 631 int ice_vsi_wait_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx) 632 { 633 int pf_q = vsi->rxq_map[rxq_idx]; 634 struct ice_pf *pf = vsi->back; 635 636 return ice_pf_rxq_wait(pf, pf_q, ena); 637 } 638 639 /** 640 * ice_vsi_alloc_q_vectors - Allocate memory for interrupt vectors 641 * @vsi: the VSI being configured 642 * 643 * We allocate one q_vector per queue interrupt. If allocation fails we 644 * return -ENOMEM. 645 */ 646 int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi) 647 { 648 struct device *dev = ice_pf_to_dev(vsi->back); 649 u16 v_idx; 650 int err; 651 652 if (vsi->q_vectors[0]) { 653 dev_dbg(dev, "VSI %d has existing q_vectors\n", vsi->vsi_num); 654 return -EEXIST; 655 } 656 657 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) { 658 err = ice_vsi_alloc_q_vector(vsi, v_idx); 659 if (err) 660 goto err_out; 661 } 662 663 return 0; 664 665 err_out: 666 while (v_idx--) 667 ice_free_q_vector(vsi, v_idx); 668 669 dev_err(dev, "Failed to allocate %d q_vector for VSI %d, ret=%d\n", 670 vsi->num_q_vectors, vsi->vsi_num, err); 671 vsi->num_q_vectors = 0; 672 return err; 673 } 674 675 /** 676 * ice_vsi_map_rings_to_vectors - Map VSI rings to interrupt vectors 677 * @vsi: the VSI being configured 678 * 679 * This function maps descriptor rings to the queue-specific vectors allotted 680 * through the MSI-X enabling code. On a constrained vector budget, we map Tx 681 * and Rx rings to the vector as "efficiently" as possible. 682 */ 683 void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi) 684 { 685 int q_vectors = vsi->num_q_vectors; 686 u16 tx_rings_rem, rx_rings_rem; 687 int v_id; 688 689 /* initially assigning remaining rings count to VSIs num queue value */ 690 tx_rings_rem = vsi->num_txq; 691 rx_rings_rem = vsi->num_rxq; 692 693 for (v_id = 0; v_id < q_vectors; v_id++) { 694 struct ice_q_vector *q_vector = vsi->q_vectors[v_id]; 695 u8 tx_rings_per_v, rx_rings_per_v; 696 u16 q_id, q_base; 697 698 /* Tx rings mapping to vector */ 699 tx_rings_per_v = (u8)DIV_ROUND_UP(tx_rings_rem, 700 q_vectors - v_id); 701 q_vector->num_ring_tx = tx_rings_per_v; 702 q_vector->tx.tx_ring = NULL; 703 q_vector->tx.itr_idx = ICE_TX_ITR; 704 q_base = vsi->num_txq - tx_rings_rem; 705 706 for (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) { 707 struct ice_tx_ring *tx_ring = vsi->tx_rings[q_id]; 708 709 tx_ring->q_vector = q_vector; 710 tx_ring->next = q_vector->tx.tx_ring; 711 q_vector->tx.tx_ring = tx_ring; 712 } 713 tx_rings_rem -= tx_rings_per_v; 714 715 /* Rx rings mapping to vector */ 716 rx_rings_per_v = (u8)DIV_ROUND_UP(rx_rings_rem, 717 q_vectors - v_id); 718 q_vector->num_ring_rx = rx_rings_per_v; 719 q_vector->rx.rx_ring = NULL; 720 q_vector->rx.itr_idx = ICE_RX_ITR; 721 q_base = vsi->num_rxq - rx_rings_rem; 722 723 for (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) { 724 struct ice_rx_ring *rx_ring = vsi->rx_rings[q_id]; 725 726 rx_ring->q_vector = q_vector; 727 rx_ring->next = q_vector->rx.rx_ring; 728 q_vector->rx.rx_ring = rx_ring; 729 } 730 rx_rings_rem -= rx_rings_per_v; 731 } 732 } 733 734 /** 735 * ice_vsi_free_q_vectors - Free memory allocated for interrupt vectors 736 * @vsi: the VSI having memory freed 737 */ 738 void ice_vsi_free_q_vectors(struct ice_vsi *vsi) 739 { 740 int v_idx; 741 742 ice_for_each_q_vector(vsi, v_idx) 743 ice_free_q_vector(vsi, v_idx); 744 } 745 746 /** 747 * ice_vsi_cfg_txq - Configure single Tx queue 748 * @vsi: the VSI that queue belongs to 749 * @ring: Tx ring to be configured 750 * @qg_buf: queue group buffer 751 */ 752 int 753 ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_tx_ring *ring, 754 struct ice_aqc_add_tx_qgrp *qg_buf) 755 { 756 u8 buf_len = struct_size(qg_buf, txqs, 1); 757 struct ice_tlan_ctx tlan_ctx = { 0 }; 758 struct ice_aqc_add_txqs_perq *txq; 759 struct ice_channel *ch = ring->ch; 760 struct ice_pf *pf = vsi->back; 761 struct ice_hw *hw = &pf->hw; 762 enum ice_status status; 763 u16 pf_q; 764 u8 tc; 765 766 /* Configure XPS */ 767 ice_cfg_xps_tx_ring(ring); 768 769 pf_q = ring->reg_idx; 770 ice_setup_tx_ctx(ring, &tlan_ctx, pf_q); 771 /* copy context contents into the qg_buf */ 772 qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q); 773 ice_set_ctx(hw, (u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx, 774 ice_tlan_ctx_info); 775 776 /* init queue specific tail reg. It is referred as 777 * transmit comm scheduler queue doorbell. 778 */ 779 ring->tail = hw->hw_addr + QTX_COMM_DBELL(pf_q); 780 781 if (IS_ENABLED(CONFIG_DCB)) 782 tc = ring->dcb_tc; 783 else 784 tc = 0; 785 786 /* Add unique software queue handle of the Tx queue per 787 * TC into the VSI Tx ring 788 */ 789 if (vsi->type == ICE_VSI_SWITCHDEV_CTRL) { 790 ring->q_handle = ice_eswitch_calc_txq_handle(ring); 791 792 if (ring->q_handle == ICE_INVAL_Q_INDEX) 793 return -ENODEV; 794 } else { 795 ring->q_handle = ice_calc_txq_handle(vsi, ring, tc); 796 } 797 798 if (ch) 799 status = ice_ena_vsi_txq(vsi->port_info, ch->ch_vsi->idx, 0, 800 ring->q_handle, 1, qg_buf, buf_len, 801 NULL); 802 else 803 status = ice_ena_vsi_txq(vsi->port_info, vsi->idx, tc, 804 ring->q_handle, 1, qg_buf, buf_len, 805 NULL); 806 if (status) { 807 dev_err(ice_pf_to_dev(pf), "Failed to set LAN Tx queue context, error: %s\n", 808 ice_stat_str(status)); 809 return -ENODEV; 810 } 811 812 /* Add Tx Queue TEID into the VSI Tx ring from the 813 * response. This will complete configuring and 814 * enabling the queue. 815 */ 816 txq = &qg_buf->txqs[0]; 817 if (pf_q == le16_to_cpu(txq->txq_id)) 818 ring->txq_teid = le32_to_cpu(txq->q_teid); 819 820 return 0; 821 } 822 823 /** 824 * ice_cfg_itr - configure the initial interrupt throttle values 825 * @hw: pointer to the HW structure 826 * @q_vector: interrupt vector that's being configured 827 * 828 * Configure interrupt throttling values for the ring containers that are 829 * associated with the interrupt vector passed in. 830 */ 831 void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector) 832 { 833 ice_cfg_itr_gran(hw); 834 835 if (q_vector->num_ring_rx) 836 ice_write_itr(&q_vector->rx, q_vector->rx.itr_setting); 837 838 if (q_vector->num_ring_tx) 839 ice_write_itr(&q_vector->tx, q_vector->tx.itr_setting); 840 841 ice_write_intrl(q_vector, q_vector->intrl); 842 } 843 844 /** 845 * ice_cfg_txq_interrupt - configure interrupt on Tx queue 846 * @vsi: the VSI being configured 847 * @txq: Tx queue being mapped to MSI-X vector 848 * @msix_idx: MSI-X vector index within the function 849 * @itr_idx: ITR index of the interrupt cause 850 * 851 * Configure interrupt on Tx queue by associating Tx queue to MSI-X vector 852 * within the function space. 853 */ 854 void 855 ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx) 856 { 857 struct ice_pf *pf = vsi->back; 858 struct ice_hw *hw = &pf->hw; 859 u32 val; 860 861 itr_idx = (itr_idx << QINT_TQCTL_ITR_INDX_S) & QINT_TQCTL_ITR_INDX_M; 862 863 val = QINT_TQCTL_CAUSE_ENA_M | itr_idx | 864 ((msix_idx << QINT_TQCTL_MSIX_INDX_S) & QINT_TQCTL_MSIX_INDX_M); 865 866 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val); 867 if (ice_is_xdp_ena_vsi(vsi)) { 868 u32 xdp_txq = txq + vsi->num_xdp_txq; 869 870 wr32(hw, QINT_TQCTL(vsi->txq_map[xdp_txq]), 871 val); 872 } 873 ice_flush(hw); 874 } 875 876 /** 877 * ice_cfg_rxq_interrupt - configure interrupt on Rx queue 878 * @vsi: the VSI being configured 879 * @rxq: Rx queue being mapped to MSI-X vector 880 * @msix_idx: MSI-X vector index within the function 881 * @itr_idx: ITR index of the interrupt cause 882 * 883 * Configure interrupt on Rx queue by associating Rx queue to MSI-X vector 884 * within the function space. 885 */ 886 void 887 ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx) 888 { 889 struct ice_pf *pf = vsi->back; 890 struct ice_hw *hw = &pf->hw; 891 u32 val; 892 893 itr_idx = (itr_idx << QINT_RQCTL_ITR_INDX_S) & QINT_RQCTL_ITR_INDX_M; 894 895 val = QINT_RQCTL_CAUSE_ENA_M | itr_idx | 896 ((msix_idx << QINT_RQCTL_MSIX_INDX_S) & QINT_RQCTL_MSIX_INDX_M); 897 898 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val); 899 900 ice_flush(hw); 901 } 902 903 /** 904 * ice_trigger_sw_intr - trigger a software interrupt 905 * @hw: pointer to the HW structure 906 * @q_vector: interrupt vector to trigger the software interrupt for 907 */ 908 void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector) 909 { 910 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx), 911 (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) | 912 GLINT_DYN_CTL_SWINT_TRIG_M | 913 GLINT_DYN_CTL_INTENA_M); 914 } 915 916 /** 917 * ice_vsi_stop_tx_ring - Disable single Tx ring 918 * @vsi: the VSI being configured 919 * @rst_src: reset source 920 * @rel_vmvf_num: Relative ID of VF/VM 921 * @ring: Tx ring to be stopped 922 * @txq_meta: Meta data of Tx ring to be stopped 923 */ 924 int 925 ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src, 926 u16 rel_vmvf_num, struct ice_tx_ring *ring, 927 struct ice_txq_meta *txq_meta) 928 { 929 struct ice_pf *pf = vsi->back; 930 struct ice_q_vector *q_vector; 931 struct ice_hw *hw = &pf->hw; 932 enum ice_status status; 933 u32 val; 934 935 /* clear cause_ena bit for disabled queues */ 936 val = rd32(hw, QINT_TQCTL(ring->reg_idx)); 937 val &= ~QINT_TQCTL_CAUSE_ENA_M; 938 wr32(hw, QINT_TQCTL(ring->reg_idx), val); 939 940 /* software is expected to wait for 100 ns */ 941 ndelay(100); 942 943 /* trigger a software interrupt for the vector 944 * associated to the queue to schedule NAPI handler 945 */ 946 q_vector = ring->q_vector; 947 if (q_vector) 948 ice_trigger_sw_intr(hw, q_vector); 949 950 status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx, 951 txq_meta->tc, 1, &txq_meta->q_handle, 952 &txq_meta->q_id, &txq_meta->q_teid, rst_src, 953 rel_vmvf_num, NULL); 954 955 /* if the disable queue command was exercised during an 956 * active reset flow, ICE_ERR_RESET_ONGOING is returned. 957 * This is not an error as the reset operation disables 958 * queues at the hardware level anyway. 959 */ 960 if (status == ICE_ERR_RESET_ONGOING) { 961 dev_dbg(ice_pf_to_dev(vsi->back), "Reset in progress. LAN Tx queues already disabled\n"); 962 } else if (status == ICE_ERR_DOES_NOT_EXIST) { 963 dev_dbg(ice_pf_to_dev(vsi->back), "LAN Tx queues do not exist, nothing to disable\n"); 964 } else if (status) { 965 dev_dbg(ice_pf_to_dev(vsi->back), "Failed to disable LAN Tx queues, error: %s\n", 966 ice_stat_str(status)); 967 return -ENODEV; 968 } 969 970 return 0; 971 } 972 973 /** 974 * ice_fill_txq_meta - Prepare the Tx queue's meta data 975 * @vsi: VSI that ring belongs to 976 * @ring: ring that txq_meta will be based on 977 * @txq_meta: a helper struct that wraps Tx queue's information 978 * 979 * Set up a helper struct that will contain all the necessary fields that 980 * are needed for stopping Tx queue 981 */ 982 void 983 ice_fill_txq_meta(struct ice_vsi *vsi, struct ice_tx_ring *ring, 984 struct ice_txq_meta *txq_meta) 985 { 986 struct ice_channel *ch = ring->ch; 987 u8 tc; 988 989 if (IS_ENABLED(CONFIG_DCB)) 990 tc = ring->dcb_tc; 991 else 992 tc = 0; 993 994 txq_meta->q_id = ring->reg_idx; 995 txq_meta->q_teid = ring->txq_teid; 996 txq_meta->q_handle = ring->q_handle; 997 if (ch) { 998 txq_meta->vsi_idx = ch->ch_vsi->idx; 999 txq_meta->tc = 0; 1000 } else { 1001 txq_meta->vsi_idx = vsi->idx; 1002 txq_meta->tc = tc; 1003 } 1004 } 1005