1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019, Intel Corporation. */ 3 4 #include <net/xdp_sock_drv.h> 5 #include "ice_base.h" 6 #include "ice_lib.h" 7 #include "ice_dcb_lib.h" 8 9 /** 10 * __ice_vsi_get_qs_contig - Assign a contiguous chunk of queues to VSI 11 * @qs_cfg: gathered variables needed for PF->VSI queues assignment 12 * 13 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 14 */ 15 static int __ice_vsi_get_qs_contig(struct ice_qs_cfg *qs_cfg) 16 { 17 unsigned int offset, i; 18 19 mutex_lock(qs_cfg->qs_mutex); 20 offset = bitmap_find_next_zero_area(qs_cfg->pf_map, qs_cfg->pf_map_size, 21 0, qs_cfg->q_count, 0); 22 if (offset >= qs_cfg->pf_map_size) { 23 mutex_unlock(qs_cfg->qs_mutex); 24 return -ENOMEM; 25 } 26 27 bitmap_set(qs_cfg->pf_map, offset, qs_cfg->q_count); 28 for (i = 0; i < qs_cfg->q_count; i++) 29 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)(i + offset); 30 mutex_unlock(qs_cfg->qs_mutex); 31 32 return 0; 33 } 34 35 /** 36 * __ice_vsi_get_qs_sc - Assign a scattered queues from PF to VSI 37 * @qs_cfg: gathered variables needed for pf->vsi queues assignment 38 * 39 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 40 */ 41 static int __ice_vsi_get_qs_sc(struct ice_qs_cfg *qs_cfg) 42 { 43 unsigned int i, index = 0; 44 45 mutex_lock(qs_cfg->qs_mutex); 46 for (i = 0; i < qs_cfg->q_count; i++) { 47 index = find_next_zero_bit(qs_cfg->pf_map, 48 qs_cfg->pf_map_size, index); 49 if (index >= qs_cfg->pf_map_size) 50 goto err_scatter; 51 set_bit(index, qs_cfg->pf_map); 52 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)index; 53 } 54 mutex_unlock(qs_cfg->qs_mutex); 55 56 return 0; 57 err_scatter: 58 for (index = 0; index < i; index++) { 59 clear_bit(qs_cfg->vsi_map[index], qs_cfg->pf_map); 60 qs_cfg->vsi_map[index + qs_cfg->vsi_map_offset] = 0; 61 } 62 mutex_unlock(qs_cfg->qs_mutex); 63 64 return -ENOMEM; 65 } 66 67 /** 68 * ice_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled 69 * @pf: the PF being configured 70 * @pf_q: the PF queue 71 * @ena: enable or disable state of the queue 72 * 73 * This routine will wait for the given Rx queue of the PF to reach the 74 * enabled or disabled state. 75 * Returns -ETIMEDOUT in case of failing to reach the requested state after 76 * multiple retries; else will return 0 in case of success. 77 */ 78 static int ice_pf_rxq_wait(struct ice_pf *pf, int pf_q, bool ena) 79 { 80 int i; 81 82 for (i = 0; i < ICE_Q_WAIT_MAX_RETRY; i++) { 83 if (ena == !!(rd32(&pf->hw, QRX_CTRL(pf_q)) & 84 QRX_CTRL_QENA_STAT_M)) 85 return 0; 86 87 usleep_range(20, 40); 88 } 89 90 return -ETIMEDOUT; 91 } 92 93 /** 94 * ice_vsi_alloc_q_vector - Allocate memory for a single interrupt vector 95 * @vsi: the VSI being configured 96 * @v_idx: index of the vector in the VSI struct 97 * 98 * We allocate one q_vector and set default value for ITR setting associated 99 * with this q_vector. If allocation fails we return -ENOMEM. 100 */ 101 static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, u16 v_idx) 102 { 103 struct ice_pf *pf = vsi->back; 104 struct ice_q_vector *q_vector; 105 106 /* allocate q_vector */ 107 q_vector = devm_kzalloc(ice_pf_to_dev(pf), sizeof(*q_vector), 108 GFP_KERNEL); 109 if (!q_vector) 110 return -ENOMEM; 111 112 q_vector->vsi = vsi; 113 q_vector->v_idx = v_idx; 114 q_vector->tx.itr_setting = ICE_DFLT_TX_ITR; 115 q_vector->rx.itr_setting = ICE_DFLT_RX_ITR; 116 q_vector->tx.itr_mode = ITR_DYNAMIC; 117 q_vector->rx.itr_mode = ITR_DYNAMIC; 118 q_vector->tx.type = ICE_TX_CONTAINER; 119 q_vector->rx.type = ICE_RX_CONTAINER; 120 121 if (vsi->type == ICE_VSI_VF) 122 goto out; 123 /* only set affinity_mask if the CPU is online */ 124 if (cpu_online(v_idx)) 125 cpumask_set_cpu(v_idx, &q_vector->affinity_mask); 126 127 /* This will not be called in the driver load path because the netdev 128 * will not be created yet. All other cases with register the NAPI 129 * handler here (i.e. resume, reset/rebuild, etc.) 130 */ 131 if (vsi->netdev) 132 netif_napi_add(vsi->netdev, &q_vector->napi, ice_napi_poll, 133 NAPI_POLL_WEIGHT); 134 135 out: 136 /* tie q_vector and VSI together */ 137 vsi->q_vectors[v_idx] = q_vector; 138 139 return 0; 140 } 141 142 /** 143 * ice_free_q_vector - Free memory allocated for a specific interrupt vector 144 * @vsi: VSI having the memory freed 145 * @v_idx: index of the vector to be freed 146 */ 147 static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx) 148 { 149 struct ice_q_vector *q_vector; 150 struct ice_pf *pf = vsi->back; 151 struct ice_tx_ring *tx_ring; 152 struct ice_rx_ring *rx_ring; 153 struct device *dev; 154 155 dev = ice_pf_to_dev(pf); 156 if (!vsi->q_vectors[v_idx]) { 157 dev_dbg(dev, "Queue vector at index %d not found\n", v_idx); 158 return; 159 } 160 q_vector = vsi->q_vectors[v_idx]; 161 162 ice_for_each_tx_ring(tx_ring, q_vector->tx) 163 tx_ring->q_vector = NULL; 164 ice_for_each_rx_ring(rx_ring, q_vector->rx) 165 rx_ring->q_vector = NULL; 166 167 /* only VSI with an associated netdev is set up with NAPI */ 168 if (vsi->netdev) 169 netif_napi_del(&q_vector->napi); 170 171 devm_kfree(dev, q_vector); 172 vsi->q_vectors[v_idx] = NULL; 173 } 174 175 /** 176 * ice_cfg_itr_gran - set the ITR granularity to 2 usecs if not already set 177 * @hw: board specific structure 178 */ 179 static void ice_cfg_itr_gran(struct ice_hw *hw) 180 { 181 u32 regval = rd32(hw, GLINT_CTL); 182 183 /* no need to update global register if ITR gran is already set */ 184 if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) && 185 (((regval & GLINT_CTL_ITR_GRAN_200_M) >> 186 GLINT_CTL_ITR_GRAN_200_S) == ICE_ITR_GRAN_US) && 187 (((regval & GLINT_CTL_ITR_GRAN_100_M) >> 188 GLINT_CTL_ITR_GRAN_100_S) == ICE_ITR_GRAN_US) && 189 (((regval & GLINT_CTL_ITR_GRAN_50_M) >> 190 GLINT_CTL_ITR_GRAN_50_S) == ICE_ITR_GRAN_US) && 191 (((regval & GLINT_CTL_ITR_GRAN_25_M) >> 192 GLINT_CTL_ITR_GRAN_25_S) == ICE_ITR_GRAN_US)) 193 return; 194 195 regval = ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_200_S) & 196 GLINT_CTL_ITR_GRAN_200_M) | 197 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_100_S) & 198 GLINT_CTL_ITR_GRAN_100_M) | 199 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_50_S) & 200 GLINT_CTL_ITR_GRAN_50_M) | 201 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_25_S) & 202 GLINT_CTL_ITR_GRAN_25_M); 203 wr32(hw, GLINT_CTL, regval); 204 } 205 206 /** 207 * ice_calc_txq_handle - calculate the queue handle 208 * @vsi: VSI that ring belongs to 209 * @ring: ring to get the absolute queue index 210 * @tc: traffic class number 211 */ 212 static u16 ice_calc_txq_handle(struct ice_vsi *vsi, struct ice_tx_ring *ring, u8 tc) 213 { 214 WARN_ONCE(ice_ring_is_xdp(ring) && tc, "XDP ring can't belong to TC other than 0\n"); 215 216 /* Idea here for calculation is that we subtract the number of queue 217 * count from TC that ring belongs to from it's absolute queue index 218 * and as a result we get the queue's index within TC. 219 */ 220 return ring->q_index - vsi->tc_cfg.tc_info[tc].qoffset; 221 } 222 223 /** 224 * ice_eswitch_calc_txq_handle 225 * @ring: pointer to ring which unique index is needed 226 * 227 * To correctly work with many netdevs ring->q_index of Tx rings on switchdev 228 * VSI can repeat. Hardware ring setup requires unique q_index. Calculate it 229 * here by finding index in vsi->tx_rings of this ring. 230 * 231 * Return ICE_INVAL_Q_INDEX when index wasn't found. Should never happen, 232 * because VSI is get from ring->vsi, so it has to be present in this VSI. 233 */ 234 static u16 ice_eswitch_calc_txq_handle(struct ice_tx_ring *ring) 235 { 236 struct ice_vsi *vsi = ring->vsi; 237 int i; 238 239 ice_for_each_txq(vsi, i) { 240 if (vsi->tx_rings[i] == ring) 241 return i; 242 } 243 244 return ICE_INVAL_Q_INDEX; 245 } 246 247 /** 248 * ice_cfg_xps_tx_ring - Configure XPS for a Tx ring 249 * @ring: The Tx ring to configure 250 * 251 * This enables/disables XPS for a given Tx descriptor ring 252 * based on the TCs enabled for the VSI that ring belongs to. 253 */ 254 static void ice_cfg_xps_tx_ring(struct ice_tx_ring *ring) 255 { 256 if (!ring->q_vector || !ring->netdev) 257 return; 258 259 /* We only initialize XPS once, so as not to overwrite user settings */ 260 if (test_and_set_bit(ICE_TX_XPS_INIT_DONE, ring->xps_state)) 261 return; 262 263 netif_set_xps_queue(ring->netdev, &ring->q_vector->affinity_mask, 264 ring->q_index); 265 } 266 267 /** 268 * ice_setup_tx_ctx - setup a struct ice_tlan_ctx instance 269 * @ring: The Tx ring to configure 270 * @tlan_ctx: Pointer to the Tx LAN queue context structure to be initialized 271 * @pf_q: queue index in the PF space 272 * 273 * Configure the Tx descriptor ring in TLAN context. 274 */ 275 static void 276 ice_setup_tx_ctx(struct ice_tx_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q) 277 { 278 struct ice_vsi *vsi = ring->vsi; 279 struct ice_hw *hw = &vsi->back->hw; 280 281 tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S; 282 283 tlan_ctx->port_num = vsi->port_info->lport; 284 285 /* Transmit Queue Length */ 286 tlan_ctx->qlen = ring->count; 287 288 ice_set_cgd_num(tlan_ctx, ring->dcb_tc); 289 290 /* PF number */ 291 tlan_ctx->pf_num = hw->pf_id; 292 293 /* queue belongs to a specific VSI type 294 * VF / VM index should be programmed per vmvf_type setting: 295 * for vmvf_type = VF, it is VF number between 0-256 296 * for vmvf_type = VM, it is VM number between 0-767 297 * for PF or EMP this field should be set to zero 298 */ 299 switch (vsi->type) { 300 case ICE_VSI_LB: 301 case ICE_VSI_CTRL: 302 case ICE_VSI_PF: 303 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF; 304 break; 305 case ICE_VSI_VF: 306 /* Firmware expects vmvf_num to be absolute VF ID */ 307 tlan_ctx->vmvf_num = hw->func_caps.vf_base_id + vsi->vf_id; 308 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF; 309 break; 310 case ICE_VSI_SWITCHDEV_CTRL: 311 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VMQ; 312 break; 313 default: 314 return; 315 } 316 317 /* make sure the context is associated with the right VSI */ 318 tlan_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx); 319 320 /* Restrict Tx timestamps to the PF VSI */ 321 switch (vsi->type) { 322 case ICE_VSI_PF: 323 tlan_ctx->tsyn_ena = 1; 324 break; 325 default: 326 break; 327 } 328 329 tlan_ctx->tso_ena = ICE_TX_LEGACY; 330 tlan_ctx->tso_qnum = pf_q; 331 332 /* Legacy or Advanced Host Interface: 333 * 0: Advanced Host Interface 334 * 1: Legacy Host Interface 335 */ 336 tlan_ctx->legacy_int = ICE_TX_LEGACY; 337 } 338 339 /** 340 * ice_rx_offset - Return expected offset into page to access data 341 * @rx_ring: Ring we are requesting offset of 342 * 343 * Returns the offset value for ring into the data buffer. 344 */ 345 static unsigned int ice_rx_offset(struct ice_rx_ring *rx_ring) 346 { 347 if (ice_ring_uses_build_skb(rx_ring)) 348 return ICE_SKB_PAD; 349 else if (ice_is_xdp_ena_vsi(rx_ring->vsi)) 350 return XDP_PACKET_HEADROOM; 351 352 return 0; 353 } 354 355 /** 356 * ice_setup_rx_ctx - Configure a receive ring context 357 * @ring: The Rx ring to configure 358 * 359 * Configure the Rx descriptor ring in RLAN context. 360 */ 361 static int ice_setup_rx_ctx(struct ice_rx_ring *ring) 362 { 363 int chain_len = ICE_MAX_CHAINED_RX_BUFS; 364 struct ice_vsi *vsi = ring->vsi; 365 u32 rxdid = ICE_RXDID_FLEX_NIC; 366 struct ice_rlan_ctx rlan_ctx; 367 struct ice_hw *hw; 368 u16 pf_q; 369 int err; 370 371 hw = &vsi->back->hw; 372 373 /* what is Rx queue number in global space of 2K Rx queues */ 374 pf_q = vsi->rxq_map[ring->q_index]; 375 376 /* clear the context structure first */ 377 memset(&rlan_ctx, 0, sizeof(rlan_ctx)); 378 379 /* Receive Queue Base Address. 380 * Indicates the starting address of the descriptor queue defined in 381 * 128 Byte units. 382 */ 383 rlan_ctx.base = ring->dma >> 7; 384 385 rlan_ctx.qlen = ring->count; 386 387 /* Receive Packet Data Buffer Size. 388 * The Packet Data Buffer Size is defined in 128 byte units. 389 */ 390 rlan_ctx.dbuf = ring->rx_buf_len >> ICE_RLAN_CTX_DBUF_S; 391 392 /* use 32 byte descriptors */ 393 rlan_ctx.dsize = 1; 394 395 /* Strip the Ethernet CRC bytes before the packet is posted to host 396 * memory. 397 */ 398 rlan_ctx.crcstrip = 1; 399 400 /* L2TSEL flag defines the reported L2 Tags in the receive descriptor */ 401 rlan_ctx.l2tsel = 1; 402 403 rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT; 404 rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_NO_SPLIT; 405 rlan_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_NO_SPLIT; 406 407 /* This controls whether VLAN is stripped from inner headers 408 * The VLAN in the inner L2 header is stripped to the receive 409 * descriptor if enabled by this flag. 410 */ 411 rlan_ctx.showiv = 0; 412 413 /* For AF_XDP ZC, we disallow packets to span on 414 * multiple buffers, thus letting us skip that 415 * handling in the fast-path. 416 */ 417 if (ring->xsk_pool) 418 chain_len = 1; 419 /* Max packet size for this queue - must not be set to a larger value 420 * than 5 x DBUF 421 */ 422 rlan_ctx.rxmax = min_t(u32, vsi->max_frame, 423 chain_len * ring->rx_buf_len); 424 425 /* Rx queue threshold in units of 64 */ 426 rlan_ctx.lrxqthresh = 1; 427 428 /* Enable Flexible Descriptors in the queue context which 429 * allows this driver to select a specific receive descriptor format 430 * increasing context priority to pick up profile ID; default is 0x01; 431 * setting to 0x03 to ensure profile is programming if prev context is 432 * of same priority 433 */ 434 if (vsi->type != ICE_VSI_VF) 435 ice_write_qrxflxp_cntxt(hw, pf_q, rxdid, 0x3, true); 436 else 437 ice_write_qrxflxp_cntxt(hw, pf_q, ICE_RXDID_LEGACY_1, 0x3, 438 false); 439 440 /* Absolute queue number out of 2K needs to be passed */ 441 err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q); 442 if (err) { 443 dev_err(ice_pf_to_dev(vsi->back), "Failed to set LAN Rx queue context for absolute Rx queue %d error: %d\n", 444 pf_q, err); 445 return -EIO; 446 } 447 448 if (vsi->type == ICE_VSI_VF) 449 return 0; 450 451 /* configure Rx buffer alignment */ 452 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags)) 453 ice_clear_ring_build_skb_ena(ring); 454 else 455 ice_set_ring_build_skb_ena(ring); 456 457 ring->rx_offset = ice_rx_offset(ring); 458 459 /* init queue specific tail register */ 460 ring->tail = hw->hw_addr + QRX_TAIL(pf_q); 461 writel(0, ring->tail); 462 463 return 0; 464 } 465 466 /** 467 * ice_vsi_cfg_rxq - Configure an Rx queue 468 * @ring: the ring being configured 469 * 470 * Return 0 on success and a negative value on error. 471 */ 472 int ice_vsi_cfg_rxq(struct ice_rx_ring *ring) 473 { 474 struct device *dev = ice_pf_to_dev(ring->vsi->back); 475 u16 num_bufs = ICE_DESC_UNUSED(ring); 476 int err; 477 478 ring->rx_buf_len = ring->vsi->rx_buf_len; 479 480 if (ring->vsi->type == ICE_VSI_PF) { 481 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) 482 /* coverity[check_return] */ 483 xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev, 484 ring->q_index, ring->q_vector->napi.napi_id); 485 486 ring->xsk_pool = ice_xsk_pool(ring); 487 if (ring->xsk_pool) { 488 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 489 490 ring->rx_buf_len = 491 xsk_pool_get_rx_frame_size(ring->xsk_pool); 492 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 493 MEM_TYPE_XSK_BUFF_POOL, 494 NULL); 495 if (err) 496 return err; 497 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 498 499 dev_info(dev, "Registered XDP mem model MEM_TYPE_XSK_BUFF_POOL on Rx ring %d\n", 500 ring->q_index); 501 } else { 502 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) 503 /* coverity[check_return] */ 504 xdp_rxq_info_reg(&ring->xdp_rxq, 505 ring->netdev, 506 ring->q_index, ring->q_vector->napi.napi_id); 507 508 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 509 MEM_TYPE_PAGE_SHARED, 510 NULL); 511 if (err) 512 return err; 513 } 514 } 515 516 err = ice_setup_rx_ctx(ring); 517 if (err) { 518 dev_err(dev, "ice_setup_rx_ctx failed for RxQ %d, err %d\n", 519 ring->q_index, err); 520 return err; 521 } 522 523 if (ring->xsk_pool) { 524 bool ok; 525 526 if (!xsk_buff_can_alloc(ring->xsk_pool, num_bufs)) { 527 dev_warn(dev, "XSK buffer pool does not provide enough addresses to fill %d buffers on Rx ring %d\n", 528 num_bufs, ring->q_index); 529 dev_warn(dev, "Change Rx ring/fill queue size to avoid performance issues\n"); 530 531 return 0; 532 } 533 534 ok = ice_alloc_rx_bufs_zc(ring, num_bufs); 535 if (!ok) { 536 u16 pf_q = ring->vsi->rxq_map[ring->q_index]; 537 538 dev_info(dev, "Failed to allocate some buffers on XSK buffer pool enabled Rx ring %d (pf_q %d)\n", 539 ring->q_index, pf_q); 540 } 541 542 return 0; 543 } 544 545 ice_alloc_rx_bufs(ring, num_bufs); 546 547 return 0; 548 } 549 550 /** 551 * __ice_vsi_get_qs - helper function for assigning queues from PF to VSI 552 * @qs_cfg: gathered variables needed for pf->vsi queues assignment 553 * 554 * This function first tries to find contiguous space. If it is not successful, 555 * it tries with the scatter approach. 556 * 557 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 558 */ 559 int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg) 560 { 561 int ret = 0; 562 563 ret = __ice_vsi_get_qs_contig(qs_cfg); 564 if (ret) { 565 /* contig failed, so try with scatter approach */ 566 qs_cfg->mapping_mode = ICE_VSI_MAP_SCATTER; 567 qs_cfg->q_count = min_t(unsigned int, qs_cfg->q_count, 568 qs_cfg->scatter_count); 569 ret = __ice_vsi_get_qs_sc(qs_cfg); 570 } 571 return ret; 572 } 573 574 /** 575 * ice_vsi_ctrl_one_rx_ring - start/stop VSI's Rx ring with no busy wait 576 * @vsi: the VSI being configured 577 * @ena: start or stop the Rx ring 578 * @rxq_idx: 0-based Rx queue index for the VSI passed in 579 * @wait: wait or don't wait for configuration to finish in hardware 580 * 581 * Return 0 on success and negative on error. 582 */ 583 int 584 ice_vsi_ctrl_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx, bool wait) 585 { 586 int pf_q = vsi->rxq_map[rxq_idx]; 587 struct ice_pf *pf = vsi->back; 588 struct ice_hw *hw = &pf->hw; 589 u32 rx_reg; 590 591 rx_reg = rd32(hw, QRX_CTRL(pf_q)); 592 593 /* Skip if the queue is already in the requested state */ 594 if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M)) 595 return 0; 596 597 /* turn on/off the queue */ 598 if (ena) 599 rx_reg |= QRX_CTRL_QENA_REQ_M; 600 else 601 rx_reg &= ~QRX_CTRL_QENA_REQ_M; 602 wr32(hw, QRX_CTRL(pf_q), rx_reg); 603 604 if (!wait) 605 return 0; 606 607 ice_flush(hw); 608 return ice_pf_rxq_wait(pf, pf_q, ena); 609 } 610 611 /** 612 * ice_vsi_wait_one_rx_ring - wait for a VSI's Rx ring to be stopped/started 613 * @vsi: the VSI being configured 614 * @ena: true/false to verify Rx ring has been enabled/disabled respectively 615 * @rxq_idx: 0-based Rx queue index for the VSI passed in 616 * 617 * This routine will wait for the given Rx queue of the VSI to reach the 618 * enabled or disabled state. Returns -ETIMEDOUT in case of failing to reach 619 * the requested state after multiple retries; else will return 0 in case of 620 * success. 621 */ 622 int ice_vsi_wait_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx) 623 { 624 int pf_q = vsi->rxq_map[rxq_idx]; 625 struct ice_pf *pf = vsi->back; 626 627 return ice_pf_rxq_wait(pf, pf_q, ena); 628 } 629 630 /** 631 * ice_vsi_alloc_q_vectors - Allocate memory for interrupt vectors 632 * @vsi: the VSI being configured 633 * 634 * We allocate one q_vector per queue interrupt. If allocation fails we 635 * return -ENOMEM. 636 */ 637 int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi) 638 { 639 struct device *dev = ice_pf_to_dev(vsi->back); 640 u16 v_idx; 641 int err; 642 643 if (vsi->q_vectors[0]) { 644 dev_dbg(dev, "VSI %d has existing q_vectors\n", vsi->vsi_num); 645 return -EEXIST; 646 } 647 648 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) { 649 err = ice_vsi_alloc_q_vector(vsi, v_idx); 650 if (err) 651 goto err_out; 652 } 653 654 return 0; 655 656 err_out: 657 while (v_idx--) 658 ice_free_q_vector(vsi, v_idx); 659 660 dev_err(dev, "Failed to allocate %d q_vector for VSI %d, ret=%d\n", 661 vsi->num_q_vectors, vsi->vsi_num, err); 662 vsi->num_q_vectors = 0; 663 return err; 664 } 665 666 /** 667 * ice_vsi_map_rings_to_vectors - Map VSI rings to interrupt vectors 668 * @vsi: the VSI being configured 669 * 670 * This function maps descriptor rings to the queue-specific vectors allotted 671 * through the MSI-X enabling code. On a constrained vector budget, we map Tx 672 * and Rx rings to the vector as "efficiently" as possible. 673 */ 674 void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi) 675 { 676 int q_vectors = vsi->num_q_vectors; 677 u16 tx_rings_rem, rx_rings_rem; 678 int v_id; 679 680 /* initially assigning remaining rings count to VSIs num queue value */ 681 tx_rings_rem = vsi->num_txq; 682 rx_rings_rem = vsi->num_rxq; 683 684 for (v_id = 0; v_id < q_vectors; v_id++) { 685 struct ice_q_vector *q_vector = vsi->q_vectors[v_id]; 686 u8 tx_rings_per_v, rx_rings_per_v; 687 u16 q_id, q_base; 688 689 /* Tx rings mapping to vector */ 690 tx_rings_per_v = (u8)DIV_ROUND_UP(tx_rings_rem, 691 q_vectors - v_id); 692 q_vector->num_ring_tx = tx_rings_per_v; 693 q_vector->tx.tx_ring = NULL; 694 q_vector->tx.itr_idx = ICE_TX_ITR; 695 q_base = vsi->num_txq - tx_rings_rem; 696 697 for (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) { 698 struct ice_tx_ring *tx_ring = vsi->tx_rings[q_id]; 699 700 tx_ring->q_vector = q_vector; 701 tx_ring->next = q_vector->tx.tx_ring; 702 q_vector->tx.tx_ring = tx_ring; 703 } 704 tx_rings_rem -= tx_rings_per_v; 705 706 /* Rx rings mapping to vector */ 707 rx_rings_per_v = (u8)DIV_ROUND_UP(rx_rings_rem, 708 q_vectors - v_id); 709 q_vector->num_ring_rx = rx_rings_per_v; 710 q_vector->rx.rx_ring = NULL; 711 q_vector->rx.itr_idx = ICE_RX_ITR; 712 q_base = vsi->num_rxq - rx_rings_rem; 713 714 for (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) { 715 struct ice_rx_ring *rx_ring = vsi->rx_rings[q_id]; 716 717 rx_ring->q_vector = q_vector; 718 rx_ring->next = q_vector->rx.rx_ring; 719 q_vector->rx.rx_ring = rx_ring; 720 } 721 rx_rings_rem -= rx_rings_per_v; 722 } 723 } 724 725 /** 726 * ice_vsi_free_q_vectors - Free memory allocated for interrupt vectors 727 * @vsi: the VSI having memory freed 728 */ 729 void ice_vsi_free_q_vectors(struct ice_vsi *vsi) 730 { 731 int v_idx; 732 733 ice_for_each_q_vector(vsi, v_idx) 734 ice_free_q_vector(vsi, v_idx); 735 } 736 737 /** 738 * ice_vsi_cfg_txq - Configure single Tx queue 739 * @vsi: the VSI that queue belongs to 740 * @ring: Tx ring to be configured 741 * @qg_buf: queue group buffer 742 */ 743 int 744 ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_tx_ring *ring, 745 struct ice_aqc_add_tx_qgrp *qg_buf) 746 { 747 u8 buf_len = struct_size(qg_buf, txqs, 1); 748 struct ice_tlan_ctx tlan_ctx = { 0 }; 749 struct ice_aqc_add_txqs_perq *txq; 750 struct ice_pf *pf = vsi->back; 751 struct ice_hw *hw = &pf->hw; 752 enum ice_status status; 753 u16 pf_q; 754 u8 tc; 755 756 /* Configure XPS */ 757 ice_cfg_xps_tx_ring(ring); 758 759 pf_q = ring->reg_idx; 760 ice_setup_tx_ctx(ring, &tlan_ctx, pf_q); 761 /* copy context contents into the qg_buf */ 762 qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q); 763 ice_set_ctx(hw, (u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx, 764 ice_tlan_ctx_info); 765 766 /* init queue specific tail reg. It is referred as 767 * transmit comm scheduler queue doorbell. 768 */ 769 ring->tail = hw->hw_addr + QTX_COMM_DBELL(pf_q); 770 771 if (IS_ENABLED(CONFIG_DCB)) 772 tc = ring->dcb_tc; 773 else 774 tc = 0; 775 776 /* Add unique software queue handle of the Tx queue per 777 * TC into the VSI Tx ring 778 */ 779 if (vsi->type == ICE_VSI_SWITCHDEV_CTRL) { 780 ring->q_handle = ice_eswitch_calc_txq_handle(ring); 781 782 if (ring->q_handle == ICE_INVAL_Q_INDEX) 783 return -ENODEV; 784 } else { 785 ring->q_handle = ice_calc_txq_handle(vsi, ring, tc); 786 } 787 788 status = ice_ena_vsi_txq(vsi->port_info, vsi->idx, tc, ring->q_handle, 789 1, qg_buf, buf_len, NULL); 790 if (status) { 791 dev_err(ice_pf_to_dev(pf), "Failed to set LAN Tx queue context, error: %s\n", 792 ice_stat_str(status)); 793 return -ENODEV; 794 } 795 796 /* Add Tx Queue TEID into the VSI Tx ring from the 797 * response. This will complete configuring and 798 * enabling the queue. 799 */ 800 txq = &qg_buf->txqs[0]; 801 if (pf_q == le16_to_cpu(txq->txq_id)) 802 ring->txq_teid = le32_to_cpu(txq->q_teid); 803 804 return 0; 805 } 806 807 /** 808 * ice_cfg_itr - configure the initial interrupt throttle values 809 * @hw: pointer to the HW structure 810 * @q_vector: interrupt vector that's being configured 811 * 812 * Configure interrupt throttling values for the ring containers that are 813 * associated with the interrupt vector passed in. 814 */ 815 void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector) 816 { 817 ice_cfg_itr_gran(hw); 818 819 if (q_vector->num_ring_rx) 820 ice_write_itr(&q_vector->rx, q_vector->rx.itr_setting); 821 822 if (q_vector->num_ring_tx) 823 ice_write_itr(&q_vector->tx, q_vector->tx.itr_setting); 824 825 ice_write_intrl(q_vector, q_vector->intrl); 826 } 827 828 /** 829 * ice_cfg_txq_interrupt - configure interrupt on Tx queue 830 * @vsi: the VSI being configured 831 * @txq: Tx queue being mapped to MSI-X vector 832 * @msix_idx: MSI-X vector index within the function 833 * @itr_idx: ITR index of the interrupt cause 834 * 835 * Configure interrupt on Tx queue by associating Tx queue to MSI-X vector 836 * within the function space. 837 */ 838 void 839 ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx) 840 { 841 struct ice_pf *pf = vsi->back; 842 struct ice_hw *hw = &pf->hw; 843 u32 val; 844 845 itr_idx = (itr_idx << QINT_TQCTL_ITR_INDX_S) & QINT_TQCTL_ITR_INDX_M; 846 847 val = QINT_TQCTL_CAUSE_ENA_M | itr_idx | 848 ((msix_idx << QINT_TQCTL_MSIX_INDX_S) & QINT_TQCTL_MSIX_INDX_M); 849 850 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val); 851 if (ice_is_xdp_ena_vsi(vsi)) { 852 u32 xdp_txq = txq + vsi->num_xdp_txq; 853 854 wr32(hw, QINT_TQCTL(vsi->txq_map[xdp_txq]), 855 val); 856 } 857 ice_flush(hw); 858 } 859 860 /** 861 * ice_cfg_rxq_interrupt - configure interrupt on Rx queue 862 * @vsi: the VSI being configured 863 * @rxq: Rx queue being mapped to MSI-X vector 864 * @msix_idx: MSI-X vector index within the function 865 * @itr_idx: ITR index of the interrupt cause 866 * 867 * Configure interrupt on Rx queue by associating Rx queue to MSI-X vector 868 * within the function space. 869 */ 870 void 871 ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx) 872 { 873 struct ice_pf *pf = vsi->back; 874 struct ice_hw *hw = &pf->hw; 875 u32 val; 876 877 itr_idx = (itr_idx << QINT_RQCTL_ITR_INDX_S) & QINT_RQCTL_ITR_INDX_M; 878 879 val = QINT_RQCTL_CAUSE_ENA_M | itr_idx | 880 ((msix_idx << QINT_RQCTL_MSIX_INDX_S) & QINT_RQCTL_MSIX_INDX_M); 881 882 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val); 883 884 ice_flush(hw); 885 } 886 887 /** 888 * ice_trigger_sw_intr - trigger a software interrupt 889 * @hw: pointer to the HW structure 890 * @q_vector: interrupt vector to trigger the software interrupt for 891 */ 892 void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector) 893 { 894 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx), 895 (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) | 896 GLINT_DYN_CTL_SWINT_TRIG_M | 897 GLINT_DYN_CTL_INTENA_M); 898 } 899 900 /** 901 * ice_vsi_stop_tx_ring - Disable single Tx ring 902 * @vsi: the VSI being configured 903 * @rst_src: reset source 904 * @rel_vmvf_num: Relative ID of VF/VM 905 * @ring: Tx ring to be stopped 906 * @txq_meta: Meta data of Tx ring to be stopped 907 */ 908 int 909 ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src, 910 u16 rel_vmvf_num, struct ice_tx_ring *ring, 911 struct ice_txq_meta *txq_meta) 912 { 913 struct ice_pf *pf = vsi->back; 914 struct ice_q_vector *q_vector; 915 struct ice_hw *hw = &pf->hw; 916 enum ice_status status; 917 u32 val; 918 919 /* clear cause_ena bit for disabled queues */ 920 val = rd32(hw, QINT_TQCTL(ring->reg_idx)); 921 val &= ~QINT_TQCTL_CAUSE_ENA_M; 922 wr32(hw, QINT_TQCTL(ring->reg_idx), val); 923 924 /* software is expected to wait for 100 ns */ 925 ndelay(100); 926 927 /* trigger a software interrupt for the vector 928 * associated to the queue to schedule NAPI handler 929 */ 930 q_vector = ring->q_vector; 931 if (q_vector) 932 ice_trigger_sw_intr(hw, q_vector); 933 934 status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx, 935 txq_meta->tc, 1, &txq_meta->q_handle, 936 &txq_meta->q_id, &txq_meta->q_teid, rst_src, 937 rel_vmvf_num, NULL); 938 939 /* if the disable queue command was exercised during an 940 * active reset flow, ICE_ERR_RESET_ONGOING is returned. 941 * This is not an error as the reset operation disables 942 * queues at the hardware level anyway. 943 */ 944 if (status == ICE_ERR_RESET_ONGOING) { 945 dev_dbg(ice_pf_to_dev(vsi->back), "Reset in progress. LAN Tx queues already disabled\n"); 946 } else if (status == ICE_ERR_DOES_NOT_EXIST) { 947 dev_dbg(ice_pf_to_dev(vsi->back), "LAN Tx queues do not exist, nothing to disable\n"); 948 } else if (status) { 949 dev_err(ice_pf_to_dev(vsi->back), "Failed to disable LAN Tx queues, error: %s\n", 950 ice_stat_str(status)); 951 return -ENODEV; 952 } 953 954 return 0; 955 } 956 957 /** 958 * ice_fill_txq_meta - Prepare the Tx queue's meta data 959 * @vsi: VSI that ring belongs to 960 * @ring: ring that txq_meta will be based on 961 * @txq_meta: a helper struct that wraps Tx queue's information 962 * 963 * Set up a helper struct that will contain all the necessary fields that 964 * are needed for stopping Tx queue 965 */ 966 void 967 ice_fill_txq_meta(struct ice_vsi *vsi, struct ice_tx_ring *ring, 968 struct ice_txq_meta *txq_meta) 969 { 970 u8 tc; 971 972 if (IS_ENABLED(CONFIG_DCB)) 973 tc = ring->dcb_tc; 974 else 975 tc = 0; 976 977 txq_meta->q_id = ring->reg_idx; 978 txq_meta->q_teid = ring->txq_teid; 979 txq_meta->q_handle = ring->q_handle; 980 txq_meta->vsi_idx = vsi->idx; 981 txq_meta->tc = tc; 982 } 983