1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019, Intel Corporation. */ 3 4 #include <net/xdp_sock_drv.h> 5 #include "ice_base.h" 6 #include "ice_lib.h" 7 #include "ice_dcb_lib.h" 8 9 /** 10 * __ice_vsi_get_qs_contig - Assign a contiguous chunk of queues to VSI 11 * @qs_cfg: gathered variables needed for PF->VSI queues assignment 12 * 13 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 14 */ 15 static int __ice_vsi_get_qs_contig(struct ice_qs_cfg *qs_cfg) 16 { 17 unsigned int offset, i; 18 19 mutex_lock(qs_cfg->qs_mutex); 20 offset = bitmap_find_next_zero_area(qs_cfg->pf_map, qs_cfg->pf_map_size, 21 0, qs_cfg->q_count, 0); 22 if (offset >= qs_cfg->pf_map_size) { 23 mutex_unlock(qs_cfg->qs_mutex); 24 return -ENOMEM; 25 } 26 27 bitmap_set(qs_cfg->pf_map, offset, qs_cfg->q_count); 28 for (i = 0; i < qs_cfg->q_count; i++) 29 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)(i + offset); 30 mutex_unlock(qs_cfg->qs_mutex); 31 32 return 0; 33 } 34 35 /** 36 * __ice_vsi_get_qs_sc - Assign a scattered queues from PF to VSI 37 * @qs_cfg: gathered variables needed for pf->vsi queues assignment 38 * 39 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 40 */ 41 static int __ice_vsi_get_qs_sc(struct ice_qs_cfg *qs_cfg) 42 { 43 unsigned int i, index = 0; 44 45 mutex_lock(qs_cfg->qs_mutex); 46 for (i = 0; i < qs_cfg->q_count; i++) { 47 index = find_next_zero_bit(qs_cfg->pf_map, 48 qs_cfg->pf_map_size, index); 49 if (index >= qs_cfg->pf_map_size) 50 goto err_scatter; 51 set_bit(index, qs_cfg->pf_map); 52 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = (u16)index; 53 } 54 mutex_unlock(qs_cfg->qs_mutex); 55 56 return 0; 57 err_scatter: 58 for (index = 0; index < i; index++) { 59 clear_bit(qs_cfg->vsi_map[index], qs_cfg->pf_map); 60 qs_cfg->vsi_map[index + qs_cfg->vsi_map_offset] = 0; 61 } 62 mutex_unlock(qs_cfg->qs_mutex); 63 64 return -ENOMEM; 65 } 66 67 /** 68 * ice_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled 69 * @pf: the PF being configured 70 * @pf_q: the PF queue 71 * @ena: enable or disable state of the queue 72 * 73 * This routine will wait for the given Rx queue of the PF to reach the 74 * enabled or disabled state. 75 * Returns -ETIMEDOUT in case of failing to reach the requested state after 76 * multiple retries; else will return 0 in case of success. 77 */ 78 static int ice_pf_rxq_wait(struct ice_pf *pf, int pf_q, bool ena) 79 { 80 int i; 81 82 for (i = 0; i < ICE_Q_WAIT_MAX_RETRY; i++) { 83 if (ena == !!(rd32(&pf->hw, QRX_CTRL(pf_q)) & 84 QRX_CTRL_QENA_STAT_M)) 85 return 0; 86 87 usleep_range(20, 40); 88 } 89 90 return -ETIMEDOUT; 91 } 92 93 /** 94 * ice_vsi_alloc_q_vector - Allocate memory for a single interrupt vector 95 * @vsi: the VSI being configured 96 * @v_idx: index of the vector in the VSI struct 97 * 98 * We allocate one q_vector and set default value for ITR setting associated 99 * with this q_vector. If allocation fails we return -ENOMEM. 100 */ 101 static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, u16 v_idx) 102 { 103 struct ice_pf *pf = vsi->back; 104 struct ice_q_vector *q_vector; 105 106 /* allocate q_vector */ 107 q_vector = devm_kzalloc(ice_pf_to_dev(pf), sizeof(*q_vector), 108 GFP_KERNEL); 109 if (!q_vector) 110 return -ENOMEM; 111 112 q_vector->vsi = vsi; 113 q_vector->v_idx = v_idx; 114 q_vector->tx.itr_setting = ICE_DFLT_TX_ITR; 115 q_vector->rx.itr_setting = ICE_DFLT_RX_ITR; 116 if (vsi->type == ICE_VSI_VF) 117 goto out; 118 /* only set affinity_mask if the CPU is online */ 119 if (cpu_online(v_idx)) 120 cpumask_set_cpu(v_idx, &q_vector->affinity_mask); 121 122 /* This will not be called in the driver load path because the netdev 123 * will not be created yet. All other cases with register the NAPI 124 * handler here (i.e. resume, reset/rebuild, etc.) 125 */ 126 if (vsi->netdev) 127 netif_napi_add(vsi->netdev, &q_vector->napi, ice_napi_poll, 128 NAPI_POLL_WEIGHT); 129 130 out: 131 /* tie q_vector and VSI together */ 132 vsi->q_vectors[v_idx] = q_vector; 133 134 return 0; 135 } 136 137 /** 138 * ice_free_q_vector - Free memory allocated for a specific interrupt vector 139 * @vsi: VSI having the memory freed 140 * @v_idx: index of the vector to be freed 141 */ 142 static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx) 143 { 144 struct ice_q_vector *q_vector; 145 struct ice_pf *pf = vsi->back; 146 struct ice_ring *ring; 147 struct device *dev; 148 149 dev = ice_pf_to_dev(pf); 150 if (!vsi->q_vectors[v_idx]) { 151 dev_dbg(dev, "Queue vector at index %d not found\n", v_idx); 152 return; 153 } 154 q_vector = vsi->q_vectors[v_idx]; 155 156 ice_for_each_ring(ring, q_vector->tx) 157 ring->q_vector = NULL; 158 ice_for_each_ring(ring, q_vector->rx) 159 ring->q_vector = NULL; 160 161 /* only VSI with an associated netdev is set up with NAPI */ 162 if (vsi->netdev) 163 netif_napi_del(&q_vector->napi); 164 165 devm_kfree(dev, q_vector); 166 vsi->q_vectors[v_idx] = NULL; 167 } 168 169 /** 170 * ice_cfg_itr_gran - set the ITR granularity to 2 usecs if not already set 171 * @hw: board specific structure 172 */ 173 static void ice_cfg_itr_gran(struct ice_hw *hw) 174 { 175 u32 regval = rd32(hw, GLINT_CTL); 176 177 /* no need to update global register if ITR gran is already set */ 178 if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) && 179 (((regval & GLINT_CTL_ITR_GRAN_200_M) >> 180 GLINT_CTL_ITR_GRAN_200_S) == ICE_ITR_GRAN_US) && 181 (((regval & GLINT_CTL_ITR_GRAN_100_M) >> 182 GLINT_CTL_ITR_GRAN_100_S) == ICE_ITR_GRAN_US) && 183 (((regval & GLINT_CTL_ITR_GRAN_50_M) >> 184 GLINT_CTL_ITR_GRAN_50_S) == ICE_ITR_GRAN_US) && 185 (((regval & GLINT_CTL_ITR_GRAN_25_M) >> 186 GLINT_CTL_ITR_GRAN_25_S) == ICE_ITR_GRAN_US)) 187 return; 188 189 regval = ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_200_S) & 190 GLINT_CTL_ITR_GRAN_200_M) | 191 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_100_S) & 192 GLINT_CTL_ITR_GRAN_100_M) | 193 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_50_S) & 194 GLINT_CTL_ITR_GRAN_50_M) | 195 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_25_S) & 196 GLINT_CTL_ITR_GRAN_25_M); 197 wr32(hw, GLINT_CTL, regval); 198 } 199 200 /** 201 * ice_calc_q_handle - calculate the queue handle 202 * @vsi: VSI that ring belongs to 203 * @ring: ring to get the absolute queue index 204 * @tc: traffic class number 205 */ 206 static u16 ice_calc_q_handle(struct ice_vsi *vsi, struct ice_ring *ring, u8 tc) 207 { 208 WARN_ONCE(ice_ring_is_xdp(ring) && tc, "XDP ring can't belong to TC other than 0\n"); 209 210 /* Idea here for calculation is that we subtract the number of queue 211 * count from TC that ring belongs to from it's absolute queue index 212 * and as a result we get the queue's index within TC. 213 */ 214 return ring->q_index - vsi->tc_cfg.tc_info[tc].qoffset; 215 } 216 217 /** 218 * ice_setup_tx_ctx - setup a struct ice_tlan_ctx instance 219 * @ring: The Tx ring to configure 220 * @tlan_ctx: Pointer to the Tx LAN queue context structure to be initialized 221 * @pf_q: queue index in the PF space 222 * 223 * Configure the Tx descriptor ring in TLAN context. 224 */ 225 static void 226 ice_setup_tx_ctx(struct ice_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q) 227 { 228 struct ice_vsi *vsi = ring->vsi; 229 struct ice_hw *hw = &vsi->back->hw; 230 231 tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S; 232 233 tlan_ctx->port_num = vsi->port_info->lport; 234 235 /* Transmit Queue Length */ 236 tlan_ctx->qlen = ring->count; 237 238 ice_set_cgd_num(tlan_ctx, ring); 239 240 /* PF number */ 241 tlan_ctx->pf_num = hw->pf_id; 242 243 /* queue belongs to a specific VSI type 244 * VF / VM index should be programmed per vmvf_type setting: 245 * for vmvf_type = VF, it is VF number between 0-256 246 * for vmvf_type = VM, it is VM number between 0-767 247 * for PF or EMP this field should be set to zero 248 */ 249 switch (vsi->type) { 250 case ICE_VSI_LB: 251 case ICE_VSI_CTRL: 252 case ICE_VSI_PF: 253 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF; 254 break; 255 case ICE_VSI_VF: 256 /* Firmware expects vmvf_num to be absolute VF ID */ 257 tlan_ctx->vmvf_num = hw->func_caps.vf_base_id + vsi->vf_id; 258 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF; 259 break; 260 default: 261 return; 262 } 263 264 /* make sure the context is associated with the right VSI */ 265 tlan_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx); 266 267 tlan_ctx->tso_ena = ICE_TX_LEGACY; 268 tlan_ctx->tso_qnum = pf_q; 269 270 /* Legacy or Advanced Host Interface: 271 * 0: Advanced Host Interface 272 * 1: Legacy Host Interface 273 */ 274 tlan_ctx->legacy_int = ICE_TX_LEGACY; 275 } 276 277 /** 278 * ice_rx_offset - Return expected offset into page to access data 279 * @rx_ring: Ring we are requesting offset of 280 * 281 * Returns the offset value for ring into the data buffer. 282 */ 283 static unsigned int ice_rx_offset(struct ice_ring *rx_ring) 284 { 285 if (ice_ring_uses_build_skb(rx_ring)) 286 return ICE_SKB_PAD; 287 else if (ice_is_xdp_ena_vsi(rx_ring->vsi)) 288 return XDP_PACKET_HEADROOM; 289 290 return 0; 291 } 292 293 /** 294 * ice_setup_rx_ctx - Configure a receive ring context 295 * @ring: The Rx ring to configure 296 * 297 * Configure the Rx descriptor ring in RLAN context. 298 */ 299 int ice_setup_rx_ctx(struct ice_ring *ring) 300 { 301 struct device *dev = ice_pf_to_dev(ring->vsi->back); 302 int chain_len = ICE_MAX_CHAINED_RX_BUFS; 303 u16 num_bufs = ICE_DESC_UNUSED(ring); 304 struct ice_vsi *vsi = ring->vsi; 305 u32 rxdid = ICE_RXDID_FLEX_NIC; 306 struct ice_rlan_ctx rlan_ctx; 307 struct ice_hw *hw; 308 u16 pf_q; 309 int err; 310 311 hw = &vsi->back->hw; 312 313 /* what is Rx queue number in global space of 2K Rx queues */ 314 pf_q = vsi->rxq_map[ring->q_index]; 315 316 /* clear the context structure first */ 317 memset(&rlan_ctx, 0, sizeof(rlan_ctx)); 318 319 ring->rx_buf_len = vsi->rx_buf_len; 320 321 if (ring->vsi->type == ICE_VSI_PF) { 322 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) 323 /* coverity[check_return] */ 324 xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev, 325 ring->q_index, ring->q_vector->napi.napi_id); 326 327 ring->xsk_pool = ice_xsk_pool(ring); 328 if (ring->xsk_pool) { 329 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 330 331 ring->rx_buf_len = 332 xsk_pool_get_rx_frame_size(ring->xsk_pool); 333 /* For AF_XDP ZC, we disallow packets to span on 334 * multiple buffers, thus letting us skip that 335 * handling in the fast-path. 336 */ 337 chain_len = 1; 338 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 339 MEM_TYPE_XSK_BUFF_POOL, 340 NULL); 341 if (err) 342 return err; 343 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 344 345 dev_info(dev, "Registered XDP mem model MEM_TYPE_XSK_BUFF_POOL on Rx ring %d\n", 346 ring->q_index); 347 } else { 348 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq)) 349 /* coverity[check_return] */ 350 xdp_rxq_info_reg(&ring->xdp_rxq, 351 ring->netdev, 352 ring->q_index, ring->q_vector->napi.napi_id); 353 354 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 355 MEM_TYPE_PAGE_SHARED, 356 NULL); 357 if (err) 358 return err; 359 } 360 } 361 /* Receive Queue Base Address. 362 * Indicates the starting address of the descriptor queue defined in 363 * 128 Byte units. 364 */ 365 rlan_ctx.base = ring->dma >> 7; 366 367 rlan_ctx.qlen = ring->count; 368 369 /* Receive Packet Data Buffer Size. 370 * The Packet Data Buffer Size is defined in 128 byte units. 371 */ 372 rlan_ctx.dbuf = ring->rx_buf_len >> ICE_RLAN_CTX_DBUF_S; 373 374 /* use 32 byte descriptors */ 375 rlan_ctx.dsize = 1; 376 377 /* Strip the Ethernet CRC bytes before the packet is posted to host 378 * memory. 379 */ 380 rlan_ctx.crcstrip = 1; 381 382 /* L2TSEL flag defines the reported L2 Tags in the receive descriptor */ 383 rlan_ctx.l2tsel = 1; 384 385 rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT; 386 rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_NO_SPLIT; 387 rlan_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_NO_SPLIT; 388 389 /* This controls whether VLAN is stripped from inner headers 390 * The VLAN in the inner L2 header is stripped to the receive 391 * descriptor if enabled by this flag. 392 */ 393 rlan_ctx.showiv = 0; 394 395 /* Max packet size for this queue - must not be set to a larger value 396 * than 5 x DBUF 397 */ 398 rlan_ctx.rxmax = min_t(u32, vsi->max_frame, 399 chain_len * ring->rx_buf_len); 400 401 /* Rx queue threshold in units of 64 */ 402 rlan_ctx.lrxqthresh = 1; 403 404 /* Enable Flexible Descriptors in the queue context which 405 * allows this driver to select a specific receive descriptor format 406 * increasing context priority to pick up profile ID; default is 0x01; 407 * setting to 0x03 to ensure profile is programming if prev context is 408 * of same priority 409 */ 410 if (vsi->type != ICE_VSI_VF) 411 ice_write_qrxflxp_cntxt(hw, pf_q, rxdid, 0x3); 412 else 413 ice_write_qrxflxp_cntxt(hw, pf_q, ICE_RXDID_LEGACY_1, 0x3); 414 415 /* Absolute queue number out of 2K needs to be passed */ 416 err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q); 417 if (err) { 418 dev_err(dev, "Failed to set LAN Rx queue context for absolute Rx queue %d error: %d\n", 419 pf_q, err); 420 return -EIO; 421 } 422 423 if (vsi->type == ICE_VSI_VF) 424 return 0; 425 426 /* configure Rx buffer alignment */ 427 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags)) 428 ice_clear_ring_build_skb_ena(ring); 429 else 430 ice_set_ring_build_skb_ena(ring); 431 432 ring->rx_offset = ice_rx_offset(ring); 433 434 /* init queue specific tail register */ 435 ring->tail = hw->hw_addr + QRX_TAIL(pf_q); 436 writel(0, ring->tail); 437 438 if (ring->xsk_pool) { 439 bool ok; 440 441 if (!xsk_buff_can_alloc(ring->xsk_pool, num_bufs)) { 442 dev_warn(dev, "XSK buffer pool does not provide enough addresses to fill %d buffers on Rx ring %d\n", 443 num_bufs, ring->q_index); 444 dev_warn(dev, "Change Rx ring/fill queue size to avoid performance issues\n"); 445 446 return 0; 447 } 448 449 ok = ice_alloc_rx_bufs_zc(ring, num_bufs); 450 if (!ok) 451 dev_info(dev, "Failed to allocate some buffers on XSK buffer pool enabled Rx ring %d (pf_q %d)\n", 452 ring->q_index, pf_q); 453 return 0; 454 } 455 456 ice_alloc_rx_bufs(ring, num_bufs); 457 458 return 0; 459 } 460 461 /** 462 * __ice_vsi_get_qs - helper function for assigning queues from PF to VSI 463 * @qs_cfg: gathered variables needed for pf->vsi queues assignment 464 * 465 * This function first tries to find contiguous space. If it is not successful, 466 * it tries with the scatter approach. 467 * 468 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap 469 */ 470 int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg) 471 { 472 int ret = 0; 473 474 ret = __ice_vsi_get_qs_contig(qs_cfg); 475 if (ret) { 476 /* contig failed, so try with scatter approach */ 477 qs_cfg->mapping_mode = ICE_VSI_MAP_SCATTER; 478 qs_cfg->q_count = min_t(unsigned int, qs_cfg->q_count, 479 qs_cfg->scatter_count); 480 ret = __ice_vsi_get_qs_sc(qs_cfg); 481 } 482 return ret; 483 } 484 485 /** 486 * ice_vsi_ctrl_one_rx_ring - start/stop VSI's Rx ring with no busy wait 487 * @vsi: the VSI being configured 488 * @ena: start or stop the Rx ring 489 * @rxq_idx: 0-based Rx queue index for the VSI passed in 490 * @wait: wait or don't wait for configuration to finish in hardware 491 * 492 * Return 0 on success and negative on error. 493 */ 494 int 495 ice_vsi_ctrl_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx, bool wait) 496 { 497 int pf_q = vsi->rxq_map[rxq_idx]; 498 struct ice_pf *pf = vsi->back; 499 struct ice_hw *hw = &pf->hw; 500 u32 rx_reg; 501 502 rx_reg = rd32(hw, QRX_CTRL(pf_q)); 503 504 /* Skip if the queue is already in the requested state */ 505 if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M)) 506 return 0; 507 508 /* turn on/off the queue */ 509 if (ena) 510 rx_reg |= QRX_CTRL_QENA_REQ_M; 511 else 512 rx_reg &= ~QRX_CTRL_QENA_REQ_M; 513 wr32(hw, QRX_CTRL(pf_q), rx_reg); 514 515 if (!wait) 516 return 0; 517 518 ice_flush(hw); 519 return ice_pf_rxq_wait(pf, pf_q, ena); 520 } 521 522 /** 523 * ice_vsi_wait_one_rx_ring - wait for a VSI's Rx ring to be stopped/started 524 * @vsi: the VSI being configured 525 * @ena: true/false to verify Rx ring has been enabled/disabled respectively 526 * @rxq_idx: 0-based Rx queue index for the VSI passed in 527 * 528 * This routine will wait for the given Rx queue of the VSI to reach the 529 * enabled or disabled state. Returns -ETIMEDOUT in case of failing to reach 530 * the requested state after multiple retries; else will return 0 in case of 531 * success. 532 */ 533 int ice_vsi_wait_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx) 534 { 535 int pf_q = vsi->rxq_map[rxq_idx]; 536 struct ice_pf *pf = vsi->back; 537 538 return ice_pf_rxq_wait(pf, pf_q, ena); 539 } 540 541 /** 542 * ice_vsi_alloc_q_vectors - Allocate memory for interrupt vectors 543 * @vsi: the VSI being configured 544 * 545 * We allocate one q_vector per queue interrupt. If allocation fails we 546 * return -ENOMEM. 547 */ 548 int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi) 549 { 550 struct device *dev = ice_pf_to_dev(vsi->back); 551 u16 v_idx; 552 int err; 553 554 if (vsi->q_vectors[0]) { 555 dev_dbg(dev, "VSI %d has existing q_vectors\n", vsi->vsi_num); 556 return -EEXIST; 557 } 558 559 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) { 560 err = ice_vsi_alloc_q_vector(vsi, v_idx); 561 if (err) 562 goto err_out; 563 } 564 565 return 0; 566 567 err_out: 568 while (v_idx--) 569 ice_free_q_vector(vsi, v_idx); 570 571 dev_err(dev, "Failed to allocate %d q_vector for VSI %d, ret=%d\n", 572 vsi->num_q_vectors, vsi->vsi_num, err); 573 vsi->num_q_vectors = 0; 574 return err; 575 } 576 577 /** 578 * ice_vsi_map_rings_to_vectors - Map VSI rings to interrupt vectors 579 * @vsi: the VSI being configured 580 * 581 * This function maps descriptor rings to the queue-specific vectors allotted 582 * through the MSI-X enabling code. On a constrained vector budget, we map Tx 583 * and Rx rings to the vector as "efficiently" as possible. 584 */ 585 void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi) 586 { 587 int q_vectors = vsi->num_q_vectors; 588 u16 tx_rings_rem, rx_rings_rem; 589 int v_id; 590 591 /* initially assigning remaining rings count to VSIs num queue value */ 592 tx_rings_rem = vsi->num_txq; 593 rx_rings_rem = vsi->num_rxq; 594 595 for (v_id = 0; v_id < q_vectors; v_id++) { 596 struct ice_q_vector *q_vector = vsi->q_vectors[v_id]; 597 u8 tx_rings_per_v, rx_rings_per_v; 598 u16 q_id, q_base; 599 600 /* Tx rings mapping to vector */ 601 tx_rings_per_v = (u8)DIV_ROUND_UP(tx_rings_rem, 602 q_vectors - v_id); 603 q_vector->num_ring_tx = tx_rings_per_v; 604 q_vector->tx.ring = NULL; 605 q_vector->tx.itr_idx = ICE_TX_ITR; 606 q_base = vsi->num_txq - tx_rings_rem; 607 608 for (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) { 609 struct ice_ring *tx_ring = vsi->tx_rings[q_id]; 610 611 tx_ring->q_vector = q_vector; 612 tx_ring->next = q_vector->tx.ring; 613 q_vector->tx.ring = tx_ring; 614 } 615 tx_rings_rem -= tx_rings_per_v; 616 617 /* Rx rings mapping to vector */ 618 rx_rings_per_v = (u8)DIV_ROUND_UP(rx_rings_rem, 619 q_vectors - v_id); 620 q_vector->num_ring_rx = rx_rings_per_v; 621 q_vector->rx.ring = NULL; 622 q_vector->rx.itr_idx = ICE_RX_ITR; 623 q_base = vsi->num_rxq - rx_rings_rem; 624 625 for (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) { 626 struct ice_ring *rx_ring = vsi->rx_rings[q_id]; 627 628 rx_ring->q_vector = q_vector; 629 rx_ring->next = q_vector->rx.ring; 630 q_vector->rx.ring = rx_ring; 631 } 632 rx_rings_rem -= rx_rings_per_v; 633 } 634 } 635 636 /** 637 * ice_vsi_free_q_vectors - Free memory allocated for interrupt vectors 638 * @vsi: the VSI having memory freed 639 */ 640 void ice_vsi_free_q_vectors(struct ice_vsi *vsi) 641 { 642 int v_idx; 643 644 ice_for_each_q_vector(vsi, v_idx) 645 ice_free_q_vector(vsi, v_idx); 646 } 647 648 /** 649 * ice_vsi_cfg_txq - Configure single Tx queue 650 * @vsi: the VSI that queue belongs to 651 * @ring: Tx ring to be configured 652 * @qg_buf: queue group buffer 653 */ 654 int 655 ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_ring *ring, 656 struct ice_aqc_add_tx_qgrp *qg_buf) 657 { 658 u8 buf_len = struct_size(qg_buf, txqs, 1); 659 struct ice_tlan_ctx tlan_ctx = { 0 }; 660 struct ice_aqc_add_txqs_perq *txq; 661 struct ice_pf *pf = vsi->back; 662 struct ice_hw *hw = &pf->hw; 663 enum ice_status status; 664 u16 pf_q; 665 u8 tc; 666 667 pf_q = ring->reg_idx; 668 ice_setup_tx_ctx(ring, &tlan_ctx, pf_q); 669 /* copy context contents into the qg_buf */ 670 qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q); 671 ice_set_ctx(hw, (u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx, 672 ice_tlan_ctx_info); 673 674 /* init queue specific tail reg. It is referred as 675 * transmit comm scheduler queue doorbell. 676 */ 677 ring->tail = hw->hw_addr + QTX_COMM_DBELL(pf_q); 678 679 if (IS_ENABLED(CONFIG_DCB)) 680 tc = ring->dcb_tc; 681 else 682 tc = 0; 683 684 /* Add unique software queue handle of the Tx queue per 685 * TC into the VSI Tx ring 686 */ 687 ring->q_handle = ice_calc_q_handle(vsi, ring, tc); 688 689 status = ice_ena_vsi_txq(vsi->port_info, vsi->idx, tc, ring->q_handle, 690 1, qg_buf, buf_len, NULL); 691 if (status) { 692 dev_err(ice_pf_to_dev(pf), "Failed to set LAN Tx queue context, error: %s\n", 693 ice_stat_str(status)); 694 return -ENODEV; 695 } 696 697 /* Add Tx Queue TEID into the VSI Tx ring from the 698 * response. This will complete configuring and 699 * enabling the queue. 700 */ 701 txq = &qg_buf->txqs[0]; 702 if (pf_q == le16_to_cpu(txq->txq_id)) 703 ring->txq_teid = le32_to_cpu(txq->q_teid); 704 705 return 0; 706 } 707 708 /** 709 * ice_cfg_itr - configure the initial interrupt throttle values 710 * @hw: pointer to the HW structure 711 * @q_vector: interrupt vector that's being configured 712 * 713 * Configure interrupt throttling values for the ring containers that are 714 * associated with the interrupt vector passed in. 715 */ 716 void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector) 717 { 718 ice_cfg_itr_gran(hw); 719 720 if (q_vector->num_ring_rx) { 721 struct ice_ring_container *rc = &q_vector->rx; 722 723 rc->target_itr = ITR_TO_REG(rc->itr_setting); 724 rc->next_update = jiffies + 1; 725 rc->current_itr = rc->target_itr; 726 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx), 727 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S); 728 } 729 730 if (q_vector->num_ring_tx) { 731 struct ice_ring_container *rc = &q_vector->tx; 732 733 rc->target_itr = ITR_TO_REG(rc->itr_setting); 734 rc->next_update = jiffies + 1; 735 rc->current_itr = rc->target_itr; 736 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx), 737 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S); 738 } 739 } 740 741 /** 742 * ice_cfg_txq_interrupt - configure interrupt on Tx queue 743 * @vsi: the VSI being configured 744 * @txq: Tx queue being mapped to MSI-X vector 745 * @msix_idx: MSI-X vector index within the function 746 * @itr_idx: ITR index of the interrupt cause 747 * 748 * Configure interrupt on Tx queue by associating Tx queue to MSI-X vector 749 * within the function space. 750 */ 751 void 752 ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx) 753 { 754 struct ice_pf *pf = vsi->back; 755 struct ice_hw *hw = &pf->hw; 756 u32 val; 757 758 itr_idx = (itr_idx << QINT_TQCTL_ITR_INDX_S) & QINT_TQCTL_ITR_INDX_M; 759 760 val = QINT_TQCTL_CAUSE_ENA_M | itr_idx | 761 ((msix_idx << QINT_TQCTL_MSIX_INDX_S) & QINT_TQCTL_MSIX_INDX_M); 762 763 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val); 764 if (ice_is_xdp_ena_vsi(vsi)) { 765 u32 xdp_txq = txq + vsi->num_xdp_txq; 766 767 wr32(hw, QINT_TQCTL(vsi->txq_map[xdp_txq]), 768 val); 769 } 770 ice_flush(hw); 771 } 772 773 /** 774 * ice_cfg_rxq_interrupt - configure interrupt on Rx queue 775 * @vsi: the VSI being configured 776 * @rxq: Rx queue being mapped to MSI-X vector 777 * @msix_idx: MSI-X vector index within the function 778 * @itr_idx: ITR index of the interrupt cause 779 * 780 * Configure interrupt on Rx queue by associating Rx queue to MSI-X vector 781 * within the function space. 782 */ 783 void 784 ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx) 785 { 786 struct ice_pf *pf = vsi->back; 787 struct ice_hw *hw = &pf->hw; 788 u32 val; 789 790 itr_idx = (itr_idx << QINT_RQCTL_ITR_INDX_S) & QINT_RQCTL_ITR_INDX_M; 791 792 val = QINT_RQCTL_CAUSE_ENA_M | itr_idx | 793 ((msix_idx << QINT_RQCTL_MSIX_INDX_S) & QINT_RQCTL_MSIX_INDX_M); 794 795 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val); 796 797 ice_flush(hw); 798 } 799 800 /** 801 * ice_trigger_sw_intr - trigger a software interrupt 802 * @hw: pointer to the HW structure 803 * @q_vector: interrupt vector to trigger the software interrupt for 804 */ 805 void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector) 806 { 807 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx), 808 (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) | 809 GLINT_DYN_CTL_SWINT_TRIG_M | 810 GLINT_DYN_CTL_INTENA_M); 811 } 812 813 /** 814 * ice_vsi_stop_tx_ring - Disable single Tx ring 815 * @vsi: the VSI being configured 816 * @rst_src: reset source 817 * @rel_vmvf_num: Relative ID of VF/VM 818 * @ring: Tx ring to be stopped 819 * @txq_meta: Meta data of Tx ring to be stopped 820 */ 821 int 822 ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src, 823 u16 rel_vmvf_num, struct ice_ring *ring, 824 struct ice_txq_meta *txq_meta) 825 { 826 struct ice_pf *pf = vsi->back; 827 struct ice_q_vector *q_vector; 828 struct ice_hw *hw = &pf->hw; 829 enum ice_status status; 830 u32 val; 831 832 /* clear cause_ena bit for disabled queues */ 833 val = rd32(hw, QINT_TQCTL(ring->reg_idx)); 834 val &= ~QINT_TQCTL_CAUSE_ENA_M; 835 wr32(hw, QINT_TQCTL(ring->reg_idx), val); 836 837 /* software is expected to wait for 100 ns */ 838 ndelay(100); 839 840 /* trigger a software interrupt for the vector 841 * associated to the queue to schedule NAPI handler 842 */ 843 q_vector = ring->q_vector; 844 if (q_vector) 845 ice_trigger_sw_intr(hw, q_vector); 846 847 status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx, 848 txq_meta->tc, 1, &txq_meta->q_handle, 849 &txq_meta->q_id, &txq_meta->q_teid, rst_src, 850 rel_vmvf_num, NULL); 851 852 /* if the disable queue command was exercised during an 853 * active reset flow, ICE_ERR_RESET_ONGOING is returned. 854 * This is not an error as the reset operation disables 855 * queues at the hardware level anyway. 856 */ 857 if (status == ICE_ERR_RESET_ONGOING) { 858 dev_dbg(ice_pf_to_dev(vsi->back), "Reset in progress. LAN Tx queues already disabled\n"); 859 } else if (status == ICE_ERR_DOES_NOT_EXIST) { 860 dev_dbg(ice_pf_to_dev(vsi->back), "LAN Tx queues do not exist, nothing to disable\n"); 861 } else if (status) { 862 dev_err(ice_pf_to_dev(vsi->back), "Failed to disable LAN Tx queues, error: %s\n", 863 ice_stat_str(status)); 864 return -ENODEV; 865 } 866 867 return 0; 868 } 869 870 /** 871 * ice_fill_txq_meta - Prepare the Tx queue's meta data 872 * @vsi: VSI that ring belongs to 873 * @ring: ring that txq_meta will be based on 874 * @txq_meta: a helper struct that wraps Tx queue's information 875 * 876 * Set up a helper struct that will contain all the necessary fields that 877 * are needed for stopping Tx queue 878 */ 879 void 880 ice_fill_txq_meta(struct ice_vsi *vsi, struct ice_ring *ring, 881 struct ice_txq_meta *txq_meta) 882 { 883 u8 tc; 884 885 if (IS_ENABLED(CONFIG_DCB)) 886 tc = ring->dcb_tc; 887 else 888 tc = 0; 889 890 txq_meta->q_id = ring->reg_idx; 891 txq_meta->q_teid = ring->txq_teid; 892 txq_meta->q_handle = ring->q_handle; 893 txq_meta->vsi_idx = vsi->idx; 894 txq_meta->tc = tc; 895 } 896