1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 struct ice_aqc_generic { 16 __le32 param0; 17 __le32 param1; 18 __le32 addr_high; 19 __le32 addr_low; 20 }; 21 22 /* Get version (direct 0x0001) */ 23 struct ice_aqc_get_ver { 24 __le32 rom_ver; 25 __le32 fw_build; 26 u8 fw_branch; 27 u8 fw_major; 28 u8 fw_minor; 29 u8 fw_patch; 30 u8 api_branch; 31 u8 api_major; 32 u8 api_minor; 33 u8 api_patch; 34 }; 35 36 /* Send driver version (indirect 0x0002) */ 37 struct ice_aqc_driver_ver { 38 u8 major_ver; 39 u8 minor_ver; 40 u8 build_ver; 41 u8 subbuild_ver; 42 u8 reserved[4]; 43 __le32 addr_high; 44 __le32 addr_low; 45 }; 46 47 /* Queue Shutdown (direct 0x0003) */ 48 struct ice_aqc_q_shutdown { 49 u8 driver_unloading; 50 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 51 u8 reserved[15]; 52 }; 53 54 /* Request resource ownership (direct 0x0008) 55 * Release resource ownership (direct 0x0009) 56 */ 57 struct ice_aqc_req_res { 58 __le16 res_id; 59 #define ICE_AQC_RES_ID_NVM 1 60 #define ICE_AQC_RES_ID_SDP 2 61 #define ICE_AQC_RES_ID_CHNG_LOCK 3 62 #define ICE_AQC_RES_ID_GLBL_LOCK 4 63 __le16 access_type; 64 #define ICE_AQC_RES_ACCESS_READ 1 65 #define ICE_AQC_RES_ACCESS_WRITE 2 66 67 /* Upon successful completion, FW writes this value and driver is 68 * expected to release resource before timeout. This value is provided 69 * in milliseconds. 70 */ 71 __le32 timeout; 72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 76 /* For SDP: pin ID of the SDP */ 77 __le32 res_number; 78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 79 __le16 status; 80 #define ICE_AQ_RES_GLBL_SUCCESS 0 81 #define ICE_AQ_RES_GLBL_IN_PROG 1 82 #define ICE_AQ_RES_GLBL_DONE 2 83 u8 reserved[2]; 84 }; 85 86 /* Get function capabilities (indirect 0x000A) 87 * Get device capabilities (indirect 0x000B) 88 */ 89 struct ice_aqc_list_caps { 90 u8 cmd_flags; 91 u8 pf_index; 92 u8 reserved[2]; 93 __le32 count; 94 __le32 addr_high; 95 __le32 addr_low; 96 }; 97 98 /* Device/Function buffer entry, repeated per reported capability */ 99 struct ice_aqc_list_caps_elem { 100 __le16 cap; 101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 102 #define ICE_AQC_CAPS_SRIOV 0x0012 103 #define ICE_AQC_CAPS_VF 0x0013 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_1588 0x0046 112 #define ICE_AQC_CAPS_MAX_MTU 0x0047 113 #define ICE_AQC_CAPS_NVM_VER 0x0048 114 #define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049 115 #define ICE_AQC_CAPS_OROM_VER 0x004A 116 #define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B 117 #define ICE_AQC_CAPS_NET_VER 0x004C 118 #define ICE_AQC_CAPS_PENDING_NET_VER 0x004D 119 #define ICE_AQC_CAPS_RDMA 0x0051 120 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 121 122 u8 major_ver; 123 u8 minor_ver; 124 /* Number of resources described by this capability */ 125 __le32 number; 126 /* Only meaningful for some types of resources */ 127 __le32 logical_id; 128 /* Only meaningful for some types of resources */ 129 __le32 phys_id; 130 __le64 rsvd1; 131 __le64 rsvd2; 132 }; 133 134 /* Manage MAC address, read command - indirect (0x0107) 135 * This struct is also used for the response 136 */ 137 struct ice_aqc_manage_mac_read { 138 __le16 flags; /* Zeroed by device driver */ 139 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 140 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 141 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 142 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 143 #define ICE_AQC_MAN_MAC_READ_S 4 144 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 145 u8 rsvd[2]; 146 u8 num_addr; /* Used in response */ 147 u8 rsvd1[3]; 148 __le32 addr_high; 149 __le32 addr_low; 150 }; 151 152 /* Response buffer format for manage MAC read command */ 153 struct ice_aqc_manage_mac_read_resp { 154 u8 lport_num; 155 u8 addr_type; 156 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 157 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 158 u8 mac_addr[ETH_ALEN]; 159 }; 160 161 /* Manage MAC address, write command - direct (0x0108) */ 162 struct ice_aqc_manage_mac_write { 163 u8 rsvd; 164 u8 flags; 165 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 166 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 167 #define ICE_AQC_MAN_MAC_WR_S 6 168 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S) 169 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 170 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 171 /* byte stream in network order */ 172 u8 mac_addr[ETH_ALEN]; 173 __le32 addr_high; 174 __le32 addr_low; 175 }; 176 177 /* Clear PXE Command and response (direct 0x0110) */ 178 struct ice_aqc_clear_pxe { 179 u8 rx_cnt; 180 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 181 u8 reserved[15]; 182 }; 183 184 /* Get switch configuration (0x0200) */ 185 struct ice_aqc_get_sw_cfg { 186 /* Reserved for command and copy of request flags for response */ 187 __le16 flags; 188 /* First desc in case of command and next_elem in case of response 189 * In case of response, if it is not zero, means all the configuration 190 * was not returned and new command shall be sent with this value in 191 * the 'first desc' field 192 */ 193 __le16 element; 194 /* Reserved for command, only used for response */ 195 __le16 num_elems; 196 __le16 rsvd; 197 __le32 addr_high; 198 __le32 addr_low; 199 }; 200 201 /* Each entry in the response buffer is of the following type: */ 202 struct ice_aqc_get_sw_cfg_resp_elem { 203 /* VSI/Port Number */ 204 __le16 vsi_port_num; 205 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 206 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 207 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 208 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 209 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 210 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 211 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 212 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 213 214 /* SWID VSI/Port belongs to */ 215 __le16 swid; 216 217 /* Bit 14..0 : PF/VF number VSI belongs to 218 * Bit 15 : VF indication bit 219 */ 220 __le16 pf_vf_num; 221 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 222 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 223 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 224 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 225 }; 226 227 /* These resource type defines are used for all switch resource 228 * commands where a resource type is required, such as: 229 * Get Resource Allocation command (indirect 0x0204) 230 * Allocate Resources command (indirect 0x0208) 231 * Free Resources command (indirect 0x0209) 232 * Get Allocated Resource Descriptors Command (indirect 0x020A) 233 */ 234 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 235 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 236 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 237 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 238 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 239 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 240 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 241 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 242 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 243 244 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 245 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 246 247 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 248 249 #define ICE_AQC_RES_TYPE_S 0 250 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 251 252 /* Allocate Resources command (indirect 0x0208) 253 * Free Resources command (indirect 0x0209) 254 */ 255 struct ice_aqc_alloc_free_res_cmd { 256 __le16 num_entries; /* Number of Resource entries */ 257 u8 reserved[6]; 258 __le32 addr_high; 259 __le32 addr_low; 260 }; 261 262 /* Resource descriptor */ 263 struct ice_aqc_res_elem { 264 union { 265 __le16 sw_resp; 266 __le16 flu_resp; 267 } e; 268 }; 269 270 /* Buffer for Allocate/Free Resources commands */ 271 struct ice_aqc_alloc_free_res_elem { 272 __le16 res_type; /* Types defined above cmd 0x0204 */ 273 #define ICE_AQC_RES_TYPE_SHARED_S 7 274 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 275 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 276 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 277 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 278 __le16 num_elems; 279 struct ice_aqc_res_elem elem[]; 280 }; 281 282 /* Add VSI (indirect 0x0210) 283 * Update VSI (indirect 0x0211) 284 * Get VSI (indirect 0x0212) 285 * Free VSI (indirect 0x0213) 286 */ 287 struct ice_aqc_add_get_update_free_vsi { 288 __le16 vsi_num; 289 #define ICE_AQ_VSI_NUM_S 0 290 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 291 #define ICE_AQ_VSI_IS_VALID BIT(15) 292 __le16 cmd_flags; 293 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 294 u8 vf_id; 295 u8 reserved; 296 __le16 vsi_flags; 297 #define ICE_AQ_VSI_TYPE_S 0 298 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 299 #define ICE_AQ_VSI_TYPE_VF 0x0 300 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 301 #define ICE_AQ_VSI_TYPE_PF 0x2 302 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 303 __le32 addr_high; 304 __le32 addr_low; 305 }; 306 307 /* Response descriptor for: 308 * Add VSI (indirect 0x0210) 309 * Update VSI (indirect 0x0211) 310 * Free VSI (indirect 0x0213) 311 */ 312 struct ice_aqc_add_update_free_vsi_resp { 313 __le16 vsi_num; 314 __le16 ext_status; 315 __le16 vsi_used; 316 __le16 vsi_free; 317 __le32 addr_high; 318 __le32 addr_low; 319 }; 320 321 struct ice_aqc_vsi_props { 322 __le16 valid_sections; 323 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 324 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 325 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 326 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 327 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 328 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 329 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 330 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 331 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 332 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 333 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 334 /* switch section */ 335 u8 sw_id; 336 u8 sw_flags; 337 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 338 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 339 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 340 u8 sw_flags2; 341 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 342 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 343 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 344 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 345 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 346 u8 veb_stat_id; 347 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 348 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 349 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 350 /* security section */ 351 u8 sec_flags; 352 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 353 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 354 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 355 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 356 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 357 u8 sec_reserved; 358 /* VLAN section */ 359 __le16 pvid; /* VLANS include priority bits */ 360 u8 pvlan_reserved[2]; 361 u8 vlan_flags; 362 #define ICE_AQ_VSI_VLAN_MODE_S 0 363 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 364 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 365 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 366 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 367 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 368 #define ICE_AQ_VSI_VLAN_EMOD_S 3 369 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 370 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 371 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 372 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 373 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 374 u8 pvlan_reserved2[3]; 375 /* ingress egress up sections */ 376 __le32 ingress_table; /* bitmap, 3 bits per up */ 377 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 378 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 379 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 380 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 381 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 382 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 383 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 384 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 385 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 386 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 387 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 388 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 389 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 390 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 391 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 392 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 393 __le32 egress_table; /* same defines as for ingress table */ 394 /* outer tags section */ 395 __le16 outer_tag; 396 u8 outer_tag_flags; 397 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 398 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 399 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 400 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 401 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 402 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 403 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 404 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 405 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 406 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 407 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 408 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 409 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 410 u8 outer_tag_reserved; 411 /* queue mapping section */ 412 __le16 mapping_flags; 413 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 414 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 415 __le16 q_mapping[16]; 416 #define ICE_AQ_VSI_Q_S 0 417 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 418 __le16 tc_mapping[8]; 419 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 420 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 421 #define ICE_AQ_VSI_TC_Q_NUM_S 11 422 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 423 /* queueing option section */ 424 u8 q_opt_rss; 425 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 426 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 427 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 428 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 429 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 430 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 431 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 432 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 433 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 434 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 435 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 436 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 437 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 438 u8 q_opt_tc; 439 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 440 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 441 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 442 u8 q_opt_flags; 443 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 444 u8 q_opt_reserved[3]; 445 /* outer up section */ 446 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 447 /* section 10 */ 448 __le16 sect_10_reserved; 449 /* flow director section */ 450 __le16 fd_options; 451 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 452 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 453 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 454 __le16 max_fd_fltr_dedicated; 455 __le16 max_fd_fltr_shared; 456 __le16 fd_def_q; 457 #define ICE_AQ_VSI_FD_DEF_Q_S 0 458 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 459 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 460 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 461 __le16 fd_report_opt; 462 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 463 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 464 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 465 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 466 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 467 /* PASID section */ 468 __le32 pasid_id; 469 #define ICE_AQ_VSI_PASID_ID_S 0 470 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 471 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 472 u8 reserved[24]; 473 }; 474 475 #define ICE_MAX_NUM_RECIPES 64 476 477 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 478 */ 479 struct ice_aqc_sw_rules { 480 /* ops: add switch rules, referring the number of rules. 481 * ops: update switch rules, referring the number of filters 482 * ops: remove switch rules, referring the entry index. 483 * ops: get switch rules, referring to the number of filters. 484 */ 485 __le16 num_rules_fltr_entry_index; 486 u8 reserved[6]; 487 __le32 addr_high; 488 __le32 addr_low; 489 }; 490 491 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 492 * This structures describes the lookup rules and associated actions. "index" 493 * is returned as part of a response to a successful Add command, and can be 494 * used to identify the rule for Update/Get/Remove commands. 495 */ 496 struct ice_sw_rule_lkup_rx_tx { 497 __le16 recipe_id; 498 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 499 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 500 __le16 src; 501 __le32 act; 502 503 /* Bit 0:1 - Action type */ 504 #define ICE_SINGLE_ACT_TYPE_S 0x00 505 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 506 507 /* Bit 2 - Loop back enable 508 * Bit 3 - LAN enable 509 */ 510 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 511 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 512 513 /* Action type = 0 - Forward to VSI or VSI list */ 514 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 515 516 #define ICE_SINGLE_ACT_VSI_ID_S 4 517 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 518 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 519 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 520 /* This bit needs to be set if action is forward to VSI list */ 521 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 522 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 523 #define ICE_SINGLE_ACT_DROP BIT(18) 524 525 /* Action type = 1 - Forward to Queue of Queue group */ 526 #define ICE_SINGLE_ACT_TO_Q 0x1 527 #define ICE_SINGLE_ACT_Q_INDEX_S 4 528 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 529 #define ICE_SINGLE_ACT_Q_REGION_S 15 530 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 531 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 532 533 /* Action type = 2 - Prune */ 534 #define ICE_SINGLE_ACT_PRUNE 0x2 535 #define ICE_SINGLE_ACT_EGRESS BIT(15) 536 #define ICE_SINGLE_ACT_INGRESS BIT(16) 537 #define ICE_SINGLE_ACT_PRUNET BIT(17) 538 /* Bit 18 should be set to 0 for this action */ 539 540 /* Action type = 2 - Pointer */ 541 #define ICE_SINGLE_ACT_PTR 0x2 542 #define ICE_SINGLE_ACT_PTR_VAL_S 4 543 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 544 /* Bit 18 should be set to 1 */ 545 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 546 547 /* Action type = 3 - Other actions. Last two bits 548 * are other action identifier 549 */ 550 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 551 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 552 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 553 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 554 555 /* Bit 17:18 - Defines other actions */ 556 /* Other action = 0 - Mirror VSI */ 557 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 558 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 559 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 560 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 561 562 /* Other action = 3 - Set Stat count */ 563 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 564 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 565 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 566 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 567 568 __le16 index; /* The index of the rule in the lookup table */ 569 /* Length and values of the header to be matched per recipe or 570 * lookup-type 571 */ 572 __le16 hdr_len; 573 u8 hdr[]; 574 }; 575 576 /* Add/Update/Remove large action command/response entry 577 * "index" is returned as part of a response to a successful Add command, and 578 * can be used to identify the action for Update/Get/Remove commands. 579 */ 580 struct ice_sw_rule_lg_act { 581 __le16 index; /* Index in large action table */ 582 __le16 size; 583 /* Max number of large actions */ 584 #define ICE_MAX_LG_ACT 4 585 /* Bit 0:1 - Action type */ 586 #define ICE_LG_ACT_TYPE_S 0 587 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 588 589 /* Action type = 0 - Forward to VSI or VSI list */ 590 #define ICE_LG_ACT_VSI_FORWARDING 0 591 #define ICE_LG_ACT_VSI_ID_S 3 592 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 593 #define ICE_LG_ACT_VSI_LIST_ID_S 3 594 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 595 /* This bit needs to be set if action is forward to VSI list */ 596 #define ICE_LG_ACT_VSI_LIST BIT(13) 597 598 #define ICE_LG_ACT_VALID_BIT BIT(16) 599 600 /* Action type = 1 - Forward to Queue of Queue group */ 601 #define ICE_LG_ACT_TO_Q 0x1 602 #define ICE_LG_ACT_Q_INDEX_S 3 603 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 604 #define ICE_LG_ACT_Q_REGION_S 14 605 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 606 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 607 608 /* Action type = 2 - Prune */ 609 #define ICE_LG_ACT_PRUNE 0x2 610 #define ICE_LG_ACT_EGRESS BIT(14) 611 #define ICE_LG_ACT_INGRESS BIT(15) 612 #define ICE_LG_ACT_PRUNET BIT(16) 613 614 /* Action type = 3 - Mirror VSI */ 615 #define ICE_LG_OTHER_ACT_MIRROR 0x3 616 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 617 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 618 619 /* Action type = 5 - Generic Value */ 620 #define ICE_LG_ACT_GENERIC 0x5 621 #define ICE_LG_ACT_GENERIC_VALUE_S 3 622 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 623 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 624 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 625 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 626 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 627 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 628 629 /* Action = 7 - Set Stat count */ 630 #define ICE_LG_ACT_STAT_COUNT 0x7 631 #define ICE_LG_ACT_STAT_COUNT_S 3 632 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 633 __le32 act[]; /* array of size for actions */ 634 }; 635 636 /* Add/Update/Remove VSI list command/response entry 637 * "index" is returned as part of a response to a successful Add command, and 638 * can be used to identify the VSI list for Update/Get/Remove commands. 639 */ 640 struct ice_sw_rule_vsi_list { 641 __le16 index; /* Index of VSI/Prune list */ 642 __le16 number_vsi; 643 __le16 vsi[]; /* Array of number_vsi VSI numbers */ 644 }; 645 646 /* Query VSI list command/response entry */ 647 struct ice_sw_rule_vsi_list_query { 648 __le16 index; 649 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI); 650 } __packed; 651 652 /* Add switch rule response: 653 * Content of return buffer is same as the input buffer. The status field and 654 * LUT index are updated as part of the response 655 */ 656 struct ice_aqc_sw_rules_elem { 657 __le16 type; /* Switch rule type, one of T_... */ 658 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 659 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 660 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 661 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 662 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 663 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 664 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 665 __le16 status; 666 union { 667 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 668 struct ice_sw_rule_lg_act lg_act; 669 struct ice_sw_rule_vsi_list vsi_list; 670 struct ice_sw_rule_vsi_list_query vsi_list_query; 671 } __packed pdata; 672 }; 673 674 /* Query PFC Mode (direct 0x0302) 675 * Set PFC Mode (direct 0x0303) 676 */ 677 struct ice_aqc_set_query_pfc_mode { 678 u8 pfc_mode; 679 /* For Query Command response, reserved in all other cases */ 680 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 681 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 682 u8 rsvd[15]; 683 }; 684 /* Get Default Topology (indirect 0x0400) */ 685 struct ice_aqc_get_topo { 686 u8 port_num; 687 u8 num_branches; 688 __le16 reserved1; 689 __le32 reserved2; 690 __le32 addr_high; 691 __le32 addr_low; 692 }; 693 694 /* Update TSE (indirect 0x0403) 695 * Get TSE (indirect 0x0404) 696 * Add TSE (indirect 0x0401) 697 * Delete TSE (indirect 0x040F) 698 * Move TSE (indirect 0x0408) 699 * Suspend Nodes (indirect 0x0409) 700 * Resume Nodes (indirect 0x040A) 701 */ 702 struct ice_aqc_sched_elem_cmd { 703 __le16 num_elem_req; /* Used by commands */ 704 __le16 num_elem_resp; /* Used by responses */ 705 __le32 reserved; 706 __le32 addr_high; 707 __le32 addr_low; 708 }; 709 710 struct ice_aqc_txsched_move_grp_info_hdr { 711 __le32 src_parent_teid; 712 __le32 dest_parent_teid; 713 __le16 num_elems; 714 __le16 reserved; 715 }; 716 717 struct ice_aqc_move_elem { 718 struct ice_aqc_txsched_move_grp_info_hdr hdr; 719 __le32 teid[]; 720 }; 721 722 struct ice_aqc_elem_info_bw { 723 __le16 bw_profile_idx; 724 __le16 bw_alloc; 725 }; 726 727 struct ice_aqc_txsched_elem { 728 u8 elem_type; /* Special field, reserved for some aq calls */ 729 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 730 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 731 #define ICE_AQC_ELEM_TYPE_TC 0x2 732 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 733 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 734 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 735 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 736 u8 valid_sections; 737 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 738 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 739 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 740 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 741 u8 generic; 742 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 743 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 744 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 745 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 746 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 747 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 748 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 749 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 750 u8 flags; /* Special field, reserved for some aq calls */ 751 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 752 struct ice_aqc_elem_info_bw cir_bw; 753 struct ice_aqc_elem_info_bw eir_bw; 754 __le16 srl_id; 755 __le16 reserved2; 756 }; 757 758 struct ice_aqc_txsched_elem_data { 759 __le32 parent_teid; 760 __le32 node_teid; 761 struct ice_aqc_txsched_elem data; 762 }; 763 764 struct ice_aqc_txsched_topo_grp_info_hdr { 765 __le32 parent_teid; 766 __le16 num_elems; 767 __le16 reserved2; 768 }; 769 770 struct ice_aqc_add_elem { 771 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 772 struct ice_aqc_txsched_elem_data generic[]; 773 }; 774 775 struct ice_aqc_get_topo_elem { 776 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 777 struct ice_aqc_txsched_elem_data 778 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 779 }; 780 781 struct ice_aqc_delete_elem { 782 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 783 __le32 teid[]; 784 }; 785 786 /* Query Port ETS (indirect 0x040E) 787 * 788 * This indirect command is used to query port TC node configuration. 789 */ 790 struct ice_aqc_query_port_ets { 791 __le32 port_teid; 792 __le32 reserved; 793 __le32 addr_high; 794 __le32 addr_low; 795 }; 796 797 struct ice_aqc_port_ets_elem { 798 u8 tc_valid_bits; 799 u8 reserved[3]; 800 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 801 __le32 up2tc; 802 u8 tc_bw_share[8]; 803 __le32 port_eir_prof_id; 804 __le32 port_cir_prof_id; 805 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 806 __le32 tc_node_prio; 807 #define ICE_TC_NODE_PRIO_S 0x4 808 u8 reserved1[4]; 809 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 810 }; 811 812 /* Rate limiting profile for 813 * Add RL profile (indirect 0x0410) 814 * Query RL profile (indirect 0x0411) 815 * Remove RL profile (indirect 0x0415) 816 * These indirect commands acts on single or multiple 817 * RL profiles with specified data. 818 */ 819 struct ice_aqc_rl_profile { 820 __le16 num_profiles; 821 __le16 num_processed; /* Only for response. Reserved in Command. */ 822 u8 reserved[4]; 823 __le32 addr_high; 824 __le32 addr_low; 825 }; 826 827 struct ice_aqc_rl_profile_elem { 828 u8 level; 829 u8 flags; 830 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 831 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 832 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 833 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 834 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 835 /* The following flag is used for Query RL Profile Data */ 836 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 837 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 838 839 __le16 profile_id; 840 __le16 max_burst_size; 841 __le16 rl_multiply; 842 __le16 wake_up_calc; 843 __le16 rl_encode; 844 }; 845 846 /* Query Scheduler Resource Allocation (indirect 0x0412) 847 * This indirect command retrieves the scheduler resources allocated by 848 * EMP Firmware to the given PF. 849 */ 850 struct ice_aqc_query_txsched_res { 851 u8 reserved[8]; 852 __le32 addr_high; 853 __le32 addr_low; 854 }; 855 856 struct ice_aqc_generic_sched_props { 857 __le16 phys_levels; 858 __le16 logical_levels; 859 u8 flattening_bitmap; 860 u8 max_device_cgds; 861 u8 max_pf_cgds; 862 u8 rsvd0; 863 __le16 rdma_qsets; 864 u8 rsvd1[22]; 865 }; 866 867 struct ice_aqc_layer_props { 868 u8 logical_layer; 869 u8 chunk_size; 870 __le16 max_device_nodes; 871 __le16 max_pf_nodes; 872 u8 rsvd0[4]; 873 __le16 max_sibl_grp_sz; 874 __le16 max_cir_rl_profiles; 875 __le16 max_eir_rl_profiles; 876 __le16 max_srl_profiles; 877 u8 rsvd1[14]; 878 }; 879 880 struct ice_aqc_query_txsched_res_resp { 881 struct ice_aqc_generic_sched_props sched_props; 882 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 883 }; 884 885 /* Get PHY capabilities (indirect 0x0600) */ 886 struct ice_aqc_get_phy_caps { 887 u8 lport_num; 888 u8 reserved; 889 __le16 param0; 890 /* 18.0 - Report qualified modules */ 891 #define ICE_AQC_GET_PHY_RQM BIT(0) 892 /* 18.1 - 18.3 : Report mode 893 * 000b - Report NVM capabilities 894 * 001b - Report topology capabilities 895 * 010b - Report SW configured 896 * 100b - Report default capabilities 897 */ 898 #define ICE_AQC_REPORT_MODE_S 1 899 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 900 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 901 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 902 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 903 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 904 __le32 reserved1; 905 __le32 addr_high; 906 __le32 addr_low; 907 }; 908 909 /* This is #define of PHY type (Extended): 910 * The first set of defines is for phy_type_low. 911 */ 912 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 913 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 914 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 915 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 916 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 917 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 918 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 919 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 920 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 921 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 922 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 923 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 924 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 925 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 926 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 927 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 928 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 929 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 930 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 931 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 932 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 933 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 934 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 935 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 936 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 937 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 938 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 939 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 940 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 941 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 942 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 943 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 944 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 945 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 946 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 947 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 948 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 949 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 950 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 951 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 952 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 953 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 954 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 955 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 956 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 957 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 958 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 959 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 960 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 961 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 962 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 963 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 964 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 965 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 966 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 967 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 968 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 969 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 970 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 971 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 972 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 973 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 974 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 975 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 976 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 977 /* The second set of defines is for phy_type_high. */ 978 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 979 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 980 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 981 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 982 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 983 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 984 985 struct ice_aqc_get_phy_caps_data { 986 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 987 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 988 u8 caps; 989 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 990 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 991 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 992 #define ICE_AQC_PHY_EN_LINK BIT(3) 993 #define ICE_AQC_PHY_AN_MODE BIT(4) 994 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 995 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 996 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 997 u8 low_power_ctrl_an; 998 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 999 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1000 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1001 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1002 __le16 eee_cap; 1003 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1004 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1005 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1006 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1007 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1008 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1009 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1010 __le16 eeer_value; 1011 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1012 u8 phy_fw_ver[8]; 1013 u8 link_fec_options; 1014 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1015 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1016 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1017 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1018 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1019 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1020 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1021 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 1022 u8 module_compliance_enforcement; 1023 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1024 u8 extended_compliance_code; 1025 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1026 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1027 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1028 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1029 #define ICE_AQC_MOD_TYPE_IDENT 1 1030 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1031 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1032 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1033 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1034 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1035 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1036 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1037 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1038 u8 qualified_module_count; 1039 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1040 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1041 struct { 1042 u8 v_oui[3]; 1043 u8 rsvd3; 1044 u8 v_part[16]; 1045 __le32 v_rev; 1046 __le64 rsvd4; 1047 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1048 }; 1049 1050 /* Set PHY capabilities (direct 0x0601) 1051 * NOTE: This command must be followed by setup link and restart auto-neg 1052 */ 1053 struct ice_aqc_set_phy_cfg { 1054 u8 lport_num; 1055 u8 reserved[7]; 1056 __le32 addr_high; 1057 __le32 addr_low; 1058 }; 1059 1060 /* Set PHY config command data structure */ 1061 struct ice_aqc_set_phy_cfg_data { 1062 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1063 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1064 u8 caps; 1065 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1066 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1067 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1068 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1069 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1070 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1071 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1072 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1073 u8 low_power_ctrl_an; 1074 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1075 __le16 eeer_value; 1076 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1077 u8 module_compliance_enforcement; 1078 }; 1079 1080 /* Set MAC Config command data structure (direct 0x0603) */ 1081 struct ice_aqc_set_mac_cfg { 1082 __le16 max_frame_size; 1083 u8 params; 1084 #define ICE_AQ_SET_MAC_PACE_S 3 1085 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1086 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1087 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1088 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1089 u8 tx_tmr_priority; 1090 __le16 tx_tmr_value; 1091 __le16 fc_refresh_threshold; 1092 u8 drop_opts; 1093 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1094 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1095 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1096 u8 reserved[7]; 1097 }; 1098 1099 /* Restart AN command data structure (direct 0x0605) 1100 * Also used for response, with only the lport_num field present. 1101 */ 1102 struct ice_aqc_restart_an { 1103 u8 lport_num; 1104 u8 reserved; 1105 u8 cmd_flags; 1106 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1107 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1108 u8 reserved2[13]; 1109 }; 1110 1111 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1112 struct ice_aqc_get_link_status { 1113 u8 lport_num; 1114 u8 reserved; 1115 __le16 cmd_flags; 1116 #define ICE_AQ_LSE_M 0x3 1117 #define ICE_AQ_LSE_NOP 0x0 1118 #define ICE_AQ_LSE_DIS 0x2 1119 #define ICE_AQ_LSE_ENA 0x3 1120 /* only response uses this flag */ 1121 #define ICE_AQ_LSE_IS_ENABLED 0x1 1122 __le32 reserved2; 1123 __le32 addr_high; 1124 __le32 addr_low; 1125 }; 1126 1127 /* Get link status response data structure, also used for Link Status Event */ 1128 struct ice_aqc_get_link_status_data { 1129 u8 topo_media_conflict; 1130 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1131 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1132 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1133 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1134 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1135 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1136 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1137 u8 link_cfg_err; 1138 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1139 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1140 u8 link_info; 1141 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1142 #define ICE_AQ_LINK_FAULT BIT(1) 1143 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1144 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1145 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1146 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1147 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1148 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1149 u8 an_info; 1150 #define ICE_AQ_AN_COMPLETED BIT(0) 1151 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1152 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1153 #define ICE_AQ_FEC_EN BIT(3) 1154 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1155 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1156 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1157 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1158 u8 ext_info; 1159 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1160 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1161 /* Port Tx Suspended */ 1162 #define ICE_AQ_LINK_TX_S 2 1163 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1164 #define ICE_AQ_LINK_TX_ACTIVE 0 1165 #define ICE_AQ_LINK_TX_DRAINED 1 1166 #define ICE_AQ_LINK_TX_FLUSHED 3 1167 u8 reserved2; 1168 __le16 max_frame_size; 1169 u8 cfg; 1170 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1171 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1172 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1173 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1174 /* Pacing Config */ 1175 #define ICE_AQ_CFG_PACING_S 3 1176 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1177 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1178 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1179 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1180 /* External Device Power Ability */ 1181 u8 power_desc; 1182 #define ICE_AQ_PWR_CLASS_M 0x3F 1183 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1184 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1185 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1186 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1187 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1188 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1189 __le16 link_speed; 1190 #define ICE_AQ_LINK_SPEED_M 0x7FF 1191 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1192 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1193 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1194 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1195 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1196 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1197 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1198 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1199 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1200 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1201 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1202 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1203 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1204 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1205 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1206 }; 1207 1208 /* Set event mask command (direct 0x0613) */ 1209 struct ice_aqc_set_event_mask { 1210 u8 lport_num; 1211 u8 reserved[7]; 1212 __le16 event_mask; 1213 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1214 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1215 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1216 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1217 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1218 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1219 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1220 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1221 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1222 u8 reserved1[6]; 1223 }; 1224 1225 /* Set MAC Loopback command (direct 0x0620) */ 1226 struct ice_aqc_set_mac_lb { 1227 u8 lb_mode; 1228 #define ICE_AQ_MAC_LB_EN BIT(0) 1229 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1230 u8 reserved[15]; 1231 }; 1232 1233 struct ice_aqc_link_topo_addr { 1234 u8 lport_num; 1235 u8 lport_num_valid; 1236 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1237 u8 node_type_ctx; 1238 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1239 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1240 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1241 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1242 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1243 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1244 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1245 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1246 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1247 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1248 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1249 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1250 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1251 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1252 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1253 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1254 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1255 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1256 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1257 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1258 u8 index; 1259 __le16 handle; 1260 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1261 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1262 /* Used to decode the handle field */ 1263 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1264 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1265 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1266 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1267 /* In case of a Mezzanine type */ 1268 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1269 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1270 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1271 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1272 /* In case of a LOM type */ 1273 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1274 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1275 }; 1276 1277 /* Get Link Topology Handle (direct, 0x06E0) */ 1278 struct ice_aqc_get_link_topo { 1279 struct ice_aqc_link_topo_addr addr; 1280 u8 node_part_num; 1281 u8 rsvd[9]; 1282 }; 1283 1284 /* Set Port Identification LED (direct, 0x06E9) */ 1285 struct ice_aqc_set_port_id_led { 1286 u8 lport_num; 1287 u8 lport_num_valid; 1288 u8 ident_mode; 1289 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1290 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1291 u8 rsvd[13]; 1292 }; 1293 1294 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1295 struct ice_aqc_sff_eeprom { 1296 u8 lport_num; 1297 u8 lport_num_valid; 1298 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1299 __le16 i2c_bus_addr; 1300 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1301 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1302 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1303 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1304 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1305 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1306 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1307 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1308 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1309 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1310 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1311 __le16 i2c_mem_addr; 1312 __le16 eeprom_page; 1313 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1314 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1315 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1316 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1317 __le32 addr_high; 1318 __le32 addr_low; 1319 }; 1320 1321 /* NVM Read command (indirect 0x0701) 1322 * NVM Erase commands (direct 0x0702) 1323 * NVM Update commands (indirect 0x0703) 1324 */ 1325 struct ice_aqc_nvm { 1326 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1327 __le16 offset_low; 1328 u8 offset_high; 1329 u8 cmd_flags; 1330 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1331 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1332 #define ICE_AQC_NVM_PRESERVATION_S 1 1333 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1334 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1335 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1336 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 1337 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1338 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1339 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1340 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1341 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1342 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1343 #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3) 1344 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1345 __le16 module_typeid; 1346 __le16 length; 1347 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1348 __le32 addr_high; 1349 __le32 addr_low; 1350 }; 1351 1352 #define ICE_AQC_NVM_START_POINT 0 1353 1354 /* NVM Checksum Command (direct, 0x0706) */ 1355 struct ice_aqc_nvm_checksum { 1356 u8 flags; 1357 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1358 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1359 u8 rsvd; 1360 __le16 checksum; /* Used only by response */ 1361 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1362 u8 rsvd2[12]; 1363 }; 1364 1365 /* Used for NVM Set Package Data command - 0x070A */ 1366 struct ice_aqc_nvm_pkg_data { 1367 u8 reserved[3]; 1368 u8 cmd_flags; 1369 #define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */ 1370 #define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */ 1371 1372 u32 reserved1; 1373 __le32 addr_high; 1374 __le32 addr_low; 1375 }; 1376 1377 /* Used for Pass Component Table command - 0x070B */ 1378 struct ice_aqc_nvm_pass_comp_tbl { 1379 u8 component_response; /* Response only */ 1380 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0 1381 #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1 1382 #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2 1383 u8 component_response_code; /* Response only */ 1384 #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0 1385 #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1 1386 #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2 1387 #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3 1388 #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4 1389 #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5 1390 #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6 1391 #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7 1392 #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8 1393 #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA 1394 #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB 1395 u8 reserved; 1396 u8 transfer_flag; 1397 #define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1 1398 #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2 1399 #define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4 1400 #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5 1401 __le32 reserved1; 1402 __le32 addr_high; 1403 __le32 addr_low; 1404 }; 1405 1406 struct ice_aqc_nvm_comp_tbl { 1407 __le16 comp_class; 1408 #define NVM_COMP_CLASS_ALL_FW 0x000A 1409 1410 __le16 comp_id; 1411 #define NVM_COMP_ID_OROM 0x5 1412 #define NVM_COMP_ID_NVM 0x6 1413 #define NVM_COMP_ID_NETLIST 0x8 1414 1415 u8 comp_class_idx; 1416 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0 1417 1418 __le32 comp_cmp_stamp; 1419 u8 cvs_type; 1420 #define NVM_CVS_TYPE_ASCII 0x1 1421 1422 u8 cvs_len; 1423 u8 cvs[]; /* Component Version String */ 1424 } __packed; 1425 1426 /* Send to PF command (indirect 0x0801) ID is only used by PF 1427 * 1428 * Send to VF command (indirect 0x0802) ID is only used by PF 1429 * 1430 */ 1431 struct ice_aqc_pf_vf_msg { 1432 __le32 id; 1433 u32 reserved; 1434 __le32 addr_high; 1435 __le32 addr_low; 1436 }; 1437 1438 /* Get LLDP MIB (indirect 0x0A00) 1439 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1440 * as the format is the same. 1441 */ 1442 struct ice_aqc_lldp_get_mib { 1443 u8 type; 1444 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1445 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1446 #define ICE_AQ_LLDP_MIB_LOCAL 0 1447 #define ICE_AQ_LLDP_MIB_REMOTE 1 1448 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1449 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1450 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1451 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1452 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1453 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1454 #define ICE_AQ_LLDP_TX_S 0x4 1455 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1456 #define ICE_AQ_LLDP_TX_ACTIVE 0 1457 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1458 #define ICE_AQ_LLDP_TX_FLUSHED 3 1459 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1460 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1461 * Get LLDP MIB (0x0A00) response only. 1462 */ 1463 u8 reserved1; 1464 __le16 local_len; 1465 __le16 remote_len; 1466 u8 reserved2[2]; 1467 __le32 addr_high; 1468 __le32 addr_low; 1469 }; 1470 1471 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1472 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1473 struct ice_aqc_lldp_set_mib_change { 1474 u8 command; 1475 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1476 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1477 u8 reserved[15]; 1478 }; 1479 1480 /* Stop LLDP (direct 0x0A05) */ 1481 struct ice_aqc_lldp_stop { 1482 u8 command; 1483 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1484 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1485 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1486 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1487 u8 reserved[15]; 1488 }; 1489 1490 /* Start LLDP (direct 0x0A06) */ 1491 struct ice_aqc_lldp_start { 1492 u8 command; 1493 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1494 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1495 u8 reserved[15]; 1496 }; 1497 1498 /* Get CEE DCBX Oper Config (0x0A07) 1499 * The command uses the generic descriptor struct and 1500 * returns the struct below as an indirect response. 1501 */ 1502 struct ice_aqc_get_cee_dcb_cfg_resp { 1503 u8 oper_num_tc; 1504 u8 oper_prio_tc[4]; 1505 u8 oper_tc_bw[8]; 1506 u8 oper_pfc_en; 1507 __le16 oper_app_prio; 1508 #define ICE_AQC_CEE_APP_FCOE_S 0 1509 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1510 #define ICE_AQC_CEE_APP_ISCSI_S 3 1511 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1512 #define ICE_AQC_CEE_APP_FIP_S 8 1513 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1514 __le32 tlv_status; 1515 #define ICE_AQC_CEE_PG_STATUS_S 0 1516 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1517 #define ICE_AQC_CEE_PFC_STATUS_S 3 1518 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1519 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1520 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1521 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1522 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1523 #define ICE_AQC_CEE_FIP_STATUS_S 16 1524 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1525 u8 reserved[12]; 1526 }; 1527 1528 /* Set Local LLDP MIB (indirect 0x0A08) 1529 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1530 */ 1531 struct ice_aqc_lldp_set_local_mib { 1532 u8 type; 1533 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1534 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1535 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1536 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1537 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1538 u8 reserved0; 1539 __le16 length; 1540 u8 reserved1[4]; 1541 __le32 addr_high; 1542 __le32 addr_low; 1543 }; 1544 1545 /* Stop/Start LLDP Agent (direct 0x0A09) 1546 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1547 * The same structure is used for the response, with the command field 1548 * being used as the status field. 1549 */ 1550 struct ice_aqc_lldp_stop_start_specific_agent { 1551 u8 command; 1552 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1553 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1554 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1555 u8 reserved[15]; 1556 }; 1557 1558 /* LLDP Filter Control (direct 0x0A0A) */ 1559 struct ice_aqc_lldp_filter_ctrl { 1560 u8 cmd_flags; 1561 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 1562 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 1563 u8 reserved1; 1564 __le16 vsi_num; 1565 u8 reserved2[12]; 1566 }; 1567 1568 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1569 struct ice_aqc_get_set_rss_key { 1570 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1571 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1572 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1573 __le16 vsi_id; 1574 u8 reserved[6]; 1575 __le32 addr_high; 1576 __le32 addr_low; 1577 }; 1578 1579 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1580 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1581 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1582 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1583 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1584 1585 struct ice_aqc_get_set_rss_keys { 1586 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1587 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1588 }; 1589 1590 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1591 struct ice_aqc_get_set_rss_lut { 1592 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1593 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1594 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1595 __le16 vsi_id; 1596 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1597 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1598 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1599 1600 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1601 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1602 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1603 1604 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1605 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1606 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1607 1608 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1609 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1610 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1611 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1612 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1613 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1614 1615 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1616 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1617 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1618 1619 __le16 flags; 1620 __le32 reserved; 1621 __le32 addr_high; 1622 __le32 addr_low; 1623 }; 1624 1625 /* Sideband Control Interface Commands */ 1626 /* Neighbor Device Request (indirect 0x0C00); also used for the response. */ 1627 struct ice_aqc_neigh_dev_req { 1628 __le16 sb_data_len; 1629 u8 reserved[6]; 1630 __le32 addr_high; 1631 __le32 addr_low; 1632 }; 1633 1634 /* Add Tx LAN Queues (indirect 0x0C30) */ 1635 struct ice_aqc_add_txqs { 1636 u8 num_qgrps; 1637 u8 reserved[3]; 1638 __le32 reserved1; 1639 __le32 addr_high; 1640 __le32 addr_low; 1641 }; 1642 1643 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1644 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1645 */ 1646 struct ice_aqc_add_txqs_perq { 1647 __le16 txq_id; 1648 u8 rsvd[2]; 1649 __le32 q_teid; 1650 u8 txq_ctx[22]; 1651 u8 rsvd2[2]; 1652 struct ice_aqc_txsched_elem info; 1653 }; 1654 1655 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 1656 * is an array of the following structs. Please note that the length of 1657 * each struct ice_aqc_add_tx_qgrp is variable due 1658 * to the variable number of queues in each group! 1659 */ 1660 struct ice_aqc_add_tx_qgrp { 1661 __le32 parent_teid; 1662 u8 num_txqs; 1663 u8 rsvd[3]; 1664 struct ice_aqc_add_txqs_perq txqs[]; 1665 }; 1666 1667 /* Disable Tx LAN Queues (indirect 0x0C31) */ 1668 struct ice_aqc_dis_txqs { 1669 u8 cmd_type; 1670 #define ICE_AQC_Q_DIS_CMD_S 0 1671 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1672 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1673 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1674 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1675 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1676 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1677 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1678 u8 num_entries; 1679 __le16 vmvf_and_timeout; 1680 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1681 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1682 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1683 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1684 __le32 blocked_cgds; 1685 __le32 addr_high; 1686 __le32 addr_low; 1687 }; 1688 1689 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 1690 * contains the following structures, arrayed one after the 1691 * other. 1692 * Note: Since the q_id is 16 bits wide, if the 1693 * number of queues is even, then 2 bytes of alignment MUST be 1694 * added before the start of the next group, to allow correct 1695 * alignment of the parent_teid field. 1696 */ 1697 struct ice_aqc_dis_txq_item { 1698 __le32 parent_teid; 1699 u8 num_qs; 1700 u8 rsvd; 1701 /* The length of the q_id array varies according to num_qs */ 1702 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1703 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1704 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1705 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1706 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1707 __le16 q_id[]; 1708 } __packed; 1709 1710 /* Add Tx RDMA Queue Set (indirect 0x0C33) */ 1711 struct ice_aqc_add_rdma_qset { 1712 u8 num_qset_grps; 1713 u8 reserved[7]; 1714 __le32 addr_high; 1715 __le32 addr_low; 1716 }; 1717 1718 /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set 1719 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. 1720 */ 1721 struct ice_aqc_add_tx_rdma_qset_entry { 1722 __le16 tx_qset_id; 1723 u8 rsvd[2]; 1724 __le32 qset_teid; 1725 struct ice_aqc_txsched_elem info; 1726 }; 1727 1728 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) 1729 * is an array of the following structs. Please note that the length of 1730 * each struct ice_aqc_add_rdma_qset is variable due to the variable 1731 * number of queues in each group! 1732 */ 1733 struct ice_aqc_add_rdma_qset_data { 1734 __le32 parent_teid; 1735 __le16 num_qsets; 1736 u8 rsvd[2]; 1737 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[]; 1738 }; 1739 1740 /* Configure Firmware Logging Command (indirect 0xFF09) 1741 * Logging Information Read Response (indirect 0xFF10) 1742 * Note: The 0xFF10 command has no input parameters. 1743 */ 1744 struct ice_aqc_fw_logging { 1745 u8 log_ctrl; 1746 #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 1747 #define ICE_AQC_FW_LOG_UART_EN BIT(1) 1748 u8 rsvd0; 1749 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 1750 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 1751 #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 1752 u8 rsvd1[5]; 1753 __le32 addr_high; 1754 __le32 addr_low; 1755 }; 1756 1757 enum ice_aqc_fw_logging_mod { 1758 ICE_AQC_FW_LOG_ID_GENERAL = 0, 1759 ICE_AQC_FW_LOG_ID_CTRL, 1760 ICE_AQC_FW_LOG_ID_LINK, 1761 ICE_AQC_FW_LOG_ID_LINK_TOPO, 1762 ICE_AQC_FW_LOG_ID_DNL, 1763 ICE_AQC_FW_LOG_ID_I2C, 1764 ICE_AQC_FW_LOG_ID_SDP, 1765 ICE_AQC_FW_LOG_ID_MDIO, 1766 ICE_AQC_FW_LOG_ID_ADMINQ, 1767 ICE_AQC_FW_LOG_ID_HDMA, 1768 ICE_AQC_FW_LOG_ID_LLDP, 1769 ICE_AQC_FW_LOG_ID_DCBX, 1770 ICE_AQC_FW_LOG_ID_DCB, 1771 ICE_AQC_FW_LOG_ID_NETPROXY, 1772 ICE_AQC_FW_LOG_ID_NVM, 1773 ICE_AQC_FW_LOG_ID_AUTH, 1774 ICE_AQC_FW_LOG_ID_VPD, 1775 ICE_AQC_FW_LOG_ID_IOSF, 1776 ICE_AQC_FW_LOG_ID_PARSER, 1777 ICE_AQC_FW_LOG_ID_SW, 1778 ICE_AQC_FW_LOG_ID_SCHEDULER, 1779 ICE_AQC_FW_LOG_ID_TXQ, 1780 ICE_AQC_FW_LOG_ID_RSVD, 1781 ICE_AQC_FW_LOG_ID_POST, 1782 ICE_AQC_FW_LOG_ID_WATCHDOG, 1783 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 1784 ICE_AQC_FW_LOG_ID_MNG, 1785 ICE_AQC_FW_LOG_ID_MAX, 1786 }; 1787 1788 /* Defines for both above FW logging command/response buffers */ 1789 #define ICE_AQC_FW_LOG_ID_S 0 1790 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 1791 1792 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 1793 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 1794 1795 #define ICE_AQC_FW_LOG_EN_S 12 1796 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 1797 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 1798 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 1799 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 1800 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 1801 1802 /* Get/Clear FW Log (indirect 0xFF11) */ 1803 struct ice_aqc_get_clear_fw_log { 1804 u8 flags; 1805 #define ICE_AQC_FW_LOG_CLEAR BIT(0) 1806 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 1807 u8 rsvd1[7]; 1808 __le32 addr_high; 1809 __le32 addr_low; 1810 }; 1811 1812 /* Download Package (indirect 0x0C40) */ 1813 /* Also used for Update Package (indirect 0x0C42) */ 1814 struct ice_aqc_download_pkg { 1815 u8 flags; 1816 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 1817 u8 reserved[3]; 1818 __le32 reserved1; 1819 __le32 addr_high; 1820 __le32 addr_low; 1821 }; 1822 1823 struct ice_aqc_download_pkg_resp { 1824 __le32 error_offset; 1825 __le32 error_info; 1826 __le32 addr_high; 1827 __le32 addr_low; 1828 }; 1829 1830 /* Get Package Info List (indirect 0x0C43) */ 1831 struct ice_aqc_get_pkg_info_list { 1832 __le32 reserved1; 1833 __le32 reserved2; 1834 __le32 addr_high; 1835 __le32 addr_low; 1836 }; 1837 1838 /* Version format for packages */ 1839 struct ice_pkg_ver { 1840 u8 major; 1841 u8 minor; 1842 u8 update; 1843 u8 draft; 1844 }; 1845 1846 #define ICE_PKG_NAME_SIZE 32 1847 #define ICE_SEG_ID_SIZE 28 1848 #define ICE_SEG_NAME_SIZE 28 1849 1850 struct ice_aqc_get_pkg_info { 1851 struct ice_pkg_ver ver; 1852 char name[ICE_SEG_NAME_SIZE]; 1853 __le32 track_id; 1854 u8 is_in_nvm; 1855 u8 is_active; 1856 u8 is_active_at_boot; 1857 u8 is_modified; 1858 }; 1859 1860 /* Get Package Info List response buffer format (0x0C43) */ 1861 struct ice_aqc_get_pkg_info_resp { 1862 __le32 count; 1863 struct ice_aqc_get_pkg_info pkg_info[]; 1864 }; 1865 1866 /* Driver Shared Parameters (direct, 0x0C90) */ 1867 struct ice_aqc_driver_shared_params { 1868 u8 set_or_get_op; 1869 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 1870 #define ICE_AQC_DRIVER_PARAM_SET 0 1871 #define ICE_AQC_DRIVER_PARAM_GET 1 1872 u8 param_indx; 1873 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 1874 u8 rsvd[2]; 1875 __le32 param_val; 1876 __le32 addr_high; 1877 __le32 addr_low; 1878 }; 1879 1880 enum ice_aqc_driver_params { 1881 /* OS clock index for PTP timer Domain 0 */ 1882 ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0 = 0, 1883 /* OS clock index for PTP timer Domain 1 */ 1884 ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1, 1885 1886 /* Add new parameters above */ 1887 ICE_AQC_DRIVER_PARAM_MAX = 16, 1888 }; 1889 1890 /* Lan Queue Overflow Event (direct, 0x1001) */ 1891 struct ice_aqc_event_lan_overflow { 1892 __le32 prtdcb_ruptq; 1893 __le32 qtx_ctl; 1894 u8 reserved[8]; 1895 }; 1896 1897 /** 1898 * struct ice_aq_desc - Admin Queue (AQ) descriptor 1899 * @flags: ICE_AQ_FLAG_* flags 1900 * @opcode: AQ command opcode 1901 * @datalen: length in bytes of indirect/external data buffer 1902 * @retval: return value from firmware 1903 * @cookie_high: opaque data high-half 1904 * @cookie_low: opaque data low-half 1905 * @params: command-specific parameters 1906 * 1907 * Descriptor format for commands the driver posts on the Admin Transmit Queue 1908 * (ATQ). The firmware writes back onto the command descriptor and returns 1909 * the result of the command. Asynchronous events that are not an immediate 1910 * result of the command are written to the Admin Receive Queue (ARQ) using 1911 * the same descriptor format. Descriptors are in little-endian notation with 1912 * 32-bit words. 1913 */ 1914 struct ice_aq_desc { 1915 __le16 flags; 1916 __le16 opcode; 1917 __le16 datalen; 1918 __le16 retval; 1919 __le32 cookie_high; 1920 __le32 cookie_low; 1921 union { 1922 u8 raw[16]; 1923 struct ice_aqc_generic generic; 1924 struct ice_aqc_get_ver get_ver; 1925 struct ice_aqc_driver_ver driver_ver; 1926 struct ice_aqc_q_shutdown q_shutdown; 1927 struct ice_aqc_req_res res_owner; 1928 struct ice_aqc_manage_mac_read mac_read; 1929 struct ice_aqc_manage_mac_write mac_write; 1930 struct ice_aqc_clear_pxe clear_pxe; 1931 struct ice_aqc_list_caps get_cap; 1932 struct ice_aqc_get_phy_caps get_phy; 1933 struct ice_aqc_set_phy_cfg set_phy; 1934 struct ice_aqc_restart_an restart_an; 1935 struct ice_aqc_sff_eeprom read_write_sff_param; 1936 struct ice_aqc_set_port_id_led set_port_id_led; 1937 struct ice_aqc_get_sw_cfg get_sw_conf; 1938 struct ice_aqc_sw_rules sw_rules; 1939 struct ice_aqc_get_topo get_topo; 1940 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 1941 struct ice_aqc_query_txsched_res query_sched_res; 1942 struct ice_aqc_query_port_ets port_ets; 1943 struct ice_aqc_rl_profile rl_profile; 1944 struct ice_aqc_nvm nvm; 1945 struct ice_aqc_nvm_checksum nvm_checksum; 1946 struct ice_aqc_nvm_pkg_data pkg_data; 1947 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl; 1948 struct ice_aqc_pf_vf_msg virt; 1949 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 1950 struct ice_aqc_lldp_get_mib lldp_get_mib; 1951 struct ice_aqc_lldp_set_mib_change lldp_set_event; 1952 struct ice_aqc_lldp_stop lldp_stop; 1953 struct ice_aqc_lldp_start lldp_start; 1954 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 1955 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 1956 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 1957 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 1958 struct ice_aqc_get_set_rss_key get_set_rss_key; 1959 struct ice_aqc_neigh_dev_req neigh_dev; 1960 struct ice_aqc_add_txqs add_txqs; 1961 struct ice_aqc_dis_txqs dis_txqs; 1962 struct ice_aqc_add_rdma_qset add_rdma_qset; 1963 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 1964 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 1965 struct ice_aqc_fw_logging fw_logging; 1966 struct ice_aqc_get_clear_fw_log get_clear_fw_log; 1967 struct ice_aqc_download_pkg download_pkg; 1968 struct ice_aqc_driver_shared_params drv_shared_params; 1969 struct ice_aqc_set_mac_lb set_mac_lb; 1970 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 1971 struct ice_aqc_set_mac_cfg set_mac_cfg; 1972 struct ice_aqc_set_event_mask set_event_mask; 1973 struct ice_aqc_get_link_status get_link_status; 1974 struct ice_aqc_event_lan_overflow lan_overflow; 1975 struct ice_aqc_get_link_topo get_link_topo; 1976 } params; 1977 }; 1978 1979 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 1980 #define ICE_AQ_LG_BUF 512 1981 1982 #define ICE_AQ_FLAG_ERR_S 2 1983 #define ICE_AQ_FLAG_LB_S 9 1984 #define ICE_AQ_FLAG_RD_S 10 1985 #define ICE_AQ_FLAG_BUF_S 12 1986 #define ICE_AQ_FLAG_SI_S 13 1987 1988 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 1989 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 1990 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 1991 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 1992 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 1993 1994 /* error codes */ 1995 enum ice_aq_err { 1996 ICE_AQ_RC_OK = 0, /* Success */ 1997 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 1998 ICE_AQ_RC_ENOENT = 2, /* No such element */ 1999 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2000 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2001 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2002 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2003 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2004 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2005 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2006 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2007 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2008 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2009 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2010 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2011 }; 2012 2013 /* Admin Queue command opcodes */ 2014 enum ice_adminq_opc { 2015 /* AQ commands */ 2016 ice_aqc_opc_get_ver = 0x0001, 2017 ice_aqc_opc_driver_ver = 0x0002, 2018 ice_aqc_opc_q_shutdown = 0x0003, 2019 2020 /* resource ownership */ 2021 ice_aqc_opc_req_res = 0x0008, 2022 ice_aqc_opc_release_res = 0x0009, 2023 2024 /* device/function capabilities */ 2025 ice_aqc_opc_list_func_caps = 0x000A, 2026 ice_aqc_opc_list_dev_caps = 0x000B, 2027 2028 /* manage MAC address */ 2029 ice_aqc_opc_manage_mac_read = 0x0107, 2030 ice_aqc_opc_manage_mac_write = 0x0108, 2031 2032 /* PXE */ 2033 ice_aqc_opc_clear_pxe_mode = 0x0110, 2034 2035 /* internal switch commands */ 2036 ice_aqc_opc_get_sw_cfg = 0x0200, 2037 2038 /* Alloc/Free/Get Resources */ 2039 ice_aqc_opc_alloc_res = 0x0208, 2040 ice_aqc_opc_free_res = 0x0209, 2041 2042 /* VSI commands */ 2043 ice_aqc_opc_add_vsi = 0x0210, 2044 ice_aqc_opc_update_vsi = 0x0211, 2045 ice_aqc_opc_free_vsi = 0x0213, 2046 2047 /* switch rules population commands */ 2048 ice_aqc_opc_add_sw_rules = 0x02A0, 2049 ice_aqc_opc_update_sw_rules = 0x02A1, 2050 ice_aqc_opc_remove_sw_rules = 0x02A2, 2051 2052 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2053 2054 /* DCB commands */ 2055 ice_aqc_opc_query_pfc_mode = 0x0302, 2056 ice_aqc_opc_set_pfc_mode = 0x0303, 2057 2058 /* transmit scheduler commands */ 2059 ice_aqc_opc_get_dflt_topo = 0x0400, 2060 ice_aqc_opc_add_sched_elems = 0x0401, 2061 ice_aqc_opc_cfg_sched_elems = 0x0403, 2062 ice_aqc_opc_get_sched_elems = 0x0404, 2063 ice_aqc_opc_move_sched_elems = 0x0408, 2064 ice_aqc_opc_suspend_sched_elems = 0x0409, 2065 ice_aqc_opc_resume_sched_elems = 0x040A, 2066 ice_aqc_opc_query_port_ets = 0x040E, 2067 ice_aqc_opc_delete_sched_elems = 0x040F, 2068 ice_aqc_opc_add_rl_profiles = 0x0410, 2069 ice_aqc_opc_query_sched_res = 0x0412, 2070 ice_aqc_opc_remove_rl_profiles = 0x0415, 2071 2072 /* PHY commands */ 2073 ice_aqc_opc_get_phy_caps = 0x0600, 2074 ice_aqc_opc_set_phy_cfg = 0x0601, 2075 ice_aqc_opc_set_mac_cfg = 0x0603, 2076 ice_aqc_opc_restart_an = 0x0605, 2077 ice_aqc_opc_get_link_status = 0x0607, 2078 ice_aqc_opc_set_event_mask = 0x0613, 2079 ice_aqc_opc_set_mac_lb = 0x0620, 2080 ice_aqc_opc_get_link_topo = 0x06E0, 2081 ice_aqc_opc_set_port_id_led = 0x06E9, 2082 ice_aqc_opc_sff_eeprom = 0x06EE, 2083 2084 /* NVM commands */ 2085 ice_aqc_opc_nvm_read = 0x0701, 2086 ice_aqc_opc_nvm_erase = 0x0702, 2087 ice_aqc_opc_nvm_write = 0x0703, 2088 ice_aqc_opc_nvm_checksum = 0x0706, 2089 ice_aqc_opc_nvm_write_activate = 0x0707, 2090 ice_aqc_opc_nvm_update_empr = 0x0709, 2091 ice_aqc_opc_nvm_pkg_data = 0x070A, 2092 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 2093 2094 /* PF/VF mailbox commands */ 2095 ice_mbx_opc_send_msg_to_pf = 0x0801, 2096 ice_mbx_opc_send_msg_to_vf = 0x0802, 2097 /* LLDP commands */ 2098 ice_aqc_opc_lldp_get_mib = 0x0A00, 2099 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2100 ice_aqc_opc_lldp_stop = 0x0A05, 2101 ice_aqc_opc_lldp_start = 0x0A06, 2102 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2103 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2104 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2105 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 2106 2107 /* RSS commands */ 2108 ice_aqc_opc_set_rss_key = 0x0B02, 2109 ice_aqc_opc_set_rss_lut = 0x0B03, 2110 ice_aqc_opc_get_rss_key = 0x0B04, 2111 ice_aqc_opc_get_rss_lut = 0x0B05, 2112 2113 /* Sideband Control Interface commands */ 2114 ice_aqc_opc_neighbour_device_request = 0x0C00, 2115 2116 /* Tx queue handling commands/events */ 2117 ice_aqc_opc_add_txqs = 0x0C30, 2118 ice_aqc_opc_dis_txqs = 0x0C31, 2119 ice_aqc_opc_add_rdma_qset = 0x0C33, 2120 2121 /* package commands */ 2122 ice_aqc_opc_download_pkg = 0x0C40, 2123 ice_aqc_opc_update_pkg = 0x0C42, 2124 ice_aqc_opc_get_pkg_info_list = 0x0C43, 2125 2126 ice_aqc_opc_driver_shared_params = 0x0C90, 2127 2128 /* Standalone Commands/Events */ 2129 ice_aqc_opc_event_lan_overflow = 0x1001, 2130 2131 /* debug commands */ 2132 ice_aqc_opc_fw_logging = 0xFF09, 2133 ice_aqc_opc_fw_logging_info = 0xFF10, 2134 }; 2135 2136 #endif /* _ICE_ADMINQ_CMD_H_ */ 2137