1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 struct ice_aqc_generic { 16 __le32 param0; 17 __le32 param1; 18 __le32 addr_high; 19 __le32 addr_low; 20 }; 21 22 /* Get version (direct 0x0001) */ 23 struct ice_aqc_get_ver { 24 __le32 rom_ver; 25 __le32 fw_build; 26 u8 fw_branch; 27 u8 fw_major; 28 u8 fw_minor; 29 u8 fw_patch; 30 u8 api_branch; 31 u8 api_major; 32 u8 api_minor; 33 u8 api_patch; 34 }; 35 36 /* Queue Shutdown (direct 0x0003) */ 37 struct ice_aqc_q_shutdown { 38 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 39 __le32 driver_unloading; 40 u8 reserved[12]; 41 }; 42 43 /* Request resource ownership (direct 0x0008) 44 * Release resource ownership (direct 0x0009) 45 */ 46 struct ice_aqc_req_res { 47 __le16 res_id; 48 #define ICE_AQC_RES_ID_NVM 1 49 #define ICE_AQC_RES_ID_SDP 2 50 #define ICE_AQC_RES_ID_CHNG_LOCK 3 51 #define ICE_AQC_RES_ID_GLBL_LOCK 4 52 __le16 access_type; 53 #define ICE_AQC_RES_ACCESS_READ 1 54 #define ICE_AQC_RES_ACCESS_WRITE 2 55 56 /* Upon successful completion, FW writes this value and driver is 57 * expected to release resource before timeout. This value is provided 58 * in milliseconds. 59 */ 60 __le32 timeout; 61 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 62 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 63 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 64 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 65 /* For SDP: pin id of the SDP */ 66 __le32 res_number; 67 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 68 __le16 status; 69 #define ICE_AQ_RES_GLBL_SUCCESS 0 70 #define ICE_AQ_RES_GLBL_IN_PROG 1 71 #define ICE_AQ_RES_GLBL_DONE 2 72 u8 reserved[2]; 73 }; 74 75 /* Get function capabilities (indirect 0x000A) 76 * Get device capabilities (indirect 0x000B) 77 */ 78 struct ice_aqc_list_caps { 79 u8 cmd_flags; 80 u8 pf_index; 81 u8 reserved[2]; 82 __le32 count; 83 __le32 addr_high; 84 __le32 addr_low; 85 }; 86 87 /* Device/Function buffer entry, repeated per reported capability */ 88 struct ice_aqc_list_caps_elem { 89 __le16 cap; 90 #define ICE_AQC_CAPS_VSI 0x0017 91 #define ICE_AQC_CAPS_RSS 0x0040 92 #define ICE_AQC_CAPS_RXQS 0x0041 93 #define ICE_AQC_CAPS_TXQS 0x0042 94 #define ICE_AQC_CAPS_MSIX 0x0043 95 #define ICE_AQC_CAPS_MAX_MTU 0x0047 96 97 u8 major_ver; 98 u8 minor_ver; 99 /* Number of resources described by this capability */ 100 __le32 number; 101 /* Only meaningful for some types of resources */ 102 __le32 logical_id; 103 /* Only meaningful for some types of resources */ 104 __le32 phys_id; 105 __le64 rsvd1; 106 __le64 rsvd2; 107 }; 108 109 /* Manage MAC address, read command - indirect (0x0107) 110 * This struct is also used for the response 111 */ 112 struct ice_aqc_manage_mac_read { 113 __le16 flags; /* Zeroed by device driver */ 114 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 115 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 116 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 117 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 118 #define ICE_AQC_MAN_MAC_READ_S 4 119 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 120 u8 lport_num; 121 u8 lport_num_valid; 122 #define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID BIT(0) 123 u8 num_addr; /* Used in response */ 124 u8 reserved[3]; 125 __le32 addr_high; 126 __le32 addr_low; 127 }; 128 129 /* Response buffer format for manage MAC read command */ 130 struct ice_aqc_manage_mac_read_resp { 131 u8 lport_num; 132 u8 addr_type; 133 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 134 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 135 u8 mac_addr[ETH_ALEN]; 136 }; 137 138 /* Manage MAC address, write command - direct (0x0108) */ 139 struct ice_aqc_manage_mac_write { 140 u8 port_num; 141 u8 flags; 142 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 143 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 144 #define ICE_AQC_MAN_MAC_WR_S 6 145 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S) 146 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 147 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S) 148 /* High 16 bits of MAC address in big endian order */ 149 __be16 sah; 150 /* Low 32 bits of MAC address in big endian order */ 151 __be32 sal; 152 __le32 addr_high; 153 __le32 addr_low; 154 }; 155 156 /* Clear PXE Command and response (direct 0x0110) */ 157 struct ice_aqc_clear_pxe { 158 u8 rx_cnt; 159 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 160 u8 reserved[15]; 161 }; 162 163 /* Get switch configuration (0x0200) */ 164 struct ice_aqc_get_sw_cfg { 165 /* Reserved for command and copy of request flags for response */ 166 __le16 flags; 167 /* First desc in case of command and next_elem in case of response 168 * In case of response, if it is not zero, means all the configuration 169 * was not returned and new command shall be sent with this value in 170 * the 'first desc' field 171 */ 172 __le16 element; 173 /* Reserved for command, only used for response */ 174 __le16 num_elems; 175 __le16 rsvd; 176 __le32 addr_high; 177 __le32 addr_low; 178 }; 179 180 /* Each entry in the response buffer is of the following type: */ 181 struct ice_aqc_get_sw_cfg_resp_elem { 182 /* VSI/Port Number */ 183 __le16 vsi_port_num; 184 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 185 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 186 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 187 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 188 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 189 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 190 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 191 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 192 193 /* SWID VSI/Port belongs to */ 194 __le16 swid; 195 196 /* Bit 14..0 : PF/VF number VSI belongs to 197 * Bit 15 : VF indication bit 198 */ 199 __le16 pf_vf_num; 200 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 201 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 202 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 203 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 204 }; 205 206 /* The response buffer is as follows. Note that the length of the 207 * elements array varies with the length of the command response. 208 */ 209 struct ice_aqc_get_sw_cfg_resp { 210 struct ice_aqc_get_sw_cfg_resp_elem elements[1]; 211 }; 212 213 /* These resource type defines are used for all switch resource 214 * commands where a resource type is required, such as: 215 * Get Resource Allocation command (indirect 0x0204) 216 * Allocate Resources command (indirect 0x0208) 217 * Free Resources command (indirect 0x0209) 218 * Get Allocated Resource Descriptors Command (indirect 0x020A) 219 */ 220 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 221 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 222 223 /* Allocate Resources command (indirect 0x0208) 224 * Free Resources command (indirect 0x0209) 225 */ 226 struct ice_aqc_alloc_free_res_cmd { 227 __le16 num_entries; /* Number of Resource entries */ 228 u8 reserved[6]; 229 __le32 addr_high; 230 __le32 addr_low; 231 }; 232 233 /* Resource descriptor */ 234 struct ice_aqc_res_elem { 235 union { 236 __le16 sw_resp; 237 __le16 flu_resp; 238 } e; 239 }; 240 241 /* Buffer for Allocate/Free Resources commands */ 242 struct ice_aqc_alloc_free_res_elem { 243 __le16 res_type; /* Types defined above cmd 0x0204 */ 244 #define ICE_AQC_RES_TYPE_SHARED_S 7 245 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 246 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 247 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 248 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 249 __le16 num_elems; 250 struct ice_aqc_res_elem elem[1]; 251 }; 252 253 /* Add VSI (indirect 0x0210) 254 * Update VSI (indirect 0x0211) 255 * Get VSI (indirect 0x0212) 256 * Free VSI (indirect 0x0213) 257 */ 258 struct ice_aqc_add_get_update_free_vsi { 259 __le16 vsi_num; 260 #define ICE_AQ_VSI_NUM_S 0 261 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 262 #define ICE_AQ_VSI_IS_VALID BIT(15) 263 __le16 cmd_flags; 264 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 265 u8 vf_id; 266 u8 reserved; 267 __le16 vsi_flags; 268 #define ICE_AQ_VSI_TYPE_S 0 269 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 270 #define ICE_AQ_VSI_TYPE_VF 0x0 271 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 272 #define ICE_AQ_VSI_TYPE_PF 0x2 273 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 274 __le32 addr_high; 275 __le32 addr_low; 276 }; 277 278 /* Response descriptor for: 279 * Add VSI (indirect 0x0210) 280 * Update VSI (indirect 0x0211) 281 * Free VSI (indirect 0x0213) 282 */ 283 struct ice_aqc_add_update_free_vsi_resp { 284 __le16 vsi_num; 285 __le16 ext_status; 286 __le16 vsi_used; 287 __le16 vsi_free; 288 __le32 addr_high; 289 __le32 addr_low; 290 }; 291 292 struct ice_aqc_vsi_props { 293 __le16 valid_sections; 294 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 295 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 296 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 297 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 298 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 299 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 300 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 301 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 302 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 303 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 304 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 305 /* switch section */ 306 u8 sw_id; 307 u8 sw_flags; 308 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 309 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 310 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 311 u8 sw_flags2; 312 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 313 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 314 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 315 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 316 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 317 u8 veb_stat_id; 318 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 319 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 320 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 321 /* security section */ 322 u8 sec_flags; 323 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 324 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 325 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 326 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 327 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 328 u8 sec_reserved; 329 /* VLAN section */ 330 __le16 pvid; /* VLANS include priority bits */ 331 u8 pvlan_reserved[2]; 332 u8 port_vlan_flags; 333 #define ICE_AQ_VSI_PVLAN_MODE_S 0 334 #define ICE_AQ_VSI_PVLAN_MODE_M (0x3 << ICE_AQ_VSI_PVLAN_MODE_S) 335 #define ICE_AQ_VSI_PVLAN_MODE_UNTAGGED 0x1 336 #define ICE_AQ_VSI_PVLAN_MODE_TAGGED 0x2 337 #define ICE_AQ_VSI_PVLAN_MODE_ALL 0x3 338 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 339 #define ICE_AQ_VSI_PVLAN_EMOD_S 3 340 #define ICE_AQ_VSI_PVLAN_EMOD_M (0x3 << ICE_AQ_VSI_PVLAN_EMOD_S) 341 #define ICE_AQ_VSI_PVLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_PVLAN_EMOD_S) 342 #define ICE_AQ_VSI_PVLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_PVLAN_EMOD_S) 343 #define ICE_AQ_VSI_PVLAN_EMOD_STR (0x2 << ICE_AQ_VSI_PVLAN_EMOD_S) 344 #define ICE_AQ_VSI_PVLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_PVLAN_EMOD_S) 345 u8 pvlan_reserved2[3]; 346 /* ingress egress up sections */ 347 __le32 ingress_table; /* bitmap, 3 bits per up */ 348 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 349 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 350 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 351 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 352 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 353 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 354 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 355 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 356 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 357 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 358 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 359 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 360 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 361 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 362 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 363 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 364 __le32 egress_table; /* same defines as for ingress table */ 365 /* outer tags section */ 366 __le16 outer_tag; 367 u8 outer_tag_flags; 368 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 369 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 370 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 371 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 372 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 373 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 374 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 375 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 376 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 377 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 378 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 379 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 380 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 381 u8 outer_tag_reserved; 382 /* queue mapping section */ 383 __le16 mapping_flags; 384 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 385 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 386 __le16 q_mapping[16]; 387 #define ICE_AQ_VSI_Q_S 0 388 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 389 __le16 tc_mapping[8]; 390 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 391 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 392 #define ICE_AQ_VSI_TC_Q_NUM_S 11 393 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 394 /* queueing option section */ 395 u8 q_opt_rss; 396 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 397 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 398 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 399 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 400 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 401 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 402 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 403 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 404 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 405 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 406 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 407 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 408 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 409 u8 q_opt_tc; 410 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 411 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 412 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 413 u8 q_opt_flags; 414 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 415 u8 q_opt_reserved[3]; 416 /* outer up section */ 417 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 418 /* section 10 */ 419 __le16 sect_10_reserved; 420 /* flow director section */ 421 __le16 fd_options; 422 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 423 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 424 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 425 __le16 max_fd_fltr_dedicated; 426 __le16 max_fd_fltr_shared; 427 __le16 fd_def_q; 428 #define ICE_AQ_VSI_FD_DEF_Q_S 0 429 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 430 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 431 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 432 __le16 fd_report_opt; 433 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 434 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 435 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 436 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 437 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 438 /* PASID section */ 439 __le32 pasid_id; 440 #define ICE_AQ_VSI_PASID_ID_S 0 441 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 442 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 443 u8 reserved[24]; 444 }; 445 446 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 447 */ 448 struct ice_aqc_sw_rules { 449 /* ops: add switch rules, referring the number of rules. 450 * ops: update switch rules, referring the number of filters 451 * ops: remove switch rules, referring the entry index. 452 * ops: get switch rules, referring to the number of filters. 453 */ 454 __le16 num_rules_fltr_entry_index; 455 u8 reserved[6]; 456 __le32 addr_high; 457 __le32 addr_low; 458 }; 459 460 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 461 * This structures describes the lookup rules and associated actions. "index" 462 * is returned as part of a response to a successful Add command, and can be 463 * used to identify the rule for Update/Get/Remove commands. 464 */ 465 struct ice_sw_rule_lkup_rx_tx { 466 __le16 recipe_id; 467 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 468 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 469 __le16 src; 470 __le32 act; 471 472 /* Bit 0:1 - Action type */ 473 #define ICE_SINGLE_ACT_TYPE_S 0x00 474 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 475 476 /* Bit 2 - Loop back enable 477 * Bit 3 - LAN enable 478 */ 479 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 480 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 481 482 /* Action type = 0 - Forward to VSI or VSI list */ 483 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 484 485 #define ICE_SINGLE_ACT_VSI_ID_S 4 486 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 487 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 488 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 489 /* This bit needs to be set if action is forward to VSI list */ 490 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 491 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 492 #define ICE_SINGLE_ACT_DROP BIT(18) 493 494 /* Action type = 1 - Forward to Queue of Queue group */ 495 #define ICE_SINGLE_ACT_TO_Q 0x1 496 #define ICE_SINGLE_ACT_Q_INDEX_S 4 497 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 498 #define ICE_SINGLE_ACT_Q_REGION_S 15 499 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 500 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 501 502 /* Action type = 2 - Prune */ 503 #define ICE_SINGLE_ACT_PRUNE 0x2 504 #define ICE_SINGLE_ACT_EGRESS BIT(15) 505 #define ICE_SINGLE_ACT_INGRESS BIT(16) 506 #define ICE_SINGLE_ACT_PRUNET BIT(17) 507 /* Bit 18 should be set to 0 for this action */ 508 509 /* Action type = 2 - Pointer */ 510 #define ICE_SINGLE_ACT_PTR 0x2 511 #define ICE_SINGLE_ACT_PTR_VAL_S 4 512 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 513 /* Bit 18 should be set to 1 */ 514 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 515 516 /* Action type = 3 - Other actions. Last two bits 517 * are other action identifier 518 */ 519 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 520 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 521 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 522 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 523 524 /* Bit 17:18 - Defines other actions */ 525 /* Other action = 0 - Mirror VSI */ 526 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 527 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 528 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 529 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 530 531 /* Other action = 3 - Set Stat count */ 532 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 533 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 534 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 535 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 536 537 __le16 index; /* The index of the rule in the lookup table */ 538 /* Length and values of the header to be matched per recipe or 539 * lookup-type 540 */ 541 __le16 hdr_len; 542 u8 hdr[1]; 543 } __packed; 544 545 /* Add/Update/Remove large action command/response entry 546 * "index" is returned as part of a response to a successful Add command, and 547 * can be used to identify the action for Update/Get/Remove commands. 548 */ 549 struct ice_sw_rule_lg_act { 550 __le16 index; /* Index in large action table */ 551 __le16 size; 552 __le32 act[1]; /* array of size for actions */ 553 /* Max number of large actions */ 554 #define ICE_MAX_LG_ACT 4 555 /* Bit 0:1 - Action type */ 556 #define ICE_LG_ACT_TYPE_S 0 557 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 558 559 /* Action type = 0 - Forward to VSI or VSI list */ 560 #define ICE_LG_ACT_VSI_FORWARDING 0 561 #define ICE_LG_ACT_VSI_ID_S 3 562 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 563 #define ICE_LG_ACT_VSI_LIST_ID_S 3 564 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 565 /* This bit needs to be set if action is forward to VSI list */ 566 #define ICE_LG_ACT_VSI_LIST BIT(13) 567 568 #define ICE_LG_ACT_VALID_BIT BIT(16) 569 570 /* Action type = 1 - Forward to Queue of Queue group */ 571 #define ICE_LG_ACT_TO_Q 0x1 572 #define ICE_LG_ACT_Q_INDEX_S 3 573 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 574 #define ICE_LG_ACT_Q_REGION_S 14 575 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 576 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 577 578 /* Action type = 2 - Prune */ 579 #define ICE_LG_ACT_PRUNE 0x2 580 #define ICE_LG_ACT_EGRESS BIT(14) 581 #define ICE_LG_ACT_INGRESS BIT(15) 582 #define ICE_LG_ACT_PRUNET BIT(16) 583 584 /* Action type = 3 - Mirror VSI */ 585 #define ICE_LG_OTHER_ACT_MIRROR 0x3 586 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 587 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 588 589 /* Action type = 5 - Generic Value */ 590 #define ICE_LG_ACT_GENERIC 0x5 591 #define ICE_LG_ACT_GENERIC_VALUE_S 3 592 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 593 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 594 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 595 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 596 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 597 598 /* Action = 7 - Set Stat count */ 599 #define ICE_LG_ACT_STAT_COUNT 0x7 600 #define ICE_LG_ACT_STAT_COUNT_S 3 601 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 602 }; 603 604 /* Add/Update/Remove VSI list command/response entry 605 * "index" is returned as part of a response to a successful Add command, and 606 * can be used to identify the VSI list for Update/Get/Remove commands. 607 */ 608 struct ice_sw_rule_vsi_list { 609 __le16 index; /* Index of VSI/Prune list */ 610 __le16 number_vsi; 611 __le16 vsi[1]; /* Array of number_vsi VSI numbers */ 612 }; 613 614 /* Query VSI list command/response entry */ 615 struct ice_sw_rule_vsi_list_query { 616 __le16 index; 617 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI); 618 } __packed; 619 620 /* Add switch rule response: 621 * Content of return buffer is same as the input buffer. The status field and 622 * LUT index are updated as part of the response 623 */ 624 struct ice_aqc_sw_rules_elem { 625 __le16 type; /* Switch rule type, one of T_... */ 626 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 627 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 628 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 629 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 630 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 631 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 632 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 633 __le16 status; 634 union { 635 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 636 struct ice_sw_rule_lg_act lg_act; 637 struct ice_sw_rule_vsi_list vsi_list; 638 struct ice_sw_rule_vsi_list_query vsi_list_query; 639 } __packed pdata; 640 }; 641 642 /* Get Default Topology (indirect 0x0400) */ 643 struct ice_aqc_get_topo { 644 u8 port_num; 645 u8 num_branches; 646 __le16 reserved1; 647 __le32 reserved2; 648 __le32 addr_high; 649 __le32 addr_low; 650 }; 651 652 /* Update TSE (indirect 0x0403) 653 * Get TSE (indirect 0x0404) 654 */ 655 struct ice_aqc_get_cfg_elem { 656 __le16 num_elem_req; /* Used by commands */ 657 __le16 num_elem_resp; /* Used by responses */ 658 __le32 reserved; 659 __le32 addr_high; 660 __le32 addr_low; 661 }; 662 663 /* This is the buffer for: 664 * Suspend Nodes (indirect 0x0409) 665 * Resume Nodes (indirect 0x040A) 666 */ 667 struct ice_aqc_suspend_resume_elem { 668 __le32 teid[1]; 669 }; 670 671 /* Add TSE (indirect 0x0401) 672 * Delete TSE (indirect 0x040F) 673 * Move TSE (indirect 0x0408) 674 */ 675 struct ice_aqc_add_move_delete_elem { 676 __le16 num_grps_req; 677 __le16 num_grps_updated; 678 __le32 reserved; 679 __le32 addr_high; 680 __le32 addr_low; 681 }; 682 683 struct ice_aqc_elem_info_bw { 684 __le16 bw_profile_idx; 685 __le16 bw_alloc; 686 }; 687 688 struct ice_aqc_txsched_elem { 689 u8 elem_type; /* Special field, reserved for some aq calls */ 690 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 691 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 692 #define ICE_AQC_ELEM_TYPE_TC 0x2 693 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 694 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 695 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 696 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 697 u8 valid_sections; 698 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 699 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 700 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 701 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 702 u8 generic; 703 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 704 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 705 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 706 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 707 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 708 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 709 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 710 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 711 u8 flags; /* Special field, reserved for some aq calls */ 712 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 713 struct ice_aqc_elem_info_bw cir_bw; 714 struct ice_aqc_elem_info_bw eir_bw; 715 __le16 srl_id; 716 __le16 reserved2; 717 }; 718 719 struct ice_aqc_txsched_elem_data { 720 __le32 parent_teid; 721 __le32 node_teid; 722 struct ice_aqc_txsched_elem data; 723 }; 724 725 struct ice_aqc_txsched_topo_grp_info_hdr { 726 __le32 parent_teid; 727 __le16 num_elems; 728 __le16 reserved2; 729 }; 730 731 struct ice_aqc_add_elem { 732 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 733 struct ice_aqc_txsched_elem_data generic[1]; 734 }; 735 736 struct ice_aqc_get_topo_elem { 737 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 738 struct ice_aqc_txsched_elem_data 739 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 740 }; 741 742 struct ice_aqc_delete_elem { 743 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 744 __le32 teid[1]; 745 }; 746 747 /* Query Scheduler Resource Allocation (indirect 0x0412) 748 * This indirect command retrieves the scheduler resources allocated by 749 * EMP Firmware to the given PF. 750 */ 751 struct ice_aqc_query_txsched_res { 752 u8 reserved[8]; 753 __le32 addr_high; 754 __le32 addr_low; 755 }; 756 757 struct ice_aqc_generic_sched_props { 758 __le16 phys_levels; 759 __le16 logical_levels; 760 u8 flattening_bitmap; 761 u8 max_device_cgds; 762 u8 max_pf_cgds; 763 u8 rsvd0; 764 __le16 rdma_qsets; 765 u8 rsvd1[22]; 766 }; 767 768 struct ice_aqc_layer_props { 769 u8 logical_layer; 770 u8 chunk_size; 771 __le16 max_device_nodes; 772 __le16 max_pf_nodes; 773 u8 rsvd0[2]; 774 __le16 max_shared_rate_lmtr; 775 __le16 max_children; 776 __le16 max_cir_rl_profiles; 777 __le16 max_eir_rl_profiles; 778 __le16 max_srl_profiles; 779 u8 rsvd1[14]; 780 }; 781 782 struct ice_aqc_query_txsched_res_resp { 783 struct ice_aqc_generic_sched_props sched_props; 784 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 785 }; 786 787 /* Get PHY capabilities (indirect 0x0600) */ 788 struct ice_aqc_get_phy_caps { 789 u8 lport_num; 790 u8 reserved; 791 __le16 param0; 792 /* 18.0 - Report qualified modules */ 793 #define ICE_AQC_GET_PHY_RQM BIT(0) 794 /* 18.1 - 18.2 : Report mode 795 * 00b - Report NVM capabilities 796 * 01b - Report topology capabilities 797 * 10b - Report SW configured 798 */ 799 #define ICE_AQC_REPORT_MODE_S 1 800 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 801 #define ICE_AQC_REPORT_NVM_CAP 0 802 #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 803 #define ICE_AQC_REPORT_SW_CFG BIT(2) 804 __le32 reserved1; 805 __le32 addr_high; 806 __le32 addr_low; 807 }; 808 809 /* This is #define of PHY type (Extended): 810 * The first set of defines is for phy_type_low. 811 */ 812 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 813 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 814 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 815 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 816 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 817 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 818 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 819 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 820 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 821 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 822 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 823 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 824 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 825 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 826 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 827 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 828 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 829 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 830 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 831 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 832 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 833 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 834 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 835 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 836 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 837 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 838 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 839 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 840 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 841 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 842 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 843 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 844 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 845 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 846 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 847 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 848 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 849 850 struct ice_aqc_get_phy_caps_data { 851 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 852 __le64 reserved; 853 u8 caps; 854 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 855 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 856 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 857 #define ICE_AQC_PHY_EN_LINK BIT(3) 858 #define ICE_AQC_PHY_AN_MODE BIT(4) 859 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 860 u8 low_power_ctrl; 861 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 862 __le16 eee_cap; 863 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 864 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 865 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 866 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 867 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 868 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 869 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 870 __le16 eeer_value; 871 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 872 u8 link_fec_options; 873 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 874 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 875 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 876 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 877 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 878 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 879 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 880 u8 extended_compliance_code; 881 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 882 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 883 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 884 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 885 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 886 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 887 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 888 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 889 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 890 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 891 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 892 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 893 u8 qualified_module_count; 894 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 895 struct { 896 u8 v_oui[3]; 897 u8 rsvd1; 898 u8 v_part[16]; 899 __le32 v_rev; 900 __le64 rsvd8; 901 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 902 }; 903 904 /* Set PHY capabilities (direct 0x0601) 905 * NOTE: This command must be followed by setup link and restart auto-neg 906 */ 907 struct ice_aqc_set_phy_cfg { 908 u8 lport_num; 909 u8 reserved[7]; 910 __le32 addr_high; 911 __le32 addr_low; 912 }; 913 914 /* Set PHY config command data structure */ 915 struct ice_aqc_set_phy_cfg_data { 916 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 917 __le64 rsvd0; 918 u8 caps; 919 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 920 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 921 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 922 #define ICE_AQ_PHY_ENA_LINK BIT(3) 923 #define ICE_AQ_PHY_ENA_ATOMIC_LINK BIT(5) 924 u8 low_power_ctrl; 925 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 926 __le16 eeer_value; 927 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 928 u8 rsvd1; 929 }; 930 931 /* Restart AN command data structure (direct 0x0605) 932 * Also used for response, with only the lport_num field present. 933 */ 934 struct ice_aqc_restart_an { 935 u8 lport_num; 936 u8 reserved; 937 u8 cmd_flags; 938 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 939 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 940 u8 reserved2[13]; 941 }; 942 943 /* Get link status (indirect 0x0607), also used for Link Status Event */ 944 struct ice_aqc_get_link_status { 945 u8 lport_num; 946 u8 reserved; 947 __le16 cmd_flags; 948 #define ICE_AQ_LSE_M 0x3 949 #define ICE_AQ_LSE_NOP 0x0 950 #define ICE_AQ_LSE_DIS 0x2 951 #define ICE_AQ_LSE_ENA 0x3 952 /* only response uses this flag */ 953 #define ICE_AQ_LSE_IS_ENABLED 0x1 954 __le32 reserved2; 955 __le32 addr_high; 956 __le32 addr_low; 957 }; 958 959 /* Get link status response data structure, also used for Link Status Event */ 960 struct ice_aqc_get_link_status_data { 961 u8 topo_media_conflict; 962 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 963 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 964 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 965 u8 reserved1; 966 u8 link_info; 967 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 968 #define ICE_AQ_LINK_FAULT BIT(1) 969 #define ICE_AQ_LINK_FAULT_TX BIT(2) 970 #define ICE_AQ_LINK_FAULT_RX BIT(3) 971 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 972 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 973 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 974 #define ICE_AQ_SIGNAL_DETECT BIT(7) 975 u8 an_info; 976 #define ICE_AQ_AN_COMPLETED BIT(0) 977 #define ICE_AQ_LP_AN_ABILITY BIT(1) 978 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 979 #define ICE_AQ_FEC_EN BIT(3) 980 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 981 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 982 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 983 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 984 u8 ext_info; 985 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 986 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 987 /* Port TX Suspended */ 988 #define ICE_AQ_LINK_TX_S 2 989 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 990 #define ICE_AQ_LINK_TX_ACTIVE 0 991 #define ICE_AQ_LINK_TX_DRAINED 1 992 #define ICE_AQ_LINK_TX_FLUSHED 3 993 u8 reserved2; 994 __le16 max_frame_size; 995 u8 cfg; 996 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 997 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 998 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 999 /* Pacing Config */ 1000 #define ICE_AQ_CFG_PACING_S 3 1001 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1002 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1003 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1004 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1005 /* External Device Power Ability */ 1006 u8 power_desc; 1007 #define ICE_AQ_PWR_CLASS_M 0x3 1008 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1009 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1010 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1011 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1012 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1013 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1014 __le16 link_speed; 1015 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1016 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1017 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1018 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1019 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1020 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1021 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1022 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1023 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1024 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1025 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1026 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1027 __le64 reserved4; 1028 }; 1029 1030 /* Set event mask command (direct 0x0613) */ 1031 struct ice_aqc_set_event_mask { 1032 u8 lport_num; 1033 u8 reserved[7]; 1034 __le16 event_mask; 1035 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1036 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1037 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1038 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1039 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1040 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1041 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1042 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1043 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1044 u8 reserved1[6]; 1045 }; 1046 1047 /* NVM Read command (indirect 0x0701) 1048 * NVM Erase commands (direct 0x0702) 1049 * NVM Update commands (indirect 0x0703) 1050 */ 1051 struct ice_aqc_nvm { 1052 __le16 offset_low; 1053 u8 offset_high; 1054 u8 cmd_flags; 1055 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1056 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1057 #define ICE_AQC_NVM_PRESERVATION_S 1 1058 #define ICE_AQC_NVM_PRESERVATION_M (3 << CSR_AQ_NVM_PRESERVATION_S) 1059 #define ICE_AQC_NVM_NO_PRESERVATION (0 << CSR_AQ_NVM_PRESERVATION_S) 1060 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1061 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << CSR_AQ_NVM_PRESERVATION_S) 1062 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1063 __le16 module_typeid; 1064 __le16 length; 1065 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1066 __le32 addr_high; 1067 __le32 addr_low; 1068 }; 1069 1070 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1071 struct ice_aqc_get_set_rss_key { 1072 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1073 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1074 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1075 __le16 vsi_id; 1076 u8 reserved[6]; 1077 __le32 addr_high; 1078 __le32 addr_low; 1079 }; 1080 1081 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1082 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1083 1084 struct ice_aqc_get_set_rss_keys { 1085 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1086 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1087 }; 1088 1089 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1090 struct ice_aqc_get_set_rss_lut { 1091 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1092 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1093 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1094 __le16 vsi_id; 1095 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1096 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1097 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1098 1099 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1100 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1101 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1102 1103 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1104 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1105 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1106 1107 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1108 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1109 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1110 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1111 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1112 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1113 1114 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1115 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1116 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1117 1118 __le16 flags; 1119 __le32 reserved; 1120 __le32 addr_high; 1121 __le32 addr_low; 1122 }; 1123 1124 /* Add TX LAN Queues (indirect 0x0C30) */ 1125 struct ice_aqc_add_txqs { 1126 u8 num_qgrps; 1127 u8 reserved[3]; 1128 __le32 reserved1; 1129 __le32 addr_high; 1130 __le32 addr_low; 1131 }; 1132 1133 /* This is the descriptor of each queue entry for the Add TX LAN Queues 1134 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1135 */ 1136 struct ice_aqc_add_txqs_perq { 1137 __le16 txq_id; 1138 u8 rsvd[2]; 1139 __le32 q_teid; 1140 u8 txq_ctx[22]; 1141 u8 rsvd2[2]; 1142 struct ice_aqc_txsched_elem info; 1143 }; 1144 1145 /* The format of the command buffer for Add TX LAN Queues (0x0C30) 1146 * is an array of the following structs. Please note that the length of 1147 * each struct ice_aqc_add_tx_qgrp is variable due 1148 * to the variable number of queues in each group! 1149 */ 1150 struct ice_aqc_add_tx_qgrp { 1151 __le32 parent_teid; 1152 u8 num_txqs; 1153 u8 rsvd[3]; 1154 struct ice_aqc_add_txqs_perq txqs[1]; 1155 }; 1156 1157 /* Disable TX LAN Queues (indirect 0x0C31) */ 1158 struct ice_aqc_dis_txqs { 1159 u8 cmd_type; 1160 #define ICE_AQC_Q_DIS_CMD_S 0 1161 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1162 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1163 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1164 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1165 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1166 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1167 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1168 u8 num_entries; 1169 __le16 vmvf_and_timeout; 1170 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1171 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1172 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1173 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1174 __le32 blocked_cgds; 1175 __le32 addr_high; 1176 __le32 addr_low; 1177 }; 1178 1179 /* The buffer for Disable TX LAN Queues (indirect 0x0C31) 1180 * contains the following structures, arrayed one after the 1181 * other. 1182 * Note: Since the q_id is 16 bits wide, if the 1183 * number of queues is even, then 2 bytes of alignment MUST be 1184 * added before the start of the next group, to allow correct 1185 * alignment of the parent_teid field. 1186 */ 1187 struct ice_aqc_dis_txq_item { 1188 __le32 parent_teid; 1189 u8 num_qs; 1190 u8 rsvd; 1191 /* The length of the q_id array varies according to num_qs */ 1192 __le16 q_id[1]; 1193 /* This only applies from F8 onward */ 1194 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1195 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1196 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1197 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1198 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1199 }; 1200 1201 struct ice_aqc_dis_txq { 1202 struct ice_aqc_dis_txq_item qgrps[1]; 1203 }; 1204 1205 /** 1206 * struct ice_aq_desc - Admin Queue (AQ) descriptor 1207 * @flags: ICE_AQ_FLAG_* flags 1208 * @opcode: AQ command opcode 1209 * @datalen: length in bytes of indirect/external data buffer 1210 * @retval: return value from firmware 1211 * @cookie_h: opaque data high-half 1212 * @cookie_l: opaque data low-half 1213 * @params: command-specific parameters 1214 * 1215 * Descriptor format for commands the driver posts on the Admin Transmit Queue 1216 * (ATQ). The firmware writes back onto the command descriptor and returns 1217 * the result of the command. Asynchronous events that are not an immediate 1218 * result of the command are written to the Admin Receive Queue (ARQ) using 1219 * the same descriptor format. Descriptors are in little-endian notation with 1220 * 32-bit words. 1221 */ 1222 struct ice_aq_desc { 1223 __le16 flags; 1224 __le16 opcode; 1225 __le16 datalen; 1226 __le16 retval; 1227 __le32 cookie_high; 1228 __le32 cookie_low; 1229 union { 1230 u8 raw[16]; 1231 struct ice_aqc_generic generic; 1232 struct ice_aqc_get_ver get_ver; 1233 struct ice_aqc_q_shutdown q_shutdown; 1234 struct ice_aqc_req_res res_owner; 1235 struct ice_aqc_manage_mac_read mac_read; 1236 struct ice_aqc_manage_mac_write mac_write; 1237 struct ice_aqc_clear_pxe clear_pxe; 1238 struct ice_aqc_list_caps get_cap; 1239 struct ice_aqc_get_phy_caps get_phy; 1240 struct ice_aqc_set_phy_cfg set_phy; 1241 struct ice_aqc_restart_an restart_an; 1242 struct ice_aqc_get_sw_cfg get_sw_conf; 1243 struct ice_aqc_sw_rules sw_rules; 1244 struct ice_aqc_get_topo get_topo; 1245 struct ice_aqc_get_cfg_elem get_update_elem; 1246 struct ice_aqc_query_txsched_res query_sched_res; 1247 struct ice_aqc_add_move_delete_elem add_move_delete_elem; 1248 struct ice_aqc_nvm nvm; 1249 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 1250 struct ice_aqc_get_set_rss_key get_set_rss_key; 1251 struct ice_aqc_add_txqs add_txqs; 1252 struct ice_aqc_dis_txqs dis_txqs; 1253 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 1254 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 1255 struct ice_aqc_set_event_mask set_event_mask; 1256 struct ice_aqc_get_link_status get_link_status; 1257 } params; 1258 }; 1259 1260 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 1261 #define ICE_AQ_LG_BUF 512 1262 1263 #define ICE_AQ_FLAG_ERR_S 2 1264 #define ICE_AQ_FLAG_LB_S 9 1265 #define ICE_AQ_FLAG_RD_S 10 1266 #define ICE_AQ_FLAG_BUF_S 12 1267 #define ICE_AQ_FLAG_SI_S 13 1268 1269 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 1270 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 1271 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 1272 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 1273 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 1274 1275 /* error codes */ 1276 enum ice_aq_err { 1277 ICE_AQ_RC_OK = 0, /* success */ 1278 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 1279 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1280 ICE_AQ_RC_EEXIST = 13, /* object already exists */ 1281 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 1282 }; 1283 1284 /* Admin Queue command opcodes */ 1285 enum ice_adminq_opc { 1286 /* AQ commands */ 1287 ice_aqc_opc_get_ver = 0x0001, 1288 ice_aqc_opc_q_shutdown = 0x0003, 1289 1290 /* resource ownership */ 1291 ice_aqc_opc_req_res = 0x0008, 1292 ice_aqc_opc_release_res = 0x0009, 1293 1294 /* device/function capabilities */ 1295 ice_aqc_opc_list_func_caps = 0x000A, 1296 ice_aqc_opc_list_dev_caps = 0x000B, 1297 1298 /* manage MAC address */ 1299 ice_aqc_opc_manage_mac_read = 0x0107, 1300 ice_aqc_opc_manage_mac_write = 0x0108, 1301 1302 /* PXE */ 1303 ice_aqc_opc_clear_pxe_mode = 0x0110, 1304 1305 /* internal switch commands */ 1306 ice_aqc_opc_get_sw_cfg = 0x0200, 1307 1308 /* Alloc/Free/Get Resources */ 1309 ice_aqc_opc_alloc_res = 0x0208, 1310 ice_aqc_opc_free_res = 0x0209, 1311 1312 /* VSI commands */ 1313 ice_aqc_opc_add_vsi = 0x0210, 1314 ice_aqc_opc_update_vsi = 0x0211, 1315 ice_aqc_opc_free_vsi = 0x0213, 1316 1317 /* switch rules population commands */ 1318 ice_aqc_opc_add_sw_rules = 0x02A0, 1319 ice_aqc_opc_update_sw_rules = 0x02A1, 1320 ice_aqc_opc_remove_sw_rules = 0x02A2, 1321 1322 ice_aqc_opc_clear_pf_cfg = 0x02A4, 1323 1324 /* transmit scheduler commands */ 1325 ice_aqc_opc_get_dflt_topo = 0x0400, 1326 ice_aqc_opc_add_sched_elems = 0x0401, 1327 ice_aqc_opc_suspend_sched_elems = 0x0409, 1328 ice_aqc_opc_resume_sched_elems = 0x040A, 1329 ice_aqc_opc_delete_sched_elems = 0x040F, 1330 ice_aqc_opc_query_sched_res = 0x0412, 1331 1332 /* PHY commands */ 1333 ice_aqc_opc_get_phy_caps = 0x0600, 1334 ice_aqc_opc_set_phy_cfg = 0x0601, 1335 ice_aqc_opc_restart_an = 0x0605, 1336 ice_aqc_opc_get_link_status = 0x0607, 1337 ice_aqc_opc_set_event_mask = 0x0613, 1338 1339 /* NVM commands */ 1340 ice_aqc_opc_nvm_read = 0x0701, 1341 1342 /* RSS commands */ 1343 ice_aqc_opc_set_rss_key = 0x0B02, 1344 ice_aqc_opc_set_rss_lut = 0x0B03, 1345 ice_aqc_opc_get_rss_key = 0x0B04, 1346 ice_aqc_opc_get_rss_lut = 0x0B05, 1347 1348 /* TX queue handling commands/events */ 1349 ice_aqc_opc_add_txqs = 0x0C30, 1350 ice_aqc_opc_dis_txqs = 0x0C31, 1351 }; 1352 1353 #endif /* _ICE_ADMINQ_CMD_H_ */ 1354