1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 struct ice_aqc_generic { 16 __le32 param0; 17 __le32 param1; 18 __le32 addr_high; 19 __le32 addr_low; 20 }; 21 22 /* Get version (direct 0x0001) */ 23 struct ice_aqc_get_ver { 24 __le32 rom_ver; 25 __le32 fw_build; 26 u8 fw_branch; 27 u8 fw_major; 28 u8 fw_minor; 29 u8 fw_patch; 30 u8 api_branch; 31 u8 api_major; 32 u8 api_minor; 33 u8 api_patch; 34 }; 35 36 /* Queue Shutdown (direct 0x0003) */ 37 struct ice_aqc_q_shutdown { 38 __le32 driver_unloading; 39 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 40 u8 reserved[12]; 41 }; 42 43 /* Request resource ownership (direct 0x0008) 44 * Release resource ownership (direct 0x0009) 45 */ 46 struct ice_aqc_req_res { 47 __le16 res_id; 48 #define ICE_AQC_RES_ID_NVM 1 49 #define ICE_AQC_RES_ID_SDP 2 50 #define ICE_AQC_RES_ID_CHNG_LOCK 3 51 #define ICE_AQC_RES_ID_GLBL_LOCK 4 52 __le16 access_type; 53 #define ICE_AQC_RES_ACCESS_READ 1 54 #define ICE_AQC_RES_ACCESS_WRITE 2 55 56 /* Upon successful completion, FW writes this value and driver is 57 * expected to release resource before timeout. This value is provided 58 * in milliseconds. 59 */ 60 __le32 timeout; 61 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 62 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 63 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 64 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 65 /* For SDP: pin ID of the SDP */ 66 __le32 res_number; 67 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 68 __le16 status; 69 #define ICE_AQ_RES_GLBL_SUCCESS 0 70 #define ICE_AQ_RES_GLBL_IN_PROG 1 71 #define ICE_AQ_RES_GLBL_DONE 2 72 u8 reserved[2]; 73 }; 74 75 /* Get function capabilities (indirect 0x000A) 76 * Get device capabilities (indirect 0x000B) 77 */ 78 struct ice_aqc_list_caps { 79 u8 cmd_flags; 80 u8 pf_index; 81 u8 reserved[2]; 82 __le32 count; 83 __le32 addr_high; 84 __le32 addr_low; 85 }; 86 87 /* Device/Function buffer entry, repeated per reported capability */ 88 struct ice_aqc_list_caps_elem { 89 __le16 cap; 90 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 91 #define ICE_AQC_CAPS_SRIOV 0x0012 92 #define ICE_AQC_CAPS_VF 0x0013 93 #define ICE_AQC_CAPS_VSI 0x0017 94 #define ICE_AQC_CAPS_RSS 0x0040 95 #define ICE_AQC_CAPS_RXQS 0x0041 96 #define ICE_AQC_CAPS_TXQS 0x0042 97 #define ICE_AQC_CAPS_MSIX 0x0043 98 #define ICE_AQC_CAPS_MAX_MTU 0x0047 99 100 u8 major_ver; 101 u8 minor_ver; 102 /* Number of resources described by this capability */ 103 __le32 number; 104 /* Only meaningful for some types of resources */ 105 __le32 logical_id; 106 /* Only meaningful for some types of resources */ 107 __le32 phys_id; 108 __le64 rsvd1; 109 __le64 rsvd2; 110 }; 111 112 /* Manage MAC address, read command - indirect (0x0107) 113 * This struct is also used for the response 114 */ 115 struct ice_aqc_manage_mac_read { 116 __le16 flags; /* Zeroed by device driver */ 117 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 118 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 119 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 120 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 121 #define ICE_AQC_MAN_MAC_READ_S 4 122 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 123 u8 rsvd[2]; 124 u8 num_addr; /* Used in response */ 125 u8 rsvd1[3]; 126 __le32 addr_high; 127 __le32 addr_low; 128 }; 129 130 /* Response buffer format for manage MAC read command */ 131 struct ice_aqc_manage_mac_read_resp { 132 u8 lport_num; 133 u8 addr_type; 134 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 135 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 136 u8 mac_addr[ETH_ALEN]; 137 }; 138 139 /* Manage MAC address, write command - direct (0x0108) */ 140 struct ice_aqc_manage_mac_write { 141 u8 rsvd; 142 u8 flags; 143 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 144 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 145 #define ICE_AQC_MAN_MAC_WR_S 6 146 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S) 147 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 148 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S) 149 /* High 16 bits of MAC address in big endian order */ 150 __be16 sah; 151 /* Low 32 bits of MAC address in big endian order */ 152 __be32 sal; 153 __le32 addr_high; 154 __le32 addr_low; 155 }; 156 157 /* Clear PXE Command and response (direct 0x0110) */ 158 struct ice_aqc_clear_pxe { 159 u8 rx_cnt; 160 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 161 u8 reserved[15]; 162 }; 163 164 /* Get switch configuration (0x0200) */ 165 struct ice_aqc_get_sw_cfg { 166 /* Reserved for command and copy of request flags for response */ 167 __le16 flags; 168 /* First desc in case of command and next_elem in case of response 169 * In case of response, if it is not zero, means all the configuration 170 * was not returned and new command shall be sent with this value in 171 * the 'first desc' field 172 */ 173 __le16 element; 174 /* Reserved for command, only used for response */ 175 __le16 num_elems; 176 __le16 rsvd; 177 __le32 addr_high; 178 __le32 addr_low; 179 }; 180 181 /* Each entry in the response buffer is of the following type: */ 182 struct ice_aqc_get_sw_cfg_resp_elem { 183 /* VSI/Port Number */ 184 __le16 vsi_port_num; 185 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 186 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 187 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 188 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 189 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 190 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 191 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 192 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 193 194 /* SWID VSI/Port belongs to */ 195 __le16 swid; 196 197 /* Bit 14..0 : PF/VF number VSI belongs to 198 * Bit 15 : VF indication bit 199 */ 200 __le16 pf_vf_num; 201 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 202 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 203 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 204 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 205 }; 206 207 /* The response buffer is as follows. Note that the length of the 208 * elements array varies with the length of the command response. 209 */ 210 struct ice_aqc_get_sw_cfg_resp { 211 struct ice_aqc_get_sw_cfg_resp_elem elements[1]; 212 }; 213 214 /* These resource type defines are used for all switch resource 215 * commands where a resource type is required, such as: 216 * Get Resource Allocation command (indirect 0x0204) 217 * Allocate Resources command (indirect 0x0208) 218 * Free Resources command (indirect 0x0209) 219 * Get Allocated Resource Descriptors Command (indirect 0x020A) 220 */ 221 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 222 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 223 224 /* Allocate Resources command (indirect 0x0208) 225 * Free Resources command (indirect 0x0209) 226 */ 227 struct ice_aqc_alloc_free_res_cmd { 228 __le16 num_entries; /* Number of Resource entries */ 229 u8 reserved[6]; 230 __le32 addr_high; 231 __le32 addr_low; 232 }; 233 234 /* Resource descriptor */ 235 struct ice_aqc_res_elem { 236 union { 237 __le16 sw_resp; 238 __le16 flu_resp; 239 } e; 240 }; 241 242 /* Buffer for Allocate/Free Resources commands */ 243 struct ice_aqc_alloc_free_res_elem { 244 __le16 res_type; /* Types defined above cmd 0x0204 */ 245 #define ICE_AQC_RES_TYPE_SHARED_S 7 246 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 247 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 248 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 249 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 250 __le16 num_elems; 251 struct ice_aqc_res_elem elem[1]; 252 }; 253 254 /* Add VSI (indirect 0x0210) 255 * Update VSI (indirect 0x0211) 256 * Get VSI (indirect 0x0212) 257 * Free VSI (indirect 0x0213) 258 */ 259 struct ice_aqc_add_get_update_free_vsi { 260 __le16 vsi_num; 261 #define ICE_AQ_VSI_NUM_S 0 262 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 263 #define ICE_AQ_VSI_IS_VALID BIT(15) 264 __le16 cmd_flags; 265 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 266 u8 vf_id; 267 u8 reserved; 268 __le16 vsi_flags; 269 #define ICE_AQ_VSI_TYPE_S 0 270 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 271 #define ICE_AQ_VSI_TYPE_VF 0x0 272 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 273 #define ICE_AQ_VSI_TYPE_PF 0x2 274 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 275 __le32 addr_high; 276 __le32 addr_low; 277 }; 278 279 /* Response descriptor for: 280 * Add VSI (indirect 0x0210) 281 * Update VSI (indirect 0x0211) 282 * Free VSI (indirect 0x0213) 283 */ 284 struct ice_aqc_add_update_free_vsi_resp { 285 __le16 vsi_num; 286 __le16 ext_status; 287 __le16 vsi_used; 288 __le16 vsi_free; 289 __le32 addr_high; 290 __le32 addr_low; 291 }; 292 293 struct ice_aqc_vsi_props { 294 __le16 valid_sections; 295 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 296 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 297 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 298 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 299 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 300 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 301 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 302 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 303 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 304 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 305 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 306 /* switch section */ 307 u8 sw_id; 308 u8 sw_flags; 309 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 310 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 311 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 312 u8 sw_flags2; 313 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 314 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 315 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 316 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 317 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 318 u8 veb_stat_id; 319 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 320 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 321 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 322 /* security section */ 323 u8 sec_flags; 324 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 325 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 326 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 327 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 328 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 329 u8 sec_reserved; 330 /* VLAN section */ 331 __le16 pvid; /* VLANS include priority bits */ 332 u8 pvlan_reserved[2]; 333 u8 vlan_flags; 334 #define ICE_AQ_VSI_VLAN_MODE_S 0 335 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 336 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 337 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 338 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 339 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 340 #define ICE_AQ_VSI_VLAN_EMOD_S 3 341 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 342 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 343 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 344 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 345 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 346 u8 pvlan_reserved2[3]; 347 /* ingress egress up sections */ 348 __le32 ingress_table; /* bitmap, 3 bits per up */ 349 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 350 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 351 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 352 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 353 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 354 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 355 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 356 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 357 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 358 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 359 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 360 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 361 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 362 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 363 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 364 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 365 __le32 egress_table; /* same defines as for ingress table */ 366 /* outer tags section */ 367 __le16 outer_tag; 368 u8 outer_tag_flags; 369 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 370 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 371 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 372 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 373 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 374 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 375 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 376 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 377 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 378 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 379 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 380 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 381 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 382 u8 outer_tag_reserved; 383 /* queue mapping section */ 384 __le16 mapping_flags; 385 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 386 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 387 __le16 q_mapping[16]; 388 #define ICE_AQ_VSI_Q_S 0 389 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 390 __le16 tc_mapping[8]; 391 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 392 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 393 #define ICE_AQ_VSI_TC_Q_NUM_S 11 394 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 395 /* queueing option section */ 396 u8 q_opt_rss; 397 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 398 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 399 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 400 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 401 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 402 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 403 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 404 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 405 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 406 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 407 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 408 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 409 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 410 u8 q_opt_tc; 411 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 412 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 413 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 414 u8 q_opt_flags; 415 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 416 u8 q_opt_reserved[3]; 417 /* outer up section */ 418 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 419 /* section 10 */ 420 __le16 sect_10_reserved; 421 /* flow director section */ 422 __le16 fd_options; 423 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 424 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 425 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 426 __le16 max_fd_fltr_dedicated; 427 __le16 max_fd_fltr_shared; 428 __le16 fd_def_q; 429 #define ICE_AQ_VSI_FD_DEF_Q_S 0 430 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 431 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 432 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 433 __le16 fd_report_opt; 434 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 435 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 436 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 437 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 438 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 439 /* PASID section */ 440 __le32 pasid_id; 441 #define ICE_AQ_VSI_PASID_ID_S 0 442 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 443 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 444 u8 reserved[24]; 445 }; 446 447 #define ICE_MAX_NUM_RECIPES 64 448 449 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 450 */ 451 struct ice_aqc_sw_rules { 452 /* ops: add switch rules, referring the number of rules. 453 * ops: update switch rules, referring the number of filters 454 * ops: remove switch rules, referring the entry index. 455 * ops: get switch rules, referring to the number of filters. 456 */ 457 __le16 num_rules_fltr_entry_index; 458 u8 reserved[6]; 459 __le32 addr_high; 460 __le32 addr_low; 461 }; 462 463 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 464 * This structures describes the lookup rules and associated actions. "index" 465 * is returned as part of a response to a successful Add command, and can be 466 * used to identify the rule for Update/Get/Remove commands. 467 */ 468 struct ice_sw_rule_lkup_rx_tx { 469 __le16 recipe_id; 470 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 471 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 472 __le16 src; 473 __le32 act; 474 475 /* Bit 0:1 - Action type */ 476 #define ICE_SINGLE_ACT_TYPE_S 0x00 477 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 478 479 /* Bit 2 - Loop back enable 480 * Bit 3 - LAN enable 481 */ 482 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 483 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 484 485 /* Action type = 0 - Forward to VSI or VSI list */ 486 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 487 488 #define ICE_SINGLE_ACT_VSI_ID_S 4 489 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 490 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 491 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 492 /* This bit needs to be set if action is forward to VSI list */ 493 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 494 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 495 #define ICE_SINGLE_ACT_DROP BIT(18) 496 497 /* Action type = 1 - Forward to Queue of Queue group */ 498 #define ICE_SINGLE_ACT_TO_Q 0x1 499 #define ICE_SINGLE_ACT_Q_INDEX_S 4 500 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 501 #define ICE_SINGLE_ACT_Q_REGION_S 15 502 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 503 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 504 505 /* Action type = 2 - Prune */ 506 #define ICE_SINGLE_ACT_PRUNE 0x2 507 #define ICE_SINGLE_ACT_EGRESS BIT(15) 508 #define ICE_SINGLE_ACT_INGRESS BIT(16) 509 #define ICE_SINGLE_ACT_PRUNET BIT(17) 510 /* Bit 18 should be set to 0 for this action */ 511 512 /* Action type = 2 - Pointer */ 513 #define ICE_SINGLE_ACT_PTR 0x2 514 #define ICE_SINGLE_ACT_PTR_VAL_S 4 515 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 516 /* Bit 18 should be set to 1 */ 517 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 518 519 /* Action type = 3 - Other actions. Last two bits 520 * are other action identifier 521 */ 522 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 523 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 524 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 525 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 526 527 /* Bit 17:18 - Defines other actions */ 528 /* Other action = 0 - Mirror VSI */ 529 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 530 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 531 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 532 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 533 534 /* Other action = 3 - Set Stat count */ 535 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 536 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 537 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 538 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 539 540 __le16 index; /* The index of the rule in the lookup table */ 541 /* Length and values of the header to be matched per recipe or 542 * lookup-type 543 */ 544 __le16 hdr_len; 545 u8 hdr[1]; 546 } __packed; 547 548 /* Add/Update/Remove large action command/response entry 549 * "index" is returned as part of a response to a successful Add command, and 550 * can be used to identify the action for Update/Get/Remove commands. 551 */ 552 struct ice_sw_rule_lg_act { 553 __le16 index; /* Index in large action table */ 554 __le16 size; 555 __le32 act[1]; /* array of size for actions */ 556 /* Max number of large actions */ 557 #define ICE_MAX_LG_ACT 4 558 /* Bit 0:1 - Action type */ 559 #define ICE_LG_ACT_TYPE_S 0 560 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 561 562 /* Action type = 0 - Forward to VSI or VSI list */ 563 #define ICE_LG_ACT_VSI_FORWARDING 0 564 #define ICE_LG_ACT_VSI_ID_S 3 565 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 566 #define ICE_LG_ACT_VSI_LIST_ID_S 3 567 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 568 /* This bit needs to be set if action is forward to VSI list */ 569 #define ICE_LG_ACT_VSI_LIST BIT(13) 570 571 #define ICE_LG_ACT_VALID_BIT BIT(16) 572 573 /* Action type = 1 - Forward to Queue of Queue group */ 574 #define ICE_LG_ACT_TO_Q 0x1 575 #define ICE_LG_ACT_Q_INDEX_S 3 576 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 577 #define ICE_LG_ACT_Q_REGION_S 14 578 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 579 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 580 581 /* Action type = 2 - Prune */ 582 #define ICE_LG_ACT_PRUNE 0x2 583 #define ICE_LG_ACT_EGRESS BIT(14) 584 #define ICE_LG_ACT_INGRESS BIT(15) 585 #define ICE_LG_ACT_PRUNET BIT(16) 586 587 /* Action type = 3 - Mirror VSI */ 588 #define ICE_LG_OTHER_ACT_MIRROR 0x3 589 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 590 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 591 592 /* Action type = 5 - Generic Value */ 593 #define ICE_LG_ACT_GENERIC 0x5 594 #define ICE_LG_ACT_GENERIC_VALUE_S 3 595 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 596 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 597 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 598 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 599 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 600 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 601 602 /* Action = 7 - Set Stat count */ 603 #define ICE_LG_ACT_STAT_COUNT 0x7 604 #define ICE_LG_ACT_STAT_COUNT_S 3 605 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 606 }; 607 608 /* Add/Update/Remove VSI list command/response entry 609 * "index" is returned as part of a response to a successful Add command, and 610 * can be used to identify the VSI list for Update/Get/Remove commands. 611 */ 612 struct ice_sw_rule_vsi_list { 613 __le16 index; /* Index of VSI/Prune list */ 614 __le16 number_vsi; 615 __le16 vsi[1]; /* Array of number_vsi VSI numbers */ 616 }; 617 618 /* Query VSI list command/response entry */ 619 struct ice_sw_rule_vsi_list_query { 620 __le16 index; 621 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI); 622 } __packed; 623 624 /* Add switch rule response: 625 * Content of return buffer is same as the input buffer. The status field and 626 * LUT index are updated as part of the response 627 */ 628 struct ice_aqc_sw_rules_elem { 629 __le16 type; /* Switch rule type, one of T_... */ 630 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 631 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 632 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 633 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 634 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 635 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 636 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 637 __le16 status; 638 union { 639 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 640 struct ice_sw_rule_lg_act lg_act; 641 struct ice_sw_rule_vsi_list vsi_list; 642 struct ice_sw_rule_vsi_list_query vsi_list_query; 643 } __packed pdata; 644 }; 645 646 /* Get Default Topology (indirect 0x0400) */ 647 struct ice_aqc_get_topo { 648 u8 port_num; 649 u8 num_branches; 650 __le16 reserved1; 651 __le32 reserved2; 652 __le32 addr_high; 653 __le32 addr_low; 654 }; 655 656 /* Update TSE (indirect 0x0403) 657 * Get TSE (indirect 0x0404) 658 * Add TSE (indirect 0x0401) 659 * Delete TSE (indirect 0x040F) 660 * Move TSE (indirect 0x0408) 661 * Suspend Nodes (indirect 0x0409) 662 * Resume Nodes (indirect 0x040A) 663 */ 664 struct ice_aqc_sched_elem_cmd { 665 __le16 num_elem_req; /* Used by commands */ 666 __le16 num_elem_resp; /* Used by responses */ 667 __le32 reserved; 668 __le32 addr_high; 669 __le32 addr_low; 670 }; 671 672 /* This is the buffer for: 673 * Suspend Nodes (indirect 0x0409) 674 * Resume Nodes (indirect 0x040A) 675 */ 676 struct ice_aqc_suspend_resume_elem { 677 __le32 teid[1]; 678 }; 679 680 struct ice_aqc_elem_info_bw { 681 __le16 bw_profile_idx; 682 __le16 bw_alloc; 683 }; 684 685 struct ice_aqc_txsched_elem { 686 u8 elem_type; /* Special field, reserved for some aq calls */ 687 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 688 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 689 #define ICE_AQC_ELEM_TYPE_TC 0x2 690 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 691 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 692 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 693 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 694 u8 valid_sections; 695 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 696 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 697 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 698 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 699 u8 generic; 700 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 701 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 702 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 703 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 704 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 705 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 706 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 707 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 708 u8 flags; /* Special field, reserved for some aq calls */ 709 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 710 struct ice_aqc_elem_info_bw cir_bw; 711 struct ice_aqc_elem_info_bw eir_bw; 712 __le16 srl_id; 713 __le16 reserved2; 714 }; 715 716 struct ice_aqc_txsched_elem_data { 717 __le32 parent_teid; 718 __le32 node_teid; 719 struct ice_aqc_txsched_elem data; 720 }; 721 722 struct ice_aqc_txsched_topo_grp_info_hdr { 723 __le32 parent_teid; 724 __le16 num_elems; 725 __le16 reserved2; 726 }; 727 728 struct ice_aqc_add_elem { 729 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 730 struct ice_aqc_txsched_elem_data generic[1]; 731 }; 732 733 struct ice_aqc_get_elem { 734 struct ice_aqc_txsched_elem_data generic[1]; 735 }; 736 737 struct ice_aqc_get_topo_elem { 738 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 739 struct ice_aqc_txsched_elem_data 740 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 741 }; 742 743 struct ice_aqc_delete_elem { 744 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 745 __le32 teid[1]; 746 }; 747 748 /* Query Port ETS (indirect 0x040E) 749 * 750 * This indirect command is used to query port TC node configuration. 751 */ 752 struct ice_aqc_query_port_ets { 753 __le32 port_teid; 754 __le32 reserved; 755 __le32 addr_high; 756 __le32 addr_low; 757 }; 758 759 struct ice_aqc_port_ets_elem { 760 u8 tc_valid_bits; 761 u8 reserved[3]; 762 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 763 __le32 up2tc; 764 u8 tc_bw_share[8]; 765 __le32 port_eir_prof_id; 766 __le32 port_cir_prof_id; 767 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 768 __le32 tc_node_prio; 769 #define ICE_TC_NODE_PRIO_S 0x4 770 u8 reserved1[4]; 771 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 772 }; 773 774 /* Query Scheduler Resource Allocation (indirect 0x0412) 775 * This indirect command retrieves the scheduler resources allocated by 776 * EMP Firmware to the given PF. 777 */ 778 struct ice_aqc_query_txsched_res { 779 u8 reserved[8]; 780 __le32 addr_high; 781 __le32 addr_low; 782 }; 783 784 struct ice_aqc_generic_sched_props { 785 __le16 phys_levels; 786 __le16 logical_levels; 787 u8 flattening_bitmap; 788 u8 max_device_cgds; 789 u8 max_pf_cgds; 790 u8 rsvd0; 791 __le16 rdma_qsets; 792 u8 rsvd1[22]; 793 }; 794 795 struct ice_aqc_layer_props { 796 u8 logical_layer; 797 u8 chunk_size; 798 __le16 max_device_nodes; 799 __le16 max_pf_nodes; 800 u8 rsvd0[4]; 801 __le16 max_sibl_grp_sz; 802 __le16 max_cir_rl_profiles; 803 __le16 max_eir_rl_profiles; 804 __le16 max_srl_profiles; 805 u8 rsvd1[14]; 806 }; 807 808 struct ice_aqc_query_txsched_res_resp { 809 struct ice_aqc_generic_sched_props sched_props; 810 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 811 }; 812 813 /* Get PHY capabilities (indirect 0x0600) */ 814 struct ice_aqc_get_phy_caps { 815 u8 lport_num; 816 u8 reserved; 817 __le16 param0; 818 /* 18.0 - Report qualified modules */ 819 #define ICE_AQC_GET_PHY_RQM BIT(0) 820 /* 18.1 - 18.2 : Report mode 821 * 00b - Report NVM capabilities 822 * 01b - Report topology capabilities 823 * 10b - Report SW configured 824 */ 825 #define ICE_AQC_REPORT_MODE_S 1 826 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 827 #define ICE_AQC_REPORT_NVM_CAP 0 828 #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 829 #define ICE_AQC_REPORT_SW_CFG BIT(2) 830 __le32 reserved1; 831 __le32 addr_high; 832 __le32 addr_low; 833 }; 834 835 /* This is #define of PHY type (Extended): 836 * The first set of defines is for phy_type_low. 837 */ 838 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 839 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 840 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 841 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 842 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 843 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 844 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 845 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 846 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 847 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 848 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 849 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 850 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 851 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 852 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 853 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 854 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 855 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 856 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 857 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 858 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 859 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 860 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 861 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 862 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 863 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 864 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 865 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 866 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 867 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 868 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 869 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 870 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 871 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 872 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 873 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 874 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 875 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 876 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 877 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 878 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 879 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 880 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 881 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 882 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 883 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 884 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 885 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 886 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 887 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 888 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 889 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 890 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 891 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 892 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 893 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 894 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 895 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 896 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 897 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 898 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 899 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 900 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 901 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 902 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 903 /* The second set of defines is for phy_type_high. */ 904 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 905 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 906 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 907 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 908 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 909 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19 910 911 struct ice_aqc_get_phy_caps_data { 912 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 913 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 914 u8 caps; 915 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 916 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 917 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 918 #define ICE_AQC_PHY_EN_LINK BIT(3) 919 #define ICE_AQC_PHY_AN_MODE BIT(4) 920 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 921 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 922 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 923 u8 low_power_ctrl; 924 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 925 __le16 eee_cap; 926 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 927 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 928 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 929 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 930 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 931 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 932 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 933 __le16 eeer_value; 934 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 935 u8 phy_fw_ver[8]; 936 u8 link_fec_options; 937 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 938 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 939 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 940 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 941 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 942 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 943 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 944 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 945 u8 rsvd1; /* Byte 35 reserved */ 946 u8 extended_compliance_code; 947 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 948 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 949 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 950 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 951 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 952 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 953 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 954 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 955 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 956 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 957 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 958 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 959 u8 qualified_module_count; 960 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 961 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 962 struct { 963 u8 v_oui[3]; 964 u8 rsvd3; 965 u8 v_part[16]; 966 __le32 v_rev; 967 __le64 rsvd4; 968 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 969 }; 970 971 /* Set PHY capabilities (direct 0x0601) 972 * NOTE: This command must be followed by setup link and restart auto-neg 973 */ 974 struct ice_aqc_set_phy_cfg { 975 u8 lport_num; 976 u8 reserved[7]; 977 __le32 addr_high; 978 __le32 addr_low; 979 }; 980 981 /* Set PHY config command data structure */ 982 struct ice_aqc_set_phy_cfg_data { 983 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 984 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 985 u8 caps; 986 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 987 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 988 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 989 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 990 #define ICE_AQ_PHY_ENA_LINK BIT(3) 991 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 992 #define ICE_AQ_PHY_ENA_LESM BIT(6) 993 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 994 u8 low_power_ctrl; 995 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 996 __le16 eeer_value; 997 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 998 u8 rsvd1; 999 }; 1000 1001 /* Restart AN command data structure (direct 0x0605) 1002 * Also used for response, with only the lport_num field present. 1003 */ 1004 struct ice_aqc_restart_an { 1005 u8 lport_num; 1006 u8 reserved; 1007 u8 cmd_flags; 1008 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1009 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1010 u8 reserved2[13]; 1011 }; 1012 1013 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1014 struct ice_aqc_get_link_status { 1015 u8 lport_num; 1016 u8 reserved; 1017 __le16 cmd_flags; 1018 #define ICE_AQ_LSE_M 0x3 1019 #define ICE_AQ_LSE_NOP 0x0 1020 #define ICE_AQ_LSE_DIS 0x2 1021 #define ICE_AQ_LSE_ENA 0x3 1022 /* only response uses this flag */ 1023 #define ICE_AQ_LSE_IS_ENABLED 0x1 1024 __le32 reserved2; 1025 __le32 addr_high; 1026 __le32 addr_low; 1027 }; 1028 1029 /* Get link status response data structure, also used for Link Status Event */ 1030 struct ice_aqc_get_link_status_data { 1031 u8 topo_media_conflict; 1032 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1033 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1034 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1035 u8 reserved1; 1036 u8 link_info; 1037 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1038 #define ICE_AQ_LINK_FAULT BIT(1) 1039 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1040 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1041 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1042 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1043 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1044 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1045 u8 an_info; 1046 #define ICE_AQ_AN_COMPLETED BIT(0) 1047 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1048 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1049 #define ICE_AQ_FEC_EN BIT(3) 1050 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1051 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1052 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1053 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1054 u8 ext_info; 1055 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1056 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1057 /* Port Tx Suspended */ 1058 #define ICE_AQ_LINK_TX_S 2 1059 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1060 #define ICE_AQ_LINK_TX_ACTIVE 0 1061 #define ICE_AQ_LINK_TX_DRAINED 1 1062 #define ICE_AQ_LINK_TX_FLUSHED 3 1063 u8 reserved2; 1064 __le16 max_frame_size; 1065 u8 cfg; 1066 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1067 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1068 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1069 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1070 /* Pacing Config */ 1071 #define ICE_AQ_CFG_PACING_S 3 1072 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1073 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1074 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1075 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1076 /* External Device Power Ability */ 1077 u8 power_desc; 1078 #define ICE_AQ_PWR_CLASS_M 0x3 1079 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1080 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1081 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1082 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1083 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1084 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1085 __le16 link_speed; 1086 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1087 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1088 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1089 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1090 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1091 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1092 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1093 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1094 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1095 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1096 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1097 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1098 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1099 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1100 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1101 }; 1102 1103 /* Set event mask command (direct 0x0613) */ 1104 struct ice_aqc_set_event_mask { 1105 u8 lport_num; 1106 u8 reserved[7]; 1107 __le16 event_mask; 1108 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1109 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1110 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1111 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1112 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1113 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1114 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1115 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1116 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1117 u8 reserved1[6]; 1118 }; 1119 1120 /* Set MAC Loopback command (direct 0x0620) */ 1121 struct ice_aqc_set_mac_lb { 1122 u8 lb_mode; 1123 #define ICE_AQ_MAC_LB_EN BIT(0) 1124 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1125 u8 reserved[15]; 1126 }; 1127 1128 /* Set Port Identification LED (direct, 0x06E9) */ 1129 struct ice_aqc_set_port_id_led { 1130 u8 lport_num; 1131 u8 lport_num_valid; 1132 u8 ident_mode; 1133 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1134 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1135 u8 rsvd[13]; 1136 }; 1137 1138 /* NVM Read command (indirect 0x0701) 1139 * NVM Erase commands (direct 0x0702) 1140 * NVM Update commands (indirect 0x0703) 1141 */ 1142 struct ice_aqc_nvm { 1143 __le16 offset_low; 1144 u8 offset_high; 1145 u8 cmd_flags; 1146 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1147 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1148 #define ICE_AQC_NVM_PRESERVATION_S 1 1149 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1150 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1151 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1152 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1153 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1154 __le16 module_typeid; 1155 __le16 length; 1156 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1157 __le32 addr_high; 1158 __le32 addr_low; 1159 }; 1160 1161 /* NVM Checksum Command (direct, 0x0706) */ 1162 struct ice_aqc_nvm_checksum { 1163 u8 flags; 1164 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1165 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1166 u8 rsvd; 1167 __le16 checksum; /* Used only by response */ 1168 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1169 u8 rsvd2[12]; 1170 }; 1171 1172 /** 1173 * Send to PF command (indirect 0x0801) ID is only used by PF 1174 * 1175 * Send to VF command (indirect 0x0802) ID is only used by PF 1176 * 1177 */ 1178 struct ice_aqc_pf_vf_msg { 1179 __le32 id; 1180 u32 reserved; 1181 __le32 addr_high; 1182 __le32 addr_low; 1183 }; 1184 1185 /* Get LLDP MIB (indirect 0x0A00) 1186 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1187 * as the format is the same. 1188 */ 1189 struct ice_aqc_lldp_get_mib { 1190 u8 type; 1191 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1192 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1193 #define ICE_AQ_LLDP_MIB_LOCAL 0 1194 #define ICE_AQ_LLDP_MIB_REMOTE 1 1195 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1196 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1197 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1198 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1199 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1200 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1201 #define ICE_AQ_LLDP_TX_S 0x4 1202 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1203 #define ICE_AQ_LLDP_TX_ACTIVE 0 1204 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1205 #define ICE_AQ_LLDP_TX_FLUSHED 3 1206 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1207 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1208 * Get LLDP MIB (0x0A00) response only. 1209 */ 1210 u8 reserved1; 1211 __le16 local_len; 1212 __le16 remote_len; 1213 u8 reserved2[2]; 1214 __le32 addr_high; 1215 __le32 addr_low; 1216 }; 1217 1218 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1219 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1220 struct ice_aqc_lldp_set_mib_change { 1221 u8 command; 1222 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1223 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1224 u8 reserved[15]; 1225 }; 1226 1227 /* Stop LLDP (direct 0x0A05) */ 1228 struct ice_aqc_lldp_stop { 1229 u8 command; 1230 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1231 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1232 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1233 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1234 u8 reserved[15]; 1235 }; 1236 1237 /* Start LLDP (direct 0x0A06) */ 1238 struct ice_aqc_lldp_start { 1239 u8 command; 1240 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1241 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1242 u8 reserved[15]; 1243 }; 1244 1245 /* Get CEE DCBX Oper Config (0x0A07) 1246 * The command uses the generic descriptor struct and 1247 * returns the struct below as an indirect response. 1248 */ 1249 struct ice_aqc_get_cee_dcb_cfg_resp { 1250 u8 oper_num_tc; 1251 u8 oper_prio_tc[4]; 1252 u8 oper_tc_bw[8]; 1253 u8 oper_pfc_en; 1254 __le16 oper_app_prio; 1255 #define ICE_AQC_CEE_APP_FCOE_S 0 1256 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1257 #define ICE_AQC_CEE_APP_ISCSI_S 3 1258 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1259 #define ICE_AQC_CEE_APP_FIP_S 8 1260 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1261 __le32 tlv_status; 1262 #define ICE_AQC_CEE_PG_STATUS_S 0 1263 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1264 #define ICE_AQC_CEE_PFC_STATUS_S 3 1265 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1266 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1267 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1268 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1269 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1270 #define ICE_AQC_CEE_FIP_STATUS_S 16 1271 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1272 u8 reserved[12]; 1273 }; 1274 1275 /* Set Local LLDP MIB (indirect 0x0A08) 1276 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1277 */ 1278 struct ice_aqc_lldp_set_local_mib { 1279 u8 type; 1280 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1281 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1282 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1283 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1284 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1285 u8 reserved0; 1286 __le16 length; 1287 u8 reserved1[4]; 1288 __le32 addr_high; 1289 __le32 addr_low; 1290 }; 1291 1292 /* Stop/Start LLDP Agent (direct 0x0A09) 1293 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1294 * The same structure is used for the response, with the command field 1295 * being used as the status field. 1296 */ 1297 struct ice_aqc_lldp_stop_start_specific_agent { 1298 u8 command; 1299 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1300 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1301 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1302 u8 reserved[15]; 1303 }; 1304 1305 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1306 struct ice_aqc_get_set_rss_key { 1307 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1308 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1309 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1310 __le16 vsi_id; 1311 u8 reserved[6]; 1312 __le32 addr_high; 1313 __le32 addr_low; 1314 }; 1315 1316 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1317 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1318 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1319 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1320 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1321 1322 struct ice_aqc_get_set_rss_keys { 1323 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1324 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1325 }; 1326 1327 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1328 struct ice_aqc_get_set_rss_lut { 1329 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1330 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1331 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1332 __le16 vsi_id; 1333 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1334 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1335 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1336 1337 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1338 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1339 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1340 1341 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1342 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1343 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1344 1345 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1346 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1347 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1348 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1349 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1350 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1351 1352 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1353 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1354 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1355 1356 __le16 flags; 1357 __le32 reserved; 1358 __le32 addr_high; 1359 __le32 addr_low; 1360 }; 1361 1362 /* Add Tx LAN Queues (indirect 0x0C30) */ 1363 struct ice_aqc_add_txqs { 1364 u8 num_qgrps; 1365 u8 reserved[3]; 1366 __le32 reserved1; 1367 __le32 addr_high; 1368 __le32 addr_low; 1369 }; 1370 1371 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1372 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1373 */ 1374 struct ice_aqc_add_txqs_perq { 1375 __le16 txq_id; 1376 u8 rsvd[2]; 1377 __le32 q_teid; 1378 u8 txq_ctx[22]; 1379 u8 rsvd2[2]; 1380 struct ice_aqc_txsched_elem info; 1381 }; 1382 1383 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 1384 * is an array of the following structs. Please note that the length of 1385 * each struct ice_aqc_add_tx_qgrp is variable due 1386 * to the variable number of queues in each group! 1387 */ 1388 struct ice_aqc_add_tx_qgrp { 1389 __le32 parent_teid; 1390 u8 num_txqs; 1391 u8 rsvd[3]; 1392 struct ice_aqc_add_txqs_perq txqs[1]; 1393 }; 1394 1395 /* Disable Tx LAN Queues (indirect 0x0C31) */ 1396 struct ice_aqc_dis_txqs { 1397 u8 cmd_type; 1398 #define ICE_AQC_Q_DIS_CMD_S 0 1399 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1400 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1401 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1402 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1403 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1404 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1405 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1406 u8 num_entries; 1407 __le16 vmvf_and_timeout; 1408 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1409 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1410 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1411 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1412 __le32 blocked_cgds; 1413 __le32 addr_high; 1414 __le32 addr_low; 1415 }; 1416 1417 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 1418 * contains the following structures, arrayed one after the 1419 * other. 1420 * Note: Since the q_id is 16 bits wide, if the 1421 * number of queues is even, then 2 bytes of alignment MUST be 1422 * added before the start of the next group, to allow correct 1423 * alignment of the parent_teid field. 1424 */ 1425 struct ice_aqc_dis_txq_item { 1426 __le32 parent_teid; 1427 u8 num_qs; 1428 u8 rsvd; 1429 /* The length of the q_id array varies according to num_qs */ 1430 __le16 q_id[1]; 1431 /* This only applies from F8 onward */ 1432 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1433 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1434 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1435 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1436 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1437 }; 1438 1439 struct ice_aqc_dis_txq { 1440 struct ice_aqc_dis_txq_item qgrps[1]; 1441 }; 1442 1443 /* Configure Firmware Logging Command (indirect 0xFF09) 1444 * Logging Information Read Response (indirect 0xFF10) 1445 * Note: The 0xFF10 command has no input parameters. 1446 */ 1447 struct ice_aqc_fw_logging { 1448 u8 log_ctrl; 1449 #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 1450 #define ICE_AQC_FW_LOG_UART_EN BIT(1) 1451 u8 rsvd0; 1452 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 1453 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 1454 #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 1455 u8 rsvd1[5]; 1456 __le32 addr_high; 1457 __le32 addr_low; 1458 }; 1459 1460 enum ice_aqc_fw_logging_mod { 1461 ICE_AQC_FW_LOG_ID_GENERAL = 0, 1462 ICE_AQC_FW_LOG_ID_CTRL, 1463 ICE_AQC_FW_LOG_ID_LINK, 1464 ICE_AQC_FW_LOG_ID_LINK_TOPO, 1465 ICE_AQC_FW_LOG_ID_DNL, 1466 ICE_AQC_FW_LOG_ID_I2C, 1467 ICE_AQC_FW_LOG_ID_SDP, 1468 ICE_AQC_FW_LOG_ID_MDIO, 1469 ICE_AQC_FW_LOG_ID_ADMINQ, 1470 ICE_AQC_FW_LOG_ID_HDMA, 1471 ICE_AQC_FW_LOG_ID_LLDP, 1472 ICE_AQC_FW_LOG_ID_DCBX, 1473 ICE_AQC_FW_LOG_ID_DCB, 1474 ICE_AQC_FW_LOG_ID_NETPROXY, 1475 ICE_AQC_FW_LOG_ID_NVM, 1476 ICE_AQC_FW_LOG_ID_AUTH, 1477 ICE_AQC_FW_LOG_ID_VPD, 1478 ICE_AQC_FW_LOG_ID_IOSF, 1479 ICE_AQC_FW_LOG_ID_PARSER, 1480 ICE_AQC_FW_LOG_ID_SW, 1481 ICE_AQC_FW_LOG_ID_SCHEDULER, 1482 ICE_AQC_FW_LOG_ID_TXQ, 1483 ICE_AQC_FW_LOG_ID_RSVD, 1484 ICE_AQC_FW_LOG_ID_POST, 1485 ICE_AQC_FW_LOG_ID_WATCHDOG, 1486 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 1487 ICE_AQC_FW_LOG_ID_MNG, 1488 ICE_AQC_FW_LOG_ID_MAX, 1489 }; 1490 1491 /* This is the buffer for both of the logging commands. 1492 * The entry array size depends on the datalen parameter in the descriptor. 1493 * There will be a total of datalen / 2 entries. 1494 */ 1495 struct ice_aqc_fw_logging_data { 1496 __le16 entry[1]; 1497 #define ICE_AQC_FW_LOG_ID_S 0 1498 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 1499 1500 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 1501 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 1502 1503 #define ICE_AQC_FW_LOG_EN_S 12 1504 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 1505 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 1506 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 1507 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 1508 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 1509 }; 1510 1511 /* Get/Clear FW Log (indirect 0xFF11) */ 1512 struct ice_aqc_get_clear_fw_log { 1513 u8 flags; 1514 #define ICE_AQC_FW_LOG_CLEAR BIT(0) 1515 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 1516 u8 rsvd1[7]; 1517 __le32 addr_high; 1518 __le32 addr_low; 1519 }; 1520 1521 /** 1522 * struct ice_aq_desc - Admin Queue (AQ) descriptor 1523 * @flags: ICE_AQ_FLAG_* flags 1524 * @opcode: AQ command opcode 1525 * @datalen: length in bytes of indirect/external data buffer 1526 * @retval: return value from firmware 1527 * @cookie_h: opaque data high-half 1528 * @cookie_l: opaque data low-half 1529 * @params: command-specific parameters 1530 * 1531 * Descriptor format for commands the driver posts on the Admin Transmit Queue 1532 * (ATQ). The firmware writes back onto the command descriptor and returns 1533 * the result of the command. Asynchronous events that are not an immediate 1534 * result of the command are written to the Admin Receive Queue (ARQ) using 1535 * the same descriptor format. Descriptors are in little-endian notation with 1536 * 32-bit words. 1537 */ 1538 struct ice_aq_desc { 1539 __le16 flags; 1540 __le16 opcode; 1541 __le16 datalen; 1542 __le16 retval; 1543 __le32 cookie_high; 1544 __le32 cookie_low; 1545 union { 1546 u8 raw[16]; 1547 struct ice_aqc_generic generic; 1548 struct ice_aqc_get_ver get_ver; 1549 struct ice_aqc_q_shutdown q_shutdown; 1550 struct ice_aqc_req_res res_owner; 1551 struct ice_aqc_manage_mac_read mac_read; 1552 struct ice_aqc_manage_mac_write mac_write; 1553 struct ice_aqc_clear_pxe clear_pxe; 1554 struct ice_aqc_list_caps get_cap; 1555 struct ice_aqc_get_phy_caps get_phy; 1556 struct ice_aqc_set_phy_cfg set_phy; 1557 struct ice_aqc_restart_an restart_an; 1558 struct ice_aqc_set_port_id_led set_port_id_led; 1559 struct ice_aqc_get_sw_cfg get_sw_conf; 1560 struct ice_aqc_sw_rules sw_rules; 1561 struct ice_aqc_get_topo get_topo; 1562 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 1563 struct ice_aqc_query_txsched_res query_sched_res; 1564 struct ice_aqc_query_port_ets port_ets; 1565 struct ice_aqc_nvm nvm; 1566 struct ice_aqc_nvm_checksum nvm_checksum; 1567 struct ice_aqc_pf_vf_msg virt; 1568 struct ice_aqc_lldp_get_mib lldp_get_mib; 1569 struct ice_aqc_lldp_set_mib_change lldp_set_event; 1570 struct ice_aqc_lldp_stop lldp_stop; 1571 struct ice_aqc_lldp_start lldp_start; 1572 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 1573 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 1574 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 1575 struct ice_aqc_get_set_rss_key get_set_rss_key; 1576 struct ice_aqc_add_txqs add_txqs; 1577 struct ice_aqc_dis_txqs dis_txqs; 1578 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 1579 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 1580 struct ice_aqc_fw_logging fw_logging; 1581 struct ice_aqc_get_clear_fw_log get_clear_fw_log; 1582 struct ice_aqc_set_mac_lb set_mac_lb; 1583 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 1584 struct ice_aqc_set_event_mask set_event_mask; 1585 struct ice_aqc_get_link_status get_link_status; 1586 } params; 1587 }; 1588 1589 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 1590 #define ICE_AQ_LG_BUF 512 1591 1592 #define ICE_AQ_FLAG_ERR_S 2 1593 #define ICE_AQ_FLAG_LB_S 9 1594 #define ICE_AQ_FLAG_RD_S 10 1595 #define ICE_AQ_FLAG_BUF_S 12 1596 #define ICE_AQ_FLAG_SI_S 13 1597 1598 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 1599 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 1600 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 1601 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 1602 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 1603 1604 /* error codes */ 1605 enum ice_aq_err { 1606 ICE_AQ_RC_OK = 0, /* Success */ 1607 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 1608 ICE_AQ_RC_ENOENT = 2, /* No such element */ 1609 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 1610 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1611 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 1612 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 1613 }; 1614 1615 /* Admin Queue command opcodes */ 1616 enum ice_adminq_opc { 1617 /* AQ commands */ 1618 ice_aqc_opc_get_ver = 0x0001, 1619 ice_aqc_opc_q_shutdown = 0x0003, 1620 1621 /* resource ownership */ 1622 ice_aqc_opc_req_res = 0x0008, 1623 ice_aqc_opc_release_res = 0x0009, 1624 1625 /* device/function capabilities */ 1626 ice_aqc_opc_list_func_caps = 0x000A, 1627 ice_aqc_opc_list_dev_caps = 0x000B, 1628 1629 /* manage MAC address */ 1630 ice_aqc_opc_manage_mac_read = 0x0107, 1631 ice_aqc_opc_manage_mac_write = 0x0108, 1632 1633 /* PXE */ 1634 ice_aqc_opc_clear_pxe_mode = 0x0110, 1635 1636 /* internal switch commands */ 1637 ice_aqc_opc_get_sw_cfg = 0x0200, 1638 1639 /* Alloc/Free/Get Resources */ 1640 ice_aqc_opc_alloc_res = 0x0208, 1641 ice_aqc_opc_free_res = 0x0209, 1642 1643 /* VSI commands */ 1644 ice_aqc_opc_add_vsi = 0x0210, 1645 ice_aqc_opc_update_vsi = 0x0211, 1646 ice_aqc_opc_free_vsi = 0x0213, 1647 1648 /* switch rules population commands */ 1649 ice_aqc_opc_add_sw_rules = 0x02A0, 1650 ice_aqc_opc_update_sw_rules = 0x02A1, 1651 ice_aqc_opc_remove_sw_rules = 0x02A2, 1652 1653 ice_aqc_opc_clear_pf_cfg = 0x02A4, 1654 1655 /* transmit scheduler commands */ 1656 ice_aqc_opc_get_dflt_topo = 0x0400, 1657 ice_aqc_opc_add_sched_elems = 0x0401, 1658 ice_aqc_opc_get_sched_elems = 0x0404, 1659 ice_aqc_opc_suspend_sched_elems = 0x0409, 1660 ice_aqc_opc_resume_sched_elems = 0x040A, 1661 ice_aqc_opc_query_port_ets = 0x040E, 1662 ice_aqc_opc_delete_sched_elems = 0x040F, 1663 ice_aqc_opc_query_sched_res = 0x0412, 1664 1665 /* PHY commands */ 1666 ice_aqc_opc_get_phy_caps = 0x0600, 1667 ice_aqc_opc_set_phy_cfg = 0x0601, 1668 ice_aqc_opc_restart_an = 0x0605, 1669 ice_aqc_opc_get_link_status = 0x0607, 1670 ice_aqc_opc_set_event_mask = 0x0613, 1671 ice_aqc_opc_set_mac_lb = 0x0620, 1672 ice_aqc_opc_set_port_id_led = 0x06E9, 1673 1674 /* NVM commands */ 1675 ice_aqc_opc_nvm_read = 0x0701, 1676 ice_aqc_opc_nvm_checksum = 0x0706, 1677 1678 /* PF/VF mailbox commands */ 1679 ice_mbx_opc_send_msg_to_pf = 0x0801, 1680 ice_mbx_opc_send_msg_to_vf = 0x0802, 1681 /* LLDP commands */ 1682 ice_aqc_opc_lldp_get_mib = 0x0A00, 1683 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 1684 ice_aqc_opc_lldp_stop = 0x0A05, 1685 ice_aqc_opc_lldp_start = 0x0A06, 1686 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 1687 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 1688 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 1689 1690 /* RSS commands */ 1691 ice_aqc_opc_set_rss_key = 0x0B02, 1692 ice_aqc_opc_set_rss_lut = 0x0B03, 1693 ice_aqc_opc_get_rss_key = 0x0B04, 1694 ice_aqc_opc_get_rss_lut = 0x0B05, 1695 1696 /* Tx queue handling commands/events */ 1697 ice_aqc_opc_add_txqs = 0x0C30, 1698 ice_aqc_opc_dis_txqs = 0x0C31, 1699 1700 /* debug commands */ 1701 ice_aqc_opc_fw_logging = 0xFF09, 1702 ice_aqc_opc_fw_logging_info = 0xFF10, 1703 }; 1704 1705 #endif /* _ICE_ADMINQ_CMD_H_ */ 1706