1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 struct ice_aqc_generic { 16 __le32 param0; 17 __le32 param1; 18 __le32 addr_high; 19 __le32 addr_low; 20 }; 21 22 /* Get version (direct 0x0001) */ 23 struct ice_aqc_get_ver { 24 __le32 rom_ver; 25 __le32 fw_build; 26 u8 fw_branch; 27 u8 fw_major; 28 u8 fw_minor; 29 u8 fw_patch; 30 u8 api_branch; 31 u8 api_major; 32 u8 api_minor; 33 u8 api_patch; 34 }; 35 36 /* Send driver version (indirect 0x0002) */ 37 struct ice_aqc_driver_ver { 38 u8 major_ver; 39 u8 minor_ver; 40 u8 build_ver; 41 u8 subbuild_ver; 42 u8 reserved[4]; 43 __le32 addr_high; 44 __le32 addr_low; 45 }; 46 47 /* Queue Shutdown (direct 0x0003) */ 48 struct ice_aqc_q_shutdown { 49 u8 driver_unloading; 50 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 51 u8 reserved[15]; 52 }; 53 54 /* Request resource ownership (direct 0x0008) 55 * Release resource ownership (direct 0x0009) 56 */ 57 struct ice_aqc_req_res { 58 __le16 res_id; 59 #define ICE_AQC_RES_ID_NVM 1 60 #define ICE_AQC_RES_ID_SDP 2 61 #define ICE_AQC_RES_ID_CHNG_LOCK 3 62 #define ICE_AQC_RES_ID_GLBL_LOCK 4 63 __le16 access_type; 64 #define ICE_AQC_RES_ACCESS_READ 1 65 #define ICE_AQC_RES_ACCESS_WRITE 2 66 67 /* Upon successful completion, FW writes this value and driver is 68 * expected to release resource before timeout. This value is provided 69 * in milliseconds. 70 */ 71 __le32 timeout; 72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 76 /* For SDP: pin ID of the SDP */ 77 __le32 res_number; 78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 79 __le16 status; 80 #define ICE_AQ_RES_GLBL_SUCCESS 0 81 #define ICE_AQ_RES_GLBL_IN_PROG 1 82 #define ICE_AQ_RES_GLBL_DONE 2 83 u8 reserved[2]; 84 }; 85 86 /* Get function capabilities (indirect 0x000A) 87 * Get device capabilities (indirect 0x000B) 88 */ 89 struct ice_aqc_list_caps { 90 u8 cmd_flags; 91 u8 pf_index; 92 u8 reserved[2]; 93 __le32 count; 94 __le32 addr_high; 95 __le32 addr_low; 96 }; 97 98 /* Device/Function buffer entry, repeated per reported capability */ 99 struct ice_aqc_list_caps_elem { 100 __le16 cap; 101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 102 #define ICE_AQC_CAPS_SRIOV 0x0012 103 #define ICE_AQC_CAPS_VF 0x0013 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_MAX_MTU 0x0047 112 113 u8 major_ver; 114 u8 minor_ver; 115 /* Number of resources described by this capability */ 116 __le32 number; 117 /* Only meaningful for some types of resources */ 118 __le32 logical_id; 119 /* Only meaningful for some types of resources */ 120 __le32 phys_id; 121 __le64 rsvd1; 122 __le64 rsvd2; 123 }; 124 125 /* Manage MAC address, read command - indirect (0x0107) 126 * This struct is also used for the response 127 */ 128 struct ice_aqc_manage_mac_read { 129 __le16 flags; /* Zeroed by device driver */ 130 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 131 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 132 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 133 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 134 #define ICE_AQC_MAN_MAC_READ_S 4 135 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 136 u8 rsvd[2]; 137 u8 num_addr; /* Used in response */ 138 u8 rsvd1[3]; 139 __le32 addr_high; 140 __le32 addr_low; 141 }; 142 143 /* Response buffer format for manage MAC read command */ 144 struct ice_aqc_manage_mac_read_resp { 145 u8 lport_num; 146 u8 addr_type; 147 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 148 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 149 u8 mac_addr[ETH_ALEN]; 150 }; 151 152 /* Manage MAC address, write command - direct (0x0108) */ 153 struct ice_aqc_manage_mac_write { 154 u8 rsvd; 155 u8 flags; 156 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 157 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 158 #define ICE_AQC_MAN_MAC_WR_S 6 159 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S) 160 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 161 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S) 162 /* High 16 bits of MAC address in big endian order */ 163 __be16 sah; 164 /* Low 32 bits of MAC address in big endian order */ 165 __be32 sal; 166 __le32 addr_high; 167 __le32 addr_low; 168 }; 169 170 /* Clear PXE Command and response (direct 0x0110) */ 171 struct ice_aqc_clear_pxe { 172 u8 rx_cnt; 173 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 174 u8 reserved[15]; 175 }; 176 177 /* Get switch configuration (0x0200) */ 178 struct ice_aqc_get_sw_cfg { 179 /* Reserved for command and copy of request flags for response */ 180 __le16 flags; 181 /* First desc in case of command and next_elem in case of response 182 * In case of response, if it is not zero, means all the configuration 183 * was not returned and new command shall be sent with this value in 184 * the 'first desc' field 185 */ 186 __le16 element; 187 /* Reserved for command, only used for response */ 188 __le16 num_elems; 189 __le16 rsvd; 190 __le32 addr_high; 191 __le32 addr_low; 192 }; 193 194 /* Each entry in the response buffer is of the following type: */ 195 struct ice_aqc_get_sw_cfg_resp_elem { 196 /* VSI/Port Number */ 197 __le16 vsi_port_num; 198 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 199 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 200 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 201 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 202 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 203 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 204 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 205 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 206 207 /* SWID VSI/Port belongs to */ 208 __le16 swid; 209 210 /* Bit 14..0 : PF/VF number VSI belongs to 211 * Bit 15 : VF indication bit 212 */ 213 __le16 pf_vf_num; 214 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 215 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 216 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 217 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 218 }; 219 220 /* The response buffer is as follows. Note that the length of the 221 * elements array varies with the length of the command response. 222 */ 223 struct ice_aqc_get_sw_cfg_resp { 224 struct ice_aqc_get_sw_cfg_resp_elem elements[1]; 225 }; 226 227 /* These resource type defines are used for all switch resource 228 * commands where a resource type is required, such as: 229 * Get Resource Allocation command (indirect 0x0204) 230 * Allocate Resources command (indirect 0x0208) 231 * Free Resources command (indirect 0x0209) 232 * Get Allocated Resource Descriptors Command (indirect 0x020A) 233 */ 234 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 235 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 236 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 237 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 238 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 239 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 240 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 241 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 242 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 243 244 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 245 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 246 247 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 248 249 #define ICE_AQC_RES_TYPE_S 0 250 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 251 252 /* Allocate Resources command (indirect 0x0208) 253 * Free Resources command (indirect 0x0209) 254 */ 255 struct ice_aqc_alloc_free_res_cmd { 256 __le16 num_entries; /* Number of Resource entries */ 257 u8 reserved[6]; 258 __le32 addr_high; 259 __le32 addr_low; 260 }; 261 262 /* Resource descriptor */ 263 struct ice_aqc_res_elem { 264 union { 265 __le16 sw_resp; 266 __le16 flu_resp; 267 } e; 268 }; 269 270 /* Buffer for Allocate/Free Resources commands */ 271 struct ice_aqc_alloc_free_res_elem { 272 __le16 res_type; /* Types defined above cmd 0x0204 */ 273 #define ICE_AQC_RES_TYPE_SHARED_S 7 274 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 275 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 276 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 277 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 278 __le16 num_elems; 279 struct ice_aqc_res_elem elem[1]; 280 }; 281 282 /* Add VSI (indirect 0x0210) 283 * Update VSI (indirect 0x0211) 284 * Get VSI (indirect 0x0212) 285 * Free VSI (indirect 0x0213) 286 */ 287 struct ice_aqc_add_get_update_free_vsi { 288 __le16 vsi_num; 289 #define ICE_AQ_VSI_NUM_S 0 290 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 291 #define ICE_AQ_VSI_IS_VALID BIT(15) 292 __le16 cmd_flags; 293 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 294 u8 vf_id; 295 u8 reserved; 296 __le16 vsi_flags; 297 #define ICE_AQ_VSI_TYPE_S 0 298 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 299 #define ICE_AQ_VSI_TYPE_VF 0x0 300 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 301 #define ICE_AQ_VSI_TYPE_PF 0x2 302 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 303 __le32 addr_high; 304 __le32 addr_low; 305 }; 306 307 /* Response descriptor for: 308 * Add VSI (indirect 0x0210) 309 * Update VSI (indirect 0x0211) 310 * Free VSI (indirect 0x0213) 311 */ 312 struct ice_aqc_add_update_free_vsi_resp { 313 __le16 vsi_num; 314 __le16 ext_status; 315 __le16 vsi_used; 316 __le16 vsi_free; 317 __le32 addr_high; 318 __le32 addr_low; 319 }; 320 321 struct ice_aqc_vsi_props { 322 __le16 valid_sections; 323 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 324 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 325 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 326 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 327 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 328 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 329 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 330 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 331 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 332 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 333 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 334 /* switch section */ 335 u8 sw_id; 336 u8 sw_flags; 337 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 338 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 339 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 340 u8 sw_flags2; 341 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 342 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 343 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 344 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 345 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 346 u8 veb_stat_id; 347 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 348 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 349 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 350 /* security section */ 351 u8 sec_flags; 352 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 353 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 354 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 355 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 356 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 357 u8 sec_reserved; 358 /* VLAN section */ 359 __le16 pvid; /* VLANS include priority bits */ 360 u8 pvlan_reserved[2]; 361 u8 vlan_flags; 362 #define ICE_AQ_VSI_VLAN_MODE_S 0 363 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 364 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 365 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 366 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 367 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 368 #define ICE_AQ_VSI_VLAN_EMOD_S 3 369 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 370 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 371 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 372 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 373 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 374 u8 pvlan_reserved2[3]; 375 /* ingress egress up sections */ 376 __le32 ingress_table; /* bitmap, 3 bits per up */ 377 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 378 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 379 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 380 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 381 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 382 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 383 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 384 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 385 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 386 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 387 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 388 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 389 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 390 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 391 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 392 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 393 __le32 egress_table; /* same defines as for ingress table */ 394 /* outer tags section */ 395 __le16 outer_tag; 396 u8 outer_tag_flags; 397 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 398 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 399 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 400 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 401 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 402 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 403 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 404 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 405 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 406 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 407 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 408 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 409 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 410 u8 outer_tag_reserved; 411 /* queue mapping section */ 412 __le16 mapping_flags; 413 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 414 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 415 __le16 q_mapping[16]; 416 #define ICE_AQ_VSI_Q_S 0 417 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 418 __le16 tc_mapping[8]; 419 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 420 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 421 #define ICE_AQ_VSI_TC_Q_NUM_S 11 422 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 423 /* queueing option section */ 424 u8 q_opt_rss; 425 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 426 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 427 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 428 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 429 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 430 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 431 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 432 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 433 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 434 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 435 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 436 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 437 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 438 u8 q_opt_tc; 439 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 440 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 441 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 442 u8 q_opt_flags; 443 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 444 u8 q_opt_reserved[3]; 445 /* outer up section */ 446 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 447 /* section 10 */ 448 __le16 sect_10_reserved; 449 /* flow director section */ 450 __le16 fd_options; 451 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 452 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 453 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 454 __le16 max_fd_fltr_dedicated; 455 __le16 max_fd_fltr_shared; 456 __le16 fd_def_q; 457 #define ICE_AQ_VSI_FD_DEF_Q_S 0 458 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 459 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 460 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 461 __le16 fd_report_opt; 462 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 463 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 464 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 465 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 466 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 467 /* PASID section */ 468 __le32 pasid_id; 469 #define ICE_AQ_VSI_PASID_ID_S 0 470 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 471 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 472 u8 reserved[24]; 473 }; 474 475 #define ICE_MAX_NUM_RECIPES 64 476 477 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 478 */ 479 struct ice_aqc_sw_rules { 480 /* ops: add switch rules, referring the number of rules. 481 * ops: update switch rules, referring the number of filters 482 * ops: remove switch rules, referring the entry index. 483 * ops: get switch rules, referring to the number of filters. 484 */ 485 __le16 num_rules_fltr_entry_index; 486 u8 reserved[6]; 487 __le32 addr_high; 488 __le32 addr_low; 489 }; 490 491 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 492 * This structures describes the lookup rules and associated actions. "index" 493 * is returned as part of a response to a successful Add command, and can be 494 * used to identify the rule for Update/Get/Remove commands. 495 */ 496 struct ice_sw_rule_lkup_rx_tx { 497 __le16 recipe_id; 498 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 499 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 500 __le16 src; 501 __le32 act; 502 503 /* Bit 0:1 - Action type */ 504 #define ICE_SINGLE_ACT_TYPE_S 0x00 505 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 506 507 /* Bit 2 - Loop back enable 508 * Bit 3 - LAN enable 509 */ 510 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 511 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 512 513 /* Action type = 0 - Forward to VSI or VSI list */ 514 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 515 516 #define ICE_SINGLE_ACT_VSI_ID_S 4 517 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 518 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 519 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 520 /* This bit needs to be set if action is forward to VSI list */ 521 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 522 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 523 #define ICE_SINGLE_ACT_DROP BIT(18) 524 525 /* Action type = 1 - Forward to Queue of Queue group */ 526 #define ICE_SINGLE_ACT_TO_Q 0x1 527 #define ICE_SINGLE_ACT_Q_INDEX_S 4 528 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 529 #define ICE_SINGLE_ACT_Q_REGION_S 15 530 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 531 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 532 533 /* Action type = 2 - Prune */ 534 #define ICE_SINGLE_ACT_PRUNE 0x2 535 #define ICE_SINGLE_ACT_EGRESS BIT(15) 536 #define ICE_SINGLE_ACT_INGRESS BIT(16) 537 #define ICE_SINGLE_ACT_PRUNET BIT(17) 538 /* Bit 18 should be set to 0 for this action */ 539 540 /* Action type = 2 - Pointer */ 541 #define ICE_SINGLE_ACT_PTR 0x2 542 #define ICE_SINGLE_ACT_PTR_VAL_S 4 543 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 544 /* Bit 18 should be set to 1 */ 545 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 546 547 /* Action type = 3 - Other actions. Last two bits 548 * are other action identifier 549 */ 550 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 551 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 552 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 553 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 554 555 /* Bit 17:18 - Defines other actions */ 556 /* Other action = 0 - Mirror VSI */ 557 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 558 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 559 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 560 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 561 562 /* Other action = 3 - Set Stat count */ 563 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 564 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 565 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 566 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 567 568 __le16 index; /* The index of the rule in the lookup table */ 569 /* Length and values of the header to be matched per recipe or 570 * lookup-type 571 */ 572 __le16 hdr_len; 573 u8 hdr[1]; 574 } __packed; 575 576 /* Add/Update/Remove large action command/response entry 577 * "index" is returned as part of a response to a successful Add command, and 578 * can be used to identify the action for Update/Get/Remove commands. 579 */ 580 struct ice_sw_rule_lg_act { 581 __le16 index; /* Index in large action table */ 582 __le16 size; 583 __le32 act[1]; /* array of size for actions */ 584 /* Max number of large actions */ 585 #define ICE_MAX_LG_ACT 4 586 /* Bit 0:1 - Action type */ 587 #define ICE_LG_ACT_TYPE_S 0 588 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 589 590 /* Action type = 0 - Forward to VSI or VSI list */ 591 #define ICE_LG_ACT_VSI_FORWARDING 0 592 #define ICE_LG_ACT_VSI_ID_S 3 593 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 594 #define ICE_LG_ACT_VSI_LIST_ID_S 3 595 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 596 /* This bit needs to be set if action is forward to VSI list */ 597 #define ICE_LG_ACT_VSI_LIST BIT(13) 598 599 #define ICE_LG_ACT_VALID_BIT BIT(16) 600 601 /* Action type = 1 - Forward to Queue of Queue group */ 602 #define ICE_LG_ACT_TO_Q 0x1 603 #define ICE_LG_ACT_Q_INDEX_S 3 604 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 605 #define ICE_LG_ACT_Q_REGION_S 14 606 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 607 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 608 609 /* Action type = 2 - Prune */ 610 #define ICE_LG_ACT_PRUNE 0x2 611 #define ICE_LG_ACT_EGRESS BIT(14) 612 #define ICE_LG_ACT_INGRESS BIT(15) 613 #define ICE_LG_ACT_PRUNET BIT(16) 614 615 /* Action type = 3 - Mirror VSI */ 616 #define ICE_LG_OTHER_ACT_MIRROR 0x3 617 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 618 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 619 620 /* Action type = 5 - Generic Value */ 621 #define ICE_LG_ACT_GENERIC 0x5 622 #define ICE_LG_ACT_GENERIC_VALUE_S 3 623 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 624 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 625 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 626 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 627 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 628 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 629 630 /* Action = 7 - Set Stat count */ 631 #define ICE_LG_ACT_STAT_COUNT 0x7 632 #define ICE_LG_ACT_STAT_COUNT_S 3 633 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 634 }; 635 636 /* Add/Update/Remove VSI list command/response entry 637 * "index" is returned as part of a response to a successful Add command, and 638 * can be used to identify the VSI list for Update/Get/Remove commands. 639 */ 640 struct ice_sw_rule_vsi_list { 641 __le16 index; /* Index of VSI/Prune list */ 642 __le16 number_vsi; 643 __le16 vsi[1]; /* Array of number_vsi VSI numbers */ 644 }; 645 646 /* Query VSI list command/response entry */ 647 struct ice_sw_rule_vsi_list_query { 648 __le16 index; 649 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI); 650 } __packed; 651 652 /* Add switch rule response: 653 * Content of return buffer is same as the input buffer. The status field and 654 * LUT index are updated as part of the response 655 */ 656 struct ice_aqc_sw_rules_elem { 657 __le16 type; /* Switch rule type, one of T_... */ 658 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 659 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 660 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 661 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 662 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 663 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 664 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 665 __le16 status; 666 union { 667 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 668 struct ice_sw_rule_lg_act lg_act; 669 struct ice_sw_rule_vsi_list vsi_list; 670 struct ice_sw_rule_vsi_list_query vsi_list_query; 671 } __packed pdata; 672 }; 673 674 /* Get Default Topology (indirect 0x0400) */ 675 struct ice_aqc_get_topo { 676 u8 port_num; 677 u8 num_branches; 678 __le16 reserved1; 679 __le32 reserved2; 680 __le32 addr_high; 681 __le32 addr_low; 682 }; 683 684 /* Update TSE (indirect 0x0403) 685 * Get TSE (indirect 0x0404) 686 * Add TSE (indirect 0x0401) 687 * Delete TSE (indirect 0x040F) 688 * Move TSE (indirect 0x0408) 689 * Suspend Nodes (indirect 0x0409) 690 * Resume Nodes (indirect 0x040A) 691 */ 692 struct ice_aqc_sched_elem_cmd { 693 __le16 num_elem_req; /* Used by commands */ 694 __le16 num_elem_resp; /* Used by responses */ 695 __le32 reserved; 696 __le32 addr_high; 697 __le32 addr_low; 698 }; 699 700 /* This is the buffer for: 701 * Suspend Nodes (indirect 0x0409) 702 * Resume Nodes (indirect 0x040A) 703 */ 704 struct ice_aqc_suspend_resume_elem { 705 __le32 teid[1]; 706 }; 707 708 struct ice_aqc_elem_info_bw { 709 __le16 bw_profile_idx; 710 __le16 bw_alloc; 711 }; 712 713 struct ice_aqc_txsched_elem { 714 u8 elem_type; /* Special field, reserved for some aq calls */ 715 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 716 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 717 #define ICE_AQC_ELEM_TYPE_TC 0x2 718 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 719 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 720 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 721 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 722 u8 valid_sections; 723 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 724 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 725 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 726 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 727 u8 generic; 728 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 729 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 730 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 731 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 732 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 733 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 734 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 735 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 736 u8 flags; /* Special field, reserved for some aq calls */ 737 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 738 struct ice_aqc_elem_info_bw cir_bw; 739 struct ice_aqc_elem_info_bw eir_bw; 740 __le16 srl_id; 741 __le16 reserved2; 742 }; 743 744 struct ice_aqc_txsched_elem_data { 745 __le32 parent_teid; 746 __le32 node_teid; 747 struct ice_aqc_txsched_elem data; 748 }; 749 750 struct ice_aqc_txsched_topo_grp_info_hdr { 751 __le32 parent_teid; 752 __le16 num_elems; 753 __le16 reserved2; 754 }; 755 756 struct ice_aqc_add_elem { 757 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 758 struct ice_aqc_txsched_elem_data generic[1]; 759 }; 760 761 struct ice_aqc_conf_elem { 762 struct ice_aqc_txsched_elem_data generic[1]; 763 }; 764 765 struct ice_aqc_get_elem { 766 struct ice_aqc_txsched_elem_data generic[1]; 767 }; 768 769 struct ice_aqc_get_topo_elem { 770 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 771 struct ice_aqc_txsched_elem_data 772 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 773 }; 774 775 struct ice_aqc_delete_elem { 776 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 777 __le32 teid[1]; 778 }; 779 780 /* Query Port ETS (indirect 0x040E) 781 * 782 * This indirect command is used to query port TC node configuration. 783 */ 784 struct ice_aqc_query_port_ets { 785 __le32 port_teid; 786 __le32 reserved; 787 __le32 addr_high; 788 __le32 addr_low; 789 }; 790 791 struct ice_aqc_port_ets_elem { 792 u8 tc_valid_bits; 793 u8 reserved[3]; 794 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 795 __le32 up2tc; 796 u8 tc_bw_share[8]; 797 __le32 port_eir_prof_id; 798 __le32 port_cir_prof_id; 799 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 800 __le32 tc_node_prio; 801 #define ICE_TC_NODE_PRIO_S 0x4 802 u8 reserved1[4]; 803 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 804 }; 805 806 /* Rate limiting profile for 807 * Add RL profile (indirect 0x0410) 808 * Query RL profile (indirect 0x0411) 809 * Remove RL profile (indirect 0x0415) 810 * These indirect commands acts on single or multiple 811 * RL profiles with specified data. 812 */ 813 struct ice_aqc_rl_profile { 814 __le16 num_profiles; 815 __le16 num_processed; /* Only for response. Reserved in Command. */ 816 u8 reserved[4]; 817 __le32 addr_high; 818 __le32 addr_low; 819 }; 820 821 struct ice_aqc_rl_profile_elem { 822 u8 level; 823 u8 flags; 824 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 825 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 826 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 827 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 828 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 829 /* The following flag is used for Query RL Profile Data */ 830 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 831 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 832 833 __le16 profile_id; 834 __le16 max_burst_size; 835 __le16 rl_multiply; 836 __le16 wake_up_calc; 837 __le16 rl_encode; 838 }; 839 840 struct ice_aqc_rl_profile_generic_elem { 841 struct ice_aqc_rl_profile_elem generic[1]; 842 }; 843 844 /* Query Scheduler Resource Allocation (indirect 0x0412) 845 * This indirect command retrieves the scheduler resources allocated by 846 * EMP Firmware to the given PF. 847 */ 848 struct ice_aqc_query_txsched_res { 849 u8 reserved[8]; 850 __le32 addr_high; 851 __le32 addr_low; 852 }; 853 854 struct ice_aqc_generic_sched_props { 855 __le16 phys_levels; 856 __le16 logical_levels; 857 u8 flattening_bitmap; 858 u8 max_device_cgds; 859 u8 max_pf_cgds; 860 u8 rsvd0; 861 __le16 rdma_qsets; 862 u8 rsvd1[22]; 863 }; 864 865 struct ice_aqc_layer_props { 866 u8 logical_layer; 867 u8 chunk_size; 868 __le16 max_device_nodes; 869 __le16 max_pf_nodes; 870 u8 rsvd0[4]; 871 __le16 max_sibl_grp_sz; 872 __le16 max_cir_rl_profiles; 873 __le16 max_eir_rl_profiles; 874 __le16 max_srl_profiles; 875 u8 rsvd1[14]; 876 }; 877 878 struct ice_aqc_query_txsched_res_resp { 879 struct ice_aqc_generic_sched_props sched_props; 880 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 881 }; 882 883 /* Get PHY capabilities (indirect 0x0600) */ 884 struct ice_aqc_get_phy_caps { 885 u8 lport_num; 886 u8 reserved; 887 __le16 param0; 888 /* 18.0 - Report qualified modules */ 889 #define ICE_AQC_GET_PHY_RQM BIT(0) 890 /* 18.1 - 18.2 : Report mode 891 * 00b - Report NVM capabilities 892 * 01b - Report topology capabilities 893 * 10b - Report SW configured 894 */ 895 #define ICE_AQC_REPORT_MODE_S 1 896 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 897 #define ICE_AQC_REPORT_NVM_CAP 0 898 #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 899 #define ICE_AQC_REPORT_SW_CFG BIT(2) 900 __le32 reserved1; 901 __le32 addr_high; 902 __le32 addr_low; 903 }; 904 905 /* This is #define of PHY type (Extended): 906 * The first set of defines is for phy_type_low. 907 */ 908 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 909 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 910 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 911 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 912 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 913 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 914 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 915 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 916 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 917 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 918 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 919 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 920 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 921 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 922 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 923 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 924 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 925 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 926 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 927 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 928 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 929 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 930 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 931 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 932 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 933 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 934 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 935 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 936 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 937 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 938 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 939 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 940 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 941 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 942 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 943 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 944 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 945 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 946 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 947 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 948 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 949 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 950 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 951 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 952 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 953 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 954 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 955 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 956 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 957 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 958 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 959 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 960 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 961 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 962 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 963 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 964 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 965 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 966 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 967 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 968 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 969 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 970 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 971 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 972 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 973 /* The second set of defines is for phy_type_high. */ 974 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 975 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 976 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 977 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 978 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 979 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19 980 981 struct ice_aqc_get_phy_caps_data { 982 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 983 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 984 u8 caps; 985 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 986 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 987 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 988 #define ICE_AQC_PHY_EN_LINK BIT(3) 989 #define ICE_AQC_PHY_AN_MODE BIT(4) 990 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 991 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 992 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 993 u8 low_power_ctrl; 994 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 995 __le16 eee_cap; 996 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 997 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 998 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 999 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1000 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1001 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1002 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1003 __le16 eeer_value; 1004 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1005 u8 phy_fw_ver[8]; 1006 u8 link_fec_options; 1007 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1008 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1009 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1010 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1011 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1012 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1013 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1014 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 1015 u8 rsvd1; /* Byte 35 reserved */ 1016 u8 extended_compliance_code; 1017 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1018 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1019 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1020 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1021 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1022 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1023 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1024 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1025 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1026 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1027 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1028 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1029 u8 qualified_module_count; 1030 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1031 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1032 struct { 1033 u8 v_oui[3]; 1034 u8 rsvd3; 1035 u8 v_part[16]; 1036 __le32 v_rev; 1037 __le64 rsvd4; 1038 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1039 }; 1040 1041 /* Set PHY capabilities (direct 0x0601) 1042 * NOTE: This command must be followed by setup link and restart auto-neg 1043 */ 1044 struct ice_aqc_set_phy_cfg { 1045 u8 lport_num; 1046 u8 reserved[7]; 1047 __le32 addr_high; 1048 __le32 addr_low; 1049 }; 1050 1051 /* Set PHY config command data structure */ 1052 struct ice_aqc_set_phy_cfg_data { 1053 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1054 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1055 u8 caps; 1056 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1057 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1058 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1059 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1060 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1061 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1062 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1063 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1064 u8 low_power_ctrl; 1065 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1066 __le16 eeer_value; 1067 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1068 u8 rsvd1; 1069 }; 1070 1071 /* Set MAC Config command data structure (direct 0x0603) */ 1072 struct ice_aqc_set_mac_cfg { 1073 __le16 max_frame_size; 1074 u8 params; 1075 #define ICE_AQ_SET_MAC_PACE_S 3 1076 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1077 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1078 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1079 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1080 u8 tx_tmr_priority; 1081 __le16 tx_tmr_value; 1082 __le16 fc_refresh_threshold; 1083 u8 drop_opts; 1084 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1085 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1086 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1087 u8 reserved[7]; 1088 }; 1089 1090 /* Restart AN command data structure (direct 0x0605) 1091 * Also used for response, with only the lport_num field present. 1092 */ 1093 struct ice_aqc_restart_an { 1094 u8 lport_num; 1095 u8 reserved; 1096 u8 cmd_flags; 1097 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1098 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1099 u8 reserved2[13]; 1100 }; 1101 1102 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1103 struct ice_aqc_get_link_status { 1104 u8 lport_num; 1105 u8 reserved; 1106 __le16 cmd_flags; 1107 #define ICE_AQ_LSE_M 0x3 1108 #define ICE_AQ_LSE_NOP 0x0 1109 #define ICE_AQ_LSE_DIS 0x2 1110 #define ICE_AQ_LSE_ENA 0x3 1111 /* only response uses this flag */ 1112 #define ICE_AQ_LSE_IS_ENABLED 0x1 1113 __le32 reserved2; 1114 __le32 addr_high; 1115 __le32 addr_low; 1116 }; 1117 1118 /* Get link status response data structure, also used for Link Status Event */ 1119 struct ice_aqc_get_link_status_data { 1120 u8 topo_media_conflict; 1121 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1122 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1123 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1124 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1125 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1126 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1127 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1128 u8 reserved1; 1129 u8 link_info; 1130 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1131 #define ICE_AQ_LINK_FAULT BIT(1) 1132 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1133 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1134 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1135 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1136 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1137 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1138 u8 an_info; 1139 #define ICE_AQ_AN_COMPLETED BIT(0) 1140 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1141 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1142 #define ICE_AQ_FEC_EN BIT(3) 1143 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1144 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1145 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1146 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1147 u8 ext_info; 1148 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1149 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1150 /* Port Tx Suspended */ 1151 #define ICE_AQ_LINK_TX_S 2 1152 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1153 #define ICE_AQ_LINK_TX_ACTIVE 0 1154 #define ICE_AQ_LINK_TX_DRAINED 1 1155 #define ICE_AQ_LINK_TX_FLUSHED 3 1156 u8 reserved2; 1157 __le16 max_frame_size; 1158 u8 cfg; 1159 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1160 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1161 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1162 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1163 /* Pacing Config */ 1164 #define ICE_AQ_CFG_PACING_S 3 1165 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1166 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1167 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1168 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1169 /* External Device Power Ability */ 1170 u8 power_desc; 1171 #define ICE_AQ_PWR_CLASS_M 0x3 1172 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1173 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1174 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1175 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1176 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1177 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1178 __le16 link_speed; 1179 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1180 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1181 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1182 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1183 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1184 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1185 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1186 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1187 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1188 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1189 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1190 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1191 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1192 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1193 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1194 }; 1195 1196 /* Set event mask command (direct 0x0613) */ 1197 struct ice_aqc_set_event_mask { 1198 u8 lport_num; 1199 u8 reserved[7]; 1200 __le16 event_mask; 1201 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1202 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1203 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1204 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1205 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1206 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1207 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1208 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1209 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1210 u8 reserved1[6]; 1211 }; 1212 1213 /* Set MAC Loopback command (direct 0x0620) */ 1214 struct ice_aqc_set_mac_lb { 1215 u8 lb_mode; 1216 #define ICE_AQ_MAC_LB_EN BIT(0) 1217 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1218 u8 reserved[15]; 1219 }; 1220 1221 /* Set Port Identification LED (direct, 0x06E9) */ 1222 struct ice_aqc_set_port_id_led { 1223 u8 lport_num; 1224 u8 lport_num_valid; 1225 u8 ident_mode; 1226 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1227 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1228 u8 rsvd[13]; 1229 }; 1230 1231 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1232 struct ice_aqc_sff_eeprom { 1233 u8 lport_num; 1234 u8 lport_num_valid; 1235 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1236 __le16 i2c_bus_addr; 1237 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1238 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1239 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1240 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1241 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1242 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1243 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1244 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1245 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1246 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1247 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1248 __le16 i2c_mem_addr; 1249 __le16 eeprom_page; 1250 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1251 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1252 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1253 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1254 __le32 addr_high; 1255 __le32 addr_low; 1256 }; 1257 1258 /* NVM Read command (indirect 0x0701) 1259 * NVM Erase commands (direct 0x0702) 1260 * NVM Update commands (indirect 0x0703) 1261 */ 1262 struct ice_aqc_nvm { 1263 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1264 __le16 offset_low; 1265 u8 offset_high; 1266 u8 cmd_flags; 1267 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1268 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1269 #define ICE_AQC_NVM_PRESERVATION_S 1 1270 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1271 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1272 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1273 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1274 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1275 __le16 module_typeid; 1276 __le16 length; 1277 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1278 __le32 addr_high; 1279 __le32 addr_low; 1280 }; 1281 1282 #define ICE_AQC_NVM_START_POINT 0 1283 1284 /* NVM Checksum Command (direct, 0x0706) */ 1285 struct ice_aqc_nvm_checksum { 1286 u8 flags; 1287 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1288 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1289 u8 rsvd; 1290 __le16 checksum; /* Used only by response */ 1291 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1292 u8 rsvd2[12]; 1293 }; 1294 1295 /* The result of netlist NVM read comes in a TLV format. The actual data 1296 * (netlist header) starts from word offset 1 (byte 2). The FW strips 1297 * out the type field from the TLV header so all the netlist fields 1298 * should adjust their offset value by 1 word (2 bytes) in order to map 1299 * their correct location. 1300 */ 1301 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B 1302 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1 1303 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */ 1304 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2 1305 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */ 1306 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_M ICE_M(0x3FF, 0) 1307 #define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5 1308 #define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */ 1309 1310 /* netlist ID block field offsets (word offsets) */ 1311 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2 1312 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3 1313 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4 1314 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5 1315 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6 1316 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7 1317 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8 1318 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9 1319 #define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA 1320 #define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F 1321 1322 /** 1323 * Send to PF command (indirect 0x0801) ID is only used by PF 1324 * 1325 * Send to VF command (indirect 0x0802) ID is only used by PF 1326 * 1327 */ 1328 struct ice_aqc_pf_vf_msg { 1329 __le32 id; 1330 u32 reserved; 1331 __le32 addr_high; 1332 __le32 addr_low; 1333 }; 1334 1335 /* Get LLDP MIB (indirect 0x0A00) 1336 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1337 * as the format is the same. 1338 */ 1339 struct ice_aqc_lldp_get_mib { 1340 u8 type; 1341 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1342 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1343 #define ICE_AQ_LLDP_MIB_LOCAL 0 1344 #define ICE_AQ_LLDP_MIB_REMOTE 1 1345 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1346 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1347 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1348 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1349 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1350 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1351 #define ICE_AQ_LLDP_TX_S 0x4 1352 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1353 #define ICE_AQ_LLDP_TX_ACTIVE 0 1354 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1355 #define ICE_AQ_LLDP_TX_FLUSHED 3 1356 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1357 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1358 * Get LLDP MIB (0x0A00) response only. 1359 */ 1360 u8 reserved1; 1361 __le16 local_len; 1362 __le16 remote_len; 1363 u8 reserved2[2]; 1364 __le32 addr_high; 1365 __le32 addr_low; 1366 }; 1367 1368 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1369 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1370 struct ice_aqc_lldp_set_mib_change { 1371 u8 command; 1372 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1373 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1374 u8 reserved[15]; 1375 }; 1376 1377 /* Stop LLDP (direct 0x0A05) */ 1378 struct ice_aqc_lldp_stop { 1379 u8 command; 1380 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1381 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1382 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1383 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1384 u8 reserved[15]; 1385 }; 1386 1387 /* Start LLDP (direct 0x0A06) */ 1388 struct ice_aqc_lldp_start { 1389 u8 command; 1390 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1391 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1392 u8 reserved[15]; 1393 }; 1394 1395 /* Get CEE DCBX Oper Config (0x0A07) 1396 * The command uses the generic descriptor struct and 1397 * returns the struct below as an indirect response. 1398 */ 1399 struct ice_aqc_get_cee_dcb_cfg_resp { 1400 u8 oper_num_tc; 1401 u8 oper_prio_tc[4]; 1402 u8 oper_tc_bw[8]; 1403 u8 oper_pfc_en; 1404 __le16 oper_app_prio; 1405 #define ICE_AQC_CEE_APP_FCOE_S 0 1406 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1407 #define ICE_AQC_CEE_APP_ISCSI_S 3 1408 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1409 #define ICE_AQC_CEE_APP_FIP_S 8 1410 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1411 __le32 tlv_status; 1412 #define ICE_AQC_CEE_PG_STATUS_S 0 1413 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1414 #define ICE_AQC_CEE_PFC_STATUS_S 3 1415 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1416 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1417 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1418 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1419 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1420 #define ICE_AQC_CEE_FIP_STATUS_S 16 1421 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1422 u8 reserved[12]; 1423 }; 1424 1425 /* Set Local LLDP MIB (indirect 0x0A08) 1426 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1427 */ 1428 struct ice_aqc_lldp_set_local_mib { 1429 u8 type; 1430 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1431 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1432 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1433 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1434 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1435 u8 reserved0; 1436 __le16 length; 1437 u8 reserved1[4]; 1438 __le32 addr_high; 1439 __le32 addr_low; 1440 }; 1441 1442 /* Stop/Start LLDP Agent (direct 0x0A09) 1443 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1444 * The same structure is used for the response, with the command field 1445 * being used as the status field. 1446 */ 1447 struct ice_aqc_lldp_stop_start_specific_agent { 1448 u8 command; 1449 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1450 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1451 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1452 u8 reserved[15]; 1453 }; 1454 1455 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1456 struct ice_aqc_get_set_rss_key { 1457 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1458 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1459 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1460 __le16 vsi_id; 1461 u8 reserved[6]; 1462 __le32 addr_high; 1463 __le32 addr_low; 1464 }; 1465 1466 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1467 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1468 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1469 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1470 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1471 1472 struct ice_aqc_get_set_rss_keys { 1473 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1474 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1475 }; 1476 1477 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1478 struct ice_aqc_get_set_rss_lut { 1479 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1480 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1481 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1482 __le16 vsi_id; 1483 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1484 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1485 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1486 1487 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1488 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1489 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1490 1491 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1492 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1493 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1494 1495 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1496 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1497 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1498 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1499 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1500 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1501 1502 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1503 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1504 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1505 1506 __le16 flags; 1507 __le32 reserved; 1508 __le32 addr_high; 1509 __le32 addr_low; 1510 }; 1511 1512 /* Add Tx LAN Queues (indirect 0x0C30) */ 1513 struct ice_aqc_add_txqs { 1514 u8 num_qgrps; 1515 u8 reserved[3]; 1516 __le32 reserved1; 1517 __le32 addr_high; 1518 __le32 addr_low; 1519 }; 1520 1521 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1522 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1523 */ 1524 struct ice_aqc_add_txqs_perq { 1525 __le16 txq_id; 1526 u8 rsvd[2]; 1527 __le32 q_teid; 1528 u8 txq_ctx[22]; 1529 u8 rsvd2[2]; 1530 struct ice_aqc_txsched_elem info; 1531 }; 1532 1533 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 1534 * is an array of the following structs. Please note that the length of 1535 * each struct ice_aqc_add_tx_qgrp is variable due 1536 * to the variable number of queues in each group! 1537 */ 1538 struct ice_aqc_add_tx_qgrp { 1539 __le32 parent_teid; 1540 u8 num_txqs; 1541 u8 rsvd[3]; 1542 struct ice_aqc_add_txqs_perq txqs[1]; 1543 }; 1544 1545 /* Disable Tx LAN Queues (indirect 0x0C31) */ 1546 struct ice_aqc_dis_txqs { 1547 u8 cmd_type; 1548 #define ICE_AQC_Q_DIS_CMD_S 0 1549 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1550 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1551 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1552 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1553 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1554 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1555 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1556 u8 num_entries; 1557 __le16 vmvf_and_timeout; 1558 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1559 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1560 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1561 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1562 __le32 blocked_cgds; 1563 __le32 addr_high; 1564 __le32 addr_low; 1565 }; 1566 1567 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 1568 * contains the following structures, arrayed one after the 1569 * other. 1570 * Note: Since the q_id is 16 bits wide, if the 1571 * number of queues is even, then 2 bytes of alignment MUST be 1572 * added before the start of the next group, to allow correct 1573 * alignment of the parent_teid field. 1574 */ 1575 struct ice_aqc_dis_txq_item { 1576 __le32 parent_teid; 1577 u8 num_qs; 1578 u8 rsvd; 1579 /* The length of the q_id array varies according to num_qs */ 1580 __le16 q_id[1]; 1581 /* This only applies from F8 onward */ 1582 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1583 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1584 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1585 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1586 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1587 }; 1588 1589 struct ice_aqc_dis_txq { 1590 struct ice_aqc_dis_txq_item qgrps[1]; 1591 }; 1592 1593 /* Configure Firmware Logging Command (indirect 0xFF09) 1594 * Logging Information Read Response (indirect 0xFF10) 1595 * Note: The 0xFF10 command has no input parameters. 1596 */ 1597 struct ice_aqc_fw_logging { 1598 u8 log_ctrl; 1599 #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 1600 #define ICE_AQC_FW_LOG_UART_EN BIT(1) 1601 u8 rsvd0; 1602 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 1603 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 1604 #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 1605 u8 rsvd1[5]; 1606 __le32 addr_high; 1607 __le32 addr_low; 1608 }; 1609 1610 enum ice_aqc_fw_logging_mod { 1611 ICE_AQC_FW_LOG_ID_GENERAL = 0, 1612 ICE_AQC_FW_LOG_ID_CTRL, 1613 ICE_AQC_FW_LOG_ID_LINK, 1614 ICE_AQC_FW_LOG_ID_LINK_TOPO, 1615 ICE_AQC_FW_LOG_ID_DNL, 1616 ICE_AQC_FW_LOG_ID_I2C, 1617 ICE_AQC_FW_LOG_ID_SDP, 1618 ICE_AQC_FW_LOG_ID_MDIO, 1619 ICE_AQC_FW_LOG_ID_ADMINQ, 1620 ICE_AQC_FW_LOG_ID_HDMA, 1621 ICE_AQC_FW_LOG_ID_LLDP, 1622 ICE_AQC_FW_LOG_ID_DCBX, 1623 ICE_AQC_FW_LOG_ID_DCB, 1624 ICE_AQC_FW_LOG_ID_NETPROXY, 1625 ICE_AQC_FW_LOG_ID_NVM, 1626 ICE_AQC_FW_LOG_ID_AUTH, 1627 ICE_AQC_FW_LOG_ID_VPD, 1628 ICE_AQC_FW_LOG_ID_IOSF, 1629 ICE_AQC_FW_LOG_ID_PARSER, 1630 ICE_AQC_FW_LOG_ID_SW, 1631 ICE_AQC_FW_LOG_ID_SCHEDULER, 1632 ICE_AQC_FW_LOG_ID_TXQ, 1633 ICE_AQC_FW_LOG_ID_RSVD, 1634 ICE_AQC_FW_LOG_ID_POST, 1635 ICE_AQC_FW_LOG_ID_WATCHDOG, 1636 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 1637 ICE_AQC_FW_LOG_ID_MNG, 1638 ICE_AQC_FW_LOG_ID_MAX, 1639 }; 1640 1641 /* This is the buffer for both of the logging commands. 1642 * The entry array size depends on the datalen parameter in the descriptor. 1643 * There will be a total of datalen / 2 entries. 1644 */ 1645 struct ice_aqc_fw_logging_data { 1646 __le16 entry[1]; 1647 #define ICE_AQC_FW_LOG_ID_S 0 1648 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 1649 1650 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 1651 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 1652 1653 #define ICE_AQC_FW_LOG_EN_S 12 1654 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 1655 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 1656 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 1657 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 1658 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 1659 }; 1660 1661 /* Get/Clear FW Log (indirect 0xFF11) */ 1662 struct ice_aqc_get_clear_fw_log { 1663 u8 flags; 1664 #define ICE_AQC_FW_LOG_CLEAR BIT(0) 1665 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 1666 u8 rsvd1[7]; 1667 __le32 addr_high; 1668 __le32 addr_low; 1669 }; 1670 1671 /* Download Package (indirect 0x0C40) */ 1672 /* Also used for Update Package (indirect 0x0C42) */ 1673 struct ice_aqc_download_pkg { 1674 u8 flags; 1675 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 1676 u8 reserved[3]; 1677 __le32 reserved1; 1678 __le32 addr_high; 1679 __le32 addr_low; 1680 }; 1681 1682 struct ice_aqc_download_pkg_resp { 1683 __le32 error_offset; 1684 __le32 error_info; 1685 __le32 addr_high; 1686 __le32 addr_low; 1687 }; 1688 1689 /* Get Package Info List (indirect 0x0C43) */ 1690 struct ice_aqc_get_pkg_info_list { 1691 __le32 reserved1; 1692 __le32 reserved2; 1693 __le32 addr_high; 1694 __le32 addr_low; 1695 }; 1696 1697 /* Version format for packages */ 1698 struct ice_pkg_ver { 1699 u8 major; 1700 u8 minor; 1701 u8 update; 1702 u8 draft; 1703 }; 1704 1705 #define ICE_PKG_NAME_SIZE 32 1706 #define ICE_SEG_NAME_SIZE 28 1707 1708 struct ice_aqc_get_pkg_info { 1709 struct ice_pkg_ver ver; 1710 char name[ICE_SEG_NAME_SIZE]; 1711 __le32 track_id; 1712 u8 is_in_nvm; 1713 u8 is_active; 1714 u8 is_active_at_boot; 1715 u8 is_modified; 1716 }; 1717 1718 /* Get Package Info List response buffer format (0x0C43) */ 1719 struct ice_aqc_get_pkg_info_resp { 1720 __le32 count; 1721 struct ice_aqc_get_pkg_info pkg_info[1]; 1722 }; 1723 1724 /* Lan Queue Overflow Event (direct, 0x1001) */ 1725 struct ice_aqc_event_lan_overflow { 1726 __le32 prtdcb_ruptq; 1727 __le32 qtx_ctl; 1728 u8 reserved[8]; 1729 }; 1730 1731 /** 1732 * struct ice_aq_desc - Admin Queue (AQ) descriptor 1733 * @flags: ICE_AQ_FLAG_* flags 1734 * @opcode: AQ command opcode 1735 * @datalen: length in bytes of indirect/external data buffer 1736 * @retval: return value from firmware 1737 * @cookie_h: opaque data high-half 1738 * @cookie_l: opaque data low-half 1739 * @params: command-specific parameters 1740 * 1741 * Descriptor format for commands the driver posts on the Admin Transmit Queue 1742 * (ATQ). The firmware writes back onto the command descriptor and returns 1743 * the result of the command. Asynchronous events that are not an immediate 1744 * result of the command are written to the Admin Receive Queue (ARQ) using 1745 * the same descriptor format. Descriptors are in little-endian notation with 1746 * 32-bit words. 1747 */ 1748 struct ice_aq_desc { 1749 __le16 flags; 1750 __le16 opcode; 1751 __le16 datalen; 1752 __le16 retval; 1753 __le32 cookie_high; 1754 __le32 cookie_low; 1755 union { 1756 u8 raw[16]; 1757 struct ice_aqc_generic generic; 1758 struct ice_aqc_get_ver get_ver; 1759 struct ice_aqc_driver_ver driver_ver; 1760 struct ice_aqc_q_shutdown q_shutdown; 1761 struct ice_aqc_req_res res_owner; 1762 struct ice_aqc_manage_mac_read mac_read; 1763 struct ice_aqc_manage_mac_write mac_write; 1764 struct ice_aqc_clear_pxe clear_pxe; 1765 struct ice_aqc_list_caps get_cap; 1766 struct ice_aqc_get_phy_caps get_phy; 1767 struct ice_aqc_set_phy_cfg set_phy; 1768 struct ice_aqc_restart_an restart_an; 1769 struct ice_aqc_sff_eeprom read_write_sff_param; 1770 struct ice_aqc_set_port_id_led set_port_id_led; 1771 struct ice_aqc_get_sw_cfg get_sw_conf; 1772 struct ice_aqc_sw_rules sw_rules; 1773 struct ice_aqc_get_topo get_topo; 1774 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 1775 struct ice_aqc_query_txsched_res query_sched_res; 1776 struct ice_aqc_query_port_ets port_ets; 1777 struct ice_aqc_rl_profile rl_profile; 1778 struct ice_aqc_nvm nvm; 1779 struct ice_aqc_nvm_checksum nvm_checksum; 1780 struct ice_aqc_pf_vf_msg virt; 1781 struct ice_aqc_lldp_get_mib lldp_get_mib; 1782 struct ice_aqc_lldp_set_mib_change lldp_set_event; 1783 struct ice_aqc_lldp_stop lldp_stop; 1784 struct ice_aqc_lldp_start lldp_start; 1785 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 1786 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 1787 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 1788 struct ice_aqc_get_set_rss_key get_set_rss_key; 1789 struct ice_aqc_add_txqs add_txqs; 1790 struct ice_aqc_dis_txqs dis_txqs; 1791 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 1792 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 1793 struct ice_aqc_fw_logging fw_logging; 1794 struct ice_aqc_get_clear_fw_log get_clear_fw_log; 1795 struct ice_aqc_download_pkg download_pkg; 1796 struct ice_aqc_set_mac_lb set_mac_lb; 1797 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 1798 struct ice_aqc_set_mac_cfg set_mac_cfg; 1799 struct ice_aqc_set_event_mask set_event_mask; 1800 struct ice_aqc_get_link_status get_link_status; 1801 struct ice_aqc_event_lan_overflow lan_overflow; 1802 } params; 1803 }; 1804 1805 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 1806 #define ICE_AQ_LG_BUF 512 1807 1808 #define ICE_AQ_FLAG_ERR_S 2 1809 #define ICE_AQ_FLAG_LB_S 9 1810 #define ICE_AQ_FLAG_RD_S 10 1811 #define ICE_AQ_FLAG_BUF_S 12 1812 #define ICE_AQ_FLAG_SI_S 13 1813 1814 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 1815 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 1816 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 1817 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 1818 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 1819 1820 /* error codes */ 1821 enum ice_aq_err { 1822 ICE_AQ_RC_OK = 0, /* Success */ 1823 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 1824 ICE_AQ_RC_ENOENT = 2, /* No such element */ 1825 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 1826 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1827 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 1828 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 1829 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 1830 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 1831 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 1832 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 1833 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 1834 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 1835 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 1836 }; 1837 1838 /* Admin Queue command opcodes */ 1839 enum ice_adminq_opc { 1840 /* AQ commands */ 1841 ice_aqc_opc_get_ver = 0x0001, 1842 ice_aqc_opc_driver_ver = 0x0002, 1843 ice_aqc_opc_q_shutdown = 0x0003, 1844 1845 /* resource ownership */ 1846 ice_aqc_opc_req_res = 0x0008, 1847 ice_aqc_opc_release_res = 0x0009, 1848 1849 /* device/function capabilities */ 1850 ice_aqc_opc_list_func_caps = 0x000A, 1851 ice_aqc_opc_list_dev_caps = 0x000B, 1852 1853 /* manage MAC address */ 1854 ice_aqc_opc_manage_mac_read = 0x0107, 1855 ice_aqc_opc_manage_mac_write = 0x0108, 1856 1857 /* PXE */ 1858 ice_aqc_opc_clear_pxe_mode = 0x0110, 1859 1860 /* internal switch commands */ 1861 ice_aqc_opc_get_sw_cfg = 0x0200, 1862 1863 /* Alloc/Free/Get Resources */ 1864 ice_aqc_opc_alloc_res = 0x0208, 1865 ice_aqc_opc_free_res = 0x0209, 1866 1867 /* VSI commands */ 1868 ice_aqc_opc_add_vsi = 0x0210, 1869 ice_aqc_opc_update_vsi = 0x0211, 1870 ice_aqc_opc_free_vsi = 0x0213, 1871 1872 /* switch rules population commands */ 1873 ice_aqc_opc_add_sw_rules = 0x02A0, 1874 ice_aqc_opc_update_sw_rules = 0x02A1, 1875 ice_aqc_opc_remove_sw_rules = 0x02A2, 1876 1877 ice_aqc_opc_clear_pf_cfg = 0x02A4, 1878 1879 /* transmit scheduler commands */ 1880 ice_aqc_opc_get_dflt_topo = 0x0400, 1881 ice_aqc_opc_add_sched_elems = 0x0401, 1882 ice_aqc_opc_cfg_sched_elems = 0x0403, 1883 ice_aqc_opc_get_sched_elems = 0x0404, 1884 ice_aqc_opc_suspend_sched_elems = 0x0409, 1885 ice_aqc_opc_resume_sched_elems = 0x040A, 1886 ice_aqc_opc_query_port_ets = 0x040E, 1887 ice_aqc_opc_delete_sched_elems = 0x040F, 1888 ice_aqc_opc_add_rl_profiles = 0x0410, 1889 ice_aqc_opc_query_sched_res = 0x0412, 1890 ice_aqc_opc_remove_rl_profiles = 0x0415, 1891 1892 /* PHY commands */ 1893 ice_aqc_opc_get_phy_caps = 0x0600, 1894 ice_aqc_opc_set_phy_cfg = 0x0601, 1895 ice_aqc_opc_set_mac_cfg = 0x0603, 1896 ice_aqc_opc_restart_an = 0x0605, 1897 ice_aqc_opc_get_link_status = 0x0607, 1898 ice_aqc_opc_set_event_mask = 0x0613, 1899 ice_aqc_opc_set_mac_lb = 0x0620, 1900 ice_aqc_opc_set_port_id_led = 0x06E9, 1901 ice_aqc_opc_sff_eeprom = 0x06EE, 1902 1903 /* NVM commands */ 1904 ice_aqc_opc_nvm_read = 0x0701, 1905 ice_aqc_opc_nvm_checksum = 0x0706, 1906 1907 /* PF/VF mailbox commands */ 1908 ice_mbx_opc_send_msg_to_pf = 0x0801, 1909 ice_mbx_opc_send_msg_to_vf = 0x0802, 1910 /* LLDP commands */ 1911 ice_aqc_opc_lldp_get_mib = 0x0A00, 1912 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 1913 ice_aqc_opc_lldp_stop = 0x0A05, 1914 ice_aqc_opc_lldp_start = 0x0A06, 1915 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 1916 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 1917 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 1918 1919 /* RSS commands */ 1920 ice_aqc_opc_set_rss_key = 0x0B02, 1921 ice_aqc_opc_set_rss_lut = 0x0B03, 1922 ice_aqc_opc_get_rss_key = 0x0B04, 1923 ice_aqc_opc_get_rss_lut = 0x0B05, 1924 1925 /* Tx queue handling commands/events */ 1926 ice_aqc_opc_add_txqs = 0x0C30, 1927 ice_aqc_opc_dis_txqs = 0x0C31, 1928 1929 /* package commands */ 1930 ice_aqc_opc_download_pkg = 0x0C40, 1931 ice_aqc_opc_update_pkg = 0x0C42, 1932 ice_aqc_opc_get_pkg_info_list = 0x0C43, 1933 1934 /* Standalone Commands/Events */ 1935 ice_aqc_opc_event_lan_overflow = 0x1001, 1936 1937 /* debug commands */ 1938 ice_aqc_opc_fw_logging = 0xFF09, 1939 ice_aqc_opc_fw_logging_info = 0xFF10, 1940 }; 1941 1942 #endif /* _ICE_ADMINQ_CMD_H_ */ 1943