1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 struct ice_aqc_generic { 16 __le32 param0; 17 __le32 param1; 18 __le32 addr_high; 19 __le32 addr_low; 20 }; 21 22 /* Get version (direct 0x0001) */ 23 struct ice_aqc_get_ver { 24 __le32 rom_ver; 25 __le32 fw_build; 26 u8 fw_branch; 27 u8 fw_major; 28 u8 fw_minor; 29 u8 fw_patch; 30 u8 api_branch; 31 u8 api_major; 32 u8 api_minor; 33 u8 api_patch; 34 }; 35 36 /* Send driver version (indirect 0x0002) */ 37 struct ice_aqc_driver_ver { 38 u8 major_ver; 39 u8 minor_ver; 40 u8 build_ver; 41 u8 subbuild_ver; 42 u8 reserved[4]; 43 __le32 addr_high; 44 __le32 addr_low; 45 }; 46 47 /* Queue Shutdown (direct 0x0003) */ 48 struct ice_aqc_q_shutdown { 49 u8 driver_unloading; 50 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 51 u8 reserved[15]; 52 }; 53 54 /* Request resource ownership (direct 0x0008) 55 * Release resource ownership (direct 0x0009) 56 */ 57 struct ice_aqc_req_res { 58 __le16 res_id; 59 #define ICE_AQC_RES_ID_NVM 1 60 #define ICE_AQC_RES_ID_SDP 2 61 #define ICE_AQC_RES_ID_CHNG_LOCK 3 62 #define ICE_AQC_RES_ID_GLBL_LOCK 4 63 __le16 access_type; 64 #define ICE_AQC_RES_ACCESS_READ 1 65 #define ICE_AQC_RES_ACCESS_WRITE 2 66 67 /* Upon successful completion, FW writes this value and driver is 68 * expected to release resource before timeout. This value is provided 69 * in milliseconds. 70 */ 71 __le32 timeout; 72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 76 /* For SDP: pin ID of the SDP */ 77 __le32 res_number; 78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 79 __le16 status; 80 #define ICE_AQ_RES_GLBL_SUCCESS 0 81 #define ICE_AQ_RES_GLBL_IN_PROG 1 82 #define ICE_AQ_RES_GLBL_DONE 2 83 u8 reserved[2]; 84 }; 85 86 /* Get function capabilities (indirect 0x000A) 87 * Get device capabilities (indirect 0x000B) 88 */ 89 struct ice_aqc_list_caps { 90 u8 cmd_flags; 91 u8 pf_index; 92 u8 reserved[2]; 93 __le32 count; 94 __le32 addr_high; 95 __le32 addr_low; 96 }; 97 98 /* Device/Function buffer entry, repeated per reported capability */ 99 struct ice_aqc_list_caps_elem { 100 __le16 cap; 101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 102 #define ICE_AQC_CAPS_SRIOV 0x0012 103 #define ICE_AQC_CAPS_VF 0x0013 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_MAX_MTU 0x0047 112 113 u8 major_ver; 114 u8 minor_ver; 115 /* Number of resources described by this capability */ 116 __le32 number; 117 /* Only meaningful for some types of resources */ 118 __le32 logical_id; 119 /* Only meaningful for some types of resources */ 120 __le32 phys_id; 121 __le64 rsvd1; 122 __le64 rsvd2; 123 }; 124 125 /* Manage MAC address, read command - indirect (0x0107) 126 * This struct is also used for the response 127 */ 128 struct ice_aqc_manage_mac_read { 129 __le16 flags; /* Zeroed by device driver */ 130 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 131 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 132 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 133 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 134 #define ICE_AQC_MAN_MAC_READ_S 4 135 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 136 u8 rsvd[2]; 137 u8 num_addr; /* Used in response */ 138 u8 rsvd1[3]; 139 __le32 addr_high; 140 __le32 addr_low; 141 }; 142 143 /* Response buffer format for manage MAC read command */ 144 struct ice_aqc_manage_mac_read_resp { 145 u8 lport_num; 146 u8 addr_type; 147 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 148 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 149 u8 mac_addr[ETH_ALEN]; 150 }; 151 152 /* Manage MAC address, write command - direct (0x0108) */ 153 struct ice_aqc_manage_mac_write { 154 u8 rsvd; 155 u8 flags; 156 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 157 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 158 #define ICE_AQC_MAN_MAC_WR_S 6 159 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S) 160 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 161 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 162 /* byte stream in network order */ 163 u8 mac_addr[ETH_ALEN]; 164 __le32 addr_high; 165 __le32 addr_low; 166 }; 167 168 /* Clear PXE Command and response (direct 0x0110) */ 169 struct ice_aqc_clear_pxe { 170 u8 rx_cnt; 171 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 172 u8 reserved[15]; 173 }; 174 175 /* Get switch configuration (0x0200) */ 176 struct ice_aqc_get_sw_cfg { 177 /* Reserved for command and copy of request flags for response */ 178 __le16 flags; 179 /* First desc in case of command and next_elem in case of response 180 * In case of response, if it is not zero, means all the configuration 181 * was not returned and new command shall be sent with this value in 182 * the 'first desc' field 183 */ 184 __le16 element; 185 /* Reserved for command, only used for response */ 186 __le16 num_elems; 187 __le16 rsvd; 188 __le32 addr_high; 189 __le32 addr_low; 190 }; 191 192 /* Each entry in the response buffer is of the following type: */ 193 struct ice_aqc_get_sw_cfg_resp_elem { 194 /* VSI/Port Number */ 195 __le16 vsi_port_num; 196 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 197 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 198 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 199 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 200 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 201 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 202 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 203 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 204 205 /* SWID VSI/Port belongs to */ 206 __le16 swid; 207 208 /* Bit 14..0 : PF/VF number VSI belongs to 209 * Bit 15 : VF indication bit 210 */ 211 __le16 pf_vf_num; 212 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 213 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 214 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 215 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 216 }; 217 218 /* These resource type defines are used for all switch resource 219 * commands where a resource type is required, such as: 220 * Get Resource Allocation command (indirect 0x0204) 221 * Allocate Resources command (indirect 0x0208) 222 * Free Resources command (indirect 0x0209) 223 * Get Allocated Resource Descriptors Command (indirect 0x020A) 224 */ 225 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 226 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 227 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 228 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 229 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 230 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 231 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 232 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 233 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 234 235 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 236 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 237 238 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 239 240 #define ICE_AQC_RES_TYPE_S 0 241 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 242 243 /* Allocate Resources command (indirect 0x0208) 244 * Free Resources command (indirect 0x0209) 245 */ 246 struct ice_aqc_alloc_free_res_cmd { 247 __le16 num_entries; /* Number of Resource entries */ 248 u8 reserved[6]; 249 __le32 addr_high; 250 __le32 addr_low; 251 }; 252 253 /* Resource descriptor */ 254 struct ice_aqc_res_elem { 255 union { 256 __le16 sw_resp; 257 __le16 flu_resp; 258 } e; 259 }; 260 261 /* Buffer for Allocate/Free Resources commands */ 262 struct ice_aqc_alloc_free_res_elem { 263 __le16 res_type; /* Types defined above cmd 0x0204 */ 264 #define ICE_AQC_RES_TYPE_SHARED_S 7 265 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 266 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 267 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 268 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 269 __le16 num_elems; 270 struct ice_aqc_res_elem elem[]; 271 }; 272 273 /* Add VSI (indirect 0x0210) 274 * Update VSI (indirect 0x0211) 275 * Get VSI (indirect 0x0212) 276 * Free VSI (indirect 0x0213) 277 */ 278 struct ice_aqc_add_get_update_free_vsi { 279 __le16 vsi_num; 280 #define ICE_AQ_VSI_NUM_S 0 281 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 282 #define ICE_AQ_VSI_IS_VALID BIT(15) 283 __le16 cmd_flags; 284 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 285 u8 vf_id; 286 u8 reserved; 287 __le16 vsi_flags; 288 #define ICE_AQ_VSI_TYPE_S 0 289 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 290 #define ICE_AQ_VSI_TYPE_VF 0x0 291 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 292 #define ICE_AQ_VSI_TYPE_PF 0x2 293 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 294 __le32 addr_high; 295 __le32 addr_low; 296 }; 297 298 /* Response descriptor for: 299 * Add VSI (indirect 0x0210) 300 * Update VSI (indirect 0x0211) 301 * Free VSI (indirect 0x0213) 302 */ 303 struct ice_aqc_add_update_free_vsi_resp { 304 __le16 vsi_num; 305 __le16 ext_status; 306 __le16 vsi_used; 307 __le16 vsi_free; 308 __le32 addr_high; 309 __le32 addr_low; 310 }; 311 312 struct ice_aqc_vsi_props { 313 __le16 valid_sections; 314 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 315 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 316 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 317 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 318 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 319 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 320 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 321 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 322 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 323 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 324 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 325 /* switch section */ 326 u8 sw_id; 327 u8 sw_flags; 328 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 329 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 330 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 331 u8 sw_flags2; 332 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 333 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 334 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 335 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 336 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 337 u8 veb_stat_id; 338 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 339 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 340 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 341 /* security section */ 342 u8 sec_flags; 343 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 344 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 345 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 346 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 347 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 348 u8 sec_reserved; 349 /* VLAN section */ 350 __le16 pvid; /* VLANS include priority bits */ 351 u8 pvlan_reserved[2]; 352 u8 vlan_flags; 353 #define ICE_AQ_VSI_VLAN_MODE_S 0 354 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 355 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 356 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 357 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 358 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 359 #define ICE_AQ_VSI_VLAN_EMOD_S 3 360 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 361 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 362 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 363 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 364 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 365 u8 pvlan_reserved2[3]; 366 /* ingress egress up sections */ 367 __le32 ingress_table; /* bitmap, 3 bits per up */ 368 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 369 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 370 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 371 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 372 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 373 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 374 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 375 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 376 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 377 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 378 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 379 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 380 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 381 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 382 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 383 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 384 __le32 egress_table; /* same defines as for ingress table */ 385 /* outer tags section */ 386 __le16 outer_tag; 387 u8 outer_tag_flags; 388 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 389 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 390 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 391 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 392 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 393 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 394 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 395 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 396 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 397 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 398 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 399 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 400 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 401 u8 outer_tag_reserved; 402 /* queue mapping section */ 403 __le16 mapping_flags; 404 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 405 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 406 __le16 q_mapping[16]; 407 #define ICE_AQ_VSI_Q_S 0 408 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 409 __le16 tc_mapping[8]; 410 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 411 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 412 #define ICE_AQ_VSI_TC_Q_NUM_S 11 413 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 414 /* queueing option section */ 415 u8 q_opt_rss; 416 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 417 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 418 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 419 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 420 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 421 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 422 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 423 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 424 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 425 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 426 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 427 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 428 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 429 u8 q_opt_tc; 430 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 431 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 432 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 433 u8 q_opt_flags; 434 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 435 u8 q_opt_reserved[3]; 436 /* outer up section */ 437 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 438 /* section 10 */ 439 __le16 sect_10_reserved; 440 /* flow director section */ 441 __le16 fd_options; 442 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 443 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 444 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 445 __le16 max_fd_fltr_dedicated; 446 __le16 max_fd_fltr_shared; 447 __le16 fd_def_q; 448 #define ICE_AQ_VSI_FD_DEF_Q_S 0 449 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 450 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 451 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 452 __le16 fd_report_opt; 453 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 454 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 455 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 456 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 457 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 458 /* PASID section */ 459 __le32 pasid_id; 460 #define ICE_AQ_VSI_PASID_ID_S 0 461 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 462 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 463 u8 reserved[24]; 464 }; 465 466 #define ICE_MAX_NUM_RECIPES 64 467 468 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 469 */ 470 struct ice_aqc_sw_rules { 471 /* ops: add switch rules, referring the number of rules. 472 * ops: update switch rules, referring the number of filters 473 * ops: remove switch rules, referring the entry index. 474 * ops: get switch rules, referring to the number of filters. 475 */ 476 __le16 num_rules_fltr_entry_index; 477 u8 reserved[6]; 478 __le32 addr_high; 479 __le32 addr_low; 480 }; 481 482 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 483 * This structures describes the lookup rules and associated actions. "index" 484 * is returned as part of a response to a successful Add command, and can be 485 * used to identify the rule for Update/Get/Remove commands. 486 */ 487 struct ice_sw_rule_lkup_rx_tx { 488 __le16 recipe_id; 489 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 490 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 491 __le16 src; 492 __le32 act; 493 494 /* Bit 0:1 - Action type */ 495 #define ICE_SINGLE_ACT_TYPE_S 0x00 496 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 497 498 /* Bit 2 - Loop back enable 499 * Bit 3 - LAN enable 500 */ 501 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 502 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 503 504 /* Action type = 0 - Forward to VSI or VSI list */ 505 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 506 507 #define ICE_SINGLE_ACT_VSI_ID_S 4 508 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 509 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 510 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 511 /* This bit needs to be set if action is forward to VSI list */ 512 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 513 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 514 #define ICE_SINGLE_ACT_DROP BIT(18) 515 516 /* Action type = 1 - Forward to Queue of Queue group */ 517 #define ICE_SINGLE_ACT_TO_Q 0x1 518 #define ICE_SINGLE_ACT_Q_INDEX_S 4 519 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 520 #define ICE_SINGLE_ACT_Q_REGION_S 15 521 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 522 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 523 524 /* Action type = 2 - Prune */ 525 #define ICE_SINGLE_ACT_PRUNE 0x2 526 #define ICE_SINGLE_ACT_EGRESS BIT(15) 527 #define ICE_SINGLE_ACT_INGRESS BIT(16) 528 #define ICE_SINGLE_ACT_PRUNET BIT(17) 529 /* Bit 18 should be set to 0 for this action */ 530 531 /* Action type = 2 - Pointer */ 532 #define ICE_SINGLE_ACT_PTR 0x2 533 #define ICE_SINGLE_ACT_PTR_VAL_S 4 534 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 535 /* Bit 18 should be set to 1 */ 536 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 537 538 /* Action type = 3 - Other actions. Last two bits 539 * are other action identifier 540 */ 541 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 542 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 543 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 544 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 545 546 /* Bit 17:18 - Defines other actions */ 547 /* Other action = 0 - Mirror VSI */ 548 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 549 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 550 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 551 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 552 553 /* Other action = 3 - Set Stat count */ 554 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 555 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 556 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 557 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 558 559 __le16 index; /* The index of the rule in the lookup table */ 560 /* Length and values of the header to be matched per recipe or 561 * lookup-type 562 */ 563 __le16 hdr_len; 564 u8 hdr[]; 565 }; 566 567 /* Add/Update/Remove large action command/response entry 568 * "index" is returned as part of a response to a successful Add command, and 569 * can be used to identify the action for Update/Get/Remove commands. 570 */ 571 struct ice_sw_rule_lg_act { 572 __le16 index; /* Index in large action table */ 573 __le16 size; 574 /* Max number of large actions */ 575 #define ICE_MAX_LG_ACT 4 576 /* Bit 0:1 - Action type */ 577 #define ICE_LG_ACT_TYPE_S 0 578 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 579 580 /* Action type = 0 - Forward to VSI or VSI list */ 581 #define ICE_LG_ACT_VSI_FORWARDING 0 582 #define ICE_LG_ACT_VSI_ID_S 3 583 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 584 #define ICE_LG_ACT_VSI_LIST_ID_S 3 585 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 586 /* This bit needs to be set if action is forward to VSI list */ 587 #define ICE_LG_ACT_VSI_LIST BIT(13) 588 589 #define ICE_LG_ACT_VALID_BIT BIT(16) 590 591 /* Action type = 1 - Forward to Queue of Queue group */ 592 #define ICE_LG_ACT_TO_Q 0x1 593 #define ICE_LG_ACT_Q_INDEX_S 3 594 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 595 #define ICE_LG_ACT_Q_REGION_S 14 596 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 597 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 598 599 /* Action type = 2 - Prune */ 600 #define ICE_LG_ACT_PRUNE 0x2 601 #define ICE_LG_ACT_EGRESS BIT(14) 602 #define ICE_LG_ACT_INGRESS BIT(15) 603 #define ICE_LG_ACT_PRUNET BIT(16) 604 605 /* Action type = 3 - Mirror VSI */ 606 #define ICE_LG_OTHER_ACT_MIRROR 0x3 607 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 608 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 609 610 /* Action type = 5 - Generic Value */ 611 #define ICE_LG_ACT_GENERIC 0x5 612 #define ICE_LG_ACT_GENERIC_VALUE_S 3 613 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 614 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 615 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 616 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 617 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 618 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 619 620 /* Action = 7 - Set Stat count */ 621 #define ICE_LG_ACT_STAT_COUNT 0x7 622 #define ICE_LG_ACT_STAT_COUNT_S 3 623 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 624 __le32 act[]; /* array of size for actions */ 625 }; 626 627 /* Add/Update/Remove VSI list command/response entry 628 * "index" is returned as part of a response to a successful Add command, and 629 * can be used to identify the VSI list for Update/Get/Remove commands. 630 */ 631 struct ice_sw_rule_vsi_list { 632 __le16 index; /* Index of VSI/Prune list */ 633 __le16 number_vsi; 634 __le16 vsi[]; /* Array of number_vsi VSI numbers */ 635 }; 636 637 /* Query VSI list command/response entry */ 638 struct ice_sw_rule_vsi_list_query { 639 __le16 index; 640 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI); 641 } __packed; 642 643 /* Add switch rule response: 644 * Content of return buffer is same as the input buffer. The status field and 645 * LUT index are updated as part of the response 646 */ 647 struct ice_aqc_sw_rules_elem { 648 __le16 type; /* Switch rule type, one of T_... */ 649 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 650 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 651 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 652 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 653 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 654 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 655 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 656 __le16 status; 657 union { 658 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 659 struct ice_sw_rule_lg_act lg_act; 660 struct ice_sw_rule_vsi_list vsi_list; 661 struct ice_sw_rule_vsi_list_query vsi_list_query; 662 } __packed pdata; 663 }; 664 665 /* Get Default Topology (indirect 0x0400) */ 666 struct ice_aqc_get_topo { 667 u8 port_num; 668 u8 num_branches; 669 __le16 reserved1; 670 __le32 reserved2; 671 __le32 addr_high; 672 __le32 addr_low; 673 }; 674 675 /* Update TSE (indirect 0x0403) 676 * Get TSE (indirect 0x0404) 677 * Add TSE (indirect 0x0401) 678 * Delete TSE (indirect 0x040F) 679 * Move TSE (indirect 0x0408) 680 * Suspend Nodes (indirect 0x0409) 681 * Resume Nodes (indirect 0x040A) 682 */ 683 struct ice_aqc_sched_elem_cmd { 684 __le16 num_elem_req; /* Used by commands */ 685 __le16 num_elem_resp; /* Used by responses */ 686 __le32 reserved; 687 __le32 addr_high; 688 __le32 addr_low; 689 }; 690 691 struct ice_aqc_elem_info_bw { 692 __le16 bw_profile_idx; 693 __le16 bw_alloc; 694 }; 695 696 struct ice_aqc_txsched_elem { 697 u8 elem_type; /* Special field, reserved for some aq calls */ 698 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 699 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 700 #define ICE_AQC_ELEM_TYPE_TC 0x2 701 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 702 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 703 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 704 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 705 u8 valid_sections; 706 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 707 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 708 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 709 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 710 u8 generic; 711 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 712 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 713 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 714 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 715 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 716 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 717 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 718 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 719 u8 flags; /* Special field, reserved for some aq calls */ 720 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 721 struct ice_aqc_elem_info_bw cir_bw; 722 struct ice_aqc_elem_info_bw eir_bw; 723 __le16 srl_id; 724 __le16 reserved2; 725 }; 726 727 struct ice_aqc_txsched_elem_data { 728 __le32 parent_teid; 729 __le32 node_teid; 730 struct ice_aqc_txsched_elem data; 731 }; 732 733 struct ice_aqc_txsched_topo_grp_info_hdr { 734 __le32 parent_teid; 735 __le16 num_elems; 736 __le16 reserved2; 737 }; 738 739 struct ice_aqc_add_elem { 740 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 741 struct ice_aqc_txsched_elem_data generic[]; 742 }; 743 744 struct ice_aqc_get_topo_elem { 745 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 746 struct ice_aqc_txsched_elem_data 747 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 748 }; 749 750 struct ice_aqc_delete_elem { 751 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 752 __le32 teid[]; 753 }; 754 755 /* Query Port ETS (indirect 0x040E) 756 * 757 * This indirect command is used to query port TC node configuration. 758 */ 759 struct ice_aqc_query_port_ets { 760 __le32 port_teid; 761 __le32 reserved; 762 __le32 addr_high; 763 __le32 addr_low; 764 }; 765 766 struct ice_aqc_port_ets_elem { 767 u8 tc_valid_bits; 768 u8 reserved[3]; 769 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 770 __le32 up2tc; 771 u8 tc_bw_share[8]; 772 __le32 port_eir_prof_id; 773 __le32 port_cir_prof_id; 774 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 775 __le32 tc_node_prio; 776 #define ICE_TC_NODE_PRIO_S 0x4 777 u8 reserved1[4]; 778 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 779 }; 780 781 /* Rate limiting profile for 782 * Add RL profile (indirect 0x0410) 783 * Query RL profile (indirect 0x0411) 784 * Remove RL profile (indirect 0x0415) 785 * These indirect commands acts on single or multiple 786 * RL profiles with specified data. 787 */ 788 struct ice_aqc_rl_profile { 789 __le16 num_profiles; 790 __le16 num_processed; /* Only for response. Reserved in Command. */ 791 u8 reserved[4]; 792 __le32 addr_high; 793 __le32 addr_low; 794 }; 795 796 struct ice_aqc_rl_profile_elem { 797 u8 level; 798 u8 flags; 799 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 800 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 801 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 802 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 803 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 804 /* The following flag is used for Query RL Profile Data */ 805 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 806 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 807 808 __le16 profile_id; 809 __le16 max_burst_size; 810 __le16 rl_multiply; 811 __le16 wake_up_calc; 812 __le16 rl_encode; 813 }; 814 815 /* Query Scheduler Resource Allocation (indirect 0x0412) 816 * This indirect command retrieves the scheduler resources allocated by 817 * EMP Firmware to the given PF. 818 */ 819 struct ice_aqc_query_txsched_res { 820 u8 reserved[8]; 821 __le32 addr_high; 822 __le32 addr_low; 823 }; 824 825 struct ice_aqc_generic_sched_props { 826 __le16 phys_levels; 827 __le16 logical_levels; 828 u8 flattening_bitmap; 829 u8 max_device_cgds; 830 u8 max_pf_cgds; 831 u8 rsvd0; 832 __le16 rdma_qsets; 833 u8 rsvd1[22]; 834 }; 835 836 struct ice_aqc_layer_props { 837 u8 logical_layer; 838 u8 chunk_size; 839 __le16 max_device_nodes; 840 __le16 max_pf_nodes; 841 u8 rsvd0[4]; 842 __le16 max_sibl_grp_sz; 843 __le16 max_cir_rl_profiles; 844 __le16 max_eir_rl_profiles; 845 __le16 max_srl_profiles; 846 u8 rsvd1[14]; 847 }; 848 849 struct ice_aqc_query_txsched_res_resp { 850 struct ice_aqc_generic_sched_props sched_props; 851 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 852 }; 853 854 /* Get PHY capabilities (indirect 0x0600) */ 855 struct ice_aqc_get_phy_caps { 856 u8 lport_num; 857 u8 reserved; 858 __le16 param0; 859 /* 18.0 - Report qualified modules */ 860 #define ICE_AQC_GET_PHY_RQM BIT(0) 861 /* 18.1 - 18.2 : Report mode 862 * 00b - Report NVM capabilities 863 * 01b - Report topology capabilities 864 * 10b - Report SW configured 865 */ 866 #define ICE_AQC_REPORT_MODE_S 1 867 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 868 #define ICE_AQC_REPORT_NVM_CAP 0 869 #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 870 #define ICE_AQC_REPORT_SW_CFG BIT(2) 871 __le32 reserved1; 872 __le32 addr_high; 873 __le32 addr_low; 874 }; 875 876 /* This is #define of PHY type (Extended): 877 * The first set of defines is for phy_type_low. 878 */ 879 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 880 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 881 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 882 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 883 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 884 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 885 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 886 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 887 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 888 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 889 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 890 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 891 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 892 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 893 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 894 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 895 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 896 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 897 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 898 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 899 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 900 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 901 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 902 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 903 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 904 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 905 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 906 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 907 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 908 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 909 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 910 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 911 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 912 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 913 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 914 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 915 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 916 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 917 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 918 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 919 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 920 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 921 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 922 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 923 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 924 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 925 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 926 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 927 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 928 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 929 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 930 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 931 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 932 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 933 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 934 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 935 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 936 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 937 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 938 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 939 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 940 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 941 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 942 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 943 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 944 /* The second set of defines is for phy_type_high. */ 945 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 946 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 947 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 948 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 949 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 950 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 951 952 struct ice_aqc_get_phy_caps_data { 953 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 954 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 955 u8 caps; 956 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 957 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 958 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 959 #define ICE_AQC_PHY_EN_LINK BIT(3) 960 #define ICE_AQC_PHY_AN_MODE BIT(4) 961 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 962 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 963 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 964 u8 low_power_ctrl; 965 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 966 __le16 eee_cap; 967 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 968 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 969 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 970 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 971 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 972 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 973 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 974 __le16 eeer_value; 975 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 976 u8 phy_fw_ver[8]; 977 u8 link_fec_options; 978 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 979 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 980 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 981 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 982 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 983 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 984 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 985 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 986 u8 rsvd1; /* Byte 35 reserved */ 987 u8 extended_compliance_code; 988 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 989 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 990 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 991 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 992 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 993 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 994 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 995 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 996 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 997 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 998 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 999 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1000 u8 qualified_module_count; 1001 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1002 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1003 struct { 1004 u8 v_oui[3]; 1005 u8 rsvd3; 1006 u8 v_part[16]; 1007 __le32 v_rev; 1008 __le64 rsvd4; 1009 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1010 }; 1011 1012 /* Set PHY capabilities (direct 0x0601) 1013 * NOTE: This command must be followed by setup link and restart auto-neg 1014 */ 1015 struct ice_aqc_set_phy_cfg { 1016 u8 lport_num; 1017 u8 reserved[7]; 1018 __le32 addr_high; 1019 __le32 addr_low; 1020 }; 1021 1022 /* Set PHY config command data structure */ 1023 struct ice_aqc_set_phy_cfg_data { 1024 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1025 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1026 u8 caps; 1027 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1028 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1029 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1030 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1031 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1032 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1033 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1034 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1035 u8 low_power_ctrl; 1036 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1037 __le16 eeer_value; 1038 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1039 u8 rsvd1; 1040 }; 1041 1042 /* Set MAC Config command data structure (direct 0x0603) */ 1043 struct ice_aqc_set_mac_cfg { 1044 __le16 max_frame_size; 1045 u8 params; 1046 #define ICE_AQ_SET_MAC_PACE_S 3 1047 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1048 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1049 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1050 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1051 u8 tx_tmr_priority; 1052 __le16 tx_tmr_value; 1053 __le16 fc_refresh_threshold; 1054 u8 drop_opts; 1055 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1056 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1057 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1058 u8 reserved[7]; 1059 }; 1060 1061 /* Restart AN command data structure (direct 0x0605) 1062 * Also used for response, with only the lport_num field present. 1063 */ 1064 struct ice_aqc_restart_an { 1065 u8 lport_num; 1066 u8 reserved; 1067 u8 cmd_flags; 1068 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1069 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1070 u8 reserved2[13]; 1071 }; 1072 1073 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1074 struct ice_aqc_get_link_status { 1075 u8 lport_num; 1076 u8 reserved; 1077 __le16 cmd_flags; 1078 #define ICE_AQ_LSE_M 0x3 1079 #define ICE_AQ_LSE_NOP 0x0 1080 #define ICE_AQ_LSE_DIS 0x2 1081 #define ICE_AQ_LSE_ENA 0x3 1082 /* only response uses this flag */ 1083 #define ICE_AQ_LSE_IS_ENABLED 0x1 1084 __le32 reserved2; 1085 __le32 addr_high; 1086 __le32 addr_low; 1087 }; 1088 1089 /* Get link status response data structure, also used for Link Status Event */ 1090 struct ice_aqc_get_link_status_data { 1091 u8 topo_media_conflict; 1092 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1093 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1094 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1095 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1096 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1097 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1098 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1099 u8 reserved1; 1100 u8 link_info; 1101 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1102 #define ICE_AQ_LINK_FAULT BIT(1) 1103 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1104 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1105 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1106 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1107 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1108 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1109 u8 an_info; 1110 #define ICE_AQ_AN_COMPLETED BIT(0) 1111 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1112 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1113 #define ICE_AQ_FEC_EN BIT(3) 1114 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1115 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1116 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1117 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1118 u8 ext_info; 1119 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1120 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1121 /* Port Tx Suspended */ 1122 #define ICE_AQ_LINK_TX_S 2 1123 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1124 #define ICE_AQ_LINK_TX_ACTIVE 0 1125 #define ICE_AQ_LINK_TX_DRAINED 1 1126 #define ICE_AQ_LINK_TX_FLUSHED 3 1127 u8 reserved2; 1128 __le16 max_frame_size; 1129 u8 cfg; 1130 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1131 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1132 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1133 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1134 /* Pacing Config */ 1135 #define ICE_AQ_CFG_PACING_S 3 1136 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1137 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1138 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1139 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1140 /* External Device Power Ability */ 1141 u8 power_desc; 1142 #define ICE_AQ_PWR_CLASS_M 0x3 1143 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1144 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1145 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1146 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1147 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1148 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1149 __le16 link_speed; 1150 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1151 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1152 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1153 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1154 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1155 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1156 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1157 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1158 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1159 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1160 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1161 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1162 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1163 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1164 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1165 }; 1166 1167 /* Set event mask command (direct 0x0613) */ 1168 struct ice_aqc_set_event_mask { 1169 u8 lport_num; 1170 u8 reserved[7]; 1171 __le16 event_mask; 1172 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1173 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1174 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1175 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1176 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1177 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1178 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1179 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1180 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1181 u8 reserved1[6]; 1182 }; 1183 1184 /* Set MAC Loopback command (direct 0x0620) */ 1185 struct ice_aqc_set_mac_lb { 1186 u8 lb_mode; 1187 #define ICE_AQ_MAC_LB_EN BIT(0) 1188 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1189 u8 reserved[15]; 1190 }; 1191 1192 /* Set Port Identification LED (direct, 0x06E9) */ 1193 struct ice_aqc_set_port_id_led { 1194 u8 lport_num; 1195 u8 lport_num_valid; 1196 u8 ident_mode; 1197 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1198 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1199 u8 rsvd[13]; 1200 }; 1201 1202 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1203 struct ice_aqc_sff_eeprom { 1204 u8 lport_num; 1205 u8 lport_num_valid; 1206 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1207 __le16 i2c_bus_addr; 1208 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1209 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1210 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1211 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1212 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1213 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1214 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1215 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1216 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1217 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1218 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1219 __le16 i2c_mem_addr; 1220 __le16 eeprom_page; 1221 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1222 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1223 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1224 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1225 __le32 addr_high; 1226 __le32 addr_low; 1227 }; 1228 1229 /* NVM Read command (indirect 0x0701) 1230 * NVM Erase commands (direct 0x0702) 1231 * NVM Update commands (indirect 0x0703) 1232 */ 1233 struct ice_aqc_nvm { 1234 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1235 __le16 offset_low; 1236 u8 offset_high; 1237 u8 cmd_flags; 1238 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1239 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1240 #define ICE_AQC_NVM_PRESERVATION_S 1 1241 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1242 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1243 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1244 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1245 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1246 __le16 module_typeid; 1247 __le16 length; 1248 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1249 __le32 addr_high; 1250 __le32 addr_low; 1251 }; 1252 1253 #define ICE_AQC_NVM_START_POINT 0 1254 1255 /* NVM Checksum Command (direct, 0x0706) */ 1256 struct ice_aqc_nvm_checksum { 1257 u8 flags; 1258 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1259 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1260 u8 rsvd; 1261 __le16 checksum; /* Used only by response */ 1262 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1263 u8 rsvd2[12]; 1264 }; 1265 1266 /* The result of netlist NVM read comes in a TLV format. The actual data 1267 * (netlist header) starts from word offset 1 (byte 2). The FW strips 1268 * out the type field from the TLV header so all the netlist fields 1269 * should adjust their offset value by 1 word (2 bytes) in order to map 1270 * their correct location. 1271 */ 1272 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B 1273 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1 1274 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */ 1275 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2 1276 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */ 1277 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_M ICE_M(0x3FF, 0) 1278 #define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5 1279 #define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */ 1280 1281 /* netlist ID block field offsets (word offsets) */ 1282 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2 1283 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3 1284 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4 1285 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5 1286 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6 1287 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7 1288 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8 1289 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9 1290 #define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA 1291 #define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F 1292 1293 /** 1294 * Send to PF command (indirect 0x0801) ID is only used by PF 1295 * 1296 * Send to VF command (indirect 0x0802) ID is only used by PF 1297 * 1298 */ 1299 struct ice_aqc_pf_vf_msg { 1300 __le32 id; 1301 u32 reserved; 1302 __le32 addr_high; 1303 __le32 addr_low; 1304 }; 1305 1306 /* Get LLDP MIB (indirect 0x0A00) 1307 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1308 * as the format is the same. 1309 */ 1310 struct ice_aqc_lldp_get_mib { 1311 u8 type; 1312 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1313 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1314 #define ICE_AQ_LLDP_MIB_LOCAL 0 1315 #define ICE_AQ_LLDP_MIB_REMOTE 1 1316 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1317 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1318 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1319 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1320 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1321 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1322 #define ICE_AQ_LLDP_TX_S 0x4 1323 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1324 #define ICE_AQ_LLDP_TX_ACTIVE 0 1325 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1326 #define ICE_AQ_LLDP_TX_FLUSHED 3 1327 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1328 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1329 * Get LLDP MIB (0x0A00) response only. 1330 */ 1331 u8 reserved1; 1332 __le16 local_len; 1333 __le16 remote_len; 1334 u8 reserved2[2]; 1335 __le32 addr_high; 1336 __le32 addr_low; 1337 }; 1338 1339 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1340 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1341 struct ice_aqc_lldp_set_mib_change { 1342 u8 command; 1343 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1344 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1345 u8 reserved[15]; 1346 }; 1347 1348 /* Stop LLDP (direct 0x0A05) */ 1349 struct ice_aqc_lldp_stop { 1350 u8 command; 1351 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1352 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1353 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1354 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1355 u8 reserved[15]; 1356 }; 1357 1358 /* Start LLDP (direct 0x0A06) */ 1359 struct ice_aqc_lldp_start { 1360 u8 command; 1361 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1362 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1363 u8 reserved[15]; 1364 }; 1365 1366 /* Get CEE DCBX Oper Config (0x0A07) 1367 * The command uses the generic descriptor struct and 1368 * returns the struct below as an indirect response. 1369 */ 1370 struct ice_aqc_get_cee_dcb_cfg_resp { 1371 u8 oper_num_tc; 1372 u8 oper_prio_tc[4]; 1373 u8 oper_tc_bw[8]; 1374 u8 oper_pfc_en; 1375 __le16 oper_app_prio; 1376 #define ICE_AQC_CEE_APP_FCOE_S 0 1377 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1378 #define ICE_AQC_CEE_APP_ISCSI_S 3 1379 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1380 #define ICE_AQC_CEE_APP_FIP_S 8 1381 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1382 __le32 tlv_status; 1383 #define ICE_AQC_CEE_PG_STATUS_S 0 1384 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1385 #define ICE_AQC_CEE_PFC_STATUS_S 3 1386 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1387 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1388 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1389 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1390 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1391 #define ICE_AQC_CEE_FIP_STATUS_S 16 1392 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1393 u8 reserved[12]; 1394 }; 1395 1396 /* Set Local LLDP MIB (indirect 0x0A08) 1397 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1398 */ 1399 struct ice_aqc_lldp_set_local_mib { 1400 u8 type; 1401 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1402 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1403 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1404 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1405 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1406 u8 reserved0; 1407 __le16 length; 1408 u8 reserved1[4]; 1409 __le32 addr_high; 1410 __le32 addr_low; 1411 }; 1412 1413 /* Stop/Start LLDP Agent (direct 0x0A09) 1414 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1415 * The same structure is used for the response, with the command field 1416 * being used as the status field. 1417 */ 1418 struct ice_aqc_lldp_stop_start_specific_agent { 1419 u8 command; 1420 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1421 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1422 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1423 u8 reserved[15]; 1424 }; 1425 1426 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1427 struct ice_aqc_get_set_rss_key { 1428 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1429 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1430 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1431 __le16 vsi_id; 1432 u8 reserved[6]; 1433 __le32 addr_high; 1434 __le32 addr_low; 1435 }; 1436 1437 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1438 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1439 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1440 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1441 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1442 1443 struct ice_aqc_get_set_rss_keys { 1444 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1445 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1446 }; 1447 1448 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1449 struct ice_aqc_get_set_rss_lut { 1450 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1451 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1452 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1453 __le16 vsi_id; 1454 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1455 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1456 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1457 1458 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1459 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1460 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1461 1462 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1463 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1464 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1465 1466 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1467 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1468 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1469 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1470 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1471 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1472 1473 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1474 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1475 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1476 1477 __le16 flags; 1478 __le32 reserved; 1479 __le32 addr_high; 1480 __le32 addr_low; 1481 }; 1482 1483 /* Add Tx LAN Queues (indirect 0x0C30) */ 1484 struct ice_aqc_add_txqs { 1485 u8 num_qgrps; 1486 u8 reserved[3]; 1487 __le32 reserved1; 1488 __le32 addr_high; 1489 __le32 addr_low; 1490 }; 1491 1492 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1493 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1494 */ 1495 struct ice_aqc_add_txqs_perq { 1496 __le16 txq_id; 1497 u8 rsvd[2]; 1498 __le32 q_teid; 1499 u8 txq_ctx[22]; 1500 u8 rsvd2[2]; 1501 struct ice_aqc_txsched_elem info; 1502 }; 1503 1504 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 1505 * is an array of the following structs. Please note that the length of 1506 * each struct ice_aqc_add_tx_qgrp is variable due 1507 * to the variable number of queues in each group! 1508 */ 1509 struct ice_aqc_add_tx_qgrp { 1510 __le32 parent_teid; 1511 u8 num_txqs; 1512 u8 rsvd[3]; 1513 struct ice_aqc_add_txqs_perq txqs[]; 1514 }; 1515 1516 /* Disable Tx LAN Queues (indirect 0x0C31) */ 1517 struct ice_aqc_dis_txqs { 1518 u8 cmd_type; 1519 #define ICE_AQC_Q_DIS_CMD_S 0 1520 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1521 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1522 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1523 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1524 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1525 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1526 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1527 u8 num_entries; 1528 __le16 vmvf_and_timeout; 1529 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1530 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1531 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1532 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1533 __le32 blocked_cgds; 1534 __le32 addr_high; 1535 __le32 addr_low; 1536 }; 1537 1538 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 1539 * contains the following structures, arrayed one after the 1540 * other. 1541 * Note: Since the q_id is 16 bits wide, if the 1542 * number of queues is even, then 2 bytes of alignment MUST be 1543 * added before the start of the next group, to allow correct 1544 * alignment of the parent_teid field. 1545 */ 1546 struct ice_aqc_dis_txq_item { 1547 __le32 parent_teid; 1548 u8 num_qs; 1549 u8 rsvd; 1550 /* The length of the q_id array varies according to num_qs */ 1551 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1552 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1553 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1554 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1555 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1556 __le16 q_id[]; 1557 } __packed; 1558 1559 /* Configure Firmware Logging Command (indirect 0xFF09) 1560 * Logging Information Read Response (indirect 0xFF10) 1561 * Note: The 0xFF10 command has no input parameters. 1562 */ 1563 struct ice_aqc_fw_logging { 1564 u8 log_ctrl; 1565 #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 1566 #define ICE_AQC_FW_LOG_UART_EN BIT(1) 1567 u8 rsvd0; 1568 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 1569 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 1570 #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 1571 u8 rsvd1[5]; 1572 __le32 addr_high; 1573 __le32 addr_low; 1574 }; 1575 1576 enum ice_aqc_fw_logging_mod { 1577 ICE_AQC_FW_LOG_ID_GENERAL = 0, 1578 ICE_AQC_FW_LOG_ID_CTRL, 1579 ICE_AQC_FW_LOG_ID_LINK, 1580 ICE_AQC_FW_LOG_ID_LINK_TOPO, 1581 ICE_AQC_FW_LOG_ID_DNL, 1582 ICE_AQC_FW_LOG_ID_I2C, 1583 ICE_AQC_FW_LOG_ID_SDP, 1584 ICE_AQC_FW_LOG_ID_MDIO, 1585 ICE_AQC_FW_LOG_ID_ADMINQ, 1586 ICE_AQC_FW_LOG_ID_HDMA, 1587 ICE_AQC_FW_LOG_ID_LLDP, 1588 ICE_AQC_FW_LOG_ID_DCBX, 1589 ICE_AQC_FW_LOG_ID_DCB, 1590 ICE_AQC_FW_LOG_ID_NETPROXY, 1591 ICE_AQC_FW_LOG_ID_NVM, 1592 ICE_AQC_FW_LOG_ID_AUTH, 1593 ICE_AQC_FW_LOG_ID_VPD, 1594 ICE_AQC_FW_LOG_ID_IOSF, 1595 ICE_AQC_FW_LOG_ID_PARSER, 1596 ICE_AQC_FW_LOG_ID_SW, 1597 ICE_AQC_FW_LOG_ID_SCHEDULER, 1598 ICE_AQC_FW_LOG_ID_TXQ, 1599 ICE_AQC_FW_LOG_ID_RSVD, 1600 ICE_AQC_FW_LOG_ID_POST, 1601 ICE_AQC_FW_LOG_ID_WATCHDOG, 1602 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 1603 ICE_AQC_FW_LOG_ID_MNG, 1604 ICE_AQC_FW_LOG_ID_MAX, 1605 }; 1606 1607 /* Defines for both above FW logging command/response buffers */ 1608 #define ICE_AQC_FW_LOG_ID_S 0 1609 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 1610 1611 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 1612 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 1613 1614 #define ICE_AQC_FW_LOG_EN_S 12 1615 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 1616 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 1617 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 1618 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 1619 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 1620 1621 /* Get/Clear FW Log (indirect 0xFF11) */ 1622 struct ice_aqc_get_clear_fw_log { 1623 u8 flags; 1624 #define ICE_AQC_FW_LOG_CLEAR BIT(0) 1625 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 1626 u8 rsvd1[7]; 1627 __le32 addr_high; 1628 __le32 addr_low; 1629 }; 1630 1631 /* Download Package (indirect 0x0C40) */ 1632 /* Also used for Update Package (indirect 0x0C42) */ 1633 struct ice_aqc_download_pkg { 1634 u8 flags; 1635 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 1636 u8 reserved[3]; 1637 __le32 reserved1; 1638 __le32 addr_high; 1639 __le32 addr_low; 1640 }; 1641 1642 struct ice_aqc_download_pkg_resp { 1643 __le32 error_offset; 1644 __le32 error_info; 1645 __le32 addr_high; 1646 __le32 addr_low; 1647 }; 1648 1649 /* Get Package Info List (indirect 0x0C43) */ 1650 struct ice_aqc_get_pkg_info_list { 1651 __le32 reserved1; 1652 __le32 reserved2; 1653 __le32 addr_high; 1654 __le32 addr_low; 1655 }; 1656 1657 /* Version format for packages */ 1658 struct ice_pkg_ver { 1659 u8 major; 1660 u8 minor; 1661 u8 update; 1662 u8 draft; 1663 }; 1664 1665 #define ICE_PKG_NAME_SIZE 32 1666 #define ICE_SEG_NAME_SIZE 28 1667 1668 struct ice_aqc_get_pkg_info { 1669 struct ice_pkg_ver ver; 1670 char name[ICE_SEG_NAME_SIZE]; 1671 __le32 track_id; 1672 u8 is_in_nvm; 1673 u8 is_active; 1674 u8 is_active_at_boot; 1675 u8 is_modified; 1676 }; 1677 1678 /* Get Package Info List response buffer format (0x0C43) */ 1679 struct ice_aqc_get_pkg_info_resp { 1680 __le32 count; 1681 struct ice_aqc_get_pkg_info pkg_info[]; 1682 }; 1683 1684 /* Lan Queue Overflow Event (direct, 0x1001) */ 1685 struct ice_aqc_event_lan_overflow { 1686 __le32 prtdcb_ruptq; 1687 __le32 qtx_ctl; 1688 u8 reserved[8]; 1689 }; 1690 1691 /** 1692 * struct ice_aq_desc - Admin Queue (AQ) descriptor 1693 * @flags: ICE_AQ_FLAG_* flags 1694 * @opcode: AQ command opcode 1695 * @datalen: length in bytes of indirect/external data buffer 1696 * @retval: return value from firmware 1697 * @cookie_h: opaque data high-half 1698 * @cookie_l: opaque data low-half 1699 * @params: command-specific parameters 1700 * 1701 * Descriptor format for commands the driver posts on the Admin Transmit Queue 1702 * (ATQ). The firmware writes back onto the command descriptor and returns 1703 * the result of the command. Asynchronous events that are not an immediate 1704 * result of the command are written to the Admin Receive Queue (ARQ) using 1705 * the same descriptor format. Descriptors are in little-endian notation with 1706 * 32-bit words. 1707 */ 1708 struct ice_aq_desc { 1709 __le16 flags; 1710 __le16 opcode; 1711 __le16 datalen; 1712 __le16 retval; 1713 __le32 cookie_high; 1714 __le32 cookie_low; 1715 union { 1716 u8 raw[16]; 1717 struct ice_aqc_generic generic; 1718 struct ice_aqc_get_ver get_ver; 1719 struct ice_aqc_driver_ver driver_ver; 1720 struct ice_aqc_q_shutdown q_shutdown; 1721 struct ice_aqc_req_res res_owner; 1722 struct ice_aqc_manage_mac_read mac_read; 1723 struct ice_aqc_manage_mac_write mac_write; 1724 struct ice_aqc_clear_pxe clear_pxe; 1725 struct ice_aqc_list_caps get_cap; 1726 struct ice_aqc_get_phy_caps get_phy; 1727 struct ice_aqc_set_phy_cfg set_phy; 1728 struct ice_aqc_restart_an restart_an; 1729 struct ice_aqc_sff_eeprom read_write_sff_param; 1730 struct ice_aqc_set_port_id_led set_port_id_led; 1731 struct ice_aqc_get_sw_cfg get_sw_conf; 1732 struct ice_aqc_sw_rules sw_rules; 1733 struct ice_aqc_get_topo get_topo; 1734 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 1735 struct ice_aqc_query_txsched_res query_sched_res; 1736 struct ice_aqc_query_port_ets port_ets; 1737 struct ice_aqc_rl_profile rl_profile; 1738 struct ice_aqc_nvm nvm; 1739 struct ice_aqc_nvm_checksum nvm_checksum; 1740 struct ice_aqc_pf_vf_msg virt; 1741 struct ice_aqc_lldp_get_mib lldp_get_mib; 1742 struct ice_aqc_lldp_set_mib_change lldp_set_event; 1743 struct ice_aqc_lldp_stop lldp_stop; 1744 struct ice_aqc_lldp_start lldp_start; 1745 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 1746 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 1747 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 1748 struct ice_aqc_get_set_rss_key get_set_rss_key; 1749 struct ice_aqc_add_txqs add_txqs; 1750 struct ice_aqc_dis_txqs dis_txqs; 1751 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 1752 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 1753 struct ice_aqc_fw_logging fw_logging; 1754 struct ice_aqc_get_clear_fw_log get_clear_fw_log; 1755 struct ice_aqc_download_pkg download_pkg; 1756 struct ice_aqc_set_mac_lb set_mac_lb; 1757 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 1758 struct ice_aqc_set_mac_cfg set_mac_cfg; 1759 struct ice_aqc_set_event_mask set_event_mask; 1760 struct ice_aqc_get_link_status get_link_status; 1761 struct ice_aqc_event_lan_overflow lan_overflow; 1762 } params; 1763 }; 1764 1765 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 1766 #define ICE_AQ_LG_BUF 512 1767 1768 #define ICE_AQ_FLAG_ERR_S 2 1769 #define ICE_AQ_FLAG_LB_S 9 1770 #define ICE_AQ_FLAG_RD_S 10 1771 #define ICE_AQ_FLAG_BUF_S 12 1772 #define ICE_AQ_FLAG_SI_S 13 1773 1774 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 1775 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 1776 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 1777 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 1778 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 1779 1780 /* error codes */ 1781 enum ice_aq_err { 1782 ICE_AQ_RC_OK = 0, /* Success */ 1783 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 1784 ICE_AQ_RC_ENOENT = 2, /* No such element */ 1785 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 1786 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1787 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 1788 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 1789 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 1790 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 1791 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 1792 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 1793 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 1794 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 1795 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 1796 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 1797 }; 1798 1799 /* Admin Queue command opcodes */ 1800 enum ice_adminq_opc { 1801 /* AQ commands */ 1802 ice_aqc_opc_get_ver = 0x0001, 1803 ice_aqc_opc_driver_ver = 0x0002, 1804 ice_aqc_opc_q_shutdown = 0x0003, 1805 1806 /* resource ownership */ 1807 ice_aqc_opc_req_res = 0x0008, 1808 ice_aqc_opc_release_res = 0x0009, 1809 1810 /* device/function capabilities */ 1811 ice_aqc_opc_list_func_caps = 0x000A, 1812 ice_aqc_opc_list_dev_caps = 0x000B, 1813 1814 /* manage MAC address */ 1815 ice_aqc_opc_manage_mac_read = 0x0107, 1816 ice_aqc_opc_manage_mac_write = 0x0108, 1817 1818 /* PXE */ 1819 ice_aqc_opc_clear_pxe_mode = 0x0110, 1820 1821 /* internal switch commands */ 1822 ice_aqc_opc_get_sw_cfg = 0x0200, 1823 1824 /* Alloc/Free/Get Resources */ 1825 ice_aqc_opc_alloc_res = 0x0208, 1826 ice_aqc_opc_free_res = 0x0209, 1827 1828 /* VSI commands */ 1829 ice_aqc_opc_add_vsi = 0x0210, 1830 ice_aqc_opc_update_vsi = 0x0211, 1831 ice_aqc_opc_free_vsi = 0x0213, 1832 1833 /* switch rules population commands */ 1834 ice_aqc_opc_add_sw_rules = 0x02A0, 1835 ice_aqc_opc_update_sw_rules = 0x02A1, 1836 ice_aqc_opc_remove_sw_rules = 0x02A2, 1837 1838 ice_aqc_opc_clear_pf_cfg = 0x02A4, 1839 1840 /* transmit scheduler commands */ 1841 ice_aqc_opc_get_dflt_topo = 0x0400, 1842 ice_aqc_opc_add_sched_elems = 0x0401, 1843 ice_aqc_opc_cfg_sched_elems = 0x0403, 1844 ice_aqc_opc_get_sched_elems = 0x0404, 1845 ice_aqc_opc_suspend_sched_elems = 0x0409, 1846 ice_aqc_opc_resume_sched_elems = 0x040A, 1847 ice_aqc_opc_query_port_ets = 0x040E, 1848 ice_aqc_opc_delete_sched_elems = 0x040F, 1849 ice_aqc_opc_add_rl_profiles = 0x0410, 1850 ice_aqc_opc_query_sched_res = 0x0412, 1851 ice_aqc_opc_remove_rl_profiles = 0x0415, 1852 1853 /* PHY commands */ 1854 ice_aqc_opc_get_phy_caps = 0x0600, 1855 ice_aqc_opc_set_phy_cfg = 0x0601, 1856 ice_aqc_opc_set_mac_cfg = 0x0603, 1857 ice_aqc_opc_restart_an = 0x0605, 1858 ice_aqc_opc_get_link_status = 0x0607, 1859 ice_aqc_opc_set_event_mask = 0x0613, 1860 ice_aqc_opc_set_mac_lb = 0x0620, 1861 ice_aqc_opc_set_port_id_led = 0x06E9, 1862 ice_aqc_opc_sff_eeprom = 0x06EE, 1863 1864 /* NVM commands */ 1865 ice_aqc_opc_nvm_read = 0x0701, 1866 ice_aqc_opc_nvm_checksum = 0x0706, 1867 1868 /* PF/VF mailbox commands */ 1869 ice_mbx_opc_send_msg_to_pf = 0x0801, 1870 ice_mbx_opc_send_msg_to_vf = 0x0802, 1871 /* LLDP commands */ 1872 ice_aqc_opc_lldp_get_mib = 0x0A00, 1873 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 1874 ice_aqc_opc_lldp_stop = 0x0A05, 1875 ice_aqc_opc_lldp_start = 0x0A06, 1876 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 1877 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 1878 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 1879 1880 /* RSS commands */ 1881 ice_aqc_opc_set_rss_key = 0x0B02, 1882 ice_aqc_opc_set_rss_lut = 0x0B03, 1883 ice_aqc_opc_get_rss_key = 0x0B04, 1884 ice_aqc_opc_get_rss_lut = 0x0B05, 1885 1886 /* Tx queue handling commands/events */ 1887 ice_aqc_opc_add_txqs = 0x0C30, 1888 ice_aqc_opc_dis_txqs = 0x0C31, 1889 1890 /* package commands */ 1891 ice_aqc_opc_download_pkg = 0x0C40, 1892 ice_aqc_opc_update_pkg = 0x0C42, 1893 ice_aqc_opc_get_pkg_info_list = 0x0C43, 1894 1895 /* Standalone Commands/Events */ 1896 ice_aqc_opc_event_lan_overflow = 0x1001, 1897 1898 /* debug commands */ 1899 ice_aqc_opc_fw_logging = 0xFF09, 1900 ice_aqc_opc_fw_logging_info = 0xFF10, 1901 }; 1902 1903 #endif /* _ICE_ADMINQ_CMD_H_ */ 1904