1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 struct ice_aqc_generic { 16 __le32 param0; 17 __le32 param1; 18 __le32 addr_high; 19 __le32 addr_low; 20 }; 21 22 /* Get version (direct 0x0001) */ 23 struct ice_aqc_get_ver { 24 __le32 rom_ver; 25 __le32 fw_build; 26 u8 fw_branch; 27 u8 fw_major; 28 u8 fw_minor; 29 u8 fw_patch; 30 u8 api_branch; 31 u8 api_major; 32 u8 api_minor; 33 u8 api_patch; 34 }; 35 36 /* Send driver version (indirect 0x0002) */ 37 struct ice_aqc_driver_ver { 38 u8 major_ver; 39 u8 minor_ver; 40 u8 build_ver; 41 u8 subbuild_ver; 42 u8 reserved[4]; 43 __le32 addr_high; 44 __le32 addr_low; 45 }; 46 47 /* Queue Shutdown (direct 0x0003) */ 48 struct ice_aqc_q_shutdown { 49 u8 driver_unloading; 50 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 51 u8 reserved[15]; 52 }; 53 54 /* Request resource ownership (direct 0x0008) 55 * Release resource ownership (direct 0x0009) 56 */ 57 struct ice_aqc_req_res { 58 __le16 res_id; 59 #define ICE_AQC_RES_ID_NVM 1 60 #define ICE_AQC_RES_ID_SDP 2 61 #define ICE_AQC_RES_ID_CHNG_LOCK 3 62 #define ICE_AQC_RES_ID_GLBL_LOCK 4 63 __le16 access_type; 64 #define ICE_AQC_RES_ACCESS_READ 1 65 #define ICE_AQC_RES_ACCESS_WRITE 2 66 67 /* Upon successful completion, FW writes this value and driver is 68 * expected to release resource before timeout. This value is provided 69 * in milliseconds. 70 */ 71 __le32 timeout; 72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 76 /* For SDP: pin ID of the SDP */ 77 __le32 res_number; 78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 79 __le16 status; 80 #define ICE_AQ_RES_GLBL_SUCCESS 0 81 #define ICE_AQ_RES_GLBL_IN_PROG 1 82 #define ICE_AQ_RES_GLBL_DONE 2 83 u8 reserved[2]; 84 }; 85 86 /* Get function capabilities (indirect 0x000A) 87 * Get device capabilities (indirect 0x000B) 88 */ 89 struct ice_aqc_list_caps { 90 u8 cmd_flags; 91 u8 pf_index; 92 u8 reserved[2]; 93 __le32 count; 94 __le32 addr_high; 95 __le32 addr_low; 96 }; 97 98 /* Device/Function buffer entry, repeated per reported capability */ 99 struct ice_aqc_list_caps_elem { 100 __le16 cap; 101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 102 #define ICE_AQC_CAPS_SRIOV 0x0012 103 #define ICE_AQC_CAPS_VF 0x0013 104 #define ICE_AQC_CAPS_VSI 0x0017 105 #define ICE_AQC_CAPS_DCB 0x0018 106 #define ICE_AQC_CAPS_RSS 0x0040 107 #define ICE_AQC_CAPS_RXQS 0x0041 108 #define ICE_AQC_CAPS_TXQS 0x0042 109 #define ICE_AQC_CAPS_MSIX 0x0043 110 #define ICE_AQC_CAPS_FD 0x0045 111 #define ICE_AQC_CAPS_MAX_MTU 0x0047 112 113 u8 major_ver; 114 u8 minor_ver; 115 /* Number of resources described by this capability */ 116 __le32 number; 117 /* Only meaningful for some types of resources */ 118 __le32 logical_id; 119 /* Only meaningful for some types of resources */ 120 __le32 phys_id; 121 __le64 rsvd1; 122 __le64 rsvd2; 123 }; 124 125 /* Manage MAC address, read command - indirect (0x0107) 126 * This struct is also used for the response 127 */ 128 struct ice_aqc_manage_mac_read { 129 __le16 flags; /* Zeroed by device driver */ 130 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 131 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 132 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 133 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 134 #define ICE_AQC_MAN_MAC_READ_S 4 135 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 136 u8 rsvd[2]; 137 u8 num_addr; /* Used in response */ 138 u8 rsvd1[3]; 139 __le32 addr_high; 140 __le32 addr_low; 141 }; 142 143 /* Response buffer format for manage MAC read command */ 144 struct ice_aqc_manage_mac_read_resp { 145 u8 lport_num; 146 u8 addr_type; 147 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 148 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 149 u8 mac_addr[ETH_ALEN]; 150 }; 151 152 /* Manage MAC address, write command - direct (0x0108) */ 153 struct ice_aqc_manage_mac_write { 154 u8 rsvd; 155 u8 flags; 156 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 157 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 158 #define ICE_AQC_MAN_MAC_WR_S 6 159 #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S) 160 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 161 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 162 /* byte stream in network order */ 163 u8 mac_addr[ETH_ALEN]; 164 __le32 addr_high; 165 __le32 addr_low; 166 }; 167 168 /* Clear PXE Command and response (direct 0x0110) */ 169 struct ice_aqc_clear_pxe { 170 u8 rx_cnt; 171 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 172 u8 reserved[15]; 173 }; 174 175 /* Get switch configuration (0x0200) */ 176 struct ice_aqc_get_sw_cfg { 177 /* Reserved for command and copy of request flags for response */ 178 __le16 flags; 179 /* First desc in case of command and next_elem in case of response 180 * In case of response, if it is not zero, means all the configuration 181 * was not returned and new command shall be sent with this value in 182 * the 'first desc' field 183 */ 184 __le16 element; 185 /* Reserved for command, only used for response */ 186 __le16 num_elems; 187 __le16 rsvd; 188 __le32 addr_high; 189 __le32 addr_low; 190 }; 191 192 /* Each entry in the response buffer is of the following type: */ 193 struct ice_aqc_get_sw_cfg_resp_elem { 194 /* VSI/Port Number */ 195 __le16 vsi_port_num; 196 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 197 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 198 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 199 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 200 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 201 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 202 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 203 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 204 205 /* SWID VSI/Port belongs to */ 206 __le16 swid; 207 208 /* Bit 14..0 : PF/VF number VSI belongs to 209 * Bit 15 : VF indication bit 210 */ 211 __le16 pf_vf_num; 212 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 213 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 214 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 215 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 216 }; 217 218 /* These resource type defines are used for all switch resource 219 * commands where a resource type is required, such as: 220 * Get Resource Allocation command (indirect 0x0204) 221 * Allocate Resources command (indirect 0x0208) 222 * Free Resources command (indirect 0x0209) 223 * Get Allocated Resource Descriptors Command (indirect 0x020A) 224 */ 225 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 226 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 227 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 228 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 229 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 230 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 231 #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 232 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 233 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 234 235 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 236 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 237 238 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 239 240 #define ICE_AQC_RES_TYPE_S 0 241 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 242 243 /* Allocate Resources command (indirect 0x0208) 244 * Free Resources command (indirect 0x0209) 245 */ 246 struct ice_aqc_alloc_free_res_cmd { 247 __le16 num_entries; /* Number of Resource entries */ 248 u8 reserved[6]; 249 __le32 addr_high; 250 __le32 addr_low; 251 }; 252 253 /* Resource descriptor */ 254 struct ice_aqc_res_elem { 255 union { 256 __le16 sw_resp; 257 __le16 flu_resp; 258 } e; 259 }; 260 261 /* Buffer for Allocate/Free Resources commands */ 262 struct ice_aqc_alloc_free_res_elem { 263 __le16 res_type; /* Types defined above cmd 0x0204 */ 264 #define ICE_AQC_RES_TYPE_SHARED_S 7 265 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 266 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 267 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 268 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 269 __le16 num_elems; 270 struct ice_aqc_res_elem elem[]; 271 }; 272 273 /* Add VSI (indirect 0x0210) 274 * Update VSI (indirect 0x0211) 275 * Get VSI (indirect 0x0212) 276 * Free VSI (indirect 0x0213) 277 */ 278 struct ice_aqc_add_get_update_free_vsi { 279 __le16 vsi_num; 280 #define ICE_AQ_VSI_NUM_S 0 281 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 282 #define ICE_AQ_VSI_IS_VALID BIT(15) 283 __le16 cmd_flags; 284 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 285 u8 vf_id; 286 u8 reserved; 287 __le16 vsi_flags; 288 #define ICE_AQ_VSI_TYPE_S 0 289 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 290 #define ICE_AQ_VSI_TYPE_VF 0x0 291 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 292 #define ICE_AQ_VSI_TYPE_PF 0x2 293 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 294 __le32 addr_high; 295 __le32 addr_low; 296 }; 297 298 /* Response descriptor for: 299 * Add VSI (indirect 0x0210) 300 * Update VSI (indirect 0x0211) 301 * Free VSI (indirect 0x0213) 302 */ 303 struct ice_aqc_add_update_free_vsi_resp { 304 __le16 vsi_num; 305 __le16 ext_status; 306 __le16 vsi_used; 307 __le16 vsi_free; 308 __le32 addr_high; 309 __le32 addr_low; 310 }; 311 312 struct ice_aqc_vsi_props { 313 __le16 valid_sections; 314 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 315 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 316 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 317 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 318 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 319 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 320 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 321 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 322 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 323 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 324 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 325 /* switch section */ 326 u8 sw_id; 327 u8 sw_flags; 328 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 329 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 330 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 331 u8 sw_flags2; 332 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 333 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 334 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 335 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 336 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 337 u8 veb_stat_id; 338 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 339 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 340 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 341 /* security section */ 342 u8 sec_flags; 343 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 344 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 345 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 346 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 347 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 348 u8 sec_reserved; 349 /* VLAN section */ 350 __le16 pvid; /* VLANS include priority bits */ 351 u8 pvlan_reserved[2]; 352 u8 vlan_flags; 353 #define ICE_AQ_VSI_VLAN_MODE_S 0 354 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 355 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 356 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 357 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 358 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 359 #define ICE_AQ_VSI_VLAN_EMOD_S 3 360 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 361 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 362 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 363 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 364 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 365 u8 pvlan_reserved2[3]; 366 /* ingress egress up sections */ 367 __le32 ingress_table; /* bitmap, 3 bits per up */ 368 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 369 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 370 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 371 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 372 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 373 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 374 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 375 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 376 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 377 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 378 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 379 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 380 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 381 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 382 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 383 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 384 __le32 egress_table; /* same defines as for ingress table */ 385 /* outer tags section */ 386 __le16 outer_tag; 387 u8 outer_tag_flags; 388 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 389 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 390 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 391 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 392 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 393 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 394 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 395 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 396 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 397 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 398 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 399 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 400 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 401 u8 outer_tag_reserved; 402 /* queue mapping section */ 403 __le16 mapping_flags; 404 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 405 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 406 __le16 q_mapping[16]; 407 #define ICE_AQ_VSI_Q_S 0 408 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 409 __le16 tc_mapping[8]; 410 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 411 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 412 #define ICE_AQ_VSI_TC_Q_NUM_S 11 413 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 414 /* queueing option section */ 415 u8 q_opt_rss; 416 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 417 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 418 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 419 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 420 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 421 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 422 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 423 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 424 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 425 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 426 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 427 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 428 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 429 u8 q_opt_tc; 430 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 431 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 432 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 433 u8 q_opt_flags; 434 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 435 u8 q_opt_reserved[3]; 436 /* outer up section */ 437 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 438 /* section 10 */ 439 __le16 sect_10_reserved; 440 /* flow director section */ 441 __le16 fd_options; 442 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 443 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 444 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 445 __le16 max_fd_fltr_dedicated; 446 __le16 max_fd_fltr_shared; 447 __le16 fd_def_q; 448 #define ICE_AQ_VSI_FD_DEF_Q_S 0 449 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 450 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 451 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 452 __le16 fd_report_opt; 453 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 454 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 455 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 456 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 457 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 458 /* PASID section */ 459 __le32 pasid_id; 460 #define ICE_AQ_VSI_PASID_ID_S 0 461 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 462 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 463 u8 reserved[24]; 464 }; 465 466 #define ICE_MAX_NUM_RECIPES 64 467 468 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 469 */ 470 struct ice_aqc_sw_rules { 471 /* ops: add switch rules, referring the number of rules. 472 * ops: update switch rules, referring the number of filters 473 * ops: remove switch rules, referring the entry index. 474 * ops: get switch rules, referring to the number of filters. 475 */ 476 __le16 num_rules_fltr_entry_index; 477 u8 reserved[6]; 478 __le32 addr_high; 479 __le32 addr_low; 480 }; 481 482 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 483 * This structures describes the lookup rules and associated actions. "index" 484 * is returned as part of a response to a successful Add command, and can be 485 * used to identify the rule for Update/Get/Remove commands. 486 */ 487 struct ice_sw_rule_lkup_rx_tx { 488 __le16 recipe_id; 489 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 490 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 491 __le16 src; 492 __le32 act; 493 494 /* Bit 0:1 - Action type */ 495 #define ICE_SINGLE_ACT_TYPE_S 0x00 496 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 497 498 /* Bit 2 - Loop back enable 499 * Bit 3 - LAN enable 500 */ 501 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 502 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 503 504 /* Action type = 0 - Forward to VSI or VSI list */ 505 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 506 507 #define ICE_SINGLE_ACT_VSI_ID_S 4 508 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 509 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 510 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 511 /* This bit needs to be set if action is forward to VSI list */ 512 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 513 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 514 #define ICE_SINGLE_ACT_DROP BIT(18) 515 516 /* Action type = 1 - Forward to Queue of Queue group */ 517 #define ICE_SINGLE_ACT_TO_Q 0x1 518 #define ICE_SINGLE_ACT_Q_INDEX_S 4 519 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 520 #define ICE_SINGLE_ACT_Q_REGION_S 15 521 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 522 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 523 524 /* Action type = 2 - Prune */ 525 #define ICE_SINGLE_ACT_PRUNE 0x2 526 #define ICE_SINGLE_ACT_EGRESS BIT(15) 527 #define ICE_SINGLE_ACT_INGRESS BIT(16) 528 #define ICE_SINGLE_ACT_PRUNET BIT(17) 529 /* Bit 18 should be set to 0 for this action */ 530 531 /* Action type = 2 - Pointer */ 532 #define ICE_SINGLE_ACT_PTR 0x2 533 #define ICE_SINGLE_ACT_PTR_VAL_S 4 534 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 535 /* Bit 18 should be set to 1 */ 536 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 537 538 /* Action type = 3 - Other actions. Last two bits 539 * are other action identifier 540 */ 541 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 542 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 543 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 544 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 545 546 /* Bit 17:18 - Defines other actions */ 547 /* Other action = 0 - Mirror VSI */ 548 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 549 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 550 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 551 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 552 553 /* Other action = 3 - Set Stat count */ 554 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 555 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 556 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 557 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 558 559 __le16 index; /* The index of the rule in the lookup table */ 560 /* Length and values of the header to be matched per recipe or 561 * lookup-type 562 */ 563 __le16 hdr_len; 564 u8 hdr[]; 565 }; 566 567 /* Add/Update/Remove large action command/response entry 568 * "index" is returned as part of a response to a successful Add command, and 569 * can be used to identify the action for Update/Get/Remove commands. 570 */ 571 struct ice_sw_rule_lg_act { 572 __le16 index; /* Index in large action table */ 573 __le16 size; 574 /* Max number of large actions */ 575 #define ICE_MAX_LG_ACT 4 576 /* Bit 0:1 - Action type */ 577 #define ICE_LG_ACT_TYPE_S 0 578 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 579 580 /* Action type = 0 - Forward to VSI or VSI list */ 581 #define ICE_LG_ACT_VSI_FORWARDING 0 582 #define ICE_LG_ACT_VSI_ID_S 3 583 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 584 #define ICE_LG_ACT_VSI_LIST_ID_S 3 585 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 586 /* This bit needs to be set if action is forward to VSI list */ 587 #define ICE_LG_ACT_VSI_LIST BIT(13) 588 589 #define ICE_LG_ACT_VALID_BIT BIT(16) 590 591 /* Action type = 1 - Forward to Queue of Queue group */ 592 #define ICE_LG_ACT_TO_Q 0x1 593 #define ICE_LG_ACT_Q_INDEX_S 3 594 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 595 #define ICE_LG_ACT_Q_REGION_S 14 596 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 597 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 598 599 /* Action type = 2 - Prune */ 600 #define ICE_LG_ACT_PRUNE 0x2 601 #define ICE_LG_ACT_EGRESS BIT(14) 602 #define ICE_LG_ACT_INGRESS BIT(15) 603 #define ICE_LG_ACT_PRUNET BIT(16) 604 605 /* Action type = 3 - Mirror VSI */ 606 #define ICE_LG_OTHER_ACT_MIRROR 0x3 607 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 608 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 609 610 /* Action type = 5 - Generic Value */ 611 #define ICE_LG_ACT_GENERIC 0x5 612 #define ICE_LG_ACT_GENERIC_VALUE_S 3 613 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 614 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 615 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 616 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 617 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 618 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 619 620 /* Action = 7 - Set Stat count */ 621 #define ICE_LG_ACT_STAT_COUNT 0x7 622 #define ICE_LG_ACT_STAT_COUNT_S 3 623 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 624 __le32 act[]; /* array of size for actions */ 625 }; 626 627 /* Add/Update/Remove VSI list command/response entry 628 * "index" is returned as part of a response to a successful Add command, and 629 * can be used to identify the VSI list for Update/Get/Remove commands. 630 */ 631 struct ice_sw_rule_vsi_list { 632 __le16 index; /* Index of VSI/Prune list */ 633 __le16 number_vsi; 634 __le16 vsi[]; /* Array of number_vsi VSI numbers */ 635 }; 636 637 /* Query VSI list command/response entry */ 638 struct ice_sw_rule_vsi_list_query { 639 __le16 index; 640 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI); 641 } __packed; 642 643 /* Add switch rule response: 644 * Content of return buffer is same as the input buffer. The status field and 645 * LUT index are updated as part of the response 646 */ 647 struct ice_aqc_sw_rules_elem { 648 __le16 type; /* Switch rule type, one of T_... */ 649 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 650 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 651 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 652 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 653 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 654 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 655 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 656 __le16 status; 657 union { 658 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 659 struct ice_sw_rule_lg_act lg_act; 660 struct ice_sw_rule_vsi_list vsi_list; 661 struct ice_sw_rule_vsi_list_query vsi_list_query; 662 } __packed pdata; 663 }; 664 665 /* Get Default Topology (indirect 0x0400) */ 666 struct ice_aqc_get_topo { 667 u8 port_num; 668 u8 num_branches; 669 __le16 reserved1; 670 __le32 reserved2; 671 __le32 addr_high; 672 __le32 addr_low; 673 }; 674 675 /* Update TSE (indirect 0x0403) 676 * Get TSE (indirect 0x0404) 677 * Add TSE (indirect 0x0401) 678 * Delete TSE (indirect 0x040F) 679 * Move TSE (indirect 0x0408) 680 * Suspend Nodes (indirect 0x0409) 681 * Resume Nodes (indirect 0x040A) 682 */ 683 struct ice_aqc_sched_elem_cmd { 684 __le16 num_elem_req; /* Used by commands */ 685 __le16 num_elem_resp; /* Used by responses */ 686 __le32 reserved; 687 __le32 addr_high; 688 __le32 addr_low; 689 }; 690 691 struct ice_aqc_elem_info_bw { 692 __le16 bw_profile_idx; 693 __le16 bw_alloc; 694 }; 695 696 struct ice_aqc_txsched_elem { 697 u8 elem_type; /* Special field, reserved for some aq calls */ 698 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 699 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 700 #define ICE_AQC_ELEM_TYPE_TC 0x2 701 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 702 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 703 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 704 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 705 u8 valid_sections; 706 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 707 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 708 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 709 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 710 u8 generic; 711 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 712 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 713 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 714 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 715 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 716 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 717 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 718 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 719 u8 flags; /* Special field, reserved for some aq calls */ 720 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 721 struct ice_aqc_elem_info_bw cir_bw; 722 struct ice_aqc_elem_info_bw eir_bw; 723 __le16 srl_id; 724 __le16 reserved2; 725 }; 726 727 struct ice_aqc_txsched_elem_data { 728 __le32 parent_teid; 729 __le32 node_teid; 730 struct ice_aqc_txsched_elem data; 731 }; 732 733 struct ice_aqc_txsched_topo_grp_info_hdr { 734 __le32 parent_teid; 735 __le16 num_elems; 736 __le16 reserved2; 737 }; 738 739 struct ice_aqc_add_elem { 740 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 741 struct ice_aqc_txsched_elem_data generic[]; 742 }; 743 744 struct ice_aqc_get_topo_elem { 745 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 746 struct ice_aqc_txsched_elem_data 747 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 748 }; 749 750 struct ice_aqc_delete_elem { 751 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 752 __le32 teid[]; 753 }; 754 755 /* Query Port ETS (indirect 0x040E) 756 * 757 * This indirect command is used to query port TC node configuration. 758 */ 759 struct ice_aqc_query_port_ets { 760 __le32 port_teid; 761 __le32 reserved; 762 __le32 addr_high; 763 __le32 addr_low; 764 }; 765 766 struct ice_aqc_port_ets_elem { 767 u8 tc_valid_bits; 768 u8 reserved[3]; 769 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 770 __le32 up2tc; 771 u8 tc_bw_share[8]; 772 __le32 port_eir_prof_id; 773 __le32 port_cir_prof_id; 774 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 775 __le32 tc_node_prio; 776 #define ICE_TC_NODE_PRIO_S 0x4 777 u8 reserved1[4]; 778 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 779 }; 780 781 /* Rate limiting profile for 782 * Add RL profile (indirect 0x0410) 783 * Query RL profile (indirect 0x0411) 784 * Remove RL profile (indirect 0x0415) 785 * These indirect commands acts on single or multiple 786 * RL profiles with specified data. 787 */ 788 struct ice_aqc_rl_profile { 789 __le16 num_profiles; 790 __le16 num_processed; /* Only for response. Reserved in Command. */ 791 u8 reserved[4]; 792 __le32 addr_high; 793 __le32 addr_low; 794 }; 795 796 struct ice_aqc_rl_profile_elem { 797 u8 level; 798 u8 flags; 799 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 800 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 801 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 802 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 803 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 804 /* The following flag is used for Query RL Profile Data */ 805 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 806 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 807 808 __le16 profile_id; 809 __le16 max_burst_size; 810 __le16 rl_multiply; 811 __le16 wake_up_calc; 812 __le16 rl_encode; 813 }; 814 815 /* Query Scheduler Resource Allocation (indirect 0x0412) 816 * This indirect command retrieves the scheduler resources allocated by 817 * EMP Firmware to the given PF. 818 */ 819 struct ice_aqc_query_txsched_res { 820 u8 reserved[8]; 821 __le32 addr_high; 822 __le32 addr_low; 823 }; 824 825 struct ice_aqc_generic_sched_props { 826 __le16 phys_levels; 827 __le16 logical_levels; 828 u8 flattening_bitmap; 829 u8 max_device_cgds; 830 u8 max_pf_cgds; 831 u8 rsvd0; 832 __le16 rdma_qsets; 833 u8 rsvd1[22]; 834 }; 835 836 struct ice_aqc_layer_props { 837 u8 logical_layer; 838 u8 chunk_size; 839 __le16 max_device_nodes; 840 __le16 max_pf_nodes; 841 u8 rsvd0[4]; 842 __le16 max_sibl_grp_sz; 843 __le16 max_cir_rl_profiles; 844 __le16 max_eir_rl_profiles; 845 __le16 max_srl_profiles; 846 u8 rsvd1[14]; 847 }; 848 849 struct ice_aqc_query_txsched_res_resp { 850 struct ice_aqc_generic_sched_props sched_props; 851 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 852 }; 853 854 /* Get PHY capabilities (indirect 0x0600) */ 855 struct ice_aqc_get_phy_caps { 856 u8 lport_num; 857 u8 reserved; 858 __le16 param0; 859 /* 18.0 - Report qualified modules */ 860 #define ICE_AQC_GET_PHY_RQM BIT(0) 861 /* 18.1 - 18.2 : Report mode 862 * 00b - Report NVM capabilities 863 * 01b - Report topology capabilities 864 * 10b - Report SW configured 865 */ 866 #define ICE_AQC_REPORT_MODE_S 1 867 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 868 #define ICE_AQC_REPORT_NVM_CAP 0 869 #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 870 #define ICE_AQC_REPORT_SW_CFG BIT(2) 871 __le32 reserved1; 872 __le32 addr_high; 873 __le32 addr_low; 874 }; 875 876 /* This is #define of PHY type (Extended): 877 * The first set of defines is for phy_type_low. 878 */ 879 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 880 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 881 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 882 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 883 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 884 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 885 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 886 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 887 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 888 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 889 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 890 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 891 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 892 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 893 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 894 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 895 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 896 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 897 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 898 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 899 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 900 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 901 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 902 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 903 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 904 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 905 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 906 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 907 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 908 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 909 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 910 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 911 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 912 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 913 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 914 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 915 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 916 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 917 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 918 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 919 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 920 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 921 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 922 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 923 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 924 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 925 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 926 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 927 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 928 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 929 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 930 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 931 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 932 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 933 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 934 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 935 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 936 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 937 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 938 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 939 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 940 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 941 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 942 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 943 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 944 /* The second set of defines is for phy_type_high. */ 945 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 946 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 947 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 948 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 949 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 950 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 951 952 struct ice_aqc_get_phy_caps_data { 953 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 954 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 955 u8 caps; 956 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 957 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 958 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 959 #define ICE_AQC_PHY_EN_LINK BIT(3) 960 #define ICE_AQC_PHY_AN_MODE BIT(4) 961 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 962 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 963 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 964 u8 low_power_ctrl_an; 965 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 966 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 967 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 968 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 969 __le16 eee_cap; 970 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 971 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 972 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 973 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 974 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 975 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 976 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 977 __le16 eeer_value; 978 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 979 u8 phy_fw_ver[8]; 980 u8 link_fec_options; 981 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 982 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 983 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 984 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 985 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 986 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 987 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 988 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 989 u8 module_compliance_enforcement; 990 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 991 u8 extended_compliance_code; 992 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 993 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 994 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 995 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 996 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 997 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 998 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 999 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1000 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1001 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1002 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1003 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1004 u8 qualified_module_count; 1005 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1006 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1007 struct { 1008 u8 v_oui[3]; 1009 u8 rsvd3; 1010 u8 v_part[16]; 1011 __le32 v_rev; 1012 __le64 rsvd4; 1013 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1014 }; 1015 1016 /* Set PHY capabilities (direct 0x0601) 1017 * NOTE: This command must be followed by setup link and restart auto-neg 1018 */ 1019 struct ice_aqc_set_phy_cfg { 1020 u8 lport_num; 1021 u8 reserved[7]; 1022 __le32 addr_high; 1023 __le32 addr_low; 1024 }; 1025 1026 /* Set PHY config command data structure */ 1027 struct ice_aqc_set_phy_cfg_data { 1028 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1029 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1030 u8 caps; 1031 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1032 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1033 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1034 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1035 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1036 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1037 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1038 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1039 u8 low_power_ctrl_an; 1040 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1041 __le16 eeer_value; 1042 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1043 u8 module_compliance_enforcement; 1044 }; 1045 1046 /* Set MAC Config command data structure (direct 0x0603) */ 1047 struct ice_aqc_set_mac_cfg { 1048 __le16 max_frame_size; 1049 u8 params; 1050 #define ICE_AQ_SET_MAC_PACE_S 3 1051 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1052 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1053 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1054 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1055 u8 tx_tmr_priority; 1056 __le16 tx_tmr_value; 1057 __le16 fc_refresh_threshold; 1058 u8 drop_opts; 1059 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1060 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1061 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1062 u8 reserved[7]; 1063 }; 1064 1065 /* Restart AN command data structure (direct 0x0605) 1066 * Also used for response, with only the lport_num field present. 1067 */ 1068 struct ice_aqc_restart_an { 1069 u8 lport_num; 1070 u8 reserved; 1071 u8 cmd_flags; 1072 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1073 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1074 u8 reserved2[13]; 1075 }; 1076 1077 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1078 struct ice_aqc_get_link_status { 1079 u8 lport_num; 1080 u8 reserved; 1081 __le16 cmd_flags; 1082 #define ICE_AQ_LSE_M 0x3 1083 #define ICE_AQ_LSE_NOP 0x0 1084 #define ICE_AQ_LSE_DIS 0x2 1085 #define ICE_AQ_LSE_ENA 0x3 1086 /* only response uses this flag */ 1087 #define ICE_AQ_LSE_IS_ENABLED 0x1 1088 __le32 reserved2; 1089 __le32 addr_high; 1090 __le32 addr_low; 1091 }; 1092 1093 /* Get link status response data structure, also used for Link Status Event */ 1094 struct ice_aqc_get_link_status_data { 1095 u8 topo_media_conflict; 1096 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1097 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1098 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1099 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1100 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1101 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1102 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1103 u8 reserved1; 1104 u8 link_info; 1105 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1106 #define ICE_AQ_LINK_FAULT BIT(1) 1107 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1108 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1109 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1110 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1111 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1112 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1113 u8 an_info; 1114 #define ICE_AQ_AN_COMPLETED BIT(0) 1115 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1116 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1117 #define ICE_AQ_FEC_EN BIT(3) 1118 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1119 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1120 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1121 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1122 u8 ext_info; 1123 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1124 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1125 /* Port Tx Suspended */ 1126 #define ICE_AQ_LINK_TX_S 2 1127 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1128 #define ICE_AQ_LINK_TX_ACTIVE 0 1129 #define ICE_AQ_LINK_TX_DRAINED 1 1130 #define ICE_AQ_LINK_TX_FLUSHED 3 1131 u8 reserved2; 1132 __le16 max_frame_size; 1133 u8 cfg; 1134 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1135 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1136 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1137 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1138 /* Pacing Config */ 1139 #define ICE_AQ_CFG_PACING_S 3 1140 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1141 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1142 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1143 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1144 /* External Device Power Ability */ 1145 u8 power_desc; 1146 #define ICE_AQ_PWR_CLASS_M 0x3 1147 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1148 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1149 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1150 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1151 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1152 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1153 __le16 link_speed; 1154 #define ICE_AQ_LINK_SPEED_M 0x7FF 1155 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1156 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1157 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1158 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1159 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1160 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1161 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1162 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1163 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1164 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1165 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1166 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1167 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1168 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1169 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1170 }; 1171 1172 /* Set event mask command (direct 0x0613) */ 1173 struct ice_aqc_set_event_mask { 1174 u8 lport_num; 1175 u8 reserved[7]; 1176 __le16 event_mask; 1177 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1178 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1179 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1180 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1181 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1182 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1183 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1184 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1185 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1186 u8 reserved1[6]; 1187 }; 1188 1189 /* Set MAC Loopback command (direct 0x0620) */ 1190 struct ice_aqc_set_mac_lb { 1191 u8 lb_mode; 1192 #define ICE_AQ_MAC_LB_EN BIT(0) 1193 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1194 u8 reserved[15]; 1195 }; 1196 1197 struct ice_aqc_link_topo_addr { 1198 u8 lport_num; 1199 u8 lport_num_valid; 1200 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1201 u8 node_type_ctx; 1202 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1203 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1204 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1205 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1206 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1207 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1208 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1209 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1210 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1211 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1212 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1213 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1214 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1215 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1216 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1217 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1218 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1219 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1220 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1221 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1222 u8 index; 1223 __le16 handle; 1224 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1225 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1226 /* Used to decode the handle field */ 1227 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1228 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1229 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1230 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1231 /* In case of a Mezzanine type */ 1232 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1233 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1234 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1235 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1236 /* In case of a LOM type */ 1237 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1238 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1239 }; 1240 1241 /* Get Link Topology Handle (direct, 0x06E0) */ 1242 struct ice_aqc_get_link_topo { 1243 struct ice_aqc_link_topo_addr addr; 1244 u8 node_part_num; 1245 u8 rsvd[9]; 1246 }; 1247 1248 /* Set Port Identification LED (direct, 0x06E9) */ 1249 struct ice_aqc_set_port_id_led { 1250 u8 lport_num; 1251 u8 lport_num_valid; 1252 u8 ident_mode; 1253 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1254 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1255 u8 rsvd[13]; 1256 }; 1257 1258 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1259 struct ice_aqc_sff_eeprom { 1260 u8 lport_num; 1261 u8 lport_num_valid; 1262 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1263 __le16 i2c_bus_addr; 1264 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1265 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1266 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1267 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1268 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1269 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1270 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1271 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1272 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1273 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1274 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1275 __le16 i2c_mem_addr; 1276 __le16 eeprom_page; 1277 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1278 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1279 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1280 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1281 __le32 addr_high; 1282 __le32 addr_low; 1283 }; 1284 1285 /* NVM Read command (indirect 0x0701) 1286 * NVM Erase commands (direct 0x0702) 1287 * NVM Update commands (indirect 0x0703) 1288 */ 1289 struct ice_aqc_nvm { 1290 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 1291 __le16 offset_low; 1292 u8 offset_high; 1293 u8 cmd_flags; 1294 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1295 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1296 #define ICE_AQC_NVM_PRESERVATION_S 1 1297 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1298 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1299 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1300 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1301 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1302 __le16 module_typeid; 1303 __le16 length; 1304 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1305 __le32 addr_high; 1306 __le32 addr_low; 1307 }; 1308 1309 #define ICE_AQC_NVM_START_POINT 0 1310 1311 /* NVM Checksum Command (direct, 0x0706) */ 1312 struct ice_aqc_nvm_checksum { 1313 u8 flags; 1314 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 1315 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 1316 u8 rsvd; 1317 __le16 checksum; /* Used only by response */ 1318 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 1319 u8 rsvd2[12]; 1320 }; 1321 1322 /* The result of netlist NVM read comes in a TLV format. The actual data 1323 * (netlist header) starts from word offset 1 (byte 2). The FW strips 1324 * out the type field from the TLV header so all the netlist fields 1325 * should adjust their offset value by 1 word (2 bytes) in order to map 1326 * their correct location. 1327 */ 1328 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B 1329 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1 1330 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */ 1331 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2 1332 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */ 1333 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_M ICE_M(0x3FF, 0) 1334 #define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5 1335 #define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */ 1336 1337 /* netlist ID block field offsets (word offsets) */ 1338 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2 1339 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3 1340 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4 1341 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5 1342 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6 1343 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7 1344 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8 1345 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9 1346 #define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA 1347 #define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F 1348 1349 /** 1350 * Send to PF command (indirect 0x0801) ID is only used by PF 1351 * 1352 * Send to VF command (indirect 0x0802) ID is only used by PF 1353 * 1354 */ 1355 struct ice_aqc_pf_vf_msg { 1356 __le32 id; 1357 u32 reserved; 1358 __le32 addr_high; 1359 __le32 addr_low; 1360 }; 1361 1362 /* Get LLDP MIB (indirect 0x0A00) 1363 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 1364 * as the format is the same. 1365 */ 1366 struct ice_aqc_lldp_get_mib { 1367 u8 type; 1368 #define ICE_AQ_LLDP_MIB_TYPE_S 0 1369 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 1370 #define ICE_AQ_LLDP_MIB_LOCAL 0 1371 #define ICE_AQ_LLDP_MIB_REMOTE 1 1372 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 1373 #define ICE_AQ_LLDP_BRID_TYPE_S 2 1374 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 1375 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 1376 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 1377 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 1378 #define ICE_AQ_LLDP_TX_S 0x4 1379 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 1380 #define ICE_AQ_LLDP_TX_ACTIVE 0 1381 #define ICE_AQ_LLDP_TX_SUSPENDED 1 1382 #define ICE_AQ_LLDP_TX_FLUSHED 3 1383 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 1384 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 1385 * Get LLDP MIB (0x0A00) response only. 1386 */ 1387 u8 reserved1; 1388 __le16 local_len; 1389 __le16 remote_len; 1390 u8 reserved2[2]; 1391 __le32 addr_high; 1392 __le32 addr_low; 1393 }; 1394 1395 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 1396 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 1397 struct ice_aqc_lldp_set_mib_change { 1398 u8 command; 1399 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1400 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1401 u8 reserved[15]; 1402 }; 1403 1404 /* Stop LLDP (direct 0x0A05) */ 1405 struct ice_aqc_lldp_stop { 1406 u8 command; 1407 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 1408 #define ICE_AQ_LLDP_AGENT_STOP 0x0 1409 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 1410 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 1411 u8 reserved[15]; 1412 }; 1413 1414 /* Start LLDP (direct 0x0A06) */ 1415 struct ice_aqc_lldp_start { 1416 u8 command; 1417 #define ICE_AQ_LLDP_AGENT_START BIT(0) 1418 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 1419 u8 reserved[15]; 1420 }; 1421 1422 /* Get CEE DCBX Oper Config (0x0A07) 1423 * The command uses the generic descriptor struct and 1424 * returns the struct below as an indirect response. 1425 */ 1426 struct ice_aqc_get_cee_dcb_cfg_resp { 1427 u8 oper_num_tc; 1428 u8 oper_prio_tc[4]; 1429 u8 oper_tc_bw[8]; 1430 u8 oper_pfc_en; 1431 __le16 oper_app_prio; 1432 #define ICE_AQC_CEE_APP_FCOE_S 0 1433 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 1434 #define ICE_AQC_CEE_APP_ISCSI_S 3 1435 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 1436 #define ICE_AQC_CEE_APP_FIP_S 8 1437 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 1438 __le32 tlv_status; 1439 #define ICE_AQC_CEE_PG_STATUS_S 0 1440 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 1441 #define ICE_AQC_CEE_PFC_STATUS_S 3 1442 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 1443 #define ICE_AQC_CEE_FCOE_STATUS_S 8 1444 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 1445 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 1446 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 1447 #define ICE_AQC_CEE_FIP_STATUS_S 16 1448 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 1449 u8 reserved[12]; 1450 }; 1451 1452 /* Set Local LLDP MIB (indirect 0x0A08) 1453 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 1454 */ 1455 struct ice_aqc_lldp_set_local_mib { 1456 u8 type; 1457 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 1458 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 1459 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 1460 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 1461 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 1462 u8 reserved0; 1463 __le16 length; 1464 u8 reserved1[4]; 1465 __le32 addr_high; 1466 __le32 addr_low; 1467 }; 1468 1469 /* Stop/Start LLDP Agent (direct 0x0A09) 1470 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 1471 * The same structure is used for the response, with the command field 1472 * being used as the status field. 1473 */ 1474 struct ice_aqc_lldp_stop_start_specific_agent { 1475 u8 command; 1476 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 1477 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 1478 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 1479 u8 reserved[15]; 1480 }; 1481 1482 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1483 struct ice_aqc_get_set_rss_key { 1484 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1485 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1486 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1487 __le16 vsi_id; 1488 u8 reserved[6]; 1489 __le32 addr_high; 1490 __le32 addr_low; 1491 }; 1492 1493 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1494 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1495 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1496 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1497 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1498 1499 struct ice_aqc_get_set_rss_keys { 1500 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1501 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1502 }; 1503 1504 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1505 struct ice_aqc_get_set_rss_lut { 1506 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1507 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1508 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1509 __le16 vsi_id; 1510 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1511 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1512 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1513 1514 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1515 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1516 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1517 1518 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1519 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1520 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1521 1522 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1523 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1524 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1525 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1526 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1527 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1528 1529 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1530 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1531 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1532 1533 __le16 flags; 1534 __le32 reserved; 1535 __le32 addr_high; 1536 __le32 addr_low; 1537 }; 1538 1539 /* Add Tx LAN Queues (indirect 0x0C30) */ 1540 struct ice_aqc_add_txqs { 1541 u8 num_qgrps; 1542 u8 reserved[3]; 1543 __le32 reserved1; 1544 __le32 addr_high; 1545 __le32 addr_low; 1546 }; 1547 1548 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1549 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1550 */ 1551 struct ice_aqc_add_txqs_perq { 1552 __le16 txq_id; 1553 u8 rsvd[2]; 1554 __le32 q_teid; 1555 u8 txq_ctx[22]; 1556 u8 rsvd2[2]; 1557 struct ice_aqc_txsched_elem info; 1558 }; 1559 1560 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 1561 * is an array of the following structs. Please note that the length of 1562 * each struct ice_aqc_add_tx_qgrp is variable due 1563 * to the variable number of queues in each group! 1564 */ 1565 struct ice_aqc_add_tx_qgrp { 1566 __le32 parent_teid; 1567 u8 num_txqs; 1568 u8 rsvd[3]; 1569 struct ice_aqc_add_txqs_perq txqs[]; 1570 }; 1571 1572 /* Disable Tx LAN Queues (indirect 0x0C31) */ 1573 struct ice_aqc_dis_txqs { 1574 u8 cmd_type; 1575 #define ICE_AQC_Q_DIS_CMD_S 0 1576 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1577 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1578 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1579 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1580 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1581 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1582 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1583 u8 num_entries; 1584 __le16 vmvf_and_timeout; 1585 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1586 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1587 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1588 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1589 __le32 blocked_cgds; 1590 __le32 addr_high; 1591 __le32 addr_low; 1592 }; 1593 1594 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 1595 * contains the following structures, arrayed one after the 1596 * other. 1597 * Note: Since the q_id is 16 bits wide, if the 1598 * number of queues is even, then 2 bytes of alignment MUST be 1599 * added before the start of the next group, to allow correct 1600 * alignment of the parent_teid field. 1601 */ 1602 struct ice_aqc_dis_txq_item { 1603 __le32 parent_teid; 1604 u8 num_qs; 1605 u8 rsvd; 1606 /* The length of the q_id array varies according to num_qs */ 1607 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1608 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1609 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1610 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1611 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1612 __le16 q_id[]; 1613 } __packed; 1614 1615 /* Configure Firmware Logging Command (indirect 0xFF09) 1616 * Logging Information Read Response (indirect 0xFF10) 1617 * Note: The 0xFF10 command has no input parameters. 1618 */ 1619 struct ice_aqc_fw_logging { 1620 u8 log_ctrl; 1621 #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 1622 #define ICE_AQC_FW_LOG_UART_EN BIT(1) 1623 u8 rsvd0; 1624 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 1625 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 1626 #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 1627 u8 rsvd1[5]; 1628 __le32 addr_high; 1629 __le32 addr_low; 1630 }; 1631 1632 enum ice_aqc_fw_logging_mod { 1633 ICE_AQC_FW_LOG_ID_GENERAL = 0, 1634 ICE_AQC_FW_LOG_ID_CTRL, 1635 ICE_AQC_FW_LOG_ID_LINK, 1636 ICE_AQC_FW_LOG_ID_LINK_TOPO, 1637 ICE_AQC_FW_LOG_ID_DNL, 1638 ICE_AQC_FW_LOG_ID_I2C, 1639 ICE_AQC_FW_LOG_ID_SDP, 1640 ICE_AQC_FW_LOG_ID_MDIO, 1641 ICE_AQC_FW_LOG_ID_ADMINQ, 1642 ICE_AQC_FW_LOG_ID_HDMA, 1643 ICE_AQC_FW_LOG_ID_LLDP, 1644 ICE_AQC_FW_LOG_ID_DCBX, 1645 ICE_AQC_FW_LOG_ID_DCB, 1646 ICE_AQC_FW_LOG_ID_NETPROXY, 1647 ICE_AQC_FW_LOG_ID_NVM, 1648 ICE_AQC_FW_LOG_ID_AUTH, 1649 ICE_AQC_FW_LOG_ID_VPD, 1650 ICE_AQC_FW_LOG_ID_IOSF, 1651 ICE_AQC_FW_LOG_ID_PARSER, 1652 ICE_AQC_FW_LOG_ID_SW, 1653 ICE_AQC_FW_LOG_ID_SCHEDULER, 1654 ICE_AQC_FW_LOG_ID_TXQ, 1655 ICE_AQC_FW_LOG_ID_RSVD, 1656 ICE_AQC_FW_LOG_ID_POST, 1657 ICE_AQC_FW_LOG_ID_WATCHDOG, 1658 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 1659 ICE_AQC_FW_LOG_ID_MNG, 1660 ICE_AQC_FW_LOG_ID_MAX, 1661 }; 1662 1663 /* Defines for both above FW logging command/response buffers */ 1664 #define ICE_AQC_FW_LOG_ID_S 0 1665 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 1666 1667 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 1668 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 1669 1670 #define ICE_AQC_FW_LOG_EN_S 12 1671 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 1672 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 1673 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 1674 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 1675 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 1676 1677 /* Get/Clear FW Log (indirect 0xFF11) */ 1678 struct ice_aqc_get_clear_fw_log { 1679 u8 flags; 1680 #define ICE_AQC_FW_LOG_CLEAR BIT(0) 1681 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 1682 u8 rsvd1[7]; 1683 __le32 addr_high; 1684 __le32 addr_low; 1685 }; 1686 1687 /* Download Package (indirect 0x0C40) */ 1688 /* Also used for Update Package (indirect 0x0C42) */ 1689 struct ice_aqc_download_pkg { 1690 u8 flags; 1691 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 1692 u8 reserved[3]; 1693 __le32 reserved1; 1694 __le32 addr_high; 1695 __le32 addr_low; 1696 }; 1697 1698 struct ice_aqc_download_pkg_resp { 1699 __le32 error_offset; 1700 __le32 error_info; 1701 __le32 addr_high; 1702 __le32 addr_low; 1703 }; 1704 1705 /* Get Package Info List (indirect 0x0C43) */ 1706 struct ice_aqc_get_pkg_info_list { 1707 __le32 reserved1; 1708 __le32 reserved2; 1709 __le32 addr_high; 1710 __le32 addr_low; 1711 }; 1712 1713 /* Version format for packages */ 1714 struct ice_pkg_ver { 1715 u8 major; 1716 u8 minor; 1717 u8 update; 1718 u8 draft; 1719 }; 1720 1721 #define ICE_PKG_NAME_SIZE 32 1722 #define ICE_SEG_NAME_SIZE 28 1723 1724 struct ice_aqc_get_pkg_info { 1725 struct ice_pkg_ver ver; 1726 char name[ICE_SEG_NAME_SIZE]; 1727 __le32 track_id; 1728 u8 is_in_nvm; 1729 u8 is_active; 1730 u8 is_active_at_boot; 1731 u8 is_modified; 1732 }; 1733 1734 /* Get Package Info List response buffer format (0x0C43) */ 1735 struct ice_aqc_get_pkg_info_resp { 1736 __le32 count; 1737 struct ice_aqc_get_pkg_info pkg_info[]; 1738 }; 1739 1740 /* Lan Queue Overflow Event (direct, 0x1001) */ 1741 struct ice_aqc_event_lan_overflow { 1742 __le32 prtdcb_ruptq; 1743 __le32 qtx_ctl; 1744 u8 reserved[8]; 1745 }; 1746 1747 /** 1748 * struct ice_aq_desc - Admin Queue (AQ) descriptor 1749 * @flags: ICE_AQ_FLAG_* flags 1750 * @opcode: AQ command opcode 1751 * @datalen: length in bytes of indirect/external data buffer 1752 * @retval: return value from firmware 1753 * @cookie_h: opaque data high-half 1754 * @cookie_l: opaque data low-half 1755 * @params: command-specific parameters 1756 * 1757 * Descriptor format for commands the driver posts on the Admin Transmit Queue 1758 * (ATQ). The firmware writes back onto the command descriptor and returns 1759 * the result of the command. Asynchronous events that are not an immediate 1760 * result of the command are written to the Admin Receive Queue (ARQ) using 1761 * the same descriptor format. Descriptors are in little-endian notation with 1762 * 32-bit words. 1763 */ 1764 struct ice_aq_desc { 1765 __le16 flags; 1766 __le16 opcode; 1767 __le16 datalen; 1768 __le16 retval; 1769 __le32 cookie_high; 1770 __le32 cookie_low; 1771 union { 1772 u8 raw[16]; 1773 struct ice_aqc_generic generic; 1774 struct ice_aqc_get_ver get_ver; 1775 struct ice_aqc_driver_ver driver_ver; 1776 struct ice_aqc_q_shutdown q_shutdown; 1777 struct ice_aqc_req_res res_owner; 1778 struct ice_aqc_manage_mac_read mac_read; 1779 struct ice_aqc_manage_mac_write mac_write; 1780 struct ice_aqc_clear_pxe clear_pxe; 1781 struct ice_aqc_list_caps get_cap; 1782 struct ice_aqc_get_phy_caps get_phy; 1783 struct ice_aqc_set_phy_cfg set_phy; 1784 struct ice_aqc_restart_an restart_an; 1785 struct ice_aqc_sff_eeprom read_write_sff_param; 1786 struct ice_aqc_set_port_id_led set_port_id_led; 1787 struct ice_aqc_get_sw_cfg get_sw_conf; 1788 struct ice_aqc_sw_rules sw_rules; 1789 struct ice_aqc_get_topo get_topo; 1790 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 1791 struct ice_aqc_query_txsched_res query_sched_res; 1792 struct ice_aqc_query_port_ets port_ets; 1793 struct ice_aqc_rl_profile rl_profile; 1794 struct ice_aqc_nvm nvm; 1795 struct ice_aqc_nvm_checksum nvm_checksum; 1796 struct ice_aqc_pf_vf_msg virt; 1797 struct ice_aqc_lldp_get_mib lldp_get_mib; 1798 struct ice_aqc_lldp_set_mib_change lldp_set_event; 1799 struct ice_aqc_lldp_stop lldp_stop; 1800 struct ice_aqc_lldp_start lldp_start; 1801 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 1802 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 1803 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 1804 struct ice_aqc_get_set_rss_key get_set_rss_key; 1805 struct ice_aqc_add_txqs add_txqs; 1806 struct ice_aqc_dis_txqs dis_txqs; 1807 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 1808 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 1809 struct ice_aqc_fw_logging fw_logging; 1810 struct ice_aqc_get_clear_fw_log get_clear_fw_log; 1811 struct ice_aqc_download_pkg download_pkg; 1812 struct ice_aqc_set_mac_lb set_mac_lb; 1813 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 1814 struct ice_aqc_set_mac_cfg set_mac_cfg; 1815 struct ice_aqc_set_event_mask set_event_mask; 1816 struct ice_aqc_get_link_status get_link_status; 1817 struct ice_aqc_event_lan_overflow lan_overflow; 1818 struct ice_aqc_get_link_topo get_link_topo; 1819 } params; 1820 }; 1821 1822 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 1823 #define ICE_AQ_LG_BUF 512 1824 1825 #define ICE_AQ_FLAG_ERR_S 2 1826 #define ICE_AQ_FLAG_LB_S 9 1827 #define ICE_AQ_FLAG_RD_S 10 1828 #define ICE_AQ_FLAG_BUF_S 12 1829 #define ICE_AQ_FLAG_SI_S 13 1830 1831 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 1832 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 1833 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 1834 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 1835 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 1836 1837 /* error codes */ 1838 enum ice_aq_err { 1839 ICE_AQ_RC_OK = 0, /* Success */ 1840 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 1841 ICE_AQ_RC_ENOENT = 2, /* No such element */ 1842 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 1843 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1844 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 1845 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 1846 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 1847 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 1848 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 1849 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 1850 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 1851 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 1852 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 1853 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 1854 }; 1855 1856 /* Admin Queue command opcodes */ 1857 enum ice_adminq_opc { 1858 /* AQ commands */ 1859 ice_aqc_opc_get_ver = 0x0001, 1860 ice_aqc_opc_driver_ver = 0x0002, 1861 ice_aqc_opc_q_shutdown = 0x0003, 1862 1863 /* resource ownership */ 1864 ice_aqc_opc_req_res = 0x0008, 1865 ice_aqc_opc_release_res = 0x0009, 1866 1867 /* device/function capabilities */ 1868 ice_aqc_opc_list_func_caps = 0x000A, 1869 ice_aqc_opc_list_dev_caps = 0x000B, 1870 1871 /* manage MAC address */ 1872 ice_aqc_opc_manage_mac_read = 0x0107, 1873 ice_aqc_opc_manage_mac_write = 0x0108, 1874 1875 /* PXE */ 1876 ice_aqc_opc_clear_pxe_mode = 0x0110, 1877 1878 /* internal switch commands */ 1879 ice_aqc_opc_get_sw_cfg = 0x0200, 1880 1881 /* Alloc/Free/Get Resources */ 1882 ice_aqc_opc_alloc_res = 0x0208, 1883 ice_aqc_opc_free_res = 0x0209, 1884 1885 /* VSI commands */ 1886 ice_aqc_opc_add_vsi = 0x0210, 1887 ice_aqc_opc_update_vsi = 0x0211, 1888 ice_aqc_opc_free_vsi = 0x0213, 1889 1890 /* switch rules population commands */ 1891 ice_aqc_opc_add_sw_rules = 0x02A0, 1892 ice_aqc_opc_update_sw_rules = 0x02A1, 1893 ice_aqc_opc_remove_sw_rules = 0x02A2, 1894 1895 ice_aqc_opc_clear_pf_cfg = 0x02A4, 1896 1897 /* transmit scheduler commands */ 1898 ice_aqc_opc_get_dflt_topo = 0x0400, 1899 ice_aqc_opc_add_sched_elems = 0x0401, 1900 ice_aqc_opc_cfg_sched_elems = 0x0403, 1901 ice_aqc_opc_get_sched_elems = 0x0404, 1902 ice_aqc_opc_suspend_sched_elems = 0x0409, 1903 ice_aqc_opc_resume_sched_elems = 0x040A, 1904 ice_aqc_opc_query_port_ets = 0x040E, 1905 ice_aqc_opc_delete_sched_elems = 0x040F, 1906 ice_aqc_opc_add_rl_profiles = 0x0410, 1907 ice_aqc_opc_query_sched_res = 0x0412, 1908 ice_aqc_opc_remove_rl_profiles = 0x0415, 1909 1910 /* PHY commands */ 1911 ice_aqc_opc_get_phy_caps = 0x0600, 1912 ice_aqc_opc_set_phy_cfg = 0x0601, 1913 ice_aqc_opc_set_mac_cfg = 0x0603, 1914 ice_aqc_opc_restart_an = 0x0605, 1915 ice_aqc_opc_get_link_status = 0x0607, 1916 ice_aqc_opc_set_event_mask = 0x0613, 1917 ice_aqc_opc_set_mac_lb = 0x0620, 1918 ice_aqc_opc_get_link_topo = 0x06E0, 1919 ice_aqc_opc_set_port_id_led = 0x06E9, 1920 ice_aqc_opc_sff_eeprom = 0x06EE, 1921 1922 /* NVM commands */ 1923 ice_aqc_opc_nvm_read = 0x0701, 1924 ice_aqc_opc_nvm_checksum = 0x0706, 1925 1926 /* PF/VF mailbox commands */ 1927 ice_mbx_opc_send_msg_to_pf = 0x0801, 1928 ice_mbx_opc_send_msg_to_vf = 0x0802, 1929 /* LLDP commands */ 1930 ice_aqc_opc_lldp_get_mib = 0x0A00, 1931 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 1932 ice_aqc_opc_lldp_stop = 0x0A05, 1933 ice_aqc_opc_lldp_start = 0x0A06, 1934 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 1935 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 1936 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 1937 1938 /* RSS commands */ 1939 ice_aqc_opc_set_rss_key = 0x0B02, 1940 ice_aqc_opc_set_rss_lut = 0x0B03, 1941 ice_aqc_opc_get_rss_key = 0x0B04, 1942 ice_aqc_opc_get_rss_lut = 0x0B05, 1943 1944 /* Tx queue handling commands/events */ 1945 ice_aqc_opc_add_txqs = 0x0C30, 1946 ice_aqc_opc_dis_txqs = 0x0C31, 1947 1948 /* package commands */ 1949 ice_aqc_opc_download_pkg = 0x0C40, 1950 ice_aqc_opc_update_pkg = 0x0C42, 1951 ice_aqc_opc_get_pkg_info_list = 0x0C43, 1952 1953 /* Standalone Commands/Events */ 1954 ice_aqc_opc_event_lan_overflow = 0x1001, 1955 1956 /* debug commands */ 1957 ice_aqc_opc_fw_logging = 0xFF09, 1958 ice_aqc_opc_fw_logging_info = 0xFF10, 1959 }; 1960 1961 #endif /* _ICE_ADMINQ_CMD_H_ */ 1962