1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 struct ice_aqc_generic { 16 __le32 param0; 17 __le32 param1; 18 __le32 addr_high; 19 __le32 addr_low; 20 }; 21 22 /* Get version (direct 0x0001) */ 23 struct ice_aqc_get_ver { 24 __le32 rom_ver; 25 __le32 fw_build; 26 u8 fw_branch; 27 u8 fw_major; 28 u8 fw_minor; 29 u8 fw_patch; 30 u8 api_branch; 31 u8 api_major; 32 u8 api_minor; 33 u8 api_patch; 34 }; 35 36 /* Queue Shutdown (direct 0x0003) */ 37 struct ice_aqc_q_shutdown { 38 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 39 __le32 driver_unloading; 40 u8 reserved[12]; 41 }; 42 43 /* Request resource ownership (direct 0x0008) 44 * Release resource ownership (direct 0x0009) 45 */ 46 struct ice_aqc_req_res { 47 __le16 res_id; 48 #define ICE_AQC_RES_ID_NVM 1 49 #define ICE_AQC_RES_ID_SDP 2 50 #define ICE_AQC_RES_ID_CHNG_LOCK 3 51 #define ICE_AQC_RES_ID_GLBL_LOCK 4 52 __le16 access_type; 53 #define ICE_AQC_RES_ACCESS_READ 1 54 #define ICE_AQC_RES_ACCESS_WRITE 2 55 56 /* Upon successful completion, FW writes this value and driver is 57 * expected to release resource before timeout. This value is provided 58 * in milliseconds. 59 */ 60 __le32 timeout; 61 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 62 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 63 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 64 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 65 /* For SDP: pin id of the SDP */ 66 __le32 res_number; 67 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 68 __le16 status; 69 #define ICE_AQ_RES_GLBL_SUCCESS 0 70 #define ICE_AQ_RES_GLBL_IN_PROG 1 71 #define ICE_AQ_RES_GLBL_DONE 2 72 u8 reserved[2]; 73 }; 74 75 /* Get function capabilities (indirect 0x000A) 76 * Get device capabilities (indirect 0x000B) 77 */ 78 struct ice_aqc_list_caps { 79 u8 cmd_flags; 80 u8 pf_index; 81 u8 reserved[2]; 82 __le32 count; 83 __le32 addr_high; 84 __le32 addr_low; 85 }; 86 87 /* Device/Function buffer entry, repeated per reported capability */ 88 struct ice_aqc_list_caps_elem { 89 __le16 cap; 90 #define ICE_AQC_CAPS_SRIOV 0x0012 91 #define ICE_AQC_CAPS_VF 0x0013 92 #define ICE_AQC_CAPS_VSI 0x0017 93 #define ICE_AQC_CAPS_RSS 0x0040 94 #define ICE_AQC_CAPS_RXQS 0x0041 95 #define ICE_AQC_CAPS_TXQS 0x0042 96 #define ICE_AQC_CAPS_MSIX 0x0043 97 #define ICE_AQC_CAPS_MAX_MTU 0x0047 98 99 u8 major_ver; 100 u8 minor_ver; 101 /* Number of resources described by this capability */ 102 __le32 number; 103 /* Only meaningful for some types of resources */ 104 __le32 logical_id; 105 /* Only meaningful for some types of resources */ 106 __le32 phys_id; 107 __le64 rsvd1; 108 __le64 rsvd2; 109 }; 110 111 /* Manage MAC address, read command - indirect (0x0107) 112 * This struct is also used for the response 113 */ 114 struct ice_aqc_manage_mac_read { 115 __le16 flags; /* Zeroed by device driver */ 116 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 117 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 118 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 119 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 120 #define ICE_AQC_MAN_MAC_READ_S 4 121 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 122 u8 lport_num; 123 u8 lport_num_valid; 124 #define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID BIT(0) 125 u8 num_addr; /* Used in response */ 126 u8 reserved[3]; 127 __le32 addr_high; 128 __le32 addr_low; 129 }; 130 131 /* Response buffer format for manage MAC read command */ 132 struct ice_aqc_manage_mac_read_resp { 133 u8 lport_num; 134 u8 addr_type; 135 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 136 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 137 u8 mac_addr[ETH_ALEN]; 138 }; 139 140 /* Manage MAC address, write command - direct (0x0108) */ 141 struct ice_aqc_manage_mac_write { 142 u8 port_num; 143 u8 flags; 144 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 145 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 146 #define ICE_AQC_MAN_MAC_WR_S 6 147 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S) 148 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 149 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S) 150 /* High 16 bits of MAC address in big endian order */ 151 __be16 sah; 152 /* Low 32 bits of MAC address in big endian order */ 153 __be32 sal; 154 __le32 addr_high; 155 __le32 addr_low; 156 }; 157 158 /* Clear PXE Command and response (direct 0x0110) */ 159 struct ice_aqc_clear_pxe { 160 u8 rx_cnt; 161 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 162 u8 reserved[15]; 163 }; 164 165 /* Get switch configuration (0x0200) */ 166 struct ice_aqc_get_sw_cfg { 167 /* Reserved for command and copy of request flags for response */ 168 __le16 flags; 169 /* First desc in case of command and next_elem in case of response 170 * In case of response, if it is not zero, means all the configuration 171 * was not returned and new command shall be sent with this value in 172 * the 'first desc' field 173 */ 174 __le16 element; 175 /* Reserved for command, only used for response */ 176 __le16 num_elems; 177 __le16 rsvd; 178 __le32 addr_high; 179 __le32 addr_low; 180 }; 181 182 /* Each entry in the response buffer is of the following type: */ 183 struct ice_aqc_get_sw_cfg_resp_elem { 184 /* VSI/Port Number */ 185 __le16 vsi_port_num; 186 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 187 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 188 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 189 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 190 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 191 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 192 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 193 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 194 195 /* SWID VSI/Port belongs to */ 196 __le16 swid; 197 198 /* Bit 14..0 : PF/VF number VSI belongs to 199 * Bit 15 : VF indication bit 200 */ 201 __le16 pf_vf_num; 202 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 203 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 204 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 205 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 206 }; 207 208 /* The response buffer is as follows. Note that the length of the 209 * elements array varies with the length of the command response. 210 */ 211 struct ice_aqc_get_sw_cfg_resp { 212 struct ice_aqc_get_sw_cfg_resp_elem elements[1]; 213 }; 214 215 /* These resource type defines are used for all switch resource 216 * commands where a resource type is required, such as: 217 * Get Resource Allocation command (indirect 0x0204) 218 * Allocate Resources command (indirect 0x0208) 219 * Free Resources command (indirect 0x0209) 220 * Get Allocated Resource Descriptors Command (indirect 0x020A) 221 */ 222 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 223 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 224 225 /* Allocate Resources command (indirect 0x0208) 226 * Free Resources command (indirect 0x0209) 227 */ 228 struct ice_aqc_alloc_free_res_cmd { 229 __le16 num_entries; /* Number of Resource entries */ 230 u8 reserved[6]; 231 __le32 addr_high; 232 __le32 addr_low; 233 }; 234 235 /* Resource descriptor */ 236 struct ice_aqc_res_elem { 237 union { 238 __le16 sw_resp; 239 __le16 flu_resp; 240 } e; 241 }; 242 243 /* Buffer for Allocate/Free Resources commands */ 244 struct ice_aqc_alloc_free_res_elem { 245 __le16 res_type; /* Types defined above cmd 0x0204 */ 246 #define ICE_AQC_RES_TYPE_SHARED_S 7 247 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 248 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 249 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 250 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 251 __le16 num_elems; 252 struct ice_aqc_res_elem elem[1]; 253 }; 254 255 /* Add VSI (indirect 0x0210) 256 * Update VSI (indirect 0x0211) 257 * Get VSI (indirect 0x0212) 258 * Free VSI (indirect 0x0213) 259 */ 260 struct ice_aqc_add_get_update_free_vsi { 261 __le16 vsi_num; 262 #define ICE_AQ_VSI_NUM_S 0 263 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 264 #define ICE_AQ_VSI_IS_VALID BIT(15) 265 __le16 cmd_flags; 266 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 267 u8 vf_id; 268 u8 reserved; 269 __le16 vsi_flags; 270 #define ICE_AQ_VSI_TYPE_S 0 271 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 272 #define ICE_AQ_VSI_TYPE_VF 0x0 273 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 274 #define ICE_AQ_VSI_TYPE_PF 0x2 275 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 276 __le32 addr_high; 277 __le32 addr_low; 278 }; 279 280 /* Response descriptor for: 281 * Add VSI (indirect 0x0210) 282 * Update VSI (indirect 0x0211) 283 * Free VSI (indirect 0x0213) 284 */ 285 struct ice_aqc_add_update_free_vsi_resp { 286 __le16 vsi_num; 287 __le16 ext_status; 288 __le16 vsi_used; 289 __le16 vsi_free; 290 __le32 addr_high; 291 __le32 addr_low; 292 }; 293 294 struct ice_aqc_vsi_props { 295 __le16 valid_sections; 296 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 297 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 298 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 299 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 300 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 301 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 302 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 303 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 304 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 305 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 306 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 307 /* switch section */ 308 u8 sw_id; 309 u8 sw_flags; 310 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 311 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 312 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 313 u8 sw_flags2; 314 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 315 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 316 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 317 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 318 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 319 u8 veb_stat_id; 320 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 321 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 322 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 323 /* security section */ 324 u8 sec_flags; 325 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 326 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 327 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 328 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 329 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 330 u8 sec_reserved; 331 /* VLAN section */ 332 __le16 pvid; /* VLANS include priority bits */ 333 u8 pvlan_reserved[2]; 334 u8 vlan_flags; 335 #define ICE_AQ_VSI_VLAN_MODE_S 0 336 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 337 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 338 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 339 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 340 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 341 #define ICE_AQ_VSI_VLAN_EMOD_S 3 342 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 343 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 344 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 345 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 346 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 347 u8 pvlan_reserved2[3]; 348 /* ingress egress up sections */ 349 __le32 ingress_table; /* bitmap, 3 bits per up */ 350 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 351 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 352 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 353 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 354 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 355 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 356 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 357 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 358 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 359 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 360 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 361 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 362 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 363 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 364 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 365 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 366 __le32 egress_table; /* same defines as for ingress table */ 367 /* outer tags section */ 368 __le16 outer_tag; 369 u8 outer_tag_flags; 370 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 371 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 372 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 373 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 374 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 375 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 376 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 377 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 378 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 379 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 380 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 381 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 382 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 383 u8 outer_tag_reserved; 384 /* queue mapping section */ 385 __le16 mapping_flags; 386 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 387 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 388 __le16 q_mapping[16]; 389 #define ICE_AQ_VSI_Q_S 0 390 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 391 __le16 tc_mapping[8]; 392 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 393 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 394 #define ICE_AQ_VSI_TC_Q_NUM_S 11 395 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 396 /* queueing option section */ 397 u8 q_opt_rss; 398 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 399 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 400 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 401 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 402 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 403 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 404 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 405 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 406 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 407 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 408 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 409 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 410 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 411 u8 q_opt_tc; 412 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 413 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 414 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 415 u8 q_opt_flags; 416 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 417 u8 q_opt_reserved[3]; 418 /* outer up section */ 419 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 420 /* section 10 */ 421 __le16 sect_10_reserved; 422 /* flow director section */ 423 __le16 fd_options; 424 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 425 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 426 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 427 __le16 max_fd_fltr_dedicated; 428 __le16 max_fd_fltr_shared; 429 __le16 fd_def_q; 430 #define ICE_AQ_VSI_FD_DEF_Q_S 0 431 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 432 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 433 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 434 __le16 fd_report_opt; 435 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 436 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 437 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 438 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 439 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 440 /* PASID section */ 441 __le32 pasid_id; 442 #define ICE_AQ_VSI_PASID_ID_S 0 443 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 444 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 445 u8 reserved[24]; 446 }; 447 448 #define ICE_MAX_NUM_RECIPES 64 449 450 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 451 */ 452 struct ice_aqc_sw_rules { 453 /* ops: add switch rules, referring the number of rules. 454 * ops: update switch rules, referring the number of filters 455 * ops: remove switch rules, referring the entry index. 456 * ops: get switch rules, referring to the number of filters. 457 */ 458 __le16 num_rules_fltr_entry_index; 459 u8 reserved[6]; 460 __le32 addr_high; 461 __le32 addr_low; 462 }; 463 464 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 465 * This structures describes the lookup rules and associated actions. "index" 466 * is returned as part of a response to a successful Add command, and can be 467 * used to identify the rule for Update/Get/Remove commands. 468 */ 469 struct ice_sw_rule_lkup_rx_tx { 470 __le16 recipe_id; 471 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 472 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 473 __le16 src; 474 __le32 act; 475 476 /* Bit 0:1 - Action type */ 477 #define ICE_SINGLE_ACT_TYPE_S 0x00 478 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 479 480 /* Bit 2 - Loop back enable 481 * Bit 3 - LAN enable 482 */ 483 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 484 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 485 486 /* Action type = 0 - Forward to VSI or VSI list */ 487 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 488 489 #define ICE_SINGLE_ACT_VSI_ID_S 4 490 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 491 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 492 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 493 /* This bit needs to be set if action is forward to VSI list */ 494 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 495 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 496 #define ICE_SINGLE_ACT_DROP BIT(18) 497 498 /* Action type = 1 - Forward to Queue of Queue group */ 499 #define ICE_SINGLE_ACT_TO_Q 0x1 500 #define ICE_SINGLE_ACT_Q_INDEX_S 4 501 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 502 #define ICE_SINGLE_ACT_Q_REGION_S 15 503 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 504 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 505 506 /* Action type = 2 - Prune */ 507 #define ICE_SINGLE_ACT_PRUNE 0x2 508 #define ICE_SINGLE_ACT_EGRESS BIT(15) 509 #define ICE_SINGLE_ACT_INGRESS BIT(16) 510 #define ICE_SINGLE_ACT_PRUNET BIT(17) 511 /* Bit 18 should be set to 0 for this action */ 512 513 /* Action type = 2 - Pointer */ 514 #define ICE_SINGLE_ACT_PTR 0x2 515 #define ICE_SINGLE_ACT_PTR_VAL_S 4 516 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 517 /* Bit 18 should be set to 1 */ 518 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 519 520 /* Action type = 3 - Other actions. Last two bits 521 * are other action identifier 522 */ 523 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 524 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 525 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 526 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 527 528 /* Bit 17:18 - Defines other actions */ 529 /* Other action = 0 - Mirror VSI */ 530 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 531 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 532 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 533 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 534 535 /* Other action = 3 - Set Stat count */ 536 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 537 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 538 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 539 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 540 541 __le16 index; /* The index of the rule in the lookup table */ 542 /* Length and values of the header to be matched per recipe or 543 * lookup-type 544 */ 545 __le16 hdr_len; 546 u8 hdr[1]; 547 } __packed; 548 549 /* Add/Update/Remove large action command/response entry 550 * "index" is returned as part of a response to a successful Add command, and 551 * can be used to identify the action for Update/Get/Remove commands. 552 */ 553 struct ice_sw_rule_lg_act { 554 __le16 index; /* Index in large action table */ 555 __le16 size; 556 __le32 act[1]; /* array of size for actions */ 557 /* Max number of large actions */ 558 #define ICE_MAX_LG_ACT 4 559 /* Bit 0:1 - Action type */ 560 #define ICE_LG_ACT_TYPE_S 0 561 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 562 563 /* Action type = 0 - Forward to VSI or VSI list */ 564 #define ICE_LG_ACT_VSI_FORWARDING 0 565 #define ICE_LG_ACT_VSI_ID_S 3 566 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 567 #define ICE_LG_ACT_VSI_LIST_ID_S 3 568 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 569 /* This bit needs to be set if action is forward to VSI list */ 570 #define ICE_LG_ACT_VSI_LIST BIT(13) 571 572 #define ICE_LG_ACT_VALID_BIT BIT(16) 573 574 /* Action type = 1 - Forward to Queue of Queue group */ 575 #define ICE_LG_ACT_TO_Q 0x1 576 #define ICE_LG_ACT_Q_INDEX_S 3 577 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 578 #define ICE_LG_ACT_Q_REGION_S 14 579 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 580 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 581 582 /* Action type = 2 - Prune */ 583 #define ICE_LG_ACT_PRUNE 0x2 584 #define ICE_LG_ACT_EGRESS BIT(14) 585 #define ICE_LG_ACT_INGRESS BIT(15) 586 #define ICE_LG_ACT_PRUNET BIT(16) 587 588 /* Action type = 3 - Mirror VSI */ 589 #define ICE_LG_OTHER_ACT_MIRROR 0x3 590 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 591 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 592 593 /* Action type = 5 - Generic Value */ 594 #define ICE_LG_ACT_GENERIC 0x5 595 #define ICE_LG_ACT_GENERIC_VALUE_S 3 596 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 597 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 598 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 599 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 600 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 601 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 602 603 /* Action = 7 - Set Stat count */ 604 #define ICE_LG_ACT_STAT_COUNT 0x7 605 #define ICE_LG_ACT_STAT_COUNT_S 3 606 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 607 }; 608 609 /* Add/Update/Remove VSI list command/response entry 610 * "index" is returned as part of a response to a successful Add command, and 611 * can be used to identify the VSI list for Update/Get/Remove commands. 612 */ 613 struct ice_sw_rule_vsi_list { 614 __le16 index; /* Index of VSI/Prune list */ 615 __le16 number_vsi; 616 __le16 vsi[1]; /* Array of number_vsi VSI numbers */ 617 }; 618 619 /* Query VSI list command/response entry */ 620 struct ice_sw_rule_vsi_list_query { 621 __le16 index; 622 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI); 623 } __packed; 624 625 /* Add switch rule response: 626 * Content of return buffer is same as the input buffer. The status field and 627 * LUT index are updated as part of the response 628 */ 629 struct ice_aqc_sw_rules_elem { 630 __le16 type; /* Switch rule type, one of T_... */ 631 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 632 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 633 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 634 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 635 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 636 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 637 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 638 __le16 status; 639 union { 640 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 641 struct ice_sw_rule_lg_act lg_act; 642 struct ice_sw_rule_vsi_list vsi_list; 643 struct ice_sw_rule_vsi_list_query vsi_list_query; 644 } __packed pdata; 645 }; 646 647 /* Get Default Topology (indirect 0x0400) */ 648 struct ice_aqc_get_topo { 649 u8 port_num; 650 u8 num_branches; 651 __le16 reserved1; 652 __le32 reserved2; 653 __le32 addr_high; 654 __le32 addr_low; 655 }; 656 657 /* Update TSE (indirect 0x0403) 658 * Get TSE (indirect 0x0404) 659 */ 660 struct ice_aqc_get_cfg_elem { 661 __le16 num_elem_req; /* Used by commands */ 662 __le16 num_elem_resp; /* Used by responses */ 663 __le32 reserved; 664 __le32 addr_high; 665 __le32 addr_low; 666 }; 667 668 /* This is the buffer for: 669 * Suspend Nodes (indirect 0x0409) 670 * Resume Nodes (indirect 0x040A) 671 */ 672 struct ice_aqc_suspend_resume_elem { 673 __le32 teid[1]; 674 }; 675 676 /* Add TSE (indirect 0x0401) 677 * Delete TSE (indirect 0x040F) 678 * Move TSE (indirect 0x0408) 679 */ 680 struct ice_aqc_add_move_delete_elem { 681 __le16 num_grps_req; 682 __le16 num_grps_updated; 683 __le32 reserved; 684 __le32 addr_high; 685 __le32 addr_low; 686 }; 687 688 struct ice_aqc_elem_info_bw { 689 __le16 bw_profile_idx; 690 __le16 bw_alloc; 691 }; 692 693 struct ice_aqc_txsched_elem { 694 u8 elem_type; /* Special field, reserved for some aq calls */ 695 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 696 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 697 #define ICE_AQC_ELEM_TYPE_TC 0x2 698 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 699 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 700 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 701 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 702 u8 valid_sections; 703 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 704 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 705 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 706 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 707 u8 generic; 708 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 709 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 710 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 711 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 712 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 713 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 714 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 715 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 716 u8 flags; /* Special field, reserved for some aq calls */ 717 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 718 struct ice_aqc_elem_info_bw cir_bw; 719 struct ice_aqc_elem_info_bw eir_bw; 720 __le16 srl_id; 721 __le16 reserved2; 722 }; 723 724 struct ice_aqc_txsched_elem_data { 725 __le32 parent_teid; 726 __le32 node_teid; 727 struct ice_aqc_txsched_elem data; 728 }; 729 730 struct ice_aqc_txsched_topo_grp_info_hdr { 731 __le32 parent_teid; 732 __le16 num_elems; 733 __le16 reserved2; 734 }; 735 736 struct ice_aqc_add_elem { 737 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 738 struct ice_aqc_txsched_elem_data generic[1]; 739 }; 740 741 struct ice_aqc_get_elem { 742 struct ice_aqc_txsched_elem_data generic[1]; 743 }; 744 745 struct ice_aqc_get_topo_elem { 746 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 747 struct ice_aqc_txsched_elem_data 748 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 749 }; 750 751 struct ice_aqc_delete_elem { 752 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 753 __le32 teid[1]; 754 }; 755 756 /* Query Scheduler Resource Allocation (indirect 0x0412) 757 * This indirect command retrieves the scheduler resources allocated by 758 * EMP Firmware to the given PF. 759 */ 760 struct ice_aqc_query_txsched_res { 761 u8 reserved[8]; 762 __le32 addr_high; 763 __le32 addr_low; 764 }; 765 766 struct ice_aqc_generic_sched_props { 767 __le16 phys_levels; 768 __le16 logical_levels; 769 u8 flattening_bitmap; 770 u8 max_device_cgds; 771 u8 max_pf_cgds; 772 u8 rsvd0; 773 __le16 rdma_qsets; 774 u8 rsvd1[22]; 775 }; 776 777 struct ice_aqc_layer_props { 778 u8 logical_layer; 779 u8 chunk_size; 780 __le16 max_device_nodes; 781 __le16 max_pf_nodes; 782 u8 rsvd0[4]; 783 __le16 max_sibl_grp_sz; 784 __le16 max_cir_rl_profiles; 785 __le16 max_eir_rl_profiles; 786 __le16 max_srl_profiles; 787 u8 rsvd1[14]; 788 }; 789 790 struct ice_aqc_query_txsched_res_resp { 791 struct ice_aqc_generic_sched_props sched_props; 792 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 793 }; 794 795 /* Get PHY capabilities (indirect 0x0600) */ 796 struct ice_aqc_get_phy_caps { 797 u8 lport_num; 798 u8 reserved; 799 __le16 param0; 800 /* 18.0 - Report qualified modules */ 801 #define ICE_AQC_GET_PHY_RQM BIT(0) 802 /* 18.1 - 18.2 : Report mode 803 * 00b - Report NVM capabilities 804 * 01b - Report topology capabilities 805 * 10b - Report SW configured 806 */ 807 #define ICE_AQC_REPORT_MODE_S 1 808 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 809 #define ICE_AQC_REPORT_NVM_CAP 0 810 #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 811 #define ICE_AQC_REPORT_SW_CFG BIT(2) 812 __le32 reserved1; 813 __le32 addr_high; 814 __le32 addr_low; 815 }; 816 817 /* This is #define of PHY type (Extended): 818 * The first set of defines is for phy_type_low. 819 */ 820 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 821 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 822 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 823 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 824 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 825 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 826 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 827 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 828 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 829 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 830 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 831 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 832 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 833 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 834 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 835 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 836 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 837 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 838 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 839 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 840 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 841 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 842 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 843 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 844 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 845 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 846 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 847 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 848 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 849 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 850 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 851 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 852 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 853 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 854 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 855 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 856 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 857 858 struct ice_aqc_get_phy_caps_data { 859 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 860 __le64 reserved; 861 u8 caps; 862 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 863 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 864 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 865 #define ICE_AQC_PHY_EN_LINK BIT(3) 866 #define ICE_AQC_PHY_AN_MODE BIT(4) 867 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 868 u8 low_power_ctrl; 869 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 870 __le16 eee_cap; 871 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 872 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 873 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 874 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 875 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 876 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 877 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 878 __le16 eeer_value; 879 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 880 u8 link_fec_options; 881 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 882 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 883 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 884 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 885 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 886 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 887 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 888 u8 extended_compliance_code; 889 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 890 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 891 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 892 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 893 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 894 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 895 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 896 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 897 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 898 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 899 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 900 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 901 u8 qualified_module_count; 902 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 903 struct { 904 u8 v_oui[3]; 905 u8 rsvd1; 906 u8 v_part[16]; 907 __le32 v_rev; 908 __le64 rsvd8; 909 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 910 }; 911 912 /* Set PHY capabilities (direct 0x0601) 913 * NOTE: This command must be followed by setup link and restart auto-neg 914 */ 915 struct ice_aqc_set_phy_cfg { 916 u8 lport_num; 917 u8 reserved[7]; 918 __le32 addr_high; 919 __le32 addr_low; 920 }; 921 922 /* Set PHY config command data structure */ 923 struct ice_aqc_set_phy_cfg_data { 924 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 925 __le64 rsvd0; 926 u8 caps; 927 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 928 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 929 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 930 #define ICE_AQ_PHY_ENA_LINK BIT(3) 931 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 932 #define ICE_AQ_PHY_ENA_LESM BIT(6) 933 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 934 u8 low_power_ctrl; 935 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 936 __le16 eeer_value; 937 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 938 u8 rsvd1; 939 }; 940 941 /* Restart AN command data structure (direct 0x0605) 942 * Also used for response, with only the lport_num field present. 943 */ 944 struct ice_aqc_restart_an { 945 u8 lport_num; 946 u8 reserved; 947 u8 cmd_flags; 948 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 949 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 950 u8 reserved2[13]; 951 }; 952 953 /* Get link status (indirect 0x0607), also used for Link Status Event */ 954 struct ice_aqc_get_link_status { 955 u8 lport_num; 956 u8 reserved; 957 __le16 cmd_flags; 958 #define ICE_AQ_LSE_M 0x3 959 #define ICE_AQ_LSE_NOP 0x0 960 #define ICE_AQ_LSE_DIS 0x2 961 #define ICE_AQ_LSE_ENA 0x3 962 /* only response uses this flag */ 963 #define ICE_AQ_LSE_IS_ENABLED 0x1 964 __le32 reserved2; 965 __le32 addr_high; 966 __le32 addr_low; 967 }; 968 969 /* Get link status response data structure, also used for Link Status Event */ 970 struct ice_aqc_get_link_status_data { 971 u8 topo_media_conflict; 972 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 973 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 974 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 975 u8 reserved1; 976 u8 link_info; 977 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 978 #define ICE_AQ_LINK_FAULT BIT(1) 979 #define ICE_AQ_LINK_FAULT_TX BIT(2) 980 #define ICE_AQ_LINK_FAULT_RX BIT(3) 981 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 982 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 983 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 984 #define ICE_AQ_SIGNAL_DETECT BIT(7) 985 u8 an_info; 986 #define ICE_AQ_AN_COMPLETED BIT(0) 987 #define ICE_AQ_LP_AN_ABILITY BIT(1) 988 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 989 #define ICE_AQ_FEC_EN BIT(3) 990 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 991 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 992 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 993 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 994 u8 ext_info; 995 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 996 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 997 /* Port TX Suspended */ 998 #define ICE_AQ_LINK_TX_S 2 999 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1000 #define ICE_AQ_LINK_TX_ACTIVE 0 1001 #define ICE_AQ_LINK_TX_DRAINED 1 1002 #define ICE_AQ_LINK_TX_FLUSHED 3 1003 u8 reserved2; 1004 __le16 max_frame_size; 1005 u8 cfg; 1006 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1007 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1008 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1009 /* Pacing Config */ 1010 #define ICE_AQ_CFG_PACING_S 3 1011 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1012 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1013 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1014 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1015 /* External Device Power Ability */ 1016 u8 power_desc; 1017 #define ICE_AQ_PWR_CLASS_M 0x3 1018 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1019 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1020 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1021 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1022 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1023 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1024 __le16 link_speed; 1025 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1026 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1027 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1028 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1029 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1030 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1031 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1032 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1033 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1034 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1035 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1036 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1037 __le64 reserved4; 1038 }; 1039 1040 /* Set event mask command (direct 0x0613) */ 1041 struct ice_aqc_set_event_mask { 1042 u8 lport_num; 1043 u8 reserved[7]; 1044 __le16 event_mask; 1045 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1046 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1047 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1048 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1049 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1050 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1051 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1052 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1053 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1054 u8 reserved1[6]; 1055 }; 1056 1057 /* NVM Read command (indirect 0x0701) 1058 * NVM Erase commands (direct 0x0702) 1059 * NVM Update commands (indirect 0x0703) 1060 */ 1061 struct ice_aqc_nvm { 1062 __le16 offset_low; 1063 u8 offset_high; 1064 u8 cmd_flags; 1065 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1066 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1067 #define ICE_AQC_NVM_PRESERVATION_S 1 1068 #define ICE_AQC_NVM_PRESERVATION_M (3 << CSR_AQ_NVM_PRESERVATION_S) 1069 #define ICE_AQC_NVM_NO_PRESERVATION (0 << CSR_AQ_NVM_PRESERVATION_S) 1070 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1071 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << CSR_AQ_NVM_PRESERVATION_S) 1072 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1073 __le16 module_typeid; 1074 __le16 length; 1075 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1076 __le32 addr_high; 1077 __le32 addr_low; 1078 }; 1079 1080 /** 1081 * Send to PF command (indirect 0x0801) id is only used by PF 1082 * 1083 * Send to VF command (indirect 0x0802) id is only used by PF 1084 * 1085 */ 1086 struct ice_aqc_pf_vf_msg { 1087 __le32 id; 1088 u32 reserved; 1089 __le32 addr_high; 1090 __le32 addr_low; 1091 }; 1092 1093 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1094 struct ice_aqc_get_set_rss_key { 1095 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1096 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1097 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1098 __le16 vsi_id; 1099 u8 reserved[6]; 1100 __le32 addr_high; 1101 __le32 addr_low; 1102 }; 1103 1104 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1105 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1106 1107 struct ice_aqc_get_set_rss_keys { 1108 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1109 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1110 }; 1111 1112 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1113 struct ice_aqc_get_set_rss_lut { 1114 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1115 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1116 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1117 __le16 vsi_id; 1118 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1119 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1120 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1121 1122 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1123 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1124 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1125 1126 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1127 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1128 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1129 1130 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1131 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1132 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1133 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1134 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1135 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1136 1137 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1138 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1139 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1140 1141 __le16 flags; 1142 __le32 reserved; 1143 __le32 addr_high; 1144 __le32 addr_low; 1145 }; 1146 1147 /* Add TX LAN Queues (indirect 0x0C30) */ 1148 struct ice_aqc_add_txqs { 1149 u8 num_qgrps; 1150 u8 reserved[3]; 1151 __le32 reserved1; 1152 __le32 addr_high; 1153 __le32 addr_low; 1154 }; 1155 1156 /* This is the descriptor of each queue entry for the Add TX LAN Queues 1157 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1158 */ 1159 struct ice_aqc_add_txqs_perq { 1160 __le16 txq_id; 1161 u8 rsvd[2]; 1162 __le32 q_teid; 1163 u8 txq_ctx[22]; 1164 u8 rsvd2[2]; 1165 struct ice_aqc_txsched_elem info; 1166 }; 1167 1168 /* The format of the command buffer for Add TX LAN Queues (0x0C30) 1169 * is an array of the following structs. Please note that the length of 1170 * each struct ice_aqc_add_tx_qgrp is variable due 1171 * to the variable number of queues in each group! 1172 */ 1173 struct ice_aqc_add_tx_qgrp { 1174 __le32 parent_teid; 1175 u8 num_txqs; 1176 u8 rsvd[3]; 1177 struct ice_aqc_add_txqs_perq txqs[1]; 1178 }; 1179 1180 /* Disable TX LAN Queues (indirect 0x0C31) */ 1181 struct ice_aqc_dis_txqs { 1182 u8 cmd_type; 1183 #define ICE_AQC_Q_DIS_CMD_S 0 1184 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1185 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1186 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1187 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1188 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1189 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1190 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1191 u8 num_entries; 1192 __le16 vmvf_and_timeout; 1193 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1194 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1195 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1196 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1197 __le32 blocked_cgds; 1198 __le32 addr_high; 1199 __le32 addr_low; 1200 }; 1201 1202 /* The buffer for Disable TX LAN Queues (indirect 0x0C31) 1203 * contains the following structures, arrayed one after the 1204 * other. 1205 * Note: Since the q_id is 16 bits wide, if the 1206 * number of queues is even, then 2 bytes of alignment MUST be 1207 * added before the start of the next group, to allow correct 1208 * alignment of the parent_teid field. 1209 */ 1210 struct ice_aqc_dis_txq_item { 1211 __le32 parent_teid; 1212 u8 num_qs; 1213 u8 rsvd; 1214 /* The length of the q_id array varies according to num_qs */ 1215 __le16 q_id[1]; 1216 /* This only applies from F8 onward */ 1217 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1218 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1219 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1220 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1221 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1222 }; 1223 1224 struct ice_aqc_dis_txq { 1225 struct ice_aqc_dis_txq_item qgrps[1]; 1226 }; 1227 1228 /* Configure Firmware Logging Command (indirect 0xFF09) 1229 * Logging Information Read Response (indirect 0xFF10) 1230 * Note: The 0xFF10 command has no input parameters. 1231 */ 1232 struct ice_aqc_fw_logging { 1233 u8 log_ctrl; 1234 #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 1235 #define ICE_AQC_FW_LOG_UART_EN BIT(1) 1236 u8 rsvd0; 1237 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 1238 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 1239 #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 1240 u8 rsvd1[5]; 1241 __le32 addr_high; 1242 __le32 addr_low; 1243 }; 1244 1245 enum ice_aqc_fw_logging_mod { 1246 ICE_AQC_FW_LOG_ID_GENERAL = 0, 1247 ICE_AQC_FW_LOG_ID_CTRL, 1248 ICE_AQC_FW_LOG_ID_LINK, 1249 ICE_AQC_FW_LOG_ID_LINK_TOPO, 1250 ICE_AQC_FW_LOG_ID_DNL, 1251 ICE_AQC_FW_LOG_ID_I2C, 1252 ICE_AQC_FW_LOG_ID_SDP, 1253 ICE_AQC_FW_LOG_ID_MDIO, 1254 ICE_AQC_FW_LOG_ID_ADMINQ, 1255 ICE_AQC_FW_LOG_ID_HDMA, 1256 ICE_AQC_FW_LOG_ID_LLDP, 1257 ICE_AQC_FW_LOG_ID_DCBX, 1258 ICE_AQC_FW_LOG_ID_DCB, 1259 ICE_AQC_FW_LOG_ID_NETPROXY, 1260 ICE_AQC_FW_LOG_ID_NVM, 1261 ICE_AQC_FW_LOG_ID_AUTH, 1262 ICE_AQC_FW_LOG_ID_VPD, 1263 ICE_AQC_FW_LOG_ID_IOSF, 1264 ICE_AQC_FW_LOG_ID_PARSER, 1265 ICE_AQC_FW_LOG_ID_SW, 1266 ICE_AQC_FW_LOG_ID_SCHEDULER, 1267 ICE_AQC_FW_LOG_ID_TXQ, 1268 ICE_AQC_FW_LOG_ID_RSVD, 1269 ICE_AQC_FW_LOG_ID_POST, 1270 ICE_AQC_FW_LOG_ID_WATCHDOG, 1271 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 1272 ICE_AQC_FW_LOG_ID_MNG, 1273 ICE_AQC_FW_LOG_ID_MAX, 1274 }; 1275 1276 /* This is the buffer for both of the logging commands. 1277 * The entry array size depends on the datalen parameter in the descriptor. 1278 * There will be a total of datalen / 2 entries. 1279 */ 1280 struct ice_aqc_fw_logging_data { 1281 __le16 entry[1]; 1282 #define ICE_AQC_FW_LOG_ID_S 0 1283 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 1284 1285 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 1286 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 1287 1288 #define ICE_AQC_FW_LOG_EN_S 12 1289 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 1290 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 1291 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 1292 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 1293 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 1294 }; 1295 1296 /* Get/Clear FW Log (indirect 0xFF11) */ 1297 struct ice_aqc_get_clear_fw_log { 1298 u8 flags; 1299 #define ICE_AQC_FW_LOG_CLEAR BIT(0) 1300 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 1301 u8 rsvd1[7]; 1302 __le32 addr_high; 1303 __le32 addr_low; 1304 }; 1305 1306 /** 1307 * struct ice_aq_desc - Admin Queue (AQ) descriptor 1308 * @flags: ICE_AQ_FLAG_* flags 1309 * @opcode: AQ command opcode 1310 * @datalen: length in bytes of indirect/external data buffer 1311 * @retval: return value from firmware 1312 * @cookie_h: opaque data high-half 1313 * @cookie_l: opaque data low-half 1314 * @params: command-specific parameters 1315 * 1316 * Descriptor format for commands the driver posts on the Admin Transmit Queue 1317 * (ATQ). The firmware writes back onto the command descriptor and returns 1318 * the result of the command. Asynchronous events that are not an immediate 1319 * result of the command are written to the Admin Receive Queue (ARQ) using 1320 * the same descriptor format. Descriptors are in little-endian notation with 1321 * 32-bit words. 1322 */ 1323 struct ice_aq_desc { 1324 __le16 flags; 1325 __le16 opcode; 1326 __le16 datalen; 1327 __le16 retval; 1328 __le32 cookie_high; 1329 __le32 cookie_low; 1330 union { 1331 u8 raw[16]; 1332 struct ice_aqc_generic generic; 1333 struct ice_aqc_get_ver get_ver; 1334 struct ice_aqc_q_shutdown q_shutdown; 1335 struct ice_aqc_req_res res_owner; 1336 struct ice_aqc_manage_mac_read mac_read; 1337 struct ice_aqc_manage_mac_write mac_write; 1338 struct ice_aqc_clear_pxe clear_pxe; 1339 struct ice_aqc_list_caps get_cap; 1340 struct ice_aqc_get_phy_caps get_phy; 1341 struct ice_aqc_set_phy_cfg set_phy; 1342 struct ice_aqc_restart_an restart_an; 1343 struct ice_aqc_get_sw_cfg get_sw_conf; 1344 struct ice_aqc_sw_rules sw_rules; 1345 struct ice_aqc_get_topo get_topo; 1346 struct ice_aqc_get_cfg_elem get_update_elem; 1347 struct ice_aqc_query_txsched_res query_sched_res; 1348 struct ice_aqc_add_move_delete_elem add_move_delete_elem; 1349 struct ice_aqc_nvm nvm; 1350 struct ice_aqc_pf_vf_msg virt; 1351 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 1352 struct ice_aqc_get_set_rss_key get_set_rss_key; 1353 struct ice_aqc_add_txqs add_txqs; 1354 struct ice_aqc_dis_txqs dis_txqs; 1355 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 1356 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 1357 struct ice_aqc_fw_logging fw_logging; 1358 struct ice_aqc_get_clear_fw_log get_clear_fw_log; 1359 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 1360 struct ice_aqc_set_event_mask set_event_mask; 1361 struct ice_aqc_get_link_status get_link_status; 1362 } params; 1363 }; 1364 1365 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 1366 #define ICE_AQ_LG_BUF 512 1367 1368 #define ICE_AQ_FLAG_ERR_S 2 1369 #define ICE_AQ_FLAG_LB_S 9 1370 #define ICE_AQ_FLAG_RD_S 10 1371 #define ICE_AQ_FLAG_BUF_S 12 1372 #define ICE_AQ_FLAG_SI_S 13 1373 1374 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 1375 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 1376 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 1377 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 1378 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 1379 1380 /* error codes */ 1381 enum ice_aq_err { 1382 ICE_AQ_RC_OK = 0, /* success */ 1383 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 1384 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1385 ICE_AQ_RC_EEXIST = 13, /* object already exists */ 1386 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 1387 }; 1388 1389 /* Admin Queue command opcodes */ 1390 enum ice_adminq_opc { 1391 /* AQ commands */ 1392 ice_aqc_opc_get_ver = 0x0001, 1393 ice_aqc_opc_q_shutdown = 0x0003, 1394 1395 /* resource ownership */ 1396 ice_aqc_opc_req_res = 0x0008, 1397 ice_aqc_opc_release_res = 0x0009, 1398 1399 /* device/function capabilities */ 1400 ice_aqc_opc_list_func_caps = 0x000A, 1401 ice_aqc_opc_list_dev_caps = 0x000B, 1402 1403 /* manage MAC address */ 1404 ice_aqc_opc_manage_mac_read = 0x0107, 1405 ice_aqc_opc_manage_mac_write = 0x0108, 1406 1407 /* PXE */ 1408 ice_aqc_opc_clear_pxe_mode = 0x0110, 1409 1410 /* internal switch commands */ 1411 ice_aqc_opc_get_sw_cfg = 0x0200, 1412 1413 /* Alloc/Free/Get Resources */ 1414 ice_aqc_opc_alloc_res = 0x0208, 1415 ice_aqc_opc_free_res = 0x0209, 1416 1417 /* VSI commands */ 1418 ice_aqc_opc_add_vsi = 0x0210, 1419 ice_aqc_opc_update_vsi = 0x0211, 1420 ice_aqc_opc_free_vsi = 0x0213, 1421 1422 /* switch rules population commands */ 1423 ice_aqc_opc_add_sw_rules = 0x02A0, 1424 ice_aqc_opc_update_sw_rules = 0x02A1, 1425 ice_aqc_opc_remove_sw_rules = 0x02A2, 1426 1427 ice_aqc_opc_clear_pf_cfg = 0x02A4, 1428 1429 /* transmit scheduler commands */ 1430 ice_aqc_opc_get_dflt_topo = 0x0400, 1431 ice_aqc_opc_add_sched_elems = 0x0401, 1432 ice_aqc_opc_get_sched_elems = 0x0404, 1433 ice_aqc_opc_suspend_sched_elems = 0x0409, 1434 ice_aqc_opc_resume_sched_elems = 0x040A, 1435 ice_aqc_opc_delete_sched_elems = 0x040F, 1436 ice_aqc_opc_query_sched_res = 0x0412, 1437 1438 /* PHY commands */ 1439 ice_aqc_opc_get_phy_caps = 0x0600, 1440 ice_aqc_opc_set_phy_cfg = 0x0601, 1441 ice_aqc_opc_restart_an = 0x0605, 1442 ice_aqc_opc_get_link_status = 0x0607, 1443 ice_aqc_opc_set_event_mask = 0x0613, 1444 1445 /* NVM commands */ 1446 ice_aqc_opc_nvm_read = 0x0701, 1447 1448 /* PF/VF mailbox commands */ 1449 ice_mbx_opc_send_msg_to_pf = 0x0801, 1450 ice_mbx_opc_send_msg_to_vf = 0x0802, 1451 1452 /* RSS commands */ 1453 ice_aqc_opc_set_rss_key = 0x0B02, 1454 ice_aqc_opc_set_rss_lut = 0x0B03, 1455 ice_aqc_opc_get_rss_key = 0x0B04, 1456 ice_aqc_opc_get_rss_lut = 0x0B05, 1457 1458 /* TX queue handling commands/events */ 1459 ice_aqc_opc_add_txqs = 0x0C30, 1460 ice_aqc_opc_dis_txqs = 0x0C31, 1461 1462 /* debug commands */ 1463 ice_aqc_opc_fw_logging = 0xFF09, 1464 }; 1465 1466 #endif /* _ICE_ADMINQ_CMD_H_ */ 1467