1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3 
4 #ifndef _ICE_ADMINQ_CMD_H_
5 #define _ICE_ADMINQ_CMD_H_
6 
7 /* This header file defines the Admin Queue commands, error codes and
8  * descriptor format. It is shared between Firmware and Software.
9  */
10 
11 #define ICE_MAX_VSI			768
12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM	0x9
13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX	9728
14 
15 struct ice_aqc_generic {
16 	__le32 param0;
17 	__le32 param1;
18 	__le32 addr_high;
19 	__le32 addr_low;
20 };
21 
22 /* Get version (direct 0x0001) */
23 struct ice_aqc_get_ver {
24 	__le32 rom_ver;
25 	__le32 fw_build;
26 	u8 fw_branch;
27 	u8 fw_major;
28 	u8 fw_minor;
29 	u8 fw_patch;
30 	u8 api_branch;
31 	u8 api_major;
32 	u8 api_minor;
33 	u8 api_patch;
34 };
35 
36 /* Queue Shutdown (direct 0x0003) */
37 struct ice_aqc_q_shutdown {
38 #define ICE_AQC_DRIVER_UNLOADING	BIT(0)
39 	__le32 driver_unloading;
40 	u8 reserved[12];
41 };
42 
43 /* Request resource ownership (direct 0x0008)
44  * Release resource ownership (direct 0x0009)
45  */
46 struct ice_aqc_req_res {
47 	__le16 res_id;
48 #define ICE_AQC_RES_ID_NVM		1
49 #define ICE_AQC_RES_ID_SDP		2
50 #define ICE_AQC_RES_ID_CHNG_LOCK	3
51 #define ICE_AQC_RES_ID_GLBL_LOCK	4
52 	__le16 access_type;
53 #define ICE_AQC_RES_ACCESS_READ		1
54 #define ICE_AQC_RES_ACCESS_WRITE	2
55 
56 	/* Upon successful completion, FW writes this value and driver is
57 	 * expected to release resource before timeout. This value is provided
58 	 * in milliseconds.
59 	 */
60 	__le32 timeout;
61 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS	3000
62 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS	180000
63 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS	1000
64 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS	3000
65 	/* For SDP: pin id of the SDP */
66 	__le32 res_number;
67 	/* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
68 	__le16 status;
69 #define ICE_AQ_RES_GLBL_SUCCESS		0
70 #define ICE_AQ_RES_GLBL_IN_PROG		1
71 #define ICE_AQ_RES_GLBL_DONE		2
72 	u8 reserved[2];
73 };
74 
75 /* Get function capabilities (indirect 0x000A)
76  * Get device capabilities (indirect 0x000B)
77  */
78 struct ice_aqc_list_caps {
79 	u8 cmd_flags;
80 	u8 pf_index;
81 	u8 reserved[2];
82 	__le32 count;
83 	__le32 addr_high;
84 	__le32 addr_low;
85 };
86 
87 /* Device/Function buffer entry, repeated per reported capability */
88 struct ice_aqc_list_caps_elem {
89 	__le16 cap;
90 #define ICE_AQC_CAPS_VALID_FUNCTIONS			0x0005
91 #define ICE_AQC_CAPS_SRIOV				0x0012
92 #define ICE_AQC_CAPS_VF					0x0013
93 #define ICE_AQC_CAPS_VSI				0x0017
94 #define ICE_AQC_CAPS_RSS				0x0040
95 #define ICE_AQC_CAPS_RXQS				0x0041
96 #define ICE_AQC_CAPS_TXQS				0x0042
97 #define ICE_AQC_CAPS_MSIX				0x0043
98 #define ICE_AQC_CAPS_MAX_MTU				0x0047
99 
100 	u8 major_ver;
101 	u8 minor_ver;
102 	/* Number of resources described by this capability */
103 	__le32 number;
104 	/* Only meaningful for some types of resources */
105 	__le32 logical_id;
106 	/* Only meaningful for some types of resources */
107 	__le32 phys_id;
108 	__le64 rsvd1;
109 	__le64 rsvd2;
110 };
111 
112 /* Manage MAC address, read command - indirect (0x0107)
113  * This struct is also used for the response
114  */
115 struct ice_aqc_manage_mac_read {
116 	__le16 flags; /* Zeroed by device driver */
117 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID		BIT(4)
118 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID		BIT(5)
119 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID		BIT(6)
120 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID		BIT(7)
121 #define ICE_AQC_MAN_MAC_READ_S			4
122 #define ICE_AQC_MAN_MAC_READ_M			(0xF << ICE_AQC_MAN_MAC_READ_S)
123 	u8 lport_num;
124 	u8 lport_num_valid;
125 #define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID	BIT(0)
126 	u8 num_addr; /* Used in response */
127 	u8 reserved[3];
128 	__le32 addr_high;
129 	__le32 addr_low;
130 };
131 
132 /* Response buffer format for manage MAC read command */
133 struct ice_aqc_manage_mac_read_resp {
134 	u8 lport_num;
135 	u8 addr_type;
136 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN		0
137 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL		1
138 	u8 mac_addr[ETH_ALEN];
139 };
140 
141 /* Manage MAC address, write command - direct (0x0108) */
142 struct ice_aqc_manage_mac_write {
143 	u8 port_num;
144 	u8 flags;
145 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN		BIT(0)
146 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP	BIT(1)
147 #define ICE_AQC_MAN_MAC_WR_S		6
148 #define ICE_AQC_MAN_MAC_WR_M		(3 << ICE_AQC_MAN_MAC_WR_S)
149 #define ICE_AQC_MAN_MAC_UPDATE_LAA	0
150 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL	(BIT(0) << ICE_AQC_MAN_MAC_WR_S)
151 	/* High 16 bits of MAC address in big endian order */
152 	__be16 sah;
153 	/* Low 32 bits of MAC address in big endian order */
154 	__be32 sal;
155 	__le32 addr_high;
156 	__le32 addr_low;
157 };
158 
159 /* Clear PXE Command and response (direct 0x0110) */
160 struct ice_aqc_clear_pxe {
161 	u8 rx_cnt;
162 #define ICE_AQC_CLEAR_PXE_RX_CNT		0x2
163 	u8 reserved[15];
164 };
165 
166 /* Get switch configuration (0x0200) */
167 struct ice_aqc_get_sw_cfg {
168 	/* Reserved for command and copy of request flags for response */
169 	__le16 flags;
170 	/* First desc in case of command and next_elem in case of response
171 	 * In case of response, if it is not zero, means all the configuration
172 	 * was not returned and new command shall be sent with this value in
173 	 * the 'first desc' field
174 	 */
175 	__le16 element;
176 	/* Reserved for command, only used for response */
177 	__le16 num_elems;
178 	__le16 rsvd;
179 	__le32 addr_high;
180 	__le32 addr_low;
181 };
182 
183 /* Each entry in the response buffer is of the following type: */
184 struct ice_aqc_get_sw_cfg_resp_elem {
185 	/* VSI/Port Number */
186 	__le16 vsi_port_num;
187 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S	0
188 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M	\
189 			(0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
190 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S	14
191 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M	(0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
192 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT	0
193 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT	1
194 #define ICE_AQC_GET_SW_CONF_RESP_VSI		2
195 
196 	/* SWID VSI/Port belongs to */
197 	__le16 swid;
198 
199 	/* Bit 14..0 : PF/VF number VSI belongs to
200 	 * Bit 15 : VF indication bit
201 	 */
202 	__le16 pf_vf_num;
203 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S	0
204 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M	\
205 				(0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
206 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF		BIT(15)
207 };
208 
209 /* The response buffer is as follows. Note that the length of the
210  * elements array varies with the length of the command response.
211  */
212 struct ice_aqc_get_sw_cfg_resp {
213 	struct ice_aqc_get_sw_cfg_resp_elem elements[1];
214 };
215 
216 /* These resource type defines are used for all switch resource
217  * commands where a resource type is required, such as:
218  * Get Resource Allocation command (indirect 0x0204)
219  * Allocate Resources command (indirect 0x0208)
220  * Free Resources command (indirect 0x0209)
221  * Get Allocated Resource Descriptors Command (indirect 0x020A)
222  */
223 #define ICE_AQC_RES_TYPE_VSI_LIST_REP			0x03
224 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE			0x04
225 
226 /* Allocate Resources command (indirect 0x0208)
227  * Free Resources command (indirect 0x0209)
228  */
229 struct ice_aqc_alloc_free_res_cmd {
230 	__le16 num_entries; /* Number of Resource entries */
231 	u8 reserved[6];
232 	__le32 addr_high;
233 	__le32 addr_low;
234 };
235 
236 /* Resource descriptor */
237 struct ice_aqc_res_elem {
238 	union {
239 		__le16 sw_resp;
240 		__le16 flu_resp;
241 	} e;
242 };
243 
244 /* Buffer for Allocate/Free Resources commands */
245 struct ice_aqc_alloc_free_res_elem {
246 	__le16 res_type; /* Types defined above cmd 0x0204 */
247 #define ICE_AQC_RES_TYPE_SHARED_S	7
248 #define ICE_AQC_RES_TYPE_SHARED_M	(0x1 << ICE_AQC_RES_TYPE_SHARED_S)
249 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S	8
250 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M	\
251 				(0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
252 	__le16 num_elems;
253 	struct ice_aqc_res_elem elem[1];
254 };
255 
256 /* Add VSI (indirect 0x0210)
257  * Update VSI (indirect 0x0211)
258  * Get VSI (indirect 0x0212)
259  * Free VSI (indirect 0x0213)
260  */
261 struct ice_aqc_add_get_update_free_vsi {
262 	__le16 vsi_num;
263 #define ICE_AQ_VSI_NUM_S	0
264 #define ICE_AQ_VSI_NUM_M	(0x03FF << ICE_AQ_VSI_NUM_S)
265 #define ICE_AQ_VSI_IS_VALID	BIT(15)
266 	__le16 cmd_flags;
267 #define ICE_AQ_VSI_KEEP_ALLOC	0x1
268 	u8 vf_id;
269 	u8 reserved;
270 	__le16 vsi_flags;
271 #define ICE_AQ_VSI_TYPE_S	0
272 #define ICE_AQ_VSI_TYPE_M	(0x3 << ICE_AQ_VSI_TYPE_S)
273 #define ICE_AQ_VSI_TYPE_VF	0x0
274 #define ICE_AQ_VSI_TYPE_VMDQ2	0x1
275 #define ICE_AQ_VSI_TYPE_PF	0x2
276 #define ICE_AQ_VSI_TYPE_EMP_MNG	0x3
277 	__le32 addr_high;
278 	__le32 addr_low;
279 };
280 
281 /* Response descriptor for:
282  * Add VSI (indirect 0x0210)
283  * Update VSI (indirect 0x0211)
284  * Free VSI (indirect 0x0213)
285  */
286 struct ice_aqc_add_update_free_vsi_resp {
287 	__le16 vsi_num;
288 	__le16 ext_status;
289 	__le16 vsi_used;
290 	__le16 vsi_free;
291 	__le32 addr_high;
292 	__le32 addr_low;
293 };
294 
295 struct ice_aqc_vsi_props {
296 	__le16 valid_sections;
297 #define ICE_AQ_VSI_PROP_SW_VALID		BIT(0)
298 #define ICE_AQ_VSI_PROP_SECURITY_VALID		BIT(1)
299 #define ICE_AQ_VSI_PROP_VLAN_VALID		BIT(2)
300 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID		BIT(3)
301 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID	BIT(4)
302 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID		BIT(5)
303 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID		BIT(6)
304 #define ICE_AQ_VSI_PROP_Q_OPT_VALID		BIT(7)
305 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID		BIT(8)
306 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID		BIT(11)
307 #define ICE_AQ_VSI_PROP_PASID_VALID		BIT(12)
308 	/* switch section */
309 	u8 sw_id;
310 	u8 sw_flags;
311 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB		BIT(5)
312 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB		BIT(6)
313 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE		BIT(7)
314 	u8 sw_flags2;
315 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S	0
316 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M	\
317 				(0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
318 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA	BIT(0)
319 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA		BIT(4)
320 	u8 veb_stat_id;
321 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S		0
322 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M	(0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
323 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID		BIT(5)
324 	/* security section */
325 	u8 sec_flags;
326 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD	BIT(0)
327 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF	BIT(2)
328 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S	4
329 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M	(0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
330 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA	BIT(0)
331 	u8 sec_reserved;
332 	/* VLAN section */
333 	__le16 pvid; /* VLANS include priority bits */
334 	u8 pvlan_reserved[2];
335 	u8 vlan_flags;
336 #define ICE_AQ_VSI_VLAN_MODE_S	0
337 #define ICE_AQ_VSI_VLAN_MODE_M	(0x3 << ICE_AQ_VSI_VLAN_MODE_S)
338 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED	0x1
339 #define ICE_AQ_VSI_VLAN_MODE_TAGGED	0x2
340 #define ICE_AQ_VSI_VLAN_MODE_ALL	0x3
341 #define ICE_AQ_VSI_PVLAN_INSERT_PVID	BIT(2)
342 #define ICE_AQ_VSI_VLAN_EMOD_S		3
343 #define ICE_AQ_VSI_VLAN_EMOD_M		(0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
344 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH	(0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
345 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP	(0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
346 #define ICE_AQ_VSI_VLAN_EMOD_STR	(0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
347 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING	(0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
348 	u8 pvlan_reserved2[3];
349 	/* ingress egress up sections */
350 	__le32 ingress_table; /* bitmap, 3 bits per up */
351 #define ICE_AQ_VSI_UP_TABLE_UP0_S	0
352 #define ICE_AQ_VSI_UP_TABLE_UP0_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
353 #define ICE_AQ_VSI_UP_TABLE_UP1_S	3
354 #define ICE_AQ_VSI_UP_TABLE_UP1_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
355 #define ICE_AQ_VSI_UP_TABLE_UP2_S	6
356 #define ICE_AQ_VSI_UP_TABLE_UP2_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
357 #define ICE_AQ_VSI_UP_TABLE_UP3_S	9
358 #define ICE_AQ_VSI_UP_TABLE_UP3_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
359 #define ICE_AQ_VSI_UP_TABLE_UP4_S	12
360 #define ICE_AQ_VSI_UP_TABLE_UP4_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
361 #define ICE_AQ_VSI_UP_TABLE_UP5_S	15
362 #define ICE_AQ_VSI_UP_TABLE_UP5_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
363 #define ICE_AQ_VSI_UP_TABLE_UP6_S	18
364 #define ICE_AQ_VSI_UP_TABLE_UP6_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
365 #define ICE_AQ_VSI_UP_TABLE_UP7_S	21
366 #define ICE_AQ_VSI_UP_TABLE_UP7_M	(0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
367 	__le32 egress_table;   /* same defines as for ingress table */
368 	/* outer tags section */
369 	__le16 outer_tag;
370 	u8 outer_tag_flags;
371 #define ICE_AQ_VSI_OUTER_TAG_MODE_S	0
372 #define ICE_AQ_VSI_OUTER_TAG_MODE_M	(0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
373 #define ICE_AQ_VSI_OUTER_TAG_NOTHING	0x0
374 #define ICE_AQ_VSI_OUTER_TAG_REMOVE	0x1
375 #define ICE_AQ_VSI_OUTER_TAG_COPY	0x2
376 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S	2
377 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M	(0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
378 #define ICE_AQ_VSI_OUTER_TAG_NONE	0x0
379 #define ICE_AQ_VSI_OUTER_TAG_STAG	0x1
380 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100	0x2
381 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100	0x3
382 #define ICE_AQ_VSI_OUTER_TAG_INSERT	BIT(4)
383 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
384 	u8 outer_tag_reserved;
385 	/* queue mapping section */
386 	__le16 mapping_flags;
387 #define ICE_AQ_VSI_Q_MAP_CONTIG	0x0
388 #define ICE_AQ_VSI_Q_MAP_NONCONTIG	BIT(0)
389 	__le16 q_mapping[16];
390 #define ICE_AQ_VSI_Q_S		0
391 #define ICE_AQ_VSI_Q_M		(0x7FF << ICE_AQ_VSI_Q_S)
392 	__le16 tc_mapping[8];
393 #define ICE_AQ_VSI_TC_Q_OFFSET_S	0
394 #define ICE_AQ_VSI_TC_Q_OFFSET_M	(0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
395 #define ICE_AQ_VSI_TC_Q_NUM_S		11
396 #define ICE_AQ_VSI_TC_Q_NUM_M		(0xF << ICE_AQ_VSI_TC_Q_NUM_S)
397 	/* queueing option section */
398 	u8 q_opt_rss;
399 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S	0
400 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M	(0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
401 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI	0x0
402 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF	0x2
403 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL	0x3
404 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S	2
405 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M	(0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
406 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S	6
407 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M	(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
408 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ	(0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
409 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ	(0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
410 #define ICE_AQ_VSI_Q_OPT_RSS_XOR	(0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
411 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH	(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
412 	u8 q_opt_tc;
413 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S	0
414 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M	(0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
415 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR	BIT(7)
416 	u8 q_opt_flags;
417 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN	BIT(0)
418 	u8 q_opt_reserved[3];
419 	/* outer up section */
420 	__le32 outer_up_table; /* same structure and defines as ingress tbl */
421 	/* section 10 */
422 	__le16 sect_10_reserved;
423 	/* flow director section */
424 	__le16 fd_options;
425 #define ICE_AQ_VSI_FD_ENABLE		BIT(0)
426 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE	BIT(1)
427 #define ICE_AQ_VSI_FD_PROG_ENABLE	BIT(3)
428 	__le16 max_fd_fltr_dedicated;
429 	__le16 max_fd_fltr_shared;
430 	__le16 fd_def_q;
431 #define ICE_AQ_VSI_FD_DEF_Q_S		0
432 #define ICE_AQ_VSI_FD_DEF_Q_M		(0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
433 #define ICE_AQ_VSI_FD_DEF_GRP_S	12
434 #define ICE_AQ_VSI_FD_DEF_GRP_M	(0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
435 	__le16 fd_report_opt;
436 #define ICE_AQ_VSI_FD_REPORT_Q_S	0
437 #define ICE_AQ_VSI_FD_REPORT_Q_M	(0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
438 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S	12
439 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M	(0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
440 #define ICE_AQ_VSI_FD_DEF_DROP		BIT(15)
441 	/* PASID section */
442 	__le32 pasid_id;
443 #define ICE_AQ_VSI_PASID_ID_S		0
444 #define ICE_AQ_VSI_PASID_ID_M		(0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
445 #define ICE_AQ_VSI_PASID_ID_VALID	BIT(31)
446 	u8 reserved[24];
447 };
448 
449 #define ICE_MAX_NUM_RECIPES 64
450 
451 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
452  */
453 struct ice_aqc_sw_rules {
454 	/* ops: add switch rules, referring the number of rules.
455 	 * ops: update switch rules, referring the number of filters
456 	 * ops: remove switch rules, referring the entry index.
457 	 * ops: get switch rules, referring to the number of filters.
458 	 */
459 	__le16 num_rules_fltr_entry_index;
460 	u8 reserved[6];
461 	__le32 addr_high;
462 	__le32 addr_low;
463 };
464 
465 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
466  * This structures describes the lookup rules and associated actions. "index"
467  * is returned as part of a response to a successful Add command, and can be
468  * used to identify the rule for Update/Get/Remove commands.
469  */
470 struct ice_sw_rule_lkup_rx_tx {
471 	__le16 recipe_id;
472 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD		10
473 	/* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
474 	__le16 src;
475 	__le32 act;
476 
477 	/* Bit 0:1 - Action type */
478 #define ICE_SINGLE_ACT_TYPE_S	0x00
479 #define ICE_SINGLE_ACT_TYPE_M	(0x3 << ICE_SINGLE_ACT_TYPE_S)
480 
481 	/* Bit 2 - Loop back enable
482 	 * Bit 3 - LAN enable
483 	 */
484 #define ICE_SINGLE_ACT_LB_ENABLE	BIT(2)
485 #define ICE_SINGLE_ACT_LAN_ENABLE	BIT(3)
486 
487 	/* Action type = 0 - Forward to VSI or VSI list */
488 #define ICE_SINGLE_ACT_VSI_FORWARDING	0x0
489 
490 #define ICE_SINGLE_ACT_VSI_ID_S		4
491 #define ICE_SINGLE_ACT_VSI_ID_M		(0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
492 #define ICE_SINGLE_ACT_VSI_LIST_ID_S	4
493 #define ICE_SINGLE_ACT_VSI_LIST_ID_M	(0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
494 	/* This bit needs to be set if action is forward to VSI list */
495 #define ICE_SINGLE_ACT_VSI_LIST		BIT(14)
496 #define ICE_SINGLE_ACT_VALID_BIT	BIT(17)
497 #define ICE_SINGLE_ACT_DROP		BIT(18)
498 
499 	/* Action type = 1 - Forward to Queue of Queue group */
500 #define ICE_SINGLE_ACT_TO_Q		0x1
501 #define ICE_SINGLE_ACT_Q_INDEX_S	4
502 #define ICE_SINGLE_ACT_Q_INDEX_M	(0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
503 #define ICE_SINGLE_ACT_Q_REGION_S	15
504 #define ICE_SINGLE_ACT_Q_REGION_M	(0x7 << ICE_SINGLE_ACT_Q_REGION_S)
505 #define ICE_SINGLE_ACT_Q_PRIORITY	BIT(18)
506 
507 	/* Action type = 2 - Prune */
508 #define ICE_SINGLE_ACT_PRUNE		0x2
509 #define ICE_SINGLE_ACT_EGRESS		BIT(15)
510 #define ICE_SINGLE_ACT_INGRESS		BIT(16)
511 #define ICE_SINGLE_ACT_PRUNET		BIT(17)
512 	/* Bit 18 should be set to 0 for this action */
513 
514 	/* Action type = 2 - Pointer */
515 #define ICE_SINGLE_ACT_PTR		0x2
516 #define ICE_SINGLE_ACT_PTR_VAL_S	4
517 #define ICE_SINGLE_ACT_PTR_VAL_M	(0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
518 	/* Bit 18 should be set to 1 */
519 #define ICE_SINGLE_ACT_PTR_BIT		BIT(18)
520 
521 	/* Action type = 3 - Other actions. Last two bits
522 	 * are other action identifier
523 	 */
524 #define ICE_SINGLE_ACT_OTHER_ACTS		0x3
525 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S	17
526 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M	\
527 				(0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
528 
529 	/* Bit 17:18 - Defines other actions */
530 	/* Other action = 0 - Mirror VSI */
531 #define ICE_SINGLE_OTHER_ACT_MIRROR		0
532 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S	4
533 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M	\
534 				(0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
535 
536 	/* Other action = 3 - Set Stat count */
537 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT		3
538 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S	4
539 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M	\
540 				(0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
541 
542 	__le16 index; /* The index of the rule in the lookup table */
543 	/* Length and values of the header to be matched per recipe or
544 	 * lookup-type
545 	 */
546 	__le16 hdr_len;
547 	u8 hdr[1];
548 } __packed;
549 
550 /* Add/Update/Remove large action command/response entry
551  * "index" is returned as part of a response to a successful Add command, and
552  * can be used to identify the action for Update/Get/Remove commands.
553  */
554 struct ice_sw_rule_lg_act {
555 	__le16 index; /* Index in large action table */
556 	__le16 size;
557 	__le32 act[1]; /* array of size for actions */
558 	/* Max number of large actions */
559 #define ICE_MAX_LG_ACT	4
560 	/* Bit 0:1 - Action type */
561 #define ICE_LG_ACT_TYPE_S	0
562 #define ICE_LG_ACT_TYPE_M	(0x7 << ICE_LG_ACT_TYPE_S)
563 
564 	/* Action type = 0 - Forward to VSI or VSI list */
565 #define ICE_LG_ACT_VSI_FORWARDING	0
566 #define ICE_LG_ACT_VSI_ID_S		3
567 #define ICE_LG_ACT_VSI_ID_M		(0x3FF << ICE_LG_ACT_VSI_ID_S)
568 #define ICE_LG_ACT_VSI_LIST_ID_S	3
569 #define ICE_LG_ACT_VSI_LIST_ID_M	(0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
570 	/* This bit needs to be set if action is forward to VSI list */
571 #define ICE_LG_ACT_VSI_LIST		BIT(13)
572 
573 #define ICE_LG_ACT_VALID_BIT		BIT(16)
574 
575 	/* Action type = 1 - Forward to Queue of Queue group */
576 #define ICE_LG_ACT_TO_Q			0x1
577 #define ICE_LG_ACT_Q_INDEX_S		3
578 #define ICE_LG_ACT_Q_INDEX_M		(0x7FF << ICE_LG_ACT_Q_INDEX_S)
579 #define ICE_LG_ACT_Q_REGION_S		14
580 #define ICE_LG_ACT_Q_REGION_M		(0x7 << ICE_LG_ACT_Q_REGION_S)
581 #define ICE_LG_ACT_Q_PRIORITY_SET	BIT(17)
582 
583 	/* Action type = 2 - Prune */
584 #define ICE_LG_ACT_PRUNE		0x2
585 #define ICE_LG_ACT_EGRESS		BIT(14)
586 #define ICE_LG_ACT_INGRESS		BIT(15)
587 #define ICE_LG_ACT_PRUNET		BIT(16)
588 
589 	/* Action type = 3 - Mirror VSI */
590 #define ICE_LG_OTHER_ACT_MIRROR		0x3
591 #define ICE_LG_ACT_MIRROR_VSI_ID_S	3
592 #define ICE_LG_ACT_MIRROR_VSI_ID_M	(0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
593 
594 	/* Action type = 5 - Generic Value */
595 #define ICE_LG_ACT_GENERIC		0x5
596 #define ICE_LG_ACT_GENERIC_VALUE_S	3
597 #define ICE_LG_ACT_GENERIC_VALUE_M	(0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
598 #define ICE_LG_ACT_GENERIC_OFFSET_S	19
599 #define ICE_LG_ACT_GENERIC_OFFSET_M	(0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
600 #define ICE_LG_ACT_GENERIC_PRIORITY_S	22
601 #define ICE_LG_ACT_GENERIC_PRIORITY_M	(0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
602 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX	7
603 
604 	/* Action = 7 - Set Stat count */
605 #define ICE_LG_ACT_STAT_COUNT		0x7
606 #define ICE_LG_ACT_STAT_COUNT_S		3
607 #define ICE_LG_ACT_STAT_COUNT_M		(0x7F << ICE_LG_ACT_STAT_COUNT_S)
608 };
609 
610 /* Add/Update/Remove VSI list command/response entry
611  * "index" is returned as part of a response to a successful Add command, and
612  * can be used to identify the VSI list for Update/Get/Remove commands.
613  */
614 struct ice_sw_rule_vsi_list {
615 	__le16 index; /* Index of VSI/Prune list */
616 	__le16 number_vsi;
617 	__le16 vsi[1]; /* Array of number_vsi VSI numbers */
618 };
619 
620 /* Query VSI list command/response entry */
621 struct ice_sw_rule_vsi_list_query {
622 	__le16 index;
623 	DECLARE_BITMAP(vsi_list, ICE_MAX_VSI);
624 } __packed;
625 
626 /* Add switch rule response:
627  * Content of return buffer is same as the input buffer. The status field and
628  * LUT index are updated as part of the response
629  */
630 struct ice_aqc_sw_rules_elem {
631 	__le16 type; /* Switch rule type, one of T_... */
632 #define ICE_AQC_SW_RULES_T_LKUP_RX		0x0
633 #define ICE_AQC_SW_RULES_T_LKUP_TX		0x1
634 #define ICE_AQC_SW_RULES_T_LG_ACT		0x2
635 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET		0x3
636 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR	0x4
637 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET	0x5
638 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR	0x6
639 	__le16 status;
640 	union {
641 		struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
642 		struct ice_sw_rule_lg_act lg_act;
643 		struct ice_sw_rule_vsi_list vsi_list;
644 		struct ice_sw_rule_vsi_list_query vsi_list_query;
645 	} __packed pdata;
646 };
647 
648 /* Get Default Topology (indirect 0x0400) */
649 struct ice_aqc_get_topo {
650 	u8 port_num;
651 	u8 num_branches;
652 	__le16 reserved1;
653 	__le32 reserved2;
654 	__le32 addr_high;
655 	__le32 addr_low;
656 };
657 
658 /* Update TSE (indirect 0x0403)
659  * Get TSE (indirect 0x0404)
660  */
661 struct ice_aqc_get_cfg_elem {
662 	__le16 num_elem_req;	/* Used by commands */
663 	__le16 num_elem_resp;	/* Used by responses */
664 	__le32 reserved;
665 	__le32 addr_high;
666 	__le32 addr_low;
667 };
668 
669 /* This is the buffer for:
670  * Suspend Nodes (indirect 0x0409)
671  * Resume Nodes (indirect 0x040A)
672  */
673 struct ice_aqc_suspend_resume_elem {
674 	__le32 teid[1];
675 };
676 
677 /* Add TSE (indirect 0x0401)
678  * Delete TSE (indirect 0x040F)
679  * Move TSE (indirect 0x0408)
680  */
681 struct ice_aqc_add_move_delete_elem {
682 	__le16 num_grps_req;
683 	__le16 num_grps_updated;
684 	__le32 reserved;
685 	__le32 addr_high;
686 	__le32 addr_low;
687 };
688 
689 struct ice_aqc_elem_info_bw {
690 	__le16 bw_profile_idx;
691 	__le16 bw_alloc;
692 };
693 
694 struct ice_aqc_txsched_elem {
695 	u8 elem_type; /* Special field, reserved for some aq calls */
696 #define ICE_AQC_ELEM_TYPE_UNDEFINED		0x0
697 #define ICE_AQC_ELEM_TYPE_ROOT_PORT		0x1
698 #define ICE_AQC_ELEM_TYPE_TC			0x2
699 #define ICE_AQC_ELEM_TYPE_SE_GENERIC		0x3
700 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT		0x4
701 #define ICE_AQC_ELEM_TYPE_LEAF			0x5
702 #define ICE_AQC_ELEM_TYPE_SE_PADDED		0x6
703 	u8 valid_sections;
704 #define ICE_AQC_ELEM_VALID_GENERIC		BIT(0)
705 #define ICE_AQC_ELEM_VALID_CIR			BIT(1)
706 #define ICE_AQC_ELEM_VALID_EIR			BIT(2)
707 #define ICE_AQC_ELEM_VALID_SHARED		BIT(3)
708 	u8 generic;
709 #define ICE_AQC_ELEM_GENERIC_MODE_M		0x1
710 #define ICE_AQC_ELEM_GENERIC_PRIO_S		0x1
711 #define ICE_AQC_ELEM_GENERIC_PRIO_M	(0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
712 #define ICE_AQC_ELEM_GENERIC_SP_S		0x4
713 #define ICE_AQC_ELEM_GENERIC_SP_M	(0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
714 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S	0x5
715 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M	\
716 	(0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
717 	u8 flags; /* Special field, reserved for some aq calls */
718 #define ICE_AQC_ELEM_FLAG_SUSPEND_M		0x1
719 	struct ice_aqc_elem_info_bw cir_bw;
720 	struct ice_aqc_elem_info_bw eir_bw;
721 	__le16 srl_id;
722 	__le16 reserved2;
723 };
724 
725 struct ice_aqc_txsched_elem_data {
726 	__le32 parent_teid;
727 	__le32 node_teid;
728 	struct ice_aqc_txsched_elem data;
729 };
730 
731 struct ice_aqc_txsched_topo_grp_info_hdr {
732 	__le32 parent_teid;
733 	__le16 num_elems;
734 	__le16 reserved2;
735 };
736 
737 struct ice_aqc_add_elem {
738 	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
739 	struct ice_aqc_txsched_elem_data generic[1];
740 };
741 
742 struct ice_aqc_get_elem {
743 	struct ice_aqc_txsched_elem_data generic[1];
744 };
745 
746 struct ice_aqc_get_topo_elem {
747 	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
748 	struct ice_aqc_txsched_elem_data
749 		generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
750 };
751 
752 struct ice_aqc_delete_elem {
753 	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
754 	__le32 teid[1];
755 };
756 
757 /* Query Scheduler Resource Allocation (indirect 0x0412)
758  * This indirect command retrieves the scheduler resources allocated by
759  * EMP Firmware to the given PF.
760  */
761 struct ice_aqc_query_txsched_res {
762 	u8 reserved[8];
763 	__le32 addr_high;
764 	__le32 addr_low;
765 };
766 
767 struct ice_aqc_generic_sched_props {
768 	__le16 phys_levels;
769 	__le16 logical_levels;
770 	u8 flattening_bitmap;
771 	u8 max_device_cgds;
772 	u8 max_pf_cgds;
773 	u8 rsvd0;
774 	__le16 rdma_qsets;
775 	u8 rsvd1[22];
776 };
777 
778 struct ice_aqc_layer_props {
779 	u8 logical_layer;
780 	u8 chunk_size;
781 	__le16 max_device_nodes;
782 	__le16 max_pf_nodes;
783 	u8 rsvd0[4];
784 	__le16 max_sibl_grp_sz;
785 	__le16 max_cir_rl_profiles;
786 	__le16 max_eir_rl_profiles;
787 	__le16 max_srl_profiles;
788 	u8 rsvd1[14];
789 };
790 
791 struct ice_aqc_query_txsched_res_resp {
792 	struct ice_aqc_generic_sched_props sched_props;
793 	struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
794 };
795 
796 /* Get PHY capabilities (indirect 0x0600) */
797 struct ice_aqc_get_phy_caps {
798 	u8 lport_num;
799 	u8 reserved;
800 	__le16 param0;
801 	/* 18.0 - Report qualified modules */
802 #define ICE_AQC_GET_PHY_RQM		BIT(0)
803 	/* 18.1 - 18.2 : Report mode
804 	 * 00b - Report NVM capabilities
805 	 * 01b - Report topology capabilities
806 	 * 10b - Report SW configured
807 	 */
808 #define ICE_AQC_REPORT_MODE_S		1
809 #define ICE_AQC_REPORT_MODE_M		(3 << ICE_AQC_REPORT_MODE_S)
810 #define ICE_AQC_REPORT_NVM_CAP		0
811 #define ICE_AQC_REPORT_TOPO_CAP		BIT(1)
812 #define ICE_AQC_REPORT_SW_CFG		BIT(2)
813 	__le32 reserved1;
814 	__le32 addr_high;
815 	__le32 addr_low;
816 };
817 
818 /* This is #define of PHY type (Extended):
819  * The first set of defines is for phy_type_low.
820  */
821 #define ICE_PHY_TYPE_LOW_100BASE_TX		BIT_ULL(0)
822 #define ICE_PHY_TYPE_LOW_100M_SGMII		BIT_ULL(1)
823 #define ICE_PHY_TYPE_LOW_1000BASE_T		BIT_ULL(2)
824 #define ICE_PHY_TYPE_LOW_1000BASE_SX		BIT_ULL(3)
825 #define ICE_PHY_TYPE_LOW_1000BASE_LX		BIT_ULL(4)
826 #define ICE_PHY_TYPE_LOW_1000BASE_KX		BIT_ULL(5)
827 #define ICE_PHY_TYPE_LOW_1G_SGMII		BIT_ULL(6)
828 #define ICE_PHY_TYPE_LOW_2500BASE_T		BIT_ULL(7)
829 #define ICE_PHY_TYPE_LOW_2500BASE_X		BIT_ULL(8)
830 #define ICE_PHY_TYPE_LOW_2500BASE_KX		BIT_ULL(9)
831 #define ICE_PHY_TYPE_LOW_5GBASE_T		BIT_ULL(10)
832 #define ICE_PHY_TYPE_LOW_5GBASE_KR		BIT_ULL(11)
833 #define ICE_PHY_TYPE_LOW_10GBASE_T		BIT_ULL(12)
834 #define ICE_PHY_TYPE_LOW_10G_SFI_DA		BIT_ULL(13)
835 #define ICE_PHY_TYPE_LOW_10GBASE_SR		BIT_ULL(14)
836 #define ICE_PHY_TYPE_LOW_10GBASE_LR		BIT_ULL(15)
837 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1		BIT_ULL(16)
838 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC	BIT_ULL(17)
839 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C		BIT_ULL(18)
840 #define ICE_PHY_TYPE_LOW_25GBASE_T		BIT_ULL(19)
841 #define ICE_PHY_TYPE_LOW_25GBASE_CR		BIT_ULL(20)
842 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S		BIT_ULL(21)
843 #define ICE_PHY_TYPE_LOW_25GBASE_CR1		BIT_ULL(22)
844 #define ICE_PHY_TYPE_LOW_25GBASE_SR		BIT_ULL(23)
845 #define ICE_PHY_TYPE_LOW_25GBASE_LR		BIT_ULL(24)
846 #define ICE_PHY_TYPE_LOW_25GBASE_KR		BIT_ULL(25)
847 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S		BIT_ULL(26)
848 #define ICE_PHY_TYPE_LOW_25GBASE_KR1		BIT_ULL(27)
849 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC	BIT_ULL(28)
850 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C		BIT_ULL(29)
851 #define ICE_PHY_TYPE_LOW_40GBASE_CR4		BIT_ULL(30)
852 #define ICE_PHY_TYPE_LOW_40GBASE_SR4		BIT_ULL(31)
853 #define ICE_PHY_TYPE_LOW_40GBASE_LR4		BIT_ULL(32)
854 #define ICE_PHY_TYPE_LOW_40GBASE_KR4		BIT_ULL(33)
855 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC	BIT_ULL(34)
856 #define ICE_PHY_TYPE_LOW_40G_XLAUI		BIT_ULL(35)
857 #define ICE_PHY_TYPE_LOW_MAX_INDEX		63
858 
859 struct ice_aqc_get_phy_caps_data {
860 	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
861 	__le64 reserved;
862 	u8 caps;
863 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE			BIT(0)
864 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE			BIT(1)
865 #define ICE_AQC_PHY_LOW_POWER_MODE			BIT(2)
866 #define ICE_AQC_PHY_EN_LINK				BIT(3)
867 #define ICE_AQC_PHY_AN_MODE				BIT(4)
868 #define ICE_AQC_GET_PHY_EN_MOD_QUAL			BIT(5)
869 	u8 low_power_ctrl;
870 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG		BIT(0)
871 	__le16 eee_cap;
872 #define ICE_AQC_PHY_EEE_EN_100BASE_TX			BIT(0)
873 #define ICE_AQC_PHY_EEE_EN_1000BASE_T			BIT(1)
874 #define ICE_AQC_PHY_EEE_EN_10GBASE_T			BIT(2)
875 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX			BIT(3)
876 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR			BIT(4)
877 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR			BIT(5)
878 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4			BIT(6)
879 	__le16 eeer_value;
880 	u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
881 	u8 link_fec_options;
882 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN		BIT(0)
883 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ		BIT(1)
884 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ			BIT(2)
885 #define ICE_AQC_PHY_FEC_25G_KR_REQ			BIT(3)
886 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ			BIT(4)
887 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN		BIT(6)
888 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN		BIT(7)
889 	u8 extended_compliance_code;
890 #define ICE_MODULE_TYPE_TOTAL_BYTE			3
891 	u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
892 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS			0xA0
893 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS		0x80
894 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE	BIT(0)
895 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE	BIT(1)
896 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR		BIT(4)
897 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR		BIT(5)
898 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM		BIT(6)
899 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER		BIT(7)
900 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS			0xA0
901 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS		0x86
902 	u8 qualified_module_count;
903 #define ICE_AQC_QUAL_MOD_COUNT_MAX			16
904 	struct {
905 		u8 v_oui[3];
906 		u8 rsvd1;
907 		u8 v_part[16];
908 		__le32 v_rev;
909 		__le64 rsvd8;
910 	} qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
911 };
912 
913 /* Set PHY capabilities (direct 0x0601)
914  * NOTE: This command must be followed by setup link and restart auto-neg
915  */
916 struct ice_aqc_set_phy_cfg {
917 	u8 lport_num;
918 	u8 reserved[7];
919 	__le32 addr_high;
920 	__le32 addr_low;
921 };
922 
923 /* Set PHY config command data structure */
924 struct ice_aqc_set_phy_cfg_data {
925 	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
926 	__le64 rsvd0;
927 	u8 caps;
928 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY		BIT(0)
929 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY		BIT(1)
930 #define ICE_AQ_PHY_ENA_LOW_POWER	BIT(2)
931 #define ICE_AQ_PHY_ENA_LINK		BIT(3)
932 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT	BIT(5)
933 #define ICE_AQ_PHY_ENA_LESM		BIT(6)
934 #define ICE_AQ_PHY_ENA_AUTO_FEC		BIT(7)
935 	u8 low_power_ctrl;
936 	__le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
937 	__le16 eeer_value;
938 	u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
939 	u8 rsvd1;
940 };
941 
942 /* Restart AN command data structure (direct 0x0605)
943  * Also used for response, with only the lport_num field present.
944  */
945 struct ice_aqc_restart_an {
946 	u8 lport_num;
947 	u8 reserved;
948 	u8 cmd_flags;
949 #define ICE_AQC_RESTART_AN_LINK_RESTART	BIT(1)
950 #define ICE_AQC_RESTART_AN_LINK_ENABLE	BIT(2)
951 	u8 reserved2[13];
952 };
953 
954 /* Get link status (indirect 0x0607), also used for Link Status Event */
955 struct ice_aqc_get_link_status {
956 	u8 lport_num;
957 	u8 reserved;
958 	__le16 cmd_flags;
959 #define ICE_AQ_LSE_M			0x3
960 #define ICE_AQ_LSE_NOP			0x0
961 #define ICE_AQ_LSE_DIS			0x2
962 #define ICE_AQ_LSE_ENA			0x3
963 	/* only response uses this flag */
964 #define ICE_AQ_LSE_IS_ENABLED		0x1
965 	__le32 reserved2;
966 	__le32 addr_high;
967 	__le32 addr_low;
968 };
969 
970 /* Get link status response data structure, also used for Link Status Event */
971 struct ice_aqc_get_link_status_data {
972 	u8 topo_media_conflict;
973 #define ICE_AQ_LINK_TOPO_CONFLICT	BIT(0)
974 #define ICE_AQ_LINK_MEDIA_CONFLICT	BIT(1)
975 #define ICE_AQ_LINK_TOPO_CORRUPT	BIT(2)
976 	u8 reserved1;
977 	u8 link_info;
978 #define ICE_AQ_LINK_UP			BIT(0)	/* Link Status */
979 #define ICE_AQ_LINK_FAULT		BIT(1)
980 #define ICE_AQ_LINK_FAULT_TX		BIT(2)
981 #define ICE_AQ_LINK_FAULT_RX		BIT(3)
982 #define ICE_AQ_LINK_FAULT_REMOTE	BIT(4)
983 #define ICE_AQ_LINK_UP_PORT		BIT(5)	/* External Port Link Status */
984 #define ICE_AQ_MEDIA_AVAILABLE		BIT(6)
985 #define ICE_AQ_SIGNAL_DETECT		BIT(7)
986 	u8 an_info;
987 #define ICE_AQ_AN_COMPLETED		BIT(0)
988 #define ICE_AQ_LP_AN_ABILITY		BIT(1)
989 #define ICE_AQ_PD_FAULT			BIT(2)	/* Parallel Detection Fault */
990 #define ICE_AQ_FEC_EN			BIT(3)
991 #define ICE_AQ_PHY_LOW_POWER		BIT(4)	/* Low Power State */
992 #define ICE_AQ_LINK_PAUSE_TX		BIT(5)
993 #define ICE_AQ_LINK_PAUSE_RX		BIT(6)
994 #define ICE_AQ_QUALIFIED_MODULE		BIT(7)
995 	u8 ext_info;
996 #define ICE_AQ_LINK_PHY_TEMP_ALARM	BIT(0)
997 #define ICE_AQ_LINK_EXCESSIVE_ERRORS	BIT(1)	/* Excessive Link Errors */
998 	/* Port TX Suspended */
999 #define ICE_AQ_LINK_TX_S		2
1000 #define ICE_AQ_LINK_TX_M		(0x03 << ICE_AQ_LINK_TX_S)
1001 #define ICE_AQ_LINK_TX_ACTIVE		0
1002 #define ICE_AQ_LINK_TX_DRAINED		1
1003 #define ICE_AQ_LINK_TX_FLUSHED		3
1004 	u8 reserved2;
1005 	__le16 max_frame_size;
1006 	u8 cfg;
1007 #define ICE_AQ_LINK_25G_KR_FEC_EN	BIT(0)
1008 #define ICE_AQ_LINK_25G_RS_528_FEC_EN	BIT(1)
1009 #define ICE_AQ_LINK_25G_RS_544_FEC_EN	BIT(2)
1010 	/* Pacing Config */
1011 #define ICE_AQ_CFG_PACING_S		3
1012 #define ICE_AQ_CFG_PACING_M		(0xF << ICE_AQ_CFG_PACING_S)
1013 #define ICE_AQ_CFG_PACING_TYPE_M	BIT(7)
1014 #define ICE_AQ_CFG_PACING_TYPE_AVG	0
1015 #define ICE_AQ_CFG_PACING_TYPE_FIXED	ICE_AQ_CFG_PACING_TYPE_M
1016 	/* External Device Power Ability */
1017 	u8 power_desc;
1018 #define ICE_AQ_PWR_CLASS_M		0x3
1019 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH	0
1020 #define ICE_AQ_LINK_PWR_BASET_HIGH	1
1021 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1	0
1022 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2	1
1023 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3	2
1024 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4	3
1025 	__le16 link_speed;
1026 #define ICE_AQ_LINK_SPEED_10MB		BIT(0)
1027 #define ICE_AQ_LINK_SPEED_100MB		BIT(1)
1028 #define ICE_AQ_LINK_SPEED_1000MB	BIT(2)
1029 #define ICE_AQ_LINK_SPEED_2500MB	BIT(3)
1030 #define ICE_AQ_LINK_SPEED_5GB		BIT(4)
1031 #define ICE_AQ_LINK_SPEED_10GB		BIT(5)
1032 #define ICE_AQ_LINK_SPEED_20GB		BIT(6)
1033 #define ICE_AQ_LINK_SPEED_25GB		BIT(7)
1034 #define ICE_AQ_LINK_SPEED_40GB		BIT(8)
1035 #define ICE_AQ_LINK_SPEED_UNKNOWN	BIT(15)
1036 	__le32 reserved3; /* Aligns next field to 8-byte boundary */
1037 	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1038 	__le64 reserved4;
1039 };
1040 
1041 /* Set event mask command (direct 0x0613) */
1042 struct ice_aqc_set_event_mask {
1043 	u8	lport_num;
1044 	u8	reserved[7];
1045 	__le16	event_mask;
1046 #define ICE_AQ_LINK_EVENT_UPDOWN		BIT(1)
1047 #define ICE_AQ_LINK_EVENT_MEDIA_NA		BIT(2)
1048 #define ICE_AQ_LINK_EVENT_LINK_FAULT		BIT(3)
1049 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM	BIT(4)
1050 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS	BIT(5)
1051 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT		BIT(6)
1052 #define ICE_AQ_LINK_EVENT_AN_COMPLETED		BIT(7)
1053 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL	BIT(8)
1054 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED	BIT(9)
1055 	u8	reserved1[6];
1056 };
1057 
1058 /* NVM Read command (indirect 0x0701)
1059  * NVM Erase commands (direct 0x0702)
1060  * NVM Update commands (indirect 0x0703)
1061  */
1062 struct ice_aqc_nvm {
1063 	__le16 offset_low;
1064 	u8 offset_high;
1065 	u8 cmd_flags;
1066 #define ICE_AQC_NVM_LAST_CMD		BIT(0)
1067 #define ICE_AQC_NVM_PCIR_REQ		BIT(0)	/* Used by NVM Update reply */
1068 #define ICE_AQC_NVM_PRESERVATION_S	1
1069 #define ICE_AQC_NVM_PRESERVATION_M	(3 << ICE_AQC_NVM_PRESERVATION_S)
1070 #define ICE_AQC_NVM_NO_PRESERVATION	(0 << ICE_AQC_NVM_PRESERVATION_S)
1071 #define ICE_AQC_NVM_PRESERVE_ALL	BIT(1)
1072 #define ICE_AQC_NVM_PRESERVE_SELECTED	(3 << ICE_AQC_NVM_PRESERVATION_S)
1073 #define ICE_AQC_NVM_FLASH_ONLY		BIT(7)
1074 	__le16 module_typeid;
1075 	__le16 length;
1076 #define ICE_AQC_NVM_ERASE_LEN	0xFFFF
1077 	__le32 addr_high;
1078 	__le32 addr_low;
1079 };
1080 
1081 /**
1082  * Send to PF command (indirect 0x0801) id is only used by PF
1083  *
1084  * Send to VF command (indirect 0x0802) id is only used by PF
1085  *
1086  */
1087 struct ice_aqc_pf_vf_msg {
1088 	__le32 id;
1089 	u32 reserved;
1090 	__le32 addr_high;
1091 	__le32 addr_low;
1092 };
1093 
1094 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1095 struct ice_aqc_get_set_rss_key {
1096 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID	BIT(15)
1097 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S	0
1098 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M	(0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1099 	__le16 vsi_id;
1100 	u8 reserved[6];
1101 	__le32 addr_high;
1102 	__le32 addr_low;
1103 };
1104 
1105 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE	0x28
1106 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE	0xC
1107 
1108 struct ice_aqc_get_set_rss_keys {
1109 	u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1110 	u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1111 };
1112 
1113 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1114 struct ice_aqc_get_set_rss_lut {
1115 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID	BIT(15)
1116 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S	0
1117 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M	(0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1118 	__le16 vsi_id;
1119 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S	0
1120 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M	\
1121 				(0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1122 
1123 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI	 0
1124 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF	 1
1125 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL	 2
1126 
1127 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S	 2
1128 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M	 \
1129 				(0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1130 
1131 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128	 128
1132 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1133 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512	 512
1134 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1135 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K	 2048
1136 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG	 2
1137 
1138 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S	 4
1139 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M	 \
1140 				(0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1141 
1142 	__le16 flags;
1143 	__le32 reserved;
1144 	__le32 addr_high;
1145 	__le32 addr_low;
1146 };
1147 
1148 /* Add TX LAN Queues (indirect 0x0C30) */
1149 struct ice_aqc_add_txqs {
1150 	u8 num_qgrps;
1151 	u8 reserved[3];
1152 	__le32 reserved1;
1153 	__le32 addr_high;
1154 	__le32 addr_low;
1155 };
1156 
1157 /* This is the descriptor of each queue entry for the Add TX LAN Queues
1158  * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1159  */
1160 struct ice_aqc_add_txqs_perq {
1161 	__le16 txq_id;
1162 	u8 rsvd[2];
1163 	__le32 q_teid;
1164 	u8 txq_ctx[22];
1165 	u8 rsvd2[2];
1166 	struct ice_aqc_txsched_elem info;
1167 };
1168 
1169 /* The format of the command buffer for Add TX LAN Queues (0x0C30)
1170  * is an array of the following structs. Please note that the length of
1171  * each struct ice_aqc_add_tx_qgrp is variable due
1172  * to the variable number of queues in each group!
1173  */
1174 struct ice_aqc_add_tx_qgrp {
1175 	__le32 parent_teid;
1176 	u8 num_txqs;
1177 	u8 rsvd[3];
1178 	struct ice_aqc_add_txqs_perq txqs[1];
1179 };
1180 
1181 /* Disable TX LAN Queues (indirect 0x0C31) */
1182 struct ice_aqc_dis_txqs {
1183 	u8 cmd_type;
1184 #define ICE_AQC_Q_DIS_CMD_S		0
1185 #define ICE_AQC_Q_DIS_CMD_M		(0x3 << ICE_AQC_Q_DIS_CMD_S)
1186 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET	(0 << ICE_AQC_Q_DIS_CMD_S)
1187 #define ICE_AQC_Q_DIS_CMD_VM_RESET	BIT(ICE_AQC_Q_DIS_CMD_S)
1188 #define ICE_AQC_Q_DIS_CMD_VF_RESET	(2 << ICE_AQC_Q_DIS_CMD_S)
1189 #define ICE_AQC_Q_DIS_CMD_PF_RESET	(3 << ICE_AQC_Q_DIS_CMD_S)
1190 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL	BIT(2)
1191 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE	BIT(3)
1192 	u8 num_entries;
1193 	__le16 vmvf_and_timeout;
1194 #define ICE_AQC_Q_DIS_VMVF_NUM_S	0
1195 #define ICE_AQC_Q_DIS_VMVF_NUM_M	(0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1196 #define ICE_AQC_Q_DIS_TIMEOUT_S		10
1197 #define ICE_AQC_Q_DIS_TIMEOUT_M		(0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1198 	__le32 blocked_cgds;
1199 	__le32 addr_high;
1200 	__le32 addr_low;
1201 };
1202 
1203 /* The buffer for Disable TX LAN Queues (indirect 0x0C31)
1204  * contains the following structures, arrayed one after the
1205  * other.
1206  * Note: Since the q_id is 16 bits wide, if the
1207  * number of queues is even, then 2 bytes of alignment MUST be
1208  * added before the start of the next group, to allow correct
1209  * alignment of the parent_teid field.
1210  */
1211 struct ice_aqc_dis_txq_item {
1212 	__le32 parent_teid;
1213 	u8 num_qs;
1214 	u8 rsvd;
1215 	/* The length of the q_id array varies according to num_qs */
1216 	__le16 q_id[1];
1217 	/* This only applies from F8 onward */
1218 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S		15
1219 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q	\
1220 			(0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1221 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET	\
1222 			(1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1223 };
1224 
1225 struct ice_aqc_dis_txq {
1226 	struct ice_aqc_dis_txq_item qgrps[1];
1227 };
1228 
1229 /* Configure Firmware Logging Command (indirect 0xFF09)
1230  * Logging Information Read Response (indirect 0xFF10)
1231  * Note: The 0xFF10 command has no input parameters.
1232  */
1233 struct ice_aqc_fw_logging {
1234 	u8 log_ctrl;
1235 #define ICE_AQC_FW_LOG_AQ_EN		BIT(0)
1236 #define ICE_AQC_FW_LOG_UART_EN		BIT(1)
1237 	u8 rsvd0;
1238 	u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
1239 #define ICE_AQC_FW_LOG_AQ_VALID		BIT(0)
1240 #define ICE_AQC_FW_LOG_UART_VALID	BIT(1)
1241 	u8 rsvd1[5];
1242 	__le32 addr_high;
1243 	__le32 addr_low;
1244 };
1245 
1246 enum ice_aqc_fw_logging_mod {
1247 	ICE_AQC_FW_LOG_ID_GENERAL = 0,
1248 	ICE_AQC_FW_LOG_ID_CTRL,
1249 	ICE_AQC_FW_LOG_ID_LINK,
1250 	ICE_AQC_FW_LOG_ID_LINK_TOPO,
1251 	ICE_AQC_FW_LOG_ID_DNL,
1252 	ICE_AQC_FW_LOG_ID_I2C,
1253 	ICE_AQC_FW_LOG_ID_SDP,
1254 	ICE_AQC_FW_LOG_ID_MDIO,
1255 	ICE_AQC_FW_LOG_ID_ADMINQ,
1256 	ICE_AQC_FW_LOG_ID_HDMA,
1257 	ICE_AQC_FW_LOG_ID_LLDP,
1258 	ICE_AQC_FW_LOG_ID_DCBX,
1259 	ICE_AQC_FW_LOG_ID_DCB,
1260 	ICE_AQC_FW_LOG_ID_NETPROXY,
1261 	ICE_AQC_FW_LOG_ID_NVM,
1262 	ICE_AQC_FW_LOG_ID_AUTH,
1263 	ICE_AQC_FW_LOG_ID_VPD,
1264 	ICE_AQC_FW_LOG_ID_IOSF,
1265 	ICE_AQC_FW_LOG_ID_PARSER,
1266 	ICE_AQC_FW_LOG_ID_SW,
1267 	ICE_AQC_FW_LOG_ID_SCHEDULER,
1268 	ICE_AQC_FW_LOG_ID_TXQ,
1269 	ICE_AQC_FW_LOG_ID_RSVD,
1270 	ICE_AQC_FW_LOG_ID_POST,
1271 	ICE_AQC_FW_LOG_ID_WATCHDOG,
1272 	ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
1273 	ICE_AQC_FW_LOG_ID_MNG,
1274 	ICE_AQC_FW_LOG_ID_MAX,
1275 };
1276 
1277 /* This is the buffer for both of the logging commands.
1278  * The entry array size depends on the datalen parameter in the descriptor.
1279  * There will be a total of datalen / 2 entries.
1280  */
1281 struct ice_aqc_fw_logging_data {
1282 	__le16 entry[1];
1283 #define ICE_AQC_FW_LOG_ID_S		0
1284 #define ICE_AQC_FW_LOG_ID_M		(0xFFF << ICE_AQC_FW_LOG_ID_S)
1285 
1286 #define ICE_AQC_FW_LOG_CONF_SUCCESS	0	/* Used by response */
1287 #define ICE_AQC_FW_LOG_CONF_BAD_INDX	BIT(12)	/* Used by response */
1288 
1289 #define ICE_AQC_FW_LOG_EN_S		12
1290 #define ICE_AQC_FW_LOG_EN_M		(0xF << ICE_AQC_FW_LOG_EN_S)
1291 #define ICE_AQC_FW_LOG_INFO_EN		BIT(12)	/* Used by command */
1292 #define ICE_AQC_FW_LOG_INIT_EN		BIT(13)	/* Used by command */
1293 #define ICE_AQC_FW_LOG_FLOW_EN		BIT(14)	/* Used by command */
1294 #define ICE_AQC_FW_LOG_ERR_EN		BIT(15)	/* Used by command */
1295 };
1296 
1297 /* Get/Clear FW Log (indirect 0xFF11) */
1298 struct ice_aqc_get_clear_fw_log {
1299 	u8 flags;
1300 #define ICE_AQC_FW_LOG_CLEAR		BIT(0)
1301 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL	BIT(1)
1302 	u8 rsvd1[7];
1303 	__le32 addr_high;
1304 	__le32 addr_low;
1305 };
1306 
1307 /**
1308  * struct ice_aq_desc - Admin Queue (AQ) descriptor
1309  * @flags: ICE_AQ_FLAG_* flags
1310  * @opcode: AQ command opcode
1311  * @datalen: length in bytes of indirect/external data buffer
1312  * @retval: return value from firmware
1313  * @cookie_h: opaque data high-half
1314  * @cookie_l: opaque data low-half
1315  * @params: command-specific parameters
1316  *
1317  * Descriptor format for commands the driver posts on the Admin Transmit Queue
1318  * (ATQ). The firmware writes back onto the command descriptor and returns
1319  * the result of the command. Asynchronous events that are not an immediate
1320  * result of the command are written to the Admin Receive Queue (ARQ) using
1321  * the same descriptor format. Descriptors are in little-endian notation with
1322  * 32-bit words.
1323  */
1324 struct ice_aq_desc {
1325 	__le16 flags;
1326 	__le16 opcode;
1327 	__le16 datalen;
1328 	__le16 retval;
1329 	__le32 cookie_high;
1330 	__le32 cookie_low;
1331 	union {
1332 		u8 raw[16];
1333 		struct ice_aqc_generic generic;
1334 		struct ice_aqc_get_ver get_ver;
1335 		struct ice_aqc_q_shutdown q_shutdown;
1336 		struct ice_aqc_req_res res_owner;
1337 		struct ice_aqc_manage_mac_read mac_read;
1338 		struct ice_aqc_manage_mac_write mac_write;
1339 		struct ice_aqc_clear_pxe clear_pxe;
1340 		struct ice_aqc_list_caps get_cap;
1341 		struct ice_aqc_get_phy_caps get_phy;
1342 		struct ice_aqc_set_phy_cfg set_phy;
1343 		struct ice_aqc_restart_an restart_an;
1344 		struct ice_aqc_get_sw_cfg get_sw_conf;
1345 		struct ice_aqc_sw_rules sw_rules;
1346 		struct ice_aqc_get_topo get_topo;
1347 		struct ice_aqc_get_cfg_elem get_update_elem;
1348 		struct ice_aqc_query_txsched_res query_sched_res;
1349 		struct ice_aqc_add_move_delete_elem add_move_delete_elem;
1350 		struct ice_aqc_nvm nvm;
1351 		struct ice_aqc_pf_vf_msg virt;
1352 		struct ice_aqc_get_set_rss_lut get_set_rss_lut;
1353 		struct ice_aqc_get_set_rss_key get_set_rss_key;
1354 		struct ice_aqc_add_txqs add_txqs;
1355 		struct ice_aqc_dis_txqs dis_txqs;
1356 		struct ice_aqc_add_get_update_free_vsi vsi_cmd;
1357 		struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
1358 		struct ice_aqc_fw_logging fw_logging;
1359 		struct ice_aqc_get_clear_fw_log get_clear_fw_log;
1360 		struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
1361 		struct ice_aqc_set_event_mask set_event_mask;
1362 		struct ice_aqc_get_link_status get_link_status;
1363 	} params;
1364 };
1365 
1366 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
1367 #define ICE_AQ_LG_BUF	512
1368 
1369 #define ICE_AQ_FLAG_ERR_S	2
1370 #define ICE_AQ_FLAG_LB_S	9
1371 #define ICE_AQ_FLAG_RD_S	10
1372 #define ICE_AQ_FLAG_BUF_S	12
1373 #define ICE_AQ_FLAG_SI_S	13
1374 
1375 #define ICE_AQ_FLAG_ERR		BIT(ICE_AQ_FLAG_ERR_S) /* 0x4    */
1376 #define ICE_AQ_FLAG_LB		BIT(ICE_AQ_FLAG_LB_S)  /* 0x200  */
1377 #define ICE_AQ_FLAG_RD		BIT(ICE_AQ_FLAG_RD_S)  /* 0x400  */
1378 #define ICE_AQ_FLAG_BUF		BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
1379 #define ICE_AQ_FLAG_SI		BIT(ICE_AQ_FLAG_SI_S)  /* 0x2000 */
1380 
1381 /* error codes */
1382 enum ice_aq_err {
1383 	ICE_AQ_RC_OK		= 0,  /* Success */
1384 	ICE_AQ_RC_ENOMEM	= 9,  /* Out of memory */
1385 	ICE_AQ_RC_EBUSY		= 12, /* Device or resource busy */
1386 	ICE_AQ_RC_EEXIST	= 13, /* Object already exists */
1387 	ICE_AQ_RC_ENOSPC	= 16, /* No space left or allocation failure */
1388 };
1389 
1390 /* Admin Queue command opcodes */
1391 enum ice_adminq_opc {
1392 	/* AQ commands */
1393 	ice_aqc_opc_get_ver				= 0x0001,
1394 	ice_aqc_opc_q_shutdown				= 0x0003,
1395 
1396 	/* resource ownership */
1397 	ice_aqc_opc_req_res				= 0x0008,
1398 	ice_aqc_opc_release_res				= 0x0009,
1399 
1400 	/* device/function capabilities */
1401 	ice_aqc_opc_list_func_caps			= 0x000A,
1402 	ice_aqc_opc_list_dev_caps			= 0x000B,
1403 
1404 	/* manage MAC address */
1405 	ice_aqc_opc_manage_mac_read			= 0x0107,
1406 	ice_aqc_opc_manage_mac_write			= 0x0108,
1407 
1408 	/* PXE */
1409 	ice_aqc_opc_clear_pxe_mode			= 0x0110,
1410 
1411 	/* internal switch commands */
1412 	ice_aqc_opc_get_sw_cfg				= 0x0200,
1413 
1414 	/* Alloc/Free/Get Resources */
1415 	ice_aqc_opc_alloc_res				= 0x0208,
1416 	ice_aqc_opc_free_res				= 0x0209,
1417 
1418 	/* VSI commands */
1419 	ice_aqc_opc_add_vsi				= 0x0210,
1420 	ice_aqc_opc_update_vsi				= 0x0211,
1421 	ice_aqc_opc_free_vsi				= 0x0213,
1422 
1423 	/* switch rules population commands */
1424 	ice_aqc_opc_add_sw_rules			= 0x02A0,
1425 	ice_aqc_opc_update_sw_rules			= 0x02A1,
1426 	ice_aqc_opc_remove_sw_rules			= 0x02A2,
1427 
1428 	ice_aqc_opc_clear_pf_cfg			= 0x02A4,
1429 
1430 	/* transmit scheduler commands */
1431 	ice_aqc_opc_get_dflt_topo			= 0x0400,
1432 	ice_aqc_opc_add_sched_elems			= 0x0401,
1433 	ice_aqc_opc_get_sched_elems			= 0x0404,
1434 	ice_aqc_opc_suspend_sched_elems			= 0x0409,
1435 	ice_aqc_opc_resume_sched_elems			= 0x040A,
1436 	ice_aqc_opc_delete_sched_elems			= 0x040F,
1437 	ice_aqc_opc_query_sched_res			= 0x0412,
1438 
1439 	/* PHY commands */
1440 	ice_aqc_opc_get_phy_caps			= 0x0600,
1441 	ice_aqc_opc_set_phy_cfg				= 0x0601,
1442 	ice_aqc_opc_restart_an				= 0x0605,
1443 	ice_aqc_opc_get_link_status			= 0x0607,
1444 	ice_aqc_opc_set_event_mask			= 0x0613,
1445 
1446 	/* NVM commands */
1447 	ice_aqc_opc_nvm_read				= 0x0701,
1448 
1449 	/* PF/VF mailbox commands */
1450 	ice_mbx_opc_send_msg_to_pf			= 0x0801,
1451 	ice_mbx_opc_send_msg_to_vf			= 0x0802,
1452 
1453 	/* RSS commands */
1454 	ice_aqc_opc_set_rss_key				= 0x0B02,
1455 	ice_aqc_opc_set_rss_lut				= 0x0B03,
1456 	ice_aqc_opc_get_rss_key				= 0x0B04,
1457 	ice_aqc_opc_get_rss_lut				= 0x0B05,
1458 
1459 	/* TX queue handling commands/events */
1460 	ice_aqc_opc_add_txqs				= 0x0C30,
1461 	ice_aqc_opc_dis_txqs				= 0x0C31,
1462 
1463 	/* debug commands */
1464 	ice_aqc_opc_fw_logging				= 0xFF09,
1465 };
1466 
1467 #endif /* _ICE_ADMINQ_CMD_H_ */
1468