1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_ADMINQ_CMD_H_ 5 #define _ICE_ADMINQ_CMD_H_ 6 7 /* This header file defines the Admin Queue commands, error codes and 8 * descriptor format. It is shared between Firmware and Software. 9 */ 10 11 #define ICE_MAX_VSI 768 12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 14 15 struct ice_aqc_generic { 16 __le32 param0; 17 __le32 param1; 18 __le32 addr_high; 19 __le32 addr_low; 20 }; 21 22 /* Get version (direct 0x0001) */ 23 struct ice_aqc_get_ver { 24 __le32 rom_ver; 25 __le32 fw_build; 26 u8 fw_branch; 27 u8 fw_major; 28 u8 fw_minor; 29 u8 fw_patch; 30 u8 api_branch; 31 u8 api_major; 32 u8 api_minor; 33 u8 api_patch; 34 }; 35 36 /* Queue Shutdown (direct 0x0003) */ 37 struct ice_aqc_q_shutdown { 38 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 39 __le32 driver_unloading; 40 u8 reserved[12]; 41 }; 42 43 /* Request resource ownership (direct 0x0008) 44 * Release resource ownership (direct 0x0009) 45 */ 46 struct ice_aqc_req_res { 47 __le16 res_id; 48 #define ICE_AQC_RES_ID_NVM 1 49 #define ICE_AQC_RES_ID_SDP 2 50 #define ICE_AQC_RES_ID_CHNG_LOCK 3 51 #define ICE_AQC_RES_ID_GLBL_LOCK 4 52 __le16 access_type; 53 #define ICE_AQC_RES_ACCESS_READ 1 54 #define ICE_AQC_RES_ACCESS_WRITE 2 55 56 /* Upon successful completion, FW writes this value and driver is 57 * expected to release resource before timeout. This value is provided 58 * in milliseconds. 59 */ 60 __le32 timeout; 61 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 62 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 63 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 64 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 65 /* For SDP: pin id of the SDP */ 66 __le32 res_number; 67 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 68 __le16 status; 69 #define ICE_AQ_RES_GLBL_SUCCESS 0 70 #define ICE_AQ_RES_GLBL_IN_PROG 1 71 #define ICE_AQ_RES_GLBL_DONE 2 72 u8 reserved[2]; 73 }; 74 75 /* Get function capabilities (indirect 0x000A) 76 * Get device capabilities (indirect 0x000B) 77 */ 78 struct ice_aqc_list_caps { 79 u8 cmd_flags; 80 u8 pf_index; 81 u8 reserved[2]; 82 __le32 count; 83 __le32 addr_high; 84 __le32 addr_low; 85 }; 86 87 /* Device/Function buffer entry, repeated per reported capability */ 88 struct ice_aqc_list_caps_elem { 89 __le16 cap; 90 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 91 #define ICE_AQC_CAPS_SRIOV 0x0012 92 #define ICE_AQC_CAPS_VF 0x0013 93 #define ICE_AQC_CAPS_VSI 0x0017 94 #define ICE_AQC_CAPS_RSS 0x0040 95 #define ICE_AQC_CAPS_RXQS 0x0041 96 #define ICE_AQC_CAPS_TXQS 0x0042 97 #define ICE_AQC_CAPS_MSIX 0x0043 98 #define ICE_AQC_CAPS_MAX_MTU 0x0047 99 100 u8 major_ver; 101 u8 minor_ver; 102 /* Number of resources described by this capability */ 103 __le32 number; 104 /* Only meaningful for some types of resources */ 105 __le32 logical_id; 106 /* Only meaningful for some types of resources */ 107 __le32 phys_id; 108 __le64 rsvd1; 109 __le64 rsvd2; 110 }; 111 112 /* Manage MAC address, read command - indirect (0x0107) 113 * This struct is also used for the response 114 */ 115 struct ice_aqc_manage_mac_read { 116 __le16 flags; /* Zeroed by device driver */ 117 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 118 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 119 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 120 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 121 #define ICE_AQC_MAN_MAC_READ_S 4 122 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 123 u8 lport_num; 124 u8 lport_num_valid; 125 #define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID BIT(0) 126 u8 num_addr; /* Used in response */ 127 u8 reserved[3]; 128 __le32 addr_high; 129 __le32 addr_low; 130 }; 131 132 /* Response buffer format for manage MAC read command */ 133 struct ice_aqc_manage_mac_read_resp { 134 u8 lport_num; 135 u8 addr_type; 136 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 137 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 138 u8 mac_addr[ETH_ALEN]; 139 }; 140 141 /* Manage MAC address, write command - direct (0x0108) */ 142 struct ice_aqc_manage_mac_write { 143 u8 port_num; 144 u8 flags; 145 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 146 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 147 #define ICE_AQC_MAN_MAC_WR_S 6 148 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S) 149 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 150 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S) 151 /* High 16 bits of MAC address in big endian order */ 152 __be16 sah; 153 /* Low 32 bits of MAC address in big endian order */ 154 __be32 sal; 155 __le32 addr_high; 156 __le32 addr_low; 157 }; 158 159 /* Clear PXE Command and response (direct 0x0110) */ 160 struct ice_aqc_clear_pxe { 161 u8 rx_cnt; 162 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 163 u8 reserved[15]; 164 }; 165 166 /* Get switch configuration (0x0200) */ 167 struct ice_aqc_get_sw_cfg { 168 /* Reserved for command and copy of request flags for response */ 169 __le16 flags; 170 /* First desc in case of command and next_elem in case of response 171 * In case of response, if it is not zero, means all the configuration 172 * was not returned and new command shall be sent with this value in 173 * the 'first desc' field 174 */ 175 __le16 element; 176 /* Reserved for command, only used for response */ 177 __le16 num_elems; 178 __le16 rsvd; 179 __le32 addr_high; 180 __le32 addr_low; 181 }; 182 183 /* Each entry in the response buffer is of the following type: */ 184 struct ice_aqc_get_sw_cfg_resp_elem { 185 /* VSI/Port Number */ 186 __le16 vsi_port_num; 187 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 188 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 189 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 190 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 191 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 192 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 193 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 194 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 195 196 /* SWID VSI/Port belongs to */ 197 __le16 swid; 198 199 /* Bit 14..0 : PF/VF number VSI belongs to 200 * Bit 15 : VF indication bit 201 */ 202 __le16 pf_vf_num; 203 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 204 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 205 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 206 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 207 }; 208 209 /* The response buffer is as follows. Note that the length of the 210 * elements array varies with the length of the command response. 211 */ 212 struct ice_aqc_get_sw_cfg_resp { 213 struct ice_aqc_get_sw_cfg_resp_elem elements[1]; 214 }; 215 216 /* These resource type defines are used for all switch resource 217 * commands where a resource type is required, such as: 218 * Get Resource Allocation command (indirect 0x0204) 219 * Allocate Resources command (indirect 0x0208) 220 * Free Resources command (indirect 0x0209) 221 * Get Allocated Resource Descriptors Command (indirect 0x020A) 222 */ 223 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 224 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 225 226 /* Allocate Resources command (indirect 0x0208) 227 * Free Resources command (indirect 0x0209) 228 */ 229 struct ice_aqc_alloc_free_res_cmd { 230 __le16 num_entries; /* Number of Resource entries */ 231 u8 reserved[6]; 232 __le32 addr_high; 233 __le32 addr_low; 234 }; 235 236 /* Resource descriptor */ 237 struct ice_aqc_res_elem { 238 union { 239 __le16 sw_resp; 240 __le16 flu_resp; 241 } e; 242 }; 243 244 /* Buffer for Allocate/Free Resources commands */ 245 struct ice_aqc_alloc_free_res_elem { 246 __le16 res_type; /* Types defined above cmd 0x0204 */ 247 #define ICE_AQC_RES_TYPE_SHARED_S 7 248 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 249 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 250 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 251 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 252 __le16 num_elems; 253 struct ice_aqc_res_elem elem[1]; 254 }; 255 256 /* Add VSI (indirect 0x0210) 257 * Update VSI (indirect 0x0211) 258 * Get VSI (indirect 0x0212) 259 * Free VSI (indirect 0x0213) 260 */ 261 struct ice_aqc_add_get_update_free_vsi { 262 __le16 vsi_num; 263 #define ICE_AQ_VSI_NUM_S 0 264 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 265 #define ICE_AQ_VSI_IS_VALID BIT(15) 266 __le16 cmd_flags; 267 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 268 u8 vf_id; 269 u8 reserved; 270 __le16 vsi_flags; 271 #define ICE_AQ_VSI_TYPE_S 0 272 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 273 #define ICE_AQ_VSI_TYPE_VF 0x0 274 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 275 #define ICE_AQ_VSI_TYPE_PF 0x2 276 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 277 __le32 addr_high; 278 __le32 addr_low; 279 }; 280 281 /* Response descriptor for: 282 * Add VSI (indirect 0x0210) 283 * Update VSI (indirect 0x0211) 284 * Free VSI (indirect 0x0213) 285 */ 286 struct ice_aqc_add_update_free_vsi_resp { 287 __le16 vsi_num; 288 __le16 ext_status; 289 __le16 vsi_used; 290 __le16 vsi_free; 291 __le32 addr_high; 292 __le32 addr_low; 293 }; 294 295 struct ice_aqc_vsi_props { 296 __le16 valid_sections; 297 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 298 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 299 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 300 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 301 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 302 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 303 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 304 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 305 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 306 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 307 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 308 /* switch section */ 309 u8 sw_id; 310 u8 sw_flags; 311 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 312 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 313 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 314 u8 sw_flags2; 315 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 316 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 317 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 318 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 319 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 320 u8 veb_stat_id; 321 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 322 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 323 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 324 /* security section */ 325 u8 sec_flags; 326 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 327 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 328 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 329 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 330 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 331 u8 sec_reserved; 332 /* VLAN section */ 333 __le16 pvid; /* VLANS include priority bits */ 334 u8 pvlan_reserved[2]; 335 u8 vlan_flags; 336 #define ICE_AQ_VSI_VLAN_MODE_S 0 337 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 338 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 339 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 340 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 341 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 342 #define ICE_AQ_VSI_VLAN_EMOD_S 3 343 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 344 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 345 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 346 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 347 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 348 u8 pvlan_reserved2[3]; 349 /* ingress egress up sections */ 350 __le32 ingress_table; /* bitmap, 3 bits per up */ 351 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 352 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 353 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 354 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 355 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 356 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 357 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 358 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 359 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 360 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 361 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 362 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 363 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 364 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 365 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 366 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 367 __le32 egress_table; /* same defines as for ingress table */ 368 /* outer tags section */ 369 __le16 outer_tag; 370 u8 outer_tag_flags; 371 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 372 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 373 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 374 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 375 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 376 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 377 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 378 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 379 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 380 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 381 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 382 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 383 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 384 u8 outer_tag_reserved; 385 /* queue mapping section */ 386 __le16 mapping_flags; 387 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 388 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 389 __le16 q_mapping[16]; 390 #define ICE_AQ_VSI_Q_S 0 391 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 392 __le16 tc_mapping[8]; 393 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 394 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 395 #define ICE_AQ_VSI_TC_Q_NUM_S 11 396 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 397 /* queueing option section */ 398 u8 q_opt_rss; 399 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 400 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 401 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 402 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 403 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 404 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 405 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 406 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 407 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 408 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 409 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 410 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 411 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 412 u8 q_opt_tc; 413 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 414 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 415 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 416 u8 q_opt_flags; 417 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 418 u8 q_opt_reserved[3]; 419 /* outer up section */ 420 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 421 /* section 10 */ 422 __le16 sect_10_reserved; 423 /* flow director section */ 424 __le16 fd_options; 425 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 426 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 427 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 428 __le16 max_fd_fltr_dedicated; 429 __le16 max_fd_fltr_shared; 430 __le16 fd_def_q; 431 #define ICE_AQ_VSI_FD_DEF_Q_S 0 432 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 433 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 434 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 435 __le16 fd_report_opt; 436 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 437 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 438 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 439 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 440 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 441 /* PASID section */ 442 __le32 pasid_id; 443 #define ICE_AQ_VSI_PASID_ID_S 0 444 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 445 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 446 u8 reserved[24]; 447 }; 448 449 #define ICE_MAX_NUM_RECIPES 64 450 451 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 452 */ 453 struct ice_aqc_sw_rules { 454 /* ops: add switch rules, referring the number of rules. 455 * ops: update switch rules, referring the number of filters 456 * ops: remove switch rules, referring the entry index. 457 * ops: get switch rules, referring to the number of filters. 458 */ 459 __le16 num_rules_fltr_entry_index; 460 u8 reserved[6]; 461 __le32 addr_high; 462 __le32 addr_low; 463 }; 464 465 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 466 * This structures describes the lookup rules and associated actions. "index" 467 * is returned as part of a response to a successful Add command, and can be 468 * used to identify the rule for Update/Get/Remove commands. 469 */ 470 struct ice_sw_rule_lkup_rx_tx { 471 __le16 recipe_id; 472 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 473 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 474 __le16 src; 475 __le32 act; 476 477 /* Bit 0:1 - Action type */ 478 #define ICE_SINGLE_ACT_TYPE_S 0x00 479 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 480 481 /* Bit 2 - Loop back enable 482 * Bit 3 - LAN enable 483 */ 484 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 485 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 486 487 /* Action type = 0 - Forward to VSI or VSI list */ 488 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 489 490 #define ICE_SINGLE_ACT_VSI_ID_S 4 491 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 492 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 493 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 494 /* This bit needs to be set if action is forward to VSI list */ 495 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 496 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 497 #define ICE_SINGLE_ACT_DROP BIT(18) 498 499 /* Action type = 1 - Forward to Queue of Queue group */ 500 #define ICE_SINGLE_ACT_TO_Q 0x1 501 #define ICE_SINGLE_ACT_Q_INDEX_S 4 502 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 503 #define ICE_SINGLE_ACT_Q_REGION_S 15 504 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 505 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 506 507 /* Action type = 2 - Prune */ 508 #define ICE_SINGLE_ACT_PRUNE 0x2 509 #define ICE_SINGLE_ACT_EGRESS BIT(15) 510 #define ICE_SINGLE_ACT_INGRESS BIT(16) 511 #define ICE_SINGLE_ACT_PRUNET BIT(17) 512 /* Bit 18 should be set to 0 for this action */ 513 514 /* Action type = 2 - Pointer */ 515 #define ICE_SINGLE_ACT_PTR 0x2 516 #define ICE_SINGLE_ACT_PTR_VAL_S 4 517 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 518 /* Bit 18 should be set to 1 */ 519 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 520 521 /* Action type = 3 - Other actions. Last two bits 522 * are other action identifier 523 */ 524 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 525 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 526 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 527 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 528 529 /* Bit 17:18 - Defines other actions */ 530 /* Other action = 0 - Mirror VSI */ 531 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 532 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 533 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 534 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 535 536 /* Other action = 3 - Set Stat count */ 537 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 538 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 539 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 540 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 541 542 __le16 index; /* The index of the rule in the lookup table */ 543 /* Length and values of the header to be matched per recipe or 544 * lookup-type 545 */ 546 __le16 hdr_len; 547 u8 hdr[1]; 548 } __packed; 549 550 /* Add/Update/Remove large action command/response entry 551 * "index" is returned as part of a response to a successful Add command, and 552 * can be used to identify the action for Update/Get/Remove commands. 553 */ 554 struct ice_sw_rule_lg_act { 555 __le16 index; /* Index in large action table */ 556 __le16 size; 557 __le32 act[1]; /* array of size for actions */ 558 /* Max number of large actions */ 559 #define ICE_MAX_LG_ACT 4 560 /* Bit 0:1 - Action type */ 561 #define ICE_LG_ACT_TYPE_S 0 562 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 563 564 /* Action type = 0 - Forward to VSI or VSI list */ 565 #define ICE_LG_ACT_VSI_FORWARDING 0 566 #define ICE_LG_ACT_VSI_ID_S 3 567 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 568 #define ICE_LG_ACT_VSI_LIST_ID_S 3 569 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 570 /* This bit needs to be set if action is forward to VSI list */ 571 #define ICE_LG_ACT_VSI_LIST BIT(13) 572 573 #define ICE_LG_ACT_VALID_BIT BIT(16) 574 575 /* Action type = 1 - Forward to Queue of Queue group */ 576 #define ICE_LG_ACT_TO_Q 0x1 577 #define ICE_LG_ACT_Q_INDEX_S 3 578 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 579 #define ICE_LG_ACT_Q_REGION_S 14 580 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 581 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 582 583 /* Action type = 2 - Prune */ 584 #define ICE_LG_ACT_PRUNE 0x2 585 #define ICE_LG_ACT_EGRESS BIT(14) 586 #define ICE_LG_ACT_INGRESS BIT(15) 587 #define ICE_LG_ACT_PRUNET BIT(16) 588 589 /* Action type = 3 - Mirror VSI */ 590 #define ICE_LG_OTHER_ACT_MIRROR 0x3 591 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 592 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 593 594 /* Action type = 5 - Generic Value */ 595 #define ICE_LG_ACT_GENERIC 0x5 596 #define ICE_LG_ACT_GENERIC_VALUE_S 3 597 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 598 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 599 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 600 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 601 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 602 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 603 604 /* Action = 7 - Set Stat count */ 605 #define ICE_LG_ACT_STAT_COUNT 0x7 606 #define ICE_LG_ACT_STAT_COUNT_S 3 607 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 608 }; 609 610 /* Add/Update/Remove VSI list command/response entry 611 * "index" is returned as part of a response to a successful Add command, and 612 * can be used to identify the VSI list for Update/Get/Remove commands. 613 */ 614 struct ice_sw_rule_vsi_list { 615 __le16 index; /* Index of VSI/Prune list */ 616 __le16 number_vsi; 617 __le16 vsi[1]; /* Array of number_vsi VSI numbers */ 618 }; 619 620 /* Query VSI list command/response entry */ 621 struct ice_sw_rule_vsi_list_query { 622 __le16 index; 623 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI); 624 } __packed; 625 626 /* Add switch rule response: 627 * Content of return buffer is same as the input buffer. The status field and 628 * LUT index are updated as part of the response 629 */ 630 struct ice_aqc_sw_rules_elem { 631 __le16 type; /* Switch rule type, one of T_... */ 632 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 633 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 634 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 635 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 636 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 637 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 638 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 639 __le16 status; 640 union { 641 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 642 struct ice_sw_rule_lg_act lg_act; 643 struct ice_sw_rule_vsi_list vsi_list; 644 struct ice_sw_rule_vsi_list_query vsi_list_query; 645 } __packed pdata; 646 }; 647 648 /* Get Default Topology (indirect 0x0400) */ 649 struct ice_aqc_get_topo { 650 u8 port_num; 651 u8 num_branches; 652 __le16 reserved1; 653 __le32 reserved2; 654 __le32 addr_high; 655 __le32 addr_low; 656 }; 657 658 /* Update TSE (indirect 0x0403) 659 * Get TSE (indirect 0x0404) 660 * Add TSE (indirect 0x0401) 661 * Delete TSE (indirect 0x040F) 662 * Move TSE (indirect 0x0408) 663 * Suspend Nodes (indirect 0x0409) 664 * Resume Nodes (indirect 0x040A) 665 */ 666 struct ice_aqc_sched_elem_cmd { 667 __le16 num_elem_req; /* Used by commands */ 668 __le16 num_elem_resp; /* Used by responses */ 669 __le32 reserved; 670 __le32 addr_high; 671 __le32 addr_low; 672 }; 673 674 /* This is the buffer for: 675 * Suspend Nodes (indirect 0x0409) 676 * Resume Nodes (indirect 0x040A) 677 */ 678 struct ice_aqc_suspend_resume_elem { 679 __le32 teid[1]; 680 }; 681 682 struct ice_aqc_elem_info_bw { 683 __le16 bw_profile_idx; 684 __le16 bw_alloc; 685 }; 686 687 struct ice_aqc_txsched_elem { 688 u8 elem_type; /* Special field, reserved for some aq calls */ 689 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 690 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 691 #define ICE_AQC_ELEM_TYPE_TC 0x2 692 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 693 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 694 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 695 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 696 u8 valid_sections; 697 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 698 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 699 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 700 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 701 u8 generic; 702 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 703 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 704 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 705 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 706 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 707 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 708 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 709 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 710 u8 flags; /* Special field, reserved for some aq calls */ 711 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 712 struct ice_aqc_elem_info_bw cir_bw; 713 struct ice_aqc_elem_info_bw eir_bw; 714 __le16 srl_id; 715 __le16 reserved2; 716 }; 717 718 struct ice_aqc_txsched_elem_data { 719 __le32 parent_teid; 720 __le32 node_teid; 721 struct ice_aqc_txsched_elem data; 722 }; 723 724 struct ice_aqc_txsched_topo_grp_info_hdr { 725 __le32 parent_teid; 726 __le16 num_elems; 727 __le16 reserved2; 728 }; 729 730 struct ice_aqc_add_elem { 731 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 732 struct ice_aqc_txsched_elem_data generic[1]; 733 }; 734 735 struct ice_aqc_get_elem { 736 struct ice_aqc_txsched_elem_data generic[1]; 737 }; 738 739 struct ice_aqc_get_topo_elem { 740 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 741 struct ice_aqc_txsched_elem_data 742 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 743 }; 744 745 struct ice_aqc_delete_elem { 746 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 747 __le32 teid[1]; 748 }; 749 750 /* Query Scheduler Resource Allocation (indirect 0x0412) 751 * This indirect command retrieves the scheduler resources allocated by 752 * EMP Firmware to the given PF. 753 */ 754 struct ice_aqc_query_txsched_res { 755 u8 reserved[8]; 756 __le32 addr_high; 757 __le32 addr_low; 758 }; 759 760 struct ice_aqc_generic_sched_props { 761 __le16 phys_levels; 762 __le16 logical_levels; 763 u8 flattening_bitmap; 764 u8 max_device_cgds; 765 u8 max_pf_cgds; 766 u8 rsvd0; 767 __le16 rdma_qsets; 768 u8 rsvd1[22]; 769 }; 770 771 struct ice_aqc_layer_props { 772 u8 logical_layer; 773 u8 chunk_size; 774 __le16 max_device_nodes; 775 __le16 max_pf_nodes; 776 u8 rsvd0[4]; 777 __le16 max_sibl_grp_sz; 778 __le16 max_cir_rl_profiles; 779 __le16 max_eir_rl_profiles; 780 __le16 max_srl_profiles; 781 u8 rsvd1[14]; 782 }; 783 784 struct ice_aqc_query_txsched_res_resp { 785 struct ice_aqc_generic_sched_props sched_props; 786 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 787 }; 788 789 /* Get PHY capabilities (indirect 0x0600) */ 790 struct ice_aqc_get_phy_caps { 791 u8 lport_num; 792 u8 reserved; 793 __le16 param0; 794 /* 18.0 - Report qualified modules */ 795 #define ICE_AQC_GET_PHY_RQM BIT(0) 796 /* 18.1 - 18.2 : Report mode 797 * 00b - Report NVM capabilities 798 * 01b - Report topology capabilities 799 * 10b - Report SW configured 800 */ 801 #define ICE_AQC_REPORT_MODE_S 1 802 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 803 #define ICE_AQC_REPORT_NVM_CAP 0 804 #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 805 #define ICE_AQC_REPORT_SW_CFG BIT(2) 806 __le32 reserved1; 807 __le32 addr_high; 808 __le32 addr_low; 809 }; 810 811 /* This is #define of PHY type (Extended): 812 * The first set of defines is for phy_type_low. 813 */ 814 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 815 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 816 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 817 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 818 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 819 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 820 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 821 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 822 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 823 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 824 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 825 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 826 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 827 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 828 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 829 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 830 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 831 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 832 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 833 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 834 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 835 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 836 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 837 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 838 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 839 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 840 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 841 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 842 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 843 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 844 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 845 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 846 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 847 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 848 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 849 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 850 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 851 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 852 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 853 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 854 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 855 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 856 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 857 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 858 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 859 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 860 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 861 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 862 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 863 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 864 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 865 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 866 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 867 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 868 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 869 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 870 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 871 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 872 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 873 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 874 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 875 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 876 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 877 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 878 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 879 /* The second set of defines is for phy_type_high. */ 880 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 881 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 882 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 883 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 884 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 885 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19 886 887 struct ice_aqc_get_phy_caps_data { 888 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 889 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 890 u8 caps; 891 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 892 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 893 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 894 #define ICE_AQC_PHY_EN_LINK BIT(3) 895 #define ICE_AQC_PHY_AN_MODE BIT(4) 896 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 897 u8 low_power_ctrl; 898 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 899 __le16 eee_cap; 900 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 901 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 902 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 903 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 904 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 905 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 906 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 907 __le16 eeer_value; 908 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 909 u8 link_fec_options; 910 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 911 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 912 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 913 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 914 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 915 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 916 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 917 u8 extended_compliance_code; 918 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 919 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 920 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 921 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 922 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 923 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 924 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 925 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 926 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 927 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 928 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 929 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 930 u8 qualified_module_count; 931 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 932 struct { 933 u8 v_oui[3]; 934 u8 rsvd1; 935 u8 v_part[16]; 936 __le32 v_rev; 937 __le64 rsvd8; 938 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 939 }; 940 941 /* Set PHY capabilities (direct 0x0601) 942 * NOTE: This command must be followed by setup link and restart auto-neg 943 */ 944 struct ice_aqc_set_phy_cfg { 945 u8 lport_num; 946 u8 reserved[7]; 947 __le32 addr_high; 948 __le32 addr_low; 949 }; 950 951 /* Set PHY config command data structure */ 952 struct ice_aqc_set_phy_cfg_data { 953 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 954 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 955 u8 caps; 956 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 957 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 958 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 959 #define ICE_AQ_PHY_ENA_LINK BIT(3) 960 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 961 #define ICE_AQ_PHY_ENA_LESM BIT(6) 962 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 963 u8 low_power_ctrl; 964 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 965 __le16 eeer_value; 966 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 967 u8 rsvd1; 968 }; 969 970 /* Restart AN command data structure (direct 0x0605) 971 * Also used for response, with only the lport_num field present. 972 */ 973 struct ice_aqc_restart_an { 974 u8 lport_num; 975 u8 reserved; 976 u8 cmd_flags; 977 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 978 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 979 u8 reserved2[13]; 980 }; 981 982 /* Get link status (indirect 0x0607), also used for Link Status Event */ 983 struct ice_aqc_get_link_status { 984 u8 lport_num; 985 u8 reserved; 986 __le16 cmd_flags; 987 #define ICE_AQ_LSE_M 0x3 988 #define ICE_AQ_LSE_NOP 0x0 989 #define ICE_AQ_LSE_DIS 0x2 990 #define ICE_AQ_LSE_ENA 0x3 991 /* only response uses this flag */ 992 #define ICE_AQ_LSE_IS_ENABLED 0x1 993 __le32 reserved2; 994 __le32 addr_high; 995 __le32 addr_low; 996 }; 997 998 /* Get link status response data structure, also used for Link Status Event */ 999 struct ice_aqc_get_link_status_data { 1000 u8 topo_media_conflict; 1001 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1002 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1003 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1004 u8 reserved1; 1005 u8 link_info; 1006 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1007 #define ICE_AQ_LINK_FAULT BIT(1) 1008 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1009 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1010 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1011 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1012 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1013 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1014 u8 an_info; 1015 #define ICE_AQ_AN_COMPLETED BIT(0) 1016 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1017 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1018 #define ICE_AQ_FEC_EN BIT(3) 1019 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1020 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1021 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1022 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1023 u8 ext_info; 1024 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1025 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1026 /* Port TX Suspended */ 1027 #define ICE_AQ_LINK_TX_S 2 1028 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1029 #define ICE_AQ_LINK_TX_ACTIVE 0 1030 #define ICE_AQ_LINK_TX_DRAINED 1 1031 #define ICE_AQ_LINK_TX_FLUSHED 3 1032 u8 reserved2; 1033 __le16 max_frame_size; 1034 u8 cfg; 1035 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1036 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1037 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1038 /* Pacing Config */ 1039 #define ICE_AQ_CFG_PACING_S 3 1040 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1041 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1042 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1043 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1044 /* External Device Power Ability */ 1045 u8 power_desc; 1046 #define ICE_AQ_PWR_CLASS_M 0x3 1047 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1048 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1049 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1050 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1051 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1052 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1053 __le16 link_speed; 1054 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1055 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1056 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1057 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1058 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1059 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1060 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1061 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1062 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1063 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1064 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1065 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1066 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1067 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1068 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1069 }; 1070 1071 /* Set event mask command (direct 0x0613) */ 1072 struct ice_aqc_set_event_mask { 1073 u8 lport_num; 1074 u8 reserved[7]; 1075 __le16 event_mask; 1076 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1077 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1078 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1079 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1080 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1081 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1082 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1083 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1084 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1085 u8 reserved1[6]; 1086 }; 1087 1088 /* Set Port Identification LED (direct, 0x06E9) */ 1089 struct ice_aqc_set_port_id_led { 1090 u8 lport_num; 1091 u8 lport_num_valid; 1092 u8 ident_mode; 1093 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1094 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1095 u8 rsvd[13]; 1096 }; 1097 1098 /* NVM Read command (indirect 0x0701) 1099 * NVM Erase commands (direct 0x0702) 1100 * NVM Update commands (indirect 0x0703) 1101 */ 1102 struct ice_aqc_nvm { 1103 __le16 offset_low; 1104 u8 offset_high; 1105 u8 cmd_flags; 1106 #define ICE_AQC_NVM_LAST_CMD BIT(0) 1107 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1108 #define ICE_AQC_NVM_PRESERVATION_S 1 1109 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 1110 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1111 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1112 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1113 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1114 __le16 module_typeid; 1115 __le16 length; 1116 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1117 __le32 addr_high; 1118 __le32 addr_low; 1119 }; 1120 1121 /** 1122 * Send to PF command (indirect 0x0801) id is only used by PF 1123 * 1124 * Send to VF command (indirect 0x0802) id is only used by PF 1125 * 1126 */ 1127 struct ice_aqc_pf_vf_msg { 1128 __le32 id; 1129 u32 reserved; 1130 __le32 addr_high; 1131 __le32 addr_low; 1132 }; 1133 1134 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1135 struct ice_aqc_get_set_rss_key { 1136 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1137 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1138 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1139 __le16 vsi_id; 1140 u8 reserved[6]; 1141 __le32 addr_high; 1142 __le32 addr_low; 1143 }; 1144 1145 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1146 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1147 1148 struct ice_aqc_get_set_rss_keys { 1149 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1150 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1151 }; 1152 1153 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1154 struct ice_aqc_get_set_rss_lut { 1155 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1156 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1157 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1158 __le16 vsi_id; 1159 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1160 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1161 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1162 1163 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1164 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1165 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1166 1167 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1168 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1169 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1170 1171 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1172 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1173 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1174 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1175 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1176 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1177 1178 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1179 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1180 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1181 1182 __le16 flags; 1183 __le32 reserved; 1184 __le32 addr_high; 1185 __le32 addr_low; 1186 }; 1187 1188 /* Add TX LAN Queues (indirect 0x0C30) */ 1189 struct ice_aqc_add_txqs { 1190 u8 num_qgrps; 1191 u8 reserved[3]; 1192 __le32 reserved1; 1193 __le32 addr_high; 1194 __le32 addr_low; 1195 }; 1196 1197 /* This is the descriptor of each queue entry for the Add TX LAN Queues 1198 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1199 */ 1200 struct ice_aqc_add_txqs_perq { 1201 __le16 txq_id; 1202 u8 rsvd[2]; 1203 __le32 q_teid; 1204 u8 txq_ctx[22]; 1205 u8 rsvd2[2]; 1206 struct ice_aqc_txsched_elem info; 1207 }; 1208 1209 /* The format of the command buffer for Add TX LAN Queues (0x0C30) 1210 * is an array of the following structs. Please note that the length of 1211 * each struct ice_aqc_add_tx_qgrp is variable due 1212 * to the variable number of queues in each group! 1213 */ 1214 struct ice_aqc_add_tx_qgrp { 1215 __le32 parent_teid; 1216 u8 num_txqs; 1217 u8 rsvd[3]; 1218 struct ice_aqc_add_txqs_perq txqs[1]; 1219 }; 1220 1221 /* Disable TX LAN Queues (indirect 0x0C31) */ 1222 struct ice_aqc_dis_txqs { 1223 u8 cmd_type; 1224 #define ICE_AQC_Q_DIS_CMD_S 0 1225 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1226 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1227 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1228 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1229 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1230 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1231 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1232 u8 num_entries; 1233 __le16 vmvf_and_timeout; 1234 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1235 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1236 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1237 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1238 __le32 blocked_cgds; 1239 __le32 addr_high; 1240 __le32 addr_low; 1241 }; 1242 1243 /* The buffer for Disable TX LAN Queues (indirect 0x0C31) 1244 * contains the following structures, arrayed one after the 1245 * other. 1246 * Note: Since the q_id is 16 bits wide, if the 1247 * number of queues is even, then 2 bytes of alignment MUST be 1248 * added before the start of the next group, to allow correct 1249 * alignment of the parent_teid field. 1250 */ 1251 struct ice_aqc_dis_txq_item { 1252 __le32 parent_teid; 1253 u8 num_qs; 1254 u8 rsvd; 1255 /* The length of the q_id array varies according to num_qs */ 1256 __le16 q_id[1]; 1257 /* This only applies from F8 onward */ 1258 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1259 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1260 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1261 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1262 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1263 }; 1264 1265 struct ice_aqc_dis_txq { 1266 struct ice_aqc_dis_txq_item qgrps[1]; 1267 }; 1268 1269 /* Configure Firmware Logging Command (indirect 0xFF09) 1270 * Logging Information Read Response (indirect 0xFF10) 1271 * Note: The 0xFF10 command has no input parameters. 1272 */ 1273 struct ice_aqc_fw_logging { 1274 u8 log_ctrl; 1275 #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 1276 #define ICE_AQC_FW_LOG_UART_EN BIT(1) 1277 u8 rsvd0; 1278 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 1279 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 1280 #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 1281 u8 rsvd1[5]; 1282 __le32 addr_high; 1283 __le32 addr_low; 1284 }; 1285 1286 enum ice_aqc_fw_logging_mod { 1287 ICE_AQC_FW_LOG_ID_GENERAL = 0, 1288 ICE_AQC_FW_LOG_ID_CTRL, 1289 ICE_AQC_FW_LOG_ID_LINK, 1290 ICE_AQC_FW_LOG_ID_LINK_TOPO, 1291 ICE_AQC_FW_LOG_ID_DNL, 1292 ICE_AQC_FW_LOG_ID_I2C, 1293 ICE_AQC_FW_LOG_ID_SDP, 1294 ICE_AQC_FW_LOG_ID_MDIO, 1295 ICE_AQC_FW_LOG_ID_ADMINQ, 1296 ICE_AQC_FW_LOG_ID_HDMA, 1297 ICE_AQC_FW_LOG_ID_LLDP, 1298 ICE_AQC_FW_LOG_ID_DCBX, 1299 ICE_AQC_FW_LOG_ID_DCB, 1300 ICE_AQC_FW_LOG_ID_NETPROXY, 1301 ICE_AQC_FW_LOG_ID_NVM, 1302 ICE_AQC_FW_LOG_ID_AUTH, 1303 ICE_AQC_FW_LOG_ID_VPD, 1304 ICE_AQC_FW_LOG_ID_IOSF, 1305 ICE_AQC_FW_LOG_ID_PARSER, 1306 ICE_AQC_FW_LOG_ID_SW, 1307 ICE_AQC_FW_LOG_ID_SCHEDULER, 1308 ICE_AQC_FW_LOG_ID_TXQ, 1309 ICE_AQC_FW_LOG_ID_RSVD, 1310 ICE_AQC_FW_LOG_ID_POST, 1311 ICE_AQC_FW_LOG_ID_WATCHDOG, 1312 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 1313 ICE_AQC_FW_LOG_ID_MNG, 1314 ICE_AQC_FW_LOG_ID_MAX, 1315 }; 1316 1317 /* This is the buffer for both of the logging commands. 1318 * The entry array size depends on the datalen parameter in the descriptor. 1319 * There will be a total of datalen / 2 entries. 1320 */ 1321 struct ice_aqc_fw_logging_data { 1322 __le16 entry[1]; 1323 #define ICE_AQC_FW_LOG_ID_S 0 1324 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 1325 1326 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 1327 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 1328 1329 #define ICE_AQC_FW_LOG_EN_S 12 1330 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 1331 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 1332 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 1333 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 1334 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 1335 }; 1336 1337 /* Get/Clear FW Log (indirect 0xFF11) */ 1338 struct ice_aqc_get_clear_fw_log { 1339 u8 flags; 1340 #define ICE_AQC_FW_LOG_CLEAR BIT(0) 1341 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 1342 u8 rsvd1[7]; 1343 __le32 addr_high; 1344 __le32 addr_low; 1345 }; 1346 1347 /** 1348 * struct ice_aq_desc - Admin Queue (AQ) descriptor 1349 * @flags: ICE_AQ_FLAG_* flags 1350 * @opcode: AQ command opcode 1351 * @datalen: length in bytes of indirect/external data buffer 1352 * @retval: return value from firmware 1353 * @cookie_h: opaque data high-half 1354 * @cookie_l: opaque data low-half 1355 * @params: command-specific parameters 1356 * 1357 * Descriptor format for commands the driver posts on the Admin Transmit Queue 1358 * (ATQ). The firmware writes back onto the command descriptor and returns 1359 * the result of the command. Asynchronous events that are not an immediate 1360 * result of the command are written to the Admin Receive Queue (ARQ) using 1361 * the same descriptor format. Descriptors are in little-endian notation with 1362 * 32-bit words. 1363 */ 1364 struct ice_aq_desc { 1365 __le16 flags; 1366 __le16 opcode; 1367 __le16 datalen; 1368 __le16 retval; 1369 __le32 cookie_high; 1370 __le32 cookie_low; 1371 union { 1372 u8 raw[16]; 1373 struct ice_aqc_generic generic; 1374 struct ice_aqc_get_ver get_ver; 1375 struct ice_aqc_q_shutdown q_shutdown; 1376 struct ice_aqc_req_res res_owner; 1377 struct ice_aqc_manage_mac_read mac_read; 1378 struct ice_aqc_manage_mac_write mac_write; 1379 struct ice_aqc_clear_pxe clear_pxe; 1380 struct ice_aqc_list_caps get_cap; 1381 struct ice_aqc_get_phy_caps get_phy; 1382 struct ice_aqc_set_phy_cfg set_phy; 1383 struct ice_aqc_restart_an restart_an; 1384 struct ice_aqc_set_port_id_led set_port_id_led; 1385 struct ice_aqc_get_sw_cfg get_sw_conf; 1386 struct ice_aqc_sw_rules sw_rules; 1387 struct ice_aqc_get_topo get_topo; 1388 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 1389 struct ice_aqc_query_txsched_res query_sched_res; 1390 struct ice_aqc_nvm nvm; 1391 struct ice_aqc_pf_vf_msg virt; 1392 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 1393 struct ice_aqc_get_set_rss_key get_set_rss_key; 1394 struct ice_aqc_add_txqs add_txqs; 1395 struct ice_aqc_dis_txqs dis_txqs; 1396 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 1397 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 1398 struct ice_aqc_fw_logging fw_logging; 1399 struct ice_aqc_get_clear_fw_log get_clear_fw_log; 1400 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 1401 struct ice_aqc_set_event_mask set_event_mask; 1402 struct ice_aqc_get_link_status get_link_status; 1403 } params; 1404 }; 1405 1406 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 1407 #define ICE_AQ_LG_BUF 512 1408 1409 #define ICE_AQ_FLAG_ERR_S 2 1410 #define ICE_AQ_FLAG_LB_S 9 1411 #define ICE_AQ_FLAG_RD_S 10 1412 #define ICE_AQ_FLAG_BUF_S 12 1413 #define ICE_AQ_FLAG_SI_S 13 1414 1415 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 1416 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 1417 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 1418 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 1419 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 1420 1421 /* error codes */ 1422 enum ice_aq_err { 1423 ICE_AQ_RC_OK = 0, /* Success */ 1424 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 1425 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1426 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 1427 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 1428 }; 1429 1430 /* Admin Queue command opcodes */ 1431 enum ice_adminq_opc { 1432 /* AQ commands */ 1433 ice_aqc_opc_get_ver = 0x0001, 1434 ice_aqc_opc_q_shutdown = 0x0003, 1435 1436 /* resource ownership */ 1437 ice_aqc_opc_req_res = 0x0008, 1438 ice_aqc_opc_release_res = 0x0009, 1439 1440 /* device/function capabilities */ 1441 ice_aqc_opc_list_func_caps = 0x000A, 1442 ice_aqc_opc_list_dev_caps = 0x000B, 1443 1444 /* manage MAC address */ 1445 ice_aqc_opc_manage_mac_read = 0x0107, 1446 ice_aqc_opc_manage_mac_write = 0x0108, 1447 1448 /* PXE */ 1449 ice_aqc_opc_clear_pxe_mode = 0x0110, 1450 1451 /* internal switch commands */ 1452 ice_aqc_opc_get_sw_cfg = 0x0200, 1453 1454 /* Alloc/Free/Get Resources */ 1455 ice_aqc_opc_alloc_res = 0x0208, 1456 ice_aqc_opc_free_res = 0x0209, 1457 1458 /* VSI commands */ 1459 ice_aqc_opc_add_vsi = 0x0210, 1460 ice_aqc_opc_update_vsi = 0x0211, 1461 ice_aqc_opc_free_vsi = 0x0213, 1462 1463 /* switch rules population commands */ 1464 ice_aqc_opc_add_sw_rules = 0x02A0, 1465 ice_aqc_opc_update_sw_rules = 0x02A1, 1466 ice_aqc_opc_remove_sw_rules = 0x02A2, 1467 1468 ice_aqc_opc_clear_pf_cfg = 0x02A4, 1469 1470 /* transmit scheduler commands */ 1471 ice_aqc_opc_get_dflt_topo = 0x0400, 1472 ice_aqc_opc_add_sched_elems = 0x0401, 1473 ice_aqc_opc_get_sched_elems = 0x0404, 1474 ice_aqc_opc_suspend_sched_elems = 0x0409, 1475 ice_aqc_opc_resume_sched_elems = 0x040A, 1476 ice_aqc_opc_delete_sched_elems = 0x040F, 1477 ice_aqc_opc_query_sched_res = 0x0412, 1478 1479 /* PHY commands */ 1480 ice_aqc_opc_get_phy_caps = 0x0600, 1481 ice_aqc_opc_set_phy_cfg = 0x0601, 1482 ice_aqc_opc_restart_an = 0x0605, 1483 ice_aqc_opc_get_link_status = 0x0607, 1484 ice_aqc_opc_set_event_mask = 0x0613, 1485 ice_aqc_opc_set_port_id_led = 0x06E9, 1486 1487 /* NVM commands */ 1488 ice_aqc_opc_nvm_read = 0x0701, 1489 1490 /* PF/VF mailbox commands */ 1491 ice_mbx_opc_send_msg_to_pf = 0x0801, 1492 ice_mbx_opc_send_msg_to_vf = 0x0802, 1493 1494 /* RSS commands */ 1495 ice_aqc_opc_set_rss_key = 0x0B02, 1496 ice_aqc_opc_set_rss_lut = 0x0B03, 1497 ice_aqc_opc_get_rss_key = 0x0B04, 1498 ice_aqc_opc_get_rss_lut = 0x0B05, 1499 1500 /* TX queue handling commands/events */ 1501 ice_aqc_opc_add_txqs = 0x0C30, 1502 ice_aqc_opc_dis_txqs = 0x0C31, 1503 1504 /* debug commands */ 1505 ice_aqc_opc_fw_logging = 0xFF09, 1506 }; 1507 1508 #endif /* _ICE_ADMINQ_CMD_H_ */ 1509