17ec59eeaSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 27ec59eeaSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 37ec59eeaSAnirudh Venkataramanan 47ec59eeaSAnirudh Venkataramanan #ifndef _ICE_ADMINQ_CMD_H_ 57ec59eeaSAnirudh Venkataramanan #define _ICE_ADMINQ_CMD_H_ 67ec59eeaSAnirudh Venkataramanan 77ec59eeaSAnirudh Venkataramanan /* This header file defines the Admin Queue commands, error codes and 87ec59eeaSAnirudh Venkataramanan * descriptor format. It is shared between Firmware and Software. 97ec59eeaSAnirudh Venkataramanan */ 107ec59eeaSAnirudh Venkataramanan 119daf8208SAnirudh Venkataramanan #define ICE_MAX_VSI 768 129c20346bSAnirudh Venkataramanan #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 133a858ba3SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 149c20346bSAnirudh Venkataramanan 157ec59eeaSAnirudh Venkataramanan struct ice_aqc_generic { 167ec59eeaSAnirudh Venkataramanan __le32 param0; 177ec59eeaSAnirudh Venkataramanan __le32 param1; 187ec59eeaSAnirudh Venkataramanan __le32 addr_high; 197ec59eeaSAnirudh Venkataramanan __le32 addr_low; 207ec59eeaSAnirudh Venkataramanan }; 217ec59eeaSAnirudh Venkataramanan 227ec59eeaSAnirudh Venkataramanan /* Get version (direct 0x0001) */ 237ec59eeaSAnirudh Venkataramanan struct ice_aqc_get_ver { 247ec59eeaSAnirudh Venkataramanan __le32 rom_ver; 257ec59eeaSAnirudh Venkataramanan __le32 fw_build; 267ec59eeaSAnirudh Venkataramanan u8 fw_branch; 277ec59eeaSAnirudh Venkataramanan u8 fw_major; 287ec59eeaSAnirudh Venkataramanan u8 fw_minor; 297ec59eeaSAnirudh Venkataramanan u8 fw_patch; 307ec59eeaSAnirudh Venkataramanan u8 api_branch; 317ec59eeaSAnirudh Venkataramanan u8 api_major; 327ec59eeaSAnirudh Venkataramanan u8 api_minor; 337ec59eeaSAnirudh Venkataramanan u8 api_patch; 347ec59eeaSAnirudh Venkataramanan }; 357ec59eeaSAnirudh Venkataramanan 36e3710a01SPaul M Stillwell Jr /* Send driver version (indirect 0x0002) */ 37e3710a01SPaul M Stillwell Jr struct ice_aqc_driver_ver { 38e3710a01SPaul M Stillwell Jr u8 major_ver; 39e3710a01SPaul M Stillwell Jr u8 minor_ver; 40e3710a01SPaul M Stillwell Jr u8 build_ver; 41e3710a01SPaul M Stillwell Jr u8 subbuild_ver; 42e3710a01SPaul M Stillwell Jr u8 reserved[4]; 43e3710a01SPaul M Stillwell Jr __le32 addr_high; 44e3710a01SPaul M Stillwell Jr __le32 addr_low; 45e3710a01SPaul M Stillwell Jr }; 46e3710a01SPaul M Stillwell Jr 477ec59eeaSAnirudh Venkataramanan /* Queue Shutdown (direct 0x0003) */ 487ec59eeaSAnirudh Venkataramanan struct ice_aqc_q_shutdown { 497404e84aSBruce Allan u8 driver_unloading; 5049c6e41bSAnirudh Venkataramanan #define ICE_AQC_DRIVER_UNLOADING BIT(0) 517404e84aSBruce Allan u8 reserved[15]; 527ec59eeaSAnirudh Venkataramanan }; 537ec59eeaSAnirudh Venkataramanan 54f31e4b6fSAnirudh Venkataramanan /* Request resource ownership (direct 0x0008) 55f31e4b6fSAnirudh Venkataramanan * Release resource ownership (direct 0x0009) 56f31e4b6fSAnirudh Venkataramanan */ 57f31e4b6fSAnirudh Venkataramanan struct ice_aqc_req_res { 58f31e4b6fSAnirudh Venkataramanan __le16 res_id; 59f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_NVM 1 60f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_SDP 2 61f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_CHNG_LOCK 3 62f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_GLBL_LOCK 4 63f31e4b6fSAnirudh Venkataramanan __le16 access_type; 64f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ACCESS_READ 1 65f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ACCESS_WRITE 2 66f31e4b6fSAnirudh Venkataramanan 67f31e4b6fSAnirudh Venkataramanan /* Upon successful completion, FW writes this value and driver is 68f31e4b6fSAnirudh Venkataramanan * expected to release resource before timeout. This value is provided 69f31e4b6fSAnirudh Venkataramanan * in milliseconds. 70f31e4b6fSAnirudh Venkataramanan */ 71f31e4b6fSAnirudh Venkataramanan __le32 timeout; 72f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 73f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 74f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 75f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 76f9867df6SAnirudh Venkataramanan /* For SDP: pin ID of the SDP */ 77f31e4b6fSAnirudh Venkataramanan __le32 res_number; 78f31e4b6fSAnirudh Venkataramanan /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 79f31e4b6fSAnirudh Venkataramanan __le16 status; 80f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_SUCCESS 0 81f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_IN_PROG 1 82f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_DONE 2 83f31e4b6fSAnirudh Venkataramanan u8 reserved[2]; 84f31e4b6fSAnirudh Venkataramanan }; 85f31e4b6fSAnirudh Venkataramanan 869c20346bSAnirudh Venkataramanan /* Get function capabilities (indirect 0x000A) 879c20346bSAnirudh Venkataramanan * Get device capabilities (indirect 0x000B) 889c20346bSAnirudh Venkataramanan */ 899c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps { 909c20346bSAnirudh Venkataramanan u8 cmd_flags; 919c20346bSAnirudh Venkataramanan u8 pf_index; 929c20346bSAnirudh Venkataramanan u8 reserved[2]; 939c20346bSAnirudh Venkataramanan __le32 count; 949c20346bSAnirudh Venkataramanan __le32 addr_high; 959c20346bSAnirudh Venkataramanan __le32 addr_low; 969c20346bSAnirudh Venkataramanan }; 979c20346bSAnirudh Venkataramanan 989c20346bSAnirudh Venkataramanan /* Device/Function buffer entry, repeated per reported capability */ 999c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps_elem { 1009c20346bSAnirudh Venkataramanan __le16 cap; 101995c90f2SAnirudh Venkataramanan #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 10275d2b253SAnirudh Venkataramanan #define ICE_AQC_CAPS_SRIOV 0x0012 10375d2b253SAnirudh Venkataramanan #define ICE_AQC_CAPS_VF 0x0013 1049c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_VSI 0x0017 105a257f188SUsha Ketineni #define ICE_AQC_CAPS_DCB 0x0018 1069c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_RSS 0x0040 1079c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_RXQS 0x0041 1089c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_TXQS 0x0042 1099c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_MSIX 0x0043 110148beb61SHenry Tieman #define ICE_AQC_CAPS_FD 0x0045 1119c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_MAX_MTU 0x0047 1129c20346bSAnirudh Venkataramanan 1139c20346bSAnirudh Venkataramanan u8 major_ver; 1149c20346bSAnirudh Venkataramanan u8 minor_ver; 1159c20346bSAnirudh Venkataramanan /* Number of resources described by this capability */ 1169c20346bSAnirudh Venkataramanan __le32 number; 1179c20346bSAnirudh Venkataramanan /* Only meaningful for some types of resources */ 1189c20346bSAnirudh Venkataramanan __le32 logical_id; 1199c20346bSAnirudh Venkataramanan /* Only meaningful for some types of resources */ 1209c20346bSAnirudh Venkataramanan __le32 phys_id; 1219c20346bSAnirudh Venkataramanan __le64 rsvd1; 1229c20346bSAnirudh Venkataramanan __le64 rsvd2; 1239c20346bSAnirudh Venkataramanan }; 1249c20346bSAnirudh Venkataramanan 125dc49c772SAnirudh Venkataramanan /* Manage MAC address, read command - indirect (0x0107) 126dc49c772SAnirudh Venkataramanan * This struct is also used for the response 127dc49c772SAnirudh Venkataramanan */ 128dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read { 129dc49c772SAnirudh Venkataramanan __le16 flags; /* Zeroed by device driver */ 130dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 131dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 132dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 133dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 134dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_READ_S 4 135dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 13662f4dafcSAnirudh Venkataramanan u8 rsvd[2]; 137dc49c772SAnirudh Venkataramanan u8 num_addr; /* Used in response */ 13862f4dafcSAnirudh Venkataramanan u8 rsvd1[3]; 139dc49c772SAnirudh Venkataramanan __le32 addr_high; 140dc49c772SAnirudh Venkataramanan __le32 addr_low; 141dc49c772SAnirudh Venkataramanan }; 142dc49c772SAnirudh Venkataramanan 143dc49c772SAnirudh Venkataramanan /* Response buffer format for manage MAC read command */ 144dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read_resp { 145dc49c772SAnirudh Venkataramanan u8 lport_num; 146dc49c772SAnirudh Venkataramanan u8 addr_type; 147dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 148dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 149dc49c772SAnirudh Venkataramanan u8 mac_addr[ETH_ALEN]; 150dc49c772SAnirudh Venkataramanan }; 151dc49c772SAnirudh Venkataramanan 152e94d4478SAnirudh Venkataramanan /* Manage MAC address, write command - direct (0x0108) */ 153e94d4478SAnirudh Venkataramanan struct ice_aqc_manage_mac_write { 15462f4dafcSAnirudh Venkataramanan u8 rsvd; 155e94d4478SAnirudh Venkataramanan u8 flags; 156e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 157e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 158e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WR_S 6 1595df42c82SJesse Brandeburg #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S) 160e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 1615df42c82SJesse Brandeburg #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 1625df42c82SJesse Brandeburg /* byte stream in network order */ 1635df42c82SJesse Brandeburg u8 mac_addr[ETH_ALEN]; 164e94d4478SAnirudh Venkataramanan __le32 addr_high; 165e94d4478SAnirudh Venkataramanan __le32 addr_low; 166e94d4478SAnirudh Venkataramanan }; 167e94d4478SAnirudh Venkataramanan 168f31e4b6fSAnirudh Venkataramanan /* Clear PXE Command and response (direct 0x0110) */ 169f31e4b6fSAnirudh Venkataramanan struct ice_aqc_clear_pxe { 170f31e4b6fSAnirudh Venkataramanan u8 rx_cnt; 171f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 172f31e4b6fSAnirudh Venkataramanan u8 reserved[15]; 173f31e4b6fSAnirudh Venkataramanan }; 174f31e4b6fSAnirudh Venkataramanan 1759c20346bSAnirudh Venkataramanan /* Get switch configuration (0x0200) */ 1769c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg { 1779c20346bSAnirudh Venkataramanan /* Reserved for command and copy of request flags for response */ 1789c20346bSAnirudh Venkataramanan __le16 flags; 1799c20346bSAnirudh Venkataramanan /* First desc in case of command and next_elem in case of response 1809c20346bSAnirudh Venkataramanan * In case of response, if it is not zero, means all the configuration 1819c20346bSAnirudh Venkataramanan * was not returned and new command shall be sent with this value in 1829c20346bSAnirudh Venkataramanan * the 'first desc' field 1839c20346bSAnirudh Venkataramanan */ 1849c20346bSAnirudh Venkataramanan __le16 element; 1859c20346bSAnirudh Venkataramanan /* Reserved for command, only used for response */ 1869c20346bSAnirudh Venkataramanan __le16 num_elems; 1879c20346bSAnirudh Venkataramanan __le16 rsvd; 1889c20346bSAnirudh Venkataramanan __le32 addr_high; 1899c20346bSAnirudh Venkataramanan __le32 addr_low; 1909c20346bSAnirudh Venkataramanan }; 1919c20346bSAnirudh Venkataramanan 1929c20346bSAnirudh Venkataramanan /* Each entry in the response buffer is of the following type: */ 1939c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg_resp_elem { 1949c20346bSAnirudh Venkataramanan /* VSI/Port Number */ 1959c20346bSAnirudh Venkataramanan __le16 vsi_port_num; 1969c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 1979c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 1989c20346bSAnirudh Venkataramanan (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 1999c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 2009c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 2019c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 2029c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 2039c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 2049c20346bSAnirudh Venkataramanan 2059c20346bSAnirudh Venkataramanan /* SWID VSI/Port belongs to */ 2069c20346bSAnirudh Venkataramanan __le16 swid; 2079c20346bSAnirudh Venkataramanan 2089c20346bSAnirudh Venkataramanan /* Bit 14..0 : PF/VF number VSI belongs to 2099c20346bSAnirudh Venkataramanan * Bit 15 : VF indication bit 2109c20346bSAnirudh Venkataramanan */ 2119c20346bSAnirudh Venkataramanan __le16 pf_vf_num; 2129c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 2139c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 2149c20346bSAnirudh Venkataramanan (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 2159c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 2169c20346bSAnirudh Venkataramanan }; 2179c20346bSAnirudh Venkataramanan 2189daf8208SAnirudh Venkataramanan /* These resource type defines are used for all switch resource 2199daf8208SAnirudh Venkataramanan * commands where a resource type is required, such as: 2209daf8208SAnirudh Venkataramanan * Get Resource Allocation command (indirect 0x0204) 2219daf8208SAnirudh Venkataramanan * Allocate Resources command (indirect 0x0208) 2229daf8208SAnirudh Venkataramanan * Free Resources command (indirect 0x0209) 2239daf8208SAnirudh Venkataramanan * Get Allocated Resource Descriptors Command (indirect 0x020A) 2249daf8208SAnirudh Venkataramanan */ 2259daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 2269daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 227148beb61SHenry Tieman #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 228148beb61SHenry Tieman #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 229148beb61SHenry Tieman #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 230148beb61SHenry Tieman #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 231148beb61SHenry Tieman #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 23231ad4e4eSTony Nguyen #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 233451f2c44STony Nguyen #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 23431ad4e4eSTony Nguyen 23531ad4e4eSTony Nguyen #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 23631ad4e4eSTony Nguyen #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 23731ad4e4eSTony Nguyen 23831ad4e4eSTony Nguyen #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 2399daf8208SAnirudh Venkataramanan 240148beb61SHenry Tieman #define ICE_AQC_RES_TYPE_S 0 241148beb61SHenry Tieman #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 242148beb61SHenry Tieman 2439daf8208SAnirudh Venkataramanan /* Allocate Resources command (indirect 0x0208) 2449daf8208SAnirudh Venkataramanan * Free Resources command (indirect 0x0209) 2459daf8208SAnirudh Venkataramanan */ 2469daf8208SAnirudh Venkataramanan struct ice_aqc_alloc_free_res_cmd { 2479daf8208SAnirudh Venkataramanan __le16 num_entries; /* Number of Resource entries */ 2489daf8208SAnirudh Venkataramanan u8 reserved[6]; 2499daf8208SAnirudh Venkataramanan __le32 addr_high; 2509daf8208SAnirudh Venkataramanan __le32 addr_low; 2519daf8208SAnirudh Venkataramanan }; 2529daf8208SAnirudh Venkataramanan 2539daf8208SAnirudh Venkataramanan /* Resource descriptor */ 2549daf8208SAnirudh Venkataramanan struct ice_aqc_res_elem { 2559daf8208SAnirudh Venkataramanan union { 2569daf8208SAnirudh Venkataramanan __le16 sw_resp; 2579daf8208SAnirudh Venkataramanan __le16 flu_resp; 2589daf8208SAnirudh Venkataramanan } e; 2599daf8208SAnirudh Venkataramanan }; 2609daf8208SAnirudh Venkataramanan 2619daf8208SAnirudh Venkataramanan /* Buffer for Allocate/Free Resources commands */ 2629daf8208SAnirudh Venkataramanan struct ice_aqc_alloc_free_res_elem { 2639daf8208SAnirudh Venkataramanan __le16 res_type; /* Types defined above cmd 0x0204 */ 2649daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_SHARED_S 7 2659daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 2669daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 2679daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 2689daf8208SAnirudh Venkataramanan (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 2699daf8208SAnirudh Venkataramanan __le16 num_elems; 27066486d89SBruce Allan struct ice_aqc_res_elem elem[]; 2719daf8208SAnirudh Venkataramanan }; 2729daf8208SAnirudh Venkataramanan 2733a858ba3SAnirudh Venkataramanan /* Add VSI (indirect 0x0210) 2743a858ba3SAnirudh Venkataramanan * Update VSI (indirect 0x0211) 2753a858ba3SAnirudh Venkataramanan * Get VSI (indirect 0x0212) 2763a858ba3SAnirudh Venkataramanan * Free VSI (indirect 0x0213) 2773a858ba3SAnirudh Venkataramanan */ 2783a858ba3SAnirudh Venkataramanan struct ice_aqc_add_get_update_free_vsi { 2793a858ba3SAnirudh Venkataramanan __le16 vsi_num; 2803a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_NUM_S 0 2813a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 2823a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_IS_VALID BIT(15) 2833a858ba3SAnirudh Venkataramanan __le16 cmd_flags; 2843a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_KEEP_ALLOC 0x1 2853a858ba3SAnirudh Venkataramanan u8 vf_id; 2863a858ba3SAnirudh Venkataramanan u8 reserved; 2873a858ba3SAnirudh Venkataramanan __le16 vsi_flags; 2883a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_S 0 2893a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 2903a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_VF 0x0 2913a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 2923a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_PF 0x2 2933a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 2943a858ba3SAnirudh Venkataramanan __le32 addr_high; 2953a858ba3SAnirudh Venkataramanan __le32 addr_low; 2963a858ba3SAnirudh Venkataramanan }; 2973a858ba3SAnirudh Venkataramanan 2983a858ba3SAnirudh Venkataramanan /* Response descriptor for: 2993a858ba3SAnirudh Venkataramanan * Add VSI (indirect 0x0210) 3003a858ba3SAnirudh Venkataramanan * Update VSI (indirect 0x0211) 3013a858ba3SAnirudh Venkataramanan * Free VSI (indirect 0x0213) 3023a858ba3SAnirudh Venkataramanan */ 3033a858ba3SAnirudh Venkataramanan struct ice_aqc_add_update_free_vsi_resp { 3043a858ba3SAnirudh Venkataramanan __le16 vsi_num; 3053a858ba3SAnirudh Venkataramanan __le16 ext_status; 3063a858ba3SAnirudh Venkataramanan __le16 vsi_used; 3073a858ba3SAnirudh Venkataramanan __le16 vsi_free; 3083a858ba3SAnirudh Venkataramanan __le32 addr_high; 3093a858ba3SAnirudh Venkataramanan __le32 addr_low; 3103a858ba3SAnirudh Venkataramanan }; 3113a858ba3SAnirudh Venkataramanan 3123a858ba3SAnirudh Venkataramanan struct ice_aqc_vsi_props { 3133a858ba3SAnirudh Venkataramanan __le16 valid_sections; 3143a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 3153a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 3163a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 3173a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 3183a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 3193a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 3203a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 3213a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 3223a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 3233a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 3243a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 3253a858ba3SAnirudh Venkataramanan /* switch section */ 3263a858ba3SAnirudh Venkataramanan u8 sw_id; 3273a858ba3SAnirudh Venkataramanan u8 sw_flags; 3283a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 3293a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 3303a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 3313a858ba3SAnirudh Venkataramanan u8 sw_flags2; 3323a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 3333a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 3343a858ba3SAnirudh Venkataramanan (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 3353a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 3363a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 3373a858ba3SAnirudh Venkataramanan u8 veb_stat_id; 3383a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 3393a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 3403a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 3413a858ba3SAnirudh Venkataramanan /* security section */ 3423a858ba3SAnirudh Venkataramanan u8 sec_flags; 3433a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 3443a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 3453a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 3463a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 3473a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 3483a858ba3SAnirudh Venkataramanan u8 sec_reserved; 3493a858ba3SAnirudh Venkataramanan /* VLAN section */ 3503a858ba3SAnirudh Venkataramanan __le16 pvid; /* VLANS include priority bits */ 3513a858ba3SAnirudh Venkataramanan u8 pvlan_reserved[2]; 3525d8778d8SBrett Creeley u8 vlan_flags; 3535d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_S 0 3545d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 3555d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 3565d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 3575d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 3583a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 3595d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_S 3 3605d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 3615d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 3625d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 3635d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 3645d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 3653a858ba3SAnirudh Venkataramanan u8 pvlan_reserved2[3]; 3663a858ba3SAnirudh Venkataramanan /* ingress egress up sections */ 3673a858ba3SAnirudh Venkataramanan __le32 ingress_table; /* bitmap, 3 bits per up */ 3683a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 3693a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 3703a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 3713a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 3723a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 3733a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 3743a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 3753a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 3763a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 3773a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 3783a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 3793a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 3803a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 3813a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 3823a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 3833a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 3843a858ba3SAnirudh Venkataramanan __le32 egress_table; /* same defines as for ingress table */ 3853a858ba3SAnirudh Venkataramanan /* outer tags section */ 3863a858ba3SAnirudh Venkataramanan __le16 outer_tag; 3873a858ba3SAnirudh Venkataramanan u8 outer_tag_flags; 3883a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 3893a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 3903a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 3913a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 3923a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 3933a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 3943a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 3953a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 3963a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 3973a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 3983a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 3993a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 4003a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 4013a858ba3SAnirudh Venkataramanan u8 outer_tag_reserved; 4023a858ba3SAnirudh Venkataramanan /* queue mapping section */ 4033a858ba3SAnirudh Venkataramanan __le16 mapping_flags; 4043a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 4053a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 4063a858ba3SAnirudh Venkataramanan __le16 q_mapping[16]; 4073a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_S 0 4083a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 4093a858ba3SAnirudh Venkataramanan __le16 tc_mapping[8]; 4103a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 4113a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 4123a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_NUM_S 11 4133a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 4143a858ba3SAnirudh Venkataramanan /* queueing option section */ 4153a858ba3SAnirudh Venkataramanan u8 q_opt_rss; 4163a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 4173a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 4183a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 4193a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 4203a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 4213a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 4223a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 4233a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 4243a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4253a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4263a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4273a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4283a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4293a858ba3SAnirudh Venkataramanan u8 q_opt_tc; 4303a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 4313a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 4323a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 4333a858ba3SAnirudh Venkataramanan u8 q_opt_flags; 4343a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 4353a858ba3SAnirudh Venkataramanan u8 q_opt_reserved[3]; 4363a858ba3SAnirudh Venkataramanan /* outer up section */ 4373a858ba3SAnirudh Venkataramanan __le32 outer_up_table; /* same structure and defines as ingress tbl */ 4383a858ba3SAnirudh Venkataramanan /* section 10 */ 4393a858ba3SAnirudh Venkataramanan __le16 sect_10_reserved; 4403a858ba3SAnirudh Venkataramanan /* flow director section */ 4413a858ba3SAnirudh Venkataramanan __le16 fd_options; 4423a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_ENABLE BIT(0) 4433a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 4443a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 4453a858ba3SAnirudh Venkataramanan __le16 max_fd_fltr_dedicated; 4463a858ba3SAnirudh Venkataramanan __le16 max_fd_fltr_shared; 4473a858ba3SAnirudh Venkataramanan __le16 fd_def_q; 4483a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_Q_S 0 4493a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 4503a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_GRP_S 12 4513a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 4523a858ba3SAnirudh Venkataramanan __le16 fd_report_opt; 4533a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_REPORT_Q_S 0 4543a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 4553a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 4563a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 4573a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 4583a858ba3SAnirudh Venkataramanan /* PASID section */ 4593a858ba3SAnirudh Venkataramanan __le32 pasid_id; 4603a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PASID_ID_S 0 4613a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 4623a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 4633a858ba3SAnirudh Venkataramanan u8 reserved[24]; 4643a858ba3SAnirudh Venkataramanan }; 4653a858ba3SAnirudh Venkataramanan 46680d144c9SAnirudh Venkataramanan #define ICE_MAX_NUM_RECIPES 64 46780d144c9SAnirudh Venkataramanan 4689daf8208SAnirudh Venkataramanan /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 4699daf8208SAnirudh Venkataramanan */ 4709daf8208SAnirudh Venkataramanan struct ice_aqc_sw_rules { 4719daf8208SAnirudh Venkataramanan /* ops: add switch rules, referring the number of rules. 4729daf8208SAnirudh Venkataramanan * ops: update switch rules, referring the number of filters 4739daf8208SAnirudh Venkataramanan * ops: remove switch rules, referring the entry index. 4749daf8208SAnirudh Venkataramanan * ops: get switch rules, referring to the number of filters. 4759daf8208SAnirudh Venkataramanan */ 4769daf8208SAnirudh Venkataramanan __le16 num_rules_fltr_entry_index; 4779daf8208SAnirudh Venkataramanan u8 reserved[6]; 4789daf8208SAnirudh Venkataramanan __le32 addr_high; 4799daf8208SAnirudh Venkataramanan __le32 addr_low; 4809daf8208SAnirudh Venkataramanan }; 4819daf8208SAnirudh Venkataramanan 4829daf8208SAnirudh Venkataramanan /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 4839daf8208SAnirudh Venkataramanan * This structures describes the lookup rules and associated actions. "index" 4849daf8208SAnirudh Venkataramanan * is returned as part of a response to a successful Add command, and can be 4859daf8208SAnirudh Venkataramanan * used to identify the rule for Update/Get/Remove commands. 4869daf8208SAnirudh Venkataramanan */ 4879daf8208SAnirudh Venkataramanan struct ice_sw_rule_lkup_rx_tx { 4889daf8208SAnirudh Venkataramanan __le16 recipe_id; 4899daf8208SAnirudh Venkataramanan #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 4909daf8208SAnirudh Venkataramanan /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 4919daf8208SAnirudh Venkataramanan __le16 src; 4929daf8208SAnirudh Venkataramanan __le32 act; 4939daf8208SAnirudh Venkataramanan 4949daf8208SAnirudh Venkataramanan /* Bit 0:1 - Action type */ 4959daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_TYPE_S 0x00 4969daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 4979daf8208SAnirudh Venkataramanan 4989daf8208SAnirudh Venkataramanan /* Bit 2 - Loop back enable 4999daf8208SAnirudh Venkataramanan * Bit 3 - LAN enable 5009daf8208SAnirudh Venkataramanan */ 5019daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 5029daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 5039daf8208SAnirudh Venkataramanan 5049daf8208SAnirudh Venkataramanan /* Action type = 0 - Forward to VSI or VSI list */ 5059daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 5069daf8208SAnirudh Venkataramanan 5079daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_ID_S 4 5089daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 5099daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 5109daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 5119daf8208SAnirudh Venkataramanan /* This bit needs to be set if action is forward to VSI list */ 5129daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 5139daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 5149daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_DROP BIT(18) 5159daf8208SAnirudh Venkataramanan 5169daf8208SAnirudh Venkataramanan /* Action type = 1 - Forward to Queue of Queue group */ 5179daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_TO_Q 0x1 5189daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_INDEX_S 4 5199daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 5209daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_REGION_S 15 5219daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 5229daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 5239daf8208SAnirudh Venkataramanan 5249daf8208SAnirudh Venkataramanan /* Action type = 2 - Prune */ 5259daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PRUNE 0x2 5269daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_EGRESS BIT(15) 5279daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_INGRESS BIT(16) 5289daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PRUNET BIT(17) 5299daf8208SAnirudh Venkataramanan /* Bit 18 should be set to 0 for this action */ 5309daf8208SAnirudh Venkataramanan 5319daf8208SAnirudh Venkataramanan /* Action type = 2 - Pointer */ 5329daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR 0x2 5339daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR_VAL_S 4 5349daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 5359daf8208SAnirudh Venkataramanan /* Bit 18 should be set to 1 */ 5369daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 5379daf8208SAnirudh Venkataramanan 5389daf8208SAnirudh Venkataramanan /* Action type = 3 - Other actions. Last two bits 5399daf8208SAnirudh Venkataramanan * are other action identifier 5409daf8208SAnirudh Venkataramanan */ 5419daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 5429daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 5439daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 544c522d1f6SBruce Allan (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 5459daf8208SAnirudh Venkataramanan 5469daf8208SAnirudh Venkataramanan /* Bit 17:18 - Defines other actions */ 5479daf8208SAnirudh Venkataramanan /* Other action = 0 - Mirror VSI */ 5489daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_MIRROR 0 5499daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 5509daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 5519daf8208SAnirudh Venkataramanan (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 5529daf8208SAnirudh Venkataramanan 5539daf8208SAnirudh Venkataramanan /* Other action = 3 - Set Stat count */ 5549daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 5559daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 5569daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 5579daf8208SAnirudh Venkataramanan (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 5589daf8208SAnirudh Venkataramanan 5599daf8208SAnirudh Venkataramanan __le16 index; /* The index of the rule in the lookup table */ 5609daf8208SAnirudh Venkataramanan /* Length and values of the header to be matched per recipe or 5619daf8208SAnirudh Venkataramanan * lookup-type 5629daf8208SAnirudh Venkataramanan */ 5639daf8208SAnirudh Venkataramanan __le16 hdr_len; 56466486d89SBruce Allan u8 hdr[]; 56566486d89SBruce Allan }; 5669daf8208SAnirudh Venkataramanan 5679daf8208SAnirudh Venkataramanan /* Add/Update/Remove large action command/response entry 5689daf8208SAnirudh Venkataramanan * "index" is returned as part of a response to a successful Add command, and 5699daf8208SAnirudh Venkataramanan * can be used to identify the action for Update/Get/Remove commands. 5709daf8208SAnirudh Venkataramanan */ 5719daf8208SAnirudh Venkataramanan struct ice_sw_rule_lg_act { 5729daf8208SAnirudh Venkataramanan __le16 index; /* Index in large action table */ 5739daf8208SAnirudh Venkataramanan __le16 size; 5749daf8208SAnirudh Venkataramanan /* Max number of large actions */ 5759daf8208SAnirudh Venkataramanan #define ICE_MAX_LG_ACT 4 5769daf8208SAnirudh Venkataramanan /* Bit 0:1 - Action type */ 5779daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_TYPE_S 0 5789daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 5799daf8208SAnirudh Venkataramanan 5809daf8208SAnirudh Venkataramanan /* Action type = 0 - Forward to VSI or VSI list */ 5819daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_FORWARDING 0 5829daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_ID_S 3 5839daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 5849daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_LIST_ID_S 3 5859daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 5869daf8208SAnirudh Venkataramanan /* This bit needs to be set if action is forward to VSI list */ 5879daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_LIST BIT(13) 5889daf8208SAnirudh Venkataramanan 5899daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VALID_BIT BIT(16) 5909daf8208SAnirudh Venkataramanan 5919daf8208SAnirudh Venkataramanan /* Action type = 1 - Forward to Queue of Queue group */ 5929daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_TO_Q 0x1 5939daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_INDEX_S 3 5949daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 5959daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_REGION_S 14 5969daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 5979daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 5989daf8208SAnirudh Venkataramanan 5999daf8208SAnirudh Venkataramanan /* Action type = 2 - Prune */ 6009daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_PRUNE 0x2 6019daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_EGRESS BIT(14) 6029daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_INGRESS BIT(15) 6039daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_PRUNET BIT(16) 6049daf8208SAnirudh Venkataramanan 6059daf8208SAnirudh Venkataramanan /* Action type = 3 - Mirror VSI */ 6069daf8208SAnirudh Venkataramanan #define ICE_LG_OTHER_ACT_MIRROR 0x3 6079daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 6089daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 6099daf8208SAnirudh Venkataramanan 61034357a90SAnirudh Venkataramanan /* Action type = 5 - Generic Value */ 6119daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC 0x5 6129daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_VALUE_S 3 6139daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 6149daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_OFFSET_S 19 6159daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 6169daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 6179daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 6184381147dSAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 6199daf8208SAnirudh Venkataramanan 6209daf8208SAnirudh Venkataramanan /* Action = 7 - Set Stat count */ 6219daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_STAT_COUNT 0x7 6229daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_STAT_COUNT_S 3 6239daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 62466486d89SBruce Allan __le32 act[]; /* array of size for actions */ 6259daf8208SAnirudh Venkataramanan }; 6269daf8208SAnirudh Venkataramanan 6279daf8208SAnirudh Venkataramanan /* Add/Update/Remove VSI list command/response entry 6289daf8208SAnirudh Venkataramanan * "index" is returned as part of a response to a successful Add command, and 6299daf8208SAnirudh Venkataramanan * can be used to identify the VSI list for Update/Get/Remove commands. 6309daf8208SAnirudh Venkataramanan */ 6319daf8208SAnirudh Venkataramanan struct ice_sw_rule_vsi_list { 6329daf8208SAnirudh Venkataramanan __le16 index; /* Index of VSI/Prune list */ 6339daf8208SAnirudh Venkataramanan __le16 number_vsi; 63466486d89SBruce Allan __le16 vsi[]; /* Array of number_vsi VSI numbers */ 6359daf8208SAnirudh Venkataramanan }; 6369daf8208SAnirudh Venkataramanan 6379daf8208SAnirudh Venkataramanan /* Query VSI list command/response entry */ 6389daf8208SAnirudh Venkataramanan struct ice_sw_rule_vsi_list_query { 6399daf8208SAnirudh Venkataramanan __le16 index; 6409daf8208SAnirudh Venkataramanan DECLARE_BITMAP(vsi_list, ICE_MAX_VSI); 6419daf8208SAnirudh Venkataramanan } __packed; 6429daf8208SAnirudh Venkataramanan 6439daf8208SAnirudh Venkataramanan /* Add switch rule response: 6449daf8208SAnirudh Venkataramanan * Content of return buffer is same as the input buffer. The status field and 6459daf8208SAnirudh Venkataramanan * LUT index are updated as part of the response 6469daf8208SAnirudh Venkataramanan */ 6479daf8208SAnirudh Venkataramanan struct ice_aqc_sw_rules_elem { 6489daf8208SAnirudh Venkataramanan __le16 type; /* Switch rule type, one of T_... */ 6499daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 6509daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 6519daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 6529daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 6539daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 6549daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 6559daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 6569daf8208SAnirudh Venkataramanan __le16 status; 6579daf8208SAnirudh Venkataramanan union { 6589daf8208SAnirudh Venkataramanan struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 6599daf8208SAnirudh Venkataramanan struct ice_sw_rule_lg_act lg_act; 6609daf8208SAnirudh Venkataramanan struct ice_sw_rule_vsi_list vsi_list; 6619daf8208SAnirudh Venkataramanan struct ice_sw_rule_vsi_list_query vsi_list_query; 6629daf8208SAnirudh Venkataramanan } __packed pdata; 6639daf8208SAnirudh Venkataramanan }; 6649daf8208SAnirudh Venkataramanan 665dc49c772SAnirudh Venkataramanan /* Get Default Topology (indirect 0x0400) */ 666dc49c772SAnirudh Venkataramanan struct ice_aqc_get_topo { 667dc49c772SAnirudh Venkataramanan u8 port_num; 668dc49c772SAnirudh Venkataramanan u8 num_branches; 669dc49c772SAnirudh Venkataramanan __le16 reserved1; 670dc49c772SAnirudh Venkataramanan __le32 reserved2; 671dc49c772SAnirudh Venkataramanan __le32 addr_high; 672dc49c772SAnirudh Venkataramanan __le32 addr_low; 673dc49c772SAnirudh Venkataramanan }; 674dc49c772SAnirudh Venkataramanan 6755513b920SAnirudh Venkataramanan /* Update TSE (indirect 0x0403) 6765513b920SAnirudh Venkataramanan * Get TSE (indirect 0x0404) 6771f9c7840SAnirudh Venkataramanan * Add TSE (indirect 0x0401) 6781f9c7840SAnirudh Venkataramanan * Delete TSE (indirect 0x040F) 6791f9c7840SAnirudh Venkataramanan * Move TSE (indirect 0x0408) 6801f9c7840SAnirudh Venkataramanan * Suspend Nodes (indirect 0x0409) 6811f9c7840SAnirudh Venkataramanan * Resume Nodes (indirect 0x040A) 6825513b920SAnirudh Venkataramanan */ 6831f9c7840SAnirudh Venkataramanan struct ice_aqc_sched_elem_cmd { 6845513b920SAnirudh Venkataramanan __le16 num_elem_req; /* Used by commands */ 6855513b920SAnirudh Venkataramanan __le16 num_elem_resp; /* Used by responses */ 6865513b920SAnirudh Venkataramanan __le32 reserved; 6875513b920SAnirudh Venkataramanan __le32 addr_high; 6885513b920SAnirudh Venkataramanan __le32 addr_low; 6895513b920SAnirudh Venkataramanan }; 6905513b920SAnirudh Venkataramanan 6919c20346bSAnirudh Venkataramanan struct ice_aqc_elem_info_bw { 6929c20346bSAnirudh Venkataramanan __le16 bw_profile_idx; 6939c20346bSAnirudh Venkataramanan __le16 bw_alloc; 6949c20346bSAnirudh Venkataramanan }; 6959c20346bSAnirudh Venkataramanan 6969c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem { 6979c20346bSAnirudh Venkataramanan u8 elem_type; /* Special field, reserved for some aq calls */ 6989c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 6999c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 7009c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_TC 0x2 7019c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 7029c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 7039c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_LEAF 0x5 7049c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 7059c20346bSAnirudh Venkataramanan u8 valid_sections; 7069c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 7079c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_CIR BIT(1) 7089c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_EIR BIT(2) 7099c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 7109c20346bSAnirudh Venkataramanan u8 generic; 7119c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 7129c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 7139c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 7149c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 7159c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 7169c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 7179c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 7189c20346bSAnirudh Venkataramanan (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 7199c20346bSAnirudh Venkataramanan u8 flags; /* Special field, reserved for some aq calls */ 7209c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 7219c20346bSAnirudh Venkataramanan struct ice_aqc_elem_info_bw cir_bw; 7229c20346bSAnirudh Venkataramanan struct ice_aqc_elem_info_bw eir_bw; 7239c20346bSAnirudh Venkataramanan __le16 srl_id; 7249c20346bSAnirudh Venkataramanan __le16 reserved2; 7259c20346bSAnirudh Venkataramanan }; 7269c20346bSAnirudh Venkataramanan 7279c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem_data { 7289c20346bSAnirudh Venkataramanan __le32 parent_teid; 7299c20346bSAnirudh Venkataramanan __le32 node_teid; 7309c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem data; 7319c20346bSAnirudh Venkataramanan }; 7329c20346bSAnirudh Venkataramanan 7339c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr { 7349c20346bSAnirudh Venkataramanan __le32 parent_teid; 7359c20346bSAnirudh Venkataramanan __le16 num_elems; 7369c20346bSAnirudh Venkataramanan __le16 reserved2; 7379c20346bSAnirudh Venkataramanan }; 7389c20346bSAnirudh Venkataramanan 7395513b920SAnirudh Venkataramanan struct ice_aqc_add_elem { 7405513b920SAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr hdr; 74166486d89SBruce Allan struct ice_aqc_txsched_elem_data generic[]; 7425513b920SAnirudh Venkataramanan }; 7435513b920SAnirudh Venkataramanan 744dc49c772SAnirudh Venkataramanan struct ice_aqc_get_topo_elem { 745dc49c772SAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr hdr; 746dc49c772SAnirudh Venkataramanan struct ice_aqc_txsched_elem_data 747dc49c772SAnirudh Venkataramanan generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 748dc49c772SAnirudh Venkataramanan }; 749dc49c772SAnirudh Venkataramanan 7509c20346bSAnirudh Venkataramanan struct ice_aqc_delete_elem { 7519c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr hdr; 75266486d89SBruce Allan __le32 teid[]; 7539c20346bSAnirudh Venkataramanan }; 7549c20346bSAnirudh Venkataramanan 7557b9ffc76SAnirudh Venkataramanan /* Query Port ETS (indirect 0x040E) 7567b9ffc76SAnirudh Venkataramanan * 7577b9ffc76SAnirudh Venkataramanan * This indirect command is used to query port TC node configuration. 7587b9ffc76SAnirudh Venkataramanan */ 7597b9ffc76SAnirudh Venkataramanan struct ice_aqc_query_port_ets { 7607b9ffc76SAnirudh Venkataramanan __le32 port_teid; 7617b9ffc76SAnirudh Venkataramanan __le32 reserved; 7627b9ffc76SAnirudh Venkataramanan __le32 addr_high; 7637b9ffc76SAnirudh Venkataramanan __le32 addr_low; 7647b9ffc76SAnirudh Venkataramanan }; 7657b9ffc76SAnirudh Venkataramanan 7667b9ffc76SAnirudh Venkataramanan struct ice_aqc_port_ets_elem { 7677b9ffc76SAnirudh Venkataramanan u8 tc_valid_bits; 7687b9ffc76SAnirudh Venkataramanan u8 reserved[3]; 7697b9ffc76SAnirudh Venkataramanan /* 3 bits for UP per TC 0-7, 4th byte reserved */ 7707b9ffc76SAnirudh Venkataramanan __le32 up2tc; 7717b9ffc76SAnirudh Venkataramanan u8 tc_bw_share[8]; 7727b9ffc76SAnirudh Venkataramanan __le32 port_eir_prof_id; 7737b9ffc76SAnirudh Venkataramanan __le32 port_cir_prof_id; 7747b9ffc76SAnirudh Venkataramanan /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 7757b9ffc76SAnirudh Venkataramanan __le32 tc_node_prio; 7767b9ffc76SAnirudh Venkataramanan #define ICE_TC_NODE_PRIO_S 0x4 7777b9ffc76SAnirudh Venkataramanan u8 reserved1[4]; 7787b9ffc76SAnirudh Venkataramanan __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 7797b9ffc76SAnirudh Venkataramanan }; 7807b9ffc76SAnirudh Venkataramanan 7811ddef455SUsha Ketineni /* Rate limiting profile for 7821ddef455SUsha Ketineni * Add RL profile (indirect 0x0410) 7831ddef455SUsha Ketineni * Query RL profile (indirect 0x0411) 7841ddef455SUsha Ketineni * Remove RL profile (indirect 0x0415) 7851ddef455SUsha Ketineni * These indirect commands acts on single or multiple 7861ddef455SUsha Ketineni * RL profiles with specified data. 7871ddef455SUsha Ketineni */ 7881ddef455SUsha Ketineni struct ice_aqc_rl_profile { 7891ddef455SUsha Ketineni __le16 num_profiles; 7901ddef455SUsha Ketineni __le16 num_processed; /* Only for response. Reserved in Command. */ 7911ddef455SUsha Ketineni u8 reserved[4]; 7921ddef455SUsha Ketineni __le32 addr_high; 7931ddef455SUsha Ketineni __le32 addr_low; 7941ddef455SUsha Ketineni }; 7951ddef455SUsha Ketineni 7961ddef455SUsha Ketineni struct ice_aqc_rl_profile_elem { 7971ddef455SUsha Ketineni u8 level; 7981ddef455SUsha Ketineni u8 flags; 7991ddef455SUsha Ketineni #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 8001ddef455SUsha Ketineni #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 8011ddef455SUsha Ketineni #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 8021ddef455SUsha Ketineni #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 8031ddef455SUsha Ketineni #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 8041ddef455SUsha Ketineni /* The following flag is used for Query RL Profile Data */ 8051ddef455SUsha Ketineni #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 8061ddef455SUsha Ketineni #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 8071ddef455SUsha Ketineni 8081ddef455SUsha Ketineni __le16 profile_id; 8091ddef455SUsha Ketineni __le16 max_burst_size; 8101ddef455SUsha Ketineni __le16 rl_multiply; 8111ddef455SUsha Ketineni __le16 wake_up_calc; 8121ddef455SUsha Ketineni __le16 rl_encode; 8131ddef455SUsha Ketineni }; 8141ddef455SUsha Ketineni 8159c20346bSAnirudh Venkataramanan /* Query Scheduler Resource Allocation (indirect 0x0412) 8169c20346bSAnirudh Venkataramanan * This indirect command retrieves the scheduler resources allocated by 8179c20346bSAnirudh Venkataramanan * EMP Firmware to the given PF. 8189c20346bSAnirudh Venkataramanan */ 8199c20346bSAnirudh Venkataramanan struct ice_aqc_query_txsched_res { 8209c20346bSAnirudh Venkataramanan u8 reserved[8]; 8219c20346bSAnirudh Venkataramanan __le32 addr_high; 8229c20346bSAnirudh Venkataramanan __le32 addr_low; 8239c20346bSAnirudh Venkataramanan }; 8249c20346bSAnirudh Venkataramanan 8259c20346bSAnirudh Venkataramanan struct ice_aqc_generic_sched_props { 8269c20346bSAnirudh Venkataramanan __le16 phys_levels; 8279c20346bSAnirudh Venkataramanan __le16 logical_levels; 8289c20346bSAnirudh Venkataramanan u8 flattening_bitmap; 8299c20346bSAnirudh Venkataramanan u8 max_device_cgds; 8309c20346bSAnirudh Venkataramanan u8 max_pf_cgds; 8319c20346bSAnirudh Venkataramanan u8 rsvd0; 8329c20346bSAnirudh Venkataramanan __le16 rdma_qsets; 8339c20346bSAnirudh Venkataramanan u8 rsvd1[22]; 8349c20346bSAnirudh Venkataramanan }; 8359c20346bSAnirudh Venkataramanan 8369c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props { 8379c20346bSAnirudh Venkataramanan u8 logical_layer; 8389c20346bSAnirudh Venkataramanan u8 chunk_size; 8399c20346bSAnirudh Venkataramanan __le16 max_device_nodes; 8409c20346bSAnirudh Venkataramanan __le16 max_pf_nodes; 841b36c598cSAnirudh Venkataramanan u8 rsvd0[4]; 842b36c598cSAnirudh Venkataramanan __le16 max_sibl_grp_sz; 8439c20346bSAnirudh Venkataramanan __le16 max_cir_rl_profiles; 8449c20346bSAnirudh Venkataramanan __le16 max_eir_rl_profiles; 8459c20346bSAnirudh Venkataramanan __le16 max_srl_profiles; 8469c20346bSAnirudh Venkataramanan u8 rsvd1[14]; 8479c20346bSAnirudh Venkataramanan }; 8489c20346bSAnirudh Venkataramanan 8499c20346bSAnirudh Venkataramanan struct ice_aqc_query_txsched_res_resp { 8509c20346bSAnirudh Venkataramanan struct ice_aqc_generic_sched_props sched_props; 8519c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 8529c20346bSAnirudh Venkataramanan }; 8539c20346bSAnirudh Venkataramanan 854dc49c772SAnirudh Venkataramanan /* Get PHY capabilities (indirect 0x0600) */ 855dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps { 856dc49c772SAnirudh Venkataramanan u8 lport_num; 857dc49c772SAnirudh Venkataramanan u8 reserved; 858dc49c772SAnirudh Venkataramanan __le16 param0; 859dc49c772SAnirudh Venkataramanan /* 18.0 - Report qualified modules */ 860dc49c772SAnirudh Venkataramanan #define ICE_AQC_GET_PHY_RQM BIT(0) 861dc49c772SAnirudh Venkataramanan /* 18.1 - 18.2 : Report mode 862dc49c772SAnirudh Venkataramanan * 00b - Report NVM capabilities 863dc49c772SAnirudh Venkataramanan * 01b - Report topology capabilities 864dc49c772SAnirudh Venkataramanan * 10b - Report SW configured 865dc49c772SAnirudh Venkataramanan */ 866dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_MODE_S 1 867dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 868dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_NVM_CAP 0 869dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 870dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_SW_CFG BIT(2) 871dc49c772SAnirudh Venkataramanan __le32 reserved1; 872dc49c772SAnirudh Venkataramanan __le32 addr_high; 873dc49c772SAnirudh Venkataramanan __le32 addr_low; 874dc49c772SAnirudh Venkataramanan }; 875dc49c772SAnirudh Venkataramanan 876dc49c772SAnirudh Venkataramanan /* This is #define of PHY type (Extended): 877dc49c772SAnirudh Venkataramanan * The first set of defines is for phy_type_low. 878dc49c772SAnirudh Venkataramanan */ 879dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 880dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 881dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 882dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 883dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 884dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 885dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 886dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 887dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 888dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 889dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 890dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 891dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 892dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 893dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 894dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 895dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 896dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 897dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 898dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 899dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 900dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 901dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 902dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 903dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 904dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 905dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 906dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 907dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 908dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 909dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 910dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 911dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 912dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 913dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 914dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 915aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 916aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 917aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 918aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 919aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 920aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 921aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 922aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 923aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 924aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 925aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 926aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 927aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 928aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 929aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 930aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 931aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 932aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 933aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 934aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 935aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 936aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 937aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 938aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 939aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 940aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 941aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 942aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 943dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 944aef74145SAnirudh Venkataramanan /* The second set of defines is for phy_type_high. */ 945aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 946aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 947aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 948aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 949aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 950bff185e2SChinh T Cao #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 951dc49c772SAnirudh Venkataramanan 952dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps_data { 953dc49c772SAnirudh Venkataramanan __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 954b6f934f0SBrett Creeley __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 955dc49c772SAnirudh Venkataramanan u8 caps; 956dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 957dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 958dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 959dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_LINK BIT(3) 960dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_AN_MODE BIT(4) 961dc49c772SAnirudh Venkataramanan #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 962f776b3acSPaul Greenwalt #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 963f776b3acSPaul Greenwalt #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 964dc49c772SAnirudh Venkataramanan u8 low_power_ctrl; 965dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 966dc49c772SAnirudh Venkataramanan __le16 eee_cap; 967dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 968dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 969dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 970dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 971dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 972dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 973dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 974dc49c772SAnirudh Venkataramanan __le16 eeer_value; 975dc49c772SAnirudh Venkataramanan u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 97662f4dafcSAnirudh Venkataramanan u8 phy_fw_ver[8]; 977dc49c772SAnirudh Venkataramanan u8 link_fec_options; 978dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 979dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 980dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 981dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 982dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 983dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 984dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 985f776b3acSPaul Greenwalt #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 986ea78ce4dSPaul Greenwalt u8 module_compliance_enforcement; 987ea78ce4dSPaul Greenwalt #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 988dc49c772SAnirudh Venkataramanan u8 extended_compliance_code; 989dc49c772SAnirudh Venkataramanan #define ICE_MODULE_TYPE_TOTAL_BYTE 3 990dc49c772SAnirudh Venkataramanan u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 991dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 992dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 993dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 994dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 995dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 996dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 997dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 998dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 999dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1000dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1001dc49c772SAnirudh Venkataramanan u8 qualified_module_count; 100262f4dafcSAnirudh Venkataramanan u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1003dc49c772SAnirudh Venkataramanan #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1004dc49c772SAnirudh Venkataramanan struct { 1005dc49c772SAnirudh Venkataramanan u8 v_oui[3]; 100662f4dafcSAnirudh Venkataramanan u8 rsvd3; 1007dc49c772SAnirudh Venkataramanan u8 v_part[16]; 1008dc49c772SAnirudh Venkataramanan __le32 v_rev; 100962f4dafcSAnirudh Venkataramanan __le64 rsvd4; 1010dc49c772SAnirudh Venkataramanan } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1011dc49c772SAnirudh Venkataramanan }; 1012dc49c772SAnirudh Venkataramanan 1013fcea6f3dSAnirudh Venkataramanan /* Set PHY capabilities (direct 0x0601) 1014fcea6f3dSAnirudh Venkataramanan * NOTE: This command must be followed by setup link and restart auto-neg 1015fcea6f3dSAnirudh Venkataramanan */ 1016fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg { 1017fcea6f3dSAnirudh Venkataramanan u8 lport_num; 1018fcea6f3dSAnirudh Venkataramanan u8 reserved[7]; 1019fcea6f3dSAnirudh Venkataramanan __le32 addr_high; 1020fcea6f3dSAnirudh Venkataramanan __le32 addr_low; 1021fcea6f3dSAnirudh Venkataramanan }; 1022fcea6f3dSAnirudh Venkataramanan 1023fcea6f3dSAnirudh Venkataramanan /* Set PHY config command data structure */ 1024fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg_data { 1025fcea6f3dSAnirudh Venkataramanan __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1026b6f934f0SBrett Creeley __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1027fcea6f3dSAnirudh Venkataramanan u8 caps; 1028d8df260aSChinh T Cao #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1029fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1030fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1031fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1032fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_LINK BIT(3) 103348cb27f2SChinh Cao #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 103448cb27f2SChinh Cao #define ICE_AQ_PHY_ENA_LESM BIT(6) 103548cb27f2SChinh Cao #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1036fcea6f3dSAnirudh Venkataramanan u8 low_power_ctrl; 1037fcea6f3dSAnirudh Venkataramanan __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1038fcea6f3dSAnirudh Venkataramanan __le16 eeer_value; 1039fcea6f3dSAnirudh Venkataramanan u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1040ea78ce4dSPaul Greenwalt u8 module_compliance_enforcement; 1041fcea6f3dSAnirudh Venkataramanan }; 1042fcea6f3dSAnirudh Venkataramanan 104342449105SAnirudh Venkataramanan /* Set MAC Config command data structure (direct 0x0603) */ 104442449105SAnirudh Venkataramanan struct ice_aqc_set_mac_cfg { 104542449105SAnirudh Venkataramanan __le16 max_frame_size; 104642449105SAnirudh Venkataramanan u8 params; 104742449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_PACE_S 3 104842449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 104942449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 105042449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 105142449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 105242449105SAnirudh Venkataramanan u8 tx_tmr_priority; 105342449105SAnirudh Venkataramanan __le16 tx_tmr_value; 105442449105SAnirudh Venkataramanan __le16 fc_refresh_threshold; 105542449105SAnirudh Venkataramanan u8 drop_opts; 105642449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 105742449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 105842449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 105942449105SAnirudh Venkataramanan u8 reserved[7]; 106042449105SAnirudh Venkataramanan }; 106142449105SAnirudh Venkataramanan 1062fcea6f3dSAnirudh Venkataramanan /* Restart AN command data structure (direct 0x0605) 1063fcea6f3dSAnirudh Venkataramanan * Also used for response, with only the lport_num field present. 1064fcea6f3dSAnirudh Venkataramanan */ 1065fcea6f3dSAnirudh Venkataramanan struct ice_aqc_restart_an { 1066fcea6f3dSAnirudh Venkataramanan u8 lport_num; 1067fcea6f3dSAnirudh Venkataramanan u8 reserved; 1068fcea6f3dSAnirudh Venkataramanan u8 cmd_flags; 1069fcea6f3dSAnirudh Venkataramanan #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1070fcea6f3dSAnirudh Venkataramanan #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1071fcea6f3dSAnirudh Venkataramanan u8 reserved2[13]; 1072fcea6f3dSAnirudh Venkataramanan }; 1073fcea6f3dSAnirudh Venkataramanan 1074dc49c772SAnirudh Venkataramanan /* Get link status (indirect 0x0607), also used for Link Status Event */ 1075dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status { 1076dc49c772SAnirudh Venkataramanan u8 lport_num; 1077dc49c772SAnirudh Venkataramanan u8 reserved; 1078dc49c772SAnirudh Venkataramanan __le16 cmd_flags; 1079dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_M 0x3 1080dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_NOP 0x0 1081dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_DIS 0x2 1082dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_ENA 0x3 1083dc49c772SAnirudh Venkataramanan /* only response uses this flag */ 1084dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_IS_ENABLED 0x1 1085dc49c772SAnirudh Venkataramanan __le32 reserved2; 1086dc49c772SAnirudh Venkataramanan __le32 addr_high; 1087dc49c772SAnirudh Venkataramanan __le32 addr_low; 1088dc49c772SAnirudh Venkataramanan }; 1089dc49c772SAnirudh Venkataramanan 1090dc49c772SAnirudh Venkataramanan /* Get link status response data structure, also used for Link Status Event */ 1091dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status_data { 1092dc49c772SAnirudh Venkataramanan u8 topo_media_conflict; 1093dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1094dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1095dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 10965878589dSPaul Greenwalt #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 10975878589dSPaul Greenwalt #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 10985878589dSPaul Greenwalt #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 10995878589dSPaul Greenwalt #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1100dc49c772SAnirudh Venkataramanan u8 reserved1; 1101dc49c772SAnirudh Venkataramanan u8 link_info; 1102dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1103dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT BIT(1) 1104dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT_TX BIT(2) 1105dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT_RX BIT(3) 1106dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1107dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1108dc49c772SAnirudh Venkataramanan #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1109dc49c772SAnirudh Venkataramanan #define ICE_AQ_SIGNAL_DETECT BIT(7) 1110dc49c772SAnirudh Venkataramanan u8 an_info; 1111dc49c772SAnirudh Venkataramanan #define ICE_AQ_AN_COMPLETED BIT(0) 1112dc49c772SAnirudh Venkataramanan #define ICE_AQ_LP_AN_ABILITY BIT(1) 1113dc49c772SAnirudh Venkataramanan #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1114dc49c772SAnirudh Venkataramanan #define ICE_AQ_FEC_EN BIT(3) 1115dc49c772SAnirudh Venkataramanan #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1116dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1117dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1118dc49c772SAnirudh Venkataramanan #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1119dc49c772SAnirudh Venkataramanan u8 ext_info; 1120dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1121dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1122f9867df6SAnirudh Venkataramanan /* Port Tx Suspended */ 1123dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_S 2 1124dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1125dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_ACTIVE 0 1126dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_DRAINED 1 1127dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_FLUSHED 3 1128dc49c772SAnirudh Venkataramanan u8 reserved2; 1129dc49c772SAnirudh Venkataramanan __le16 max_frame_size; 1130dc49c772SAnirudh Venkataramanan u8 cfg; 1131dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1132dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1133dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1134f776b3acSPaul Greenwalt #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1135dc49c772SAnirudh Venkataramanan /* Pacing Config */ 1136dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_S 3 1137dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1138dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1139dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1140dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1141dc49c772SAnirudh Venkataramanan /* External Device Power Ability */ 1142dc49c772SAnirudh Venkataramanan u8 power_desc; 1143dc49c772SAnirudh Venkataramanan #define ICE_AQ_PWR_CLASS_M 0x3 1144dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1145dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1146dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1147dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1148dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1149dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1150dc49c772SAnirudh Venkataramanan __le16 link_speed; 11511a3571b5SPaul Greenwalt #define ICE_AQ_LINK_SPEED_M 0x7FF 1152dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1153dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1154dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1155dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1156dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1157dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1158dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1159dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1160dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1161aef74145SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1162aef74145SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1163dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1164dc49c772SAnirudh Venkataramanan __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1165dc49c772SAnirudh Venkataramanan __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1166aef74145SAnirudh Venkataramanan __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1167dc49c772SAnirudh Venkataramanan }; 1168dc49c772SAnirudh Venkataramanan 11690b28b702SAnirudh Venkataramanan /* Set event mask command (direct 0x0613) */ 11700b28b702SAnirudh Venkataramanan struct ice_aqc_set_event_mask { 11710b28b702SAnirudh Venkataramanan u8 lport_num; 11720b28b702SAnirudh Venkataramanan u8 reserved[7]; 11730b28b702SAnirudh Venkataramanan __le16 event_mask; 11740b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 11750b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 11760b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 11770b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 11780b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 11790b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 11800b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 11810b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 11820b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 11830b28b702SAnirudh Venkataramanan u8 reserved1[6]; 11840b28b702SAnirudh Venkataramanan }; 11850b28b702SAnirudh Venkataramanan 11860e674aebSAnirudh Venkataramanan /* Set MAC Loopback command (direct 0x0620) */ 11870e674aebSAnirudh Venkataramanan struct ice_aqc_set_mac_lb { 11880e674aebSAnirudh Venkataramanan u8 lb_mode; 11890e674aebSAnirudh Venkataramanan #define ICE_AQ_MAC_LB_EN BIT(0) 11900e674aebSAnirudh Venkataramanan #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 11910e674aebSAnirudh Venkataramanan u8 reserved[15]; 11920e674aebSAnirudh Venkataramanan }; 11930e674aebSAnirudh Venkataramanan 11948e151d50SAnirudh Venkataramanan /* Set Port Identification LED (direct, 0x06E9) */ 11958e151d50SAnirudh Venkataramanan struct ice_aqc_set_port_id_led { 11968e151d50SAnirudh Venkataramanan u8 lport_num; 11978e151d50SAnirudh Venkataramanan u8 lport_num_valid; 11988e151d50SAnirudh Venkataramanan u8 ident_mode; 11998e151d50SAnirudh Venkataramanan #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 12008e151d50SAnirudh Venkataramanan #define ICE_AQC_PORT_IDENT_LED_ORIG 0 12018e151d50SAnirudh Venkataramanan u8 rsvd[13]; 12028e151d50SAnirudh Venkataramanan }; 12038e151d50SAnirudh Venkataramanan 1204a012dca9SScott W Taylor /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1205a012dca9SScott W Taylor struct ice_aqc_sff_eeprom { 1206a012dca9SScott W Taylor u8 lport_num; 1207a012dca9SScott W Taylor u8 lport_num_valid; 1208a012dca9SScott W Taylor #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1209a012dca9SScott W Taylor __le16 i2c_bus_addr; 1210a012dca9SScott W Taylor #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1211a012dca9SScott W Taylor #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1212a012dca9SScott W Taylor #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1213a012dca9SScott W Taylor #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1214a012dca9SScott W Taylor #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1215a012dca9SScott W Taylor #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1216a012dca9SScott W Taylor #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1217a012dca9SScott W Taylor #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1218a012dca9SScott W Taylor #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1219a012dca9SScott W Taylor #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1220a012dca9SScott W Taylor #define ICE_AQC_SFF_IS_WRITE BIT(15) 1221a012dca9SScott W Taylor __le16 i2c_mem_addr; 1222a012dca9SScott W Taylor __le16 eeprom_page; 1223a012dca9SScott W Taylor #define ICE_AQC_SFF_EEPROM_BANK_S 0 1224a012dca9SScott W Taylor #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1225a012dca9SScott W Taylor #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1226a012dca9SScott W Taylor #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1227a012dca9SScott W Taylor __le32 addr_high; 1228a012dca9SScott W Taylor __le32 addr_low; 1229a012dca9SScott W Taylor }; 1230a012dca9SScott W Taylor 1231f31e4b6fSAnirudh Venkataramanan /* NVM Read command (indirect 0x0701) 1232f31e4b6fSAnirudh Venkataramanan * NVM Erase commands (direct 0x0702) 1233f31e4b6fSAnirudh Venkataramanan * NVM Update commands (indirect 0x0703) 1234f31e4b6fSAnirudh Venkataramanan */ 1235f31e4b6fSAnirudh Venkataramanan struct ice_aqc_nvm { 123681f07491SJacob Keller #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 123743c89b16SAnirudh Venkataramanan __le16 offset_low; 123843c89b16SAnirudh Venkataramanan u8 offset_high; 1239f31e4b6fSAnirudh Venkataramanan u8 cmd_flags; 1240f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_LAST_CMD BIT(0) 1241f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1242f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_PRESERVATION_S 1 12436263e811SLev Faerman #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 12446263e811SLev Faerman #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1245f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 12466263e811SLev Faerman #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1247f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 124843c89b16SAnirudh Venkataramanan __le16 module_typeid; 1249f31e4b6fSAnirudh Venkataramanan __le16 length; 1250f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1251f31e4b6fSAnirudh Venkataramanan __le32 addr_high; 1252f31e4b6fSAnirudh Venkataramanan __le32 addr_low; 1253f31e4b6fSAnirudh Venkataramanan }; 1254f31e4b6fSAnirudh Venkataramanan 1255e9450990SJacob Keller #define ICE_AQC_NVM_START_POINT 0 1256e9450990SJacob Keller 12570e674aebSAnirudh Venkataramanan /* NVM Checksum Command (direct, 0x0706) */ 12580e674aebSAnirudh Venkataramanan struct ice_aqc_nvm_checksum { 12590e674aebSAnirudh Venkataramanan u8 flags; 12600e674aebSAnirudh Venkataramanan #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 12610e674aebSAnirudh Venkataramanan #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 12620e674aebSAnirudh Venkataramanan u8 rsvd; 12630e674aebSAnirudh Venkataramanan __le16 checksum; /* Used only by response */ 12640e674aebSAnirudh Venkataramanan #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 12650e674aebSAnirudh Venkataramanan u8 rsvd2[12]; 12660e674aebSAnirudh Venkataramanan }; 12670e674aebSAnirudh Venkataramanan 1268f45a645fSJacob Keller /* The result of netlist NVM read comes in a TLV format. The actual data 1269f45a645fSJacob Keller * (netlist header) starts from word offset 1 (byte 2). The FW strips 1270f45a645fSJacob Keller * out the type field from the TLV header so all the netlist fields 1271f45a645fSJacob Keller * should adjust their offset value by 1 word (2 bytes) in order to map 1272f45a645fSJacob Keller * their correct location. 1273f45a645fSJacob Keller */ 1274f45a645fSJacob Keller #define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B 1275f45a645fSJacob Keller #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1 1276f45a645fSJacob Keller #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */ 1277f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2 1278f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */ 1279f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_NODE_COUNT_M ICE_M(0x3FF, 0) 1280f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5 1281f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */ 1282f45a645fSJacob Keller 1283f45a645fSJacob Keller /* netlist ID block field offsets (word offsets) */ 1284f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2 1285f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3 1286f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4 1287f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5 1288f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6 1289f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7 1290f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8 1291f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9 1292f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA 1293f45a645fSJacob Keller #define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F 1294f45a645fSJacob Keller 1295007676b4SAnirudh Venkataramanan /** 1296f9867df6SAnirudh Venkataramanan * Send to PF command (indirect 0x0801) ID is only used by PF 1297007676b4SAnirudh Venkataramanan * 1298f9867df6SAnirudh Venkataramanan * Send to VF command (indirect 0x0802) ID is only used by PF 1299007676b4SAnirudh Venkataramanan * 1300007676b4SAnirudh Venkataramanan */ 1301007676b4SAnirudh Venkataramanan struct ice_aqc_pf_vf_msg { 1302007676b4SAnirudh Venkataramanan __le32 id; 1303007676b4SAnirudh Venkataramanan u32 reserved; 1304007676b4SAnirudh Venkataramanan __le32 addr_high; 1305007676b4SAnirudh Venkataramanan __le32 addr_low; 1306007676b4SAnirudh Venkataramanan }; 1307007676b4SAnirudh Venkataramanan 13080ebd3ff1SAnirudh Venkataramanan /* Get LLDP MIB (indirect 0x0A00) 13090ebd3ff1SAnirudh Venkataramanan * Note: This is also used by the LLDP MIB Change Event (0x0A01) 13100ebd3ff1SAnirudh Venkataramanan * as the format is the same. 13110ebd3ff1SAnirudh Venkataramanan */ 13120ebd3ff1SAnirudh Venkataramanan struct ice_aqc_lldp_get_mib { 13130ebd3ff1SAnirudh Venkataramanan u8 type; 13140ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_TYPE_S 0 13150ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 13160ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_LOCAL 0 13170ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_REMOTE 1 13180ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 13190ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_BRID_TYPE_S 2 13200ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 13210ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 13220ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 13230ebd3ff1SAnirudh Venkataramanan /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 13240ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_S 0x4 13250ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 13260ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_ACTIVE 0 13270ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_SUSPENDED 1 13280ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_FLUSHED 3 13290ebd3ff1SAnirudh Venkataramanan /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 13300ebd3ff1SAnirudh Venkataramanan * and in the LLDP MIB Change Event (0x0A01). They are valid for the 13310ebd3ff1SAnirudh Venkataramanan * Get LLDP MIB (0x0A00) response only. 13320ebd3ff1SAnirudh Venkataramanan */ 13330ebd3ff1SAnirudh Venkataramanan u8 reserved1; 13340ebd3ff1SAnirudh Venkataramanan __le16 local_len; 13350ebd3ff1SAnirudh Venkataramanan __le16 remote_len; 13360ebd3ff1SAnirudh Venkataramanan u8 reserved2[2]; 13370ebd3ff1SAnirudh Venkataramanan __le32 addr_high; 13380ebd3ff1SAnirudh Venkataramanan __le32 addr_low; 13390ebd3ff1SAnirudh Venkataramanan }; 13400ebd3ff1SAnirudh Venkataramanan 13410ebd3ff1SAnirudh Venkataramanan /* Configure LLDP MIB Change Event (direct 0x0A01) */ 13420ebd3ff1SAnirudh Venkataramanan /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 13430ebd3ff1SAnirudh Venkataramanan struct ice_aqc_lldp_set_mib_change { 13440ebd3ff1SAnirudh Venkataramanan u8 command; 13450ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 13460ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 13470ebd3ff1SAnirudh Venkataramanan u8 reserved[15]; 13480ebd3ff1SAnirudh Venkataramanan }; 13490ebd3ff1SAnirudh Venkataramanan 13503a257a14SAnirudh Venkataramanan /* Stop LLDP (direct 0x0A05) */ 13513a257a14SAnirudh Venkataramanan struct ice_aqc_lldp_stop { 13523a257a14SAnirudh Venkataramanan u8 command; 13533a257a14SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 13543a257a14SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_STOP 0x0 13553a257a14SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 13563a257a14SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 13573a257a14SAnirudh Venkataramanan u8 reserved[15]; 13583a257a14SAnirudh Venkataramanan }; 13593a257a14SAnirudh Venkataramanan 136037b6f646SAnirudh Venkataramanan /* Start LLDP (direct 0x0A06) */ 136137b6f646SAnirudh Venkataramanan struct ice_aqc_lldp_start { 136237b6f646SAnirudh Venkataramanan u8 command; 136337b6f646SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_START BIT(0) 136437b6f646SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 136537b6f646SAnirudh Venkataramanan u8 reserved[15]; 136637b6f646SAnirudh Venkataramanan }; 136737b6f646SAnirudh Venkataramanan 13680ebd3ff1SAnirudh Venkataramanan /* Get CEE DCBX Oper Config (0x0A07) 13690ebd3ff1SAnirudh Venkataramanan * The command uses the generic descriptor struct and 13700ebd3ff1SAnirudh Venkataramanan * returns the struct below as an indirect response. 13710ebd3ff1SAnirudh Venkataramanan */ 13720ebd3ff1SAnirudh Venkataramanan struct ice_aqc_get_cee_dcb_cfg_resp { 13730ebd3ff1SAnirudh Venkataramanan u8 oper_num_tc; 13740ebd3ff1SAnirudh Venkataramanan u8 oper_prio_tc[4]; 13750ebd3ff1SAnirudh Venkataramanan u8 oper_tc_bw[8]; 13760ebd3ff1SAnirudh Venkataramanan u8 oper_pfc_en; 13770ebd3ff1SAnirudh Venkataramanan __le16 oper_app_prio; 13780ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_FCOE_S 0 13790ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 13800ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_ISCSI_S 3 13810ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 13820ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_FIP_S 8 13830ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 13840ebd3ff1SAnirudh Venkataramanan __le32 tlv_status; 13850ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_PG_STATUS_S 0 13860ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 13870ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_PFC_STATUS_S 3 13880ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 13890ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_FCOE_STATUS_S 8 13900ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 13910ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_ISCSI_STATUS_S 11 13920ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 13930ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_FIP_STATUS_S 16 13940ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 13950ebd3ff1SAnirudh Venkataramanan u8 reserved[12]; 13960ebd3ff1SAnirudh Venkataramanan }; 13970ebd3ff1SAnirudh Venkataramanan 13987b9ffc76SAnirudh Venkataramanan /* Set Local LLDP MIB (indirect 0x0A08) 13992f2da36eSAnirudh Venkataramanan * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 14007b9ffc76SAnirudh Venkataramanan */ 14017b9ffc76SAnirudh Venkataramanan struct ice_aqc_lldp_set_local_mib { 14027b9ffc76SAnirudh Venkataramanan u8 type; 14037b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 14047b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 14057b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 14067b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 14077b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 14087b9ffc76SAnirudh Venkataramanan u8 reserved0; 14097b9ffc76SAnirudh Venkataramanan __le16 length; 14107b9ffc76SAnirudh Venkataramanan u8 reserved1[4]; 14117b9ffc76SAnirudh Venkataramanan __le32 addr_high; 14127b9ffc76SAnirudh Venkataramanan __le32 addr_low; 14137b9ffc76SAnirudh Venkataramanan }; 14147b9ffc76SAnirudh Venkataramanan 141537b6f646SAnirudh Venkataramanan /* Stop/Start LLDP Agent (direct 0x0A09) 14162f2da36eSAnirudh Venkataramanan * Used for stopping/starting specific LLDP agent. e.g. DCBX. 141737b6f646SAnirudh Venkataramanan * The same structure is used for the response, with the command field 141837b6f646SAnirudh Venkataramanan * being used as the status field. 141937b6f646SAnirudh Venkataramanan */ 142037b6f646SAnirudh Venkataramanan struct ice_aqc_lldp_stop_start_specific_agent { 142137b6f646SAnirudh Venkataramanan u8 command; 142237b6f646SAnirudh Venkataramanan #define ICE_AQC_START_STOP_AGENT_M BIT(0) 142337b6f646SAnirudh Venkataramanan #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 142437b6f646SAnirudh Venkataramanan #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 142537b6f646SAnirudh Venkataramanan u8 reserved[15]; 142637b6f646SAnirudh Venkataramanan }; 142737b6f646SAnirudh Venkataramanan 1428d76a60baSAnirudh Venkataramanan /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1429d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_key { 1430d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1431d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1432d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1433d76a60baSAnirudh Venkataramanan __le16 vsi_id; 1434d76a60baSAnirudh Venkataramanan u8 reserved[6]; 1435d76a60baSAnirudh Venkataramanan __le32 addr_high; 1436d76a60baSAnirudh Venkataramanan __le32 addr_low; 1437d76a60baSAnirudh Venkataramanan }; 1438d76a60baSAnirudh Venkataramanan 1439d76a60baSAnirudh Venkataramanan #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1440d76a60baSAnirudh Venkataramanan #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1441b4b418b3SPaul Greenwalt #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1442b4b418b3SPaul Greenwalt (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1443b4b418b3SPaul Greenwalt ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1444d76a60baSAnirudh Venkataramanan 1445d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_keys { 1446d76a60baSAnirudh Venkataramanan u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1447d76a60baSAnirudh Venkataramanan u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1448d76a60baSAnirudh Venkataramanan }; 1449d76a60baSAnirudh Venkataramanan 1450d76a60baSAnirudh Venkataramanan /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1451d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_lut { 1452d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1453d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1454d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1455d76a60baSAnirudh Venkataramanan __le16 vsi_id; 1456d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1457d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1458d76a60baSAnirudh Venkataramanan (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1459d76a60baSAnirudh Venkataramanan 1460d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1461d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1462d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1463d76a60baSAnirudh Venkataramanan 1464d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1465d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1466d76a60baSAnirudh Venkataramanan (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1467d76a60baSAnirudh Venkataramanan 1468d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1469d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1470d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1471d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1472d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1473d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1474d76a60baSAnirudh Venkataramanan 1475d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1476d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1477d76a60baSAnirudh Venkataramanan (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1478d76a60baSAnirudh Venkataramanan 1479d76a60baSAnirudh Venkataramanan __le16 flags; 1480d76a60baSAnirudh Venkataramanan __le32 reserved; 1481d76a60baSAnirudh Venkataramanan __le32 addr_high; 1482d76a60baSAnirudh Venkataramanan __le32 addr_low; 1483d76a60baSAnirudh Venkataramanan }; 1484d76a60baSAnirudh Venkataramanan 1485f9867df6SAnirudh Venkataramanan /* Add Tx LAN Queues (indirect 0x0C30) */ 1486cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs { 1487cdedef59SAnirudh Venkataramanan u8 num_qgrps; 1488cdedef59SAnirudh Venkataramanan u8 reserved[3]; 1489cdedef59SAnirudh Venkataramanan __le32 reserved1; 1490cdedef59SAnirudh Venkataramanan __le32 addr_high; 1491cdedef59SAnirudh Venkataramanan __le32 addr_low; 1492cdedef59SAnirudh Venkataramanan }; 1493cdedef59SAnirudh Venkataramanan 1494f9867df6SAnirudh Venkataramanan /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1495cdedef59SAnirudh Venkataramanan * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1496cdedef59SAnirudh Venkataramanan */ 1497cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs_perq { 1498cdedef59SAnirudh Venkataramanan __le16 txq_id; 1499cdedef59SAnirudh Venkataramanan u8 rsvd[2]; 1500cdedef59SAnirudh Venkataramanan __le32 q_teid; 1501cdedef59SAnirudh Venkataramanan u8 txq_ctx[22]; 1502cdedef59SAnirudh Venkataramanan u8 rsvd2[2]; 1503cdedef59SAnirudh Venkataramanan struct ice_aqc_txsched_elem info; 1504cdedef59SAnirudh Venkataramanan }; 1505cdedef59SAnirudh Venkataramanan 1506f9867df6SAnirudh Venkataramanan /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 1507cdedef59SAnirudh Venkataramanan * is an array of the following structs. Please note that the length of 1508cdedef59SAnirudh Venkataramanan * each struct ice_aqc_add_tx_qgrp is variable due 1509cdedef59SAnirudh Venkataramanan * to the variable number of queues in each group! 1510cdedef59SAnirudh Venkataramanan */ 1511cdedef59SAnirudh Venkataramanan struct ice_aqc_add_tx_qgrp { 1512cdedef59SAnirudh Venkataramanan __le32 parent_teid; 1513cdedef59SAnirudh Venkataramanan u8 num_txqs; 1514cdedef59SAnirudh Venkataramanan u8 rsvd[3]; 151566486d89SBruce Allan struct ice_aqc_add_txqs_perq txqs[]; 1516cdedef59SAnirudh Venkataramanan }; 1517cdedef59SAnirudh Venkataramanan 1518f9867df6SAnirudh Venkataramanan /* Disable Tx LAN Queues (indirect 0x0C31) */ 1519cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txqs { 1520cdedef59SAnirudh Venkataramanan u8 cmd_type; 1521cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_S 0 1522cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1523cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1524cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1525cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1526cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1527cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1528cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1529cdedef59SAnirudh Venkataramanan u8 num_entries; 1530cdedef59SAnirudh Venkataramanan __le16 vmvf_and_timeout; 1531cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1532cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1533cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1534cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1535cdedef59SAnirudh Venkataramanan __le32 blocked_cgds; 1536cdedef59SAnirudh Venkataramanan __le32 addr_high; 1537cdedef59SAnirudh Venkataramanan __le32 addr_low; 1538cdedef59SAnirudh Venkataramanan }; 1539cdedef59SAnirudh Venkataramanan 1540f9867df6SAnirudh Venkataramanan /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 1541cdedef59SAnirudh Venkataramanan * contains the following structures, arrayed one after the 1542cdedef59SAnirudh Venkataramanan * other. 1543cdedef59SAnirudh Venkataramanan * Note: Since the q_id is 16 bits wide, if the 1544cdedef59SAnirudh Venkataramanan * number of queues is even, then 2 bytes of alignment MUST be 1545cdedef59SAnirudh Venkataramanan * added before the start of the next group, to allow correct 1546cdedef59SAnirudh Venkataramanan * alignment of the parent_teid field. 1547cdedef59SAnirudh Venkataramanan */ 1548cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txq_item { 1549cdedef59SAnirudh Venkataramanan __le32 parent_teid; 1550cdedef59SAnirudh Venkataramanan u8 num_qs; 1551cdedef59SAnirudh Venkataramanan u8 rsvd; 1552cdedef59SAnirudh Venkataramanan /* The length of the q_id array varies according to num_qs */ 1553cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1554cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1555cdedef59SAnirudh Venkataramanan (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1556cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1557cdedef59SAnirudh Venkataramanan (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 155866486d89SBruce Allan __le16 q_id[]; 155966486d89SBruce Allan } __packed; 1560cdedef59SAnirudh Venkataramanan 15618b97ceb1SHieu Tran /* Configure Firmware Logging Command (indirect 0xFF09) 15628b97ceb1SHieu Tran * Logging Information Read Response (indirect 0xFF10) 15638b97ceb1SHieu Tran * Note: The 0xFF10 command has no input parameters. 15648b97ceb1SHieu Tran */ 15658b97ceb1SHieu Tran struct ice_aqc_fw_logging { 15668b97ceb1SHieu Tran u8 log_ctrl; 15678b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 15688b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_UART_EN BIT(1) 15698b97ceb1SHieu Tran u8 rsvd0; 15708b97ceb1SHieu Tran u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 15718b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 15728b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 15738b97ceb1SHieu Tran u8 rsvd1[5]; 15748b97ceb1SHieu Tran __le32 addr_high; 15758b97ceb1SHieu Tran __le32 addr_low; 15768b97ceb1SHieu Tran }; 15778b97ceb1SHieu Tran 15788b97ceb1SHieu Tran enum ice_aqc_fw_logging_mod { 15798b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_GENERAL = 0, 15808b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_CTRL, 15818b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_LINK, 15828b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_LINK_TOPO, 15838b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_DNL, 15848b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_I2C, 15858b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_SDP, 15868b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_MDIO, 15878b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_ADMINQ, 15888b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_HDMA, 15898b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_LLDP, 15908b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_DCBX, 15918b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_DCB, 15928b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_NETPROXY, 15938b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_NVM, 15948b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_AUTH, 15958b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_VPD, 15968b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_IOSF, 15978b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_PARSER, 15988b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_SW, 15998b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_SCHEDULER, 16008b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_TXQ, 16018b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_RSVD, 16028b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_POST, 16038b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_WATCHDOG, 16048b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 16058b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_MNG, 16068b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_MAX, 16078b97ceb1SHieu Tran }; 16088b97ceb1SHieu Tran 1609b3c38904SBruce Allan /* Defines for both above FW logging command/response buffers */ 16108b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_ID_S 0 16118b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 16128b97ceb1SHieu Tran 16138b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 16148b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 16158b97ceb1SHieu Tran 16168b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_EN_S 12 16178b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 16188b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 16198b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 16208b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 16218b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 16228b97ceb1SHieu Tran 16238b97ceb1SHieu Tran /* Get/Clear FW Log (indirect 0xFF11) */ 16248b97ceb1SHieu Tran struct ice_aqc_get_clear_fw_log { 16258b97ceb1SHieu Tran u8 flags; 16268b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_CLEAR BIT(0) 16278b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 16288b97ceb1SHieu Tran u8 rsvd1[7]; 16298b97ceb1SHieu Tran __le32 addr_high; 16308b97ceb1SHieu Tran __le32 addr_low; 16318b97ceb1SHieu Tran }; 16328b97ceb1SHieu Tran 1633c7648810STony Nguyen /* Download Package (indirect 0x0C40) */ 1634c7648810STony Nguyen /* Also used for Update Package (indirect 0x0C42) */ 1635c7648810STony Nguyen struct ice_aqc_download_pkg { 1636c7648810STony Nguyen u8 flags; 1637c7648810STony Nguyen #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 1638c7648810STony Nguyen u8 reserved[3]; 1639c7648810STony Nguyen __le32 reserved1; 1640c7648810STony Nguyen __le32 addr_high; 1641c7648810STony Nguyen __le32 addr_low; 1642c7648810STony Nguyen }; 1643c7648810STony Nguyen 1644c7648810STony Nguyen struct ice_aqc_download_pkg_resp { 1645c7648810STony Nguyen __le32 error_offset; 1646c7648810STony Nguyen __le32 error_info; 1647c7648810STony Nguyen __le32 addr_high; 1648c7648810STony Nguyen __le32 addr_low; 1649c7648810STony Nguyen }; 1650c7648810STony Nguyen 1651c7648810STony Nguyen /* Get Package Info List (indirect 0x0C43) */ 1652c7648810STony Nguyen struct ice_aqc_get_pkg_info_list { 1653c7648810STony Nguyen __le32 reserved1; 1654c7648810STony Nguyen __le32 reserved2; 1655c7648810STony Nguyen __le32 addr_high; 1656c7648810STony Nguyen __le32 addr_low; 1657c7648810STony Nguyen }; 1658c7648810STony Nguyen 1659c7648810STony Nguyen /* Version format for packages */ 1660c7648810STony Nguyen struct ice_pkg_ver { 1661c7648810STony Nguyen u8 major; 1662c7648810STony Nguyen u8 minor; 1663c7648810STony Nguyen u8 update; 1664c7648810STony Nguyen u8 draft; 1665c7648810STony Nguyen }; 1666c7648810STony Nguyen 1667c7648810STony Nguyen #define ICE_PKG_NAME_SIZE 32 1668b8272919SVictor Raj #define ICE_SEG_NAME_SIZE 28 1669c7648810STony Nguyen 1670c7648810STony Nguyen struct ice_aqc_get_pkg_info { 1671c7648810STony Nguyen struct ice_pkg_ver ver; 1672b8272919SVictor Raj char name[ICE_SEG_NAME_SIZE]; 1673b8272919SVictor Raj __le32 track_id; 1674c7648810STony Nguyen u8 is_in_nvm; 1675c7648810STony Nguyen u8 is_active; 1676c7648810STony Nguyen u8 is_active_at_boot; 1677c7648810STony Nguyen u8 is_modified; 1678c7648810STony Nguyen }; 1679c7648810STony Nguyen 1680c7648810STony Nguyen /* Get Package Info List response buffer format (0x0C43) */ 1681c7648810STony Nguyen struct ice_aqc_get_pkg_info_resp { 1682c7648810STony Nguyen __le32 count; 168366486d89SBruce Allan struct ice_aqc_get_pkg_info pkg_info[]; 1684c7648810STony Nguyen }; 16854ee656bbSTony Nguyen 16862309ae38SBrett Creeley /* Lan Queue Overflow Event (direct, 0x1001) */ 16872309ae38SBrett Creeley struct ice_aqc_event_lan_overflow { 16882309ae38SBrett Creeley __le32 prtdcb_ruptq; 16892309ae38SBrett Creeley __le32 qtx_ctl; 16902309ae38SBrett Creeley u8 reserved[8]; 16912309ae38SBrett Creeley }; 16922309ae38SBrett Creeley 16937ec59eeaSAnirudh Venkataramanan /** 16947ec59eeaSAnirudh Venkataramanan * struct ice_aq_desc - Admin Queue (AQ) descriptor 16957ec59eeaSAnirudh Venkataramanan * @flags: ICE_AQ_FLAG_* flags 16967ec59eeaSAnirudh Venkataramanan * @opcode: AQ command opcode 16977ec59eeaSAnirudh Venkataramanan * @datalen: length in bytes of indirect/external data buffer 16987ec59eeaSAnirudh Venkataramanan * @retval: return value from firmware 16997ec59eeaSAnirudh Venkataramanan * @cookie_h: opaque data high-half 17007ec59eeaSAnirudh Venkataramanan * @cookie_l: opaque data low-half 17017ec59eeaSAnirudh Venkataramanan * @params: command-specific parameters 17027ec59eeaSAnirudh Venkataramanan * 17037ec59eeaSAnirudh Venkataramanan * Descriptor format for commands the driver posts on the Admin Transmit Queue 17047ec59eeaSAnirudh Venkataramanan * (ATQ). The firmware writes back onto the command descriptor and returns 17057ec59eeaSAnirudh Venkataramanan * the result of the command. Asynchronous events that are not an immediate 17067ec59eeaSAnirudh Venkataramanan * result of the command are written to the Admin Receive Queue (ARQ) using 17077ec59eeaSAnirudh Venkataramanan * the same descriptor format. Descriptors are in little-endian notation with 17087ec59eeaSAnirudh Venkataramanan * 32-bit words. 17097ec59eeaSAnirudh Venkataramanan */ 17107ec59eeaSAnirudh Venkataramanan struct ice_aq_desc { 17117ec59eeaSAnirudh Venkataramanan __le16 flags; 17127ec59eeaSAnirudh Venkataramanan __le16 opcode; 17137ec59eeaSAnirudh Venkataramanan __le16 datalen; 17147ec59eeaSAnirudh Venkataramanan __le16 retval; 17157ec59eeaSAnirudh Venkataramanan __le32 cookie_high; 17167ec59eeaSAnirudh Venkataramanan __le32 cookie_low; 17177ec59eeaSAnirudh Venkataramanan union { 17187ec59eeaSAnirudh Venkataramanan u8 raw[16]; 17197ec59eeaSAnirudh Venkataramanan struct ice_aqc_generic generic; 17207ec59eeaSAnirudh Venkataramanan struct ice_aqc_get_ver get_ver; 1721e3710a01SPaul M Stillwell Jr struct ice_aqc_driver_ver driver_ver; 17227ec59eeaSAnirudh Venkataramanan struct ice_aqc_q_shutdown q_shutdown; 1723f31e4b6fSAnirudh Venkataramanan struct ice_aqc_req_res res_owner; 1724dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read mac_read; 1725e94d4478SAnirudh Venkataramanan struct ice_aqc_manage_mac_write mac_write; 1726f31e4b6fSAnirudh Venkataramanan struct ice_aqc_clear_pxe clear_pxe; 17279c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps get_cap; 1728dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps get_phy; 1729fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg set_phy; 1730fcea6f3dSAnirudh Venkataramanan struct ice_aqc_restart_an restart_an; 1731a012dca9SScott W Taylor struct ice_aqc_sff_eeprom read_write_sff_param; 17328e151d50SAnirudh Venkataramanan struct ice_aqc_set_port_id_led set_port_id_led; 17339c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg get_sw_conf; 17349daf8208SAnirudh Venkataramanan struct ice_aqc_sw_rules sw_rules; 1735dc49c772SAnirudh Venkataramanan struct ice_aqc_get_topo get_topo; 17361f9c7840SAnirudh Venkataramanan struct ice_aqc_sched_elem_cmd sched_elem_cmd; 17379c20346bSAnirudh Venkataramanan struct ice_aqc_query_txsched_res query_sched_res; 17387b9ffc76SAnirudh Venkataramanan struct ice_aqc_query_port_ets port_ets; 17391ddef455SUsha Ketineni struct ice_aqc_rl_profile rl_profile; 1740f31e4b6fSAnirudh Venkataramanan struct ice_aqc_nvm nvm; 17410e674aebSAnirudh Venkataramanan struct ice_aqc_nvm_checksum nvm_checksum; 1742007676b4SAnirudh Venkataramanan struct ice_aqc_pf_vf_msg virt; 17430ebd3ff1SAnirudh Venkataramanan struct ice_aqc_lldp_get_mib lldp_get_mib; 17440ebd3ff1SAnirudh Venkataramanan struct ice_aqc_lldp_set_mib_change lldp_set_event; 17453a257a14SAnirudh Venkataramanan struct ice_aqc_lldp_stop lldp_stop; 174637b6f646SAnirudh Venkataramanan struct ice_aqc_lldp_start lldp_start; 17477b9ffc76SAnirudh Venkataramanan struct ice_aqc_lldp_set_local_mib lldp_set_mib; 174837b6f646SAnirudh Venkataramanan struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 1749d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_lut get_set_rss_lut; 1750d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_key get_set_rss_key; 1751cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs add_txqs; 1752cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txqs dis_txqs; 17533a858ba3SAnirudh Venkataramanan struct ice_aqc_add_get_update_free_vsi vsi_cmd; 17540f9d5027SAnirudh Venkataramanan struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 17558b97ceb1SHieu Tran struct ice_aqc_fw_logging fw_logging; 17568b97ceb1SHieu Tran struct ice_aqc_get_clear_fw_log get_clear_fw_log; 1757c7648810STony Nguyen struct ice_aqc_download_pkg download_pkg; 17580e674aebSAnirudh Venkataramanan struct ice_aqc_set_mac_lb set_mac_lb; 17599daf8208SAnirudh Venkataramanan struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 176042449105SAnirudh Venkataramanan struct ice_aqc_set_mac_cfg set_mac_cfg; 17610b28b702SAnirudh Venkataramanan struct ice_aqc_set_event_mask set_event_mask; 1762dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status get_link_status; 17632309ae38SBrett Creeley struct ice_aqc_event_lan_overflow lan_overflow; 17647ec59eeaSAnirudh Venkataramanan } params; 17657ec59eeaSAnirudh Venkataramanan }; 17667ec59eeaSAnirudh Venkataramanan 17677ec59eeaSAnirudh Venkataramanan /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 17687ec59eeaSAnirudh Venkataramanan #define ICE_AQ_LG_BUF 512 17697ec59eeaSAnirudh Venkataramanan 1770940b61afSAnirudh Venkataramanan #define ICE_AQ_FLAG_ERR_S 2 17717ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_LB_S 9 17729c20346bSAnirudh Venkataramanan #define ICE_AQ_FLAG_RD_S 10 17737ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_BUF_S 12 17747ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_SI_S 13 17757ec59eeaSAnirudh Venkataramanan 1776940b61afSAnirudh Venkataramanan #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 17777ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 17789c20346bSAnirudh Venkataramanan #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 17797ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 17807ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 17817ec59eeaSAnirudh Venkataramanan 17827ec59eeaSAnirudh Venkataramanan /* error codes */ 17837ec59eeaSAnirudh Venkataramanan enum ice_aq_err { 1784df17b7e0SAnirudh Venkataramanan ICE_AQ_RC_OK = 0, /* Success */ 17850ebd3ff1SAnirudh Venkataramanan ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 17860ebd3ff1SAnirudh Venkataramanan ICE_AQ_RC_ENOENT = 2, /* No such element */ 17879c20346bSAnirudh Venkataramanan ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 1788f31e4b6fSAnirudh Venkataramanan ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1789df17b7e0SAnirudh Venkataramanan ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 179081f07491SJacob Keller ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 1791e94d4478SAnirudh Venkataramanan ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 179290e47737SMitch Williams ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 1793b5e19a64SChinh T Cao ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 1794c7648810STony Nguyen ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 1795c7648810STony Nguyen ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 1796c7648810STony Nguyen ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 1797c7648810STony Nguyen ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 1798c7648810STony Nguyen ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 17997ec59eeaSAnirudh Venkataramanan }; 18007ec59eeaSAnirudh Venkataramanan 18017ec59eeaSAnirudh Venkataramanan /* Admin Queue command opcodes */ 18027ec59eeaSAnirudh Venkataramanan enum ice_adminq_opc { 18037ec59eeaSAnirudh Venkataramanan /* AQ commands */ 18047ec59eeaSAnirudh Venkataramanan ice_aqc_opc_get_ver = 0x0001, 1805e3710a01SPaul M Stillwell Jr ice_aqc_opc_driver_ver = 0x0002, 18067ec59eeaSAnirudh Venkataramanan ice_aqc_opc_q_shutdown = 0x0003, 1807f31e4b6fSAnirudh Venkataramanan 1808f31e4b6fSAnirudh Venkataramanan /* resource ownership */ 1809f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_req_res = 0x0008, 1810f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_release_res = 0x0009, 1811f31e4b6fSAnirudh Venkataramanan 18129c20346bSAnirudh Venkataramanan /* device/function capabilities */ 18139c20346bSAnirudh Venkataramanan ice_aqc_opc_list_func_caps = 0x000A, 18149c20346bSAnirudh Venkataramanan ice_aqc_opc_list_dev_caps = 0x000B, 18159c20346bSAnirudh Venkataramanan 1816dc49c772SAnirudh Venkataramanan /* manage MAC address */ 1817dc49c772SAnirudh Venkataramanan ice_aqc_opc_manage_mac_read = 0x0107, 1818e94d4478SAnirudh Venkataramanan ice_aqc_opc_manage_mac_write = 0x0108, 1819dc49c772SAnirudh Venkataramanan 1820f31e4b6fSAnirudh Venkataramanan /* PXE */ 1821f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_clear_pxe_mode = 0x0110, 1822f31e4b6fSAnirudh Venkataramanan 18239c20346bSAnirudh Venkataramanan /* internal switch commands */ 18249c20346bSAnirudh Venkataramanan ice_aqc_opc_get_sw_cfg = 0x0200, 18259c20346bSAnirudh Venkataramanan 18269daf8208SAnirudh Venkataramanan /* Alloc/Free/Get Resources */ 18279daf8208SAnirudh Venkataramanan ice_aqc_opc_alloc_res = 0x0208, 18289daf8208SAnirudh Venkataramanan ice_aqc_opc_free_res = 0x0209, 18299daf8208SAnirudh Venkataramanan 18303a858ba3SAnirudh Venkataramanan /* VSI commands */ 18313a858ba3SAnirudh Venkataramanan ice_aqc_opc_add_vsi = 0x0210, 18323a858ba3SAnirudh Venkataramanan ice_aqc_opc_update_vsi = 0x0211, 18333a858ba3SAnirudh Venkataramanan ice_aqc_opc_free_vsi = 0x0213, 18349daf8208SAnirudh Venkataramanan 18359daf8208SAnirudh Venkataramanan /* switch rules population commands */ 18369daf8208SAnirudh Venkataramanan ice_aqc_opc_add_sw_rules = 0x02A0, 18379daf8208SAnirudh Venkataramanan ice_aqc_opc_update_sw_rules = 0x02A1, 18389daf8208SAnirudh Venkataramanan ice_aqc_opc_remove_sw_rules = 0x02A2, 18399daf8208SAnirudh Venkataramanan 1840f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_clear_pf_cfg = 0x02A4, 1841f31e4b6fSAnirudh Venkataramanan 18429c20346bSAnirudh Venkataramanan /* transmit scheduler commands */ 1843dc49c772SAnirudh Venkataramanan ice_aqc_opc_get_dflt_topo = 0x0400, 18445513b920SAnirudh Venkataramanan ice_aqc_opc_add_sched_elems = 0x0401, 18451ddef455SUsha Ketineni ice_aqc_opc_cfg_sched_elems = 0x0403, 184656daee6cSAnirudh Venkataramanan ice_aqc_opc_get_sched_elems = 0x0404, 18475513b920SAnirudh Venkataramanan ice_aqc_opc_suspend_sched_elems = 0x0409, 18485513b920SAnirudh Venkataramanan ice_aqc_opc_resume_sched_elems = 0x040A, 18497b9ffc76SAnirudh Venkataramanan ice_aqc_opc_query_port_ets = 0x040E, 18509c20346bSAnirudh Venkataramanan ice_aqc_opc_delete_sched_elems = 0x040F, 18511ddef455SUsha Ketineni ice_aqc_opc_add_rl_profiles = 0x0410, 18529c20346bSAnirudh Venkataramanan ice_aqc_opc_query_sched_res = 0x0412, 18531ddef455SUsha Ketineni ice_aqc_opc_remove_rl_profiles = 0x0415, 18549c20346bSAnirudh Venkataramanan 1855dc49c772SAnirudh Venkataramanan /* PHY commands */ 1856dc49c772SAnirudh Venkataramanan ice_aqc_opc_get_phy_caps = 0x0600, 1857fcea6f3dSAnirudh Venkataramanan ice_aqc_opc_set_phy_cfg = 0x0601, 185842449105SAnirudh Venkataramanan ice_aqc_opc_set_mac_cfg = 0x0603, 1859fcea6f3dSAnirudh Venkataramanan ice_aqc_opc_restart_an = 0x0605, 1860dc49c772SAnirudh Venkataramanan ice_aqc_opc_get_link_status = 0x0607, 18610b28b702SAnirudh Venkataramanan ice_aqc_opc_set_event_mask = 0x0613, 18620e674aebSAnirudh Venkataramanan ice_aqc_opc_set_mac_lb = 0x0620, 18638e151d50SAnirudh Venkataramanan ice_aqc_opc_set_port_id_led = 0x06E9, 1864a012dca9SScott W Taylor ice_aqc_opc_sff_eeprom = 0x06EE, 1865dc49c772SAnirudh Venkataramanan 1866f31e4b6fSAnirudh Venkataramanan /* NVM commands */ 1867f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_nvm_read = 0x0701, 18680e674aebSAnirudh Venkataramanan ice_aqc_opc_nvm_checksum = 0x0706, 1869f31e4b6fSAnirudh Venkataramanan 1870007676b4SAnirudh Venkataramanan /* PF/VF mailbox commands */ 18711071a835SAnirudh Venkataramanan ice_mbx_opc_send_msg_to_pf = 0x0801, 1872007676b4SAnirudh Venkataramanan ice_mbx_opc_send_msg_to_vf = 0x0802, 187337b6f646SAnirudh Venkataramanan /* LLDP commands */ 18740ebd3ff1SAnirudh Venkataramanan ice_aqc_opc_lldp_get_mib = 0x0A00, 18750ebd3ff1SAnirudh Venkataramanan ice_aqc_opc_lldp_set_mib_change = 0x0A01, 18763a257a14SAnirudh Venkataramanan ice_aqc_opc_lldp_stop = 0x0A05, 187737b6f646SAnirudh Venkataramanan ice_aqc_opc_lldp_start = 0x0A06, 18780ebd3ff1SAnirudh Venkataramanan ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 18797b9ffc76SAnirudh Venkataramanan ice_aqc_opc_lldp_set_local_mib = 0x0A08, 188037b6f646SAnirudh Venkataramanan ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 1881007676b4SAnirudh Venkataramanan 1882d76a60baSAnirudh Venkataramanan /* RSS commands */ 1883d76a60baSAnirudh Venkataramanan ice_aqc_opc_set_rss_key = 0x0B02, 1884d76a60baSAnirudh Venkataramanan ice_aqc_opc_set_rss_lut = 0x0B03, 1885d76a60baSAnirudh Venkataramanan ice_aqc_opc_get_rss_key = 0x0B04, 1886d76a60baSAnirudh Venkataramanan ice_aqc_opc_get_rss_lut = 0x0B05, 1887d76a60baSAnirudh Venkataramanan 1888f9867df6SAnirudh Venkataramanan /* Tx queue handling commands/events */ 1889cdedef59SAnirudh Venkataramanan ice_aqc_opc_add_txqs = 0x0C30, 1890cdedef59SAnirudh Venkataramanan ice_aqc_opc_dis_txqs = 0x0C31, 18918b97ceb1SHieu Tran 1892c7648810STony Nguyen /* package commands */ 1893c7648810STony Nguyen ice_aqc_opc_download_pkg = 0x0C40, 189443dbfc7bSTony Nguyen ice_aqc_opc_update_pkg = 0x0C42, 1895c7648810STony Nguyen ice_aqc_opc_get_pkg_info_list = 0x0C43, 1896c7648810STony Nguyen 18972309ae38SBrett Creeley /* Standalone Commands/Events */ 18982309ae38SBrett Creeley ice_aqc_opc_event_lan_overflow = 0x1001, 18992309ae38SBrett Creeley 19008b97ceb1SHieu Tran /* debug commands */ 19018b97ceb1SHieu Tran ice_aqc_opc_fw_logging = 0xFF09, 190211fe1b3aSDan Nowlin ice_aqc_opc_fw_logging_info = 0xFF10, 19037ec59eeaSAnirudh Venkataramanan }; 19047ec59eeaSAnirudh Venkataramanan 19057ec59eeaSAnirudh Venkataramanan #endif /* _ICE_ADMINQ_CMD_H_ */ 1906