17ec59eeaSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 27ec59eeaSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 37ec59eeaSAnirudh Venkataramanan 47ec59eeaSAnirudh Venkataramanan #ifndef _ICE_ADMINQ_CMD_H_ 57ec59eeaSAnirudh Venkataramanan #define _ICE_ADMINQ_CMD_H_ 67ec59eeaSAnirudh Venkataramanan 77ec59eeaSAnirudh Venkataramanan /* This header file defines the Admin Queue commands, error codes and 87ec59eeaSAnirudh Venkataramanan * descriptor format. It is shared between Firmware and Software. 97ec59eeaSAnirudh Venkataramanan */ 107ec59eeaSAnirudh Venkataramanan 119daf8208SAnirudh Venkataramanan #define ICE_MAX_VSI 768 129c20346bSAnirudh Venkataramanan #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 133a858ba3SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 149c20346bSAnirudh Venkataramanan 157ec59eeaSAnirudh Venkataramanan struct ice_aqc_generic { 167ec59eeaSAnirudh Venkataramanan __le32 param0; 177ec59eeaSAnirudh Venkataramanan __le32 param1; 187ec59eeaSAnirudh Venkataramanan __le32 addr_high; 197ec59eeaSAnirudh Venkataramanan __le32 addr_low; 207ec59eeaSAnirudh Venkataramanan }; 217ec59eeaSAnirudh Venkataramanan 227ec59eeaSAnirudh Venkataramanan /* Get version (direct 0x0001) */ 237ec59eeaSAnirudh Venkataramanan struct ice_aqc_get_ver { 247ec59eeaSAnirudh Venkataramanan __le32 rom_ver; 257ec59eeaSAnirudh Venkataramanan __le32 fw_build; 267ec59eeaSAnirudh Venkataramanan u8 fw_branch; 277ec59eeaSAnirudh Venkataramanan u8 fw_major; 287ec59eeaSAnirudh Venkataramanan u8 fw_minor; 297ec59eeaSAnirudh Venkataramanan u8 fw_patch; 307ec59eeaSAnirudh Venkataramanan u8 api_branch; 317ec59eeaSAnirudh Venkataramanan u8 api_major; 327ec59eeaSAnirudh Venkataramanan u8 api_minor; 337ec59eeaSAnirudh Venkataramanan u8 api_patch; 347ec59eeaSAnirudh Venkataramanan }; 357ec59eeaSAnirudh Venkataramanan 367ec59eeaSAnirudh Venkataramanan /* Queue Shutdown (direct 0x0003) */ 377ec59eeaSAnirudh Venkataramanan struct ice_aqc_q_shutdown { 387ec59eeaSAnirudh Venkataramanan __le32 driver_unloading; 3949c6e41bSAnirudh Venkataramanan #define ICE_AQC_DRIVER_UNLOADING BIT(0) 407ec59eeaSAnirudh Venkataramanan u8 reserved[12]; 417ec59eeaSAnirudh Venkataramanan }; 427ec59eeaSAnirudh Venkataramanan 43f31e4b6fSAnirudh Venkataramanan /* Request resource ownership (direct 0x0008) 44f31e4b6fSAnirudh Venkataramanan * Release resource ownership (direct 0x0009) 45f31e4b6fSAnirudh Venkataramanan */ 46f31e4b6fSAnirudh Venkataramanan struct ice_aqc_req_res { 47f31e4b6fSAnirudh Venkataramanan __le16 res_id; 48f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_NVM 1 49f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_SDP 2 50f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_CHNG_LOCK 3 51f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_GLBL_LOCK 4 52f31e4b6fSAnirudh Venkataramanan __le16 access_type; 53f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ACCESS_READ 1 54f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ACCESS_WRITE 2 55f31e4b6fSAnirudh Venkataramanan 56f31e4b6fSAnirudh Venkataramanan /* Upon successful completion, FW writes this value and driver is 57f31e4b6fSAnirudh Venkataramanan * expected to release resource before timeout. This value is provided 58f31e4b6fSAnirudh Venkataramanan * in milliseconds. 59f31e4b6fSAnirudh Venkataramanan */ 60f31e4b6fSAnirudh Venkataramanan __le32 timeout; 61f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 62f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 63f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 64f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 65f9867df6SAnirudh Venkataramanan /* For SDP: pin ID of the SDP */ 66f31e4b6fSAnirudh Venkataramanan __le32 res_number; 67f31e4b6fSAnirudh Venkataramanan /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 68f31e4b6fSAnirudh Venkataramanan __le16 status; 69f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_SUCCESS 0 70f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_IN_PROG 1 71f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_DONE 2 72f31e4b6fSAnirudh Venkataramanan u8 reserved[2]; 73f31e4b6fSAnirudh Venkataramanan }; 74f31e4b6fSAnirudh Venkataramanan 759c20346bSAnirudh Venkataramanan /* Get function capabilities (indirect 0x000A) 769c20346bSAnirudh Venkataramanan * Get device capabilities (indirect 0x000B) 779c20346bSAnirudh Venkataramanan */ 789c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps { 799c20346bSAnirudh Venkataramanan u8 cmd_flags; 809c20346bSAnirudh Venkataramanan u8 pf_index; 819c20346bSAnirudh Venkataramanan u8 reserved[2]; 829c20346bSAnirudh Venkataramanan __le32 count; 839c20346bSAnirudh Venkataramanan __le32 addr_high; 849c20346bSAnirudh Venkataramanan __le32 addr_low; 859c20346bSAnirudh Venkataramanan }; 869c20346bSAnirudh Venkataramanan 879c20346bSAnirudh Venkataramanan /* Device/Function buffer entry, repeated per reported capability */ 889c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps_elem { 899c20346bSAnirudh Venkataramanan __le16 cap; 90995c90f2SAnirudh Venkataramanan #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 9175d2b253SAnirudh Venkataramanan #define ICE_AQC_CAPS_SRIOV 0x0012 9275d2b253SAnirudh Venkataramanan #define ICE_AQC_CAPS_VF 0x0013 939c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_VSI 0x0017 949c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_RSS 0x0040 959c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_RXQS 0x0041 969c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_TXQS 0x0042 979c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_MSIX 0x0043 989c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_MAX_MTU 0x0047 999c20346bSAnirudh Venkataramanan 1009c20346bSAnirudh Venkataramanan u8 major_ver; 1019c20346bSAnirudh Venkataramanan u8 minor_ver; 1029c20346bSAnirudh Venkataramanan /* Number of resources described by this capability */ 1039c20346bSAnirudh Venkataramanan __le32 number; 1049c20346bSAnirudh Venkataramanan /* Only meaningful for some types of resources */ 1059c20346bSAnirudh Venkataramanan __le32 logical_id; 1069c20346bSAnirudh Venkataramanan /* Only meaningful for some types of resources */ 1079c20346bSAnirudh Venkataramanan __le32 phys_id; 1089c20346bSAnirudh Venkataramanan __le64 rsvd1; 1099c20346bSAnirudh Venkataramanan __le64 rsvd2; 1109c20346bSAnirudh Venkataramanan }; 1119c20346bSAnirudh Venkataramanan 112dc49c772SAnirudh Venkataramanan /* Manage MAC address, read command - indirect (0x0107) 113dc49c772SAnirudh Venkataramanan * This struct is also used for the response 114dc49c772SAnirudh Venkataramanan */ 115dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read { 116dc49c772SAnirudh Venkataramanan __le16 flags; /* Zeroed by device driver */ 117dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 118dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 119dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 120dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 121dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_READ_S 4 122dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 12362f4dafcSAnirudh Venkataramanan u8 rsvd[2]; 124dc49c772SAnirudh Venkataramanan u8 num_addr; /* Used in response */ 12562f4dafcSAnirudh Venkataramanan u8 rsvd1[3]; 126dc49c772SAnirudh Venkataramanan __le32 addr_high; 127dc49c772SAnirudh Venkataramanan __le32 addr_low; 128dc49c772SAnirudh Venkataramanan }; 129dc49c772SAnirudh Venkataramanan 130dc49c772SAnirudh Venkataramanan /* Response buffer format for manage MAC read command */ 131dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read_resp { 132dc49c772SAnirudh Venkataramanan u8 lport_num; 133dc49c772SAnirudh Venkataramanan u8 addr_type; 134dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 135dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 136dc49c772SAnirudh Venkataramanan u8 mac_addr[ETH_ALEN]; 137dc49c772SAnirudh Venkataramanan }; 138dc49c772SAnirudh Venkataramanan 139e94d4478SAnirudh Venkataramanan /* Manage MAC address, write command - direct (0x0108) */ 140e94d4478SAnirudh Venkataramanan struct ice_aqc_manage_mac_write { 14162f4dafcSAnirudh Venkataramanan u8 rsvd; 142e94d4478SAnirudh Venkataramanan u8 flags; 143e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 144e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 145e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WR_S 6 146e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S) 147e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 148e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S) 149e94d4478SAnirudh Venkataramanan /* High 16 bits of MAC address in big endian order */ 150e94d4478SAnirudh Venkataramanan __be16 sah; 151e94d4478SAnirudh Venkataramanan /* Low 32 bits of MAC address in big endian order */ 152e94d4478SAnirudh Venkataramanan __be32 sal; 153e94d4478SAnirudh Venkataramanan __le32 addr_high; 154e94d4478SAnirudh Venkataramanan __le32 addr_low; 155e94d4478SAnirudh Venkataramanan }; 156e94d4478SAnirudh Venkataramanan 157f31e4b6fSAnirudh Venkataramanan /* Clear PXE Command and response (direct 0x0110) */ 158f31e4b6fSAnirudh Venkataramanan struct ice_aqc_clear_pxe { 159f31e4b6fSAnirudh Venkataramanan u8 rx_cnt; 160f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 161f31e4b6fSAnirudh Venkataramanan u8 reserved[15]; 162f31e4b6fSAnirudh Venkataramanan }; 163f31e4b6fSAnirudh Venkataramanan 1649c20346bSAnirudh Venkataramanan /* Get switch configuration (0x0200) */ 1659c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg { 1669c20346bSAnirudh Venkataramanan /* Reserved for command and copy of request flags for response */ 1679c20346bSAnirudh Venkataramanan __le16 flags; 1689c20346bSAnirudh Venkataramanan /* First desc in case of command and next_elem in case of response 1699c20346bSAnirudh Venkataramanan * In case of response, if it is not zero, means all the configuration 1709c20346bSAnirudh Venkataramanan * was not returned and new command shall be sent with this value in 1719c20346bSAnirudh Venkataramanan * the 'first desc' field 1729c20346bSAnirudh Venkataramanan */ 1739c20346bSAnirudh Venkataramanan __le16 element; 1749c20346bSAnirudh Venkataramanan /* Reserved for command, only used for response */ 1759c20346bSAnirudh Venkataramanan __le16 num_elems; 1769c20346bSAnirudh Venkataramanan __le16 rsvd; 1779c20346bSAnirudh Venkataramanan __le32 addr_high; 1789c20346bSAnirudh Venkataramanan __le32 addr_low; 1799c20346bSAnirudh Venkataramanan }; 1809c20346bSAnirudh Venkataramanan 1819c20346bSAnirudh Venkataramanan /* Each entry in the response buffer is of the following type: */ 1829c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg_resp_elem { 1839c20346bSAnirudh Venkataramanan /* VSI/Port Number */ 1849c20346bSAnirudh Venkataramanan __le16 vsi_port_num; 1859c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 1869c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 1879c20346bSAnirudh Venkataramanan (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 1889c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 1899c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 1909c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 1919c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 1929c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 1939c20346bSAnirudh Venkataramanan 1949c20346bSAnirudh Venkataramanan /* SWID VSI/Port belongs to */ 1959c20346bSAnirudh Venkataramanan __le16 swid; 1969c20346bSAnirudh Venkataramanan 1979c20346bSAnirudh Venkataramanan /* Bit 14..0 : PF/VF number VSI belongs to 1989c20346bSAnirudh Venkataramanan * Bit 15 : VF indication bit 1999c20346bSAnirudh Venkataramanan */ 2009c20346bSAnirudh Venkataramanan __le16 pf_vf_num; 2019c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 2029c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 2039c20346bSAnirudh Venkataramanan (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 2049c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 2059c20346bSAnirudh Venkataramanan }; 2069c20346bSAnirudh Venkataramanan 2079c20346bSAnirudh Venkataramanan /* The response buffer is as follows. Note that the length of the 2089c20346bSAnirudh Venkataramanan * elements array varies with the length of the command response. 2099c20346bSAnirudh Venkataramanan */ 2109c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg_resp { 2119c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg_resp_elem elements[1]; 2129c20346bSAnirudh Venkataramanan }; 2139c20346bSAnirudh Venkataramanan 2149daf8208SAnirudh Venkataramanan /* These resource type defines are used for all switch resource 2159daf8208SAnirudh Venkataramanan * commands where a resource type is required, such as: 2169daf8208SAnirudh Venkataramanan * Get Resource Allocation command (indirect 0x0204) 2179daf8208SAnirudh Venkataramanan * Allocate Resources command (indirect 0x0208) 2189daf8208SAnirudh Venkataramanan * Free Resources command (indirect 0x0209) 2199daf8208SAnirudh Venkataramanan * Get Allocated Resource Descriptors Command (indirect 0x020A) 2209daf8208SAnirudh Venkataramanan */ 2219daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 2229daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 2239daf8208SAnirudh Venkataramanan 2249daf8208SAnirudh Venkataramanan /* Allocate Resources command (indirect 0x0208) 2259daf8208SAnirudh Venkataramanan * Free Resources command (indirect 0x0209) 2269daf8208SAnirudh Venkataramanan */ 2279daf8208SAnirudh Venkataramanan struct ice_aqc_alloc_free_res_cmd { 2289daf8208SAnirudh Venkataramanan __le16 num_entries; /* Number of Resource entries */ 2299daf8208SAnirudh Venkataramanan u8 reserved[6]; 2309daf8208SAnirudh Venkataramanan __le32 addr_high; 2319daf8208SAnirudh Venkataramanan __le32 addr_low; 2329daf8208SAnirudh Venkataramanan }; 2339daf8208SAnirudh Venkataramanan 2349daf8208SAnirudh Venkataramanan /* Resource descriptor */ 2359daf8208SAnirudh Venkataramanan struct ice_aqc_res_elem { 2369daf8208SAnirudh Venkataramanan union { 2379daf8208SAnirudh Venkataramanan __le16 sw_resp; 2389daf8208SAnirudh Venkataramanan __le16 flu_resp; 2399daf8208SAnirudh Venkataramanan } e; 2409daf8208SAnirudh Venkataramanan }; 2419daf8208SAnirudh Venkataramanan 2429daf8208SAnirudh Venkataramanan /* Buffer for Allocate/Free Resources commands */ 2439daf8208SAnirudh Venkataramanan struct ice_aqc_alloc_free_res_elem { 2449daf8208SAnirudh Venkataramanan __le16 res_type; /* Types defined above cmd 0x0204 */ 2459daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_SHARED_S 7 2469daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 2479daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 2489daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 2499daf8208SAnirudh Venkataramanan (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 2509daf8208SAnirudh Venkataramanan __le16 num_elems; 2519daf8208SAnirudh Venkataramanan struct ice_aqc_res_elem elem[1]; 2529daf8208SAnirudh Venkataramanan }; 2539daf8208SAnirudh Venkataramanan 2543a858ba3SAnirudh Venkataramanan /* Add VSI (indirect 0x0210) 2553a858ba3SAnirudh Venkataramanan * Update VSI (indirect 0x0211) 2563a858ba3SAnirudh Venkataramanan * Get VSI (indirect 0x0212) 2573a858ba3SAnirudh Venkataramanan * Free VSI (indirect 0x0213) 2583a858ba3SAnirudh Venkataramanan */ 2593a858ba3SAnirudh Venkataramanan struct ice_aqc_add_get_update_free_vsi { 2603a858ba3SAnirudh Venkataramanan __le16 vsi_num; 2613a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_NUM_S 0 2623a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 2633a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_IS_VALID BIT(15) 2643a858ba3SAnirudh Venkataramanan __le16 cmd_flags; 2653a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_KEEP_ALLOC 0x1 2663a858ba3SAnirudh Venkataramanan u8 vf_id; 2673a858ba3SAnirudh Venkataramanan u8 reserved; 2683a858ba3SAnirudh Venkataramanan __le16 vsi_flags; 2693a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_S 0 2703a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 2713a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_VF 0x0 2723a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 2733a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_PF 0x2 2743a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 2753a858ba3SAnirudh Venkataramanan __le32 addr_high; 2763a858ba3SAnirudh Venkataramanan __le32 addr_low; 2773a858ba3SAnirudh Venkataramanan }; 2783a858ba3SAnirudh Venkataramanan 2793a858ba3SAnirudh Venkataramanan /* Response descriptor for: 2803a858ba3SAnirudh Venkataramanan * Add VSI (indirect 0x0210) 2813a858ba3SAnirudh Venkataramanan * Update VSI (indirect 0x0211) 2823a858ba3SAnirudh Venkataramanan * Free VSI (indirect 0x0213) 2833a858ba3SAnirudh Venkataramanan */ 2843a858ba3SAnirudh Venkataramanan struct ice_aqc_add_update_free_vsi_resp { 2853a858ba3SAnirudh Venkataramanan __le16 vsi_num; 2863a858ba3SAnirudh Venkataramanan __le16 ext_status; 2873a858ba3SAnirudh Venkataramanan __le16 vsi_used; 2883a858ba3SAnirudh Venkataramanan __le16 vsi_free; 2893a858ba3SAnirudh Venkataramanan __le32 addr_high; 2903a858ba3SAnirudh Venkataramanan __le32 addr_low; 2913a858ba3SAnirudh Venkataramanan }; 2923a858ba3SAnirudh Venkataramanan 2933a858ba3SAnirudh Venkataramanan struct ice_aqc_vsi_props { 2943a858ba3SAnirudh Venkataramanan __le16 valid_sections; 2953a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 2963a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 2973a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 2983a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 2993a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 3003a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 3013a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 3023a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 3033a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 3043a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 3053a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 3063a858ba3SAnirudh Venkataramanan /* switch section */ 3073a858ba3SAnirudh Venkataramanan u8 sw_id; 3083a858ba3SAnirudh Venkataramanan u8 sw_flags; 3093a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 3103a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 3113a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 3123a858ba3SAnirudh Venkataramanan u8 sw_flags2; 3133a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 3143a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 3153a858ba3SAnirudh Venkataramanan (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 3163a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 3173a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 3183a858ba3SAnirudh Venkataramanan u8 veb_stat_id; 3193a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 3203a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 3213a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 3223a858ba3SAnirudh Venkataramanan /* security section */ 3233a858ba3SAnirudh Venkataramanan u8 sec_flags; 3243a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 3253a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 3263a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 3273a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 3283a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 3293a858ba3SAnirudh Venkataramanan u8 sec_reserved; 3303a858ba3SAnirudh Venkataramanan /* VLAN section */ 3313a858ba3SAnirudh Venkataramanan __le16 pvid; /* VLANS include priority bits */ 3323a858ba3SAnirudh Venkataramanan u8 pvlan_reserved[2]; 3335d8778d8SBrett Creeley u8 vlan_flags; 3345d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_S 0 3355d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 3365d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 3375d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 3385d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 3393a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 3405d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_S 3 3415d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 3425d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 3435d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 3445d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 3455d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 3463a858ba3SAnirudh Venkataramanan u8 pvlan_reserved2[3]; 3473a858ba3SAnirudh Venkataramanan /* ingress egress up sections */ 3483a858ba3SAnirudh Venkataramanan __le32 ingress_table; /* bitmap, 3 bits per up */ 3493a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 3503a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 3513a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 3523a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 3533a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 3543a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 3553a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 3563a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 3573a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 3583a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 3593a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 3603a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 3613a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 3623a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 3633a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 3643a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 3653a858ba3SAnirudh Venkataramanan __le32 egress_table; /* same defines as for ingress table */ 3663a858ba3SAnirudh Venkataramanan /* outer tags section */ 3673a858ba3SAnirudh Venkataramanan __le16 outer_tag; 3683a858ba3SAnirudh Venkataramanan u8 outer_tag_flags; 3693a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 3703a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 3713a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 3723a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 3733a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 3743a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 3753a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 3763a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 3773a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 3783a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 3793a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 3803a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 3813a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 3823a858ba3SAnirudh Venkataramanan u8 outer_tag_reserved; 3833a858ba3SAnirudh Venkataramanan /* queue mapping section */ 3843a858ba3SAnirudh Venkataramanan __le16 mapping_flags; 3853a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 3863a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 3873a858ba3SAnirudh Venkataramanan __le16 q_mapping[16]; 3883a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_S 0 3893a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 3903a858ba3SAnirudh Venkataramanan __le16 tc_mapping[8]; 3913a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 3923a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 3933a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_NUM_S 11 3943a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 3953a858ba3SAnirudh Venkataramanan /* queueing option section */ 3963a858ba3SAnirudh Venkataramanan u8 q_opt_rss; 3973a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 3983a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 3993a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 4003a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 4013a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 4023a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 4033a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 4043a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 4053a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4063a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4073a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4083a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4093a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4103a858ba3SAnirudh Venkataramanan u8 q_opt_tc; 4113a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 4123a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 4133a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 4143a858ba3SAnirudh Venkataramanan u8 q_opt_flags; 4153a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 4163a858ba3SAnirudh Venkataramanan u8 q_opt_reserved[3]; 4173a858ba3SAnirudh Venkataramanan /* outer up section */ 4183a858ba3SAnirudh Venkataramanan __le32 outer_up_table; /* same structure and defines as ingress tbl */ 4193a858ba3SAnirudh Venkataramanan /* section 10 */ 4203a858ba3SAnirudh Venkataramanan __le16 sect_10_reserved; 4213a858ba3SAnirudh Venkataramanan /* flow director section */ 4223a858ba3SAnirudh Venkataramanan __le16 fd_options; 4233a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_ENABLE BIT(0) 4243a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 4253a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 4263a858ba3SAnirudh Venkataramanan __le16 max_fd_fltr_dedicated; 4273a858ba3SAnirudh Venkataramanan __le16 max_fd_fltr_shared; 4283a858ba3SAnirudh Venkataramanan __le16 fd_def_q; 4293a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_Q_S 0 4303a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 4313a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_GRP_S 12 4323a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 4333a858ba3SAnirudh Venkataramanan __le16 fd_report_opt; 4343a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_REPORT_Q_S 0 4353a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 4363a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 4373a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 4383a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 4393a858ba3SAnirudh Venkataramanan /* PASID section */ 4403a858ba3SAnirudh Venkataramanan __le32 pasid_id; 4413a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PASID_ID_S 0 4423a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 4433a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 4443a858ba3SAnirudh Venkataramanan u8 reserved[24]; 4453a858ba3SAnirudh Venkataramanan }; 4463a858ba3SAnirudh Venkataramanan 44780d144c9SAnirudh Venkataramanan #define ICE_MAX_NUM_RECIPES 64 44880d144c9SAnirudh Venkataramanan 4499daf8208SAnirudh Venkataramanan /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 4509daf8208SAnirudh Venkataramanan */ 4519daf8208SAnirudh Venkataramanan struct ice_aqc_sw_rules { 4529daf8208SAnirudh Venkataramanan /* ops: add switch rules, referring the number of rules. 4539daf8208SAnirudh Venkataramanan * ops: update switch rules, referring the number of filters 4549daf8208SAnirudh Venkataramanan * ops: remove switch rules, referring the entry index. 4559daf8208SAnirudh Venkataramanan * ops: get switch rules, referring to the number of filters. 4569daf8208SAnirudh Venkataramanan */ 4579daf8208SAnirudh Venkataramanan __le16 num_rules_fltr_entry_index; 4589daf8208SAnirudh Venkataramanan u8 reserved[6]; 4599daf8208SAnirudh Venkataramanan __le32 addr_high; 4609daf8208SAnirudh Venkataramanan __le32 addr_low; 4619daf8208SAnirudh Venkataramanan }; 4629daf8208SAnirudh Venkataramanan 4639daf8208SAnirudh Venkataramanan /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 4649daf8208SAnirudh Venkataramanan * This structures describes the lookup rules and associated actions. "index" 4659daf8208SAnirudh Venkataramanan * is returned as part of a response to a successful Add command, and can be 4669daf8208SAnirudh Venkataramanan * used to identify the rule for Update/Get/Remove commands. 4679daf8208SAnirudh Venkataramanan */ 4689daf8208SAnirudh Venkataramanan struct ice_sw_rule_lkup_rx_tx { 4699daf8208SAnirudh Venkataramanan __le16 recipe_id; 4709daf8208SAnirudh Venkataramanan #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 4719daf8208SAnirudh Venkataramanan /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 4729daf8208SAnirudh Venkataramanan __le16 src; 4739daf8208SAnirudh Venkataramanan __le32 act; 4749daf8208SAnirudh Venkataramanan 4759daf8208SAnirudh Venkataramanan /* Bit 0:1 - Action type */ 4769daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_TYPE_S 0x00 4779daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 4789daf8208SAnirudh Venkataramanan 4799daf8208SAnirudh Venkataramanan /* Bit 2 - Loop back enable 4809daf8208SAnirudh Venkataramanan * Bit 3 - LAN enable 4819daf8208SAnirudh Venkataramanan */ 4829daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 4839daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 4849daf8208SAnirudh Venkataramanan 4859daf8208SAnirudh Venkataramanan /* Action type = 0 - Forward to VSI or VSI list */ 4869daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 4879daf8208SAnirudh Venkataramanan 4889daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_ID_S 4 4899daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 4909daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 4919daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 4929daf8208SAnirudh Venkataramanan /* This bit needs to be set if action is forward to VSI list */ 4939daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 4949daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 4959daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_DROP BIT(18) 4969daf8208SAnirudh Venkataramanan 4979daf8208SAnirudh Venkataramanan /* Action type = 1 - Forward to Queue of Queue group */ 4989daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_TO_Q 0x1 4999daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_INDEX_S 4 5009daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 5019daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_REGION_S 15 5029daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 5039daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 5049daf8208SAnirudh Venkataramanan 5059daf8208SAnirudh Venkataramanan /* Action type = 2 - Prune */ 5069daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PRUNE 0x2 5079daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_EGRESS BIT(15) 5089daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_INGRESS BIT(16) 5099daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PRUNET BIT(17) 5109daf8208SAnirudh Venkataramanan /* Bit 18 should be set to 0 for this action */ 5119daf8208SAnirudh Venkataramanan 5129daf8208SAnirudh Venkataramanan /* Action type = 2 - Pointer */ 5139daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR 0x2 5149daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR_VAL_S 4 5159daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 5169daf8208SAnirudh Venkataramanan /* Bit 18 should be set to 1 */ 5179daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 5189daf8208SAnirudh Venkataramanan 5199daf8208SAnirudh Venkataramanan /* Action type = 3 - Other actions. Last two bits 5209daf8208SAnirudh Venkataramanan * are other action identifier 5219daf8208SAnirudh Venkataramanan */ 5229daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 5239daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 5249daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 5259daf8208SAnirudh Venkataramanan (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 5269daf8208SAnirudh Venkataramanan 5279daf8208SAnirudh Venkataramanan /* Bit 17:18 - Defines other actions */ 5289daf8208SAnirudh Venkataramanan /* Other action = 0 - Mirror VSI */ 5299daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_MIRROR 0 5309daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 5319daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 5329daf8208SAnirudh Venkataramanan (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 5339daf8208SAnirudh Venkataramanan 5349daf8208SAnirudh Venkataramanan /* Other action = 3 - Set Stat count */ 5359daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 5369daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 5379daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 5389daf8208SAnirudh Venkataramanan (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 5399daf8208SAnirudh Venkataramanan 5409daf8208SAnirudh Venkataramanan __le16 index; /* The index of the rule in the lookup table */ 5419daf8208SAnirudh Venkataramanan /* Length and values of the header to be matched per recipe or 5429daf8208SAnirudh Venkataramanan * lookup-type 5439daf8208SAnirudh Venkataramanan */ 5449daf8208SAnirudh Venkataramanan __le16 hdr_len; 5459daf8208SAnirudh Venkataramanan u8 hdr[1]; 5469daf8208SAnirudh Venkataramanan } __packed; 5479daf8208SAnirudh Venkataramanan 5489daf8208SAnirudh Venkataramanan /* Add/Update/Remove large action command/response entry 5499daf8208SAnirudh Venkataramanan * "index" is returned as part of a response to a successful Add command, and 5509daf8208SAnirudh Venkataramanan * can be used to identify the action for Update/Get/Remove commands. 5519daf8208SAnirudh Venkataramanan */ 5529daf8208SAnirudh Venkataramanan struct ice_sw_rule_lg_act { 5539daf8208SAnirudh Venkataramanan __le16 index; /* Index in large action table */ 5549daf8208SAnirudh Venkataramanan __le16 size; 5559daf8208SAnirudh Venkataramanan __le32 act[1]; /* array of size for actions */ 5569daf8208SAnirudh Venkataramanan /* Max number of large actions */ 5579daf8208SAnirudh Venkataramanan #define ICE_MAX_LG_ACT 4 5589daf8208SAnirudh Venkataramanan /* Bit 0:1 - Action type */ 5599daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_TYPE_S 0 5609daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 5619daf8208SAnirudh Venkataramanan 5629daf8208SAnirudh Venkataramanan /* Action type = 0 - Forward to VSI or VSI list */ 5639daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_FORWARDING 0 5649daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_ID_S 3 5659daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 5669daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_LIST_ID_S 3 5679daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 5689daf8208SAnirudh Venkataramanan /* This bit needs to be set if action is forward to VSI list */ 5699daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_LIST BIT(13) 5709daf8208SAnirudh Venkataramanan 5719daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VALID_BIT BIT(16) 5729daf8208SAnirudh Venkataramanan 5739daf8208SAnirudh Venkataramanan /* Action type = 1 - Forward to Queue of Queue group */ 5749daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_TO_Q 0x1 5759daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_INDEX_S 3 5769daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 5779daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_REGION_S 14 5789daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 5799daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 5809daf8208SAnirudh Venkataramanan 5819daf8208SAnirudh Venkataramanan /* Action type = 2 - Prune */ 5829daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_PRUNE 0x2 5839daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_EGRESS BIT(14) 5849daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_INGRESS BIT(15) 5859daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_PRUNET BIT(16) 5869daf8208SAnirudh Venkataramanan 5879daf8208SAnirudh Venkataramanan /* Action type = 3 - Mirror VSI */ 5889daf8208SAnirudh Venkataramanan #define ICE_LG_OTHER_ACT_MIRROR 0x3 5899daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 5909daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 5919daf8208SAnirudh Venkataramanan 59234357a90SAnirudh Venkataramanan /* Action type = 5 - Generic Value */ 5939daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC 0x5 5949daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_VALUE_S 3 5959daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 5969daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_OFFSET_S 19 5979daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 5989daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 5999daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 6004381147dSAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 6019daf8208SAnirudh Venkataramanan 6029daf8208SAnirudh Venkataramanan /* Action = 7 - Set Stat count */ 6039daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_STAT_COUNT 0x7 6049daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_STAT_COUNT_S 3 6059daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 6069daf8208SAnirudh Venkataramanan }; 6079daf8208SAnirudh Venkataramanan 6089daf8208SAnirudh Venkataramanan /* Add/Update/Remove VSI list command/response entry 6099daf8208SAnirudh Venkataramanan * "index" is returned as part of a response to a successful Add command, and 6109daf8208SAnirudh Venkataramanan * can be used to identify the VSI list for Update/Get/Remove commands. 6119daf8208SAnirudh Venkataramanan */ 6129daf8208SAnirudh Venkataramanan struct ice_sw_rule_vsi_list { 6139daf8208SAnirudh Venkataramanan __le16 index; /* Index of VSI/Prune list */ 6149daf8208SAnirudh Venkataramanan __le16 number_vsi; 6159daf8208SAnirudh Venkataramanan __le16 vsi[1]; /* Array of number_vsi VSI numbers */ 6169daf8208SAnirudh Venkataramanan }; 6179daf8208SAnirudh Venkataramanan 6189daf8208SAnirudh Venkataramanan /* Query VSI list command/response entry */ 6199daf8208SAnirudh Venkataramanan struct ice_sw_rule_vsi_list_query { 6209daf8208SAnirudh Venkataramanan __le16 index; 6219daf8208SAnirudh Venkataramanan DECLARE_BITMAP(vsi_list, ICE_MAX_VSI); 6229daf8208SAnirudh Venkataramanan } __packed; 6239daf8208SAnirudh Venkataramanan 6249daf8208SAnirudh Venkataramanan /* Add switch rule response: 6259daf8208SAnirudh Venkataramanan * Content of return buffer is same as the input buffer. The status field and 6269daf8208SAnirudh Venkataramanan * LUT index are updated as part of the response 6279daf8208SAnirudh Venkataramanan */ 6289daf8208SAnirudh Venkataramanan struct ice_aqc_sw_rules_elem { 6299daf8208SAnirudh Venkataramanan __le16 type; /* Switch rule type, one of T_... */ 6309daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 6319daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 6329daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 6339daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 6349daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 6359daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 6369daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 6379daf8208SAnirudh Venkataramanan __le16 status; 6389daf8208SAnirudh Venkataramanan union { 6399daf8208SAnirudh Venkataramanan struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 6409daf8208SAnirudh Venkataramanan struct ice_sw_rule_lg_act lg_act; 6419daf8208SAnirudh Venkataramanan struct ice_sw_rule_vsi_list vsi_list; 6429daf8208SAnirudh Venkataramanan struct ice_sw_rule_vsi_list_query vsi_list_query; 6439daf8208SAnirudh Venkataramanan } __packed pdata; 6449daf8208SAnirudh Venkataramanan }; 6459daf8208SAnirudh Venkataramanan 646dc49c772SAnirudh Venkataramanan /* Get Default Topology (indirect 0x0400) */ 647dc49c772SAnirudh Venkataramanan struct ice_aqc_get_topo { 648dc49c772SAnirudh Venkataramanan u8 port_num; 649dc49c772SAnirudh Venkataramanan u8 num_branches; 650dc49c772SAnirudh Venkataramanan __le16 reserved1; 651dc49c772SAnirudh Venkataramanan __le32 reserved2; 652dc49c772SAnirudh Venkataramanan __le32 addr_high; 653dc49c772SAnirudh Venkataramanan __le32 addr_low; 654dc49c772SAnirudh Venkataramanan }; 655dc49c772SAnirudh Venkataramanan 6565513b920SAnirudh Venkataramanan /* Update TSE (indirect 0x0403) 6575513b920SAnirudh Venkataramanan * Get TSE (indirect 0x0404) 6581f9c7840SAnirudh Venkataramanan * Add TSE (indirect 0x0401) 6591f9c7840SAnirudh Venkataramanan * Delete TSE (indirect 0x040F) 6601f9c7840SAnirudh Venkataramanan * Move TSE (indirect 0x0408) 6611f9c7840SAnirudh Venkataramanan * Suspend Nodes (indirect 0x0409) 6621f9c7840SAnirudh Venkataramanan * Resume Nodes (indirect 0x040A) 6635513b920SAnirudh Venkataramanan */ 6641f9c7840SAnirudh Venkataramanan struct ice_aqc_sched_elem_cmd { 6655513b920SAnirudh Venkataramanan __le16 num_elem_req; /* Used by commands */ 6665513b920SAnirudh Venkataramanan __le16 num_elem_resp; /* Used by responses */ 6675513b920SAnirudh Venkataramanan __le32 reserved; 6685513b920SAnirudh Venkataramanan __le32 addr_high; 6695513b920SAnirudh Venkataramanan __le32 addr_low; 6705513b920SAnirudh Venkataramanan }; 6715513b920SAnirudh Venkataramanan 6725513b920SAnirudh Venkataramanan /* This is the buffer for: 6735513b920SAnirudh Venkataramanan * Suspend Nodes (indirect 0x0409) 6745513b920SAnirudh Venkataramanan * Resume Nodes (indirect 0x040A) 6755513b920SAnirudh Venkataramanan */ 6765513b920SAnirudh Venkataramanan struct ice_aqc_suspend_resume_elem { 6775513b920SAnirudh Venkataramanan __le32 teid[1]; 6785513b920SAnirudh Venkataramanan }; 6795513b920SAnirudh Venkataramanan 6809c20346bSAnirudh Venkataramanan struct ice_aqc_elem_info_bw { 6819c20346bSAnirudh Venkataramanan __le16 bw_profile_idx; 6829c20346bSAnirudh Venkataramanan __le16 bw_alloc; 6839c20346bSAnirudh Venkataramanan }; 6849c20346bSAnirudh Venkataramanan 6859c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem { 6869c20346bSAnirudh Venkataramanan u8 elem_type; /* Special field, reserved for some aq calls */ 6879c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 6889c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 6899c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_TC 0x2 6909c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 6919c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 6929c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_LEAF 0x5 6939c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 6949c20346bSAnirudh Venkataramanan u8 valid_sections; 6959c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 6969c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_CIR BIT(1) 6979c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_EIR BIT(2) 6989c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 6999c20346bSAnirudh Venkataramanan u8 generic; 7009c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 7019c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 7029c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 7039c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 7049c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 7059c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 7069c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 7079c20346bSAnirudh Venkataramanan (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 7089c20346bSAnirudh Venkataramanan u8 flags; /* Special field, reserved for some aq calls */ 7099c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 7109c20346bSAnirudh Venkataramanan struct ice_aqc_elem_info_bw cir_bw; 7119c20346bSAnirudh Venkataramanan struct ice_aqc_elem_info_bw eir_bw; 7129c20346bSAnirudh Venkataramanan __le16 srl_id; 7139c20346bSAnirudh Venkataramanan __le16 reserved2; 7149c20346bSAnirudh Venkataramanan }; 7159c20346bSAnirudh Venkataramanan 7169c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem_data { 7179c20346bSAnirudh Venkataramanan __le32 parent_teid; 7189c20346bSAnirudh Venkataramanan __le32 node_teid; 7199c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem data; 7209c20346bSAnirudh Venkataramanan }; 7219c20346bSAnirudh Venkataramanan 7229c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr { 7239c20346bSAnirudh Venkataramanan __le32 parent_teid; 7249c20346bSAnirudh Venkataramanan __le16 num_elems; 7259c20346bSAnirudh Venkataramanan __le16 reserved2; 7269c20346bSAnirudh Venkataramanan }; 7279c20346bSAnirudh Venkataramanan 7285513b920SAnirudh Venkataramanan struct ice_aqc_add_elem { 7295513b920SAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr hdr; 7305513b920SAnirudh Venkataramanan struct ice_aqc_txsched_elem_data generic[1]; 7315513b920SAnirudh Venkataramanan }; 7325513b920SAnirudh Venkataramanan 73356daee6cSAnirudh Venkataramanan struct ice_aqc_get_elem { 73456daee6cSAnirudh Venkataramanan struct ice_aqc_txsched_elem_data generic[1]; 73556daee6cSAnirudh Venkataramanan }; 73656daee6cSAnirudh Venkataramanan 737dc49c772SAnirudh Venkataramanan struct ice_aqc_get_topo_elem { 738dc49c772SAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr hdr; 739dc49c772SAnirudh Venkataramanan struct ice_aqc_txsched_elem_data 740dc49c772SAnirudh Venkataramanan generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 741dc49c772SAnirudh Venkataramanan }; 742dc49c772SAnirudh Venkataramanan 7439c20346bSAnirudh Venkataramanan struct ice_aqc_delete_elem { 7449c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr hdr; 7459c20346bSAnirudh Venkataramanan __le32 teid[1]; 7469c20346bSAnirudh Venkataramanan }; 7479c20346bSAnirudh Venkataramanan 7487b9ffc76SAnirudh Venkataramanan /* Query Port ETS (indirect 0x040E) 7497b9ffc76SAnirudh Venkataramanan * 7507b9ffc76SAnirudh Venkataramanan * This indirect command is used to query port TC node configuration. 7517b9ffc76SAnirudh Venkataramanan */ 7527b9ffc76SAnirudh Venkataramanan struct ice_aqc_query_port_ets { 7537b9ffc76SAnirudh Venkataramanan __le32 port_teid; 7547b9ffc76SAnirudh Venkataramanan __le32 reserved; 7557b9ffc76SAnirudh Venkataramanan __le32 addr_high; 7567b9ffc76SAnirudh Venkataramanan __le32 addr_low; 7577b9ffc76SAnirudh Venkataramanan }; 7587b9ffc76SAnirudh Venkataramanan 7597b9ffc76SAnirudh Venkataramanan struct ice_aqc_port_ets_elem { 7607b9ffc76SAnirudh Venkataramanan u8 tc_valid_bits; 7617b9ffc76SAnirudh Venkataramanan u8 reserved[3]; 7627b9ffc76SAnirudh Venkataramanan /* 3 bits for UP per TC 0-7, 4th byte reserved */ 7637b9ffc76SAnirudh Venkataramanan __le32 up2tc; 7647b9ffc76SAnirudh Venkataramanan u8 tc_bw_share[8]; 7657b9ffc76SAnirudh Venkataramanan __le32 port_eir_prof_id; 7667b9ffc76SAnirudh Venkataramanan __le32 port_cir_prof_id; 7677b9ffc76SAnirudh Venkataramanan /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 7687b9ffc76SAnirudh Venkataramanan __le32 tc_node_prio; 7697b9ffc76SAnirudh Venkataramanan #define ICE_TC_NODE_PRIO_S 0x4 7707b9ffc76SAnirudh Venkataramanan u8 reserved1[4]; 7717b9ffc76SAnirudh Venkataramanan __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 7727b9ffc76SAnirudh Venkataramanan }; 7737b9ffc76SAnirudh Venkataramanan 7749c20346bSAnirudh Venkataramanan /* Query Scheduler Resource Allocation (indirect 0x0412) 7759c20346bSAnirudh Venkataramanan * This indirect command retrieves the scheduler resources allocated by 7769c20346bSAnirudh Venkataramanan * EMP Firmware to the given PF. 7779c20346bSAnirudh Venkataramanan */ 7789c20346bSAnirudh Venkataramanan struct ice_aqc_query_txsched_res { 7799c20346bSAnirudh Venkataramanan u8 reserved[8]; 7809c20346bSAnirudh Venkataramanan __le32 addr_high; 7819c20346bSAnirudh Venkataramanan __le32 addr_low; 7829c20346bSAnirudh Venkataramanan }; 7839c20346bSAnirudh Venkataramanan 7849c20346bSAnirudh Venkataramanan struct ice_aqc_generic_sched_props { 7859c20346bSAnirudh Venkataramanan __le16 phys_levels; 7869c20346bSAnirudh Venkataramanan __le16 logical_levels; 7879c20346bSAnirudh Venkataramanan u8 flattening_bitmap; 7889c20346bSAnirudh Venkataramanan u8 max_device_cgds; 7899c20346bSAnirudh Venkataramanan u8 max_pf_cgds; 7909c20346bSAnirudh Venkataramanan u8 rsvd0; 7919c20346bSAnirudh Venkataramanan __le16 rdma_qsets; 7929c20346bSAnirudh Venkataramanan u8 rsvd1[22]; 7939c20346bSAnirudh Venkataramanan }; 7949c20346bSAnirudh Venkataramanan 7959c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props { 7969c20346bSAnirudh Venkataramanan u8 logical_layer; 7979c20346bSAnirudh Venkataramanan u8 chunk_size; 7989c20346bSAnirudh Venkataramanan __le16 max_device_nodes; 7999c20346bSAnirudh Venkataramanan __le16 max_pf_nodes; 800b36c598cSAnirudh Venkataramanan u8 rsvd0[4]; 801b36c598cSAnirudh Venkataramanan __le16 max_sibl_grp_sz; 8029c20346bSAnirudh Venkataramanan __le16 max_cir_rl_profiles; 8039c20346bSAnirudh Venkataramanan __le16 max_eir_rl_profiles; 8049c20346bSAnirudh Venkataramanan __le16 max_srl_profiles; 8059c20346bSAnirudh Venkataramanan u8 rsvd1[14]; 8069c20346bSAnirudh Venkataramanan }; 8079c20346bSAnirudh Venkataramanan 8089c20346bSAnirudh Venkataramanan struct ice_aqc_query_txsched_res_resp { 8099c20346bSAnirudh Venkataramanan struct ice_aqc_generic_sched_props sched_props; 8109c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 8119c20346bSAnirudh Venkataramanan }; 8129c20346bSAnirudh Venkataramanan 813dc49c772SAnirudh Venkataramanan /* Get PHY capabilities (indirect 0x0600) */ 814dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps { 815dc49c772SAnirudh Venkataramanan u8 lport_num; 816dc49c772SAnirudh Venkataramanan u8 reserved; 817dc49c772SAnirudh Venkataramanan __le16 param0; 818dc49c772SAnirudh Venkataramanan /* 18.0 - Report qualified modules */ 819dc49c772SAnirudh Venkataramanan #define ICE_AQC_GET_PHY_RQM BIT(0) 820dc49c772SAnirudh Venkataramanan /* 18.1 - 18.2 : Report mode 821dc49c772SAnirudh Venkataramanan * 00b - Report NVM capabilities 822dc49c772SAnirudh Venkataramanan * 01b - Report topology capabilities 823dc49c772SAnirudh Venkataramanan * 10b - Report SW configured 824dc49c772SAnirudh Venkataramanan */ 825dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_MODE_S 1 826dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 827dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_NVM_CAP 0 828dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 829dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_SW_CFG BIT(2) 830dc49c772SAnirudh Venkataramanan __le32 reserved1; 831dc49c772SAnirudh Venkataramanan __le32 addr_high; 832dc49c772SAnirudh Venkataramanan __le32 addr_low; 833dc49c772SAnirudh Venkataramanan }; 834dc49c772SAnirudh Venkataramanan 835dc49c772SAnirudh Venkataramanan /* This is #define of PHY type (Extended): 836dc49c772SAnirudh Venkataramanan * The first set of defines is for phy_type_low. 837dc49c772SAnirudh Venkataramanan */ 838dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 839dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 840dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 841dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 842dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 843dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 844dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 845dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 846dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 847dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 848dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 849dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 850dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 851dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 852dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 853dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 854dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 855dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 856dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 857dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 858dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 859dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 860dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 861dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 862dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 863dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 864dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 865dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 866dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 867dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 868dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 869dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 870dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 871dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 872dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 873dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 874aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 875aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 876aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 877aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 878aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 879aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 880aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 881aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 882aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 883aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 884aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 885aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 886aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 887aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 888aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 889aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 890aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 891aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 892aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 893aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 894aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 895aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 896aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 897aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 898aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 899aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 900aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 901aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 902dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 903aef74145SAnirudh Venkataramanan /* The second set of defines is for phy_type_high. */ 904aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 905aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 906aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 907aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 908aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 909aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19 910dc49c772SAnirudh Venkataramanan 911dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps_data { 912dc49c772SAnirudh Venkataramanan __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 913b6f934f0SBrett Creeley __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 914dc49c772SAnirudh Venkataramanan u8 caps; 915dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 916dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 917dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 918dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_LINK BIT(3) 919dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_AN_MODE BIT(4) 920dc49c772SAnirudh Venkataramanan #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 921f776b3acSPaul Greenwalt #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 922f776b3acSPaul Greenwalt #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 923dc49c772SAnirudh Venkataramanan u8 low_power_ctrl; 924dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 925dc49c772SAnirudh Venkataramanan __le16 eee_cap; 926dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 927dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 928dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 929dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 930dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 931dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 932dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 933dc49c772SAnirudh Venkataramanan __le16 eeer_value; 934dc49c772SAnirudh Venkataramanan u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 93562f4dafcSAnirudh Venkataramanan u8 phy_fw_ver[8]; 936dc49c772SAnirudh Venkataramanan u8 link_fec_options; 937dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 938dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 939dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 940dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 941dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 942dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 943dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 944f776b3acSPaul Greenwalt #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 94562f4dafcSAnirudh Venkataramanan u8 rsvd1; /* Byte 35 reserved */ 946dc49c772SAnirudh Venkataramanan u8 extended_compliance_code; 947dc49c772SAnirudh Venkataramanan #define ICE_MODULE_TYPE_TOTAL_BYTE 3 948dc49c772SAnirudh Venkataramanan u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 949dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 950dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 951dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 952dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 953dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 954dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 955dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 956dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 957dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 958dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 959dc49c772SAnirudh Venkataramanan u8 qualified_module_count; 96062f4dafcSAnirudh Venkataramanan u8 rsvd2[7]; /* Bytes 47:41 reserved */ 961dc49c772SAnirudh Venkataramanan #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 962dc49c772SAnirudh Venkataramanan struct { 963dc49c772SAnirudh Venkataramanan u8 v_oui[3]; 96462f4dafcSAnirudh Venkataramanan u8 rsvd3; 965dc49c772SAnirudh Venkataramanan u8 v_part[16]; 966dc49c772SAnirudh Venkataramanan __le32 v_rev; 96762f4dafcSAnirudh Venkataramanan __le64 rsvd4; 968dc49c772SAnirudh Venkataramanan } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 969dc49c772SAnirudh Venkataramanan }; 970dc49c772SAnirudh Venkataramanan 971fcea6f3dSAnirudh Venkataramanan /* Set PHY capabilities (direct 0x0601) 972fcea6f3dSAnirudh Venkataramanan * NOTE: This command must be followed by setup link and restart auto-neg 973fcea6f3dSAnirudh Venkataramanan */ 974fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg { 975fcea6f3dSAnirudh Venkataramanan u8 lport_num; 976fcea6f3dSAnirudh Venkataramanan u8 reserved[7]; 977fcea6f3dSAnirudh Venkataramanan __le32 addr_high; 978fcea6f3dSAnirudh Venkataramanan __le32 addr_low; 979fcea6f3dSAnirudh Venkataramanan }; 980fcea6f3dSAnirudh Venkataramanan 981fcea6f3dSAnirudh Venkataramanan /* Set PHY config command data structure */ 982fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg_data { 983fcea6f3dSAnirudh Venkataramanan __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 984b6f934f0SBrett Creeley __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 985fcea6f3dSAnirudh Venkataramanan u8 caps; 986d8df260aSChinh T Cao #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 987fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 988fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 989fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 990fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_LINK BIT(3) 99148cb27f2SChinh Cao #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 99248cb27f2SChinh Cao #define ICE_AQ_PHY_ENA_LESM BIT(6) 99348cb27f2SChinh Cao #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 994fcea6f3dSAnirudh Venkataramanan u8 low_power_ctrl; 995fcea6f3dSAnirudh Venkataramanan __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 996fcea6f3dSAnirudh Venkataramanan __le16 eeer_value; 997fcea6f3dSAnirudh Venkataramanan u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 998fcea6f3dSAnirudh Venkataramanan u8 rsvd1; 999fcea6f3dSAnirudh Venkataramanan }; 1000fcea6f3dSAnirudh Venkataramanan 1001fcea6f3dSAnirudh Venkataramanan /* Restart AN command data structure (direct 0x0605) 1002fcea6f3dSAnirudh Venkataramanan * Also used for response, with only the lport_num field present. 1003fcea6f3dSAnirudh Venkataramanan */ 1004fcea6f3dSAnirudh Venkataramanan struct ice_aqc_restart_an { 1005fcea6f3dSAnirudh Venkataramanan u8 lport_num; 1006fcea6f3dSAnirudh Venkataramanan u8 reserved; 1007fcea6f3dSAnirudh Venkataramanan u8 cmd_flags; 1008fcea6f3dSAnirudh Venkataramanan #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1009fcea6f3dSAnirudh Venkataramanan #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1010fcea6f3dSAnirudh Venkataramanan u8 reserved2[13]; 1011fcea6f3dSAnirudh Venkataramanan }; 1012fcea6f3dSAnirudh Venkataramanan 1013dc49c772SAnirudh Venkataramanan /* Get link status (indirect 0x0607), also used for Link Status Event */ 1014dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status { 1015dc49c772SAnirudh Venkataramanan u8 lport_num; 1016dc49c772SAnirudh Venkataramanan u8 reserved; 1017dc49c772SAnirudh Venkataramanan __le16 cmd_flags; 1018dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_M 0x3 1019dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_NOP 0x0 1020dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_DIS 0x2 1021dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_ENA 0x3 1022dc49c772SAnirudh Venkataramanan /* only response uses this flag */ 1023dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_IS_ENABLED 0x1 1024dc49c772SAnirudh Venkataramanan __le32 reserved2; 1025dc49c772SAnirudh Venkataramanan __le32 addr_high; 1026dc49c772SAnirudh Venkataramanan __le32 addr_low; 1027dc49c772SAnirudh Venkataramanan }; 1028dc49c772SAnirudh Venkataramanan 1029dc49c772SAnirudh Venkataramanan /* Get link status response data structure, also used for Link Status Event */ 1030dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status_data { 1031dc49c772SAnirudh Venkataramanan u8 topo_media_conflict; 1032dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1033dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1034dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1035dc49c772SAnirudh Venkataramanan u8 reserved1; 1036dc49c772SAnirudh Venkataramanan u8 link_info; 1037dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1038dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT BIT(1) 1039dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT_TX BIT(2) 1040dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT_RX BIT(3) 1041dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1042dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1043dc49c772SAnirudh Venkataramanan #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1044dc49c772SAnirudh Venkataramanan #define ICE_AQ_SIGNAL_DETECT BIT(7) 1045dc49c772SAnirudh Venkataramanan u8 an_info; 1046dc49c772SAnirudh Venkataramanan #define ICE_AQ_AN_COMPLETED BIT(0) 1047dc49c772SAnirudh Venkataramanan #define ICE_AQ_LP_AN_ABILITY BIT(1) 1048dc49c772SAnirudh Venkataramanan #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1049dc49c772SAnirudh Venkataramanan #define ICE_AQ_FEC_EN BIT(3) 1050dc49c772SAnirudh Venkataramanan #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1051dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1052dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1053dc49c772SAnirudh Venkataramanan #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1054dc49c772SAnirudh Venkataramanan u8 ext_info; 1055dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1056dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1057f9867df6SAnirudh Venkataramanan /* Port Tx Suspended */ 1058dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_S 2 1059dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1060dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_ACTIVE 0 1061dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_DRAINED 1 1062dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_FLUSHED 3 1063dc49c772SAnirudh Venkataramanan u8 reserved2; 1064dc49c772SAnirudh Venkataramanan __le16 max_frame_size; 1065dc49c772SAnirudh Venkataramanan u8 cfg; 1066dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1067dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1068dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1069f776b3acSPaul Greenwalt #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1070dc49c772SAnirudh Venkataramanan /* Pacing Config */ 1071dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_S 3 1072dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1073dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1074dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1075dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1076dc49c772SAnirudh Venkataramanan /* External Device Power Ability */ 1077dc49c772SAnirudh Venkataramanan u8 power_desc; 1078dc49c772SAnirudh Venkataramanan #define ICE_AQ_PWR_CLASS_M 0x3 1079dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1080dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1081dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1082dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1083dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1084dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1085dc49c772SAnirudh Venkataramanan __le16 link_speed; 1086dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1087dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1088dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1089dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1090dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1091dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1092dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1093dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1094dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1095aef74145SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1096aef74145SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1097dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1098dc49c772SAnirudh Venkataramanan __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1099dc49c772SAnirudh Venkataramanan __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1100aef74145SAnirudh Venkataramanan __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1101dc49c772SAnirudh Venkataramanan }; 1102dc49c772SAnirudh Venkataramanan 11030b28b702SAnirudh Venkataramanan /* Set event mask command (direct 0x0613) */ 11040b28b702SAnirudh Venkataramanan struct ice_aqc_set_event_mask { 11050b28b702SAnirudh Venkataramanan u8 lport_num; 11060b28b702SAnirudh Venkataramanan u8 reserved[7]; 11070b28b702SAnirudh Venkataramanan __le16 event_mask; 11080b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 11090b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 11100b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 11110b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 11120b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 11130b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 11140b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 11150b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 11160b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 11170b28b702SAnirudh Venkataramanan u8 reserved1[6]; 11180b28b702SAnirudh Venkataramanan }; 11190b28b702SAnirudh Venkataramanan 11200e674aebSAnirudh Venkataramanan /* Set MAC Loopback command (direct 0x0620) */ 11210e674aebSAnirudh Venkataramanan struct ice_aqc_set_mac_lb { 11220e674aebSAnirudh Venkataramanan u8 lb_mode; 11230e674aebSAnirudh Venkataramanan #define ICE_AQ_MAC_LB_EN BIT(0) 11240e674aebSAnirudh Venkataramanan #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 11250e674aebSAnirudh Venkataramanan u8 reserved[15]; 11260e674aebSAnirudh Venkataramanan }; 11270e674aebSAnirudh Venkataramanan 11288e151d50SAnirudh Venkataramanan /* Set Port Identification LED (direct, 0x06E9) */ 11298e151d50SAnirudh Venkataramanan struct ice_aqc_set_port_id_led { 11308e151d50SAnirudh Venkataramanan u8 lport_num; 11318e151d50SAnirudh Venkataramanan u8 lport_num_valid; 11328e151d50SAnirudh Venkataramanan u8 ident_mode; 11338e151d50SAnirudh Venkataramanan #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 11348e151d50SAnirudh Venkataramanan #define ICE_AQC_PORT_IDENT_LED_ORIG 0 11358e151d50SAnirudh Venkataramanan u8 rsvd[13]; 11368e151d50SAnirudh Venkataramanan }; 11378e151d50SAnirudh Venkataramanan 1138f31e4b6fSAnirudh Venkataramanan /* NVM Read command (indirect 0x0701) 1139f31e4b6fSAnirudh Venkataramanan * NVM Erase commands (direct 0x0702) 1140f31e4b6fSAnirudh Venkataramanan * NVM Update commands (indirect 0x0703) 1141f31e4b6fSAnirudh Venkataramanan */ 1142f31e4b6fSAnirudh Venkataramanan struct ice_aqc_nvm { 114343c89b16SAnirudh Venkataramanan __le16 offset_low; 114443c89b16SAnirudh Venkataramanan u8 offset_high; 1145f31e4b6fSAnirudh Venkataramanan u8 cmd_flags; 1146f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_LAST_CMD BIT(0) 1147f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1148f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_PRESERVATION_S 1 11496263e811SLev Faerman #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 11506263e811SLev Faerman #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1151f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 11526263e811SLev Faerman #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1153f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 115443c89b16SAnirudh Venkataramanan __le16 module_typeid; 1155f31e4b6fSAnirudh Venkataramanan __le16 length; 1156f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1157f31e4b6fSAnirudh Venkataramanan __le32 addr_high; 1158f31e4b6fSAnirudh Venkataramanan __le32 addr_low; 1159f31e4b6fSAnirudh Venkataramanan }; 1160f31e4b6fSAnirudh Venkataramanan 11610e674aebSAnirudh Venkataramanan /* NVM Checksum Command (direct, 0x0706) */ 11620e674aebSAnirudh Venkataramanan struct ice_aqc_nvm_checksum { 11630e674aebSAnirudh Venkataramanan u8 flags; 11640e674aebSAnirudh Venkataramanan #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 11650e674aebSAnirudh Venkataramanan #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 11660e674aebSAnirudh Venkataramanan u8 rsvd; 11670e674aebSAnirudh Venkataramanan __le16 checksum; /* Used only by response */ 11680e674aebSAnirudh Venkataramanan #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 11690e674aebSAnirudh Venkataramanan u8 rsvd2[12]; 11700e674aebSAnirudh Venkataramanan }; 11710e674aebSAnirudh Venkataramanan 1172007676b4SAnirudh Venkataramanan /** 1173f9867df6SAnirudh Venkataramanan * Send to PF command (indirect 0x0801) ID is only used by PF 1174007676b4SAnirudh Venkataramanan * 1175f9867df6SAnirudh Venkataramanan * Send to VF command (indirect 0x0802) ID is only used by PF 1176007676b4SAnirudh Venkataramanan * 1177007676b4SAnirudh Venkataramanan */ 1178007676b4SAnirudh Venkataramanan struct ice_aqc_pf_vf_msg { 1179007676b4SAnirudh Venkataramanan __le32 id; 1180007676b4SAnirudh Venkataramanan u32 reserved; 1181007676b4SAnirudh Venkataramanan __le32 addr_high; 1182007676b4SAnirudh Venkataramanan __le32 addr_low; 1183007676b4SAnirudh Venkataramanan }; 1184007676b4SAnirudh Venkataramanan 11850ebd3ff1SAnirudh Venkataramanan /* Get LLDP MIB (indirect 0x0A00) 11860ebd3ff1SAnirudh Venkataramanan * Note: This is also used by the LLDP MIB Change Event (0x0A01) 11870ebd3ff1SAnirudh Venkataramanan * as the format is the same. 11880ebd3ff1SAnirudh Venkataramanan */ 11890ebd3ff1SAnirudh Venkataramanan struct ice_aqc_lldp_get_mib { 11900ebd3ff1SAnirudh Venkataramanan u8 type; 11910ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_TYPE_S 0 11920ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 11930ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_LOCAL 0 11940ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_REMOTE 1 11950ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 11960ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_BRID_TYPE_S 2 11970ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 11980ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 11990ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 12000ebd3ff1SAnirudh Venkataramanan /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 12010ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_S 0x4 12020ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 12030ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_ACTIVE 0 12040ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_SUSPENDED 1 12050ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_FLUSHED 3 12060ebd3ff1SAnirudh Venkataramanan /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 12070ebd3ff1SAnirudh Venkataramanan * and in the LLDP MIB Change Event (0x0A01). They are valid for the 12080ebd3ff1SAnirudh Venkataramanan * Get LLDP MIB (0x0A00) response only. 12090ebd3ff1SAnirudh Venkataramanan */ 12100ebd3ff1SAnirudh Venkataramanan u8 reserved1; 12110ebd3ff1SAnirudh Venkataramanan __le16 local_len; 12120ebd3ff1SAnirudh Venkataramanan __le16 remote_len; 12130ebd3ff1SAnirudh Venkataramanan u8 reserved2[2]; 12140ebd3ff1SAnirudh Venkataramanan __le32 addr_high; 12150ebd3ff1SAnirudh Venkataramanan __le32 addr_low; 12160ebd3ff1SAnirudh Venkataramanan }; 12170ebd3ff1SAnirudh Venkataramanan 12180ebd3ff1SAnirudh Venkataramanan /* Configure LLDP MIB Change Event (direct 0x0A01) */ 12190ebd3ff1SAnirudh Venkataramanan /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 12200ebd3ff1SAnirudh Venkataramanan struct ice_aqc_lldp_set_mib_change { 12210ebd3ff1SAnirudh Venkataramanan u8 command; 12220ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 12230ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 12240ebd3ff1SAnirudh Venkataramanan u8 reserved[15]; 12250ebd3ff1SAnirudh Venkataramanan }; 12260ebd3ff1SAnirudh Venkataramanan 12273a257a14SAnirudh Venkataramanan /* Stop LLDP (direct 0x0A05) */ 12283a257a14SAnirudh Venkataramanan struct ice_aqc_lldp_stop { 12293a257a14SAnirudh Venkataramanan u8 command; 12303a257a14SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 12313a257a14SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_STOP 0x0 12323a257a14SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 12333a257a14SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 12343a257a14SAnirudh Venkataramanan u8 reserved[15]; 12353a257a14SAnirudh Venkataramanan }; 12363a257a14SAnirudh Venkataramanan 123737b6f646SAnirudh Venkataramanan /* Start LLDP (direct 0x0A06) */ 123837b6f646SAnirudh Venkataramanan struct ice_aqc_lldp_start { 123937b6f646SAnirudh Venkataramanan u8 command; 124037b6f646SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_START BIT(0) 124137b6f646SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 124237b6f646SAnirudh Venkataramanan u8 reserved[15]; 124337b6f646SAnirudh Venkataramanan }; 124437b6f646SAnirudh Venkataramanan 12450ebd3ff1SAnirudh Venkataramanan /* Get CEE DCBX Oper Config (0x0A07) 12460ebd3ff1SAnirudh Venkataramanan * The command uses the generic descriptor struct and 12470ebd3ff1SAnirudh Venkataramanan * returns the struct below as an indirect response. 12480ebd3ff1SAnirudh Venkataramanan */ 12490ebd3ff1SAnirudh Venkataramanan struct ice_aqc_get_cee_dcb_cfg_resp { 12500ebd3ff1SAnirudh Venkataramanan u8 oper_num_tc; 12510ebd3ff1SAnirudh Venkataramanan u8 oper_prio_tc[4]; 12520ebd3ff1SAnirudh Venkataramanan u8 oper_tc_bw[8]; 12530ebd3ff1SAnirudh Venkataramanan u8 oper_pfc_en; 12540ebd3ff1SAnirudh Venkataramanan __le16 oper_app_prio; 12550ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_FCOE_S 0 12560ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 12570ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_ISCSI_S 3 12580ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 12590ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_FIP_S 8 12600ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 12610ebd3ff1SAnirudh Venkataramanan __le32 tlv_status; 12620ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_PG_STATUS_S 0 12630ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 12640ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_PFC_STATUS_S 3 12650ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 12660ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_FCOE_STATUS_S 8 12670ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 12680ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_ISCSI_STATUS_S 11 12690ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 12700ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_FIP_STATUS_S 16 12710ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 12720ebd3ff1SAnirudh Venkataramanan u8 reserved[12]; 12730ebd3ff1SAnirudh Venkataramanan }; 12740ebd3ff1SAnirudh Venkataramanan 12757b9ffc76SAnirudh Venkataramanan /* Set Local LLDP MIB (indirect 0x0A08) 12762f2da36eSAnirudh Venkataramanan * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 12777b9ffc76SAnirudh Venkataramanan */ 12787b9ffc76SAnirudh Venkataramanan struct ice_aqc_lldp_set_local_mib { 12797b9ffc76SAnirudh Venkataramanan u8 type; 12807b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 12817b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 12827b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 12837b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 12847b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 12857b9ffc76SAnirudh Venkataramanan u8 reserved0; 12867b9ffc76SAnirudh Venkataramanan __le16 length; 12877b9ffc76SAnirudh Venkataramanan u8 reserved1[4]; 12887b9ffc76SAnirudh Venkataramanan __le32 addr_high; 12897b9ffc76SAnirudh Venkataramanan __le32 addr_low; 12907b9ffc76SAnirudh Venkataramanan }; 12917b9ffc76SAnirudh Venkataramanan 129237b6f646SAnirudh Venkataramanan /* Stop/Start LLDP Agent (direct 0x0A09) 12932f2da36eSAnirudh Venkataramanan * Used for stopping/starting specific LLDP agent. e.g. DCBX. 129437b6f646SAnirudh Venkataramanan * The same structure is used for the response, with the command field 129537b6f646SAnirudh Venkataramanan * being used as the status field. 129637b6f646SAnirudh Venkataramanan */ 129737b6f646SAnirudh Venkataramanan struct ice_aqc_lldp_stop_start_specific_agent { 129837b6f646SAnirudh Venkataramanan u8 command; 129937b6f646SAnirudh Venkataramanan #define ICE_AQC_START_STOP_AGENT_M BIT(0) 130037b6f646SAnirudh Venkataramanan #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 130137b6f646SAnirudh Venkataramanan #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 130237b6f646SAnirudh Venkataramanan u8 reserved[15]; 130337b6f646SAnirudh Venkataramanan }; 130437b6f646SAnirudh Venkataramanan 1305d76a60baSAnirudh Venkataramanan /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1306d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_key { 1307d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1308d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1309d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1310d76a60baSAnirudh Venkataramanan __le16 vsi_id; 1311d76a60baSAnirudh Venkataramanan u8 reserved[6]; 1312d76a60baSAnirudh Venkataramanan __le32 addr_high; 1313d76a60baSAnirudh Venkataramanan __le32 addr_low; 1314d76a60baSAnirudh Venkataramanan }; 1315d76a60baSAnirudh Venkataramanan 1316d76a60baSAnirudh Venkataramanan #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1317d76a60baSAnirudh Venkataramanan #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1318b4b418b3SPaul Greenwalt #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1319b4b418b3SPaul Greenwalt (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1320b4b418b3SPaul Greenwalt ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1321d76a60baSAnirudh Venkataramanan 1322d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_keys { 1323d76a60baSAnirudh Venkataramanan u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1324d76a60baSAnirudh Venkataramanan u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1325d76a60baSAnirudh Venkataramanan }; 1326d76a60baSAnirudh Venkataramanan 1327d76a60baSAnirudh Venkataramanan /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1328d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_lut { 1329d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1330d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1331d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1332d76a60baSAnirudh Venkataramanan __le16 vsi_id; 1333d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1334d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1335d76a60baSAnirudh Venkataramanan (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1336d76a60baSAnirudh Venkataramanan 1337d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1338d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1339d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1340d76a60baSAnirudh Venkataramanan 1341d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1342d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1343d76a60baSAnirudh Venkataramanan (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1344d76a60baSAnirudh Venkataramanan 1345d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1346d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1347d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1348d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1349d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1350d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1351d76a60baSAnirudh Venkataramanan 1352d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1353d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1354d76a60baSAnirudh Venkataramanan (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1355d76a60baSAnirudh Venkataramanan 1356d76a60baSAnirudh Venkataramanan __le16 flags; 1357d76a60baSAnirudh Venkataramanan __le32 reserved; 1358d76a60baSAnirudh Venkataramanan __le32 addr_high; 1359d76a60baSAnirudh Venkataramanan __le32 addr_low; 1360d76a60baSAnirudh Venkataramanan }; 1361d76a60baSAnirudh Venkataramanan 1362f9867df6SAnirudh Venkataramanan /* Add Tx LAN Queues (indirect 0x0C30) */ 1363cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs { 1364cdedef59SAnirudh Venkataramanan u8 num_qgrps; 1365cdedef59SAnirudh Venkataramanan u8 reserved[3]; 1366cdedef59SAnirudh Venkataramanan __le32 reserved1; 1367cdedef59SAnirudh Venkataramanan __le32 addr_high; 1368cdedef59SAnirudh Venkataramanan __le32 addr_low; 1369cdedef59SAnirudh Venkataramanan }; 1370cdedef59SAnirudh Venkataramanan 1371f9867df6SAnirudh Venkataramanan /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1372cdedef59SAnirudh Venkataramanan * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1373cdedef59SAnirudh Venkataramanan */ 1374cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs_perq { 1375cdedef59SAnirudh Venkataramanan __le16 txq_id; 1376cdedef59SAnirudh Venkataramanan u8 rsvd[2]; 1377cdedef59SAnirudh Venkataramanan __le32 q_teid; 1378cdedef59SAnirudh Venkataramanan u8 txq_ctx[22]; 1379cdedef59SAnirudh Venkataramanan u8 rsvd2[2]; 1380cdedef59SAnirudh Venkataramanan struct ice_aqc_txsched_elem info; 1381cdedef59SAnirudh Venkataramanan }; 1382cdedef59SAnirudh Venkataramanan 1383f9867df6SAnirudh Venkataramanan /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 1384cdedef59SAnirudh Venkataramanan * is an array of the following structs. Please note that the length of 1385cdedef59SAnirudh Venkataramanan * each struct ice_aqc_add_tx_qgrp is variable due 1386cdedef59SAnirudh Venkataramanan * to the variable number of queues in each group! 1387cdedef59SAnirudh Venkataramanan */ 1388cdedef59SAnirudh Venkataramanan struct ice_aqc_add_tx_qgrp { 1389cdedef59SAnirudh Venkataramanan __le32 parent_teid; 1390cdedef59SAnirudh Venkataramanan u8 num_txqs; 1391cdedef59SAnirudh Venkataramanan u8 rsvd[3]; 1392cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs_perq txqs[1]; 1393cdedef59SAnirudh Venkataramanan }; 1394cdedef59SAnirudh Venkataramanan 1395f9867df6SAnirudh Venkataramanan /* Disable Tx LAN Queues (indirect 0x0C31) */ 1396cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txqs { 1397cdedef59SAnirudh Venkataramanan u8 cmd_type; 1398cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_S 0 1399cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1400cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1401cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1402cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1403cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1404cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1405cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1406cdedef59SAnirudh Venkataramanan u8 num_entries; 1407cdedef59SAnirudh Venkataramanan __le16 vmvf_and_timeout; 1408cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1409cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1410cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1411cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1412cdedef59SAnirudh Venkataramanan __le32 blocked_cgds; 1413cdedef59SAnirudh Venkataramanan __le32 addr_high; 1414cdedef59SAnirudh Venkataramanan __le32 addr_low; 1415cdedef59SAnirudh Venkataramanan }; 1416cdedef59SAnirudh Venkataramanan 1417f9867df6SAnirudh Venkataramanan /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 1418cdedef59SAnirudh Venkataramanan * contains the following structures, arrayed one after the 1419cdedef59SAnirudh Venkataramanan * other. 1420cdedef59SAnirudh Venkataramanan * Note: Since the q_id is 16 bits wide, if the 1421cdedef59SAnirudh Venkataramanan * number of queues is even, then 2 bytes of alignment MUST be 1422cdedef59SAnirudh Venkataramanan * added before the start of the next group, to allow correct 1423cdedef59SAnirudh Venkataramanan * alignment of the parent_teid field. 1424cdedef59SAnirudh Venkataramanan */ 1425cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txq_item { 1426cdedef59SAnirudh Venkataramanan __le32 parent_teid; 1427cdedef59SAnirudh Venkataramanan u8 num_qs; 1428cdedef59SAnirudh Venkataramanan u8 rsvd; 1429cdedef59SAnirudh Venkataramanan /* The length of the q_id array varies according to num_qs */ 1430cdedef59SAnirudh Venkataramanan __le16 q_id[1]; 1431cdedef59SAnirudh Venkataramanan /* This only applies from F8 onward */ 1432cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1433cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1434cdedef59SAnirudh Venkataramanan (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1435cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1436cdedef59SAnirudh Venkataramanan (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1437cdedef59SAnirudh Venkataramanan }; 1438cdedef59SAnirudh Venkataramanan 1439cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txq { 1440cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txq_item qgrps[1]; 1441cdedef59SAnirudh Venkataramanan }; 1442cdedef59SAnirudh Venkataramanan 14438b97ceb1SHieu Tran /* Configure Firmware Logging Command (indirect 0xFF09) 14448b97ceb1SHieu Tran * Logging Information Read Response (indirect 0xFF10) 14458b97ceb1SHieu Tran * Note: The 0xFF10 command has no input parameters. 14468b97ceb1SHieu Tran */ 14478b97ceb1SHieu Tran struct ice_aqc_fw_logging { 14488b97ceb1SHieu Tran u8 log_ctrl; 14498b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 14508b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_UART_EN BIT(1) 14518b97ceb1SHieu Tran u8 rsvd0; 14528b97ceb1SHieu Tran u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 14538b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 14548b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 14558b97ceb1SHieu Tran u8 rsvd1[5]; 14568b97ceb1SHieu Tran __le32 addr_high; 14578b97ceb1SHieu Tran __le32 addr_low; 14588b97ceb1SHieu Tran }; 14598b97ceb1SHieu Tran 14608b97ceb1SHieu Tran enum ice_aqc_fw_logging_mod { 14618b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_GENERAL = 0, 14628b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_CTRL, 14638b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_LINK, 14648b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_LINK_TOPO, 14658b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_DNL, 14668b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_I2C, 14678b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_SDP, 14688b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_MDIO, 14698b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_ADMINQ, 14708b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_HDMA, 14718b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_LLDP, 14728b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_DCBX, 14738b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_DCB, 14748b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_NETPROXY, 14758b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_NVM, 14768b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_AUTH, 14778b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_VPD, 14788b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_IOSF, 14798b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_PARSER, 14808b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_SW, 14818b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_SCHEDULER, 14828b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_TXQ, 14838b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_RSVD, 14848b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_POST, 14858b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_WATCHDOG, 14868b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 14878b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_MNG, 14888b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_MAX, 14898b97ceb1SHieu Tran }; 14908b97ceb1SHieu Tran 14918b97ceb1SHieu Tran /* This is the buffer for both of the logging commands. 14928b97ceb1SHieu Tran * The entry array size depends on the datalen parameter in the descriptor. 14938b97ceb1SHieu Tran * There will be a total of datalen / 2 entries. 14948b97ceb1SHieu Tran */ 14958b97ceb1SHieu Tran struct ice_aqc_fw_logging_data { 14968b97ceb1SHieu Tran __le16 entry[1]; 14978b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_ID_S 0 14988b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 14998b97ceb1SHieu Tran 15008b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 15018b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 15028b97ceb1SHieu Tran 15038b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_EN_S 12 15048b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 15058b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 15068b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 15078b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 15088b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 15098b97ceb1SHieu Tran }; 15108b97ceb1SHieu Tran 15118b97ceb1SHieu Tran /* Get/Clear FW Log (indirect 0xFF11) */ 15128b97ceb1SHieu Tran struct ice_aqc_get_clear_fw_log { 15138b97ceb1SHieu Tran u8 flags; 15148b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_CLEAR BIT(0) 15158b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 15168b97ceb1SHieu Tran u8 rsvd1[7]; 15178b97ceb1SHieu Tran __le32 addr_high; 15188b97ceb1SHieu Tran __le32 addr_low; 15198b97ceb1SHieu Tran }; 15208b97ceb1SHieu Tran 15217ec59eeaSAnirudh Venkataramanan /** 15227ec59eeaSAnirudh Venkataramanan * struct ice_aq_desc - Admin Queue (AQ) descriptor 15237ec59eeaSAnirudh Venkataramanan * @flags: ICE_AQ_FLAG_* flags 15247ec59eeaSAnirudh Venkataramanan * @opcode: AQ command opcode 15257ec59eeaSAnirudh Venkataramanan * @datalen: length in bytes of indirect/external data buffer 15267ec59eeaSAnirudh Venkataramanan * @retval: return value from firmware 15277ec59eeaSAnirudh Venkataramanan * @cookie_h: opaque data high-half 15287ec59eeaSAnirudh Venkataramanan * @cookie_l: opaque data low-half 15297ec59eeaSAnirudh Venkataramanan * @params: command-specific parameters 15307ec59eeaSAnirudh Venkataramanan * 15317ec59eeaSAnirudh Venkataramanan * Descriptor format for commands the driver posts on the Admin Transmit Queue 15327ec59eeaSAnirudh Venkataramanan * (ATQ). The firmware writes back onto the command descriptor and returns 15337ec59eeaSAnirudh Venkataramanan * the result of the command. Asynchronous events that are not an immediate 15347ec59eeaSAnirudh Venkataramanan * result of the command are written to the Admin Receive Queue (ARQ) using 15357ec59eeaSAnirudh Venkataramanan * the same descriptor format. Descriptors are in little-endian notation with 15367ec59eeaSAnirudh Venkataramanan * 32-bit words. 15377ec59eeaSAnirudh Venkataramanan */ 15387ec59eeaSAnirudh Venkataramanan struct ice_aq_desc { 15397ec59eeaSAnirudh Venkataramanan __le16 flags; 15407ec59eeaSAnirudh Venkataramanan __le16 opcode; 15417ec59eeaSAnirudh Venkataramanan __le16 datalen; 15427ec59eeaSAnirudh Venkataramanan __le16 retval; 15437ec59eeaSAnirudh Venkataramanan __le32 cookie_high; 15447ec59eeaSAnirudh Venkataramanan __le32 cookie_low; 15457ec59eeaSAnirudh Venkataramanan union { 15467ec59eeaSAnirudh Venkataramanan u8 raw[16]; 15477ec59eeaSAnirudh Venkataramanan struct ice_aqc_generic generic; 15487ec59eeaSAnirudh Venkataramanan struct ice_aqc_get_ver get_ver; 15497ec59eeaSAnirudh Venkataramanan struct ice_aqc_q_shutdown q_shutdown; 1550f31e4b6fSAnirudh Venkataramanan struct ice_aqc_req_res res_owner; 1551dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read mac_read; 1552e94d4478SAnirudh Venkataramanan struct ice_aqc_manage_mac_write mac_write; 1553f31e4b6fSAnirudh Venkataramanan struct ice_aqc_clear_pxe clear_pxe; 15549c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps get_cap; 1555dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps get_phy; 1556fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg set_phy; 1557fcea6f3dSAnirudh Venkataramanan struct ice_aqc_restart_an restart_an; 15588e151d50SAnirudh Venkataramanan struct ice_aqc_set_port_id_led set_port_id_led; 15599c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg get_sw_conf; 15609daf8208SAnirudh Venkataramanan struct ice_aqc_sw_rules sw_rules; 1561dc49c772SAnirudh Venkataramanan struct ice_aqc_get_topo get_topo; 15621f9c7840SAnirudh Venkataramanan struct ice_aqc_sched_elem_cmd sched_elem_cmd; 15639c20346bSAnirudh Venkataramanan struct ice_aqc_query_txsched_res query_sched_res; 15647b9ffc76SAnirudh Venkataramanan struct ice_aqc_query_port_ets port_ets; 1565f31e4b6fSAnirudh Venkataramanan struct ice_aqc_nvm nvm; 15660e674aebSAnirudh Venkataramanan struct ice_aqc_nvm_checksum nvm_checksum; 1567007676b4SAnirudh Venkataramanan struct ice_aqc_pf_vf_msg virt; 15680ebd3ff1SAnirudh Venkataramanan struct ice_aqc_lldp_get_mib lldp_get_mib; 15690ebd3ff1SAnirudh Venkataramanan struct ice_aqc_lldp_set_mib_change lldp_set_event; 15703a257a14SAnirudh Venkataramanan struct ice_aqc_lldp_stop lldp_stop; 157137b6f646SAnirudh Venkataramanan struct ice_aqc_lldp_start lldp_start; 15727b9ffc76SAnirudh Venkataramanan struct ice_aqc_lldp_set_local_mib lldp_set_mib; 157337b6f646SAnirudh Venkataramanan struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 1574d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_lut get_set_rss_lut; 1575d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_key get_set_rss_key; 1576cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs add_txqs; 1577cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txqs dis_txqs; 15783a858ba3SAnirudh Venkataramanan struct ice_aqc_add_get_update_free_vsi vsi_cmd; 15790f9d5027SAnirudh Venkataramanan struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 15808b97ceb1SHieu Tran struct ice_aqc_fw_logging fw_logging; 15818b97ceb1SHieu Tran struct ice_aqc_get_clear_fw_log get_clear_fw_log; 15820e674aebSAnirudh Venkataramanan struct ice_aqc_set_mac_lb set_mac_lb; 15839daf8208SAnirudh Venkataramanan struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 15840b28b702SAnirudh Venkataramanan struct ice_aqc_set_event_mask set_event_mask; 1585dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status get_link_status; 15867ec59eeaSAnirudh Venkataramanan } params; 15877ec59eeaSAnirudh Venkataramanan }; 15887ec59eeaSAnirudh Venkataramanan 15897ec59eeaSAnirudh Venkataramanan /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 15907ec59eeaSAnirudh Venkataramanan #define ICE_AQ_LG_BUF 512 15917ec59eeaSAnirudh Venkataramanan 1592940b61afSAnirudh Venkataramanan #define ICE_AQ_FLAG_ERR_S 2 15937ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_LB_S 9 15949c20346bSAnirudh Venkataramanan #define ICE_AQ_FLAG_RD_S 10 15957ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_BUF_S 12 15967ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_SI_S 13 15977ec59eeaSAnirudh Venkataramanan 1598940b61afSAnirudh Venkataramanan #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 15997ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 16009c20346bSAnirudh Venkataramanan #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 16017ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 16027ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 16037ec59eeaSAnirudh Venkataramanan 16047ec59eeaSAnirudh Venkataramanan /* error codes */ 16057ec59eeaSAnirudh Venkataramanan enum ice_aq_err { 1606df17b7e0SAnirudh Venkataramanan ICE_AQ_RC_OK = 0, /* Success */ 16070ebd3ff1SAnirudh Venkataramanan ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 16080ebd3ff1SAnirudh Venkataramanan ICE_AQ_RC_ENOENT = 2, /* No such element */ 16099c20346bSAnirudh Venkataramanan ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 1610f31e4b6fSAnirudh Venkataramanan ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1611df17b7e0SAnirudh Venkataramanan ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 1612e94d4478SAnirudh Venkataramanan ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 161390e47737SMitch Williams ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 16147ec59eeaSAnirudh Venkataramanan }; 16157ec59eeaSAnirudh Venkataramanan 16167ec59eeaSAnirudh Venkataramanan /* Admin Queue command opcodes */ 16177ec59eeaSAnirudh Venkataramanan enum ice_adminq_opc { 16187ec59eeaSAnirudh Venkataramanan /* AQ commands */ 16197ec59eeaSAnirudh Venkataramanan ice_aqc_opc_get_ver = 0x0001, 16207ec59eeaSAnirudh Venkataramanan ice_aqc_opc_q_shutdown = 0x0003, 1621f31e4b6fSAnirudh Venkataramanan 1622f31e4b6fSAnirudh Venkataramanan /* resource ownership */ 1623f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_req_res = 0x0008, 1624f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_release_res = 0x0009, 1625f31e4b6fSAnirudh Venkataramanan 16269c20346bSAnirudh Venkataramanan /* device/function capabilities */ 16279c20346bSAnirudh Venkataramanan ice_aqc_opc_list_func_caps = 0x000A, 16289c20346bSAnirudh Venkataramanan ice_aqc_opc_list_dev_caps = 0x000B, 16299c20346bSAnirudh Venkataramanan 1630dc49c772SAnirudh Venkataramanan /* manage MAC address */ 1631dc49c772SAnirudh Venkataramanan ice_aqc_opc_manage_mac_read = 0x0107, 1632e94d4478SAnirudh Venkataramanan ice_aqc_opc_manage_mac_write = 0x0108, 1633dc49c772SAnirudh Venkataramanan 1634f31e4b6fSAnirudh Venkataramanan /* PXE */ 1635f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_clear_pxe_mode = 0x0110, 1636f31e4b6fSAnirudh Venkataramanan 16379c20346bSAnirudh Venkataramanan /* internal switch commands */ 16389c20346bSAnirudh Venkataramanan ice_aqc_opc_get_sw_cfg = 0x0200, 16399c20346bSAnirudh Venkataramanan 16409daf8208SAnirudh Venkataramanan /* Alloc/Free/Get Resources */ 16419daf8208SAnirudh Venkataramanan ice_aqc_opc_alloc_res = 0x0208, 16429daf8208SAnirudh Venkataramanan ice_aqc_opc_free_res = 0x0209, 16439daf8208SAnirudh Venkataramanan 16443a858ba3SAnirudh Venkataramanan /* VSI commands */ 16453a858ba3SAnirudh Venkataramanan ice_aqc_opc_add_vsi = 0x0210, 16463a858ba3SAnirudh Venkataramanan ice_aqc_opc_update_vsi = 0x0211, 16473a858ba3SAnirudh Venkataramanan ice_aqc_opc_free_vsi = 0x0213, 16489daf8208SAnirudh Venkataramanan 16499daf8208SAnirudh Venkataramanan /* switch rules population commands */ 16509daf8208SAnirudh Venkataramanan ice_aqc_opc_add_sw_rules = 0x02A0, 16519daf8208SAnirudh Venkataramanan ice_aqc_opc_update_sw_rules = 0x02A1, 16529daf8208SAnirudh Venkataramanan ice_aqc_opc_remove_sw_rules = 0x02A2, 16539daf8208SAnirudh Venkataramanan 1654f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_clear_pf_cfg = 0x02A4, 1655f31e4b6fSAnirudh Venkataramanan 16569c20346bSAnirudh Venkataramanan /* transmit scheduler commands */ 1657dc49c772SAnirudh Venkataramanan ice_aqc_opc_get_dflt_topo = 0x0400, 16585513b920SAnirudh Venkataramanan ice_aqc_opc_add_sched_elems = 0x0401, 165956daee6cSAnirudh Venkataramanan ice_aqc_opc_get_sched_elems = 0x0404, 16605513b920SAnirudh Venkataramanan ice_aqc_opc_suspend_sched_elems = 0x0409, 16615513b920SAnirudh Venkataramanan ice_aqc_opc_resume_sched_elems = 0x040A, 16627b9ffc76SAnirudh Venkataramanan ice_aqc_opc_query_port_ets = 0x040E, 16639c20346bSAnirudh Venkataramanan ice_aqc_opc_delete_sched_elems = 0x040F, 16649c20346bSAnirudh Venkataramanan ice_aqc_opc_query_sched_res = 0x0412, 16659c20346bSAnirudh Venkataramanan 1666dc49c772SAnirudh Venkataramanan /* PHY commands */ 1667dc49c772SAnirudh Venkataramanan ice_aqc_opc_get_phy_caps = 0x0600, 1668fcea6f3dSAnirudh Venkataramanan ice_aqc_opc_set_phy_cfg = 0x0601, 1669fcea6f3dSAnirudh Venkataramanan ice_aqc_opc_restart_an = 0x0605, 1670dc49c772SAnirudh Venkataramanan ice_aqc_opc_get_link_status = 0x0607, 16710b28b702SAnirudh Venkataramanan ice_aqc_opc_set_event_mask = 0x0613, 16720e674aebSAnirudh Venkataramanan ice_aqc_opc_set_mac_lb = 0x0620, 16738e151d50SAnirudh Venkataramanan ice_aqc_opc_set_port_id_led = 0x06E9, 1674dc49c772SAnirudh Venkataramanan 1675f31e4b6fSAnirudh Venkataramanan /* NVM commands */ 1676f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_nvm_read = 0x0701, 16770e674aebSAnirudh Venkataramanan ice_aqc_opc_nvm_checksum = 0x0706, 1678f31e4b6fSAnirudh Venkataramanan 1679007676b4SAnirudh Venkataramanan /* PF/VF mailbox commands */ 16801071a835SAnirudh Venkataramanan ice_mbx_opc_send_msg_to_pf = 0x0801, 1681007676b4SAnirudh Venkataramanan ice_mbx_opc_send_msg_to_vf = 0x0802, 168237b6f646SAnirudh Venkataramanan /* LLDP commands */ 16830ebd3ff1SAnirudh Venkataramanan ice_aqc_opc_lldp_get_mib = 0x0A00, 16840ebd3ff1SAnirudh Venkataramanan ice_aqc_opc_lldp_set_mib_change = 0x0A01, 16853a257a14SAnirudh Venkataramanan ice_aqc_opc_lldp_stop = 0x0A05, 168637b6f646SAnirudh Venkataramanan ice_aqc_opc_lldp_start = 0x0A06, 16870ebd3ff1SAnirudh Venkataramanan ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 16887b9ffc76SAnirudh Venkataramanan ice_aqc_opc_lldp_set_local_mib = 0x0A08, 168937b6f646SAnirudh Venkataramanan ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 1690007676b4SAnirudh Venkataramanan 1691d76a60baSAnirudh Venkataramanan /* RSS commands */ 1692d76a60baSAnirudh Venkataramanan ice_aqc_opc_set_rss_key = 0x0B02, 1693d76a60baSAnirudh Venkataramanan ice_aqc_opc_set_rss_lut = 0x0B03, 1694d76a60baSAnirudh Venkataramanan ice_aqc_opc_get_rss_key = 0x0B04, 1695d76a60baSAnirudh Venkataramanan ice_aqc_opc_get_rss_lut = 0x0B05, 1696d76a60baSAnirudh Venkataramanan 1697f9867df6SAnirudh Venkataramanan /* Tx queue handling commands/events */ 1698cdedef59SAnirudh Venkataramanan ice_aqc_opc_add_txqs = 0x0C30, 1699cdedef59SAnirudh Venkataramanan ice_aqc_opc_dis_txqs = 0x0C31, 17008b97ceb1SHieu Tran 17018b97ceb1SHieu Tran /* debug commands */ 17028b97ceb1SHieu Tran ice_aqc_opc_fw_logging = 0xFF09, 170311fe1b3aSDan Nowlin ice_aqc_opc_fw_logging_info = 0xFF10, 17047ec59eeaSAnirudh Venkataramanan }; 17057ec59eeaSAnirudh Venkataramanan 17067ec59eeaSAnirudh Venkataramanan #endif /* _ICE_ADMINQ_CMD_H_ */ 1707