17ec59eeaSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 27ec59eeaSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 37ec59eeaSAnirudh Venkataramanan 47ec59eeaSAnirudh Venkataramanan #ifndef _ICE_ADMINQ_CMD_H_ 57ec59eeaSAnirudh Venkataramanan #define _ICE_ADMINQ_CMD_H_ 67ec59eeaSAnirudh Venkataramanan 77ec59eeaSAnirudh Venkataramanan /* This header file defines the Admin Queue commands, error codes and 87ec59eeaSAnirudh Venkataramanan * descriptor format. It is shared between Firmware and Software. 97ec59eeaSAnirudh Venkataramanan */ 107ec59eeaSAnirudh Venkataramanan 119daf8208SAnirudh Venkataramanan #define ICE_MAX_VSI 768 129c20346bSAnirudh Venkataramanan #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 133a858ba3SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 149c20346bSAnirudh Venkataramanan 157ec59eeaSAnirudh Venkataramanan struct ice_aqc_generic { 167ec59eeaSAnirudh Venkataramanan __le32 param0; 177ec59eeaSAnirudh Venkataramanan __le32 param1; 187ec59eeaSAnirudh Venkataramanan __le32 addr_high; 197ec59eeaSAnirudh Venkataramanan __le32 addr_low; 207ec59eeaSAnirudh Venkataramanan }; 217ec59eeaSAnirudh Venkataramanan 227ec59eeaSAnirudh Venkataramanan /* Get version (direct 0x0001) */ 237ec59eeaSAnirudh Venkataramanan struct ice_aqc_get_ver { 247ec59eeaSAnirudh Venkataramanan __le32 rom_ver; 257ec59eeaSAnirudh Venkataramanan __le32 fw_build; 267ec59eeaSAnirudh Venkataramanan u8 fw_branch; 277ec59eeaSAnirudh Venkataramanan u8 fw_major; 287ec59eeaSAnirudh Venkataramanan u8 fw_minor; 297ec59eeaSAnirudh Venkataramanan u8 fw_patch; 307ec59eeaSAnirudh Venkataramanan u8 api_branch; 317ec59eeaSAnirudh Venkataramanan u8 api_major; 327ec59eeaSAnirudh Venkataramanan u8 api_minor; 337ec59eeaSAnirudh Venkataramanan u8 api_patch; 347ec59eeaSAnirudh Venkataramanan }; 357ec59eeaSAnirudh Venkataramanan 367ec59eeaSAnirudh Venkataramanan /* Queue Shutdown (direct 0x0003) */ 377ec59eeaSAnirudh Venkataramanan struct ice_aqc_q_shutdown { 387ec59eeaSAnirudh Venkataramanan #define ICE_AQC_DRIVER_UNLOADING BIT(0) 397ec59eeaSAnirudh Venkataramanan __le32 driver_unloading; 407ec59eeaSAnirudh Venkataramanan u8 reserved[12]; 417ec59eeaSAnirudh Venkataramanan }; 427ec59eeaSAnirudh Venkataramanan 43f31e4b6fSAnirudh Venkataramanan /* Request resource ownership (direct 0x0008) 44f31e4b6fSAnirudh Venkataramanan * Release resource ownership (direct 0x0009) 45f31e4b6fSAnirudh Venkataramanan */ 46f31e4b6fSAnirudh Venkataramanan struct ice_aqc_req_res { 47f31e4b6fSAnirudh Venkataramanan __le16 res_id; 48f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_NVM 1 49f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_SDP 2 50f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_CHNG_LOCK 3 51f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_GLBL_LOCK 4 52f31e4b6fSAnirudh Venkataramanan __le16 access_type; 53f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ACCESS_READ 1 54f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ACCESS_WRITE 2 55f31e4b6fSAnirudh Venkataramanan 56f31e4b6fSAnirudh Venkataramanan /* Upon successful completion, FW writes this value and driver is 57f31e4b6fSAnirudh Venkataramanan * expected to release resource before timeout. This value is provided 58f31e4b6fSAnirudh Venkataramanan * in milliseconds. 59f31e4b6fSAnirudh Venkataramanan */ 60f31e4b6fSAnirudh Venkataramanan __le32 timeout; 61f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 62f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 63f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 64f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 65f31e4b6fSAnirudh Venkataramanan /* For SDP: pin id of the SDP */ 66f31e4b6fSAnirudh Venkataramanan __le32 res_number; 67f31e4b6fSAnirudh Venkataramanan /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 68f31e4b6fSAnirudh Venkataramanan __le16 status; 69f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_SUCCESS 0 70f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_IN_PROG 1 71f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_DONE 2 72f31e4b6fSAnirudh Venkataramanan u8 reserved[2]; 73f31e4b6fSAnirudh Venkataramanan }; 74f31e4b6fSAnirudh Venkataramanan 759c20346bSAnirudh Venkataramanan /* Get function capabilities (indirect 0x000A) 769c20346bSAnirudh Venkataramanan * Get device capabilities (indirect 0x000B) 779c20346bSAnirudh Venkataramanan */ 789c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps { 799c20346bSAnirudh Venkataramanan u8 cmd_flags; 809c20346bSAnirudh Venkataramanan u8 pf_index; 819c20346bSAnirudh Venkataramanan u8 reserved[2]; 829c20346bSAnirudh Venkataramanan __le32 count; 839c20346bSAnirudh Venkataramanan __le32 addr_high; 849c20346bSAnirudh Venkataramanan __le32 addr_low; 859c20346bSAnirudh Venkataramanan }; 869c20346bSAnirudh Venkataramanan 879c20346bSAnirudh Venkataramanan /* Device/Function buffer entry, repeated per reported capability */ 889c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps_elem { 899c20346bSAnirudh Venkataramanan __le16 cap; 90995c90f2SAnirudh Venkataramanan #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 9175d2b253SAnirudh Venkataramanan #define ICE_AQC_CAPS_SRIOV 0x0012 9275d2b253SAnirudh Venkataramanan #define ICE_AQC_CAPS_VF 0x0013 939c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_VSI 0x0017 949c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_RSS 0x0040 959c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_RXQS 0x0041 969c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_TXQS 0x0042 979c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_MSIX 0x0043 989c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_MAX_MTU 0x0047 999c20346bSAnirudh Venkataramanan 1009c20346bSAnirudh Venkataramanan u8 major_ver; 1019c20346bSAnirudh Venkataramanan u8 minor_ver; 1029c20346bSAnirudh Venkataramanan /* Number of resources described by this capability */ 1039c20346bSAnirudh Venkataramanan __le32 number; 1049c20346bSAnirudh Venkataramanan /* Only meaningful for some types of resources */ 1059c20346bSAnirudh Venkataramanan __le32 logical_id; 1069c20346bSAnirudh Venkataramanan /* Only meaningful for some types of resources */ 1079c20346bSAnirudh Venkataramanan __le32 phys_id; 1089c20346bSAnirudh Venkataramanan __le64 rsvd1; 1099c20346bSAnirudh Venkataramanan __le64 rsvd2; 1109c20346bSAnirudh Venkataramanan }; 1119c20346bSAnirudh Venkataramanan 112dc49c772SAnirudh Venkataramanan /* Manage MAC address, read command - indirect (0x0107) 113dc49c772SAnirudh Venkataramanan * This struct is also used for the response 114dc49c772SAnirudh Venkataramanan */ 115dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read { 116dc49c772SAnirudh Venkataramanan __le16 flags; /* Zeroed by device driver */ 117dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 118dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 119dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 120dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 121dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_READ_S 4 122dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 123dc49c772SAnirudh Venkataramanan u8 lport_num; 124dc49c772SAnirudh Venkataramanan u8 lport_num_valid; 125dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID BIT(0) 126dc49c772SAnirudh Venkataramanan u8 num_addr; /* Used in response */ 127dc49c772SAnirudh Venkataramanan u8 reserved[3]; 128dc49c772SAnirudh Venkataramanan __le32 addr_high; 129dc49c772SAnirudh Venkataramanan __le32 addr_low; 130dc49c772SAnirudh Venkataramanan }; 131dc49c772SAnirudh Venkataramanan 132dc49c772SAnirudh Venkataramanan /* Response buffer format for manage MAC read command */ 133dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read_resp { 134dc49c772SAnirudh Venkataramanan u8 lport_num; 135dc49c772SAnirudh Venkataramanan u8 addr_type; 136dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 137dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 138dc49c772SAnirudh Venkataramanan u8 mac_addr[ETH_ALEN]; 139dc49c772SAnirudh Venkataramanan }; 140dc49c772SAnirudh Venkataramanan 141e94d4478SAnirudh Venkataramanan /* Manage MAC address, write command - direct (0x0108) */ 142e94d4478SAnirudh Venkataramanan struct ice_aqc_manage_mac_write { 143e94d4478SAnirudh Venkataramanan u8 port_num; 144e94d4478SAnirudh Venkataramanan u8 flags; 145e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 146e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 147e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WR_S 6 148e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S) 149e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 150e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S) 151e94d4478SAnirudh Venkataramanan /* High 16 bits of MAC address in big endian order */ 152e94d4478SAnirudh Venkataramanan __be16 sah; 153e94d4478SAnirudh Venkataramanan /* Low 32 bits of MAC address in big endian order */ 154e94d4478SAnirudh Venkataramanan __be32 sal; 155e94d4478SAnirudh Venkataramanan __le32 addr_high; 156e94d4478SAnirudh Venkataramanan __le32 addr_low; 157e94d4478SAnirudh Venkataramanan }; 158e94d4478SAnirudh Venkataramanan 159f31e4b6fSAnirudh Venkataramanan /* Clear PXE Command and response (direct 0x0110) */ 160f31e4b6fSAnirudh Venkataramanan struct ice_aqc_clear_pxe { 161f31e4b6fSAnirudh Venkataramanan u8 rx_cnt; 162f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 163f31e4b6fSAnirudh Venkataramanan u8 reserved[15]; 164f31e4b6fSAnirudh Venkataramanan }; 165f31e4b6fSAnirudh Venkataramanan 1669c20346bSAnirudh Venkataramanan /* Get switch configuration (0x0200) */ 1679c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg { 1689c20346bSAnirudh Venkataramanan /* Reserved for command and copy of request flags for response */ 1699c20346bSAnirudh Venkataramanan __le16 flags; 1709c20346bSAnirudh Venkataramanan /* First desc in case of command and next_elem in case of response 1719c20346bSAnirudh Venkataramanan * In case of response, if it is not zero, means all the configuration 1729c20346bSAnirudh Venkataramanan * was not returned and new command shall be sent with this value in 1739c20346bSAnirudh Venkataramanan * the 'first desc' field 1749c20346bSAnirudh Venkataramanan */ 1759c20346bSAnirudh Venkataramanan __le16 element; 1769c20346bSAnirudh Venkataramanan /* Reserved for command, only used for response */ 1779c20346bSAnirudh Venkataramanan __le16 num_elems; 1789c20346bSAnirudh Venkataramanan __le16 rsvd; 1799c20346bSAnirudh Venkataramanan __le32 addr_high; 1809c20346bSAnirudh Venkataramanan __le32 addr_low; 1819c20346bSAnirudh Venkataramanan }; 1829c20346bSAnirudh Venkataramanan 1839c20346bSAnirudh Venkataramanan /* Each entry in the response buffer is of the following type: */ 1849c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg_resp_elem { 1859c20346bSAnirudh Venkataramanan /* VSI/Port Number */ 1869c20346bSAnirudh Venkataramanan __le16 vsi_port_num; 1879c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 1889c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 1899c20346bSAnirudh Venkataramanan (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 1909c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 1919c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 1929c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 1939c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 1949c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 1959c20346bSAnirudh Venkataramanan 1969c20346bSAnirudh Venkataramanan /* SWID VSI/Port belongs to */ 1979c20346bSAnirudh Venkataramanan __le16 swid; 1989c20346bSAnirudh Venkataramanan 1999c20346bSAnirudh Venkataramanan /* Bit 14..0 : PF/VF number VSI belongs to 2009c20346bSAnirudh Venkataramanan * Bit 15 : VF indication bit 2019c20346bSAnirudh Venkataramanan */ 2029c20346bSAnirudh Venkataramanan __le16 pf_vf_num; 2039c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 2049c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 2059c20346bSAnirudh Venkataramanan (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 2069c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 2079c20346bSAnirudh Venkataramanan }; 2089c20346bSAnirudh Venkataramanan 2099c20346bSAnirudh Venkataramanan /* The response buffer is as follows. Note that the length of the 2109c20346bSAnirudh Venkataramanan * elements array varies with the length of the command response. 2119c20346bSAnirudh Venkataramanan */ 2129c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg_resp { 2139c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg_resp_elem elements[1]; 2149c20346bSAnirudh Venkataramanan }; 2159c20346bSAnirudh Venkataramanan 2169daf8208SAnirudh Venkataramanan /* These resource type defines are used for all switch resource 2179daf8208SAnirudh Venkataramanan * commands where a resource type is required, such as: 2189daf8208SAnirudh Venkataramanan * Get Resource Allocation command (indirect 0x0204) 2199daf8208SAnirudh Venkataramanan * Allocate Resources command (indirect 0x0208) 2209daf8208SAnirudh Venkataramanan * Free Resources command (indirect 0x0209) 2219daf8208SAnirudh Venkataramanan * Get Allocated Resource Descriptors Command (indirect 0x020A) 2229daf8208SAnirudh Venkataramanan */ 2239daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 2249daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 2259daf8208SAnirudh Venkataramanan 2269daf8208SAnirudh Venkataramanan /* Allocate Resources command (indirect 0x0208) 2279daf8208SAnirudh Venkataramanan * Free Resources command (indirect 0x0209) 2289daf8208SAnirudh Venkataramanan */ 2299daf8208SAnirudh Venkataramanan struct ice_aqc_alloc_free_res_cmd { 2309daf8208SAnirudh Venkataramanan __le16 num_entries; /* Number of Resource entries */ 2319daf8208SAnirudh Venkataramanan u8 reserved[6]; 2329daf8208SAnirudh Venkataramanan __le32 addr_high; 2339daf8208SAnirudh Venkataramanan __le32 addr_low; 2349daf8208SAnirudh Venkataramanan }; 2359daf8208SAnirudh Venkataramanan 2369daf8208SAnirudh Venkataramanan /* Resource descriptor */ 2379daf8208SAnirudh Venkataramanan struct ice_aqc_res_elem { 2389daf8208SAnirudh Venkataramanan union { 2399daf8208SAnirudh Venkataramanan __le16 sw_resp; 2409daf8208SAnirudh Venkataramanan __le16 flu_resp; 2419daf8208SAnirudh Venkataramanan } e; 2429daf8208SAnirudh Venkataramanan }; 2439daf8208SAnirudh Venkataramanan 2449daf8208SAnirudh Venkataramanan /* Buffer for Allocate/Free Resources commands */ 2459daf8208SAnirudh Venkataramanan struct ice_aqc_alloc_free_res_elem { 2469daf8208SAnirudh Venkataramanan __le16 res_type; /* Types defined above cmd 0x0204 */ 2479daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_SHARED_S 7 2489daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 2499daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 2509daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 2519daf8208SAnirudh Venkataramanan (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 2529daf8208SAnirudh Venkataramanan __le16 num_elems; 2539daf8208SAnirudh Venkataramanan struct ice_aqc_res_elem elem[1]; 2549daf8208SAnirudh Venkataramanan }; 2559daf8208SAnirudh Venkataramanan 2563a858ba3SAnirudh Venkataramanan /* Add VSI (indirect 0x0210) 2573a858ba3SAnirudh Venkataramanan * Update VSI (indirect 0x0211) 2583a858ba3SAnirudh Venkataramanan * Get VSI (indirect 0x0212) 2593a858ba3SAnirudh Venkataramanan * Free VSI (indirect 0x0213) 2603a858ba3SAnirudh Venkataramanan */ 2613a858ba3SAnirudh Venkataramanan struct ice_aqc_add_get_update_free_vsi { 2623a858ba3SAnirudh Venkataramanan __le16 vsi_num; 2633a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_NUM_S 0 2643a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 2653a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_IS_VALID BIT(15) 2663a858ba3SAnirudh Venkataramanan __le16 cmd_flags; 2673a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_KEEP_ALLOC 0x1 2683a858ba3SAnirudh Venkataramanan u8 vf_id; 2693a858ba3SAnirudh Venkataramanan u8 reserved; 2703a858ba3SAnirudh Venkataramanan __le16 vsi_flags; 2713a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_S 0 2723a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 2733a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_VF 0x0 2743a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 2753a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_PF 0x2 2763a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 2773a858ba3SAnirudh Venkataramanan __le32 addr_high; 2783a858ba3SAnirudh Venkataramanan __le32 addr_low; 2793a858ba3SAnirudh Venkataramanan }; 2803a858ba3SAnirudh Venkataramanan 2813a858ba3SAnirudh Venkataramanan /* Response descriptor for: 2823a858ba3SAnirudh Venkataramanan * Add VSI (indirect 0x0210) 2833a858ba3SAnirudh Venkataramanan * Update VSI (indirect 0x0211) 2843a858ba3SAnirudh Venkataramanan * Free VSI (indirect 0x0213) 2853a858ba3SAnirudh Venkataramanan */ 2863a858ba3SAnirudh Venkataramanan struct ice_aqc_add_update_free_vsi_resp { 2873a858ba3SAnirudh Venkataramanan __le16 vsi_num; 2883a858ba3SAnirudh Venkataramanan __le16 ext_status; 2893a858ba3SAnirudh Venkataramanan __le16 vsi_used; 2903a858ba3SAnirudh Venkataramanan __le16 vsi_free; 2913a858ba3SAnirudh Venkataramanan __le32 addr_high; 2923a858ba3SAnirudh Venkataramanan __le32 addr_low; 2933a858ba3SAnirudh Venkataramanan }; 2943a858ba3SAnirudh Venkataramanan 2953a858ba3SAnirudh Venkataramanan struct ice_aqc_vsi_props { 2963a858ba3SAnirudh Venkataramanan __le16 valid_sections; 2973a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 2983a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 2993a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 3003a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 3013a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 3023a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 3033a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 3043a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 3053a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 3063a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 3073a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 3083a858ba3SAnirudh Venkataramanan /* switch section */ 3093a858ba3SAnirudh Venkataramanan u8 sw_id; 3103a858ba3SAnirudh Venkataramanan u8 sw_flags; 3113a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 3123a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 3133a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 3143a858ba3SAnirudh Venkataramanan u8 sw_flags2; 3153a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 3163a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 3173a858ba3SAnirudh Venkataramanan (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 3183a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 3193a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 3203a858ba3SAnirudh Venkataramanan u8 veb_stat_id; 3213a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 3223a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 3233a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 3243a858ba3SAnirudh Venkataramanan /* security section */ 3253a858ba3SAnirudh Venkataramanan u8 sec_flags; 3263a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 3273a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 3283a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 3293a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 3303a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 3313a858ba3SAnirudh Venkataramanan u8 sec_reserved; 3323a858ba3SAnirudh Venkataramanan /* VLAN section */ 3333a858ba3SAnirudh Venkataramanan __le16 pvid; /* VLANS include priority bits */ 3343a858ba3SAnirudh Venkataramanan u8 pvlan_reserved[2]; 3355d8778d8SBrett Creeley u8 vlan_flags; 3365d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_S 0 3375d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 3385d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 3395d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 3405d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 3413a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 3425d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_S 3 3435d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 3445d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 3455d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 3465d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 3475d8778d8SBrett Creeley #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 3483a858ba3SAnirudh Venkataramanan u8 pvlan_reserved2[3]; 3493a858ba3SAnirudh Venkataramanan /* ingress egress up sections */ 3503a858ba3SAnirudh Venkataramanan __le32 ingress_table; /* bitmap, 3 bits per up */ 3513a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 3523a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 3533a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 3543a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 3553a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 3563a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 3573a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 3583a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 3593a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 3603a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 3613a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 3623a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 3633a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 3643a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 3653a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 3663a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 3673a858ba3SAnirudh Venkataramanan __le32 egress_table; /* same defines as for ingress table */ 3683a858ba3SAnirudh Venkataramanan /* outer tags section */ 3693a858ba3SAnirudh Venkataramanan __le16 outer_tag; 3703a858ba3SAnirudh Venkataramanan u8 outer_tag_flags; 3713a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 3723a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 3733a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 3743a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 3753a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 3763a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 3773a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 3783a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 3793a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 3803a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 3813a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 3823a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 3833a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 3843a858ba3SAnirudh Venkataramanan u8 outer_tag_reserved; 3853a858ba3SAnirudh Venkataramanan /* queue mapping section */ 3863a858ba3SAnirudh Venkataramanan __le16 mapping_flags; 3873a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 3883a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 3893a858ba3SAnirudh Venkataramanan __le16 q_mapping[16]; 3903a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_S 0 3913a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 3923a858ba3SAnirudh Venkataramanan __le16 tc_mapping[8]; 3933a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 3943a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 3953a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_NUM_S 11 3963a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 3973a858ba3SAnirudh Venkataramanan /* queueing option section */ 3983a858ba3SAnirudh Venkataramanan u8 q_opt_rss; 3993a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 4003a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 4013a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 4023a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 4033a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 4043a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 4053a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 4063a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 4073a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4083a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4093a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4103a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4113a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 4123a858ba3SAnirudh Venkataramanan u8 q_opt_tc; 4133a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 4143a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 4153a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 4163a858ba3SAnirudh Venkataramanan u8 q_opt_flags; 4173a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 4183a858ba3SAnirudh Venkataramanan u8 q_opt_reserved[3]; 4193a858ba3SAnirudh Venkataramanan /* outer up section */ 4203a858ba3SAnirudh Venkataramanan __le32 outer_up_table; /* same structure and defines as ingress tbl */ 4213a858ba3SAnirudh Venkataramanan /* section 10 */ 4223a858ba3SAnirudh Venkataramanan __le16 sect_10_reserved; 4233a858ba3SAnirudh Venkataramanan /* flow director section */ 4243a858ba3SAnirudh Venkataramanan __le16 fd_options; 4253a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_ENABLE BIT(0) 4263a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 4273a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 4283a858ba3SAnirudh Venkataramanan __le16 max_fd_fltr_dedicated; 4293a858ba3SAnirudh Venkataramanan __le16 max_fd_fltr_shared; 4303a858ba3SAnirudh Venkataramanan __le16 fd_def_q; 4313a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_Q_S 0 4323a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 4333a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_GRP_S 12 4343a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 4353a858ba3SAnirudh Venkataramanan __le16 fd_report_opt; 4363a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_REPORT_Q_S 0 4373a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 4383a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 4393a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 4403a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 4413a858ba3SAnirudh Venkataramanan /* PASID section */ 4423a858ba3SAnirudh Venkataramanan __le32 pasid_id; 4433a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PASID_ID_S 0 4443a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 4453a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 4463a858ba3SAnirudh Venkataramanan u8 reserved[24]; 4473a858ba3SAnirudh Venkataramanan }; 4483a858ba3SAnirudh Venkataramanan 44980d144c9SAnirudh Venkataramanan #define ICE_MAX_NUM_RECIPES 64 45080d144c9SAnirudh Venkataramanan 4519daf8208SAnirudh Venkataramanan /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 4529daf8208SAnirudh Venkataramanan */ 4539daf8208SAnirudh Venkataramanan struct ice_aqc_sw_rules { 4549daf8208SAnirudh Venkataramanan /* ops: add switch rules, referring the number of rules. 4559daf8208SAnirudh Venkataramanan * ops: update switch rules, referring the number of filters 4569daf8208SAnirudh Venkataramanan * ops: remove switch rules, referring the entry index. 4579daf8208SAnirudh Venkataramanan * ops: get switch rules, referring to the number of filters. 4589daf8208SAnirudh Venkataramanan */ 4599daf8208SAnirudh Venkataramanan __le16 num_rules_fltr_entry_index; 4609daf8208SAnirudh Venkataramanan u8 reserved[6]; 4619daf8208SAnirudh Venkataramanan __le32 addr_high; 4629daf8208SAnirudh Venkataramanan __le32 addr_low; 4639daf8208SAnirudh Venkataramanan }; 4649daf8208SAnirudh Venkataramanan 4659daf8208SAnirudh Venkataramanan /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 4669daf8208SAnirudh Venkataramanan * This structures describes the lookup rules and associated actions. "index" 4679daf8208SAnirudh Venkataramanan * is returned as part of a response to a successful Add command, and can be 4689daf8208SAnirudh Venkataramanan * used to identify the rule for Update/Get/Remove commands. 4699daf8208SAnirudh Venkataramanan */ 4709daf8208SAnirudh Venkataramanan struct ice_sw_rule_lkup_rx_tx { 4719daf8208SAnirudh Venkataramanan __le16 recipe_id; 4729daf8208SAnirudh Venkataramanan #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 4739daf8208SAnirudh Venkataramanan /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 4749daf8208SAnirudh Venkataramanan __le16 src; 4759daf8208SAnirudh Venkataramanan __le32 act; 4769daf8208SAnirudh Venkataramanan 4779daf8208SAnirudh Venkataramanan /* Bit 0:1 - Action type */ 4789daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_TYPE_S 0x00 4799daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 4809daf8208SAnirudh Venkataramanan 4819daf8208SAnirudh Venkataramanan /* Bit 2 - Loop back enable 4829daf8208SAnirudh Venkataramanan * Bit 3 - LAN enable 4839daf8208SAnirudh Venkataramanan */ 4849daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 4859daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 4869daf8208SAnirudh Venkataramanan 4879daf8208SAnirudh Venkataramanan /* Action type = 0 - Forward to VSI or VSI list */ 4889daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 4899daf8208SAnirudh Venkataramanan 4909daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_ID_S 4 4919daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 4929daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 4939daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 4949daf8208SAnirudh Venkataramanan /* This bit needs to be set if action is forward to VSI list */ 4959daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 4969daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 4979daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_DROP BIT(18) 4989daf8208SAnirudh Venkataramanan 4999daf8208SAnirudh Venkataramanan /* Action type = 1 - Forward to Queue of Queue group */ 5009daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_TO_Q 0x1 5019daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_INDEX_S 4 5029daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 5039daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_REGION_S 15 5049daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 5059daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 5069daf8208SAnirudh Venkataramanan 5079daf8208SAnirudh Venkataramanan /* Action type = 2 - Prune */ 5089daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PRUNE 0x2 5099daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_EGRESS BIT(15) 5109daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_INGRESS BIT(16) 5119daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PRUNET BIT(17) 5129daf8208SAnirudh Venkataramanan /* Bit 18 should be set to 0 for this action */ 5139daf8208SAnirudh Venkataramanan 5149daf8208SAnirudh Venkataramanan /* Action type = 2 - Pointer */ 5159daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR 0x2 5169daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR_VAL_S 4 5179daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 5189daf8208SAnirudh Venkataramanan /* Bit 18 should be set to 1 */ 5199daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 5209daf8208SAnirudh Venkataramanan 5219daf8208SAnirudh Venkataramanan /* Action type = 3 - Other actions. Last two bits 5229daf8208SAnirudh Venkataramanan * are other action identifier 5239daf8208SAnirudh Venkataramanan */ 5249daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 5259daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 5269daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 5279daf8208SAnirudh Venkataramanan (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 5289daf8208SAnirudh Venkataramanan 5299daf8208SAnirudh Venkataramanan /* Bit 17:18 - Defines other actions */ 5309daf8208SAnirudh Venkataramanan /* Other action = 0 - Mirror VSI */ 5319daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_MIRROR 0 5329daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 5339daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 5349daf8208SAnirudh Venkataramanan (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 5359daf8208SAnirudh Venkataramanan 5369daf8208SAnirudh Venkataramanan /* Other action = 3 - Set Stat count */ 5379daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 5389daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 5399daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 5409daf8208SAnirudh Venkataramanan (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 5419daf8208SAnirudh Venkataramanan 5429daf8208SAnirudh Venkataramanan __le16 index; /* The index of the rule in the lookup table */ 5439daf8208SAnirudh Venkataramanan /* Length and values of the header to be matched per recipe or 5449daf8208SAnirudh Venkataramanan * lookup-type 5459daf8208SAnirudh Venkataramanan */ 5469daf8208SAnirudh Venkataramanan __le16 hdr_len; 5479daf8208SAnirudh Venkataramanan u8 hdr[1]; 5489daf8208SAnirudh Venkataramanan } __packed; 5499daf8208SAnirudh Venkataramanan 5509daf8208SAnirudh Venkataramanan /* Add/Update/Remove large action command/response entry 5519daf8208SAnirudh Venkataramanan * "index" is returned as part of a response to a successful Add command, and 5529daf8208SAnirudh Venkataramanan * can be used to identify the action for Update/Get/Remove commands. 5539daf8208SAnirudh Venkataramanan */ 5549daf8208SAnirudh Venkataramanan struct ice_sw_rule_lg_act { 5559daf8208SAnirudh Venkataramanan __le16 index; /* Index in large action table */ 5569daf8208SAnirudh Venkataramanan __le16 size; 5579daf8208SAnirudh Venkataramanan __le32 act[1]; /* array of size for actions */ 5589daf8208SAnirudh Venkataramanan /* Max number of large actions */ 5599daf8208SAnirudh Venkataramanan #define ICE_MAX_LG_ACT 4 5609daf8208SAnirudh Venkataramanan /* Bit 0:1 - Action type */ 5619daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_TYPE_S 0 5629daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 5639daf8208SAnirudh Venkataramanan 5649daf8208SAnirudh Venkataramanan /* Action type = 0 - Forward to VSI or VSI list */ 5659daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_FORWARDING 0 5669daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_ID_S 3 5679daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 5689daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_LIST_ID_S 3 5699daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 5709daf8208SAnirudh Venkataramanan /* This bit needs to be set if action is forward to VSI list */ 5719daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_LIST BIT(13) 5729daf8208SAnirudh Venkataramanan 5739daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VALID_BIT BIT(16) 5749daf8208SAnirudh Venkataramanan 5759daf8208SAnirudh Venkataramanan /* Action type = 1 - Forward to Queue of Queue group */ 5769daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_TO_Q 0x1 5779daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_INDEX_S 3 5789daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 5799daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_REGION_S 14 5809daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 5819daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 5829daf8208SAnirudh Venkataramanan 5839daf8208SAnirudh Venkataramanan /* Action type = 2 - Prune */ 5849daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_PRUNE 0x2 5859daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_EGRESS BIT(14) 5869daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_INGRESS BIT(15) 5879daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_PRUNET BIT(16) 5889daf8208SAnirudh Venkataramanan 5899daf8208SAnirudh Venkataramanan /* Action type = 3 - Mirror VSI */ 5909daf8208SAnirudh Venkataramanan #define ICE_LG_OTHER_ACT_MIRROR 0x3 5919daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 5929daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 5939daf8208SAnirudh Venkataramanan 59434357a90SAnirudh Venkataramanan /* Action type = 5 - Generic Value */ 5959daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC 0x5 5969daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_VALUE_S 3 5979daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 5989daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_OFFSET_S 19 5999daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 6009daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 6019daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 6024381147dSAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 6039daf8208SAnirudh Venkataramanan 6049daf8208SAnirudh Venkataramanan /* Action = 7 - Set Stat count */ 6059daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_STAT_COUNT 0x7 6069daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_STAT_COUNT_S 3 6079daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 6089daf8208SAnirudh Venkataramanan }; 6099daf8208SAnirudh Venkataramanan 6109daf8208SAnirudh Venkataramanan /* Add/Update/Remove VSI list command/response entry 6119daf8208SAnirudh Venkataramanan * "index" is returned as part of a response to a successful Add command, and 6129daf8208SAnirudh Venkataramanan * can be used to identify the VSI list for Update/Get/Remove commands. 6139daf8208SAnirudh Venkataramanan */ 6149daf8208SAnirudh Venkataramanan struct ice_sw_rule_vsi_list { 6159daf8208SAnirudh Venkataramanan __le16 index; /* Index of VSI/Prune list */ 6169daf8208SAnirudh Venkataramanan __le16 number_vsi; 6179daf8208SAnirudh Venkataramanan __le16 vsi[1]; /* Array of number_vsi VSI numbers */ 6189daf8208SAnirudh Venkataramanan }; 6199daf8208SAnirudh Venkataramanan 6209daf8208SAnirudh Venkataramanan /* Query VSI list command/response entry */ 6219daf8208SAnirudh Venkataramanan struct ice_sw_rule_vsi_list_query { 6229daf8208SAnirudh Venkataramanan __le16 index; 6239daf8208SAnirudh Venkataramanan DECLARE_BITMAP(vsi_list, ICE_MAX_VSI); 6249daf8208SAnirudh Venkataramanan } __packed; 6259daf8208SAnirudh Venkataramanan 6269daf8208SAnirudh Venkataramanan /* Add switch rule response: 6279daf8208SAnirudh Venkataramanan * Content of return buffer is same as the input buffer. The status field and 6289daf8208SAnirudh Venkataramanan * LUT index are updated as part of the response 6299daf8208SAnirudh Venkataramanan */ 6309daf8208SAnirudh Venkataramanan struct ice_aqc_sw_rules_elem { 6319daf8208SAnirudh Venkataramanan __le16 type; /* Switch rule type, one of T_... */ 6329daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 6339daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 6349daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 6359daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 6369daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 6379daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 6389daf8208SAnirudh Venkataramanan #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 6399daf8208SAnirudh Venkataramanan __le16 status; 6409daf8208SAnirudh Venkataramanan union { 6419daf8208SAnirudh Venkataramanan struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 6429daf8208SAnirudh Venkataramanan struct ice_sw_rule_lg_act lg_act; 6439daf8208SAnirudh Venkataramanan struct ice_sw_rule_vsi_list vsi_list; 6449daf8208SAnirudh Venkataramanan struct ice_sw_rule_vsi_list_query vsi_list_query; 6459daf8208SAnirudh Venkataramanan } __packed pdata; 6469daf8208SAnirudh Venkataramanan }; 6479daf8208SAnirudh Venkataramanan 648dc49c772SAnirudh Venkataramanan /* Get Default Topology (indirect 0x0400) */ 649dc49c772SAnirudh Venkataramanan struct ice_aqc_get_topo { 650dc49c772SAnirudh Venkataramanan u8 port_num; 651dc49c772SAnirudh Venkataramanan u8 num_branches; 652dc49c772SAnirudh Venkataramanan __le16 reserved1; 653dc49c772SAnirudh Venkataramanan __le32 reserved2; 654dc49c772SAnirudh Venkataramanan __le32 addr_high; 655dc49c772SAnirudh Venkataramanan __le32 addr_low; 656dc49c772SAnirudh Venkataramanan }; 657dc49c772SAnirudh Venkataramanan 6585513b920SAnirudh Venkataramanan /* Update TSE (indirect 0x0403) 6595513b920SAnirudh Venkataramanan * Get TSE (indirect 0x0404) 6601f9c7840SAnirudh Venkataramanan * Add TSE (indirect 0x0401) 6611f9c7840SAnirudh Venkataramanan * Delete TSE (indirect 0x040F) 6621f9c7840SAnirudh Venkataramanan * Move TSE (indirect 0x0408) 6631f9c7840SAnirudh Venkataramanan * Suspend Nodes (indirect 0x0409) 6641f9c7840SAnirudh Venkataramanan * Resume Nodes (indirect 0x040A) 6655513b920SAnirudh Venkataramanan */ 6661f9c7840SAnirudh Venkataramanan struct ice_aqc_sched_elem_cmd { 6675513b920SAnirudh Venkataramanan __le16 num_elem_req; /* Used by commands */ 6685513b920SAnirudh Venkataramanan __le16 num_elem_resp; /* Used by responses */ 6695513b920SAnirudh Venkataramanan __le32 reserved; 6705513b920SAnirudh Venkataramanan __le32 addr_high; 6715513b920SAnirudh Venkataramanan __le32 addr_low; 6725513b920SAnirudh Venkataramanan }; 6735513b920SAnirudh Venkataramanan 6745513b920SAnirudh Venkataramanan /* This is the buffer for: 6755513b920SAnirudh Venkataramanan * Suspend Nodes (indirect 0x0409) 6765513b920SAnirudh Venkataramanan * Resume Nodes (indirect 0x040A) 6775513b920SAnirudh Venkataramanan */ 6785513b920SAnirudh Venkataramanan struct ice_aqc_suspend_resume_elem { 6795513b920SAnirudh Venkataramanan __le32 teid[1]; 6805513b920SAnirudh Venkataramanan }; 6815513b920SAnirudh Venkataramanan 6829c20346bSAnirudh Venkataramanan struct ice_aqc_elem_info_bw { 6839c20346bSAnirudh Venkataramanan __le16 bw_profile_idx; 6849c20346bSAnirudh Venkataramanan __le16 bw_alloc; 6859c20346bSAnirudh Venkataramanan }; 6869c20346bSAnirudh Venkataramanan 6879c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem { 6889c20346bSAnirudh Venkataramanan u8 elem_type; /* Special field, reserved for some aq calls */ 6899c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 6909c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 6919c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_TC 0x2 6929c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 6939c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 6949c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_LEAF 0x5 6959c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 6969c20346bSAnirudh Venkataramanan u8 valid_sections; 6979c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 6989c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_CIR BIT(1) 6999c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_EIR BIT(2) 7009c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 7019c20346bSAnirudh Venkataramanan u8 generic; 7029c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 7039c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 7049c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 7059c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 7069c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 7079c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 7089c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 7099c20346bSAnirudh Venkataramanan (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 7109c20346bSAnirudh Venkataramanan u8 flags; /* Special field, reserved for some aq calls */ 7119c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 7129c20346bSAnirudh Venkataramanan struct ice_aqc_elem_info_bw cir_bw; 7139c20346bSAnirudh Venkataramanan struct ice_aqc_elem_info_bw eir_bw; 7149c20346bSAnirudh Venkataramanan __le16 srl_id; 7159c20346bSAnirudh Venkataramanan __le16 reserved2; 7169c20346bSAnirudh Venkataramanan }; 7179c20346bSAnirudh Venkataramanan 7189c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem_data { 7199c20346bSAnirudh Venkataramanan __le32 parent_teid; 7209c20346bSAnirudh Venkataramanan __le32 node_teid; 7219c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem data; 7229c20346bSAnirudh Venkataramanan }; 7239c20346bSAnirudh Venkataramanan 7249c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr { 7259c20346bSAnirudh Venkataramanan __le32 parent_teid; 7269c20346bSAnirudh Venkataramanan __le16 num_elems; 7279c20346bSAnirudh Venkataramanan __le16 reserved2; 7289c20346bSAnirudh Venkataramanan }; 7299c20346bSAnirudh Venkataramanan 7305513b920SAnirudh Venkataramanan struct ice_aqc_add_elem { 7315513b920SAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr hdr; 7325513b920SAnirudh Venkataramanan struct ice_aqc_txsched_elem_data generic[1]; 7335513b920SAnirudh Venkataramanan }; 7345513b920SAnirudh Venkataramanan 73556daee6cSAnirudh Venkataramanan struct ice_aqc_get_elem { 73656daee6cSAnirudh Venkataramanan struct ice_aqc_txsched_elem_data generic[1]; 73756daee6cSAnirudh Venkataramanan }; 73856daee6cSAnirudh Venkataramanan 739dc49c772SAnirudh Venkataramanan struct ice_aqc_get_topo_elem { 740dc49c772SAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr hdr; 741dc49c772SAnirudh Venkataramanan struct ice_aqc_txsched_elem_data 742dc49c772SAnirudh Venkataramanan generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 743dc49c772SAnirudh Venkataramanan }; 744dc49c772SAnirudh Venkataramanan 7459c20346bSAnirudh Venkataramanan struct ice_aqc_delete_elem { 7469c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr hdr; 7479c20346bSAnirudh Venkataramanan __le32 teid[1]; 7489c20346bSAnirudh Venkataramanan }; 7499c20346bSAnirudh Venkataramanan 7509c20346bSAnirudh Venkataramanan /* Query Scheduler Resource Allocation (indirect 0x0412) 7519c20346bSAnirudh Venkataramanan * This indirect command retrieves the scheduler resources allocated by 7529c20346bSAnirudh Venkataramanan * EMP Firmware to the given PF. 7539c20346bSAnirudh Venkataramanan */ 7549c20346bSAnirudh Venkataramanan struct ice_aqc_query_txsched_res { 7559c20346bSAnirudh Venkataramanan u8 reserved[8]; 7569c20346bSAnirudh Venkataramanan __le32 addr_high; 7579c20346bSAnirudh Venkataramanan __le32 addr_low; 7589c20346bSAnirudh Venkataramanan }; 7599c20346bSAnirudh Venkataramanan 7609c20346bSAnirudh Venkataramanan struct ice_aqc_generic_sched_props { 7619c20346bSAnirudh Venkataramanan __le16 phys_levels; 7629c20346bSAnirudh Venkataramanan __le16 logical_levels; 7639c20346bSAnirudh Venkataramanan u8 flattening_bitmap; 7649c20346bSAnirudh Venkataramanan u8 max_device_cgds; 7659c20346bSAnirudh Venkataramanan u8 max_pf_cgds; 7669c20346bSAnirudh Venkataramanan u8 rsvd0; 7679c20346bSAnirudh Venkataramanan __le16 rdma_qsets; 7689c20346bSAnirudh Venkataramanan u8 rsvd1[22]; 7699c20346bSAnirudh Venkataramanan }; 7709c20346bSAnirudh Venkataramanan 7719c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props { 7729c20346bSAnirudh Venkataramanan u8 logical_layer; 7739c20346bSAnirudh Venkataramanan u8 chunk_size; 7749c20346bSAnirudh Venkataramanan __le16 max_device_nodes; 7759c20346bSAnirudh Venkataramanan __le16 max_pf_nodes; 776b36c598cSAnirudh Venkataramanan u8 rsvd0[4]; 777b36c598cSAnirudh Venkataramanan __le16 max_sibl_grp_sz; 7789c20346bSAnirudh Venkataramanan __le16 max_cir_rl_profiles; 7799c20346bSAnirudh Venkataramanan __le16 max_eir_rl_profiles; 7809c20346bSAnirudh Venkataramanan __le16 max_srl_profiles; 7819c20346bSAnirudh Venkataramanan u8 rsvd1[14]; 7829c20346bSAnirudh Venkataramanan }; 7839c20346bSAnirudh Venkataramanan 7849c20346bSAnirudh Venkataramanan struct ice_aqc_query_txsched_res_resp { 7859c20346bSAnirudh Venkataramanan struct ice_aqc_generic_sched_props sched_props; 7869c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 7879c20346bSAnirudh Venkataramanan }; 7889c20346bSAnirudh Venkataramanan 789dc49c772SAnirudh Venkataramanan /* Get PHY capabilities (indirect 0x0600) */ 790dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps { 791dc49c772SAnirudh Venkataramanan u8 lport_num; 792dc49c772SAnirudh Venkataramanan u8 reserved; 793dc49c772SAnirudh Venkataramanan __le16 param0; 794dc49c772SAnirudh Venkataramanan /* 18.0 - Report qualified modules */ 795dc49c772SAnirudh Venkataramanan #define ICE_AQC_GET_PHY_RQM BIT(0) 796dc49c772SAnirudh Venkataramanan /* 18.1 - 18.2 : Report mode 797dc49c772SAnirudh Venkataramanan * 00b - Report NVM capabilities 798dc49c772SAnirudh Venkataramanan * 01b - Report topology capabilities 799dc49c772SAnirudh Venkataramanan * 10b - Report SW configured 800dc49c772SAnirudh Venkataramanan */ 801dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_MODE_S 1 802dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 803dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_NVM_CAP 0 804dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 805dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_SW_CFG BIT(2) 806dc49c772SAnirudh Venkataramanan __le32 reserved1; 807dc49c772SAnirudh Venkataramanan __le32 addr_high; 808dc49c772SAnirudh Venkataramanan __le32 addr_low; 809dc49c772SAnirudh Venkataramanan }; 810dc49c772SAnirudh Venkataramanan 811dc49c772SAnirudh Venkataramanan /* This is #define of PHY type (Extended): 812dc49c772SAnirudh Venkataramanan * The first set of defines is for phy_type_low. 813dc49c772SAnirudh Venkataramanan */ 814dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 815dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 816dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 817dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 818dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 819dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 820dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 821dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 822dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 823dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 824dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 825dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 826dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 827dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 828dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 829dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 830dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 831dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 832dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 833dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 834dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 835dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 836dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 837dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 838dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 839dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 840dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 841dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 842dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 843dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 844dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 845dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 846dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 847dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 848dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 849dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 850dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 851dc49c772SAnirudh Venkataramanan 852dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps_data { 853dc49c772SAnirudh Venkataramanan __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 854dc49c772SAnirudh Venkataramanan __le64 reserved; 855dc49c772SAnirudh Venkataramanan u8 caps; 856dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 857dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 858dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 859dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_LINK BIT(3) 860dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_AN_MODE BIT(4) 861dc49c772SAnirudh Venkataramanan #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 862dc49c772SAnirudh Venkataramanan u8 low_power_ctrl; 863dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 864dc49c772SAnirudh Venkataramanan __le16 eee_cap; 865dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 866dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 867dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 868dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 869dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 870dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 871dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 872dc49c772SAnirudh Venkataramanan __le16 eeer_value; 873dc49c772SAnirudh Venkataramanan u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 874dc49c772SAnirudh Venkataramanan u8 link_fec_options; 875dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 876dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 877dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 878dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 879dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 880dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 881dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 882dc49c772SAnirudh Venkataramanan u8 extended_compliance_code; 883dc49c772SAnirudh Venkataramanan #define ICE_MODULE_TYPE_TOTAL_BYTE 3 884dc49c772SAnirudh Venkataramanan u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 885dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 886dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 887dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 888dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 889dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 890dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 891dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 892dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 893dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 894dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 895dc49c772SAnirudh Venkataramanan u8 qualified_module_count; 896dc49c772SAnirudh Venkataramanan #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 897dc49c772SAnirudh Venkataramanan struct { 898dc49c772SAnirudh Venkataramanan u8 v_oui[3]; 899dc49c772SAnirudh Venkataramanan u8 rsvd1; 900dc49c772SAnirudh Venkataramanan u8 v_part[16]; 901dc49c772SAnirudh Venkataramanan __le32 v_rev; 902dc49c772SAnirudh Venkataramanan __le64 rsvd8; 903dc49c772SAnirudh Venkataramanan } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 904dc49c772SAnirudh Venkataramanan }; 905dc49c772SAnirudh Venkataramanan 906fcea6f3dSAnirudh Venkataramanan /* Set PHY capabilities (direct 0x0601) 907fcea6f3dSAnirudh Venkataramanan * NOTE: This command must be followed by setup link and restart auto-neg 908fcea6f3dSAnirudh Venkataramanan */ 909fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg { 910fcea6f3dSAnirudh Venkataramanan u8 lport_num; 911fcea6f3dSAnirudh Venkataramanan u8 reserved[7]; 912fcea6f3dSAnirudh Venkataramanan __le32 addr_high; 913fcea6f3dSAnirudh Venkataramanan __le32 addr_low; 914fcea6f3dSAnirudh Venkataramanan }; 915fcea6f3dSAnirudh Venkataramanan 916fcea6f3dSAnirudh Venkataramanan /* Set PHY config command data structure */ 917fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg_data { 918fcea6f3dSAnirudh Venkataramanan __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 919fcea6f3dSAnirudh Venkataramanan __le64 rsvd0; 920fcea6f3dSAnirudh Venkataramanan u8 caps; 921fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 922fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 923fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 924fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_LINK BIT(3) 92548cb27f2SChinh Cao #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 92648cb27f2SChinh Cao #define ICE_AQ_PHY_ENA_LESM BIT(6) 92748cb27f2SChinh Cao #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 928fcea6f3dSAnirudh Venkataramanan u8 low_power_ctrl; 929fcea6f3dSAnirudh Venkataramanan __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 930fcea6f3dSAnirudh Venkataramanan __le16 eeer_value; 931fcea6f3dSAnirudh Venkataramanan u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 932fcea6f3dSAnirudh Venkataramanan u8 rsvd1; 933fcea6f3dSAnirudh Venkataramanan }; 934fcea6f3dSAnirudh Venkataramanan 935fcea6f3dSAnirudh Venkataramanan /* Restart AN command data structure (direct 0x0605) 936fcea6f3dSAnirudh Venkataramanan * Also used for response, with only the lport_num field present. 937fcea6f3dSAnirudh Venkataramanan */ 938fcea6f3dSAnirudh Venkataramanan struct ice_aqc_restart_an { 939fcea6f3dSAnirudh Venkataramanan u8 lport_num; 940fcea6f3dSAnirudh Venkataramanan u8 reserved; 941fcea6f3dSAnirudh Venkataramanan u8 cmd_flags; 942fcea6f3dSAnirudh Venkataramanan #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 943fcea6f3dSAnirudh Venkataramanan #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 944fcea6f3dSAnirudh Venkataramanan u8 reserved2[13]; 945fcea6f3dSAnirudh Venkataramanan }; 946fcea6f3dSAnirudh Venkataramanan 947dc49c772SAnirudh Venkataramanan /* Get link status (indirect 0x0607), also used for Link Status Event */ 948dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status { 949dc49c772SAnirudh Venkataramanan u8 lport_num; 950dc49c772SAnirudh Venkataramanan u8 reserved; 951dc49c772SAnirudh Venkataramanan __le16 cmd_flags; 952dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_M 0x3 953dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_NOP 0x0 954dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_DIS 0x2 955dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_ENA 0x3 956dc49c772SAnirudh Venkataramanan /* only response uses this flag */ 957dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_IS_ENABLED 0x1 958dc49c772SAnirudh Venkataramanan __le32 reserved2; 959dc49c772SAnirudh Venkataramanan __le32 addr_high; 960dc49c772SAnirudh Venkataramanan __le32 addr_low; 961dc49c772SAnirudh Venkataramanan }; 962dc49c772SAnirudh Venkataramanan 963dc49c772SAnirudh Venkataramanan /* Get link status response data structure, also used for Link Status Event */ 964dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status_data { 965dc49c772SAnirudh Venkataramanan u8 topo_media_conflict; 966dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 967dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 968dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 969dc49c772SAnirudh Venkataramanan u8 reserved1; 970dc49c772SAnirudh Venkataramanan u8 link_info; 971dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 972dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT BIT(1) 973dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT_TX BIT(2) 974dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT_RX BIT(3) 975dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 976dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 977dc49c772SAnirudh Venkataramanan #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 978dc49c772SAnirudh Venkataramanan #define ICE_AQ_SIGNAL_DETECT BIT(7) 979dc49c772SAnirudh Venkataramanan u8 an_info; 980dc49c772SAnirudh Venkataramanan #define ICE_AQ_AN_COMPLETED BIT(0) 981dc49c772SAnirudh Venkataramanan #define ICE_AQ_LP_AN_ABILITY BIT(1) 982dc49c772SAnirudh Venkataramanan #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 983dc49c772SAnirudh Venkataramanan #define ICE_AQ_FEC_EN BIT(3) 984dc49c772SAnirudh Venkataramanan #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 985dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PAUSE_TX BIT(5) 986dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PAUSE_RX BIT(6) 987dc49c772SAnirudh Venkataramanan #define ICE_AQ_QUALIFIED_MODULE BIT(7) 988dc49c772SAnirudh Venkataramanan u8 ext_info; 989dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 990dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 991dc49c772SAnirudh Venkataramanan /* Port TX Suspended */ 992dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_S 2 993dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 994dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_ACTIVE 0 995dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_DRAINED 1 996dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_FLUSHED 3 997dc49c772SAnirudh Venkataramanan u8 reserved2; 998dc49c772SAnirudh Venkataramanan __le16 max_frame_size; 999dc49c772SAnirudh Venkataramanan u8 cfg; 1000dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1001dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1002dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1003dc49c772SAnirudh Venkataramanan /* Pacing Config */ 1004dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_S 3 1005dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1006dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1007dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1008dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1009dc49c772SAnirudh Venkataramanan /* External Device Power Ability */ 1010dc49c772SAnirudh Venkataramanan u8 power_desc; 1011dc49c772SAnirudh Venkataramanan #define ICE_AQ_PWR_CLASS_M 0x3 1012dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1013dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1014dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1015dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1016dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1017dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1018dc49c772SAnirudh Venkataramanan __le16 link_speed; 1019dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1020dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1021dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1022dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1023dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1024dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1025dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1026dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1027dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1028dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1029dc49c772SAnirudh Venkataramanan __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1030dc49c772SAnirudh Venkataramanan __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1031dc49c772SAnirudh Venkataramanan __le64 reserved4; 1032dc49c772SAnirudh Venkataramanan }; 1033dc49c772SAnirudh Venkataramanan 10340b28b702SAnirudh Venkataramanan /* Set event mask command (direct 0x0613) */ 10350b28b702SAnirudh Venkataramanan struct ice_aqc_set_event_mask { 10360b28b702SAnirudh Venkataramanan u8 lport_num; 10370b28b702SAnirudh Venkataramanan u8 reserved[7]; 10380b28b702SAnirudh Venkataramanan __le16 event_mask; 10390b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 10400b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 10410b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 10420b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 10430b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 10440b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 10450b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 10460b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 10470b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 10480b28b702SAnirudh Venkataramanan u8 reserved1[6]; 10490b28b702SAnirudh Venkataramanan }; 10500b28b702SAnirudh Venkataramanan 1051f31e4b6fSAnirudh Venkataramanan /* NVM Read command (indirect 0x0701) 1052f31e4b6fSAnirudh Venkataramanan * NVM Erase commands (direct 0x0702) 1053f31e4b6fSAnirudh Venkataramanan * NVM Update commands (indirect 0x0703) 1054f31e4b6fSAnirudh Venkataramanan */ 1055f31e4b6fSAnirudh Venkataramanan struct ice_aqc_nvm { 105643c89b16SAnirudh Venkataramanan __le16 offset_low; 105743c89b16SAnirudh Venkataramanan u8 offset_high; 1058f31e4b6fSAnirudh Venkataramanan u8 cmd_flags; 1059f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_LAST_CMD BIT(0) 1060f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1061f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_PRESERVATION_S 1 10626263e811SLev Faerman #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 10636263e811SLev Faerman #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1064f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 10656263e811SLev Faerman #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1066f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 106743c89b16SAnirudh Venkataramanan __le16 module_typeid; 1068f31e4b6fSAnirudh Venkataramanan __le16 length; 1069f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1070f31e4b6fSAnirudh Venkataramanan __le32 addr_high; 1071f31e4b6fSAnirudh Venkataramanan __le32 addr_low; 1072f31e4b6fSAnirudh Venkataramanan }; 1073f31e4b6fSAnirudh Venkataramanan 1074007676b4SAnirudh Venkataramanan /** 1075007676b4SAnirudh Venkataramanan * Send to PF command (indirect 0x0801) id is only used by PF 1076007676b4SAnirudh Venkataramanan * 1077007676b4SAnirudh Venkataramanan * Send to VF command (indirect 0x0802) id is only used by PF 1078007676b4SAnirudh Venkataramanan * 1079007676b4SAnirudh Venkataramanan */ 1080007676b4SAnirudh Venkataramanan struct ice_aqc_pf_vf_msg { 1081007676b4SAnirudh Venkataramanan __le32 id; 1082007676b4SAnirudh Venkataramanan u32 reserved; 1083007676b4SAnirudh Venkataramanan __le32 addr_high; 1084007676b4SAnirudh Venkataramanan __le32 addr_low; 1085007676b4SAnirudh Venkataramanan }; 1086007676b4SAnirudh Venkataramanan 1087d76a60baSAnirudh Venkataramanan /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1088d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_key { 1089d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 1090d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 1091d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 1092d76a60baSAnirudh Venkataramanan __le16 vsi_id; 1093d76a60baSAnirudh Venkataramanan u8 reserved[6]; 1094d76a60baSAnirudh Venkataramanan __le32 addr_high; 1095d76a60baSAnirudh Venkataramanan __le32 addr_low; 1096d76a60baSAnirudh Venkataramanan }; 1097d76a60baSAnirudh Venkataramanan 1098d76a60baSAnirudh Venkataramanan #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1099d76a60baSAnirudh Venkataramanan #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1100d76a60baSAnirudh Venkataramanan 1101d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_keys { 1102d76a60baSAnirudh Venkataramanan u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1103d76a60baSAnirudh Venkataramanan u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1104d76a60baSAnirudh Venkataramanan }; 1105d76a60baSAnirudh Venkataramanan 1106d76a60baSAnirudh Venkataramanan /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1107d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_lut { 1108d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 1109d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 1110d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 1111d76a60baSAnirudh Venkataramanan __le16 vsi_id; 1112d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 1113d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 1114d76a60baSAnirudh Venkataramanan (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 1115d76a60baSAnirudh Venkataramanan 1116d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 1117d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 1118d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 1119d76a60baSAnirudh Venkataramanan 1120d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 1121d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 1122d76a60baSAnirudh Venkataramanan (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 1123d76a60baSAnirudh Venkataramanan 1124d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 1125d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 1126d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 1127d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 1128d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 1129d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 1130d76a60baSAnirudh Venkataramanan 1131d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 1132d76a60baSAnirudh Venkataramanan #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 1133d76a60baSAnirudh Venkataramanan (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 1134d76a60baSAnirudh Venkataramanan 1135d76a60baSAnirudh Venkataramanan __le16 flags; 1136d76a60baSAnirudh Venkataramanan __le32 reserved; 1137d76a60baSAnirudh Venkataramanan __le32 addr_high; 1138d76a60baSAnirudh Venkataramanan __le32 addr_low; 1139d76a60baSAnirudh Venkataramanan }; 1140d76a60baSAnirudh Venkataramanan 1141cdedef59SAnirudh Venkataramanan /* Add TX LAN Queues (indirect 0x0C30) */ 1142cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs { 1143cdedef59SAnirudh Venkataramanan u8 num_qgrps; 1144cdedef59SAnirudh Venkataramanan u8 reserved[3]; 1145cdedef59SAnirudh Venkataramanan __le32 reserved1; 1146cdedef59SAnirudh Venkataramanan __le32 addr_high; 1147cdedef59SAnirudh Venkataramanan __le32 addr_low; 1148cdedef59SAnirudh Venkataramanan }; 1149cdedef59SAnirudh Venkataramanan 1150cdedef59SAnirudh Venkataramanan /* This is the descriptor of each queue entry for the Add TX LAN Queues 1151cdedef59SAnirudh Venkataramanan * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1152cdedef59SAnirudh Venkataramanan */ 1153cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs_perq { 1154cdedef59SAnirudh Venkataramanan __le16 txq_id; 1155cdedef59SAnirudh Venkataramanan u8 rsvd[2]; 1156cdedef59SAnirudh Venkataramanan __le32 q_teid; 1157cdedef59SAnirudh Venkataramanan u8 txq_ctx[22]; 1158cdedef59SAnirudh Venkataramanan u8 rsvd2[2]; 1159cdedef59SAnirudh Venkataramanan struct ice_aqc_txsched_elem info; 1160cdedef59SAnirudh Venkataramanan }; 1161cdedef59SAnirudh Venkataramanan 1162cdedef59SAnirudh Venkataramanan /* The format of the command buffer for Add TX LAN Queues (0x0C30) 1163cdedef59SAnirudh Venkataramanan * is an array of the following structs. Please note that the length of 1164cdedef59SAnirudh Venkataramanan * each struct ice_aqc_add_tx_qgrp is variable due 1165cdedef59SAnirudh Venkataramanan * to the variable number of queues in each group! 1166cdedef59SAnirudh Venkataramanan */ 1167cdedef59SAnirudh Venkataramanan struct ice_aqc_add_tx_qgrp { 1168cdedef59SAnirudh Venkataramanan __le32 parent_teid; 1169cdedef59SAnirudh Venkataramanan u8 num_txqs; 1170cdedef59SAnirudh Venkataramanan u8 rsvd[3]; 1171cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs_perq txqs[1]; 1172cdedef59SAnirudh Venkataramanan }; 1173cdedef59SAnirudh Venkataramanan 1174cdedef59SAnirudh Venkataramanan /* Disable TX LAN Queues (indirect 0x0C31) */ 1175cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txqs { 1176cdedef59SAnirudh Venkataramanan u8 cmd_type; 1177cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_S 0 1178cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1179cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1180cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1181cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1182cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1183cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1184cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1185cdedef59SAnirudh Venkataramanan u8 num_entries; 1186cdedef59SAnirudh Venkataramanan __le16 vmvf_and_timeout; 1187cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1188cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1189cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1190cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1191cdedef59SAnirudh Venkataramanan __le32 blocked_cgds; 1192cdedef59SAnirudh Venkataramanan __le32 addr_high; 1193cdedef59SAnirudh Venkataramanan __le32 addr_low; 1194cdedef59SAnirudh Venkataramanan }; 1195cdedef59SAnirudh Venkataramanan 1196cdedef59SAnirudh Venkataramanan /* The buffer for Disable TX LAN Queues (indirect 0x0C31) 1197cdedef59SAnirudh Venkataramanan * contains the following structures, arrayed one after the 1198cdedef59SAnirudh Venkataramanan * other. 1199cdedef59SAnirudh Venkataramanan * Note: Since the q_id is 16 bits wide, if the 1200cdedef59SAnirudh Venkataramanan * number of queues is even, then 2 bytes of alignment MUST be 1201cdedef59SAnirudh Venkataramanan * added before the start of the next group, to allow correct 1202cdedef59SAnirudh Venkataramanan * alignment of the parent_teid field. 1203cdedef59SAnirudh Venkataramanan */ 1204cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txq_item { 1205cdedef59SAnirudh Venkataramanan __le32 parent_teid; 1206cdedef59SAnirudh Venkataramanan u8 num_qs; 1207cdedef59SAnirudh Venkataramanan u8 rsvd; 1208cdedef59SAnirudh Venkataramanan /* The length of the q_id array varies according to num_qs */ 1209cdedef59SAnirudh Venkataramanan __le16 q_id[1]; 1210cdedef59SAnirudh Venkataramanan /* This only applies from F8 onward */ 1211cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1212cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1213cdedef59SAnirudh Venkataramanan (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1214cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1215cdedef59SAnirudh Venkataramanan (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1216cdedef59SAnirudh Venkataramanan }; 1217cdedef59SAnirudh Venkataramanan 1218cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txq { 1219cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txq_item qgrps[1]; 1220cdedef59SAnirudh Venkataramanan }; 1221cdedef59SAnirudh Venkataramanan 12228b97ceb1SHieu Tran /* Configure Firmware Logging Command (indirect 0xFF09) 12238b97ceb1SHieu Tran * Logging Information Read Response (indirect 0xFF10) 12248b97ceb1SHieu Tran * Note: The 0xFF10 command has no input parameters. 12258b97ceb1SHieu Tran */ 12268b97ceb1SHieu Tran struct ice_aqc_fw_logging { 12278b97ceb1SHieu Tran u8 log_ctrl; 12288b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 12298b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_UART_EN BIT(1) 12308b97ceb1SHieu Tran u8 rsvd0; 12318b97ceb1SHieu Tran u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 12328b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 12338b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 12348b97ceb1SHieu Tran u8 rsvd1[5]; 12358b97ceb1SHieu Tran __le32 addr_high; 12368b97ceb1SHieu Tran __le32 addr_low; 12378b97ceb1SHieu Tran }; 12388b97ceb1SHieu Tran 12398b97ceb1SHieu Tran enum ice_aqc_fw_logging_mod { 12408b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_GENERAL = 0, 12418b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_CTRL, 12428b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_LINK, 12438b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_LINK_TOPO, 12448b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_DNL, 12458b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_I2C, 12468b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_SDP, 12478b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_MDIO, 12488b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_ADMINQ, 12498b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_HDMA, 12508b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_LLDP, 12518b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_DCBX, 12528b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_DCB, 12538b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_NETPROXY, 12548b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_NVM, 12558b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_AUTH, 12568b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_VPD, 12578b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_IOSF, 12588b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_PARSER, 12598b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_SW, 12608b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_SCHEDULER, 12618b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_TXQ, 12628b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_RSVD, 12638b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_POST, 12648b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_WATCHDOG, 12658b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 12668b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_MNG, 12678b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_MAX, 12688b97ceb1SHieu Tran }; 12698b97ceb1SHieu Tran 12708b97ceb1SHieu Tran /* This is the buffer for both of the logging commands. 12718b97ceb1SHieu Tran * The entry array size depends on the datalen parameter in the descriptor. 12728b97ceb1SHieu Tran * There will be a total of datalen / 2 entries. 12738b97ceb1SHieu Tran */ 12748b97ceb1SHieu Tran struct ice_aqc_fw_logging_data { 12758b97ceb1SHieu Tran __le16 entry[1]; 12768b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_ID_S 0 12778b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 12788b97ceb1SHieu Tran 12798b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 12808b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 12818b97ceb1SHieu Tran 12828b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_EN_S 12 12838b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 12848b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 12858b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 12868b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 12878b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 12888b97ceb1SHieu Tran }; 12898b97ceb1SHieu Tran 12908b97ceb1SHieu Tran /* Get/Clear FW Log (indirect 0xFF11) */ 12918b97ceb1SHieu Tran struct ice_aqc_get_clear_fw_log { 12928b97ceb1SHieu Tran u8 flags; 12938b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_CLEAR BIT(0) 12948b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 12958b97ceb1SHieu Tran u8 rsvd1[7]; 12968b97ceb1SHieu Tran __le32 addr_high; 12978b97ceb1SHieu Tran __le32 addr_low; 12988b97ceb1SHieu Tran }; 12998b97ceb1SHieu Tran 13007ec59eeaSAnirudh Venkataramanan /** 13017ec59eeaSAnirudh Venkataramanan * struct ice_aq_desc - Admin Queue (AQ) descriptor 13027ec59eeaSAnirudh Venkataramanan * @flags: ICE_AQ_FLAG_* flags 13037ec59eeaSAnirudh Venkataramanan * @opcode: AQ command opcode 13047ec59eeaSAnirudh Venkataramanan * @datalen: length in bytes of indirect/external data buffer 13057ec59eeaSAnirudh Venkataramanan * @retval: return value from firmware 13067ec59eeaSAnirudh Venkataramanan * @cookie_h: opaque data high-half 13077ec59eeaSAnirudh Venkataramanan * @cookie_l: opaque data low-half 13087ec59eeaSAnirudh Venkataramanan * @params: command-specific parameters 13097ec59eeaSAnirudh Venkataramanan * 13107ec59eeaSAnirudh Venkataramanan * Descriptor format for commands the driver posts on the Admin Transmit Queue 13117ec59eeaSAnirudh Venkataramanan * (ATQ). The firmware writes back onto the command descriptor and returns 13127ec59eeaSAnirudh Venkataramanan * the result of the command. Asynchronous events that are not an immediate 13137ec59eeaSAnirudh Venkataramanan * result of the command are written to the Admin Receive Queue (ARQ) using 13147ec59eeaSAnirudh Venkataramanan * the same descriptor format. Descriptors are in little-endian notation with 13157ec59eeaSAnirudh Venkataramanan * 32-bit words. 13167ec59eeaSAnirudh Venkataramanan */ 13177ec59eeaSAnirudh Venkataramanan struct ice_aq_desc { 13187ec59eeaSAnirudh Venkataramanan __le16 flags; 13197ec59eeaSAnirudh Venkataramanan __le16 opcode; 13207ec59eeaSAnirudh Venkataramanan __le16 datalen; 13217ec59eeaSAnirudh Venkataramanan __le16 retval; 13227ec59eeaSAnirudh Venkataramanan __le32 cookie_high; 13237ec59eeaSAnirudh Venkataramanan __le32 cookie_low; 13247ec59eeaSAnirudh Venkataramanan union { 13257ec59eeaSAnirudh Venkataramanan u8 raw[16]; 13267ec59eeaSAnirudh Venkataramanan struct ice_aqc_generic generic; 13277ec59eeaSAnirudh Venkataramanan struct ice_aqc_get_ver get_ver; 13287ec59eeaSAnirudh Venkataramanan struct ice_aqc_q_shutdown q_shutdown; 1329f31e4b6fSAnirudh Venkataramanan struct ice_aqc_req_res res_owner; 1330dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read mac_read; 1331e94d4478SAnirudh Venkataramanan struct ice_aqc_manage_mac_write mac_write; 1332f31e4b6fSAnirudh Venkataramanan struct ice_aqc_clear_pxe clear_pxe; 13339c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps get_cap; 1334dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps get_phy; 1335fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg set_phy; 1336fcea6f3dSAnirudh Venkataramanan struct ice_aqc_restart_an restart_an; 13379c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg get_sw_conf; 13389daf8208SAnirudh Venkataramanan struct ice_aqc_sw_rules sw_rules; 1339dc49c772SAnirudh Venkataramanan struct ice_aqc_get_topo get_topo; 13401f9c7840SAnirudh Venkataramanan struct ice_aqc_sched_elem_cmd sched_elem_cmd; 13419c20346bSAnirudh Venkataramanan struct ice_aqc_query_txsched_res query_sched_res; 1342f31e4b6fSAnirudh Venkataramanan struct ice_aqc_nvm nvm; 1343007676b4SAnirudh Venkataramanan struct ice_aqc_pf_vf_msg virt; 1344d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_lut get_set_rss_lut; 1345d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_key get_set_rss_key; 1346cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs add_txqs; 1347cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txqs dis_txqs; 13483a858ba3SAnirudh Venkataramanan struct ice_aqc_add_get_update_free_vsi vsi_cmd; 13490f9d5027SAnirudh Venkataramanan struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 13508b97ceb1SHieu Tran struct ice_aqc_fw_logging fw_logging; 13518b97ceb1SHieu Tran struct ice_aqc_get_clear_fw_log get_clear_fw_log; 13529daf8208SAnirudh Venkataramanan struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 13530b28b702SAnirudh Venkataramanan struct ice_aqc_set_event_mask set_event_mask; 1354dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status get_link_status; 13557ec59eeaSAnirudh Venkataramanan } params; 13567ec59eeaSAnirudh Venkataramanan }; 13577ec59eeaSAnirudh Venkataramanan 13587ec59eeaSAnirudh Venkataramanan /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 13597ec59eeaSAnirudh Venkataramanan #define ICE_AQ_LG_BUF 512 13607ec59eeaSAnirudh Venkataramanan 1361940b61afSAnirudh Venkataramanan #define ICE_AQ_FLAG_ERR_S 2 13627ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_LB_S 9 13639c20346bSAnirudh Venkataramanan #define ICE_AQ_FLAG_RD_S 10 13647ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_BUF_S 12 13657ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_SI_S 13 13667ec59eeaSAnirudh Venkataramanan 1367940b61afSAnirudh Venkataramanan #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 13687ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 13699c20346bSAnirudh Venkataramanan #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 13707ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 13717ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 13727ec59eeaSAnirudh Venkataramanan 13737ec59eeaSAnirudh Venkataramanan /* error codes */ 13747ec59eeaSAnirudh Venkataramanan enum ice_aq_err { 1375df17b7e0SAnirudh Venkataramanan ICE_AQ_RC_OK = 0, /* Success */ 13769c20346bSAnirudh Venkataramanan ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 1377f31e4b6fSAnirudh Venkataramanan ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 1378df17b7e0SAnirudh Venkataramanan ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 1379e94d4478SAnirudh Venkataramanan ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 13807ec59eeaSAnirudh Venkataramanan }; 13817ec59eeaSAnirudh Venkataramanan 13827ec59eeaSAnirudh Venkataramanan /* Admin Queue command opcodes */ 13837ec59eeaSAnirudh Venkataramanan enum ice_adminq_opc { 13847ec59eeaSAnirudh Venkataramanan /* AQ commands */ 13857ec59eeaSAnirudh Venkataramanan ice_aqc_opc_get_ver = 0x0001, 13867ec59eeaSAnirudh Venkataramanan ice_aqc_opc_q_shutdown = 0x0003, 1387f31e4b6fSAnirudh Venkataramanan 1388f31e4b6fSAnirudh Venkataramanan /* resource ownership */ 1389f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_req_res = 0x0008, 1390f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_release_res = 0x0009, 1391f31e4b6fSAnirudh Venkataramanan 13929c20346bSAnirudh Venkataramanan /* device/function capabilities */ 13939c20346bSAnirudh Venkataramanan ice_aqc_opc_list_func_caps = 0x000A, 13949c20346bSAnirudh Venkataramanan ice_aqc_opc_list_dev_caps = 0x000B, 13959c20346bSAnirudh Venkataramanan 1396dc49c772SAnirudh Venkataramanan /* manage MAC address */ 1397dc49c772SAnirudh Venkataramanan ice_aqc_opc_manage_mac_read = 0x0107, 1398e94d4478SAnirudh Venkataramanan ice_aqc_opc_manage_mac_write = 0x0108, 1399dc49c772SAnirudh Venkataramanan 1400f31e4b6fSAnirudh Venkataramanan /* PXE */ 1401f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_clear_pxe_mode = 0x0110, 1402f31e4b6fSAnirudh Venkataramanan 14039c20346bSAnirudh Venkataramanan /* internal switch commands */ 14049c20346bSAnirudh Venkataramanan ice_aqc_opc_get_sw_cfg = 0x0200, 14059c20346bSAnirudh Venkataramanan 14069daf8208SAnirudh Venkataramanan /* Alloc/Free/Get Resources */ 14079daf8208SAnirudh Venkataramanan ice_aqc_opc_alloc_res = 0x0208, 14089daf8208SAnirudh Venkataramanan ice_aqc_opc_free_res = 0x0209, 14099daf8208SAnirudh Venkataramanan 14103a858ba3SAnirudh Venkataramanan /* VSI commands */ 14113a858ba3SAnirudh Venkataramanan ice_aqc_opc_add_vsi = 0x0210, 14123a858ba3SAnirudh Venkataramanan ice_aqc_opc_update_vsi = 0x0211, 14133a858ba3SAnirudh Venkataramanan ice_aqc_opc_free_vsi = 0x0213, 14149daf8208SAnirudh Venkataramanan 14159daf8208SAnirudh Venkataramanan /* switch rules population commands */ 14169daf8208SAnirudh Venkataramanan ice_aqc_opc_add_sw_rules = 0x02A0, 14179daf8208SAnirudh Venkataramanan ice_aqc_opc_update_sw_rules = 0x02A1, 14189daf8208SAnirudh Venkataramanan ice_aqc_opc_remove_sw_rules = 0x02A2, 14199daf8208SAnirudh Venkataramanan 1420f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_clear_pf_cfg = 0x02A4, 1421f31e4b6fSAnirudh Venkataramanan 14229c20346bSAnirudh Venkataramanan /* transmit scheduler commands */ 1423dc49c772SAnirudh Venkataramanan ice_aqc_opc_get_dflt_topo = 0x0400, 14245513b920SAnirudh Venkataramanan ice_aqc_opc_add_sched_elems = 0x0401, 142556daee6cSAnirudh Venkataramanan ice_aqc_opc_get_sched_elems = 0x0404, 14265513b920SAnirudh Venkataramanan ice_aqc_opc_suspend_sched_elems = 0x0409, 14275513b920SAnirudh Venkataramanan ice_aqc_opc_resume_sched_elems = 0x040A, 14289c20346bSAnirudh Venkataramanan ice_aqc_opc_delete_sched_elems = 0x040F, 14299c20346bSAnirudh Venkataramanan ice_aqc_opc_query_sched_res = 0x0412, 14309c20346bSAnirudh Venkataramanan 1431dc49c772SAnirudh Venkataramanan /* PHY commands */ 1432dc49c772SAnirudh Venkataramanan ice_aqc_opc_get_phy_caps = 0x0600, 1433fcea6f3dSAnirudh Venkataramanan ice_aqc_opc_set_phy_cfg = 0x0601, 1434fcea6f3dSAnirudh Venkataramanan ice_aqc_opc_restart_an = 0x0605, 1435dc49c772SAnirudh Venkataramanan ice_aqc_opc_get_link_status = 0x0607, 14360b28b702SAnirudh Venkataramanan ice_aqc_opc_set_event_mask = 0x0613, 1437dc49c772SAnirudh Venkataramanan 1438f31e4b6fSAnirudh Venkataramanan /* NVM commands */ 1439f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_nvm_read = 0x0701, 1440f31e4b6fSAnirudh Venkataramanan 1441007676b4SAnirudh Venkataramanan /* PF/VF mailbox commands */ 14421071a835SAnirudh Venkataramanan ice_mbx_opc_send_msg_to_pf = 0x0801, 1443007676b4SAnirudh Venkataramanan ice_mbx_opc_send_msg_to_vf = 0x0802, 1444007676b4SAnirudh Venkataramanan 1445d76a60baSAnirudh Venkataramanan /* RSS commands */ 1446d76a60baSAnirudh Venkataramanan ice_aqc_opc_set_rss_key = 0x0B02, 1447d76a60baSAnirudh Venkataramanan ice_aqc_opc_set_rss_lut = 0x0B03, 1448d76a60baSAnirudh Venkataramanan ice_aqc_opc_get_rss_key = 0x0B04, 1449d76a60baSAnirudh Venkataramanan ice_aqc_opc_get_rss_lut = 0x0B05, 1450d76a60baSAnirudh Venkataramanan 1451cdedef59SAnirudh Venkataramanan /* TX queue handling commands/events */ 1452cdedef59SAnirudh Venkataramanan ice_aqc_opc_add_txqs = 0x0C30, 1453cdedef59SAnirudh Venkataramanan ice_aqc_opc_dis_txqs = 0x0C31, 14548b97ceb1SHieu Tran 14558b97ceb1SHieu Tran /* debug commands */ 14568b97ceb1SHieu Tran ice_aqc_opc_fw_logging = 0xFF09, 14577ec59eeaSAnirudh Venkataramanan }; 14587ec59eeaSAnirudh Venkataramanan 14597ec59eeaSAnirudh Venkataramanan #endif /* _ICE_ADMINQ_CMD_H_ */ 1460