17ec59eeaSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 27ec59eeaSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 37ec59eeaSAnirudh Venkataramanan 47ec59eeaSAnirudh Venkataramanan #ifndef _ICE_ADMINQ_CMD_H_ 57ec59eeaSAnirudh Venkataramanan #define _ICE_ADMINQ_CMD_H_ 67ec59eeaSAnirudh Venkataramanan 77ec59eeaSAnirudh Venkataramanan /* This header file defines the Admin Queue commands, error codes and 87ec59eeaSAnirudh Venkataramanan * descriptor format. It is shared between Firmware and Software. 97ec59eeaSAnirudh Venkataramanan */ 107ec59eeaSAnirudh Venkataramanan 119daf8208SAnirudh Venkataramanan #define ICE_MAX_VSI 768 129c20346bSAnirudh Venkataramanan #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 133a858ba3SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 149c20346bSAnirudh Venkataramanan 157ec59eeaSAnirudh Venkataramanan struct ice_aqc_generic { 167ec59eeaSAnirudh Venkataramanan __le32 param0; 177ec59eeaSAnirudh Venkataramanan __le32 param1; 187ec59eeaSAnirudh Venkataramanan __le32 addr_high; 197ec59eeaSAnirudh Venkataramanan __le32 addr_low; 207ec59eeaSAnirudh Venkataramanan }; 217ec59eeaSAnirudh Venkataramanan 227ec59eeaSAnirudh Venkataramanan /* Get version (direct 0x0001) */ 237ec59eeaSAnirudh Venkataramanan struct ice_aqc_get_ver { 247ec59eeaSAnirudh Venkataramanan __le32 rom_ver; 257ec59eeaSAnirudh Venkataramanan __le32 fw_build; 267ec59eeaSAnirudh Venkataramanan u8 fw_branch; 277ec59eeaSAnirudh Venkataramanan u8 fw_major; 287ec59eeaSAnirudh Venkataramanan u8 fw_minor; 297ec59eeaSAnirudh Venkataramanan u8 fw_patch; 307ec59eeaSAnirudh Venkataramanan u8 api_branch; 317ec59eeaSAnirudh Venkataramanan u8 api_major; 327ec59eeaSAnirudh Venkataramanan u8 api_minor; 337ec59eeaSAnirudh Venkataramanan u8 api_patch; 347ec59eeaSAnirudh Venkataramanan }; 357ec59eeaSAnirudh Venkataramanan 36e3710a01SPaul M Stillwell Jr /* Send driver version (indirect 0x0002) */ 37e3710a01SPaul M Stillwell Jr struct ice_aqc_driver_ver { 38e3710a01SPaul M Stillwell Jr u8 major_ver; 39e3710a01SPaul M Stillwell Jr u8 minor_ver; 40e3710a01SPaul M Stillwell Jr u8 build_ver; 41e3710a01SPaul M Stillwell Jr u8 subbuild_ver; 42e3710a01SPaul M Stillwell Jr u8 reserved[4]; 43e3710a01SPaul M Stillwell Jr __le32 addr_high; 44e3710a01SPaul M Stillwell Jr __le32 addr_low; 45e3710a01SPaul M Stillwell Jr }; 46e3710a01SPaul M Stillwell Jr 477ec59eeaSAnirudh Venkataramanan /* Queue Shutdown (direct 0x0003) */ 487ec59eeaSAnirudh Venkataramanan struct ice_aqc_q_shutdown { 497404e84aSBruce Allan u8 driver_unloading; 5049c6e41bSAnirudh Venkataramanan #define ICE_AQC_DRIVER_UNLOADING BIT(0) 517404e84aSBruce Allan u8 reserved[15]; 527ec59eeaSAnirudh Venkataramanan }; 537ec59eeaSAnirudh Venkataramanan 54f31e4b6fSAnirudh Venkataramanan /* Request resource ownership (direct 0x0008) 55f31e4b6fSAnirudh Venkataramanan * Release resource ownership (direct 0x0009) 56f31e4b6fSAnirudh Venkataramanan */ 57f31e4b6fSAnirudh Venkataramanan struct ice_aqc_req_res { 58f31e4b6fSAnirudh Venkataramanan __le16 res_id; 59f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_NVM 1 60f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_SDP 2 61f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_CHNG_LOCK 3 62f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ID_GLBL_LOCK 4 63f31e4b6fSAnirudh Venkataramanan __le16 access_type; 64f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ACCESS_READ 1 65f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_RES_ACCESS_WRITE 2 66f31e4b6fSAnirudh Venkataramanan 67f31e4b6fSAnirudh Venkataramanan /* Upon successful completion, FW writes this value and driver is 68f31e4b6fSAnirudh Venkataramanan * expected to release resource before timeout. This value is provided 69f31e4b6fSAnirudh Venkataramanan * in milliseconds. 70f31e4b6fSAnirudh Venkataramanan */ 71f31e4b6fSAnirudh Venkataramanan __le32 timeout; 72f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 73f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 74f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 75f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 76f9867df6SAnirudh Venkataramanan /* For SDP: pin ID of the SDP */ 77f31e4b6fSAnirudh Venkataramanan __le32 res_number; 78f31e4b6fSAnirudh Venkataramanan /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 79f31e4b6fSAnirudh Venkataramanan __le16 status; 80f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_SUCCESS 0 81f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_IN_PROG 1 82f31e4b6fSAnirudh Venkataramanan #define ICE_AQ_RES_GLBL_DONE 2 83f31e4b6fSAnirudh Venkataramanan u8 reserved[2]; 84f31e4b6fSAnirudh Venkataramanan }; 85f31e4b6fSAnirudh Venkataramanan 869c20346bSAnirudh Venkataramanan /* Get function capabilities (indirect 0x000A) 879c20346bSAnirudh Venkataramanan * Get device capabilities (indirect 0x000B) 889c20346bSAnirudh Venkataramanan */ 899c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps { 909c20346bSAnirudh Venkataramanan u8 cmd_flags; 919c20346bSAnirudh Venkataramanan u8 pf_index; 929c20346bSAnirudh Venkataramanan u8 reserved[2]; 939c20346bSAnirudh Venkataramanan __le32 count; 949c20346bSAnirudh Venkataramanan __le32 addr_high; 959c20346bSAnirudh Venkataramanan __le32 addr_low; 969c20346bSAnirudh Venkataramanan }; 979c20346bSAnirudh Venkataramanan 989c20346bSAnirudh Venkataramanan /* Device/Function buffer entry, repeated per reported capability */ 999c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps_elem { 1009c20346bSAnirudh Venkataramanan __le16 cap; 101995c90f2SAnirudh Venkataramanan #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 10275d2b253SAnirudh Venkataramanan #define ICE_AQC_CAPS_SRIOV 0x0012 10375d2b253SAnirudh Venkataramanan #define ICE_AQC_CAPS_VF 0x0013 1049c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_VSI 0x0017 105a257f188SUsha Ketineni #define ICE_AQC_CAPS_DCB 0x0018 1069c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_RSS 0x0040 1079c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_RXQS 0x0041 1089c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_TXQS 0x0042 1099c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_MSIX 0x0043 110148beb61SHenry Tieman #define ICE_AQC_CAPS_FD 0x0045 1119733cc94SJacob Keller #define ICE_AQC_CAPS_1588 0x0046 1129c20346bSAnirudh Venkataramanan #define ICE_AQC_CAPS_MAX_MTU 0x0047 1132ab560a7SJacob Keller #define ICE_AQC_CAPS_NVM_VER 0x0048 1142ab560a7SJacob Keller #define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049 1152ab560a7SJacob Keller #define ICE_AQC_CAPS_OROM_VER 0x004A 1162ab560a7SJacob Keller #define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B 1172ab560a7SJacob Keller #define ICE_AQC_CAPS_NET_VER 0x004C 1182ab560a7SJacob Keller #define ICE_AQC_CAPS_PENDING_NET_VER 0x004D 119d25a0fc4SDave Ertman #define ICE_AQC_CAPS_RDMA 0x0051 120399e27dbSJacob Keller #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 121399e27dbSJacob Keller #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 122de9b277eSJacek Naczyk #define ICE_AQC_CAPS_NVM_MGMT 0x0080 123bb52f42aSDave Ertman #define ICE_AQC_CAPS_FW_LAG_SUPPORT 0x0092 124bb52f42aSDave Ertman #define ICE_AQC_BIT_ROCEV2_LAG 0x01 125bb52f42aSDave Ertman #define ICE_AQC_BIT_SRIOV_LAG 0x02 1269c20346bSAnirudh Venkataramanan 1279c20346bSAnirudh Venkataramanan u8 major_ver; 1289c20346bSAnirudh Venkataramanan u8 minor_ver; 1299c20346bSAnirudh Venkataramanan /* Number of resources described by this capability */ 1309c20346bSAnirudh Venkataramanan __le32 number; 1319c20346bSAnirudh Venkataramanan /* Only meaningful for some types of resources */ 1329c20346bSAnirudh Venkataramanan __le32 logical_id; 1339c20346bSAnirudh Venkataramanan /* Only meaningful for some types of resources */ 1349c20346bSAnirudh Venkataramanan __le32 phys_id; 1359c20346bSAnirudh Venkataramanan __le64 rsvd1; 1369c20346bSAnirudh Venkataramanan __le64 rsvd2; 1379c20346bSAnirudh Venkataramanan }; 1389c20346bSAnirudh Venkataramanan 139dc49c772SAnirudh Venkataramanan /* Manage MAC address, read command - indirect (0x0107) 140dc49c772SAnirudh Venkataramanan * This struct is also used for the response 141dc49c772SAnirudh Venkataramanan */ 142dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read { 143dc49c772SAnirudh Venkataramanan __le16 flags; /* Zeroed by device driver */ 144dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 145dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 146dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 147dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 148dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_READ_S 4 149dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 15062f4dafcSAnirudh Venkataramanan u8 rsvd[2]; 151dc49c772SAnirudh Venkataramanan u8 num_addr; /* Used in response */ 15262f4dafcSAnirudh Venkataramanan u8 rsvd1[3]; 153dc49c772SAnirudh Venkataramanan __le32 addr_high; 154dc49c772SAnirudh Venkataramanan __le32 addr_low; 155dc49c772SAnirudh Venkataramanan }; 156dc49c772SAnirudh Venkataramanan 157dc49c772SAnirudh Venkataramanan /* Response buffer format for manage MAC read command */ 158dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read_resp { 159dc49c772SAnirudh Venkataramanan u8 lport_num; 160dc49c772SAnirudh Venkataramanan u8 addr_type; 161dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 162dc49c772SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 163dc49c772SAnirudh Venkataramanan u8 mac_addr[ETH_ALEN]; 164dc49c772SAnirudh Venkataramanan }; 165dc49c772SAnirudh Venkataramanan 166e94d4478SAnirudh Venkataramanan /* Manage MAC address, write command - direct (0x0108) */ 167e94d4478SAnirudh Venkataramanan struct ice_aqc_manage_mac_write { 16862f4dafcSAnirudh Venkataramanan u8 rsvd; 169e94d4478SAnirudh Venkataramanan u8 flags; 170e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 171e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 172e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_WR_S 6 1735df42c82SJesse Brandeburg #define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S) 174e94d4478SAnirudh Venkataramanan #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 1755df42c82SJesse Brandeburg #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 1765df42c82SJesse Brandeburg /* byte stream in network order */ 1775df42c82SJesse Brandeburg u8 mac_addr[ETH_ALEN]; 178e94d4478SAnirudh Venkataramanan __le32 addr_high; 179e94d4478SAnirudh Venkataramanan __le32 addr_low; 180e94d4478SAnirudh Venkataramanan }; 181e94d4478SAnirudh Venkataramanan 182f31e4b6fSAnirudh Venkataramanan /* Clear PXE Command and response (direct 0x0110) */ 183f31e4b6fSAnirudh Venkataramanan struct ice_aqc_clear_pxe { 184f31e4b6fSAnirudh Venkataramanan u8 rx_cnt; 185f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 186f31e4b6fSAnirudh Venkataramanan u8 reserved[15]; 187f31e4b6fSAnirudh Venkataramanan }; 188f31e4b6fSAnirudh Venkataramanan 1899c20346bSAnirudh Venkataramanan /* Get switch configuration (0x0200) */ 1909c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg { 1919c20346bSAnirudh Venkataramanan /* Reserved for command and copy of request flags for response */ 1929c20346bSAnirudh Venkataramanan __le16 flags; 1939c20346bSAnirudh Venkataramanan /* First desc in case of command and next_elem in case of response 1949c20346bSAnirudh Venkataramanan * In case of response, if it is not zero, means all the configuration 1959c20346bSAnirudh Venkataramanan * was not returned and new command shall be sent with this value in 1969c20346bSAnirudh Venkataramanan * the 'first desc' field 1979c20346bSAnirudh Venkataramanan */ 1989c20346bSAnirudh Venkataramanan __le16 element; 1999c20346bSAnirudh Venkataramanan /* Reserved for command, only used for response */ 2009c20346bSAnirudh Venkataramanan __le16 num_elems; 2019c20346bSAnirudh Venkataramanan __le16 rsvd; 2029c20346bSAnirudh Venkataramanan __le32 addr_high; 2039c20346bSAnirudh Venkataramanan __le32 addr_low; 2049c20346bSAnirudh Venkataramanan }; 2059c20346bSAnirudh Venkataramanan 2069c20346bSAnirudh Venkataramanan /* Each entry in the response buffer is of the following type: */ 2079c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg_resp_elem { 2089c20346bSAnirudh Venkataramanan /* VSI/Port Number */ 2099c20346bSAnirudh Venkataramanan __le16 vsi_port_num; 2109c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 2119c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 2129c20346bSAnirudh Venkataramanan (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 2139c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 2149c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 2159c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 2169c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 2179c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 2189c20346bSAnirudh Venkataramanan 2199c20346bSAnirudh Venkataramanan /* SWID VSI/Port belongs to */ 2209c20346bSAnirudh Venkataramanan __le16 swid; 2219c20346bSAnirudh Venkataramanan 2229c20346bSAnirudh Venkataramanan /* Bit 14..0 : PF/VF number VSI belongs to 2239c20346bSAnirudh Venkataramanan * Bit 15 : VF indication bit 2249c20346bSAnirudh Venkataramanan */ 2259c20346bSAnirudh Venkataramanan __le16 pf_vf_num; 2269c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 2279c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 2289c20346bSAnirudh Venkataramanan (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 2299c20346bSAnirudh Venkataramanan #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 2309c20346bSAnirudh Venkataramanan }; 2319c20346bSAnirudh Venkataramanan 232a1ffafb0SBrett Creeley /* Set Port parameters, (direct, 0x0203) */ 233a1ffafb0SBrett Creeley struct ice_aqc_set_port_params { 234a1ffafb0SBrett Creeley __le16 cmd_flags; 235a1ffafb0SBrett Creeley #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 236a1ffafb0SBrett Creeley __le16 bad_frame_vsi; 237a1ffafb0SBrett Creeley __le16 swid; 23823ccae5cSDave Ertman #define ICE_AQC_PORT_SWID_VALID BIT(15) 23923ccae5cSDave Ertman #define ICE_AQC_PORT_SWID_M 0xFF 240a1ffafb0SBrett Creeley u8 reserved[10]; 241a1ffafb0SBrett Creeley }; 242a1ffafb0SBrett Creeley 2439daf8208SAnirudh Venkataramanan /* These resource type defines are used for all switch resource 2449daf8208SAnirudh Venkataramanan * commands where a resource type is required, such as: 2459daf8208SAnirudh Venkataramanan * Get Resource Allocation command (indirect 0x0204) 2469daf8208SAnirudh Venkataramanan * Allocate Resources command (indirect 0x0208) 2479daf8208SAnirudh Venkataramanan * Free Resources command (indirect 0x0209) 2489daf8208SAnirudh Venkataramanan * Get Allocated Resource Descriptors Command (indirect 0x020A) 24923ccae5cSDave Ertman * Share Resource command (indirect 0x020B) 2509daf8208SAnirudh Venkataramanan */ 2519daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 2529daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 2537715ec32SGrishma Kotecha #define ICE_AQC_RES_TYPE_RECIPE 0x05 25423ccae5cSDave Ertman #define ICE_AQC_RES_TYPE_SWID 0x07 255148beb61SHenry Tieman #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 256148beb61SHenry Tieman #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 257148beb61SHenry Tieman #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 258148beb61SHenry Tieman #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58 259148beb61SHenry Tieman #define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59 26031ad4e4eSTony Nguyen #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 261451f2c44STony Nguyen #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 26231ad4e4eSTony Nguyen 2637715ec32SGrishma Kotecha #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 26431ad4e4eSTony Nguyen #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 26531ad4e4eSTony Nguyen #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 26631ad4e4eSTony Nguyen 26731ad4e4eSTony Nguyen #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 2689daf8208SAnirudh Venkataramanan 269148beb61SHenry Tieman #define ICE_AQC_RES_TYPE_S 0 270148beb61SHenry Tieman #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 271148beb61SHenry Tieman 2729daf8208SAnirudh Venkataramanan /* Allocate Resources command (indirect 0x0208) 2739daf8208SAnirudh Venkataramanan * Free Resources command (indirect 0x0209) 27423ccae5cSDave Ertman * Share Resource command (indirect 0x020B) 2759daf8208SAnirudh Venkataramanan */ 2769daf8208SAnirudh Venkataramanan struct ice_aqc_alloc_free_res_cmd { 2779daf8208SAnirudh Venkataramanan __le16 num_entries; /* Number of Resource entries */ 2789daf8208SAnirudh Venkataramanan u8 reserved[6]; 2799daf8208SAnirudh Venkataramanan __le32 addr_high; 2809daf8208SAnirudh Venkataramanan __le32 addr_low; 2819daf8208SAnirudh Venkataramanan }; 2829daf8208SAnirudh Venkataramanan 2839daf8208SAnirudh Venkataramanan /* Resource descriptor */ 2849daf8208SAnirudh Venkataramanan struct ice_aqc_res_elem { 2859daf8208SAnirudh Venkataramanan union { 2869daf8208SAnirudh Venkataramanan __le16 sw_resp; 2879daf8208SAnirudh Venkataramanan __le16 flu_resp; 2889daf8208SAnirudh Venkataramanan } e; 2899daf8208SAnirudh Venkataramanan }; 2909daf8208SAnirudh Venkataramanan 2919daf8208SAnirudh Venkataramanan /* Buffer for Allocate/Free Resources commands */ 2929daf8208SAnirudh Venkataramanan struct ice_aqc_alloc_free_res_elem { 2939daf8208SAnirudh Venkataramanan __le16 res_type; /* Types defined above cmd 0x0204 */ 2949daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_SHARED_S 7 2959daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) 2969daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 2979daf8208SAnirudh Venkataramanan #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 2989daf8208SAnirudh Venkataramanan (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 2999daf8208SAnirudh Venkataramanan __le16 num_elems; 30066486d89SBruce Allan struct ice_aqc_res_elem elem[]; 3019daf8208SAnirudh Venkataramanan }; 3029daf8208SAnirudh Venkataramanan 303a1ffafb0SBrett Creeley /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 304a1ffafb0SBrett Creeley struct ice_aqc_set_vlan_mode { 305a1ffafb0SBrett Creeley u8 reserved; 306a1ffafb0SBrett Creeley u8 l2tag_prio_tagging; 307a1ffafb0SBrett Creeley #define ICE_AQ_VLAN_PRIO_TAG_S 0 308a1ffafb0SBrett Creeley #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 309a1ffafb0SBrett Creeley #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 310a1ffafb0SBrett Creeley #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 311a1ffafb0SBrett Creeley #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 312a1ffafb0SBrett Creeley #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 313a1ffafb0SBrett Creeley #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 314a1ffafb0SBrett Creeley #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 315a1ffafb0SBrett Creeley #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 316a1ffafb0SBrett Creeley u8 l2tag_reserved[64]; 317a1ffafb0SBrett Creeley u8 rdma_packet; 318a1ffafb0SBrett Creeley #define ICE_AQ_VLAN_RDMA_TAG_S 0 319a1ffafb0SBrett Creeley #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 320a1ffafb0SBrett Creeley #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 321a1ffafb0SBrett Creeley #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 322a1ffafb0SBrett Creeley u8 rdma_reserved[2]; 323a1ffafb0SBrett Creeley u8 mng_vlan_prot_id; 324a1ffafb0SBrett Creeley #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 325a1ffafb0SBrett Creeley #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 326a1ffafb0SBrett Creeley u8 prot_id_reserved[30]; 327a1ffafb0SBrett Creeley }; 328a1ffafb0SBrett Creeley 329a1ffafb0SBrett Creeley /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 330a1ffafb0SBrett Creeley struct ice_aqc_get_vlan_mode { 331a1ffafb0SBrett Creeley u8 vlan_mode; 332a1ffafb0SBrett Creeley #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 333a1ffafb0SBrett Creeley u8 l2tag_prio_tagging; 334a1ffafb0SBrett Creeley u8 reserved[98]; 335a1ffafb0SBrett Creeley }; 336a1ffafb0SBrett Creeley 3373a858ba3SAnirudh Venkataramanan /* Add VSI (indirect 0x0210) 3383a858ba3SAnirudh Venkataramanan * Update VSI (indirect 0x0211) 3393a858ba3SAnirudh Venkataramanan * Get VSI (indirect 0x0212) 3403a858ba3SAnirudh Venkataramanan * Free VSI (indirect 0x0213) 3413a858ba3SAnirudh Venkataramanan */ 3423a858ba3SAnirudh Venkataramanan struct ice_aqc_add_get_update_free_vsi { 3433a858ba3SAnirudh Venkataramanan __le16 vsi_num; 3443a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_NUM_S 0 3453a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 3463a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_IS_VALID BIT(15) 3473a858ba3SAnirudh Venkataramanan __le16 cmd_flags; 3483a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_KEEP_ALLOC 0x1 3493a858ba3SAnirudh Venkataramanan u8 vf_id; 3503a858ba3SAnirudh Venkataramanan u8 reserved; 3513a858ba3SAnirudh Venkataramanan __le16 vsi_flags; 3523a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_S 0 3533a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 3543a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_VF 0x0 3553a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 3563a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_PF 0x2 3573a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 3583a858ba3SAnirudh Venkataramanan __le32 addr_high; 3593a858ba3SAnirudh Venkataramanan __le32 addr_low; 3603a858ba3SAnirudh Venkataramanan }; 3613a858ba3SAnirudh Venkataramanan 3623a858ba3SAnirudh Venkataramanan /* Response descriptor for: 3633a858ba3SAnirudh Venkataramanan * Add VSI (indirect 0x0210) 3643a858ba3SAnirudh Venkataramanan * Update VSI (indirect 0x0211) 3653a858ba3SAnirudh Venkataramanan * Free VSI (indirect 0x0213) 3663a858ba3SAnirudh Venkataramanan */ 3673a858ba3SAnirudh Venkataramanan struct ice_aqc_add_update_free_vsi_resp { 3683a858ba3SAnirudh Venkataramanan __le16 vsi_num; 3693a858ba3SAnirudh Venkataramanan __le16 ext_status; 3703a858ba3SAnirudh Venkataramanan __le16 vsi_used; 3713a858ba3SAnirudh Venkataramanan __le16 vsi_free; 3723a858ba3SAnirudh Venkataramanan __le32 addr_high; 3733a858ba3SAnirudh Venkataramanan __le32 addr_low; 3743a858ba3SAnirudh Venkataramanan }; 3753a858ba3SAnirudh Venkataramanan 3763a858ba3SAnirudh Venkataramanan struct ice_aqc_vsi_props { 3773a858ba3SAnirudh Venkataramanan __le16 valid_sections; 3783a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 3793a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 3803a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 3813a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 3823a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 3833a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 3843a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 3853a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 3863a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 3873a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 3883a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 3893a858ba3SAnirudh Venkataramanan /* switch section */ 3903a858ba3SAnirudh Venkataramanan u8 sw_id; 3913a858ba3SAnirudh Venkataramanan u8 sw_flags; 3923a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 3933a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 3943a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 3953a858ba3SAnirudh Venkataramanan u8 sw_flags2; 3963a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 3977bd527aaSBrett Creeley #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 3983a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 3993a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 4003a858ba3SAnirudh Venkataramanan u8 veb_stat_id; 4013a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 4023a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 4033a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 4043a858ba3SAnirudh Venkataramanan /* security section */ 4053a858ba3SAnirudh Venkataramanan u8 sec_flags; 4063a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 4073a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 4083a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 4093a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 4103a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 4113a858ba3SAnirudh Venkataramanan u8 sec_reserved; 4123a858ba3SAnirudh Venkataramanan /* VLAN section */ 4137bd527aaSBrett Creeley __le16 port_based_inner_vlan; /* VLANS include priority bits */ 4147bd527aaSBrett Creeley u8 inner_vlan_reserved[2]; 4157bd527aaSBrett Creeley u8 inner_vlan_flags; 4167bd527aaSBrett Creeley #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 4177bd527aaSBrett Creeley #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 4187bd527aaSBrett Creeley #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 4197bd527aaSBrett Creeley #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 4207bd527aaSBrett Creeley #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 4217bd527aaSBrett Creeley #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 4227bd527aaSBrett Creeley #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 4237bd527aaSBrett Creeley #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 4246bc0e112SJesse Brandeburg #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH 0x0U 4256bc0e112SJesse Brandeburg #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP 0x1U 4266bc0e112SJesse Brandeburg #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR 0x2U 4276bc0e112SJesse Brandeburg #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING 0x3U 4287bd527aaSBrett Creeley u8 inner_vlan_reserved2[3]; 4293a858ba3SAnirudh Venkataramanan /* ingress egress up sections */ 4303a858ba3SAnirudh Venkataramanan __le32 ingress_table; /* bitmap, 3 bits per up */ 4313a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 4323a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 4333a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 4343a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 4353a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 4363a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 4373a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 4383a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 4393a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 4403a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 4413a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 4423a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 4433a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 4443a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 4453a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 4463a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 4473a858ba3SAnirudh Venkataramanan __le32 egress_table; /* same defines as for ingress table */ 4483a858ba3SAnirudh Venkataramanan /* outer tags section */ 4497bd527aaSBrett Creeley __le16 port_based_outer_vlan; 4507bd527aaSBrett Creeley u8 outer_vlan_flags; 4517bd527aaSBrett Creeley #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 4527bd527aaSBrett Creeley #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 4537bd527aaSBrett Creeley #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 4547bd527aaSBrett Creeley #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 4557bd527aaSBrett Creeley #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 4567bd527aaSBrett Creeley #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 4573a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 4583a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 4593a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 4603a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 4613a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 4623a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 4637bd527aaSBrett Creeley #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 4647bd527aaSBrett Creeley #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 4657bd527aaSBrett Creeley #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 4667bd527aaSBrett Creeley #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 4677bd527aaSBrett Creeley #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 4687bd527aaSBrett Creeley #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 4697bd527aaSBrett Creeley #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 4707bd527aaSBrett Creeley u8 outer_vlan_reserved; 4713a858ba3SAnirudh Venkataramanan /* queue mapping section */ 4723a858ba3SAnirudh Venkataramanan __le16 mapping_flags; 4733a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 4743a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 4753a858ba3SAnirudh Venkataramanan __le16 q_mapping[16]; 4763a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_S 0 4773a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 4783a858ba3SAnirudh Venkataramanan __le16 tc_mapping[8]; 4793a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 4803a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 4813a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_NUM_S 11 4823a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 4833a858ba3SAnirudh Venkataramanan /* queueing option section */ 4843a858ba3SAnirudh Venkataramanan u8 q_opt_rss; 4853a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 4863a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 4873a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 4883a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 4893a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 4903a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 4913a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 4923a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 4936bc0e112SJesse Brandeburg #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M GENMASK(7, 6) 494334a1227SAhmed Zaki #define ICE_AQ_VSI_Q_OPT_RSS_HASH_TPLZ 0x0U 495334a1227SAhmed Zaki #define ICE_AQ_VSI_Q_OPT_RSS_HASH_SYM_TPLZ 0x1U 496334a1227SAhmed Zaki #define ICE_AQ_VSI_Q_OPT_RSS_HASH_XOR 0x2U 497334a1227SAhmed Zaki #define ICE_AQ_VSI_Q_OPT_RSS_HASH_JHASH 0x3U 4983a858ba3SAnirudh Venkataramanan u8 q_opt_tc; 4993a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 5003a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 5013a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 5023a858ba3SAnirudh Venkataramanan u8 q_opt_flags; 5033a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 5043a858ba3SAnirudh Venkataramanan u8 q_opt_reserved[3]; 5053a858ba3SAnirudh Venkataramanan /* outer up section */ 5063a858ba3SAnirudh Venkataramanan __le32 outer_up_table; /* same structure and defines as ingress tbl */ 5073a858ba3SAnirudh Venkataramanan /* section 10 */ 5083a858ba3SAnirudh Venkataramanan __le16 sect_10_reserved; 5093a858ba3SAnirudh Venkataramanan /* flow director section */ 5103a858ba3SAnirudh Venkataramanan __le16 fd_options; 5113a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_ENABLE BIT(0) 5123a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 5133a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 5143a858ba3SAnirudh Venkataramanan __le16 max_fd_fltr_dedicated; 5153a858ba3SAnirudh Venkataramanan __le16 max_fd_fltr_shared; 5163a858ba3SAnirudh Venkataramanan __le16 fd_def_q; 5173a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_Q_S 0 5183a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 5193a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_GRP_S 12 5203a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 5213a858ba3SAnirudh Venkataramanan __le16 fd_report_opt; 5223a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_REPORT_Q_S 0 5233a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 5243a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 5253a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 5263a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 5273a858ba3SAnirudh Venkataramanan /* PASID section */ 5283a858ba3SAnirudh Venkataramanan __le32 pasid_id; 5293a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PASID_ID_S 0 5303a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 5313a858ba3SAnirudh Venkataramanan #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 5323a858ba3SAnirudh Venkataramanan u8 reserved[24]; 5333a858ba3SAnirudh Venkataramanan }; 5343a858ba3SAnirudh Venkataramanan 53580d144c9SAnirudh Venkataramanan #define ICE_MAX_NUM_RECIPES 64 53680d144c9SAnirudh Venkataramanan 5377715ec32SGrishma Kotecha /* Add/Get Recipe (indirect 0x0290/0x0292) */ 5387715ec32SGrishma Kotecha struct ice_aqc_add_get_recipe { 5397715ec32SGrishma Kotecha __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */ 5407715ec32SGrishma Kotecha __le16 return_index; /* Input, used for Get cmd only */ 5417715ec32SGrishma Kotecha u8 reserved[4]; 5427715ec32SGrishma Kotecha __le32 addr_high; 5437715ec32SGrishma Kotecha __le32 addr_low; 5447715ec32SGrishma Kotecha }; 5457715ec32SGrishma Kotecha 5467715ec32SGrishma Kotecha struct ice_aqc_recipe_content { 5477715ec32SGrishma Kotecha u8 rid; 548a1ffafb0SBrett Creeley #define ICE_AQ_RECIPE_ID_S 0 549a1ffafb0SBrett Creeley #define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S) 5507715ec32SGrishma Kotecha #define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7) 5517715ec32SGrishma Kotecha #define ICE_AQ_SW_ID_LKUP_IDX 0 5527715ec32SGrishma Kotecha u8 lkup_indx[5]; 553a1ffafb0SBrett Creeley #define ICE_AQ_RECIPE_LKUP_DATA_S 0 554a1ffafb0SBrett Creeley #define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S) 5557715ec32SGrishma Kotecha #define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7) 5567715ec32SGrishma Kotecha #define ICE_AQ_SW_ID_LKUP_MASK 0x00FF 5577715ec32SGrishma Kotecha __le16 mask[5]; 5587715ec32SGrishma Kotecha u8 result_indx; 5597715ec32SGrishma Kotecha #define ICE_AQ_RECIPE_RESULT_DATA_S 0 5607715ec32SGrishma Kotecha #define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S) 5617715ec32SGrishma Kotecha #define ICE_AQ_RECIPE_RESULT_EN BIT(7) 5627715ec32SGrishma Kotecha u8 rsvd0[3]; 5637715ec32SGrishma Kotecha u8 act_ctrl_join_priority; 5647715ec32SGrishma Kotecha u8 act_ctrl_fwd_priority; 565a1ffafb0SBrett Creeley #define ICE_AQ_RECIPE_FWD_PRIORITY_S 0 566a1ffafb0SBrett Creeley #define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S) 5677715ec32SGrishma Kotecha u8 act_ctrl; 568a1ffafb0SBrett Creeley #define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0) 569a1ffafb0SBrett Creeley #define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1) 5707715ec32SGrishma Kotecha #define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2) 571a1ffafb0SBrett Creeley #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4 572a1ffafb0SBrett Creeley #define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S) 5737715ec32SGrishma Kotecha u8 rsvd1; 5747715ec32SGrishma Kotecha __le32 dflt_act; 575a1ffafb0SBrett Creeley #define ICE_AQ_RECIPE_DFLT_ACT_S 0 576a1ffafb0SBrett Creeley #define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S) 577a1ffafb0SBrett Creeley #define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31) 5787715ec32SGrishma Kotecha }; 5797715ec32SGrishma Kotecha 5807715ec32SGrishma Kotecha struct ice_aqc_recipe_data_elem { 5817715ec32SGrishma Kotecha u8 recipe_indx; 5827715ec32SGrishma Kotecha u8 resp_bits; 583a1ffafb0SBrett Creeley #define ICE_AQ_RECIPE_WAS_UPDATED BIT(0) 5847715ec32SGrishma Kotecha u8 rsvd0[2]; 5857715ec32SGrishma Kotecha u8 recipe_bitmap[8]; 5867715ec32SGrishma Kotecha u8 rsvd1[4]; 5877715ec32SGrishma Kotecha struct ice_aqc_recipe_content content; 5887715ec32SGrishma Kotecha u8 rsvd2[20]; 5897715ec32SGrishma Kotecha }; 5907715ec32SGrishma Kotecha 5917715ec32SGrishma Kotecha /* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */ 5927715ec32SGrishma Kotecha struct ice_aqc_recipe_to_profile { 5937715ec32SGrishma Kotecha __le16 profile_id; 5947715ec32SGrishma Kotecha u8 rsvd[6]; 595*493b2993SSteven Zou __le64 recipe_assoc; 5967715ec32SGrishma Kotecha }; 597*493b2993SSteven Zou static_assert(sizeof(struct ice_aqc_recipe_to_profile) == 16); 5987715ec32SGrishma Kotecha 5999daf8208SAnirudh Venkataramanan /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 6009daf8208SAnirudh Venkataramanan */ 6019daf8208SAnirudh Venkataramanan struct ice_aqc_sw_rules { 6029daf8208SAnirudh Venkataramanan /* ops: add switch rules, referring the number of rules. 6039daf8208SAnirudh Venkataramanan * ops: update switch rules, referring the number of filters 6049daf8208SAnirudh Venkataramanan * ops: remove switch rules, referring the entry index. 6059daf8208SAnirudh Venkataramanan * ops: get switch rules, referring to the number of filters. 6069daf8208SAnirudh Venkataramanan */ 6079daf8208SAnirudh Venkataramanan __le16 num_rules_fltr_entry_index; 6089daf8208SAnirudh Venkataramanan u8 reserved[6]; 6099daf8208SAnirudh Venkataramanan __le32 addr_high; 6109daf8208SAnirudh Venkataramanan __le32 addr_low; 6119daf8208SAnirudh Venkataramanan }; 6129daf8208SAnirudh Venkataramanan 6136e1ff618SAlexander Lobakin /* Add switch rule response: 6146e1ff618SAlexander Lobakin * Content of return buffer is same as the input buffer. The status field and 6156e1ff618SAlexander Lobakin * LUT index are updated as part of the response 6166e1ff618SAlexander Lobakin */ 6176e1ff618SAlexander Lobakin struct ice_aqc_sw_rules_elem_hdr { 6186e1ff618SAlexander Lobakin __le16 type; /* Switch rule type, one of T_... */ 6196e1ff618SAlexander Lobakin #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 6206e1ff618SAlexander Lobakin #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 6216e1ff618SAlexander Lobakin #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 6226e1ff618SAlexander Lobakin #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 6236e1ff618SAlexander Lobakin #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 6246e1ff618SAlexander Lobakin #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 6256e1ff618SAlexander Lobakin #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 6266e1ff618SAlexander Lobakin __le16 status; 6276e1ff618SAlexander Lobakin } __packed __aligned(sizeof(__le16)); 6286e1ff618SAlexander Lobakin 6299daf8208SAnirudh Venkataramanan /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 6309daf8208SAnirudh Venkataramanan * This structures describes the lookup rules and associated actions. "index" 6319daf8208SAnirudh Venkataramanan * is returned as part of a response to a successful Add command, and can be 6329daf8208SAnirudh Venkataramanan * used to identify the rule for Update/Get/Remove commands. 6339daf8208SAnirudh Venkataramanan */ 6349daf8208SAnirudh Venkataramanan struct ice_sw_rule_lkup_rx_tx { 6356e1ff618SAlexander Lobakin struct ice_aqc_sw_rules_elem_hdr hdr; 6366e1ff618SAlexander Lobakin 6379daf8208SAnirudh Venkataramanan __le16 recipe_id; 6389daf8208SAnirudh Venkataramanan #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 6399daf8208SAnirudh Venkataramanan /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 6409daf8208SAnirudh Venkataramanan __le16 src; 6419daf8208SAnirudh Venkataramanan __le32 act; 6429daf8208SAnirudh Venkataramanan 6439daf8208SAnirudh Venkataramanan /* Bit 0:1 - Action type */ 6449daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_TYPE_S 0x00 6459daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 6469daf8208SAnirudh Venkataramanan 6479daf8208SAnirudh Venkataramanan /* Bit 2 - Loop back enable 6489daf8208SAnirudh Venkataramanan * Bit 3 - LAN enable 6499daf8208SAnirudh Venkataramanan */ 6509daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 6519daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 6529daf8208SAnirudh Venkataramanan 6539daf8208SAnirudh Venkataramanan /* Action type = 0 - Forward to VSI or VSI list */ 6549daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 6559daf8208SAnirudh Venkataramanan 6569daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_ID_S 4 6579daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 6589daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 6599daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 6609daf8208SAnirudh Venkataramanan /* This bit needs to be set if action is forward to VSI list */ 6619daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 6629daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 6639daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_DROP BIT(18) 6649daf8208SAnirudh Venkataramanan 6659daf8208SAnirudh Venkataramanan /* Action type = 1 - Forward to Queue of Queue group */ 6669daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_TO_Q 0x1 6679daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_INDEX_S 4 6689daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 6699daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_REGION_S 15 6709daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 6719daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 6729daf8208SAnirudh Venkataramanan 6739daf8208SAnirudh Venkataramanan /* Action type = 2 - Prune */ 6749daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PRUNE 0x2 6759daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_EGRESS BIT(15) 6769daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_INGRESS BIT(16) 6779daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PRUNET BIT(17) 6789daf8208SAnirudh Venkataramanan /* Bit 18 should be set to 0 for this action */ 6799daf8208SAnirudh Venkataramanan 6809daf8208SAnirudh Venkataramanan /* Action type = 2 - Pointer */ 6819daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR 0x2 6829daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR_VAL_S 4 6839daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 6849daf8208SAnirudh Venkataramanan /* Bit 18 should be set to 1 */ 6859daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 6869daf8208SAnirudh Venkataramanan 6879daf8208SAnirudh Venkataramanan /* Action type = 3 - Other actions. Last two bits 6889daf8208SAnirudh Venkataramanan * are other action identifier 6899daf8208SAnirudh Venkataramanan */ 6909daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 6919daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 6929daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 693c522d1f6SBruce Allan (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 6949daf8208SAnirudh Venkataramanan 6959daf8208SAnirudh Venkataramanan /* Bit 17:18 - Defines other actions */ 6969daf8208SAnirudh Venkataramanan /* Other action = 0 - Mirror VSI */ 6979daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_MIRROR 0 6989daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 6999daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 7009daf8208SAnirudh Venkataramanan (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 7019daf8208SAnirudh Venkataramanan 7029daf8208SAnirudh Venkataramanan /* Other action = 3 - Set Stat count */ 7039daf8208SAnirudh Venkataramanan #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 7049daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 7059daf8208SAnirudh Venkataramanan #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 7069daf8208SAnirudh Venkataramanan (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 7079daf8208SAnirudh Venkataramanan 7089daf8208SAnirudh Venkataramanan __le16 index; /* The index of the rule in the lookup table */ 7099daf8208SAnirudh Venkataramanan /* Length and values of the header to be matched per recipe or 7109daf8208SAnirudh Venkataramanan * lookup-type 7119daf8208SAnirudh Venkataramanan */ 7129daf8208SAnirudh Venkataramanan __le16 hdr_len; 7136e1ff618SAlexander Lobakin u8 hdr_data[]; 7146e1ff618SAlexander Lobakin } __packed __aligned(sizeof(__le16)); 7159daf8208SAnirudh Venkataramanan 7169daf8208SAnirudh Venkataramanan /* Add/Update/Remove large action command/response entry 7179daf8208SAnirudh Venkataramanan * "index" is returned as part of a response to a successful Add command, and 7189daf8208SAnirudh Venkataramanan * can be used to identify the action for Update/Get/Remove commands. 7199daf8208SAnirudh Venkataramanan */ 7209daf8208SAnirudh Venkataramanan struct ice_sw_rule_lg_act { 7216e1ff618SAlexander Lobakin struct ice_aqc_sw_rules_elem_hdr hdr; 7226e1ff618SAlexander Lobakin 7239daf8208SAnirudh Venkataramanan __le16 index; /* Index in large action table */ 7249daf8208SAnirudh Venkataramanan __le16 size; 7259daf8208SAnirudh Venkataramanan /* Max number of large actions */ 7269daf8208SAnirudh Venkataramanan #define ICE_MAX_LG_ACT 4 7279daf8208SAnirudh Venkataramanan /* Bit 0:1 - Action type */ 7289daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_TYPE_S 0 7299daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 7309daf8208SAnirudh Venkataramanan 7319daf8208SAnirudh Venkataramanan /* Action type = 0 - Forward to VSI or VSI list */ 7329daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_FORWARDING 0 7339daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_ID_S 3 7349daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 7359daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_LIST_ID_S 3 7369daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 7379daf8208SAnirudh Venkataramanan /* This bit needs to be set if action is forward to VSI list */ 7389daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VSI_LIST BIT(13) 7399daf8208SAnirudh Venkataramanan 7409daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_VALID_BIT BIT(16) 7419daf8208SAnirudh Venkataramanan 7429daf8208SAnirudh Venkataramanan /* Action type = 1 - Forward to Queue of Queue group */ 7439daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_TO_Q 0x1 7449daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_INDEX_S 3 7459daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 7469daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_REGION_S 14 7479daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 7489daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 7499daf8208SAnirudh Venkataramanan 7509daf8208SAnirudh Venkataramanan /* Action type = 2 - Prune */ 7519daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_PRUNE 0x2 7529daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_EGRESS BIT(14) 7539daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_INGRESS BIT(15) 7549daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_PRUNET BIT(16) 7559daf8208SAnirudh Venkataramanan 7569daf8208SAnirudh Venkataramanan /* Action type = 3 - Mirror VSI */ 7579daf8208SAnirudh Venkataramanan #define ICE_LG_OTHER_ACT_MIRROR 0x3 7589daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 7599daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 7609daf8208SAnirudh Venkataramanan 76134357a90SAnirudh Venkataramanan /* Action type = 5 - Generic Value */ 7629daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC 0x5 7639daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_VALUE_S 3 7649daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 7659daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_OFFSET_S 19 7669daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 7679daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 7689daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 7694381147dSAnirudh Venkataramanan #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 7709daf8208SAnirudh Venkataramanan 7719daf8208SAnirudh Venkataramanan /* Action = 7 - Set Stat count */ 7729daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_STAT_COUNT 0x7 7739daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_STAT_COUNT_S 3 7749daf8208SAnirudh Venkataramanan #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 77566486d89SBruce Allan __le32 act[]; /* array of size for actions */ 7766e1ff618SAlexander Lobakin } __packed __aligned(sizeof(__le16)); 7779daf8208SAnirudh Venkataramanan 7789daf8208SAnirudh Venkataramanan /* Add/Update/Remove VSI list command/response entry 7799daf8208SAnirudh Venkataramanan * "index" is returned as part of a response to a successful Add command, and 7809daf8208SAnirudh Venkataramanan * can be used to identify the VSI list for Update/Get/Remove commands. 7819daf8208SAnirudh Venkataramanan */ 7829daf8208SAnirudh Venkataramanan struct ice_sw_rule_vsi_list { 7836e1ff618SAlexander Lobakin struct ice_aqc_sw_rules_elem_hdr hdr; 7846e1ff618SAlexander Lobakin 7859daf8208SAnirudh Venkataramanan __le16 index; /* Index of VSI/Prune list */ 7869daf8208SAnirudh Venkataramanan __le16 number_vsi; 78766486d89SBruce Allan __le16 vsi[]; /* Array of number_vsi VSI numbers */ 7886e1ff618SAlexander Lobakin } __packed __aligned(sizeof(__le16)); 7899daf8208SAnirudh Venkataramanan 7902a87bd73SDave Ertman /* Query PFC Mode (direct 0x0302) 7912a87bd73SDave Ertman * Set PFC Mode (direct 0x0303) 7922a87bd73SDave Ertman */ 7932a87bd73SDave Ertman struct ice_aqc_set_query_pfc_mode { 7942a87bd73SDave Ertman u8 pfc_mode; 7952a87bd73SDave Ertman /* For Query Command response, reserved in all other cases */ 7962a87bd73SDave Ertman #define ICE_AQC_PFC_VLAN_BASED_PFC 1 7972a87bd73SDave Ertman #define ICE_AQC_PFC_DSCP_BASED_PFC 2 7982a87bd73SDave Ertman u8 rsvd[15]; 7992a87bd73SDave Ertman }; 800dc49c772SAnirudh Venkataramanan /* Get Default Topology (indirect 0x0400) */ 801dc49c772SAnirudh Venkataramanan struct ice_aqc_get_topo { 802dc49c772SAnirudh Venkataramanan u8 port_num; 803dc49c772SAnirudh Venkataramanan u8 num_branches; 804dc49c772SAnirudh Venkataramanan __le16 reserved1; 805dc49c772SAnirudh Venkataramanan __le32 reserved2; 806dc49c772SAnirudh Venkataramanan __le32 addr_high; 807dc49c772SAnirudh Venkataramanan __le32 addr_low; 808dc49c772SAnirudh Venkataramanan }; 809dc49c772SAnirudh Venkataramanan 8105513b920SAnirudh Venkataramanan /* Update TSE (indirect 0x0403) 8115513b920SAnirudh Venkataramanan * Get TSE (indirect 0x0404) 8121f9c7840SAnirudh Venkataramanan * Add TSE (indirect 0x0401) 8131f9c7840SAnirudh Venkataramanan * Delete TSE (indirect 0x040F) 8141f9c7840SAnirudh Venkataramanan * Move TSE (indirect 0x0408) 8151f9c7840SAnirudh Venkataramanan * Suspend Nodes (indirect 0x0409) 8161f9c7840SAnirudh Venkataramanan * Resume Nodes (indirect 0x040A) 8175513b920SAnirudh Venkataramanan */ 8181f9c7840SAnirudh Venkataramanan struct ice_aqc_sched_elem_cmd { 8195513b920SAnirudh Venkataramanan __le16 num_elem_req; /* Used by commands */ 8205513b920SAnirudh Venkataramanan __le16 num_elem_resp; /* Used by responses */ 8215513b920SAnirudh Venkataramanan __le32 reserved; 8225513b920SAnirudh Venkataramanan __le32 addr_high; 8235513b920SAnirudh Venkataramanan __le32 addr_low; 8245513b920SAnirudh Venkataramanan }; 8255513b920SAnirudh Venkataramanan 826b126bd6bSKiran Patil struct ice_aqc_txsched_move_grp_info_hdr { 827b126bd6bSKiran Patil __le32 src_parent_teid; 828b126bd6bSKiran Patil __le32 dest_parent_teid; 829b126bd6bSKiran Patil __le16 num_elems; 83023ccae5cSDave Ertman u8 mode; 83123ccae5cSDave Ertman #define ICE_AQC_MOVE_ELEM_MODE_SAME_PF 0x0 83223ccae5cSDave Ertman #define ICE_AQC_MOVE_ELEM_MODE_GIVE_OWN 0x1 83323ccae5cSDave Ertman #define ICE_AQC_MOVE_ELEM_MODE_KEEP_OWN 0x2 83423ccae5cSDave Ertman u8 reserved; 835b126bd6bSKiran Patil }; 836b126bd6bSKiran Patil 837b126bd6bSKiran Patil struct ice_aqc_move_elem { 838b126bd6bSKiran Patil struct ice_aqc_txsched_move_grp_info_hdr hdr; 839b126bd6bSKiran Patil __le32 teid[]; 840b126bd6bSKiran Patil }; 841b126bd6bSKiran Patil 8429c20346bSAnirudh Venkataramanan struct ice_aqc_elem_info_bw { 8439c20346bSAnirudh Venkataramanan __le16 bw_profile_idx; 8449c20346bSAnirudh Venkataramanan __le16 bw_alloc; 8459c20346bSAnirudh Venkataramanan }; 8469c20346bSAnirudh Venkataramanan 8479c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem { 8489c20346bSAnirudh Venkataramanan u8 elem_type; /* Special field, reserved for some aq calls */ 8499c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 8509c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 8519c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_TC 0x2 8529c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 8539c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 8549c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_LEAF 0x5 8559c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 8569c20346bSAnirudh Venkataramanan u8 valid_sections; 8579c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 8589c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_CIR BIT(1) 8599c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_EIR BIT(2) 8609c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 8619c20346bSAnirudh Venkataramanan u8 generic; 8629c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 8639c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 86416dfa494SMichal Wilczynski #define ICE_AQC_ELEM_GENERIC_PRIO_M GENMASK(3, 1) 8659c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 86616dfa494SMichal Wilczynski #define ICE_AQC_ELEM_GENERIC_SP_M GENMASK(4, 4) 8679c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 8689c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 8699c20346bSAnirudh Venkataramanan (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 8709c20346bSAnirudh Venkataramanan u8 flags; /* Special field, reserved for some aq calls */ 8719c20346bSAnirudh Venkataramanan #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 8729c20346bSAnirudh Venkataramanan struct ice_aqc_elem_info_bw cir_bw; 8739c20346bSAnirudh Venkataramanan struct ice_aqc_elem_info_bw eir_bw; 8749c20346bSAnirudh Venkataramanan __le16 srl_id; 8759c20346bSAnirudh Venkataramanan __le16 reserved2; 8769c20346bSAnirudh Venkataramanan }; 8779c20346bSAnirudh Venkataramanan 8789c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem_data { 8799c20346bSAnirudh Venkataramanan __le32 parent_teid; 8809c20346bSAnirudh Venkataramanan __le32 node_teid; 8819c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem data; 8829c20346bSAnirudh Venkataramanan }; 8839c20346bSAnirudh Venkataramanan 8849c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr { 8859c20346bSAnirudh Venkataramanan __le32 parent_teid; 8869c20346bSAnirudh Venkataramanan __le16 num_elems; 8879c20346bSAnirudh Venkataramanan __le16 reserved2; 8889c20346bSAnirudh Venkataramanan }; 8899c20346bSAnirudh Venkataramanan 8905513b920SAnirudh Venkataramanan struct ice_aqc_add_elem { 8915513b920SAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr hdr; 89266486d89SBruce Allan struct ice_aqc_txsched_elem_data generic[]; 8935513b920SAnirudh Venkataramanan }; 8945513b920SAnirudh Venkataramanan 895dc49c772SAnirudh Venkataramanan struct ice_aqc_get_topo_elem { 896dc49c772SAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr hdr; 897dc49c772SAnirudh Venkataramanan struct ice_aqc_txsched_elem_data 898dc49c772SAnirudh Venkataramanan generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 899dc49c772SAnirudh Venkataramanan }; 900dc49c772SAnirudh Venkataramanan 9019c20346bSAnirudh Venkataramanan struct ice_aqc_delete_elem { 9029c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_topo_grp_info_hdr hdr; 90366486d89SBruce Allan __le32 teid[]; 9049c20346bSAnirudh Venkataramanan }; 9059c20346bSAnirudh Venkataramanan 9067b9ffc76SAnirudh Venkataramanan /* Query Port ETS (indirect 0x040E) 9077b9ffc76SAnirudh Venkataramanan * 9087b9ffc76SAnirudh Venkataramanan * This indirect command is used to query port TC node configuration. 9097b9ffc76SAnirudh Venkataramanan */ 9107b9ffc76SAnirudh Venkataramanan struct ice_aqc_query_port_ets { 9117b9ffc76SAnirudh Venkataramanan __le32 port_teid; 9127b9ffc76SAnirudh Venkataramanan __le32 reserved; 9137b9ffc76SAnirudh Venkataramanan __le32 addr_high; 9147b9ffc76SAnirudh Venkataramanan __le32 addr_low; 9157b9ffc76SAnirudh Venkataramanan }; 9167b9ffc76SAnirudh Venkataramanan 9177b9ffc76SAnirudh Venkataramanan struct ice_aqc_port_ets_elem { 9187b9ffc76SAnirudh Venkataramanan u8 tc_valid_bits; 9197b9ffc76SAnirudh Venkataramanan u8 reserved[3]; 9207b9ffc76SAnirudh Venkataramanan /* 3 bits for UP per TC 0-7, 4th byte reserved */ 9217b9ffc76SAnirudh Venkataramanan __le32 up2tc; 9227b9ffc76SAnirudh Venkataramanan u8 tc_bw_share[8]; 9237b9ffc76SAnirudh Venkataramanan __le32 port_eir_prof_id; 9247b9ffc76SAnirudh Venkataramanan __le32 port_cir_prof_id; 9257b9ffc76SAnirudh Venkataramanan /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 9267b9ffc76SAnirudh Venkataramanan __le32 tc_node_prio; 9277b9ffc76SAnirudh Venkataramanan #define ICE_TC_NODE_PRIO_S 0x4 9287b9ffc76SAnirudh Venkataramanan u8 reserved1[4]; 9297b9ffc76SAnirudh Venkataramanan __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 9307b9ffc76SAnirudh Venkataramanan }; 9317b9ffc76SAnirudh Venkataramanan 9321ddef455SUsha Ketineni /* Rate limiting profile for 9331ddef455SUsha Ketineni * Add RL profile (indirect 0x0410) 9341ddef455SUsha Ketineni * Query RL profile (indirect 0x0411) 9351ddef455SUsha Ketineni * Remove RL profile (indirect 0x0415) 9361ddef455SUsha Ketineni * These indirect commands acts on single or multiple 9371ddef455SUsha Ketineni * RL profiles with specified data. 9381ddef455SUsha Ketineni */ 9391ddef455SUsha Ketineni struct ice_aqc_rl_profile { 9401ddef455SUsha Ketineni __le16 num_profiles; 9411ddef455SUsha Ketineni __le16 num_processed; /* Only for response. Reserved in Command. */ 9421ddef455SUsha Ketineni u8 reserved[4]; 9431ddef455SUsha Ketineni __le32 addr_high; 9441ddef455SUsha Ketineni __le32 addr_low; 9451ddef455SUsha Ketineni }; 9461ddef455SUsha Ketineni 9471ddef455SUsha Ketineni struct ice_aqc_rl_profile_elem { 9481ddef455SUsha Ketineni u8 level; 9491ddef455SUsha Ketineni u8 flags; 9501ddef455SUsha Ketineni #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 9511ddef455SUsha Ketineni #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 9521ddef455SUsha Ketineni #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 9531ddef455SUsha Ketineni #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 9541ddef455SUsha Ketineni #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 9551ddef455SUsha Ketineni /* The following flag is used for Query RL Profile Data */ 9561ddef455SUsha Ketineni #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 9571ddef455SUsha Ketineni #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 9581ddef455SUsha Ketineni 9591ddef455SUsha Ketineni __le16 profile_id; 9601ddef455SUsha Ketineni __le16 max_burst_size; 9611ddef455SUsha Ketineni __le16 rl_multiply; 9621ddef455SUsha Ketineni __le16 wake_up_calc; 9631ddef455SUsha Ketineni __le16 rl_encode; 9641ddef455SUsha Ketineni }; 9651ddef455SUsha Ketineni 9669c20346bSAnirudh Venkataramanan /* Query Scheduler Resource Allocation (indirect 0x0412) 9679c20346bSAnirudh Venkataramanan * This indirect command retrieves the scheduler resources allocated by 9689c20346bSAnirudh Venkataramanan * EMP Firmware to the given PF. 9699c20346bSAnirudh Venkataramanan */ 9709c20346bSAnirudh Venkataramanan struct ice_aqc_query_txsched_res { 9719c20346bSAnirudh Venkataramanan u8 reserved[8]; 9729c20346bSAnirudh Venkataramanan __le32 addr_high; 9739c20346bSAnirudh Venkataramanan __le32 addr_low; 9749c20346bSAnirudh Venkataramanan }; 9759c20346bSAnirudh Venkataramanan 9769c20346bSAnirudh Venkataramanan struct ice_aqc_generic_sched_props { 9779c20346bSAnirudh Venkataramanan __le16 phys_levels; 9789c20346bSAnirudh Venkataramanan __le16 logical_levels; 9799c20346bSAnirudh Venkataramanan u8 flattening_bitmap; 9809c20346bSAnirudh Venkataramanan u8 max_device_cgds; 9819c20346bSAnirudh Venkataramanan u8 max_pf_cgds; 9829c20346bSAnirudh Venkataramanan u8 rsvd0; 9839c20346bSAnirudh Venkataramanan __le16 rdma_qsets; 9849c20346bSAnirudh Venkataramanan u8 rsvd1[22]; 9859c20346bSAnirudh Venkataramanan }; 9869c20346bSAnirudh Venkataramanan 9879c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props { 9889c20346bSAnirudh Venkataramanan u8 logical_layer; 9899c20346bSAnirudh Venkataramanan u8 chunk_size; 9909c20346bSAnirudh Venkataramanan __le16 max_device_nodes; 9919c20346bSAnirudh Venkataramanan __le16 max_pf_nodes; 992b36c598cSAnirudh Venkataramanan u8 rsvd0[4]; 993b36c598cSAnirudh Venkataramanan __le16 max_sibl_grp_sz; 9949c20346bSAnirudh Venkataramanan __le16 max_cir_rl_profiles; 9959c20346bSAnirudh Venkataramanan __le16 max_eir_rl_profiles; 9969c20346bSAnirudh Venkataramanan __le16 max_srl_profiles; 9979c20346bSAnirudh Venkataramanan u8 rsvd1[14]; 9989c20346bSAnirudh Venkataramanan }; 9999c20346bSAnirudh Venkataramanan 10009c20346bSAnirudh Venkataramanan struct ice_aqc_query_txsched_res_resp { 10019c20346bSAnirudh Venkataramanan struct ice_aqc_generic_sched_props sched_props; 10029c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 10039c20346bSAnirudh Venkataramanan }; 10049c20346bSAnirudh Venkataramanan 1005dc49c772SAnirudh Venkataramanan /* Get PHY capabilities (indirect 0x0600) */ 1006dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps { 1007dc49c772SAnirudh Venkataramanan u8 lport_num; 1008dc49c772SAnirudh Venkataramanan u8 reserved; 1009dc49c772SAnirudh Venkataramanan __le16 param0; 1010dc49c772SAnirudh Venkataramanan /* 18.0 - Report qualified modules */ 1011dc49c772SAnirudh Venkataramanan #define ICE_AQC_GET_PHY_RQM BIT(0) 10120a02944fSAnirudh Venkataramanan /* 18.1 - 18.3 : Report mode 10130a02944fSAnirudh Venkataramanan * 000b - Report NVM capabilities 10140a02944fSAnirudh Venkataramanan * 001b - Report topology capabilities 10150a02944fSAnirudh Venkataramanan * 010b - Report SW configured 10160a02944fSAnirudh Venkataramanan * 100b - Report default capabilities 1017dc49c772SAnirudh Venkataramanan */ 1018dc49c772SAnirudh Venkataramanan #define ICE_AQC_REPORT_MODE_S 1 10190a02944fSAnirudh Venkataramanan #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1020d6730a87SAnirudh Venkataramanan #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1021d6730a87SAnirudh Venkataramanan #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1022d6730a87SAnirudh Venkataramanan #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 10230a02944fSAnirudh Venkataramanan #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1024dc49c772SAnirudh Venkataramanan __le32 reserved1; 1025dc49c772SAnirudh Venkataramanan __le32 addr_high; 1026dc49c772SAnirudh Venkataramanan __le32 addr_low; 1027dc49c772SAnirudh Venkataramanan }; 1028dc49c772SAnirudh Venkataramanan 1029dc49c772SAnirudh Venkataramanan /* This is #define of PHY type (Extended): 1030dc49c772SAnirudh Venkataramanan * The first set of defines is for phy_type_low. 1031dc49c772SAnirudh Venkataramanan */ 1032dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1033dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1034dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1035dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1036dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1037dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1038dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1039dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1040dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1041dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1042dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1043dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1044dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1045dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1046dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1047dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1048dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1049dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1050dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1051dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1052dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1053dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1054dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1055dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1056dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1057dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1058dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1059dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1060dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1061dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1062dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1063dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1064dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1065dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1066dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1067dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1068aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1069aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1070aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1071aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1072aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1073aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1074aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1075aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1076aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1077aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1078aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1079aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1080aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1081aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1082aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1083aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1084aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1085aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1086aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1087aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1088aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1089aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1090aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1091aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1092aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1093aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1094aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1095aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1096dc49c772SAnirudh Venkataramanan #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1097aef74145SAnirudh Venkataramanan /* The second set of defines is for phy_type_high. */ 1098aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1099aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1100aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1101aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1102aef74145SAnirudh Venkataramanan #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1103578fb092SPaul Greenwalt #define ICE_PHY_TYPE_HIGH_MAX_INDEX 4 1104dc49c772SAnirudh Venkataramanan 1105dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps_data { 1106dc49c772SAnirudh Venkataramanan __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1107b6f934f0SBrett Creeley __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1108dc49c772SAnirudh Venkataramanan u8 caps; 1109dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1110dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1111dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1112dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_LINK BIT(3) 1113dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_AN_MODE BIT(4) 1114dc49c772SAnirudh Venkataramanan #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) 1115f776b3acSPaul Greenwalt #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1116f776b3acSPaul Greenwalt #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0) 1117bdeff971SLev Faerman u8 low_power_ctrl_an; 1118dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 11195ee30564SPaul Greenwalt #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 11205ee30564SPaul Greenwalt #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 11215ee30564SPaul Greenwalt #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1122dc49c772SAnirudh Venkataramanan __le16 eee_cap; 1123dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1124dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1125dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1126dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1127dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1128dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1129dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1130dc49c772SAnirudh Venkataramanan __le16 eeer_value; 1131dc49c772SAnirudh Venkataramanan u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 113262f4dafcSAnirudh Venkataramanan u8 phy_fw_ver[8]; 1133dc49c772SAnirudh Venkataramanan u8 link_fec_options; 1134dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1135dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1136dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1137dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1138dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1139dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1140dc49c772SAnirudh Venkataramanan #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1141f776b3acSPaul Greenwalt #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0) 1142ea78ce4dSPaul Greenwalt u8 module_compliance_enforcement; 1143ea78ce4dSPaul Greenwalt #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1144dc49c772SAnirudh Venkataramanan u8 extended_compliance_code; 1145dc49c772SAnirudh Venkataramanan #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1146dc49c772SAnirudh Venkataramanan u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1147dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1148dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1149c2b35226SPaul M Stillwell Jr #define ICE_AQC_MOD_TYPE_IDENT 1 1150dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1151dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1152dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1153dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1154dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1155dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1156dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1157dc49c772SAnirudh Venkataramanan #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1158dc49c772SAnirudh Venkataramanan u8 qualified_module_count; 115962f4dafcSAnirudh Venkataramanan u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1160dc49c772SAnirudh Venkataramanan #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1161dc49c772SAnirudh Venkataramanan struct { 1162dc49c772SAnirudh Venkataramanan u8 v_oui[3]; 116362f4dafcSAnirudh Venkataramanan u8 rsvd3; 1164dc49c772SAnirudh Venkataramanan u8 v_part[16]; 1165dc49c772SAnirudh Venkataramanan __le32 v_rev; 116662f4dafcSAnirudh Venkataramanan __le64 rsvd4; 1167dc49c772SAnirudh Venkataramanan } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1168dc49c772SAnirudh Venkataramanan }; 1169dc49c772SAnirudh Venkataramanan 1170fcea6f3dSAnirudh Venkataramanan /* Set PHY capabilities (direct 0x0601) 1171fcea6f3dSAnirudh Venkataramanan * NOTE: This command must be followed by setup link and restart auto-neg 1172fcea6f3dSAnirudh Venkataramanan */ 1173fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg { 1174fcea6f3dSAnirudh Venkataramanan u8 lport_num; 1175fcea6f3dSAnirudh Venkataramanan u8 reserved[7]; 1176fcea6f3dSAnirudh Venkataramanan __le32 addr_high; 1177fcea6f3dSAnirudh Venkataramanan __le32 addr_low; 1178fcea6f3dSAnirudh Venkataramanan }; 1179fcea6f3dSAnirudh Venkataramanan 1180fcea6f3dSAnirudh Venkataramanan /* Set PHY config command data structure */ 1181fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg_data { 1182fcea6f3dSAnirudh Venkataramanan __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1183b6f934f0SBrett Creeley __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1184fcea6f3dSAnirudh Venkataramanan u8 caps; 1185d8df260aSChinh T Cao #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0) 1186fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1187fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1188fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1189fcea6f3dSAnirudh Venkataramanan #define ICE_AQ_PHY_ENA_LINK BIT(3) 119048cb27f2SChinh Cao #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 119148cb27f2SChinh Cao #define ICE_AQ_PHY_ENA_LESM BIT(6) 119248cb27f2SChinh Cao #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1193bdeff971SLev Faerman u8 low_power_ctrl_an; 1194fcea6f3dSAnirudh Venkataramanan __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1195fcea6f3dSAnirudh Venkataramanan __le16 eeer_value; 1196fcea6f3dSAnirudh Venkataramanan u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1197ea78ce4dSPaul Greenwalt u8 module_compliance_enforcement; 1198fcea6f3dSAnirudh Venkataramanan }; 1199fcea6f3dSAnirudh Venkataramanan 120042449105SAnirudh Venkataramanan /* Set MAC Config command data structure (direct 0x0603) */ 120142449105SAnirudh Venkataramanan struct ice_aqc_set_mac_cfg { 120242449105SAnirudh Venkataramanan __le16 max_frame_size; 120342449105SAnirudh Venkataramanan u8 params; 120442449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_PACE_S 3 120542449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 120642449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 120742449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 120842449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 120942449105SAnirudh Venkataramanan u8 tx_tmr_priority; 121042449105SAnirudh Venkataramanan __le16 tx_tmr_value; 121142449105SAnirudh Venkataramanan __le16 fc_refresh_threshold; 121242449105SAnirudh Venkataramanan u8 drop_opts; 121342449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 121442449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 121542449105SAnirudh Venkataramanan #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 121642449105SAnirudh Venkataramanan u8 reserved[7]; 121742449105SAnirudh Venkataramanan }; 121842449105SAnirudh Venkataramanan 1219fcea6f3dSAnirudh Venkataramanan /* Restart AN command data structure (direct 0x0605) 1220fcea6f3dSAnirudh Venkataramanan * Also used for response, with only the lport_num field present. 1221fcea6f3dSAnirudh Venkataramanan */ 1222fcea6f3dSAnirudh Venkataramanan struct ice_aqc_restart_an { 1223fcea6f3dSAnirudh Venkataramanan u8 lport_num; 1224fcea6f3dSAnirudh Venkataramanan u8 reserved; 1225fcea6f3dSAnirudh Venkataramanan u8 cmd_flags; 1226fcea6f3dSAnirudh Venkataramanan #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1227fcea6f3dSAnirudh Venkataramanan #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1228fcea6f3dSAnirudh Venkataramanan u8 reserved2[13]; 1229fcea6f3dSAnirudh Venkataramanan }; 1230fcea6f3dSAnirudh Venkataramanan 1231dc49c772SAnirudh Venkataramanan /* Get link status (indirect 0x0607), also used for Link Status Event */ 1232dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status { 1233dc49c772SAnirudh Venkataramanan u8 lport_num; 1234dc49c772SAnirudh Venkataramanan u8 reserved; 1235dc49c772SAnirudh Venkataramanan __le16 cmd_flags; 1236dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_M 0x3 1237dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_NOP 0x0 1238dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_DIS 0x2 1239dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_ENA 0x3 1240dc49c772SAnirudh Venkataramanan /* only response uses this flag */ 1241dc49c772SAnirudh Venkataramanan #define ICE_AQ_LSE_IS_ENABLED 0x1 1242dc49c772SAnirudh Venkataramanan __le32 reserved2; 1243dc49c772SAnirudh Venkataramanan __le32 addr_high; 1244dc49c772SAnirudh Venkataramanan __le32 addr_low; 1245dc49c772SAnirudh Venkataramanan }; 1246dc49c772SAnirudh Venkataramanan 1247dc49c772SAnirudh Venkataramanan /* Get link status response data structure, also used for Link Status Event */ 1248dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status_data { 1249dc49c772SAnirudh Venkataramanan u8 topo_media_conflict; 1250dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1251dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1252dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 12535878589dSPaul Greenwalt #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 12545878589dSPaul Greenwalt #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 12555878589dSPaul Greenwalt #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 12565878589dSPaul Greenwalt #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1257c77849f5SAnirudh Venkataramanan u8 link_cfg_err; 1258c77849f5SAnirudh Venkataramanan #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 125999d40752SBrett Creeley #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1260c77849f5SAnirudh Venkataramanan #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1261dc49c772SAnirudh Venkataramanan u8 link_info; 1262dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1263dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT BIT(1) 1264dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT_TX BIT(2) 1265dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT_RX BIT(3) 1266dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1267dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1268dc49c772SAnirudh Venkataramanan #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1269dc49c772SAnirudh Venkataramanan #define ICE_AQ_SIGNAL_DETECT BIT(7) 1270dc49c772SAnirudh Venkataramanan u8 an_info; 1271dc49c772SAnirudh Venkataramanan #define ICE_AQ_AN_COMPLETED BIT(0) 1272dc49c772SAnirudh Venkataramanan #define ICE_AQ_LP_AN_ABILITY BIT(1) 1273dc49c772SAnirudh Venkataramanan #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1274dc49c772SAnirudh Venkataramanan #define ICE_AQ_FEC_EN BIT(3) 1275dc49c772SAnirudh Venkataramanan #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1276dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1277dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1278dc49c772SAnirudh Venkataramanan #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1279dc49c772SAnirudh Venkataramanan u8 ext_info; 1280dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1281dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1282f9867df6SAnirudh Venkataramanan /* Port Tx Suspended */ 1283dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_S 2 1284dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1285dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_ACTIVE 0 1286dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_DRAINED 1 1287dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_TX_FLUSHED 3 1288dc49c772SAnirudh Venkataramanan u8 reserved2; 1289dc49c772SAnirudh Venkataramanan __le16 max_frame_size; 1290dc49c772SAnirudh Venkataramanan u8 cfg; 1291dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1292dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1293dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1294f776b3acSPaul Greenwalt #define ICE_AQ_FEC_MASK ICE_M(0x7, 0) 1295dc49c772SAnirudh Venkataramanan /* Pacing Config */ 1296dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_S 3 1297dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1298dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1299dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1300dc49c772SAnirudh Venkataramanan #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1301dc49c772SAnirudh Venkataramanan /* External Device Power Ability */ 1302dc49c772SAnirudh Venkataramanan u8 power_desc; 1303c77849f5SAnirudh Venkataramanan #define ICE_AQ_PWR_CLASS_M 0x3F 1304dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1305dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1306dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1307dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1308dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1309dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1310dc49c772SAnirudh Venkataramanan __le16 link_speed; 13111a3571b5SPaul Greenwalt #define ICE_AQ_LINK_SPEED_M 0x7FF 1312dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1313dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1314dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1315dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1316dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1317dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1318dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1319dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1320dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1321aef74145SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1322aef74145SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1323dc49c772SAnirudh Venkataramanan #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1324dc49c772SAnirudh Venkataramanan __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1325dc49c772SAnirudh Venkataramanan __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1326aef74145SAnirudh Venkataramanan __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1327dc49c772SAnirudh Venkataramanan }; 1328dc49c772SAnirudh Venkataramanan 13290b28b702SAnirudh Venkataramanan /* Set event mask command (direct 0x0613) */ 13300b28b702SAnirudh Venkataramanan struct ice_aqc_set_event_mask { 13310b28b702SAnirudh Venkataramanan u8 lport_num; 13320b28b702SAnirudh Venkataramanan u8 reserved[7]; 13330b28b702SAnirudh Venkataramanan __le16 event_mask; 13340b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 13350b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 13360b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 13370b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 13380b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 13390b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 13400b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 13410b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 13420b28b702SAnirudh Venkataramanan #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 134399d40752SBrett Creeley #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 13440b28b702SAnirudh Venkataramanan u8 reserved1[6]; 13450b28b702SAnirudh Venkataramanan }; 13460b28b702SAnirudh Venkataramanan 13470e674aebSAnirudh Venkataramanan /* Set MAC Loopback command (direct 0x0620) */ 13480e674aebSAnirudh Venkataramanan struct ice_aqc_set_mac_lb { 13490e674aebSAnirudh Venkataramanan u8 lb_mode; 13500e674aebSAnirudh Venkataramanan #define ICE_AQ_MAC_LB_EN BIT(0) 13510e674aebSAnirudh Venkataramanan #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 13520e674aebSAnirudh Venkataramanan u8 reserved[15]; 13530e674aebSAnirudh Venkataramanan }; 13540e674aebSAnirudh Venkataramanan 1355e00ae1a2SMaciej Machnikowski struct ice_aqc_link_topo_params { 13568ea1da59SPaul Greenwalt u8 lport_num; 13578ea1da59SPaul Greenwalt u8 lport_num_valid; 13588ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 13598ea1da59SPaul Greenwalt u8 node_type_ctx; 13608ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 13618ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 13628ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 13638ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 13648ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 13658ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 13668ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 13678ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 13688ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 13698ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 13708ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 13718ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 13728ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 13738ea1da59SPaul Greenwalt (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 13748ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 13758ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 13768ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 13778ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 13788ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 13798ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 13808ea1da59SPaul Greenwalt u8 index; 1381e00ae1a2SMaciej Machnikowski }; 1382e00ae1a2SMaciej Machnikowski 1383e00ae1a2SMaciej Machnikowski struct ice_aqc_link_topo_addr { 1384e00ae1a2SMaciej Machnikowski struct ice_aqc_link_topo_params topo_params; 13858ea1da59SPaul Greenwalt __le16 handle; 13868ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_HANDLE_S 0 13878ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 13888ea1da59SPaul Greenwalt /* Used to decode the handle field */ 13898ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 13908ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 13918ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 13928ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 13938ea1da59SPaul Greenwalt /* In case of a Mezzanine type */ 13948ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 13958ea1da59SPaul Greenwalt (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 13968ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 13978ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 13988ea1da59SPaul Greenwalt /* In case of a LOM type */ 13998ea1da59SPaul Greenwalt #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 14008ea1da59SPaul Greenwalt (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 14018ea1da59SPaul Greenwalt }; 14028ea1da59SPaul Greenwalt 14038ea1da59SPaul Greenwalt /* Get Link Topology Handle (direct, 0x06E0) */ 14048ea1da59SPaul Greenwalt struct ice_aqc_get_link_topo { 14058ea1da59SPaul Greenwalt struct ice_aqc_link_topo_addr addr; 14068ea1da59SPaul Greenwalt u8 node_part_num; 1407885fe693SMaciej Machnikowski #define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1408272ad794SKarol Kolacinski #define ICE_AQC_GET_LINK_TOPO_NODE_NR_C827 0x31 14098ea1da59SPaul Greenwalt u8 rsvd[9]; 14108ea1da59SPaul Greenwalt }; 14118ea1da59SPaul Greenwalt 1412fcf9b695SKarol Kolacinski /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 141343113ff7SKarol Kolacinski struct ice_aqc_i2c { 141443113ff7SKarol Kolacinski struct ice_aqc_link_topo_addr topo_addr; 141543113ff7SKarol Kolacinski __le16 i2c_addr; 141643113ff7SKarol Kolacinski u8 i2c_params; 141743113ff7SKarol Kolacinski #define ICE_AQC_I2C_DATA_SIZE_M GENMASK(3, 0) 141843113ff7SKarol Kolacinski #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 141943113ff7SKarol Kolacinski 142043113ff7SKarol Kolacinski u8 rsvd; 142143113ff7SKarol Kolacinski __le16 i2c_bus_addr; 1422fcf9b695SKarol Kolacinski u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 142343113ff7SKarol Kolacinski }; 142443113ff7SKarol Kolacinski 142543113ff7SKarol Kolacinski /* Read I2C Response (direct, 0x06E2) */ 142643113ff7SKarol Kolacinski struct ice_aqc_read_i2c_resp { 142743113ff7SKarol Kolacinski u8 i2c_data[16]; 142843113ff7SKarol Kolacinski }; 142943113ff7SKarol Kolacinski 14308e151d50SAnirudh Venkataramanan /* Set Port Identification LED (direct, 0x06E9) */ 14318e151d50SAnirudh Venkataramanan struct ice_aqc_set_port_id_led { 14328e151d50SAnirudh Venkataramanan u8 lport_num; 14338e151d50SAnirudh Venkataramanan u8 lport_num_valid; 14348e151d50SAnirudh Venkataramanan u8 ident_mode; 14358e151d50SAnirudh Venkataramanan #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 14368e151d50SAnirudh Venkataramanan #define ICE_AQC_PORT_IDENT_LED_ORIG 0 14378e151d50SAnirudh Venkataramanan u8 rsvd[13]; 14388e151d50SAnirudh Venkataramanan }; 14398e151d50SAnirudh Venkataramanan 1440781f15eaSAnatolii Gerasymenko /* Get Port Options (indirect, 0x06EA) */ 1441781f15eaSAnatolii Gerasymenko struct ice_aqc_get_port_options { 1442781f15eaSAnatolii Gerasymenko u8 lport_num; 1443781f15eaSAnatolii Gerasymenko u8 lport_num_valid; 1444781f15eaSAnatolii Gerasymenko u8 port_options_count; 1445781f15eaSAnatolii Gerasymenko #define ICE_AQC_PORT_OPT_COUNT_M GENMASK(3, 0) 1446781f15eaSAnatolii Gerasymenko #define ICE_AQC_PORT_OPT_MAX 16 1447781f15eaSAnatolii Gerasymenko 1448781f15eaSAnatolii Gerasymenko u8 innermost_phy_index; 1449781f15eaSAnatolii Gerasymenko u8 port_options; 1450781f15eaSAnatolii Gerasymenko #define ICE_AQC_PORT_OPT_ACTIVE_M GENMASK(3, 0) 1451781f15eaSAnatolii Gerasymenko #define ICE_AQC_PORT_OPT_VALID BIT(7) 1452781f15eaSAnatolii Gerasymenko 1453781f15eaSAnatolii Gerasymenko u8 pending_port_option_status; 1454781f15eaSAnatolii Gerasymenko #define ICE_AQC_PENDING_PORT_OPT_IDX_M GENMASK(3, 0) 1455781f15eaSAnatolii Gerasymenko #define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7) 1456781f15eaSAnatolii Gerasymenko 1457781f15eaSAnatolii Gerasymenko u8 rsvd[2]; 1458781f15eaSAnatolii Gerasymenko __le32 addr_high; 1459781f15eaSAnatolii Gerasymenko __le32 addr_low; 1460781f15eaSAnatolii Gerasymenko }; 1461781f15eaSAnatolii Gerasymenko 1462781f15eaSAnatolii Gerasymenko struct ice_aqc_get_port_options_elem { 1463781f15eaSAnatolii Gerasymenko u8 pmd; 1464781f15eaSAnatolii Gerasymenko #define ICE_AQC_PORT_OPT_PMD_COUNT_M GENMASK(3, 0) 1465781f15eaSAnatolii Gerasymenko 1466781f15eaSAnatolii Gerasymenko u8 max_lane_speed; 1467781f15eaSAnatolii Gerasymenko #define ICE_AQC_PORT_OPT_MAX_LANE_M GENMASK(3, 0) 1468781f15eaSAnatolii Gerasymenko #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 1469781f15eaSAnatolii Gerasymenko #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 1470781f15eaSAnatolii Gerasymenko #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 1471781f15eaSAnatolii Gerasymenko #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 1472781f15eaSAnatolii Gerasymenko #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 1473781f15eaSAnatolii Gerasymenko #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 1474781f15eaSAnatolii Gerasymenko #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 1475781f15eaSAnatolii Gerasymenko #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 1476781f15eaSAnatolii Gerasymenko 1477781f15eaSAnatolii Gerasymenko u8 global_scid[2]; 1478781f15eaSAnatolii Gerasymenko u8 phy_scid[2]; 1479781f15eaSAnatolii Gerasymenko u8 pf2port_cid[2]; 1480781f15eaSAnatolii Gerasymenko }; 1481781f15eaSAnatolii Gerasymenko 1482781f15eaSAnatolii Gerasymenko /* Set Port Option (direct, 0x06EB) */ 1483781f15eaSAnatolii Gerasymenko struct ice_aqc_set_port_option { 1484781f15eaSAnatolii Gerasymenko u8 lport_num; 1485781f15eaSAnatolii Gerasymenko u8 lport_num_valid; 1486781f15eaSAnatolii Gerasymenko u8 selected_port_option; 1487781f15eaSAnatolii Gerasymenko u8 rsvd[13]; 1488781f15eaSAnatolii Gerasymenko }; 1489781f15eaSAnatolii Gerasymenko 14903bb6324bSMaciej Machnikowski /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 14913bb6324bSMaciej Machnikowski struct ice_aqc_gpio { 14923bb6324bSMaciej Machnikowski __le16 gpio_ctrl_handle; 14933bb6324bSMaciej Machnikowski #define ICE_AQC_GPIO_HANDLE_S 0 14943bb6324bSMaciej Machnikowski #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 14953bb6324bSMaciej Machnikowski u8 gpio_num; 14963bb6324bSMaciej Machnikowski u8 gpio_val; 14973bb6324bSMaciej Machnikowski u8 rsvd[12]; 14983bb6324bSMaciej Machnikowski }; 14993bb6324bSMaciej Machnikowski 1500a012dca9SScott W Taylor /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1501a012dca9SScott W Taylor struct ice_aqc_sff_eeprom { 1502a012dca9SScott W Taylor u8 lport_num; 1503a012dca9SScott W Taylor u8 lport_num_valid; 1504a012dca9SScott W Taylor #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1505a012dca9SScott W Taylor __le16 i2c_bus_addr; 1506a012dca9SScott W Taylor #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1507a012dca9SScott W Taylor #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1508a012dca9SScott W Taylor #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1509a012dca9SScott W Taylor #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1510a012dca9SScott W Taylor #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1511a012dca9SScott W Taylor #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1512a012dca9SScott W Taylor #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1513a012dca9SScott W Taylor #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1514a012dca9SScott W Taylor #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1515a012dca9SScott W Taylor #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1516a012dca9SScott W Taylor #define ICE_AQC_SFF_IS_WRITE BIT(15) 1517a012dca9SScott W Taylor __le16 i2c_mem_addr; 1518a012dca9SScott W Taylor __le16 eeprom_page; 1519a012dca9SScott W Taylor #define ICE_AQC_SFF_EEPROM_BANK_S 0 1520a012dca9SScott W Taylor #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1521a012dca9SScott W Taylor #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1522a012dca9SScott W Taylor #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 1523a012dca9SScott W Taylor __le32 addr_high; 1524a012dca9SScott W Taylor __le32 addr_low; 1525a012dca9SScott W Taylor }; 1526a012dca9SScott W Taylor 1527f31e4b6fSAnirudh Venkataramanan /* NVM Read command (indirect 0x0701) 1528f31e4b6fSAnirudh Venkataramanan * NVM Erase commands (direct 0x0702) 1529f31e4b6fSAnirudh Venkataramanan * NVM Update commands (indirect 0x0703) 1530f31e4b6fSAnirudh Venkataramanan */ 1531f31e4b6fSAnirudh Venkataramanan struct ice_aqc_nvm { 153281f07491SJacob Keller #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 153343c89b16SAnirudh Venkataramanan __le16 offset_low; 153443c89b16SAnirudh Venkataramanan u8 offset_high; 1535f31e4b6fSAnirudh Venkataramanan u8 cmd_flags; 1536f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_LAST_CMD BIT(0) 1537f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ 1538f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_PRESERVATION_S 1 15396263e811SLev Faerman #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 15406263e811SLev Faerman #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 1541f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 1542544cd2acSCudzilo, Szymon T #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 15436263e811SLev Faerman #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 1544544cd2acSCudzilo, Szymon T #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 1545544cd2acSCudzilo, Szymon T #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 1546544cd2acSCudzilo, Szymon T #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 1547544cd2acSCudzilo, Szymon T #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 1548544cd2acSCudzilo, Szymon T #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 1549544cd2acSCudzilo, Szymon T #define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3) 1550f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 1551399e27dbSJacob Keller #define ICE_AQC_NVM_RESET_LVL_M ICE_M(0x3, 0) /* Write reply only */ 1552399e27dbSJacob Keller #define ICE_AQC_NVM_POR_FLAG 0 1553399e27dbSJacob Keller #define ICE_AQC_NVM_PERST_FLAG 1 1554399e27dbSJacob Keller #define ICE_AQC_NVM_EMPR_FLAG 2 1555399e27dbSJacob Keller #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 1556da02ee9cSJacob Keller /* For Write Activate, several flags are sent as part of a separate 1557da02ee9cSJacob Keller * flags2 field using a separate byte. For simplicity of the software 1558da02ee9cSJacob Keller * interface, we pass the flags as a 16 bit value so these flags are 1559da02ee9cSJacob Keller * all offset by 8 bits 1560da02ee9cSJacob Keller */ 1561da02ee9cSJacob Keller #define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */ 156243c89b16SAnirudh Venkataramanan __le16 module_typeid; 1563f31e4b6fSAnirudh Venkataramanan __le16 length; 1564f31e4b6fSAnirudh Venkataramanan #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 1565f31e4b6fSAnirudh Venkataramanan __le32 addr_high; 1566f31e4b6fSAnirudh Venkataramanan __le32 addr_low; 1567f31e4b6fSAnirudh Venkataramanan }; 1568f31e4b6fSAnirudh Venkataramanan 1569e9450990SJacob Keller #define ICE_AQC_NVM_START_POINT 0 1570e9450990SJacob Keller 15710e674aebSAnirudh Venkataramanan /* NVM Checksum Command (direct, 0x0706) */ 15720e674aebSAnirudh Venkataramanan struct ice_aqc_nvm_checksum { 15730e674aebSAnirudh Venkataramanan u8 flags; 15740e674aebSAnirudh Venkataramanan #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 15750e674aebSAnirudh Venkataramanan #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 15760e674aebSAnirudh Venkataramanan u8 rsvd; 15770e674aebSAnirudh Venkataramanan __le16 checksum; /* Used only by response */ 15780e674aebSAnirudh Venkataramanan #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 15790e674aebSAnirudh Venkataramanan u8 rsvd2[12]; 15800e674aebSAnirudh Venkataramanan }; 15810e674aebSAnirudh Venkataramanan 1582544cd2acSCudzilo, Szymon T /* Used for NVM Set Package Data command - 0x070A */ 1583544cd2acSCudzilo, Szymon T struct ice_aqc_nvm_pkg_data { 1584544cd2acSCudzilo, Szymon T u8 reserved[3]; 1585544cd2acSCudzilo, Szymon T u8 cmd_flags; 1586544cd2acSCudzilo, Szymon T #define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */ 1587544cd2acSCudzilo, Szymon T #define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */ 1588544cd2acSCudzilo, Szymon T 1589544cd2acSCudzilo, Szymon T u32 reserved1; 1590544cd2acSCudzilo, Szymon T __le32 addr_high; 1591544cd2acSCudzilo, Szymon T __le32 addr_low; 1592544cd2acSCudzilo, Szymon T }; 1593544cd2acSCudzilo, Szymon T 1594544cd2acSCudzilo, Szymon T /* Used for Pass Component Table command - 0x070B */ 1595544cd2acSCudzilo, Szymon T struct ice_aqc_nvm_pass_comp_tbl { 1596544cd2acSCudzilo, Szymon T u8 component_response; /* Response only */ 1597544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0 1598544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1 1599544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2 1600544cd2acSCudzilo, Szymon T u8 component_response_code; /* Response only */ 1601544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0 1602544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1 1603544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2 1604544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3 1605544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4 1606544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5 1607544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6 1608544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7 1609544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8 1610544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA 1611544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB 1612544cd2acSCudzilo, Szymon T u8 reserved; 1613544cd2acSCudzilo, Szymon T u8 transfer_flag; 1614544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1 1615544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2 1616544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4 1617544cd2acSCudzilo, Szymon T #define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5 1618544cd2acSCudzilo, Szymon T __le32 reserved1; 1619544cd2acSCudzilo, Szymon T __le32 addr_high; 1620544cd2acSCudzilo, Szymon T __le32 addr_low; 1621544cd2acSCudzilo, Szymon T }; 1622544cd2acSCudzilo, Szymon T 1623544cd2acSCudzilo, Szymon T struct ice_aqc_nvm_comp_tbl { 1624544cd2acSCudzilo, Szymon T __le16 comp_class; 1625544cd2acSCudzilo, Szymon T #define NVM_COMP_CLASS_ALL_FW 0x000A 1626544cd2acSCudzilo, Szymon T 1627544cd2acSCudzilo, Szymon T __le16 comp_id; 1628544cd2acSCudzilo, Szymon T #define NVM_COMP_ID_OROM 0x5 1629544cd2acSCudzilo, Szymon T #define NVM_COMP_ID_NVM 0x6 1630544cd2acSCudzilo, Szymon T #define NVM_COMP_ID_NETLIST 0x8 1631544cd2acSCudzilo, Szymon T 1632544cd2acSCudzilo, Szymon T u8 comp_class_idx; 1633544cd2acSCudzilo, Szymon T #define FWU_COMP_CLASS_IDX_NOT_USE 0x0 1634544cd2acSCudzilo, Szymon T 1635544cd2acSCudzilo, Szymon T __le32 comp_cmp_stamp; 1636544cd2acSCudzilo, Szymon T u8 cvs_type; 1637544cd2acSCudzilo, Szymon T #define NVM_CVS_TYPE_ASCII 0x1 1638544cd2acSCudzilo, Szymon T 1639544cd2acSCudzilo, Szymon T u8 cvs_len; 1640544cd2acSCudzilo, Szymon T u8 cvs[]; /* Component Version String */ 1641544cd2acSCudzilo, Szymon T } __packed; 1642544cd2acSCudzilo, Szymon T 1643a07cc178STony Nguyen /* Send to PF command (indirect 0x0801) ID is only used by PF 1644007676b4SAnirudh Venkataramanan * 1645f9867df6SAnirudh Venkataramanan * Send to VF command (indirect 0x0802) ID is only used by PF 1646007676b4SAnirudh Venkataramanan * 1647007676b4SAnirudh Venkataramanan */ 1648007676b4SAnirudh Venkataramanan struct ice_aqc_pf_vf_msg { 1649007676b4SAnirudh Venkataramanan __le32 id; 1650007676b4SAnirudh Venkataramanan u32 reserved; 1651007676b4SAnirudh Venkataramanan __le32 addr_high; 1652007676b4SAnirudh Venkataramanan __le32 addr_low; 1653007676b4SAnirudh Venkataramanan }; 1654007676b4SAnirudh Venkataramanan 16550ebd3ff1SAnirudh Venkataramanan /* Get LLDP MIB (indirect 0x0A00) 16560ebd3ff1SAnirudh Venkataramanan * Note: This is also used by the LLDP MIB Change Event (0x0A01) 16570ebd3ff1SAnirudh Venkataramanan * as the format is the same. 16580ebd3ff1SAnirudh Venkataramanan */ 16590ebd3ff1SAnirudh Venkataramanan struct ice_aqc_lldp_get_mib { 16600ebd3ff1SAnirudh Venkataramanan u8 type; 16610ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_TYPE_S 0 16620ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 16630ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_LOCAL 0 16640ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_REMOTE 1 16650ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 16660ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_BRID_TYPE_S 2 16670ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 16680ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 16690ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 16700ebd3ff1SAnirudh Venkataramanan /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 16710ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_S 0x4 16720ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 16730ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_ACTIVE 0 16740ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_SUSPENDED 1 16750ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_TX_FLUSHED 3 1676a4f68f37STsotne Chakhvadze /* DCBX mode */ 1677a4f68f37STsotne Chakhvadze #define ICE_AQ_LLDP_DCBX_M GENMASK(7, 6) 1678a4f68f37STsotne Chakhvadze #define ICE_AQ_LLDP_DCBX_NA 0 1679a4f68f37STsotne Chakhvadze #define ICE_AQ_LLDP_DCBX_CEE 1 1680a4f68f37STsotne Chakhvadze #define ICE_AQ_LLDP_DCBX_IEEE 2 1681a4f68f37STsotne Chakhvadze 1682a4f68f37STsotne Chakhvadze u8 state; 1683a4f68f37STsotne Chakhvadze #define ICE_AQ_LLDP_MIB_CHANGE_STATE_M BIT(0) 1684a4f68f37STsotne Chakhvadze #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0 1685a4f68f37STsotne Chakhvadze #define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1 1686a4f68f37STsotne Chakhvadze 16870ebd3ff1SAnirudh Venkataramanan /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 16880ebd3ff1SAnirudh Venkataramanan * and in the LLDP MIB Change Event (0x0A01). They are valid for the 16890ebd3ff1SAnirudh Venkataramanan * Get LLDP MIB (0x0A00) response only. 16900ebd3ff1SAnirudh Venkataramanan */ 16910ebd3ff1SAnirudh Venkataramanan __le16 local_len; 16920ebd3ff1SAnirudh Venkataramanan __le16 remote_len; 1693a4f68f37STsotne Chakhvadze u8 reserved[2]; 16940ebd3ff1SAnirudh Venkataramanan __le32 addr_high; 16950ebd3ff1SAnirudh Venkataramanan __le32 addr_low; 16960ebd3ff1SAnirudh Venkataramanan }; 16970ebd3ff1SAnirudh Venkataramanan 16980ebd3ff1SAnirudh Venkataramanan /* Configure LLDP MIB Change Event (direct 0x0A01) */ 16990ebd3ff1SAnirudh Venkataramanan /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 17000ebd3ff1SAnirudh Venkataramanan struct ice_aqc_lldp_set_mib_change { 17010ebd3ff1SAnirudh Venkataramanan u8 command; 17020ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 17030ebd3ff1SAnirudh Venkataramanan #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 1704a4f68f37STsotne Chakhvadze #define ICE_AQ_LLDP_MIB_PENDING_M BIT(1) 1705a4f68f37STsotne Chakhvadze #define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0 1706a4f68f37STsotne Chakhvadze #define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1 17070ebd3ff1SAnirudh Venkataramanan u8 reserved[15]; 17080ebd3ff1SAnirudh Venkataramanan }; 17090ebd3ff1SAnirudh Venkataramanan 17103a257a14SAnirudh Venkataramanan /* Stop LLDP (direct 0x0A05) */ 17113a257a14SAnirudh Venkataramanan struct ice_aqc_lldp_stop { 17123a257a14SAnirudh Venkataramanan u8 command; 17133a257a14SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 17143a257a14SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_STOP 0x0 17153a257a14SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 17163a257a14SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 17173a257a14SAnirudh Venkataramanan u8 reserved[15]; 17183a257a14SAnirudh Venkataramanan }; 17193a257a14SAnirudh Venkataramanan 172037b6f646SAnirudh Venkataramanan /* Start LLDP (direct 0x0A06) */ 172137b6f646SAnirudh Venkataramanan struct ice_aqc_lldp_start { 172237b6f646SAnirudh Venkataramanan u8 command; 172337b6f646SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_START BIT(0) 172437b6f646SAnirudh Venkataramanan #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 172537b6f646SAnirudh Venkataramanan u8 reserved[15]; 172637b6f646SAnirudh Venkataramanan }; 172737b6f646SAnirudh Venkataramanan 17280ebd3ff1SAnirudh Venkataramanan /* Get CEE DCBX Oper Config (0x0A07) 17290ebd3ff1SAnirudh Venkataramanan * The command uses the generic descriptor struct and 17300ebd3ff1SAnirudh Venkataramanan * returns the struct below as an indirect response. 17310ebd3ff1SAnirudh Venkataramanan */ 17320ebd3ff1SAnirudh Venkataramanan struct ice_aqc_get_cee_dcb_cfg_resp { 17330ebd3ff1SAnirudh Venkataramanan u8 oper_num_tc; 17340ebd3ff1SAnirudh Venkataramanan u8 oper_prio_tc[4]; 17350ebd3ff1SAnirudh Venkataramanan u8 oper_tc_bw[8]; 17360ebd3ff1SAnirudh Venkataramanan u8 oper_pfc_en; 17370ebd3ff1SAnirudh Venkataramanan __le16 oper_app_prio; 17380ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_FCOE_S 0 17390ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 17400ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_ISCSI_S 3 17410ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 17420ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_FIP_S 8 17430ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 17440ebd3ff1SAnirudh Venkataramanan __le32 tlv_status; 17450ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_PG_STATUS_S 0 17460ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 17470ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_PFC_STATUS_S 3 17480ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 17490ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_FCOE_STATUS_S 8 17500ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 17510ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_ISCSI_STATUS_S 11 17520ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 17530ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_FIP_STATUS_S 16 17540ebd3ff1SAnirudh Venkataramanan #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 17550ebd3ff1SAnirudh Venkataramanan u8 reserved[12]; 17560ebd3ff1SAnirudh Venkataramanan }; 17570ebd3ff1SAnirudh Venkataramanan 17587b9ffc76SAnirudh Venkataramanan /* Set Local LLDP MIB (indirect 0x0A08) 17592f2da36eSAnirudh Venkataramanan * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 17607b9ffc76SAnirudh Venkataramanan */ 17617b9ffc76SAnirudh Venkataramanan struct ice_aqc_lldp_set_local_mib { 17627b9ffc76SAnirudh Venkataramanan u8 type; 17637b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 17647b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 17657b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 17667b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 17677b9ffc76SAnirudh Venkataramanan #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 17687b9ffc76SAnirudh Venkataramanan u8 reserved0; 17697b9ffc76SAnirudh Venkataramanan __le16 length; 17707b9ffc76SAnirudh Venkataramanan u8 reserved1[4]; 17717b9ffc76SAnirudh Venkataramanan __le32 addr_high; 17727b9ffc76SAnirudh Venkataramanan __le32 addr_low; 17737b9ffc76SAnirudh Venkataramanan }; 17747b9ffc76SAnirudh Venkataramanan 177537b6f646SAnirudh Venkataramanan /* Stop/Start LLDP Agent (direct 0x0A09) 17762f2da36eSAnirudh Venkataramanan * Used for stopping/starting specific LLDP agent. e.g. DCBX. 177737b6f646SAnirudh Venkataramanan * The same structure is used for the response, with the command field 177837b6f646SAnirudh Venkataramanan * being used as the status field. 177937b6f646SAnirudh Venkataramanan */ 178037b6f646SAnirudh Venkataramanan struct ice_aqc_lldp_stop_start_specific_agent { 178137b6f646SAnirudh Venkataramanan u8 command; 178237b6f646SAnirudh Venkataramanan #define ICE_AQC_START_STOP_AGENT_M BIT(0) 178337b6f646SAnirudh Venkataramanan #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 178437b6f646SAnirudh Venkataramanan #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 178537b6f646SAnirudh Venkataramanan u8 reserved[15]; 178637b6f646SAnirudh Venkataramanan }; 178737b6f646SAnirudh Venkataramanan 178834295a36SDave Ertman /* LLDP Filter Control (direct 0x0A0A) */ 178934295a36SDave Ertman struct ice_aqc_lldp_filter_ctrl { 179034295a36SDave Ertman u8 cmd_flags; 179134295a36SDave Ertman #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 179234295a36SDave Ertman #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 179334295a36SDave Ertman u8 reserved1; 179434295a36SDave Ertman __le16 vsi_num; 179534295a36SDave Ertman u8 reserved2[12]; 179634295a36SDave Ertman }; 179734295a36SDave Ertman 1798b6143c9bSPrzemek Kitszel #define ICE_AQC_RSS_VSI_VALID BIT(15) 1799b6143c9bSPrzemek Kitszel 1800d76a60baSAnirudh Venkataramanan /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 1801d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_key { 1802d76a60baSAnirudh Venkataramanan __le16 vsi_id; 1803d76a60baSAnirudh Venkataramanan u8 reserved[6]; 1804d76a60baSAnirudh Venkataramanan __le32 addr_high; 1805d76a60baSAnirudh Venkataramanan __le32 addr_low; 1806d76a60baSAnirudh Venkataramanan }; 1807d76a60baSAnirudh Venkataramanan 1808d76a60baSAnirudh Venkataramanan #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 1809d76a60baSAnirudh Venkataramanan #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 1810b4b418b3SPaul Greenwalt #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 1811b4b418b3SPaul Greenwalt (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 1812b4b418b3SPaul Greenwalt ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 1813d76a60baSAnirudh Venkataramanan 1814d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_keys { 1815d76a60baSAnirudh Venkataramanan u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 1816d76a60baSAnirudh Venkataramanan u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 1817d76a60baSAnirudh Venkataramanan }; 1818d76a60baSAnirudh Venkataramanan 1819b6143c9bSPrzemek Kitszel enum ice_lut_type { 1820b6143c9bSPrzemek Kitszel ICE_LUT_VSI = 0, 1821b6143c9bSPrzemek Kitszel ICE_LUT_PF = 1, 1822b6143c9bSPrzemek Kitszel ICE_LUT_GLOBAL = 2, 1823b6143c9bSPrzemek Kitszel }; 1824b6143c9bSPrzemek Kitszel 1825b6143c9bSPrzemek Kitszel enum ice_lut_size { 1826b6143c9bSPrzemek Kitszel ICE_LUT_VSI_SIZE = 64, 1827b6143c9bSPrzemek Kitszel ICE_LUT_GLOBAL_SIZE = 512, 1828b6143c9bSPrzemek Kitszel ICE_LUT_PF_SIZE = 2048, 1829b6143c9bSPrzemek Kitszel }; 1830b6143c9bSPrzemek Kitszel 1831b6143c9bSPrzemek Kitszel /* enum ice_aqc_lut_flags combines constants used to fill 1832b6143c9bSPrzemek Kitszel * &ice_aqc_get_set_rss_lut ::flags, which is an amalgamation of global LUT ID, 1833b6143c9bSPrzemek Kitszel * LUT size and LUT type, last of which does not need neither shift nor mask. 1834b6143c9bSPrzemek Kitszel */ 1835b6143c9bSPrzemek Kitszel enum ice_aqc_lut_flags { 1836b6143c9bSPrzemek Kitszel ICE_AQC_LUT_SIZE_SMALL = 0, /* size = 64 or 128 */ 1837b6143c9bSPrzemek Kitszel ICE_AQC_LUT_SIZE_512 = BIT(2), 1838b6143c9bSPrzemek Kitszel ICE_AQC_LUT_SIZE_2K = BIT(3), 1839b6143c9bSPrzemek Kitszel 1840b6143c9bSPrzemek Kitszel ICE_AQC_LUT_GLOBAL_IDX = GENMASK(7, 4), 1841b6143c9bSPrzemek Kitszel }; 1842b6143c9bSPrzemek Kitszel 1843d76a60baSAnirudh Venkataramanan /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 1844d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_lut { 1845d76a60baSAnirudh Venkataramanan __le16 vsi_id; 1846d76a60baSAnirudh Venkataramanan __le16 flags; 1847d76a60baSAnirudh Venkataramanan __le32 reserved; 1848d76a60baSAnirudh Venkataramanan __le32 addr_high; 1849d76a60baSAnirudh Venkataramanan __le32 addr_low; 1850d76a60baSAnirudh Venkataramanan }; 1851d76a60baSAnirudh Venkataramanan 18528f5ee3c4SJacob Keller /* Sideband Control Interface Commands */ 18538f5ee3c4SJacob Keller /* Neighbor Device Request (indirect 0x0C00); also used for the response. */ 18548f5ee3c4SJacob Keller struct ice_aqc_neigh_dev_req { 18558f5ee3c4SJacob Keller __le16 sb_data_len; 18568f5ee3c4SJacob Keller u8 reserved[6]; 18578f5ee3c4SJacob Keller __le32 addr_high; 18588f5ee3c4SJacob Keller __le32 addr_low; 18598f5ee3c4SJacob Keller }; 18608f5ee3c4SJacob Keller 1861f9867df6SAnirudh Venkataramanan /* Add Tx LAN Queues (indirect 0x0C30) */ 1862cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs { 1863cdedef59SAnirudh Venkataramanan u8 num_qgrps; 1864cdedef59SAnirudh Venkataramanan u8 reserved[3]; 1865cdedef59SAnirudh Venkataramanan __le32 reserved1; 1866cdedef59SAnirudh Venkataramanan __le32 addr_high; 1867cdedef59SAnirudh Venkataramanan __le32 addr_low; 1868cdedef59SAnirudh Venkataramanan }; 1869cdedef59SAnirudh Venkataramanan 1870f9867df6SAnirudh Venkataramanan /* This is the descriptor of each queue entry for the Add Tx LAN Queues 1871cdedef59SAnirudh Venkataramanan * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 1872cdedef59SAnirudh Venkataramanan */ 1873cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs_perq { 1874cdedef59SAnirudh Venkataramanan __le16 txq_id; 1875cdedef59SAnirudh Venkataramanan u8 rsvd[2]; 1876cdedef59SAnirudh Venkataramanan __le32 q_teid; 1877cdedef59SAnirudh Venkataramanan u8 txq_ctx[22]; 1878cdedef59SAnirudh Venkataramanan u8 rsvd2[2]; 1879cdedef59SAnirudh Venkataramanan struct ice_aqc_txsched_elem info; 1880cdedef59SAnirudh Venkataramanan }; 1881cdedef59SAnirudh Venkataramanan 1882f9867df6SAnirudh Venkataramanan /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 1883cdedef59SAnirudh Venkataramanan * is an array of the following structs. Please note that the length of 1884cdedef59SAnirudh Venkataramanan * each struct ice_aqc_add_tx_qgrp is variable due 1885cdedef59SAnirudh Venkataramanan * to the variable number of queues in each group! 1886cdedef59SAnirudh Venkataramanan */ 1887cdedef59SAnirudh Venkataramanan struct ice_aqc_add_tx_qgrp { 1888cdedef59SAnirudh Venkataramanan __le32 parent_teid; 1889cdedef59SAnirudh Venkataramanan u8 num_txqs; 1890cdedef59SAnirudh Venkataramanan u8 rsvd[3]; 189166486d89SBruce Allan struct ice_aqc_add_txqs_perq txqs[]; 1892cdedef59SAnirudh Venkataramanan }; 1893cdedef59SAnirudh Venkataramanan 1894f9867df6SAnirudh Venkataramanan /* Disable Tx LAN Queues (indirect 0x0C31) */ 1895cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txqs { 1896cdedef59SAnirudh Venkataramanan u8 cmd_type; 1897cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_S 0 1898cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 1899cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 1900cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 1901cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 1902cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 1903cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 1904cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 1905cdedef59SAnirudh Venkataramanan u8 num_entries; 1906cdedef59SAnirudh Venkataramanan __le16 vmvf_and_timeout; 1907cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 1908cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 1909cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_TIMEOUT_S 10 1910cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 1911cdedef59SAnirudh Venkataramanan __le32 blocked_cgds; 1912cdedef59SAnirudh Venkataramanan __le32 addr_high; 1913cdedef59SAnirudh Venkataramanan __le32 addr_low; 1914cdedef59SAnirudh Venkataramanan }; 1915cdedef59SAnirudh Venkataramanan 1916f9867df6SAnirudh Venkataramanan /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 1917cdedef59SAnirudh Venkataramanan * contains the following structures, arrayed one after the 1918cdedef59SAnirudh Venkataramanan * other. 1919cdedef59SAnirudh Venkataramanan * Note: Since the q_id is 16 bits wide, if the 1920cdedef59SAnirudh Venkataramanan * number of queues is even, then 2 bytes of alignment MUST be 1921cdedef59SAnirudh Venkataramanan * added before the start of the next group, to allow correct 1922cdedef59SAnirudh Venkataramanan * alignment of the parent_teid field. 1923cdedef59SAnirudh Venkataramanan */ 1924cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txq_item { 1925cdedef59SAnirudh Venkataramanan __le32 parent_teid; 1926cdedef59SAnirudh Venkataramanan u8 num_qs; 1927cdedef59SAnirudh Venkataramanan u8 rsvd; 1928cdedef59SAnirudh Venkataramanan /* The length of the q_id array varies according to num_qs */ 1929cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 1930cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 1931cdedef59SAnirudh Venkataramanan (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 1932cdedef59SAnirudh Venkataramanan #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 1933cdedef59SAnirudh Venkataramanan (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 193466486d89SBruce Allan __le16 q_id[]; 193566486d89SBruce Allan } __packed; 1936cdedef59SAnirudh Venkataramanan 193723ccae5cSDave Ertman /* Move/Reconfigure Tx queue (indirect 0x0C32) */ 193823ccae5cSDave Ertman struct ice_aqc_cfg_txqs { 193923ccae5cSDave Ertman u8 cmd_type; 194023ccae5cSDave Ertman #define ICE_AQC_Q_CFG_MOVE_NODE 0x1 194123ccae5cSDave Ertman #define ICE_AQC_Q_CFG_TC_CHNG 0x2 194223ccae5cSDave Ertman #define ICE_AQC_Q_CFG_MOVE_TC_CHNG 0x3 194323ccae5cSDave Ertman #define ICE_AQC_Q_CFG_SUBSEQ_CALL BIT(2) 194423ccae5cSDave Ertman #define ICE_AQC_Q_CFG_FLUSH BIT(3) 194523ccae5cSDave Ertman u8 num_qs; 194623ccae5cSDave Ertman u8 port_num_chng; 194723ccae5cSDave Ertman #define ICE_AQC_Q_CFG_SRC_PRT_M 0x7 194823ccae5cSDave Ertman #define ICE_AQC_Q_CFG_DST_PRT_S 3 194923ccae5cSDave Ertman #define ICE_AQC_Q_CFG_DST_PRT_M (0x7 << ICE_AQC_Q_CFG_DST_PRT_S) 195023ccae5cSDave Ertman u8 time_out; 195123ccae5cSDave Ertman #define ICE_AQC_Q_CFG_TIMEOUT_S 2 195223ccae5cSDave Ertman #define ICE_AQC_Q_CFG_TIMEOUT_M (0x1F << ICE_AQC_Q_CFG_TIMEOUT_S) 195323ccae5cSDave Ertman __le32 blocked_cgds; 195423ccae5cSDave Ertman __le32 addr_high; 195523ccae5cSDave Ertman __le32 addr_low; 195623ccae5cSDave Ertman }; 195723ccae5cSDave Ertman 195823ccae5cSDave Ertman /* Per Q struct for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 195923ccae5cSDave Ertman struct ice_aqc_cfg_txq_perq { 196023ccae5cSDave Ertman __le16 q_handle; 196123ccae5cSDave Ertman u8 tc; 196223ccae5cSDave Ertman u8 rsvd; 196323ccae5cSDave Ertman __le32 q_teid; 196423ccae5cSDave Ertman }; 196523ccae5cSDave Ertman 196623ccae5cSDave Ertman /* The buffer for Move/Reconfigure Tx LAN Queues (indirect 0x0C32) */ 196723ccae5cSDave Ertman struct ice_aqc_cfg_txqs_buf { 196823ccae5cSDave Ertman __le32 src_parent_teid; 196923ccae5cSDave Ertman __le32 dst_parent_teid; 197023ccae5cSDave Ertman struct ice_aqc_cfg_txq_perq queue_info[]; 197123ccae5cSDave Ertman }; 197223ccae5cSDave Ertman 1973348048e7SDave Ertman /* Add Tx RDMA Queue Set (indirect 0x0C33) */ 1974348048e7SDave Ertman struct ice_aqc_add_rdma_qset { 1975348048e7SDave Ertman u8 num_qset_grps; 1976348048e7SDave Ertman u8 reserved[7]; 1977348048e7SDave Ertman __le32 addr_high; 1978348048e7SDave Ertman __le32 addr_low; 1979348048e7SDave Ertman }; 1980348048e7SDave Ertman 1981348048e7SDave Ertman /* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set 1982348048e7SDave Ertman * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. 1983348048e7SDave Ertman */ 1984348048e7SDave Ertman struct ice_aqc_add_tx_rdma_qset_entry { 1985348048e7SDave Ertman __le16 tx_qset_id; 1986348048e7SDave Ertman u8 rsvd[2]; 1987348048e7SDave Ertman __le32 qset_teid; 1988348048e7SDave Ertman struct ice_aqc_txsched_elem info; 1989348048e7SDave Ertman }; 1990348048e7SDave Ertman 1991348048e7SDave Ertman /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) 1992348048e7SDave Ertman * is an array of the following structs. Please note that the length of 1993348048e7SDave Ertman * each struct ice_aqc_add_rdma_qset is variable due to the variable 1994348048e7SDave Ertman * number of queues in each group! 1995348048e7SDave Ertman */ 1996348048e7SDave Ertman struct ice_aqc_add_rdma_qset_data { 1997348048e7SDave Ertman __le32 parent_teid; 1998348048e7SDave Ertman __le16 num_qsets; 1999348048e7SDave Ertman u8 rsvd[2]; 2000348048e7SDave Ertman struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[]; 2001348048e7SDave Ertman }; 2002348048e7SDave Ertman 20038b97ceb1SHieu Tran /* Configure Firmware Logging Command (indirect 0xFF09) 20048b97ceb1SHieu Tran * Logging Information Read Response (indirect 0xFF10) 20058b97ceb1SHieu Tran * Note: The 0xFF10 command has no input parameters. 20068b97ceb1SHieu Tran */ 20078b97ceb1SHieu Tran struct ice_aqc_fw_logging { 20088b97ceb1SHieu Tran u8 log_ctrl; 20098b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_AQ_EN BIT(0) 20108b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_UART_EN BIT(1) 20118b97ceb1SHieu Tran u8 rsvd0; 20128b97ceb1SHieu Tran u8 log_ctrl_valid; /* Not used by 0xFF10 Response */ 20138b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_AQ_VALID BIT(0) 20148b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_UART_VALID BIT(1) 20158b97ceb1SHieu Tran u8 rsvd1[5]; 20168b97ceb1SHieu Tran __le32 addr_high; 20178b97ceb1SHieu Tran __le32 addr_low; 20188b97ceb1SHieu Tran }; 20198b97ceb1SHieu Tran 20208b97ceb1SHieu Tran enum ice_aqc_fw_logging_mod { 20218b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_GENERAL = 0, 20228b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_CTRL, 20238b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_LINK, 20248b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_LINK_TOPO, 20258b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_DNL, 20268b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_I2C, 20278b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_SDP, 20288b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_MDIO, 20298b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_ADMINQ, 20308b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_HDMA, 20318b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_LLDP, 20328b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_DCBX, 20338b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_DCB, 20348b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_NETPROXY, 20358b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_NVM, 20368b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_AUTH, 20378b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_VPD, 20388b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_IOSF, 20398b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_PARSER, 20408b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_SW, 20418b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_SCHEDULER, 20428b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_TXQ, 20438b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_RSVD, 20448b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_POST, 20458b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_WATCHDOG, 20468b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 20478b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_MNG, 20488b97ceb1SHieu Tran ICE_AQC_FW_LOG_ID_MAX, 20498b97ceb1SHieu Tran }; 20508b97ceb1SHieu Tran 2051b3c38904SBruce Allan /* Defines for both above FW logging command/response buffers */ 20528b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_ID_S 0 20538b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S) 20548b97ceb1SHieu Tran 20558b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */ 20568b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */ 20578b97ceb1SHieu Tran 20588b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_EN_S 12 20598b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S) 20608b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */ 20618b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */ 20628b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */ 20638b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */ 20648b97ceb1SHieu Tran 20658b97ceb1SHieu Tran /* Get/Clear FW Log (indirect 0xFF11) */ 20668b97ceb1SHieu Tran struct ice_aqc_get_clear_fw_log { 20678b97ceb1SHieu Tran u8 flags; 20688b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_CLEAR BIT(0) 20698b97ceb1SHieu Tran #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1) 20708b97ceb1SHieu Tran u8 rsvd1[7]; 20718b97ceb1SHieu Tran __le32 addr_high; 20728b97ceb1SHieu Tran __le32 addr_low; 20738b97ceb1SHieu Tran }; 20748b97ceb1SHieu Tran 2075c7648810STony Nguyen /* Download Package (indirect 0x0C40) */ 2076a1ffafb0SBrett Creeley /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */ 2077c7648810STony Nguyen struct ice_aqc_download_pkg { 2078c7648810STony Nguyen u8 flags; 2079c7648810STony Nguyen #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2080c7648810STony Nguyen u8 reserved[3]; 2081c7648810STony Nguyen __le32 reserved1; 2082c7648810STony Nguyen __le32 addr_high; 2083c7648810STony Nguyen __le32 addr_low; 2084c7648810STony Nguyen }; 2085c7648810STony Nguyen 2086c7648810STony Nguyen struct ice_aqc_download_pkg_resp { 2087c7648810STony Nguyen __le32 error_offset; 2088c7648810STony Nguyen __le32 error_info; 2089c7648810STony Nguyen __le32 addr_high; 2090c7648810STony Nguyen __le32 addr_low; 2091c7648810STony Nguyen }; 2092c7648810STony Nguyen 2093c7648810STony Nguyen /* Get Package Info List (indirect 0x0C43) */ 2094c7648810STony Nguyen struct ice_aqc_get_pkg_info_list { 2095c7648810STony Nguyen __le32 reserved1; 2096c7648810STony Nguyen __le32 reserved2; 2097c7648810STony Nguyen __le32 addr_high; 2098c7648810STony Nguyen __le32 addr_low; 2099c7648810STony Nguyen }; 2100c7648810STony Nguyen 2101c7648810STony Nguyen /* Version format for packages */ 2102c7648810STony Nguyen struct ice_pkg_ver { 2103c7648810STony Nguyen u8 major; 2104c7648810STony Nguyen u8 minor; 2105c7648810STony Nguyen u8 update; 2106c7648810STony Nguyen u8 draft; 2107c7648810STony Nguyen }; 2108c7648810STony Nguyen 2109c7648810STony Nguyen #define ICE_PKG_NAME_SIZE 32 2110a05983c3SDan Nowlin #define ICE_SEG_ID_SIZE 28 2111b8272919SVictor Raj #define ICE_SEG_NAME_SIZE 28 2112c7648810STony Nguyen 2113c7648810STony Nguyen struct ice_aqc_get_pkg_info { 2114c7648810STony Nguyen struct ice_pkg_ver ver; 2115b8272919SVictor Raj char name[ICE_SEG_NAME_SIZE]; 2116b8272919SVictor Raj __le32 track_id; 2117c7648810STony Nguyen u8 is_in_nvm; 2118c7648810STony Nguyen u8 is_active; 2119c7648810STony Nguyen u8 is_active_at_boot; 2120c7648810STony Nguyen u8 is_modified; 2121c7648810STony Nguyen }; 2122c7648810STony Nguyen 2123c7648810STony Nguyen /* Get Package Info List response buffer format (0x0C43) */ 2124c7648810STony Nguyen struct ice_aqc_get_pkg_info_resp { 2125c7648810STony Nguyen __le32 count; 212666486d89SBruce Allan struct ice_aqc_get_pkg_info pkg_info[]; 2127c7648810STony Nguyen }; 21284ee656bbSTony Nguyen 21297f9ab54dSJacob Keller /* Driver Shared Parameters (direct, 0x0C90) */ 21307f9ab54dSJacob Keller struct ice_aqc_driver_shared_params { 21317f9ab54dSJacob Keller u8 set_or_get_op; 21327f9ab54dSJacob Keller #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 21337f9ab54dSJacob Keller #define ICE_AQC_DRIVER_PARAM_SET 0 21347f9ab54dSJacob Keller #define ICE_AQC_DRIVER_PARAM_GET 1 21357f9ab54dSJacob Keller u8 param_indx; 21367f9ab54dSJacob Keller #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 21377f9ab54dSJacob Keller u8 rsvd[2]; 21387f9ab54dSJacob Keller __le32 param_val; 21397f9ab54dSJacob Keller __le32 addr_high; 21407f9ab54dSJacob Keller __le32 addr_low; 21417f9ab54dSJacob Keller }; 21427f9ab54dSJacob Keller 21437f9ab54dSJacob Keller enum ice_aqc_driver_params { 21447f9ab54dSJacob Keller /* OS clock index for PTP timer Domain 0 */ 21457f9ab54dSJacob Keller ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0 = 0, 21467f9ab54dSJacob Keller /* OS clock index for PTP timer Domain 1 */ 21477f9ab54dSJacob Keller ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1, 21487f9ab54dSJacob Keller 21497f9ab54dSJacob Keller /* Add new parameters above */ 21507f9ab54dSJacob Keller ICE_AQC_DRIVER_PARAM_MAX = 16, 21517f9ab54dSJacob Keller }; 21527f9ab54dSJacob Keller 21532309ae38SBrett Creeley /* Lan Queue Overflow Event (direct, 0x1001) */ 21542309ae38SBrett Creeley struct ice_aqc_event_lan_overflow { 21552309ae38SBrett Creeley __le32 prtdcb_ruptq; 21562309ae38SBrett Creeley __le32 qtx_ctl; 21572309ae38SBrett Creeley u8 reserved[8]; 21582309ae38SBrett Creeley }; 21592309ae38SBrett Creeley 21607ec59eeaSAnirudh Venkataramanan /** 21617ec59eeaSAnirudh Venkataramanan * struct ice_aq_desc - Admin Queue (AQ) descriptor 21627ec59eeaSAnirudh Venkataramanan * @flags: ICE_AQ_FLAG_* flags 21637ec59eeaSAnirudh Venkataramanan * @opcode: AQ command opcode 21647ec59eeaSAnirudh Venkataramanan * @datalen: length in bytes of indirect/external data buffer 21657ec59eeaSAnirudh Venkataramanan * @retval: return value from firmware 2166b50f7bcaSJesse Brandeburg * @cookie_high: opaque data high-half 2167b50f7bcaSJesse Brandeburg * @cookie_low: opaque data low-half 21687ec59eeaSAnirudh Venkataramanan * @params: command-specific parameters 21697ec59eeaSAnirudh Venkataramanan * 21707ec59eeaSAnirudh Venkataramanan * Descriptor format for commands the driver posts on the Admin Transmit Queue 21717ec59eeaSAnirudh Venkataramanan * (ATQ). The firmware writes back onto the command descriptor and returns 21727ec59eeaSAnirudh Venkataramanan * the result of the command. Asynchronous events that are not an immediate 21737ec59eeaSAnirudh Venkataramanan * result of the command are written to the Admin Receive Queue (ARQ) using 21747ec59eeaSAnirudh Venkataramanan * the same descriptor format. Descriptors are in little-endian notation with 21757ec59eeaSAnirudh Venkataramanan * 32-bit words. 21767ec59eeaSAnirudh Venkataramanan */ 21777ec59eeaSAnirudh Venkataramanan struct ice_aq_desc { 21787ec59eeaSAnirudh Venkataramanan __le16 flags; 21797ec59eeaSAnirudh Venkataramanan __le16 opcode; 21807ec59eeaSAnirudh Venkataramanan __le16 datalen; 21817ec59eeaSAnirudh Venkataramanan __le16 retval; 21827ec59eeaSAnirudh Venkataramanan __le32 cookie_high; 21837ec59eeaSAnirudh Venkataramanan __le32 cookie_low; 21847ec59eeaSAnirudh Venkataramanan union { 21857ec59eeaSAnirudh Venkataramanan u8 raw[16]; 21867ec59eeaSAnirudh Venkataramanan struct ice_aqc_generic generic; 21877ec59eeaSAnirudh Venkataramanan struct ice_aqc_get_ver get_ver; 2188e3710a01SPaul M Stillwell Jr struct ice_aqc_driver_ver driver_ver; 21897ec59eeaSAnirudh Venkataramanan struct ice_aqc_q_shutdown q_shutdown; 2190f31e4b6fSAnirudh Venkataramanan struct ice_aqc_req_res res_owner; 2191dc49c772SAnirudh Venkataramanan struct ice_aqc_manage_mac_read mac_read; 2192e94d4478SAnirudh Venkataramanan struct ice_aqc_manage_mac_write mac_write; 2193f31e4b6fSAnirudh Venkataramanan struct ice_aqc_clear_pxe clear_pxe; 21949c20346bSAnirudh Venkataramanan struct ice_aqc_list_caps get_cap; 2195dc49c772SAnirudh Venkataramanan struct ice_aqc_get_phy_caps get_phy; 2196fcea6f3dSAnirudh Venkataramanan struct ice_aqc_set_phy_cfg set_phy; 2197fcea6f3dSAnirudh Venkataramanan struct ice_aqc_restart_an restart_an; 21983bb6324bSMaciej Machnikowski struct ice_aqc_gpio read_write_gpio; 2199a012dca9SScott W Taylor struct ice_aqc_sff_eeprom read_write_sff_param; 22008e151d50SAnirudh Venkataramanan struct ice_aqc_set_port_id_led set_port_id_led; 2201781f15eaSAnatolii Gerasymenko struct ice_aqc_get_port_options get_port_options; 2202781f15eaSAnatolii Gerasymenko struct ice_aqc_set_port_option set_port_option; 22039c20346bSAnirudh Venkataramanan struct ice_aqc_get_sw_cfg get_sw_conf; 2204a1ffafb0SBrett Creeley struct ice_aqc_set_port_params set_port_params; 22059daf8208SAnirudh Venkataramanan struct ice_aqc_sw_rules sw_rules; 22067715ec32SGrishma Kotecha struct ice_aqc_add_get_recipe add_get_recipe; 22077715ec32SGrishma Kotecha struct ice_aqc_recipe_to_profile recipe_to_profile; 2208dc49c772SAnirudh Venkataramanan struct ice_aqc_get_topo get_topo; 22091f9c7840SAnirudh Venkataramanan struct ice_aqc_sched_elem_cmd sched_elem_cmd; 22109c20346bSAnirudh Venkataramanan struct ice_aqc_query_txsched_res query_sched_res; 22117b9ffc76SAnirudh Venkataramanan struct ice_aqc_query_port_ets port_ets; 22121ddef455SUsha Ketineni struct ice_aqc_rl_profile rl_profile; 2213f31e4b6fSAnirudh Venkataramanan struct ice_aqc_nvm nvm; 22140e674aebSAnirudh Venkataramanan struct ice_aqc_nvm_checksum nvm_checksum; 2215544cd2acSCudzilo, Szymon T struct ice_aqc_nvm_pkg_data pkg_data; 2216544cd2acSCudzilo, Szymon T struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl; 2217007676b4SAnirudh Venkataramanan struct ice_aqc_pf_vf_msg virt; 22182a87bd73SDave Ertman struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 22190ebd3ff1SAnirudh Venkataramanan struct ice_aqc_lldp_get_mib lldp_get_mib; 22200ebd3ff1SAnirudh Venkataramanan struct ice_aqc_lldp_set_mib_change lldp_set_event; 22213a257a14SAnirudh Venkataramanan struct ice_aqc_lldp_stop lldp_stop; 222237b6f646SAnirudh Venkataramanan struct ice_aqc_lldp_start lldp_start; 22237b9ffc76SAnirudh Venkataramanan struct ice_aqc_lldp_set_local_mib lldp_set_mib; 222437b6f646SAnirudh Venkataramanan struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 222534295a36SDave Ertman struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2226d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2227d76a60baSAnirudh Venkataramanan struct ice_aqc_get_set_rss_key get_set_rss_key; 22288f5ee3c4SJacob Keller struct ice_aqc_neigh_dev_req neigh_dev; 2229cdedef59SAnirudh Venkataramanan struct ice_aqc_add_txqs add_txqs; 2230cdedef59SAnirudh Venkataramanan struct ice_aqc_dis_txqs dis_txqs; 223123ccae5cSDave Ertman struct ice_aqc_cfg_txqs cfg_txqs; 2232348048e7SDave Ertman struct ice_aqc_add_rdma_qset add_rdma_qset; 22333a858ba3SAnirudh Venkataramanan struct ice_aqc_add_get_update_free_vsi vsi_cmd; 22340f9d5027SAnirudh Venkataramanan struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 22358b97ceb1SHieu Tran struct ice_aqc_fw_logging fw_logging; 22368b97ceb1SHieu Tran struct ice_aqc_get_clear_fw_log get_clear_fw_log; 2237c7648810STony Nguyen struct ice_aqc_download_pkg download_pkg; 22387f9ab54dSJacob Keller struct ice_aqc_driver_shared_params drv_shared_params; 22390e674aebSAnirudh Venkataramanan struct ice_aqc_set_mac_lb set_mac_lb; 22409daf8208SAnirudh Venkataramanan struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 224142449105SAnirudh Venkataramanan struct ice_aqc_set_mac_cfg set_mac_cfg; 22420b28b702SAnirudh Venkataramanan struct ice_aqc_set_event_mask set_event_mask; 2243dc49c772SAnirudh Venkataramanan struct ice_aqc_get_link_status get_link_status; 22442309ae38SBrett Creeley struct ice_aqc_event_lan_overflow lan_overflow; 22458ea1da59SPaul Greenwalt struct ice_aqc_get_link_topo get_link_topo; 2246fcf9b695SKarol Kolacinski struct ice_aqc_i2c read_write_i2c; 224743113ff7SKarol Kolacinski struct ice_aqc_read_i2c_resp read_i2c_resp; 22487ec59eeaSAnirudh Venkataramanan } params; 22497ec59eeaSAnirudh Venkataramanan }; 22507ec59eeaSAnirudh Venkataramanan 22517ec59eeaSAnirudh Venkataramanan /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 22527ec59eeaSAnirudh Venkataramanan #define ICE_AQ_LG_BUF 512 22537ec59eeaSAnirudh Venkataramanan 2254940b61afSAnirudh Venkataramanan #define ICE_AQ_FLAG_ERR_S 2 22557ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_LB_S 9 22569c20346bSAnirudh Venkataramanan #define ICE_AQ_FLAG_RD_S 10 22577ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_BUF_S 12 22587ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_SI_S 13 22597ec59eeaSAnirudh Venkataramanan 2260940b61afSAnirudh Venkataramanan #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 22617ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 22629c20346bSAnirudh Venkataramanan #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 22637ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 22647ec59eeaSAnirudh Venkataramanan #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 22657ec59eeaSAnirudh Venkataramanan 22667ec59eeaSAnirudh Venkataramanan /* error codes */ 22677ec59eeaSAnirudh Venkataramanan enum ice_aq_err { 2268df17b7e0SAnirudh Venkataramanan ICE_AQ_RC_OK = 0, /* Success */ 22690ebd3ff1SAnirudh Venkataramanan ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 22700ebd3ff1SAnirudh Venkataramanan ICE_AQ_RC_ENOENT = 2, /* No such element */ 22719c20346bSAnirudh Venkataramanan ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2272f31e4b6fSAnirudh Venkataramanan ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2273df17b7e0SAnirudh Venkataramanan ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 227481f07491SJacob Keller ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2275e94d4478SAnirudh Venkataramanan ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 227690e47737SMitch Williams ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2277b5e19a64SChinh T Cao ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2278c7648810STony Nguyen ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2279c7648810STony Nguyen ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2280c7648810STony Nguyen ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2281c7648810STony Nguyen ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2282c7648810STony Nguyen ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 22837ec59eeaSAnirudh Venkataramanan }; 22847ec59eeaSAnirudh Venkataramanan 22857ec59eeaSAnirudh Venkataramanan /* Admin Queue command opcodes */ 22867ec59eeaSAnirudh Venkataramanan enum ice_adminq_opc { 22877ec59eeaSAnirudh Venkataramanan /* AQ commands */ 22887ec59eeaSAnirudh Venkataramanan ice_aqc_opc_get_ver = 0x0001, 2289e3710a01SPaul M Stillwell Jr ice_aqc_opc_driver_ver = 0x0002, 22907ec59eeaSAnirudh Venkataramanan ice_aqc_opc_q_shutdown = 0x0003, 2291f31e4b6fSAnirudh Venkataramanan 2292f31e4b6fSAnirudh Venkataramanan /* resource ownership */ 2293f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_req_res = 0x0008, 2294f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_release_res = 0x0009, 2295f31e4b6fSAnirudh Venkataramanan 22969c20346bSAnirudh Venkataramanan /* device/function capabilities */ 22979c20346bSAnirudh Venkataramanan ice_aqc_opc_list_func_caps = 0x000A, 22989c20346bSAnirudh Venkataramanan ice_aqc_opc_list_dev_caps = 0x000B, 22999c20346bSAnirudh Venkataramanan 2300dc49c772SAnirudh Venkataramanan /* manage MAC address */ 2301dc49c772SAnirudh Venkataramanan ice_aqc_opc_manage_mac_read = 0x0107, 2302e94d4478SAnirudh Venkataramanan ice_aqc_opc_manage_mac_write = 0x0108, 2303dc49c772SAnirudh Venkataramanan 2304f31e4b6fSAnirudh Venkataramanan /* PXE */ 2305f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_clear_pxe_mode = 0x0110, 2306f31e4b6fSAnirudh Venkataramanan 23079c20346bSAnirudh Venkataramanan /* internal switch commands */ 23089c20346bSAnirudh Venkataramanan ice_aqc_opc_get_sw_cfg = 0x0200, 2309a1ffafb0SBrett Creeley ice_aqc_opc_set_port_params = 0x0203, 23109c20346bSAnirudh Venkataramanan 23119daf8208SAnirudh Venkataramanan /* Alloc/Free/Get Resources */ 23129daf8208SAnirudh Venkataramanan ice_aqc_opc_alloc_res = 0x0208, 23139daf8208SAnirudh Venkataramanan ice_aqc_opc_free_res = 0x0209, 231423ccae5cSDave Ertman ice_aqc_opc_share_res = 0x020B, 2315a1ffafb0SBrett Creeley ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 2316a1ffafb0SBrett Creeley ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 23179daf8208SAnirudh Venkataramanan 23183a858ba3SAnirudh Venkataramanan /* VSI commands */ 23193a858ba3SAnirudh Venkataramanan ice_aqc_opc_add_vsi = 0x0210, 23203a858ba3SAnirudh Venkataramanan ice_aqc_opc_update_vsi = 0x0211, 23213a858ba3SAnirudh Venkataramanan ice_aqc_opc_free_vsi = 0x0213, 23229daf8208SAnirudh Venkataramanan 23237715ec32SGrishma Kotecha /* recipe commands */ 23247715ec32SGrishma Kotecha ice_aqc_opc_add_recipe = 0x0290, 23257715ec32SGrishma Kotecha ice_aqc_opc_recipe_to_profile = 0x0291, 23267715ec32SGrishma Kotecha ice_aqc_opc_get_recipe = 0x0292, 23277715ec32SGrishma Kotecha ice_aqc_opc_get_recipe_to_profile = 0x0293, 23287715ec32SGrishma Kotecha 23299daf8208SAnirudh Venkataramanan /* switch rules population commands */ 23309daf8208SAnirudh Venkataramanan ice_aqc_opc_add_sw_rules = 0x02A0, 23319daf8208SAnirudh Venkataramanan ice_aqc_opc_update_sw_rules = 0x02A1, 23329daf8208SAnirudh Venkataramanan ice_aqc_opc_remove_sw_rules = 0x02A2, 23339daf8208SAnirudh Venkataramanan 2334f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_clear_pf_cfg = 0x02A4, 2335f31e4b6fSAnirudh Venkataramanan 23362a87bd73SDave Ertman /* DCB commands */ 23372a87bd73SDave Ertman ice_aqc_opc_query_pfc_mode = 0x0302, 23382a87bd73SDave Ertman ice_aqc_opc_set_pfc_mode = 0x0303, 23392a87bd73SDave Ertman 23409c20346bSAnirudh Venkataramanan /* transmit scheduler commands */ 2341dc49c772SAnirudh Venkataramanan ice_aqc_opc_get_dflt_topo = 0x0400, 23425513b920SAnirudh Venkataramanan ice_aqc_opc_add_sched_elems = 0x0401, 23431ddef455SUsha Ketineni ice_aqc_opc_cfg_sched_elems = 0x0403, 234456daee6cSAnirudh Venkataramanan ice_aqc_opc_get_sched_elems = 0x0404, 2345b126bd6bSKiran Patil ice_aqc_opc_move_sched_elems = 0x0408, 23465513b920SAnirudh Venkataramanan ice_aqc_opc_suspend_sched_elems = 0x0409, 23475513b920SAnirudh Venkataramanan ice_aqc_opc_resume_sched_elems = 0x040A, 23487b9ffc76SAnirudh Venkataramanan ice_aqc_opc_query_port_ets = 0x040E, 23499c20346bSAnirudh Venkataramanan ice_aqc_opc_delete_sched_elems = 0x040F, 23501ddef455SUsha Ketineni ice_aqc_opc_add_rl_profiles = 0x0410, 23519c20346bSAnirudh Venkataramanan ice_aqc_opc_query_sched_res = 0x0412, 23521ddef455SUsha Ketineni ice_aqc_opc_remove_rl_profiles = 0x0415, 23539c20346bSAnirudh Venkataramanan 2354dc49c772SAnirudh Venkataramanan /* PHY commands */ 2355dc49c772SAnirudh Venkataramanan ice_aqc_opc_get_phy_caps = 0x0600, 2356fcea6f3dSAnirudh Venkataramanan ice_aqc_opc_set_phy_cfg = 0x0601, 235742449105SAnirudh Venkataramanan ice_aqc_opc_set_mac_cfg = 0x0603, 2358fcea6f3dSAnirudh Venkataramanan ice_aqc_opc_restart_an = 0x0605, 2359dc49c772SAnirudh Venkataramanan ice_aqc_opc_get_link_status = 0x0607, 23600b28b702SAnirudh Venkataramanan ice_aqc_opc_set_event_mask = 0x0613, 23610e674aebSAnirudh Venkataramanan ice_aqc_opc_set_mac_lb = 0x0620, 23628ea1da59SPaul Greenwalt ice_aqc_opc_get_link_topo = 0x06E0, 236343113ff7SKarol Kolacinski ice_aqc_opc_read_i2c = 0x06E2, 2364fcf9b695SKarol Kolacinski ice_aqc_opc_write_i2c = 0x06E3, 23658e151d50SAnirudh Venkataramanan ice_aqc_opc_set_port_id_led = 0x06E9, 2366781f15eaSAnatolii Gerasymenko ice_aqc_opc_get_port_options = 0x06EA, 2367781f15eaSAnatolii Gerasymenko ice_aqc_opc_set_port_option = 0x06EB, 23683bb6324bSMaciej Machnikowski ice_aqc_opc_set_gpio = 0x06EC, 23693bb6324bSMaciej Machnikowski ice_aqc_opc_get_gpio = 0x06ED, 2370a012dca9SScott W Taylor ice_aqc_opc_sff_eeprom = 0x06EE, 2371dc49c772SAnirudh Venkataramanan 2372f31e4b6fSAnirudh Venkataramanan /* NVM commands */ 2373f31e4b6fSAnirudh Venkataramanan ice_aqc_opc_nvm_read = 0x0701, 2374544cd2acSCudzilo, Szymon T ice_aqc_opc_nvm_erase = 0x0702, 2375544cd2acSCudzilo, Szymon T ice_aqc_opc_nvm_write = 0x0703, 23760e674aebSAnirudh Venkataramanan ice_aqc_opc_nvm_checksum = 0x0706, 2377544cd2acSCudzilo, Szymon T ice_aqc_opc_nvm_write_activate = 0x0707, 2378544cd2acSCudzilo, Szymon T ice_aqc_opc_nvm_update_empr = 0x0709, 2379544cd2acSCudzilo, Szymon T ice_aqc_opc_nvm_pkg_data = 0x070A, 2380544cd2acSCudzilo, Szymon T ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 2381f31e4b6fSAnirudh Venkataramanan 2382007676b4SAnirudh Venkataramanan /* PF/VF mailbox commands */ 23831071a835SAnirudh Venkataramanan ice_mbx_opc_send_msg_to_pf = 0x0801, 2384007676b4SAnirudh Venkataramanan ice_mbx_opc_send_msg_to_vf = 0x0802, 238537b6f646SAnirudh Venkataramanan /* LLDP commands */ 23860ebd3ff1SAnirudh Venkataramanan ice_aqc_opc_lldp_get_mib = 0x0A00, 23870ebd3ff1SAnirudh Venkataramanan ice_aqc_opc_lldp_set_mib_change = 0x0A01, 23883a257a14SAnirudh Venkataramanan ice_aqc_opc_lldp_stop = 0x0A05, 238937b6f646SAnirudh Venkataramanan ice_aqc_opc_lldp_start = 0x0A06, 23900ebd3ff1SAnirudh Venkataramanan ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 23917b9ffc76SAnirudh Venkataramanan ice_aqc_opc_lldp_set_local_mib = 0x0A08, 239237b6f646SAnirudh Venkataramanan ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 239334295a36SDave Ertman ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 2394a4f68f37STsotne Chakhvadze ice_aqc_opc_lldp_execute_pending_mib = 0x0A0B, 2395007676b4SAnirudh Venkataramanan 2396d76a60baSAnirudh Venkataramanan /* RSS commands */ 2397d76a60baSAnirudh Venkataramanan ice_aqc_opc_set_rss_key = 0x0B02, 2398d76a60baSAnirudh Venkataramanan ice_aqc_opc_set_rss_lut = 0x0B03, 2399d76a60baSAnirudh Venkataramanan ice_aqc_opc_get_rss_key = 0x0B04, 2400d76a60baSAnirudh Venkataramanan ice_aqc_opc_get_rss_lut = 0x0B05, 2401d76a60baSAnirudh Venkataramanan 24028f5ee3c4SJacob Keller /* Sideband Control Interface commands */ 24038f5ee3c4SJacob Keller ice_aqc_opc_neighbour_device_request = 0x0C00, 24048f5ee3c4SJacob Keller 2405f9867df6SAnirudh Venkataramanan /* Tx queue handling commands/events */ 2406cdedef59SAnirudh Venkataramanan ice_aqc_opc_add_txqs = 0x0C30, 2407cdedef59SAnirudh Venkataramanan ice_aqc_opc_dis_txqs = 0x0C31, 240823ccae5cSDave Ertman ice_aqc_opc_cfg_txqs = 0x0C32, 2409348048e7SDave Ertman ice_aqc_opc_add_rdma_qset = 0x0C33, 24108b97ceb1SHieu Tran 2411c7648810STony Nguyen /* package commands */ 2412c7648810STony Nguyen ice_aqc_opc_download_pkg = 0x0C40, 2413a1ffafb0SBrett Creeley ice_aqc_opc_upload_section = 0x0C41, 241443dbfc7bSTony Nguyen ice_aqc_opc_update_pkg = 0x0C42, 2415c7648810STony Nguyen ice_aqc_opc_get_pkg_info_list = 0x0C43, 2416c7648810STony Nguyen 24177f9ab54dSJacob Keller ice_aqc_opc_driver_shared_params = 0x0C90, 24187f9ab54dSJacob Keller 24192309ae38SBrett Creeley /* Standalone Commands/Events */ 24202309ae38SBrett Creeley ice_aqc_opc_event_lan_overflow = 0x1001, 24212309ae38SBrett Creeley 24228b97ceb1SHieu Tran /* debug commands */ 24238b97ceb1SHieu Tran ice_aqc_opc_fw_logging = 0xFF09, 242411fe1b3aSDan Nowlin ice_aqc_opc_fw_logging_info = 0xFF10, 24257ec59eeaSAnirudh Venkataramanan }; 24267ec59eeaSAnirudh Venkataramanan 24277ec59eeaSAnirudh Venkataramanan #endif /* _ICE_ADMINQ_CMD_H_ */ 2428