1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_H_ 5 #define _ICE_H_ 6 7 #include <linux/types.h> 8 #include <linux/errno.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/compiler.h> 13 #include <linux/etherdevice.h> 14 #include <linux/skbuff.h> 15 #include <linux/cpumask.h> 16 #include <linux/rtnetlink.h> 17 #include <linux/if_vlan.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/pci.h> 20 #include <linux/workqueue.h> 21 #include <linux/aer.h> 22 #include <linux/interrupt.h> 23 #include <linux/ethtool.h> 24 #include <linux/timer.h> 25 #include <linux/delay.h> 26 #include <linux/bitmap.h> 27 #include <linux/log2.h> 28 #include <linux/ip.h> 29 #include <linux/ipv6.h> 30 #include <linux/if_bridge.h> 31 #include <net/ipv6.h> 32 #include "ice_devids.h" 33 #include "ice_type.h" 34 #include "ice_txrx.h" 35 #include "ice_switch.h" 36 #include "ice_common.h" 37 #include "ice_sched.h" 38 39 extern const char ice_drv_ver[]; 40 #define ICE_BAR0 0 41 #define ICE_DFLT_NUM_DESC 128 42 #define ICE_MIN_NUM_DESC 8 43 #define ICE_MAX_NUM_DESC 8160 44 #define ICE_REQ_DESC_MULTIPLE 32 45 #define ICE_DFLT_TRAFFIC_CLASS BIT(0) 46 #define ICE_INT_NAME_STR_LEN (IFNAMSIZ + 16) 47 #define ICE_ETHTOOL_FWVER_LEN 32 48 #define ICE_AQ_LEN 64 49 #define ICE_MIN_MSIX 2 50 #define ICE_NO_VSI 0xffff 51 #define ICE_MAX_VSI_ALLOC 130 52 #define ICE_MAX_TXQS 2048 53 #define ICE_MAX_RXQS 2048 54 #define ICE_VSI_MAP_CONTIG 0 55 #define ICE_VSI_MAP_SCATTER 1 56 #define ICE_MAX_SCATTER_TXQS 16 57 #define ICE_MAX_SCATTER_RXQS 16 58 #define ICE_Q_WAIT_RETRY_LIMIT 10 59 #define ICE_Q_WAIT_MAX_RETRY (5 * ICE_Q_WAIT_RETRY_LIMIT) 60 #define ICE_MAX_LG_RSS_QS 256 61 #define ICE_MAX_SMALL_RSS_QS 8 62 #define ICE_RES_VALID_BIT 0x8000 63 #define ICE_RES_MISC_VEC_ID (ICE_RES_VALID_BIT - 1) 64 #define ICE_INVAL_Q_INDEX 0xffff 65 #define ICE_INVAL_VFID 256 66 67 #define ICE_VSIQF_HKEY_ARRAY_SIZE ((VSIQF_HKEY_MAX_INDEX + 1) * 4) 68 69 #define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 70 71 #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - \ 72 ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN) 73 74 #define ICE_UP_TABLE_TRANSLATE(val, i) \ 75 (((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \ 76 ICE_AQ_VSI_UP_TABLE_UP##i##_M) 77 78 #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i])) 79 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i])) 80 #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i])) 81 82 /* Macro for each VSI in a PF */ 83 #define ice_for_each_vsi(pf, i) \ 84 for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++) 85 86 /* Macros for each tx/rx ring in a VSI */ 87 #define ice_for_each_txq(vsi, i) \ 88 for ((i) = 0; (i) < (vsi)->num_txq; (i)++) 89 90 #define ice_for_each_rxq(vsi, i) \ 91 for ((i) = 0; (i) < (vsi)->num_rxq; (i)++) 92 93 /* Macros for each allocated tx/rx ring whether used or not in a VSI */ 94 #define ice_for_each_alloc_txq(vsi, i) \ 95 for ((i) = 0; (i) < (vsi)->alloc_txq; (i)++) 96 97 #define ice_for_each_alloc_rxq(vsi, i) \ 98 for ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++) 99 100 struct ice_tc_info { 101 u16 qoffset; 102 u16 qcount; 103 }; 104 105 struct ice_tc_cfg { 106 u8 numtc; /* Total number of enabled TCs */ 107 u8 ena_tc; /* TX map */ 108 struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS]; 109 }; 110 111 struct ice_res_tracker { 112 u16 num_entries; 113 u16 search_hint; 114 u16 list[1]; 115 }; 116 117 struct ice_sw { 118 struct ice_pf *pf; 119 u16 sw_id; /* switch ID for this switch */ 120 u16 bridge_mode; /* VEB/VEPA/Port Virtualizer */ 121 }; 122 123 enum ice_state { 124 __ICE_DOWN, 125 __ICE_NEEDS_RESTART, 126 __ICE_PREPARED_FOR_RESET, /* set by driver when prepared */ 127 __ICE_RESET_RECOVERY_PENDING, /* set by driver when reset starts */ 128 __ICE_PFR_REQ, /* set by driver and peers */ 129 __ICE_CORER_REQ, /* set by driver and peers */ 130 __ICE_GLOBR_REQ, /* set by driver and peers */ 131 __ICE_CORER_RECV, /* set by OICR handler */ 132 __ICE_GLOBR_RECV, /* set by OICR handler */ 133 __ICE_EMPR_RECV, /* set by OICR handler */ 134 __ICE_SUSPENDED, /* set on module remove path */ 135 __ICE_RESET_FAILED, /* set by reset/rebuild */ 136 __ICE_ADMINQ_EVENT_PENDING, 137 __ICE_MDD_EVENT_PENDING, 138 __ICE_FLTR_OVERFLOW_PROMISC, 139 __ICE_CFG_BUSY, 140 __ICE_SERVICE_SCHED, 141 __ICE_SERVICE_DIS, 142 __ICE_STATE_NBITS /* must be last */ 143 }; 144 145 enum ice_vsi_flags { 146 ICE_VSI_FLAG_UMAC_FLTR_CHANGED, 147 ICE_VSI_FLAG_MMAC_FLTR_CHANGED, 148 ICE_VSI_FLAG_VLAN_FLTR_CHANGED, 149 ICE_VSI_FLAG_PROMISC_CHANGED, 150 ICE_VSI_FLAG_NBITS /* must be last */ 151 }; 152 153 /* struct that defines a VSI, associated with a dev */ 154 struct ice_vsi { 155 struct net_device *netdev; 156 struct ice_sw *vsw; /* switch this VSI is on */ 157 struct ice_pf *back; /* back pointer to PF */ 158 struct ice_port_info *port_info; /* back pointer to port_info */ 159 struct ice_ring **rx_rings; /* rx ring array */ 160 struct ice_ring **tx_rings; /* tx ring array */ 161 struct ice_q_vector **q_vectors; /* q_vector array */ 162 163 irqreturn_t (*irq_handler)(int irq, void *data); 164 165 u64 tx_linearize; 166 DECLARE_BITMAP(state, __ICE_STATE_NBITS); 167 DECLARE_BITMAP(flags, ICE_VSI_FLAG_NBITS); 168 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 169 unsigned int current_netdev_flags; 170 u32 tx_restart; 171 u32 tx_busy; 172 u32 rx_buf_failed; 173 u32 rx_page_failed; 174 int num_q_vectors; 175 int base_vector; 176 enum ice_vsi_type type; 177 u16 vsi_num; /* HW (absolute) index of this VSI */ 178 u16 idx; /* software index in pf->vsi[] */ 179 180 /* Interrupt thresholds */ 181 u16 work_lmt; 182 183 /* RSS config */ 184 u16 rss_table_size; /* HW RSS table size */ 185 u16 rss_size; /* Allocated RSS queues */ 186 u8 *rss_hkey_user; /* User configured hash keys */ 187 u8 *rss_lut_user; /* User configured lookup table entries */ 188 u8 rss_lut_type; /* used to configure Get/Set RSS LUT AQ call */ 189 190 u16 max_frame; 191 u16 rx_buf_len; 192 193 struct ice_aqc_vsi_props info; /* VSI properties */ 194 195 /* VSI stats */ 196 struct rtnl_link_stats64 net_stats; 197 struct ice_eth_stats eth_stats; 198 struct ice_eth_stats eth_stats_prev; 199 200 struct list_head tmp_sync_list; /* MAC filters to be synced */ 201 struct list_head tmp_unsync_list; /* MAC filters to be unsynced */ 202 203 u8 irqs_ready; 204 u8 current_isup; /* Sync 'link up' logging */ 205 u8 stat_offsets_loaded; 206 207 /* queue information */ 208 u8 tx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */ 209 u8 rx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */ 210 u16 txq_map[ICE_MAX_TXQS]; /* index in pf->avail_txqs */ 211 u16 rxq_map[ICE_MAX_RXQS]; /* index in pf->avail_rxqs */ 212 u16 alloc_txq; /* Allocated Tx queues */ 213 u16 num_txq; /* Used Tx queues */ 214 u16 alloc_rxq; /* Allocated Rx queues */ 215 u16 num_rxq; /* Used Rx queues */ 216 u16 num_desc; 217 struct ice_tc_cfg tc_cfg; 218 } ____cacheline_internodealigned_in_smp; 219 220 /* struct that defines an interrupt vector */ 221 struct ice_q_vector { 222 struct ice_vsi *vsi; 223 cpumask_t affinity_mask; 224 struct napi_struct napi; 225 struct ice_ring_container rx; 226 struct ice_ring_container tx; 227 struct irq_affinity_notify affinity_notify; 228 u16 v_idx; /* index in the vsi->q_vector array. */ 229 u8 num_ring_tx; /* total number of tx rings in vector */ 230 u8 num_ring_rx; /* total number of rx rings in vector */ 231 char name[ICE_INT_NAME_STR_LEN]; 232 } ____cacheline_internodealigned_in_smp; 233 234 enum ice_pf_flags { 235 ICE_FLAG_MSIX_ENA, 236 ICE_FLAG_FLTR_SYNC, 237 ICE_FLAG_RSS_ENA, 238 ICE_PF_FLAGS_NBITS /* must be last */ 239 }; 240 241 struct ice_pf { 242 struct pci_dev *pdev; 243 struct msix_entry *msix_entries; 244 struct ice_res_tracker *irq_tracker; 245 struct ice_vsi **vsi; /* VSIs created by the driver */ 246 struct ice_sw *first_sw; /* first switch created by firmware */ 247 DECLARE_BITMAP(state, __ICE_STATE_NBITS); 248 DECLARE_BITMAP(avail_txqs, ICE_MAX_TXQS); 249 DECLARE_BITMAP(avail_rxqs, ICE_MAX_RXQS); 250 DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS); 251 unsigned long serv_tmr_period; 252 unsigned long serv_tmr_prev; 253 struct timer_list serv_tmr; 254 struct work_struct serv_task; 255 struct mutex avail_q_mutex; /* protects access to avail_[rx|tx]qs */ 256 struct mutex sw_mutex; /* lock for protecting VSI alloc flow */ 257 u32 msg_enable; 258 u32 hw_csum_rx_error; 259 u32 oicr_idx; /* Other interrupt cause vector index */ 260 u32 num_lan_msix; /* Total MSIX vectors for base driver */ 261 u32 num_avail_msix; /* remaining MSIX vectors left unclaimed */ 262 u16 num_lan_tx; /* num lan tx queues setup */ 263 u16 num_lan_rx; /* num lan rx queues setup */ 264 u16 q_left_tx; /* remaining num tx queues left unclaimed */ 265 u16 q_left_rx; /* remaining num rx queues left unclaimed */ 266 u16 next_vsi; /* Next free slot in pf->vsi[] - 0-based! */ 267 u16 num_alloc_vsi; 268 u16 corer_count; /* Core reset count */ 269 u16 globr_count; /* Global reset count */ 270 u16 empr_count; /* EMP reset count */ 271 u16 pfr_count; /* PF reset count */ 272 273 struct ice_hw_port_stats stats; 274 struct ice_hw_port_stats stats_prev; 275 struct ice_hw hw; 276 u8 stat_prev_loaded; /* has previous stats been loaded */ 277 u32 tx_timeout_count; 278 unsigned long tx_timeout_last_recovery; 279 u32 tx_timeout_recovery_level; 280 char int_name[ICE_INT_NAME_STR_LEN]; 281 }; 282 283 struct ice_netdev_priv { 284 struct ice_vsi *vsi; 285 }; 286 287 /** 288 * ice_irq_dynamic_ena - Enable default interrupt generation settings 289 * @hw: pointer to hw struct 290 * @vsi: pointer to vsi struct, can be NULL 291 * @q_vector: pointer to q_vector, can be NULL 292 */ 293 static inline void ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi, 294 struct ice_q_vector *q_vector) 295 { 296 u32 vector = (vsi && q_vector) ? vsi->base_vector + q_vector->v_idx : 297 ((struct ice_pf *)hw->back)->oicr_idx; 298 int itr = ICE_ITR_NONE; 299 u32 val; 300 301 /* clear the PBA here, as this function is meant to clean out all 302 * previous interrupts and enable the interrupt 303 */ 304 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 305 (itr << GLINT_DYN_CTL_ITR_INDX_S); 306 if (vsi) 307 if (test_bit(__ICE_DOWN, vsi->state)) 308 return; 309 wr32(hw, GLINT_DYN_CTL(vector), val); 310 } 311 312 static inline void ice_vsi_set_tc_cfg(struct ice_vsi *vsi) 313 { 314 vsi->tc_cfg.ena_tc = ICE_DFLT_TRAFFIC_CLASS; 315 vsi->tc_cfg.numtc = 1; 316 } 317 318 void ice_set_ethtool_ops(struct net_device *netdev); 319 int ice_up(struct ice_vsi *vsi); 320 int ice_down(struct ice_vsi *vsi); 321 int ice_set_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 322 int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 323 void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size); 324 void ice_print_link_msg(struct ice_vsi *vsi, bool isup); 325 326 #endif /* _ICE_H_ */ 327