1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_H_ 5 #define _ICE_H_ 6 7 #include <linux/types.h> 8 #include <linux/errno.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/compiler.h> 13 #include <linux/etherdevice.h> 14 #include <linux/skbuff.h> 15 #include <linux/cpumask.h> 16 #include <linux/rtnetlink.h> 17 #include <linux/if_vlan.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/pci.h> 20 #include <linux/workqueue.h> 21 #include <linux/aer.h> 22 #include <linux/interrupt.h> 23 #include <linux/ethtool.h> 24 #include <linux/timer.h> 25 #include <linux/delay.h> 26 #include <linux/bitmap.h> 27 #include <linux/log2.h> 28 #include <linux/ip.h> 29 #include <linux/ipv6.h> 30 #include <linux/if_bridge.h> 31 #include <linux/avf/virtchnl.h> 32 #include <net/ipv6.h> 33 #include "ice_devids.h" 34 #include "ice_type.h" 35 #include "ice_txrx.h" 36 #include "ice_switch.h" 37 #include "ice_common.h" 38 #include "ice_sched.h" 39 #include "ice_virtchnl_pf.h" 40 #include "ice_sriov.h" 41 42 extern const char ice_drv_ver[]; 43 #define ICE_BAR0 0 44 #define ICE_DFLT_NUM_DESC 128 45 #define ICE_REQ_DESC_MULTIPLE 32 46 #define ICE_MIN_NUM_DESC ICE_REQ_DESC_MULTIPLE 47 #define ICE_MAX_NUM_DESC 8160 48 #define ICE_DFLT_TRAFFIC_CLASS BIT(0) 49 #define ICE_INT_NAME_STR_LEN (IFNAMSIZ + 16) 50 #define ICE_ETHTOOL_FWVER_LEN 32 51 #define ICE_AQ_LEN 64 52 #define ICE_MBXQ_LEN 64 53 #define ICE_MIN_MSIX 2 54 #define ICE_NO_VSI 0xffff 55 #define ICE_MAX_TXQS 2048 56 #define ICE_MAX_RXQS 2048 57 #define ICE_VSI_MAP_CONTIG 0 58 #define ICE_VSI_MAP_SCATTER 1 59 #define ICE_MAX_SCATTER_TXQS 16 60 #define ICE_MAX_SCATTER_RXQS 16 61 #define ICE_Q_WAIT_RETRY_LIMIT 10 62 #define ICE_Q_WAIT_MAX_RETRY (5 * ICE_Q_WAIT_RETRY_LIMIT) 63 #define ICE_MAX_LG_RSS_QS 256 64 #define ICE_MAX_SMALL_RSS_QS 8 65 #define ICE_RES_VALID_BIT 0x8000 66 #define ICE_RES_MISC_VEC_ID (ICE_RES_VALID_BIT - 1) 67 #define ICE_INVAL_Q_INDEX 0xffff 68 #define ICE_INVAL_VFID 256 69 #define ICE_MAX_VF_COUNT 256 70 #define ICE_MAX_QS_PER_VF 256 71 #define ICE_MIN_QS_PER_VF 1 72 #define ICE_DFLT_QS_PER_VF 4 73 #define ICE_MAX_BASE_QS_PER_VF 16 74 #define ICE_MAX_INTR_PER_VF 65 75 #define ICE_MIN_INTR_PER_VF (ICE_MIN_QS_PER_VF + 1) 76 #define ICE_DFLT_INTR_PER_VF (ICE_DFLT_QS_PER_VF + 1) 77 78 #define ICE_MAX_RESET_WAIT 20 79 80 #define ICE_VSIQF_HKEY_ARRAY_SIZE ((VSIQF_HKEY_MAX_INDEX + 1) * 4) 81 82 #define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 83 84 #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - \ 85 ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN) 86 87 #define ICE_UP_TABLE_TRANSLATE(val, i) \ 88 (((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \ 89 ICE_AQ_VSI_UP_TABLE_UP##i##_M) 90 91 #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i])) 92 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i])) 93 #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i])) 94 95 /* Macro for each VSI in a PF */ 96 #define ice_for_each_vsi(pf, i) \ 97 for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++) 98 99 /* Macros for each Tx/Rx ring in a VSI */ 100 #define ice_for_each_txq(vsi, i) \ 101 for ((i) = 0; (i) < (vsi)->num_txq; (i)++) 102 103 #define ice_for_each_rxq(vsi, i) \ 104 for ((i) = 0; (i) < (vsi)->num_rxq; (i)++) 105 106 /* Macros for each allocated Tx/Rx ring whether used or not in a VSI */ 107 #define ice_for_each_alloc_txq(vsi, i) \ 108 for ((i) = 0; (i) < (vsi)->alloc_txq; (i)++) 109 110 #define ice_for_each_alloc_rxq(vsi, i) \ 111 for ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++) 112 113 struct ice_tc_info { 114 u16 qoffset; 115 u16 qcount_tx; 116 u16 qcount_rx; 117 u8 netdev_tc; 118 }; 119 120 struct ice_tc_cfg { 121 u8 numtc; /* Total number of enabled TCs */ 122 u8 ena_tc; /* TX map */ 123 struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS]; 124 }; 125 126 struct ice_res_tracker { 127 u16 num_entries; 128 u16 search_hint; 129 u16 list[1]; 130 }; 131 132 struct ice_sw { 133 struct ice_pf *pf; 134 u16 sw_id; /* switch ID for this switch */ 135 u16 bridge_mode; /* VEB/VEPA/Port Virtualizer */ 136 }; 137 138 enum ice_state { 139 __ICE_DOWN, 140 __ICE_NEEDS_RESTART, 141 __ICE_PREPARED_FOR_RESET, /* set by driver when prepared */ 142 __ICE_RESET_OICR_RECV, /* set by driver after rcv reset OICR */ 143 __ICE_PFR_REQ, /* set by driver and peers */ 144 __ICE_CORER_REQ, /* set by driver and peers */ 145 __ICE_GLOBR_REQ, /* set by driver and peers */ 146 __ICE_CORER_RECV, /* set by OICR handler */ 147 __ICE_GLOBR_RECV, /* set by OICR handler */ 148 __ICE_EMPR_RECV, /* set by OICR handler */ 149 __ICE_SUSPENDED, /* set on module remove path */ 150 __ICE_RESET_FAILED, /* set by reset/rebuild */ 151 /* When checking for the PF to be in a nominal operating state, the 152 * bits that are grouped at the beginning of the list need to be 153 * checked. Bits occurring before __ICE_STATE_NOMINAL_CHECK_BITS will 154 * be checked. If you need to add a bit into consideration for nominal 155 * operating state, it must be added before 156 * __ICE_STATE_NOMINAL_CHECK_BITS. Do not move this entry's position 157 * without appropriate consideration. 158 */ 159 __ICE_STATE_NOMINAL_CHECK_BITS, 160 __ICE_ADMINQ_EVENT_PENDING, 161 __ICE_MAILBOXQ_EVENT_PENDING, 162 __ICE_MDD_EVENT_PENDING, 163 __ICE_VFLR_EVENT_PENDING, 164 __ICE_FLTR_OVERFLOW_PROMISC, 165 __ICE_VF_DIS, 166 __ICE_CFG_BUSY, 167 __ICE_SERVICE_SCHED, 168 __ICE_SERVICE_DIS, 169 __ICE_STATE_NBITS /* must be last */ 170 }; 171 172 enum ice_vsi_flags { 173 ICE_VSI_FLAG_UMAC_FLTR_CHANGED, 174 ICE_VSI_FLAG_MMAC_FLTR_CHANGED, 175 ICE_VSI_FLAG_VLAN_FLTR_CHANGED, 176 ICE_VSI_FLAG_PROMISC_CHANGED, 177 ICE_VSI_FLAG_NBITS /* must be last */ 178 }; 179 180 /* struct that defines a VSI, associated with a dev */ 181 struct ice_vsi { 182 struct net_device *netdev; 183 struct ice_sw *vsw; /* switch this VSI is on */ 184 struct ice_pf *back; /* back pointer to PF */ 185 struct ice_port_info *port_info; /* back pointer to port_info */ 186 struct ice_ring **rx_rings; /* Rx ring array */ 187 struct ice_ring **tx_rings; /* Tx ring array */ 188 struct ice_q_vector **q_vectors; /* q_vector array */ 189 190 irqreturn_t (*irq_handler)(int irq, void *data); 191 192 u64 tx_linearize; 193 DECLARE_BITMAP(state, __ICE_STATE_NBITS); 194 DECLARE_BITMAP(flags, ICE_VSI_FLAG_NBITS); 195 unsigned int current_netdev_flags; 196 u32 tx_restart; 197 u32 tx_busy; 198 u32 rx_buf_failed; 199 u32 rx_page_failed; 200 int num_q_vectors; 201 int sw_base_vector; /* Irq base for OS reserved vectors */ 202 int hw_base_vector; /* HW (absolute) index of a vector */ 203 enum ice_vsi_type type; 204 u16 vsi_num; /* HW (absolute) index of this VSI */ 205 u16 idx; /* software index in pf->vsi[] */ 206 207 /* Interrupt thresholds */ 208 u16 work_lmt; 209 210 s16 vf_id; /* VF ID for SR-IOV VSIs */ 211 212 /* RSS config */ 213 u16 rss_table_size; /* HW RSS table size */ 214 u16 rss_size; /* Allocated RSS queues */ 215 u8 *rss_hkey_user; /* User configured hash keys */ 216 u8 *rss_lut_user; /* User configured lookup table entries */ 217 u8 rss_lut_type; /* used to configure Get/Set RSS LUT AQ call */ 218 219 u16 max_frame; 220 u16 rx_buf_len; 221 222 struct ice_aqc_vsi_props info; /* VSI properties */ 223 224 /* VSI stats */ 225 struct rtnl_link_stats64 net_stats; 226 struct ice_eth_stats eth_stats; 227 struct ice_eth_stats eth_stats_prev; 228 229 struct list_head tmp_sync_list; /* MAC filters to be synced */ 230 struct list_head tmp_unsync_list; /* MAC filters to be unsynced */ 231 232 u8 irqs_ready; 233 u8 current_isup; /* Sync 'link up' logging */ 234 u8 stat_offsets_loaded; 235 236 /* queue information */ 237 u8 tx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */ 238 u8 rx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */ 239 u16 txq_map[ICE_MAX_TXQS]; /* index in pf->avail_txqs */ 240 u16 rxq_map[ICE_MAX_RXQS]; /* index in pf->avail_rxqs */ 241 u16 alloc_txq; /* Allocated Tx queues */ 242 u16 num_txq; /* Used Tx queues */ 243 u16 alloc_rxq; /* Allocated Rx queues */ 244 u16 num_rxq; /* Used Rx queues */ 245 u16 num_desc; 246 struct ice_tc_cfg tc_cfg; 247 } ____cacheline_internodealigned_in_smp; 248 249 /* struct that defines an interrupt vector */ 250 struct ice_q_vector { 251 struct ice_vsi *vsi; 252 cpumask_t affinity_mask; 253 struct napi_struct napi; 254 struct ice_ring_container rx; 255 struct ice_ring_container tx; 256 struct irq_affinity_notify affinity_notify; 257 u16 v_idx; /* index in the vsi->q_vector array. */ 258 u8 num_ring_tx; /* total number of Tx rings in vector */ 259 u8 num_ring_rx; /* total number of Rx rings in vector */ 260 char name[ICE_INT_NAME_STR_LEN]; 261 /* in usecs, need to use ice_intrl_to_usecs_reg() before writing this 262 * value to the device 263 */ 264 u8 intrl; 265 } ____cacheline_internodealigned_in_smp; 266 267 enum ice_pf_flags { 268 ICE_FLAG_MSIX_ENA, 269 ICE_FLAG_FLTR_SYNC, 270 ICE_FLAG_RSS_ENA, 271 ICE_FLAG_SRIOV_ENA, 272 ICE_FLAG_SRIOV_CAPABLE, 273 ICE_PF_FLAGS_NBITS /* must be last */ 274 }; 275 276 struct ice_pf { 277 struct pci_dev *pdev; 278 279 /* OS reserved IRQ details */ 280 struct msix_entry *msix_entries; 281 struct ice_res_tracker *sw_irq_tracker; 282 283 /* HW reserved Interrupts for this PF */ 284 struct ice_res_tracker *hw_irq_tracker; 285 286 struct ice_vsi **vsi; /* VSIs created by the driver */ 287 struct ice_sw *first_sw; /* first switch created by firmware */ 288 /* Virtchnl/SR-IOV config info */ 289 struct ice_vf *vf; 290 int num_alloc_vfs; /* actual number of VFs allocated */ 291 u16 num_vfs_supported; /* num VFs supported for this PF */ 292 u16 num_vf_qps; /* num queue pairs per VF */ 293 u16 num_vf_msix; /* num vectors per VF */ 294 DECLARE_BITMAP(state, __ICE_STATE_NBITS); 295 DECLARE_BITMAP(avail_txqs, ICE_MAX_TXQS); 296 DECLARE_BITMAP(avail_rxqs, ICE_MAX_RXQS); 297 DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS); 298 unsigned long serv_tmr_period; 299 unsigned long serv_tmr_prev; 300 struct timer_list serv_tmr; 301 struct work_struct serv_task; 302 struct mutex avail_q_mutex; /* protects access to avail_[rx|tx]qs */ 303 struct mutex sw_mutex; /* lock for protecting VSI alloc flow */ 304 u32 msg_enable; 305 u32 hw_csum_rx_error; 306 u32 sw_oicr_idx; /* Other interrupt cause SW vector index */ 307 u32 num_avail_sw_msix; /* remaining MSIX SW vectors left unclaimed */ 308 u32 hw_oicr_idx; /* Other interrupt cause vector HW index */ 309 u32 num_avail_hw_msix; /* remaining HW MSIX vectors left unclaimed */ 310 u32 num_lan_msix; /* Total MSIX vectors for base driver */ 311 u16 num_lan_tx; /* num lan Tx queues setup */ 312 u16 num_lan_rx; /* num lan Rx queues setup */ 313 u16 q_left_tx; /* remaining num Tx queues left unclaimed */ 314 u16 q_left_rx; /* remaining num Rx queues left unclaimed */ 315 u16 next_vsi; /* Next free slot in pf->vsi[] - 0-based! */ 316 u16 num_alloc_vsi; 317 u16 corer_count; /* Core reset count */ 318 u16 globr_count; /* Global reset count */ 319 u16 empr_count; /* EMP reset count */ 320 u16 pfr_count; /* PF reset count */ 321 322 struct ice_hw_port_stats stats; 323 struct ice_hw_port_stats stats_prev; 324 struct ice_hw hw; 325 u8 stat_prev_loaded; /* has previous stats been loaded */ 326 u32 tx_timeout_count; 327 unsigned long tx_timeout_last_recovery; 328 u32 tx_timeout_recovery_level; 329 char int_name[ICE_INT_NAME_STR_LEN]; 330 }; 331 332 struct ice_netdev_priv { 333 struct ice_vsi *vsi; 334 }; 335 336 /** 337 * ice_irq_dynamic_ena - Enable default interrupt generation settings 338 * @hw: pointer to hw struct 339 * @vsi: pointer to vsi struct, can be NULL 340 * @q_vector: pointer to q_vector, can be NULL 341 */ 342 static inline void ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi, 343 struct ice_q_vector *q_vector) 344 { 345 u32 vector = (vsi && q_vector) ? vsi->hw_base_vector + q_vector->v_idx : 346 ((struct ice_pf *)hw->back)->hw_oicr_idx; 347 int itr = ICE_ITR_NONE; 348 u32 val; 349 350 /* clear the PBA here, as this function is meant to clean out all 351 * previous interrupts and enable the interrupt 352 */ 353 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 354 (itr << GLINT_DYN_CTL_ITR_INDX_S); 355 if (vsi) 356 if (test_bit(__ICE_DOWN, vsi->state)) 357 return; 358 wr32(hw, GLINT_DYN_CTL(vector), val); 359 } 360 361 static inline void ice_vsi_set_tc_cfg(struct ice_vsi *vsi) 362 { 363 vsi->tc_cfg.ena_tc = ICE_DFLT_TRAFFIC_CLASS; 364 vsi->tc_cfg.numtc = 1; 365 } 366 367 void ice_set_ethtool_ops(struct net_device *netdev); 368 int ice_up(struct ice_vsi *vsi); 369 int ice_down(struct ice_vsi *vsi); 370 int ice_set_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 371 int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 372 void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size); 373 void ice_print_link_msg(struct ice_vsi *vsi, bool isup); 374 void ice_napi_del(struct ice_vsi *vsi); 375 376 #endif /* _ICE_H_ */ 377