1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_H_ 5 #define _ICE_H_ 6 7 #include <linux/types.h> 8 #include <linux/errno.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/compiler.h> 13 #include <linux/etherdevice.h> 14 #include <linux/skbuff.h> 15 #include <linux/cpumask.h> 16 #include <linux/rtnetlink.h> 17 #include <linux/if_vlan.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/pci.h> 20 #include <linux/workqueue.h> 21 #include <linux/aer.h> 22 #include <linux/interrupt.h> 23 #include <linux/ethtool.h> 24 #include <linux/timer.h> 25 #include <linux/delay.h> 26 #include <linux/bitmap.h> 27 #include <linux/log2.h> 28 #include <linux/ip.h> 29 #include <linux/sctp.h> 30 #include <linux/ipv6.h> 31 #include <linux/if_bridge.h> 32 #include <linux/avf/virtchnl.h> 33 #include <net/ipv6.h> 34 #include "ice_devids.h" 35 #include "ice_type.h" 36 #include "ice_txrx.h" 37 #include "ice_dcb.h" 38 #include "ice_switch.h" 39 #include "ice_common.h" 40 #include "ice_sched.h" 41 #include "ice_virtchnl_pf.h" 42 #include "ice_sriov.h" 43 44 extern const char ice_drv_ver[]; 45 #define ICE_BAR0 0 46 #define ICE_REQ_DESC_MULTIPLE 32 47 #define ICE_MIN_NUM_DESC 64 48 #define ICE_MAX_NUM_DESC 8160 49 #define ICE_DFLT_MIN_RX_DESC 512 50 /* if the default number of Rx descriptors between ICE_MAX_NUM_DESC and the 51 * number of descriptors to fill up an entire page is greater than or equal to 52 * ICE_DFLT_MIN_RX_DESC set it based on page size, otherwise set it to 53 * ICE_DFLT_MIN_RX_DESC 54 */ 55 #define ICE_DFLT_NUM_RX_DESC \ 56 min_t(u16, ICE_MAX_NUM_DESC, \ 57 max_t(u16, ALIGN(PAGE_SIZE / sizeof(union ice_32byte_rx_desc), \ 58 ICE_REQ_DESC_MULTIPLE), \ 59 ICE_DFLT_MIN_RX_DESC)) 60 /* set default number of Tx descriptors to the minimum between ICE_MAX_NUM_DESC 61 * and the number of descriptors to fill up an entire page 62 */ 63 #define ICE_DFLT_NUM_TX_DESC min_t(u16, ICE_MAX_NUM_DESC, \ 64 ALIGN(PAGE_SIZE / \ 65 sizeof(struct ice_tx_desc), \ 66 ICE_REQ_DESC_MULTIPLE)) 67 68 #define ICE_DFLT_TRAFFIC_CLASS BIT(0) 69 #define ICE_INT_NAME_STR_LEN (IFNAMSIZ + 16) 70 #define ICE_ETHTOOL_FWVER_LEN 32 71 #define ICE_AQ_LEN 64 72 #define ICE_MBXQ_LEN 64 73 #define ICE_MIN_MSIX 2 74 #define ICE_NO_VSI 0xffff 75 #define ICE_MAX_TXQS 2048 76 #define ICE_MAX_RXQS 2048 77 #define ICE_VSI_MAP_CONTIG 0 78 #define ICE_VSI_MAP_SCATTER 1 79 #define ICE_MAX_SCATTER_TXQS 16 80 #define ICE_MAX_SCATTER_RXQS 16 81 #define ICE_Q_WAIT_RETRY_LIMIT 10 82 #define ICE_Q_WAIT_MAX_RETRY (5 * ICE_Q_WAIT_RETRY_LIMIT) 83 #define ICE_MAX_LG_RSS_QS 256 84 #define ICE_MAX_SMALL_RSS_QS 8 85 #define ICE_RES_VALID_BIT 0x8000 86 #define ICE_RES_MISC_VEC_ID (ICE_RES_VALID_BIT - 1) 87 #define ICE_INVAL_Q_INDEX 0xffff 88 #define ICE_INVAL_VFID 256 89 #define ICE_MAX_VF_COUNT 256 90 #define ICE_MAX_QS_PER_VF 256 91 #define ICE_MIN_QS_PER_VF 1 92 #define ICE_DFLT_QS_PER_VF 4 93 #define ICE_NONQ_VECS_VF 1 94 #define ICE_MAX_SCATTER_QS_PER_VF 16 95 #define ICE_MAX_BASE_QS_PER_VF 16 96 #define ICE_MAX_INTR_PER_VF 65 97 #define ICE_MIN_INTR_PER_VF (ICE_MIN_QS_PER_VF + 1) 98 #define ICE_DFLT_INTR_PER_VF (ICE_DFLT_QS_PER_VF + 1) 99 100 #define ICE_MAX_RESET_WAIT 20 101 102 #define ICE_VSIQF_HKEY_ARRAY_SIZE ((VSIQF_HKEY_MAX_INDEX + 1) * 4) 103 104 #define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 105 106 #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - \ 107 (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))) 108 109 #define ICE_UP_TABLE_TRANSLATE(val, i) \ 110 (((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \ 111 ICE_AQ_VSI_UP_TABLE_UP##i##_M) 112 113 #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i])) 114 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i])) 115 #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i])) 116 117 /* Macro for each VSI in a PF */ 118 #define ice_for_each_vsi(pf, i) \ 119 for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++) 120 121 /* Macros for each Tx/Rx ring in a VSI */ 122 #define ice_for_each_txq(vsi, i) \ 123 for ((i) = 0; (i) < (vsi)->num_txq; (i)++) 124 125 #define ice_for_each_rxq(vsi, i) \ 126 for ((i) = 0; (i) < (vsi)->num_rxq; (i)++) 127 128 /* Macros for each allocated Tx/Rx ring whether used or not in a VSI */ 129 #define ice_for_each_alloc_txq(vsi, i) \ 130 for ((i) = 0; (i) < (vsi)->alloc_txq; (i)++) 131 132 #define ice_for_each_alloc_rxq(vsi, i) \ 133 for ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++) 134 135 #define ice_for_each_q_vector(vsi, i) \ 136 for ((i) = 0; (i) < (vsi)->num_q_vectors; (i)++) 137 138 #define ICE_UCAST_PROMISC_BITS (ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX | \ 139 ICE_PROMISC_UCAST_RX | ICE_PROMISC_MCAST_RX) 140 141 #define ICE_UCAST_VLAN_PROMISC_BITS (ICE_PROMISC_UCAST_TX | \ 142 ICE_PROMISC_MCAST_TX | \ 143 ICE_PROMISC_UCAST_RX | \ 144 ICE_PROMISC_MCAST_RX | \ 145 ICE_PROMISC_VLAN_TX | \ 146 ICE_PROMISC_VLAN_RX) 147 148 #define ICE_MCAST_PROMISC_BITS (ICE_PROMISC_MCAST_TX | ICE_PROMISC_MCAST_RX) 149 150 #define ICE_MCAST_VLAN_PROMISC_BITS (ICE_PROMISC_MCAST_TX | \ 151 ICE_PROMISC_MCAST_RX | \ 152 ICE_PROMISC_VLAN_TX | \ 153 ICE_PROMISC_VLAN_RX) 154 155 struct ice_tc_info { 156 u16 qoffset; 157 u16 qcount_tx; 158 u16 qcount_rx; 159 u8 netdev_tc; 160 }; 161 162 struct ice_tc_cfg { 163 u8 numtc; /* Total number of enabled TCs */ 164 u8 ena_tc; /* Tx map */ 165 struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS]; 166 }; 167 168 struct ice_res_tracker { 169 u16 num_entries; 170 u16 end; 171 u16 list[1]; 172 }; 173 174 struct ice_qs_cfg { 175 struct mutex *qs_mutex; /* will be assigned to &pf->avail_q_mutex */ 176 unsigned long *pf_map; 177 unsigned long pf_map_size; 178 unsigned int q_count; 179 unsigned int scatter_count; 180 u16 *vsi_map; 181 u16 vsi_map_offset; 182 u8 mapping_mode; 183 }; 184 185 struct ice_sw { 186 struct ice_pf *pf; 187 u16 sw_id; /* switch ID for this switch */ 188 u16 bridge_mode; /* VEB/VEPA/Port Virtualizer */ 189 }; 190 191 enum ice_state { 192 __ICE_TESTING, 193 __ICE_DOWN, 194 __ICE_NEEDS_RESTART, 195 __ICE_PREPARED_FOR_RESET, /* set by driver when prepared */ 196 __ICE_RESET_OICR_RECV, /* set by driver after rcv reset OICR */ 197 __ICE_PFR_REQ, /* set by driver and peers */ 198 __ICE_CORER_REQ, /* set by driver and peers */ 199 __ICE_GLOBR_REQ, /* set by driver and peers */ 200 __ICE_CORER_RECV, /* set by OICR handler */ 201 __ICE_GLOBR_RECV, /* set by OICR handler */ 202 __ICE_EMPR_RECV, /* set by OICR handler */ 203 __ICE_SUSPENDED, /* set on module remove path */ 204 __ICE_RESET_FAILED, /* set by reset/rebuild */ 205 /* When checking for the PF to be in a nominal operating state, the 206 * bits that are grouped at the beginning of the list need to be 207 * checked. Bits occurring before __ICE_STATE_NOMINAL_CHECK_BITS will 208 * be checked. If you need to add a bit into consideration for nominal 209 * operating state, it must be added before 210 * __ICE_STATE_NOMINAL_CHECK_BITS. Do not move this entry's position 211 * without appropriate consideration. 212 */ 213 __ICE_STATE_NOMINAL_CHECK_BITS, 214 __ICE_ADMINQ_EVENT_PENDING, 215 __ICE_MAILBOXQ_EVENT_PENDING, 216 __ICE_MDD_EVENT_PENDING, 217 __ICE_VFLR_EVENT_PENDING, 218 __ICE_FLTR_OVERFLOW_PROMISC, 219 __ICE_VF_DIS, 220 __ICE_CFG_BUSY, 221 __ICE_SERVICE_SCHED, 222 __ICE_SERVICE_DIS, 223 __ICE_STATE_NBITS /* must be last */ 224 }; 225 226 enum ice_vsi_flags { 227 ICE_VSI_FLAG_UMAC_FLTR_CHANGED, 228 ICE_VSI_FLAG_MMAC_FLTR_CHANGED, 229 ICE_VSI_FLAG_VLAN_FLTR_CHANGED, 230 ICE_VSI_FLAG_PROMISC_CHANGED, 231 ICE_VSI_FLAG_NBITS /* must be last */ 232 }; 233 234 /* struct that defines a VSI, associated with a dev */ 235 struct ice_vsi { 236 struct net_device *netdev; 237 struct ice_sw *vsw; /* switch this VSI is on */ 238 struct ice_pf *back; /* back pointer to PF */ 239 struct ice_port_info *port_info; /* back pointer to port_info */ 240 struct ice_ring **rx_rings; /* Rx ring array */ 241 struct ice_ring **tx_rings; /* Tx ring array */ 242 struct ice_q_vector **q_vectors; /* q_vector array */ 243 244 irqreturn_t (*irq_handler)(int irq, void *data); 245 246 u64 tx_linearize; 247 DECLARE_BITMAP(state, __ICE_STATE_NBITS); 248 DECLARE_BITMAP(flags, ICE_VSI_FLAG_NBITS); 249 unsigned int current_netdev_flags; 250 u32 tx_restart; 251 u32 tx_busy; 252 u32 rx_buf_failed; 253 u32 rx_page_failed; 254 int num_q_vectors; 255 int base_vector; /* IRQ base for OS reserved vectors */ 256 enum ice_vsi_type type; 257 u16 vsi_num; /* HW (absolute) index of this VSI */ 258 u16 idx; /* software index in pf->vsi[] */ 259 260 /* Interrupt thresholds */ 261 u16 work_lmt; 262 263 s16 vf_id; /* VF ID for SR-IOV VSIs */ 264 265 u16 ethtype; /* Ethernet protocol for pause frame */ 266 267 /* RSS config */ 268 u16 rss_table_size; /* HW RSS table size */ 269 u16 rss_size; /* Allocated RSS queues */ 270 u8 *rss_hkey_user; /* User configured hash keys */ 271 u8 *rss_lut_user; /* User configured lookup table entries */ 272 u8 rss_lut_type; /* used to configure Get/Set RSS LUT AQ call */ 273 274 u16 max_frame; 275 u16 rx_buf_len; 276 277 struct ice_aqc_vsi_props info; /* VSI properties */ 278 279 /* VSI stats */ 280 struct rtnl_link_stats64 net_stats; 281 struct ice_eth_stats eth_stats; 282 struct ice_eth_stats eth_stats_prev; 283 284 struct list_head tmp_sync_list; /* MAC filters to be synced */ 285 struct list_head tmp_unsync_list; /* MAC filters to be unsynced */ 286 287 u8 irqs_ready:1; 288 u8 current_isup:1; /* Sync 'link up' logging */ 289 u8 stat_offsets_loaded:1; 290 u8 vlan_ena:1; 291 292 /* queue information */ 293 u8 tx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */ 294 u8 rx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */ 295 u16 txq_map[ICE_MAX_TXQS]; /* index in pf->avail_txqs */ 296 u16 rxq_map[ICE_MAX_RXQS]; /* index in pf->avail_rxqs */ 297 u16 alloc_txq; /* Allocated Tx queues */ 298 u16 num_txq; /* Used Tx queues */ 299 u16 alloc_rxq; /* Allocated Rx queues */ 300 u16 num_rxq; /* Used Rx queues */ 301 u16 num_rx_desc; 302 u16 num_tx_desc; 303 struct ice_tc_cfg tc_cfg; 304 } ____cacheline_internodealigned_in_smp; 305 306 /* struct that defines an interrupt vector */ 307 struct ice_q_vector { 308 struct ice_vsi *vsi; 309 310 u16 v_idx; /* index in the vsi->q_vector array. */ 311 u16 reg_idx; 312 u8 num_ring_rx; /* total number of Rx rings in vector */ 313 u8 num_ring_tx; /* total number of Tx rings in vector */ 314 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 315 /* in usecs, need to use ice_intrl_to_usecs_reg() before writing this 316 * value to the device 317 */ 318 u8 intrl; 319 320 struct napi_struct napi; 321 322 struct ice_ring_container rx; 323 struct ice_ring_container tx; 324 325 cpumask_t affinity_mask; 326 struct irq_affinity_notify affinity_notify; 327 328 char name[ICE_INT_NAME_STR_LEN]; 329 } ____cacheline_internodealigned_in_smp; 330 331 enum ice_pf_flags { 332 ICE_FLAG_MSIX_ENA, 333 ICE_FLAG_FLTR_SYNC, 334 ICE_FLAG_RSS_ENA, 335 ICE_FLAG_SRIOV_ENA, 336 ICE_FLAG_SRIOV_CAPABLE, 337 ICE_FLAG_DCB_CAPABLE, 338 ICE_FLAG_DCB_ENA, 339 ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA, 340 ICE_FLAG_ENABLE_FW_LLDP, 341 ICE_FLAG_ETHTOOL_CTXT, /* set when ethtool holds RTNL lock */ 342 ICE_PF_FLAGS_NBITS /* must be last */ 343 }; 344 345 struct ice_pf { 346 struct pci_dev *pdev; 347 348 /* OS reserved IRQ details */ 349 struct msix_entry *msix_entries; 350 struct ice_res_tracker *irq_tracker; 351 /* First MSIX vector used by SR-IOV VFs. Calculated by subtracting the 352 * number of MSIX vectors needed for all SR-IOV VFs from the number of 353 * MSIX vectors allowed on this PF. 354 */ 355 u16 sriov_base_vector; 356 357 struct ice_vsi **vsi; /* VSIs created by the driver */ 358 struct ice_sw *first_sw; /* first switch created by firmware */ 359 /* Virtchnl/SR-IOV config info */ 360 struct ice_vf *vf; 361 int num_alloc_vfs; /* actual number of VFs allocated */ 362 u16 num_vfs_supported; /* num VFs supported for this PF */ 363 u16 num_vf_qps; /* num queue pairs per VF */ 364 u16 num_vf_msix; /* num vectors per VF */ 365 DECLARE_BITMAP(state, __ICE_STATE_NBITS); 366 DECLARE_BITMAP(avail_txqs, ICE_MAX_TXQS); 367 DECLARE_BITMAP(avail_rxqs, ICE_MAX_RXQS); 368 DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS); 369 unsigned long serv_tmr_period; 370 unsigned long serv_tmr_prev; 371 struct timer_list serv_tmr; 372 struct work_struct serv_task; 373 struct mutex avail_q_mutex; /* protects access to avail_[rx|tx]qs */ 374 struct mutex sw_mutex; /* lock for protecting VSI alloc flow */ 375 u32 msg_enable; 376 u32 hw_csum_rx_error; 377 u32 oicr_idx; /* Other interrupt cause MSIX vector index */ 378 u32 num_avail_sw_msix; /* remaining MSIX SW vectors left unclaimed */ 379 u32 num_lan_msix; /* Total MSIX vectors for base driver */ 380 u16 num_lan_tx; /* num LAN Tx queues setup */ 381 u16 num_lan_rx; /* num LAN Rx queues setup */ 382 u16 q_left_tx; /* remaining num Tx queues left unclaimed */ 383 u16 q_left_rx; /* remaining num Rx queues left unclaimed */ 384 u16 next_vsi; /* Next free slot in pf->vsi[] - 0-based! */ 385 u16 num_alloc_vsi; 386 u16 corer_count; /* Core reset count */ 387 u16 globr_count; /* Global reset count */ 388 u16 empr_count; /* EMP reset count */ 389 u16 pfr_count; /* PF reset count */ 390 391 struct ice_hw_port_stats stats; 392 struct ice_hw_port_stats stats_prev; 393 struct ice_hw hw; 394 u8 stat_prev_loaded:1; /* has previous stats been loaded */ 395 #ifdef CONFIG_DCB 396 u16 dcbx_cap; 397 #endif /* CONFIG_DCB */ 398 u32 tx_timeout_count; 399 unsigned long tx_timeout_last_recovery; 400 u32 tx_timeout_recovery_level; 401 char int_name[ICE_INT_NAME_STR_LEN]; 402 u32 sw_int_count; 403 }; 404 405 struct ice_netdev_priv { 406 struct ice_vsi *vsi; 407 }; 408 409 /** 410 * ice_irq_dynamic_ena - Enable default interrupt generation settings 411 * @hw: pointer to HW struct 412 * @vsi: pointer to VSI struct, can be NULL 413 * @q_vector: pointer to q_vector, can be NULL 414 */ 415 static inline void 416 ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi, 417 struct ice_q_vector *q_vector) 418 { 419 u32 vector = (vsi && q_vector) ? q_vector->reg_idx : 420 ((struct ice_pf *)hw->back)->oicr_idx; 421 int itr = ICE_ITR_NONE; 422 u32 val; 423 424 /* clear the PBA here, as this function is meant to clean out all 425 * previous interrupts and enable the interrupt 426 */ 427 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 428 (itr << GLINT_DYN_CTL_ITR_INDX_S); 429 if (vsi) 430 if (test_bit(__ICE_DOWN, vsi->state)) 431 return; 432 wr32(hw, GLINT_DYN_CTL(vector), val); 433 } 434 435 /** 436 * ice_find_vsi_by_type - Find and return VSI of a given type 437 * @pf: PF to search for VSI 438 * @type: Value indicating type of VSI we are looking for 439 */ 440 static inline struct ice_vsi * 441 ice_find_vsi_by_type(struct ice_pf *pf, enum ice_vsi_type type) 442 { 443 int i; 444 445 for (i = 0; i < pf->num_alloc_vsi; i++) { 446 struct ice_vsi *vsi = pf->vsi[i]; 447 448 if (vsi && vsi->type == type) 449 return vsi; 450 } 451 452 return NULL; 453 } 454 455 int ice_vsi_setup_tx_rings(struct ice_vsi *vsi); 456 int ice_vsi_setup_rx_rings(struct ice_vsi *vsi); 457 void ice_set_ethtool_ops(struct net_device *netdev); 458 int ice_up(struct ice_vsi *vsi); 459 int ice_down(struct ice_vsi *vsi); 460 int ice_vsi_cfg(struct ice_vsi *vsi); 461 struct ice_vsi *ice_lb_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi); 462 int ice_set_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 463 int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 464 void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size); 465 void ice_print_link_msg(struct ice_vsi *vsi, bool isup); 466 #ifdef CONFIG_DCB 467 int ice_pf_ena_all_vsi(struct ice_pf *pf, bool locked); 468 void ice_pf_dis_all_vsi(struct ice_pf *pf, bool locked); 469 #endif /* CONFIG_DCB */ 470 int ice_open(struct net_device *netdev); 471 int ice_stop(struct net_device *netdev); 472 473 #endif /* _ICE_H_ */ 474