1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_H_ 5 #define _ICE_H_ 6 7 #include <linux/types.h> 8 #include <linux/errno.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/firmware.h> 12 #include <linux/netdevice.h> 13 #include <linux/compiler.h> 14 #include <linux/etherdevice.h> 15 #include <linux/skbuff.h> 16 #include <linux/cpumask.h> 17 #include <linux/rtnetlink.h> 18 #include <linux/if_vlan.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/pci.h> 21 #include <linux/workqueue.h> 22 #include <linux/wait.h> 23 #include <linux/aer.h> 24 #include <linux/interrupt.h> 25 #include <linux/ethtool.h> 26 #include <linux/timer.h> 27 #include <linux/delay.h> 28 #include <linux/bitmap.h> 29 #include <linux/log2.h> 30 #include <linux/ip.h> 31 #include <linux/sctp.h> 32 #include <linux/ipv6.h> 33 #include <linux/pkt_sched.h> 34 #include <linux/if_bridge.h> 35 #include <linux/ctype.h> 36 #include <linux/bpf.h> 37 #include <linux/avf/virtchnl.h> 38 #include <linux/cpu_rmap.h> 39 #include <net/devlink.h> 40 #include <net/ipv6.h> 41 #include <net/xdp_sock.h> 42 #include <net/xdp_sock_drv.h> 43 #include <net/geneve.h> 44 #include <net/gre.h> 45 #include <net/udp_tunnel.h> 46 #include <net/vxlan.h> 47 #include "ice_devids.h" 48 #include "ice_type.h" 49 #include "ice_txrx.h" 50 #include "ice_dcb.h" 51 #include "ice_switch.h" 52 #include "ice_common.h" 53 #include "ice_sched.h" 54 #include "ice_virtchnl_pf.h" 55 #include "ice_sriov.h" 56 #include "ice_fdir.h" 57 #include "ice_xsk.h" 58 #include "ice_arfs.h" 59 #include "ice_lag.h" 60 61 #define ICE_BAR0 0 62 #define ICE_REQ_DESC_MULTIPLE 32 63 #define ICE_MIN_NUM_DESC 64 64 #define ICE_MAX_NUM_DESC 8160 65 #define ICE_DFLT_MIN_RX_DESC 512 66 #define ICE_DFLT_NUM_TX_DESC 256 67 #define ICE_DFLT_NUM_RX_DESC 2048 68 69 #define ICE_DFLT_TRAFFIC_CLASS BIT(0) 70 #define ICE_INT_NAME_STR_LEN (IFNAMSIZ + 16) 71 #define ICE_AQ_LEN 64 72 #define ICE_MBXSQ_LEN 64 73 #define ICE_MIN_LAN_TXRX_MSIX 1 74 #define ICE_MIN_LAN_OICR_MSIX 1 75 #define ICE_MIN_MSIX (ICE_MIN_LAN_TXRX_MSIX + ICE_MIN_LAN_OICR_MSIX) 76 #define ICE_FDIR_MSIX 2 77 #define ICE_NO_VSI 0xffff 78 #define ICE_VSI_MAP_CONTIG 0 79 #define ICE_VSI_MAP_SCATTER 1 80 #define ICE_MAX_SCATTER_TXQS 16 81 #define ICE_MAX_SCATTER_RXQS 16 82 #define ICE_Q_WAIT_RETRY_LIMIT 10 83 #define ICE_Q_WAIT_MAX_RETRY (5 * ICE_Q_WAIT_RETRY_LIMIT) 84 #define ICE_MAX_LG_RSS_QS 256 85 #define ICE_RES_VALID_BIT 0x8000 86 #define ICE_RES_MISC_VEC_ID (ICE_RES_VALID_BIT - 1) 87 /* All VF control VSIs share the same IRQ, so assign a unique ID for them */ 88 #define ICE_RES_VF_CTRL_VEC_ID (ICE_RES_MISC_VEC_ID - 1) 89 #define ICE_INVAL_Q_INDEX 0xffff 90 #define ICE_INVAL_VFID 256 91 92 #define ICE_MAX_RESET_WAIT 20 93 94 #define ICE_VSIQF_HKEY_ARRAY_SIZE ((VSIQF_HKEY_MAX_INDEX + 1) * 4) 95 96 #define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 97 98 #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - ICE_ETH_PKT_HDR_PAD) 99 100 #define ICE_UP_TABLE_TRANSLATE(val, i) \ 101 (((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \ 102 ICE_AQ_VSI_UP_TABLE_UP##i##_M) 103 104 #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i])) 105 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i])) 106 #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i])) 107 #define ICE_TX_FDIRDESC(R, i) (&(((struct ice_fltr_desc *)((R)->desc))[i])) 108 109 /* Macro for each VSI in a PF */ 110 #define ice_for_each_vsi(pf, i) \ 111 for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++) 112 113 /* Macros for each Tx/Rx ring in a VSI */ 114 #define ice_for_each_txq(vsi, i) \ 115 for ((i) = 0; (i) < (vsi)->num_txq; (i)++) 116 117 #define ice_for_each_rxq(vsi, i) \ 118 for ((i) = 0; (i) < (vsi)->num_rxq; (i)++) 119 120 /* Macros for each allocated Tx/Rx ring whether used or not in a VSI */ 121 #define ice_for_each_alloc_txq(vsi, i) \ 122 for ((i) = 0; (i) < (vsi)->alloc_txq; (i)++) 123 124 #define ice_for_each_alloc_rxq(vsi, i) \ 125 for ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++) 126 127 #define ice_for_each_q_vector(vsi, i) \ 128 for ((i) = 0; (i) < (vsi)->num_q_vectors; (i)++) 129 130 #define ICE_UCAST_PROMISC_BITS (ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX | \ 131 ICE_PROMISC_UCAST_RX | ICE_PROMISC_MCAST_RX) 132 133 #define ICE_UCAST_VLAN_PROMISC_BITS (ICE_PROMISC_UCAST_TX | \ 134 ICE_PROMISC_MCAST_TX | \ 135 ICE_PROMISC_UCAST_RX | \ 136 ICE_PROMISC_MCAST_RX | \ 137 ICE_PROMISC_VLAN_TX | \ 138 ICE_PROMISC_VLAN_RX) 139 140 #define ICE_MCAST_PROMISC_BITS (ICE_PROMISC_MCAST_TX | ICE_PROMISC_MCAST_RX) 141 142 #define ICE_MCAST_VLAN_PROMISC_BITS (ICE_PROMISC_MCAST_TX | \ 143 ICE_PROMISC_MCAST_RX | \ 144 ICE_PROMISC_VLAN_TX | \ 145 ICE_PROMISC_VLAN_RX) 146 147 #define ice_pf_to_dev(pf) (&((pf)->pdev->dev)) 148 149 struct ice_txq_meta { 150 u32 q_teid; /* Tx-scheduler element identifier */ 151 u16 q_id; /* Entry in VSI's txq_map bitmap */ 152 u16 q_handle; /* Relative index of Tx queue within TC */ 153 u16 vsi_idx; /* VSI index that Tx queue belongs to */ 154 u8 tc; /* TC number that Tx queue belongs to */ 155 }; 156 157 struct ice_tc_info { 158 u16 qoffset; 159 u16 qcount_tx; 160 u16 qcount_rx; 161 u8 netdev_tc; 162 }; 163 164 struct ice_tc_cfg { 165 u8 numtc; /* Total number of enabled TCs */ 166 u8 ena_tc; /* Tx map */ 167 struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS]; 168 }; 169 170 struct ice_res_tracker { 171 u16 num_entries; 172 u16 end; 173 u16 list[]; 174 }; 175 176 struct ice_qs_cfg { 177 struct mutex *qs_mutex; /* will be assigned to &pf->avail_q_mutex */ 178 unsigned long *pf_map; 179 unsigned long pf_map_size; 180 unsigned int q_count; 181 unsigned int scatter_count; 182 u16 *vsi_map; 183 u16 vsi_map_offset; 184 u8 mapping_mode; 185 }; 186 187 struct ice_sw { 188 struct ice_pf *pf; 189 u16 sw_id; /* switch ID for this switch */ 190 u16 bridge_mode; /* VEB/VEPA/Port Virtualizer */ 191 struct ice_vsi *dflt_vsi; /* default VSI for this switch */ 192 u8 dflt_vsi_ena:1; /* true if above dflt_vsi is enabled */ 193 }; 194 195 enum ice_state { 196 __ICE_TESTING, 197 __ICE_DOWN, 198 __ICE_NEEDS_RESTART, 199 __ICE_PREPARED_FOR_RESET, /* set by driver when prepared */ 200 __ICE_RESET_OICR_RECV, /* set by driver after rcv reset OICR */ 201 __ICE_DCBNL_DEVRESET, /* set by dcbnl devreset */ 202 __ICE_PFR_REQ, /* set by driver and peers */ 203 __ICE_CORER_REQ, /* set by driver and peers */ 204 __ICE_GLOBR_REQ, /* set by driver and peers */ 205 __ICE_CORER_RECV, /* set by OICR handler */ 206 __ICE_GLOBR_RECV, /* set by OICR handler */ 207 __ICE_EMPR_RECV, /* set by OICR handler */ 208 __ICE_SUSPENDED, /* set on module remove path */ 209 __ICE_RESET_FAILED, /* set by reset/rebuild */ 210 /* When checking for the PF to be in a nominal operating state, the 211 * bits that are grouped at the beginning of the list need to be 212 * checked. Bits occurring before __ICE_STATE_NOMINAL_CHECK_BITS will 213 * be checked. If you need to add a bit into consideration for nominal 214 * operating state, it must be added before 215 * __ICE_STATE_NOMINAL_CHECK_BITS. Do not move this entry's position 216 * without appropriate consideration. 217 */ 218 __ICE_STATE_NOMINAL_CHECK_BITS, 219 __ICE_ADMINQ_EVENT_PENDING, 220 __ICE_MAILBOXQ_EVENT_PENDING, 221 __ICE_MDD_EVENT_PENDING, 222 __ICE_VFLR_EVENT_PENDING, 223 __ICE_FLTR_OVERFLOW_PROMISC, 224 __ICE_VF_DIS, 225 __ICE_CFG_BUSY, 226 __ICE_SERVICE_SCHED, 227 __ICE_SERVICE_DIS, 228 __ICE_FD_FLUSH_REQ, 229 __ICE_OICR_INTR_DIS, /* Global OICR interrupt disabled */ 230 __ICE_MDD_VF_PRINT_PENDING, /* set when MDD event handle */ 231 __ICE_VF_RESETS_DISABLED, /* disable resets during ice_remove */ 232 __ICE_LINK_DEFAULT_OVERRIDE_PENDING, 233 __ICE_PHY_INIT_COMPLETE, 234 __ICE_FD_VF_FLUSH_CTX, /* set at FD Rx IRQ or timeout */ 235 __ICE_STATE_NBITS /* must be last */ 236 }; 237 238 enum ice_vsi_flags { 239 ICE_VSI_FLAG_UMAC_FLTR_CHANGED, 240 ICE_VSI_FLAG_MMAC_FLTR_CHANGED, 241 ICE_VSI_FLAG_VLAN_FLTR_CHANGED, 242 ICE_VSI_FLAG_PROMISC_CHANGED, 243 ICE_VSI_FLAG_NBITS /* must be last */ 244 }; 245 246 /* struct that defines a VSI, associated with a dev */ 247 struct ice_vsi { 248 struct net_device *netdev; 249 struct ice_sw *vsw; /* switch this VSI is on */ 250 struct ice_pf *back; /* back pointer to PF */ 251 struct ice_port_info *port_info; /* back pointer to port_info */ 252 struct ice_ring **rx_rings; /* Rx ring array */ 253 struct ice_ring **tx_rings; /* Tx ring array */ 254 struct ice_q_vector **q_vectors; /* q_vector array */ 255 256 irqreturn_t (*irq_handler)(int irq, void *data); 257 258 u64 tx_linearize; 259 DECLARE_BITMAP(state, __ICE_STATE_NBITS); 260 DECLARE_BITMAP(flags, ICE_VSI_FLAG_NBITS); 261 unsigned int current_netdev_flags; 262 u32 tx_restart; 263 u32 tx_busy; 264 u32 rx_buf_failed; 265 u32 rx_page_failed; 266 u32 rx_gro_dropped; 267 u16 num_q_vectors; 268 u16 base_vector; /* IRQ base for OS reserved vectors */ 269 enum ice_vsi_type type; 270 u16 vsi_num; /* HW (absolute) index of this VSI */ 271 u16 idx; /* software index in pf->vsi[] */ 272 273 s16 vf_id; /* VF ID for SR-IOV VSIs */ 274 275 u16 ethtype; /* Ethernet protocol for pause frame */ 276 u16 num_gfltr; 277 u16 num_bfltr; 278 279 /* RSS config */ 280 u16 rss_table_size; /* HW RSS table size */ 281 u16 rss_size; /* Allocated RSS queues */ 282 u8 *rss_hkey_user; /* User configured hash keys */ 283 u8 *rss_lut_user; /* User configured lookup table entries */ 284 u8 rss_lut_type; /* used to configure Get/Set RSS LUT AQ call */ 285 286 /* aRFS members only allocated for the PF VSI */ 287 #define ICE_MAX_ARFS_LIST 1024 288 #define ICE_ARFS_LST_MASK (ICE_MAX_ARFS_LIST - 1) 289 struct hlist_head *arfs_fltr_list; 290 struct ice_arfs_active_fltr_cntrs *arfs_fltr_cntrs; 291 spinlock_t arfs_lock; /* protects aRFS hash table and filter state */ 292 atomic_t *arfs_last_fltr_id; 293 294 /* devlink port data */ 295 struct devlink_port devlink_port; 296 bool devlink_port_registered; 297 298 u16 max_frame; 299 u16 rx_buf_len; 300 301 struct ice_aqc_vsi_props info; /* VSI properties */ 302 303 /* VSI stats */ 304 struct rtnl_link_stats64 net_stats; 305 struct ice_eth_stats eth_stats; 306 struct ice_eth_stats eth_stats_prev; 307 308 struct list_head tmp_sync_list; /* MAC filters to be synced */ 309 struct list_head tmp_unsync_list; /* MAC filters to be unsynced */ 310 311 u8 irqs_ready:1; 312 u8 current_isup:1; /* Sync 'link up' logging */ 313 u8 stat_offsets_loaded:1; 314 u16 num_vlan; 315 316 /* queue information */ 317 u8 tx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */ 318 u8 rx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */ 319 u16 *txq_map; /* index in pf->avail_txqs */ 320 u16 *rxq_map; /* index in pf->avail_rxqs */ 321 u16 alloc_txq; /* Allocated Tx queues */ 322 u16 num_txq; /* Used Tx queues */ 323 u16 alloc_rxq; /* Allocated Rx queues */ 324 u16 num_rxq; /* Used Rx queues */ 325 u16 req_txq; /* User requested Tx queues */ 326 u16 req_rxq; /* User requested Rx queues */ 327 u16 num_rx_desc; 328 u16 num_tx_desc; 329 struct ice_tc_cfg tc_cfg; 330 struct bpf_prog *xdp_prog; 331 struct ice_ring **xdp_rings; /* XDP ring array */ 332 u16 num_xdp_txq; /* Used XDP queues */ 333 u8 xdp_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */ 334 335 /* setup back reference, to which aggregator node this VSI 336 * corresponds to 337 */ 338 struct ice_agg_node *agg_node; 339 } ____cacheline_internodealigned_in_smp; 340 341 /* struct that defines an interrupt vector */ 342 struct ice_q_vector { 343 struct ice_vsi *vsi; 344 345 u16 v_idx; /* index in the vsi->q_vector array. */ 346 u16 reg_idx; 347 u8 num_ring_rx; /* total number of Rx rings in vector */ 348 u8 num_ring_tx; /* total number of Tx rings in vector */ 349 u8 itr_countdown; /* when 0 should adjust adaptive ITR */ 350 /* in usecs, need to use ice_intrl_to_usecs_reg() before writing this 351 * value to the device 352 */ 353 u8 intrl; 354 355 struct napi_struct napi; 356 357 struct ice_ring_container rx; 358 struct ice_ring_container tx; 359 360 cpumask_t affinity_mask; 361 struct irq_affinity_notify affinity_notify; 362 363 char name[ICE_INT_NAME_STR_LEN]; 364 } ____cacheline_internodealigned_in_smp; 365 366 enum ice_pf_flags { 367 ICE_FLAG_FLTR_SYNC, 368 ICE_FLAG_RSS_ENA, 369 ICE_FLAG_SRIOV_ENA, 370 ICE_FLAG_SRIOV_CAPABLE, 371 ICE_FLAG_DCB_CAPABLE, 372 ICE_FLAG_DCB_ENA, 373 ICE_FLAG_FD_ENA, 374 ICE_FLAG_ADV_FEATURES, 375 ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA, 376 ICE_FLAG_TOTAL_PORT_SHUTDOWN_ENA, 377 ICE_FLAG_NO_MEDIA, 378 ICE_FLAG_FW_LLDP_AGENT, 379 ICE_FLAG_ETHTOOL_CTXT, /* set when ethtool holds RTNL lock */ 380 ICE_FLAG_LEGACY_RX, 381 ICE_FLAG_VF_TRUE_PROMISC_ENA, 382 ICE_FLAG_MDD_AUTO_RESET_VF, 383 ICE_FLAG_LINK_LENIENT_MODE_ENA, 384 ICE_PF_FLAGS_NBITS /* must be last */ 385 }; 386 387 struct ice_agg_node { 388 u32 agg_id; 389 #define ICE_MAX_VSIS_IN_AGG_NODE 64 390 u32 num_vsis; 391 u8 valid; 392 }; 393 394 struct ice_pf { 395 struct pci_dev *pdev; 396 397 struct devlink_region *nvm_region; 398 struct devlink_region *devcaps_region; 399 400 /* OS reserved IRQ details */ 401 struct msix_entry *msix_entries; 402 struct ice_res_tracker *irq_tracker; 403 /* First MSIX vector used by SR-IOV VFs. Calculated by subtracting the 404 * number of MSIX vectors needed for all SR-IOV VFs from the number of 405 * MSIX vectors allowed on this PF. 406 */ 407 u16 sriov_base_vector; 408 409 u16 ctrl_vsi_idx; /* control VSI index in pf->vsi array */ 410 411 struct ice_vsi **vsi; /* VSIs created by the driver */ 412 struct ice_sw *first_sw; /* first switch created by firmware */ 413 /* Virtchnl/SR-IOV config info */ 414 struct ice_vf *vf; 415 u16 num_alloc_vfs; /* actual number of VFs allocated */ 416 u16 num_vfs_supported; /* num VFs supported for this PF */ 417 u16 num_qps_per_vf; 418 u16 num_msix_per_vf; 419 /* used to ratelimit the MDD event logging */ 420 unsigned long last_printed_mdd_jiffies; 421 DECLARE_BITMAP(state, __ICE_STATE_NBITS); 422 DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS); 423 unsigned long *avail_txqs; /* bitmap to track PF Tx queue usage */ 424 unsigned long *avail_rxqs; /* bitmap to track PF Rx queue usage */ 425 unsigned long serv_tmr_period; 426 unsigned long serv_tmr_prev; 427 struct timer_list serv_tmr; 428 struct work_struct serv_task; 429 struct mutex avail_q_mutex; /* protects access to avail_[rx|tx]qs */ 430 struct mutex sw_mutex; /* lock for protecting VSI alloc flow */ 431 struct mutex tc_mutex; /* lock to protect TC changes */ 432 u32 msg_enable; 433 434 /* spinlock to protect the AdminQ wait list */ 435 spinlock_t aq_wait_lock; 436 struct hlist_head aq_wait_list; 437 wait_queue_head_t aq_wait_queue; 438 439 u32 hw_csum_rx_error; 440 u16 oicr_idx; /* Other interrupt cause MSIX vector index */ 441 u16 num_avail_sw_msix; /* remaining MSIX SW vectors left unclaimed */ 442 u16 max_pf_txqs; /* Total Tx queues PF wide */ 443 u16 max_pf_rxqs; /* Total Rx queues PF wide */ 444 u16 num_lan_msix; /* Total MSIX vectors for base driver */ 445 u16 num_lan_tx; /* num LAN Tx queues setup */ 446 u16 num_lan_rx; /* num LAN Rx queues setup */ 447 u16 next_vsi; /* Next free slot in pf->vsi[] - 0-based! */ 448 u16 num_alloc_vsi; 449 u16 corer_count; /* Core reset count */ 450 u16 globr_count; /* Global reset count */ 451 u16 empr_count; /* EMP reset count */ 452 u16 pfr_count; /* PF reset count */ 453 454 u8 wol_ena : 1; /* software state of WoL */ 455 u32 wakeup_reason; /* last wakeup reason */ 456 struct ice_hw_port_stats stats; 457 struct ice_hw_port_stats stats_prev; 458 struct ice_hw hw; 459 u8 stat_prev_loaded:1; /* has previous stats been loaded */ 460 u16 dcbx_cap; 461 u32 tx_timeout_count; 462 unsigned long tx_timeout_last_recovery; 463 u32 tx_timeout_recovery_level; 464 char int_name[ICE_INT_NAME_STR_LEN]; 465 u32 sw_int_count; 466 467 __le64 nvm_phy_type_lo; /* NVM PHY type low */ 468 __le64 nvm_phy_type_hi; /* NVM PHY type high */ 469 struct ice_link_default_override_tlv link_dflt_override; 470 struct ice_lag *lag; /* Link Aggregation information */ 471 472 #define ICE_INVALID_AGG_NODE_ID 0 473 #define ICE_PF_AGG_NODE_ID_START 1 474 #define ICE_MAX_PF_AGG_NODES 32 475 struct ice_agg_node pf_agg_node[ICE_MAX_PF_AGG_NODES]; 476 #define ICE_VF_AGG_NODE_ID_START 65 477 #define ICE_MAX_VF_AGG_NODES 32 478 struct ice_agg_node vf_agg_node[ICE_MAX_VF_AGG_NODES]; 479 }; 480 481 struct ice_netdev_priv { 482 struct ice_vsi *vsi; 483 }; 484 485 /** 486 * ice_irq_dynamic_ena - Enable default interrupt generation settings 487 * @hw: pointer to HW struct 488 * @vsi: pointer to VSI struct, can be NULL 489 * @q_vector: pointer to q_vector, can be NULL 490 */ 491 static inline void 492 ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi, 493 struct ice_q_vector *q_vector) 494 { 495 u32 vector = (vsi && q_vector) ? q_vector->reg_idx : 496 ((struct ice_pf *)hw->back)->oicr_idx; 497 int itr = ICE_ITR_NONE; 498 u32 val; 499 500 /* clear the PBA here, as this function is meant to clean out all 501 * previous interrupts and enable the interrupt 502 */ 503 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 504 (itr << GLINT_DYN_CTL_ITR_INDX_S); 505 if (vsi) 506 if (test_bit(__ICE_DOWN, vsi->state)) 507 return; 508 wr32(hw, GLINT_DYN_CTL(vector), val); 509 } 510 511 /** 512 * ice_netdev_to_pf - Retrieve the PF struct associated with a netdev 513 * @netdev: pointer to the netdev struct 514 */ 515 static inline struct ice_pf *ice_netdev_to_pf(struct net_device *netdev) 516 { 517 struct ice_netdev_priv *np = netdev_priv(netdev); 518 519 return np->vsi->back; 520 } 521 522 static inline bool ice_is_xdp_ena_vsi(struct ice_vsi *vsi) 523 { 524 return !!vsi->xdp_prog; 525 } 526 527 static inline void ice_set_ring_xdp(struct ice_ring *ring) 528 { 529 ring->flags |= ICE_TX_FLAGS_RING_XDP; 530 } 531 532 /** 533 * ice_xsk_pool - get XSK buffer pool bound to a ring 534 * @ring: ring to use 535 * 536 * Returns a pointer to xdp_umem structure if there is a buffer pool present, 537 * NULL otherwise. 538 */ 539 static inline struct xsk_buff_pool *ice_xsk_pool(struct ice_ring *ring) 540 { 541 u16 qid = ring->q_index; 542 543 if (ice_ring_is_xdp(ring)) 544 qid -= ring->vsi->num_xdp_txq; 545 546 if (!ice_is_xdp_ena_vsi(ring->vsi)) 547 return NULL; 548 549 return xsk_get_pool_from_qid(ring->vsi->netdev, qid); 550 } 551 552 /** 553 * ice_get_main_vsi - Get the PF VSI 554 * @pf: PF instance 555 * 556 * returns pf->vsi[0], which by definition is the PF VSI 557 */ 558 static inline struct ice_vsi *ice_get_main_vsi(struct ice_pf *pf) 559 { 560 if (pf->vsi) 561 return pf->vsi[0]; 562 563 return NULL; 564 } 565 566 /** 567 * ice_get_ctrl_vsi - Get the control VSI 568 * @pf: PF instance 569 */ 570 static inline struct ice_vsi *ice_get_ctrl_vsi(struct ice_pf *pf) 571 { 572 /* if pf->ctrl_vsi_idx is ICE_NO_VSI, control VSI was not set up */ 573 if (!pf->vsi || pf->ctrl_vsi_idx == ICE_NO_VSI) 574 return NULL; 575 576 return pf->vsi[pf->ctrl_vsi_idx]; 577 } 578 579 /** 580 * ice_set_sriov_cap - enable SRIOV in PF flags 581 * @pf: PF struct 582 */ 583 static inline void ice_set_sriov_cap(struct ice_pf *pf) 584 { 585 if (pf->hw.func_caps.common_cap.sr_iov_1_1) 586 set_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags); 587 } 588 589 /** 590 * ice_clear_sriov_cap - disable SRIOV in PF flags 591 * @pf: PF struct 592 */ 593 static inline void ice_clear_sriov_cap(struct ice_pf *pf) 594 { 595 clear_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags); 596 } 597 598 #define ICE_FD_STAT_CTR_BLOCK_COUNT 256 599 #define ICE_FD_STAT_PF_IDX(base_idx) \ 600 ((base_idx) * ICE_FD_STAT_CTR_BLOCK_COUNT) 601 #define ICE_FD_SB_STAT_IDX(base_idx) ICE_FD_STAT_PF_IDX(base_idx) 602 603 bool netif_is_ice(struct net_device *dev); 604 int ice_vsi_setup_tx_rings(struct ice_vsi *vsi); 605 int ice_vsi_setup_rx_rings(struct ice_vsi *vsi); 606 int ice_vsi_open_ctrl(struct ice_vsi *vsi); 607 void ice_set_ethtool_ops(struct net_device *netdev); 608 void ice_set_ethtool_safe_mode_ops(struct net_device *netdev); 609 u16 ice_get_avail_txq_count(struct ice_pf *pf); 610 u16 ice_get_avail_rxq_count(struct ice_pf *pf); 611 int ice_vsi_recfg_qs(struct ice_vsi *vsi, int new_rx, int new_tx); 612 void ice_update_vsi_stats(struct ice_vsi *vsi); 613 void ice_update_pf_stats(struct ice_pf *pf); 614 int ice_up(struct ice_vsi *vsi); 615 int ice_down(struct ice_vsi *vsi); 616 int ice_vsi_cfg(struct ice_vsi *vsi); 617 struct ice_vsi *ice_lb_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi); 618 int ice_prepare_xdp_rings(struct ice_vsi *vsi, struct bpf_prog *prog); 619 int ice_destroy_xdp_rings(struct ice_vsi *vsi); 620 int 621 ice_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames, 622 u32 flags); 623 int ice_set_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 624 int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size); 625 void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size); 626 int ice_schedule_reset(struct ice_pf *pf, enum ice_reset_req reset); 627 void ice_print_link_msg(struct ice_vsi *vsi, bool isup); 628 const char *ice_stat_str(enum ice_status stat_err); 629 const char *ice_aq_str(enum ice_aq_err aq_err); 630 bool ice_is_wol_supported(struct ice_pf *pf); 631 int 632 ice_fdir_write_fltr(struct ice_pf *pf, struct ice_fdir_fltr *input, bool add, 633 bool is_tun); 634 void ice_vsi_manage_fdir(struct ice_vsi *vsi, bool ena); 635 int ice_add_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd); 636 int ice_del_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd); 637 int ice_get_ethtool_fdir_entry(struct ice_hw *hw, struct ethtool_rxnfc *cmd); 638 int 639 ice_get_fdir_fltr_ids(struct ice_hw *hw, struct ethtool_rxnfc *cmd, 640 u32 *rule_locs); 641 void ice_fdir_release_flows(struct ice_hw *hw); 642 void ice_fdir_replay_flows(struct ice_hw *hw); 643 void ice_fdir_replay_fltrs(struct ice_pf *pf); 644 int ice_fdir_create_dflt_rules(struct ice_pf *pf); 645 int ice_aq_wait_for_event(struct ice_pf *pf, u16 opcode, unsigned long timeout, 646 struct ice_rq_event_info *event); 647 int ice_open(struct net_device *netdev); 648 int ice_stop(struct net_device *netdev); 649 void ice_service_task_schedule(struct ice_pf *pf); 650 651 #endif /* _ICE_H_ */ 652