1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3 
4 #include <linux/prefetch.h>
5 
6 #include "iavf.h"
7 #include "iavf_trace.h"
8 #include "iavf_prototype.h"
9 
10 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
11 				u32 td_tag)
12 {
13 	return cpu_to_le64(IAVF_TX_DESC_DTYPE_DATA |
14 			   ((u64)td_cmd  << IAVF_TXD_QW1_CMD_SHIFT) |
15 			   ((u64)td_offset << IAVF_TXD_QW1_OFFSET_SHIFT) |
16 			   ((u64)size  << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
17 			   ((u64)td_tag  << IAVF_TXD_QW1_L2TAG1_SHIFT));
18 }
19 
20 #define IAVF_TXD_CMD (IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_RS)
21 
22 /**
23  * iavf_unmap_and_free_tx_resource - Release a Tx buffer
24  * @ring:      the ring that owns the buffer
25  * @tx_buffer: the buffer to free
26  **/
27 static void iavf_unmap_and_free_tx_resource(struct iavf_ring *ring,
28 					    struct iavf_tx_buffer *tx_buffer)
29 {
30 	if (tx_buffer->skb) {
31 		if (tx_buffer->tx_flags & IAVF_TX_FLAGS_FD_SB)
32 			kfree(tx_buffer->raw_buf);
33 		else
34 			dev_kfree_skb_any(tx_buffer->skb);
35 		if (dma_unmap_len(tx_buffer, len))
36 			dma_unmap_single(ring->dev,
37 					 dma_unmap_addr(tx_buffer, dma),
38 					 dma_unmap_len(tx_buffer, len),
39 					 DMA_TO_DEVICE);
40 	} else if (dma_unmap_len(tx_buffer, len)) {
41 		dma_unmap_page(ring->dev,
42 			       dma_unmap_addr(tx_buffer, dma),
43 			       dma_unmap_len(tx_buffer, len),
44 			       DMA_TO_DEVICE);
45 	}
46 
47 	tx_buffer->next_to_watch = NULL;
48 	tx_buffer->skb = NULL;
49 	dma_unmap_len_set(tx_buffer, len, 0);
50 	/* tx_buffer must be completely set up in the transmit path */
51 }
52 
53 /**
54  * iavf_clean_tx_ring - Free any empty Tx buffers
55  * @tx_ring: ring to be cleaned
56  **/
57 void iavf_clean_tx_ring(struct iavf_ring *tx_ring)
58 {
59 	unsigned long bi_size;
60 	u16 i;
61 
62 	/* ring already cleared, nothing to do */
63 	if (!tx_ring->tx_bi)
64 		return;
65 
66 	/* Free all the Tx ring sk_buffs */
67 	for (i = 0; i < tx_ring->count; i++)
68 		iavf_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
69 
70 	bi_size = sizeof(struct iavf_tx_buffer) * tx_ring->count;
71 	memset(tx_ring->tx_bi, 0, bi_size);
72 
73 	/* Zero out the descriptor ring */
74 	memset(tx_ring->desc, 0, tx_ring->size);
75 
76 	tx_ring->next_to_use = 0;
77 	tx_ring->next_to_clean = 0;
78 
79 	if (!tx_ring->netdev)
80 		return;
81 
82 	/* cleanup Tx queue statistics */
83 	netdev_tx_reset_queue(txring_txq(tx_ring));
84 }
85 
86 /**
87  * iavf_free_tx_resources - Free Tx resources per queue
88  * @tx_ring: Tx descriptor ring for a specific queue
89  *
90  * Free all transmit software resources
91  **/
92 void iavf_free_tx_resources(struct iavf_ring *tx_ring)
93 {
94 	iavf_clean_tx_ring(tx_ring);
95 	kfree(tx_ring->tx_bi);
96 	tx_ring->tx_bi = NULL;
97 
98 	if (tx_ring->desc) {
99 		dma_free_coherent(tx_ring->dev, tx_ring->size,
100 				  tx_ring->desc, tx_ring->dma);
101 		tx_ring->desc = NULL;
102 	}
103 }
104 
105 /**
106  * iavf_get_tx_pending - how many Tx descriptors not processed
107  * @ring: the ring of descriptors
108  * @in_sw: is tx_pending being checked in SW or HW
109  *
110  * Since there is no access to the ring head register
111  * in XL710, we need to use our local copies
112  **/
113 u32 iavf_get_tx_pending(struct iavf_ring *ring, bool in_sw)
114 {
115 	u32 head, tail;
116 
117 	head = ring->next_to_clean;
118 	tail = readl(ring->tail);
119 
120 	if (head != tail)
121 		return (head < tail) ?
122 			tail - head : (tail + ring->count - head);
123 
124 	return 0;
125 }
126 
127 /**
128  * iavf_detect_recover_hung - Function to detect and recover hung_queues
129  * @vsi:  pointer to vsi struct with tx queues
130  *
131  * VSI has netdev and netdev has TX queues. This function is to check each of
132  * those TX queues if they are hung, trigger recovery by issuing SW interrupt.
133  **/
134 void iavf_detect_recover_hung(struct iavf_vsi *vsi)
135 {
136 	struct iavf_ring *tx_ring = NULL;
137 	struct net_device *netdev;
138 	unsigned int i;
139 	int packets;
140 
141 	if (!vsi)
142 		return;
143 
144 	if (test_bit(__IAVF_VSI_DOWN, vsi->state))
145 		return;
146 
147 	netdev = vsi->netdev;
148 	if (!netdev)
149 		return;
150 
151 	if (!netif_carrier_ok(netdev))
152 		return;
153 
154 	for (i = 0; i < vsi->back->num_active_queues; i++) {
155 		tx_ring = &vsi->back->tx_rings[i];
156 		if (tx_ring && tx_ring->desc) {
157 			/* If packet counter has not changed the queue is
158 			 * likely stalled, so force an interrupt for this
159 			 * queue.
160 			 *
161 			 * prev_pkt_ctr would be negative if there was no
162 			 * pending work.
163 			 */
164 			packets = tx_ring->stats.packets & INT_MAX;
165 			if (tx_ring->tx_stats.prev_pkt_ctr == packets) {
166 				iavf_force_wb(vsi, tx_ring->q_vector);
167 				continue;
168 			}
169 
170 			/* Memory barrier between read of packet count and call
171 			 * to iavf_get_tx_pending()
172 			 */
173 			smp_rmb();
174 			tx_ring->tx_stats.prev_pkt_ctr =
175 			  iavf_get_tx_pending(tx_ring, true) ? packets : -1;
176 		}
177 	}
178 }
179 
180 #define WB_STRIDE 4
181 
182 /**
183  * iavf_clean_tx_irq - Reclaim resources after transmit completes
184  * @vsi: the VSI we care about
185  * @tx_ring: Tx ring to clean
186  * @napi_budget: Used to determine if we are in netpoll
187  *
188  * Returns true if there's any budget left (e.g. the clean is finished)
189  **/
190 static bool iavf_clean_tx_irq(struct iavf_vsi *vsi,
191 			      struct iavf_ring *tx_ring, int napi_budget)
192 {
193 	int i = tx_ring->next_to_clean;
194 	struct iavf_tx_buffer *tx_buf;
195 	struct iavf_tx_desc *tx_desc;
196 	unsigned int total_bytes = 0, total_packets = 0;
197 	unsigned int budget = vsi->work_limit;
198 
199 	tx_buf = &tx_ring->tx_bi[i];
200 	tx_desc = IAVF_TX_DESC(tx_ring, i);
201 	i -= tx_ring->count;
202 
203 	do {
204 		struct iavf_tx_desc *eop_desc = tx_buf->next_to_watch;
205 
206 		/* if next_to_watch is not set then there is no work pending */
207 		if (!eop_desc)
208 			break;
209 
210 		/* prevent any other reads prior to eop_desc */
211 		smp_rmb();
212 
213 		iavf_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
214 		/* if the descriptor isn't done, no work yet to do */
215 		if (!(eop_desc->cmd_type_offset_bsz &
216 		      cpu_to_le64(IAVF_TX_DESC_DTYPE_DESC_DONE)))
217 			break;
218 
219 		/* clear next_to_watch to prevent false hangs */
220 		tx_buf->next_to_watch = NULL;
221 
222 		/* update the statistics for this packet */
223 		total_bytes += tx_buf->bytecount;
224 		total_packets += tx_buf->gso_segs;
225 
226 		/* free the skb */
227 		napi_consume_skb(tx_buf->skb, napi_budget);
228 
229 		/* unmap skb header data */
230 		dma_unmap_single(tx_ring->dev,
231 				 dma_unmap_addr(tx_buf, dma),
232 				 dma_unmap_len(tx_buf, len),
233 				 DMA_TO_DEVICE);
234 
235 		/* clear tx_buffer data */
236 		tx_buf->skb = NULL;
237 		dma_unmap_len_set(tx_buf, len, 0);
238 
239 		/* unmap remaining buffers */
240 		while (tx_desc != eop_desc) {
241 			iavf_trace(clean_tx_irq_unmap,
242 				   tx_ring, tx_desc, tx_buf);
243 
244 			tx_buf++;
245 			tx_desc++;
246 			i++;
247 			if (unlikely(!i)) {
248 				i -= tx_ring->count;
249 				tx_buf = tx_ring->tx_bi;
250 				tx_desc = IAVF_TX_DESC(tx_ring, 0);
251 			}
252 
253 			/* unmap any remaining paged data */
254 			if (dma_unmap_len(tx_buf, len)) {
255 				dma_unmap_page(tx_ring->dev,
256 					       dma_unmap_addr(tx_buf, dma),
257 					       dma_unmap_len(tx_buf, len),
258 					       DMA_TO_DEVICE);
259 				dma_unmap_len_set(tx_buf, len, 0);
260 			}
261 		}
262 
263 		/* move us one more past the eop_desc for start of next pkt */
264 		tx_buf++;
265 		tx_desc++;
266 		i++;
267 		if (unlikely(!i)) {
268 			i -= tx_ring->count;
269 			tx_buf = tx_ring->tx_bi;
270 			tx_desc = IAVF_TX_DESC(tx_ring, 0);
271 		}
272 
273 		prefetch(tx_desc);
274 
275 		/* update budget accounting */
276 		budget--;
277 	} while (likely(budget));
278 
279 	i += tx_ring->count;
280 	tx_ring->next_to_clean = i;
281 	u64_stats_update_begin(&tx_ring->syncp);
282 	tx_ring->stats.bytes += total_bytes;
283 	tx_ring->stats.packets += total_packets;
284 	u64_stats_update_end(&tx_ring->syncp);
285 	tx_ring->q_vector->tx.total_bytes += total_bytes;
286 	tx_ring->q_vector->tx.total_packets += total_packets;
287 
288 	if (tx_ring->flags & IAVF_TXR_FLAGS_WB_ON_ITR) {
289 		/* check to see if there are < 4 descriptors
290 		 * waiting to be written back, then kick the hardware to force
291 		 * them to be written back in case we stay in NAPI.
292 		 * In this mode on X722 we do not enable Interrupt.
293 		 */
294 		unsigned int j = iavf_get_tx_pending(tx_ring, false);
295 
296 		if (budget &&
297 		    ((j / WB_STRIDE) == 0) && (j > 0) &&
298 		    !test_bit(__IAVF_VSI_DOWN, vsi->state) &&
299 		    (IAVF_DESC_UNUSED(tx_ring) != tx_ring->count))
300 			tx_ring->arm_wb = true;
301 	}
302 
303 	/* notify netdev of completed buffers */
304 	netdev_tx_completed_queue(txring_txq(tx_ring),
305 				  total_packets, total_bytes);
306 
307 #define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
308 	if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
309 		     (IAVF_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
310 		/* Make sure that anybody stopping the queue after this
311 		 * sees the new next_to_clean.
312 		 */
313 		smp_mb();
314 		if (__netif_subqueue_stopped(tx_ring->netdev,
315 					     tx_ring->queue_index) &&
316 		   !test_bit(__IAVF_VSI_DOWN, vsi->state)) {
317 			netif_wake_subqueue(tx_ring->netdev,
318 					    tx_ring->queue_index);
319 			++tx_ring->tx_stats.restart_queue;
320 		}
321 	}
322 
323 	return !!budget;
324 }
325 
326 /**
327  * iavf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
328  * @vsi: the VSI we care about
329  * @q_vector: the vector on which to enable writeback
330  *
331  **/
332 static void iavf_enable_wb_on_itr(struct iavf_vsi *vsi,
333 				  struct iavf_q_vector *q_vector)
334 {
335 	u16 flags = q_vector->tx.ring[0].flags;
336 	u32 val;
337 
338 	if (!(flags & IAVF_TXR_FLAGS_WB_ON_ITR))
339 		return;
340 
341 	if (q_vector->arm_wb_state)
342 		return;
343 
344 	val = IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
345 	      IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */
346 
347 	wr32(&vsi->back->hw,
348 	     IAVF_VFINT_DYN_CTLN1(q_vector->reg_idx), val);
349 	q_vector->arm_wb_state = true;
350 }
351 
352 /**
353  * iavf_force_wb - Issue SW Interrupt so HW does a wb
354  * @vsi: the VSI we care about
355  * @q_vector: the vector  on which to force writeback
356  *
357  **/
358 void iavf_force_wb(struct iavf_vsi *vsi, struct iavf_q_vector *q_vector)
359 {
360 	u32 val = IAVF_VFINT_DYN_CTLN1_INTENA_MASK |
361 		  IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
362 		  IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
363 		  IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
364 		  /* allow 00 to be written to the index */;
365 
366 	wr32(&vsi->back->hw,
367 	     IAVF_VFINT_DYN_CTLN1(q_vector->reg_idx),
368 	     val);
369 }
370 
371 static inline bool iavf_container_is_rx(struct iavf_q_vector *q_vector,
372 					struct iavf_ring_container *rc)
373 {
374 	return &q_vector->rx == rc;
375 }
376 
377 static inline unsigned int iavf_itr_divisor(struct iavf_q_vector *q_vector)
378 {
379 	unsigned int divisor;
380 
381 	switch (q_vector->adapter->link_speed) {
382 	case VIRTCHNL_LINK_SPEED_40GB:
383 		divisor = IAVF_ITR_ADAPTIVE_MIN_INC * 1024;
384 		break;
385 	case VIRTCHNL_LINK_SPEED_25GB:
386 	case VIRTCHNL_LINK_SPEED_20GB:
387 		divisor = IAVF_ITR_ADAPTIVE_MIN_INC * 512;
388 		break;
389 	default:
390 	case VIRTCHNL_LINK_SPEED_10GB:
391 		divisor = IAVF_ITR_ADAPTIVE_MIN_INC * 256;
392 		break;
393 	case VIRTCHNL_LINK_SPEED_1GB:
394 	case VIRTCHNL_LINK_SPEED_100MB:
395 		divisor = IAVF_ITR_ADAPTIVE_MIN_INC * 32;
396 		break;
397 	}
398 
399 	return divisor;
400 }
401 
402 /**
403  * iavf_update_itr - update the dynamic ITR value based on statistics
404  * @q_vector: structure containing interrupt and ring information
405  * @rc: structure containing ring performance data
406  *
407  * Stores a new ITR value based on packets and byte
408  * counts during the last interrupt.  The advantage of per interrupt
409  * computation is faster updates and more accurate ITR for the current
410  * traffic pattern.  Constants in this function were computed
411  * based on theoretical maximum wire speed and thresholds were set based
412  * on testing data as well as attempting to minimize response time
413  * while increasing bulk throughput.
414  **/
415 static void iavf_update_itr(struct iavf_q_vector *q_vector,
416 			    struct iavf_ring_container *rc)
417 {
418 	unsigned int avg_wire_size, packets, bytes, itr;
419 	unsigned long next_update = jiffies;
420 
421 	/* If we don't have any rings just leave ourselves set for maximum
422 	 * possible latency so we take ourselves out of the equation.
423 	 */
424 	if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting))
425 		return;
426 
427 	/* For Rx we want to push the delay up and default to low latency.
428 	 * for Tx we want to pull the delay down and default to high latency.
429 	 */
430 	itr = iavf_container_is_rx(q_vector, rc) ?
431 	      IAVF_ITR_ADAPTIVE_MIN_USECS | IAVF_ITR_ADAPTIVE_LATENCY :
432 	      IAVF_ITR_ADAPTIVE_MAX_USECS | IAVF_ITR_ADAPTIVE_LATENCY;
433 
434 	/* If we didn't update within up to 1 - 2 jiffies we can assume
435 	 * that either packets are coming in so slow there hasn't been
436 	 * any work, or that there is so much work that NAPI is dealing
437 	 * with interrupt moderation and we don't need to do anything.
438 	 */
439 	if (time_after(next_update, rc->next_update))
440 		goto clear_counts;
441 
442 	/* If itr_countdown is set it means we programmed an ITR within
443 	 * the last 4 interrupt cycles. This has a side effect of us
444 	 * potentially firing an early interrupt. In order to work around
445 	 * this we need to throw out any data received for a few
446 	 * interrupts following the update.
447 	 */
448 	if (q_vector->itr_countdown) {
449 		itr = rc->target_itr;
450 		goto clear_counts;
451 	}
452 
453 	packets = rc->total_packets;
454 	bytes = rc->total_bytes;
455 
456 	if (iavf_container_is_rx(q_vector, rc)) {
457 		/* If Rx there are 1 to 4 packets and bytes are less than
458 		 * 9000 assume insufficient data to use bulk rate limiting
459 		 * approach unless Tx is already in bulk rate limiting. We
460 		 * are likely latency driven.
461 		 */
462 		if (packets && packets < 4 && bytes < 9000 &&
463 		    (q_vector->tx.target_itr & IAVF_ITR_ADAPTIVE_LATENCY)) {
464 			itr = IAVF_ITR_ADAPTIVE_LATENCY;
465 			goto adjust_by_size;
466 		}
467 	} else if (packets < 4) {
468 		/* If we have Tx and Rx ITR maxed and Tx ITR is running in
469 		 * bulk mode and we are receiving 4 or fewer packets just
470 		 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so
471 		 * that the Rx can relax.
472 		 */
473 		if (rc->target_itr == IAVF_ITR_ADAPTIVE_MAX_USECS &&
474 		    (q_vector->rx.target_itr & IAVF_ITR_MASK) ==
475 		     IAVF_ITR_ADAPTIVE_MAX_USECS)
476 			goto clear_counts;
477 	} else if (packets > 32) {
478 		/* If we have processed over 32 packets in a single interrupt
479 		 * for Tx assume we need to switch over to "bulk" mode.
480 		 */
481 		rc->target_itr &= ~IAVF_ITR_ADAPTIVE_LATENCY;
482 	}
483 
484 	/* We have no packets to actually measure against. This means
485 	 * either one of the other queues on this vector is active or
486 	 * we are a Tx queue doing TSO with too high of an interrupt rate.
487 	 *
488 	 * Between 4 and 56 we can assume that our current interrupt delay
489 	 * is only slightly too low. As such we should increase it by a small
490 	 * fixed amount.
491 	 */
492 	if (packets < 56) {
493 		itr = rc->target_itr + IAVF_ITR_ADAPTIVE_MIN_INC;
494 		if ((itr & IAVF_ITR_MASK) > IAVF_ITR_ADAPTIVE_MAX_USECS) {
495 			itr &= IAVF_ITR_ADAPTIVE_LATENCY;
496 			itr += IAVF_ITR_ADAPTIVE_MAX_USECS;
497 		}
498 		goto clear_counts;
499 	}
500 
501 	if (packets <= 256) {
502 		itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr);
503 		itr &= IAVF_ITR_MASK;
504 
505 		/* Between 56 and 112 is our "goldilocks" zone where we are
506 		 * working out "just right". Just report that our current
507 		 * ITR is good for us.
508 		 */
509 		if (packets <= 112)
510 			goto clear_counts;
511 
512 		/* If packet count is 128 or greater we are likely looking
513 		 * at a slight overrun of the delay we want. Try halving
514 		 * our delay to see if that will cut the number of packets
515 		 * in half per interrupt.
516 		 */
517 		itr /= 2;
518 		itr &= IAVF_ITR_MASK;
519 		if (itr < IAVF_ITR_ADAPTIVE_MIN_USECS)
520 			itr = IAVF_ITR_ADAPTIVE_MIN_USECS;
521 
522 		goto clear_counts;
523 	}
524 
525 	/* The paths below assume we are dealing with a bulk ITR since
526 	 * number of packets is greater than 256. We are just going to have
527 	 * to compute a value and try to bring the count under control,
528 	 * though for smaller packet sizes there isn't much we can do as
529 	 * NAPI polling will likely be kicking in sooner rather than later.
530 	 */
531 	itr = IAVF_ITR_ADAPTIVE_BULK;
532 
533 adjust_by_size:
534 	/* If packet counts are 256 or greater we can assume we have a gross
535 	 * overestimation of what the rate should be. Instead of trying to fine
536 	 * tune it just use the formula below to try and dial in an exact value
537 	 * give the current packet size of the frame.
538 	 */
539 	avg_wire_size = bytes / packets;
540 
541 	/* The following is a crude approximation of:
542 	 *  wmem_default / (size + overhead) = desired_pkts_per_int
543 	 *  rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
544 	 *  (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
545 	 *
546 	 * Assuming wmem_default is 212992 and overhead is 640 bytes per
547 	 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
548 	 * formula down to
549 	 *
550 	 *  (170 * (size + 24)) / (size + 640) = ITR
551 	 *
552 	 * We first do some math on the packet size and then finally bitshift
553 	 * by 8 after rounding up. We also have to account for PCIe link speed
554 	 * difference as ITR scales based on this.
555 	 */
556 	if (avg_wire_size <= 60) {
557 		/* Start at 250k ints/sec */
558 		avg_wire_size = 4096;
559 	} else if (avg_wire_size <= 380) {
560 		/* 250K ints/sec to 60K ints/sec */
561 		avg_wire_size *= 40;
562 		avg_wire_size += 1696;
563 	} else if (avg_wire_size <= 1084) {
564 		/* 60K ints/sec to 36K ints/sec */
565 		avg_wire_size *= 15;
566 		avg_wire_size += 11452;
567 	} else if (avg_wire_size <= 1980) {
568 		/* 36K ints/sec to 30K ints/sec */
569 		avg_wire_size *= 5;
570 		avg_wire_size += 22420;
571 	} else {
572 		/* plateau at a limit of 30K ints/sec */
573 		avg_wire_size = 32256;
574 	}
575 
576 	/* If we are in low latency mode halve our delay which doubles the
577 	 * rate to somewhere between 100K to 16K ints/sec
578 	 */
579 	if (itr & IAVF_ITR_ADAPTIVE_LATENCY)
580 		avg_wire_size /= 2;
581 
582 	/* Resultant value is 256 times larger than it needs to be. This
583 	 * gives us room to adjust the value as needed to either increase
584 	 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
585 	 *
586 	 * Use addition as we have already recorded the new latency flag
587 	 * for the ITR value.
588 	 */
589 	itr += DIV_ROUND_UP(avg_wire_size, iavf_itr_divisor(q_vector)) *
590 	       IAVF_ITR_ADAPTIVE_MIN_INC;
591 
592 	if ((itr & IAVF_ITR_MASK) > IAVF_ITR_ADAPTIVE_MAX_USECS) {
593 		itr &= IAVF_ITR_ADAPTIVE_LATENCY;
594 		itr += IAVF_ITR_ADAPTIVE_MAX_USECS;
595 	}
596 
597 clear_counts:
598 	/* write back value */
599 	rc->target_itr = itr;
600 
601 	/* next update should occur within next jiffy */
602 	rc->next_update = next_update + 1;
603 
604 	rc->total_bytes = 0;
605 	rc->total_packets = 0;
606 }
607 
608 /**
609  * iavf_setup_tx_descriptors - Allocate the Tx descriptors
610  * @tx_ring: the tx ring to set up
611  *
612  * Return 0 on success, negative on error
613  **/
614 int iavf_setup_tx_descriptors(struct iavf_ring *tx_ring)
615 {
616 	struct device *dev = tx_ring->dev;
617 	int bi_size;
618 
619 	if (!dev)
620 		return -ENOMEM;
621 
622 	/* warn if we are about to overwrite the pointer */
623 	WARN_ON(tx_ring->tx_bi);
624 	bi_size = sizeof(struct iavf_tx_buffer) * tx_ring->count;
625 	tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
626 	if (!tx_ring->tx_bi)
627 		goto err;
628 
629 	/* round up to nearest 4K */
630 	tx_ring->size = tx_ring->count * sizeof(struct iavf_tx_desc);
631 	tx_ring->size = ALIGN(tx_ring->size, 4096);
632 	tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
633 					   &tx_ring->dma, GFP_KERNEL);
634 	if (!tx_ring->desc) {
635 		dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
636 			 tx_ring->size);
637 		goto err;
638 	}
639 
640 	tx_ring->next_to_use = 0;
641 	tx_ring->next_to_clean = 0;
642 	tx_ring->tx_stats.prev_pkt_ctr = -1;
643 	return 0;
644 
645 err:
646 	kfree(tx_ring->tx_bi);
647 	tx_ring->tx_bi = NULL;
648 	return -ENOMEM;
649 }
650 
651 /**
652  * iavf_clean_rx_ring - Free Rx buffers
653  * @rx_ring: ring to be cleaned
654  **/
655 void iavf_clean_rx_ring(struct iavf_ring *rx_ring)
656 {
657 	unsigned long bi_size;
658 	u16 i;
659 
660 	/* ring already cleared, nothing to do */
661 	if (!rx_ring->rx_bi)
662 		return;
663 
664 	if (rx_ring->skb) {
665 		dev_kfree_skb(rx_ring->skb);
666 		rx_ring->skb = NULL;
667 	}
668 
669 	/* Free all the Rx ring sk_buffs */
670 	for (i = 0; i < rx_ring->count; i++) {
671 		struct iavf_rx_buffer *rx_bi = &rx_ring->rx_bi[i];
672 
673 		if (!rx_bi->page)
674 			continue;
675 
676 		/* Invalidate cache lines that may have been written to by
677 		 * device so that we avoid corrupting memory.
678 		 */
679 		dma_sync_single_range_for_cpu(rx_ring->dev,
680 					      rx_bi->dma,
681 					      rx_bi->page_offset,
682 					      rx_ring->rx_buf_len,
683 					      DMA_FROM_DEVICE);
684 
685 		/* free resources associated with mapping */
686 		dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma,
687 				     iavf_rx_pg_size(rx_ring),
688 				     DMA_FROM_DEVICE,
689 				     IAVF_RX_DMA_ATTR);
690 
691 		__page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias);
692 
693 		rx_bi->page = NULL;
694 		rx_bi->page_offset = 0;
695 	}
696 
697 	bi_size = sizeof(struct iavf_rx_buffer) * rx_ring->count;
698 	memset(rx_ring->rx_bi, 0, bi_size);
699 
700 	/* Zero out the descriptor ring */
701 	memset(rx_ring->desc, 0, rx_ring->size);
702 
703 	rx_ring->next_to_alloc = 0;
704 	rx_ring->next_to_clean = 0;
705 	rx_ring->next_to_use = 0;
706 }
707 
708 /**
709  * iavf_free_rx_resources - Free Rx resources
710  * @rx_ring: ring to clean the resources from
711  *
712  * Free all receive software resources
713  **/
714 void iavf_free_rx_resources(struct iavf_ring *rx_ring)
715 {
716 	iavf_clean_rx_ring(rx_ring);
717 	kfree(rx_ring->rx_bi);
718 	rx_ring->rx_bi = NULL;
719 
720 	if (rx_ring->desc) {
721 		dma_free_coherent(rx_ring->dev, rx_ring->size,
722 				  rx_ring->desc, rx_ring->dma);
723 		rx_ring->desc = NULL;
724 	}
725 }
726 
727 /**
728  * iavf_setup_rx_descriptors - Allocate Rx descriptors
729  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
730  *
731  * Returns 0 on success, negative on failure
732  **/
733 int iavf_setup_rx_descriptors(struct iavf_ring *rx_ring)
734 {
735 	struct device *dev = rx_ring->dev;
736 	int bi_size;
737 
738 	/* warn if we are about to overwrite the pointer */
739 	WARN_ON(rx_ring->rx_bi);
740 	bi_size = sizeof(struct iavf_rx_buffer) * rx_ring->count;
741 	rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
742 	if (!rx_ring->rx_bi)
743 		goto err;
744 
745 	u64_stats_init(&rx_ring->syncp);
746 
747 	/* Round up to nearest 4K */
748 	rx_ring->size = rx_ring->count * sizeof(union iavf_32byte_rx_desc);
749 	rx_ring->size = ALIGN(rx_ring->size, 4096);
750 	rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
751 					   &rx_ring->dma, GFP_KERNEL);
752 
753 	if (!rx_ring->desc) {
754 		dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
755 			 rx_ring->size);
756 		goto err;
757 	}
758 
759 	rx_ring->next_to_alloc = 0;
760 	rx_ring->next_to_clean = 0;
761 	rx_ring->next_to_use = 0;
762 
763 	return 0;
764 err:
765 	kfree(rx_ring->rx_bi);
766 	rx_ring->rx_bi = NULL;
767 	return -ENOMEM;
768 }
769 
770 /**
771  * iavf_release_rx_desc - Store the new tail and head values
772  * @rx_ring: ring to bump
773  * @val: new head index
774  **/
775 static inline void iavf_release_rx_desc(struct iavf_ring *rx_ring, u32 val)
776 {
777 	rx_ring->next_to_use = val;
778 
779 	/* update next to alloc since we have filled the ring */
780 	rx_ring->next_to_alloc = val;
781 
782 	/* Force memory writes to complete before letting h/w
783 	 * know there are new descriptors to fetch.  (Only
784 	 * applicable for weak-ordered memory model archs,
785 	 * such as IA-64).
786 	 */
787 	wmb();
788 	writel(val, rx_ring->tail);
789 }
790 
791 /**
792  * iavf_rx_offset - Return expected offset into page to access data
793  * @rx_ring: Ring we are requesting offset of
794  *
795  * Returns the offset value for ring into the data buffer.
796  */
797 static inline unsigned int iavf_rx_offset(struct iavf_ring *rx_ring)
798 {
799 	return ring_uses_build_skb(rx_ring) ? IAVF_SKB_PAD : 0;
800 }
801 
802 /**
803  * iavf_alloc_mapped_page - recycle or make a new page
804  * @rx_ring: ring to use
805  * @bi: rx_buffer struct to modify
806  *
807  * Returns true if the page was successfully allocated or
808  * reused.
809  **/
810 static bool iavf_alloc_mapped_page(struct iavf_ring *rx_ring,
811 				   struct iavf_rx_buffer *bi)
812 {
813 	struct page *page = bi->page;
814 	dma_addr_t dma;
815 
816 	/* since we are recycling buffers we should seldom need to alloc */
817 	if (likely(page)) {
818 		rx_ring->rx_stats.page_reuse_count++;
819 		return true;
820 	}
821 
822 	/* alloc new page for storage */
823 	page = dev_alloc_pages(iavf_rx_pg_order(rx_ring));
824 	if (unlikely(!page)) {
825 		rx_ring->rx_stats.alloc_page_failed++;
826 		return false;
827 	}
828 
829 	/* map page for use */
830 	dma = dma_map_page_attrs(rx_ring->dev, page, 0,
831 				 iavf_rx_pg_size(rx_ring),
832 				 DMA_FROM_DEVICE,
833 				 IAVF_RX_DMA_ATTR);
834 
835 	/* if mapping failed free memory back to system since
836 	 * there isn't much point in holding memory we can't use
837 	 */
838 	if (dma_mapping_error(rx_ring->dev, dma)) {
839 		__free_pages(page, iavf_rx_pg_order(rx_ring));
840 		rx_ring->rx_stats.alloc_page_failed++;
841 		return false;
842 	}
843 
844 	bi->dma = dma;
845 	bi->page = page;
846 	bi->page_offset = iavf_rx_offset(rx_ring);
847 
848 	/* initialize pagecnt_bias to 1 representing we fully own page */
849 	bi->pagecnt_bias = 1;
850 
851 	return true;
852 }
853 
854 /**
855  * iavf_receive_skb - Send a completed packet up the stack
856  * @rx_ring:  rx ring in play
857  * @skb: packet to send up
858  * @vlan_tag: vlan tag for packet
859  **/
860 static void iavf_receive_skb(struct iavf_ring *rx_ring,
861 			     struct sk_buff *skb, u16 vlan_tag)
862 {
863 	struct iavf_q_vector *q_vector = rx_ring->q_vector;
864 
865 	if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
866 	    (vlan_tag & VLAN_VID_MASK))
867 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
868 
869 	napi_gro_receive(&q_vector->napi, skb);
870 }
871 
872 /**
873  * iavf_alloc_rx_buffers - Replace used receive buffers
874  * @rx_ring: ring to place buffers on
875  * @cleaned_count: number of buffers to replace
876  *
877  * Returns false if all allocations were successful, true if any fail
878  **/
879 bool iavf_alloc_rx_buffers(struct iavf_ring *rx_ring, u16 cleaned_count)
880 {
881 	u16 ntu = rx_ring->next_to_use;
882 	union iavf_rx_desc *rx_desc;
883 	struct iavf_rx_buffer *bi;
884 
885 	/* do nothing if no valid netdev defined */
886 	if (!rx_ring->netdev || !cleaned_count)
887 		return false;
888 
889 	rx_desc = IAVF_RX_DESC(rx_ring, ntu);
890 	bi = &rx_ring->rx_bi[ntu];
891 
892 	do {
893 		if (!iavf_alloc_mapped_page(rx_ring, bi))
894 			goto no_buffers;
895 
896 		/* sync the buffer for use by the device */
897 		dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
898 						 bi->page_offset,
899 						 rx_ring->rx_buf_len,
900 						 DMA_FROM_DEVICE);
901 
902 		/* Refresh the desc even if buffer_addrs didn't change
903 		 * because each write-back erases this info.
904 		 */
905 		rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
906 
907 		rx_desc++;
908 		bi++;
909 		ntu++;
910 		if (unlikely(ntu == rx_ring->count)) {
911 			rx_desc = IAVF_RX_DESC(rx_ring, 0);
912 			bi = rx_ring->rx_bi;
913 			ntu = 0;
914 		}
915 
916 		/* clear the status bits for the next_to_use descriptor */
917 		rx_desc->wb.qword1.status_error_len = 0;
918 
919 		cleaned_count--;
920 	} while (cleaned_count);
921 
922 	if (rx_ring->next_to_use != ntu)
923 		iavf_release_rx_desc(rx_ring, ntu);
924 
925 	return false;
926 
927 no_buffers:
928 	if (rx_ring->next_to_use != ntu)
929 		iavf_release_rx_desc(rx_ring, ntu);
930 
931 	/* make sure to come back via polling to try again after
932 	 * allocation failure
933 	 */
934 	return true;
935 }
936 
937 /**
938  * iavf_rx_checksum - Indicate in skb if hw indicated a good cksum
939  * @vsi: the VSI we care about
940  * @skb: skb currently being received and modified
941  * @rx_desc: the receive descriptor
942  **/
943 static inline void iavf_rx_checksum(struct iavf_vsi *vsi,
944 				    struct sk_buff *skb,
945 				    union iavf_rx_desc *rx_desc)
946 {
947 	struct iavf_rx_ptype_decoded decoded;
948 	u32 rx_error, rx_status;
949 	bool ipv4, ipv6;
950 	u8 ptype;
951 	u64 qword;
952 
953 	qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
954 	ptype = (qword & IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT;
955 	rx_error = (qword & IAVF_RXD_QW1_ERROR_MASK) >>
956 		   IAVF_RXD_QW1_ERROR_SHIFT;
957 	rx_status = (qword & IAVF_RXD_QW1_STATUS_MASK) >>
958 		    IAVF_RXD_QW1_STATUS_SHIFT;
959 	decoded = decode_rx_desc_ptype(ptype);
960 
961 	skb->ip_summed = CHECKSUM_NONE;
962 
963 	skb_checksum_none_assert(skb);
964 
965 	/* Rx csum enabled and ip headers found? */
966 	if (!(vsi->netdev->features & NETIF_F_RXCSUM))
967 		return;
968 
969 	/* did the hardware decode the packet and checksum? */
970 	if (!(rx_status & BIT(IAVF_RX_DESC_STATUS_L3L4P_SHIFT)))
971 		return;
972 
973 	/* both known and outer_ip must be set for the below code to work */
974 	if (!(decoded.known && decoded.outer_ip))
975 		return;
976 
977 	ipv4 = (decoded.outer_ip == IAVF_RX_PTYPE_OUTER_IP) &&
978 	       (decoded.outer_ip_ver == IAVF_RX_PTYPE_OUTER_IPV4);
979 	ipv6 = (decoded.outer_ip == IAVF_RX_PTYPE_OUTER_IP) &&
980 	       (decoded.outer_ip_ver == IAVF_RX_PTYPE_OUTER_IPV6);
981 
982 	if (ipv4 &&
983 	    (rx_error & (BIT(IAVF_RX_DESC_ERROR_IPE_SHIFT) |
984 			 BIT(IAVF_RX_DESC_ERROR_EIPE_SHIFT))))
985 		goto checksum_fail;
986 
987 	/* likely incorrect csum if alternate IP extension headers found */
988 	if (ipv6 &&
989 	    rx_status & BIT(IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT))
990 		/* don't increment checksum err here, non-fatal err */
991 		return;
992 
993 	/* there was some L4 error, count error and punt packet to the stack */
994 	if (rx_error & BIT(IAVF_RX_DESC_ERROR_L4E_SHIFT))
995 		goto checksum_fail;
996 
997 	/* handle packets that were not able to be checksummed due
998 	 * to arrival speed, in this case the stack can compute
999 	 * the csum.
1000 	 */
1001 	if (rx_error & BIT(IAVF_RX_DESC_ERROR_PPRS_SHIFT))
1002 		return;
1003 
1004 	/* Only report checksum unnecessary for TCP, UDP, or SCTP */
1005 	switch (decoded.inner_prot) {
1006 	case IAVF_RX_PTYPE_INNER_PROT_TCP:
1007 	case IAVF_RX_PTYPE_INNER_PROT_UDP:
1008 	case IAVF_RX_PTYPE_INNER_PROT_SCTP:
1009 		skb->ip_summed = CHECKSUM_UNNECESSARY;
1010 		fallthrough;
1011 	default:
1012 		break;
1013 	}
1014 
1015 	return;
1016 
1017 checksum_fail:
1018 	vsi->back->hw_csum_rx_error++;
1019 }
1020 
1021 /**
1022  * iavf_ptype_to_htype - get a hash type
1023  * @ptype: the ptype value from the descriptor
1024  *
1025  * Returns a hash type to be used by skb_set_hash
1026  **/
1027 static inline int iavf_ptype_to_htype(u8 ptype)
1028 {
1029 	struct iavf_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1030 
1031 	if (!decoded.known)
1032 		return PKT_HASH_TYPE_NONE;
1033 
1034 	if (decoded.outer_ip == IAVF_RX_PTYPE_OUTER_IP &&
1035 	    decoded.payload_layer == IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1036 		return PKT_HASH_TYPE_L4;
1037 	else if (decoded.outer_ip == IAVF_RX_PTYPE_OUTER_IP &&
1038 		 decoded.payload_layer == IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1039 		return PKT_HASH_TYPE_L3;
1040 	else
1041 		return PKT_HASH_TYPE_L2;
1042 }
1043 
1044 /**
1045  * iavf_rx_hash - set the hash value in the skb
1046  * @ring: descriptor ring
1047  * @rx_desc: specific descriptor
1048  * @skb: skb currently being received and modified
1049  * @rx_ptype: Rx packet type
1050  **/
1051 static inline void iavf_rx_hash(struct iavf_ring *ring,
1052 				union iavf_rx_desc *rx_desc,
1053 				struct sk_buff *skb,
1054 				u8 rx_ptype)
1055 {
1056 	u32 hash;
1057 	const __le64 rss_mask =
1058 		cpu_to_le64((u64)IAVF_RX_DESC_FLTSTAT_RSS_HASH <<
1059 			    IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT);
1060 
1061 	if (ring->netdev->features & NETIF_F_RXHASH)
1062 		return;
1063 
1064 	if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
1065 		hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1066 		skb_set_hash(skb, hash, iavf_ptype_to_htype(rx_ptype));
1067 	}
1068 }
1069 
1070 /**
1071  * iavf_process_skb_fields - Populate skb header fields from Rx descriptor
1072  * @rx_ring: rx descriptor ring packet is being transacted on
1073  * @rx_desc: pointer to the EOP Rx descriptor
1074  * @skb: pointer to current skb being populated
1075  * @rx_ptype: the packet type decoded by hardware
1076  *
1077  * This function checks the ring, descriptor, and packet information in
1078  * order to populate the hash, checksum, VLAN, protocol, and
1079  * other fields within the skb.
1080  **/
1081 static inline
1082 void iavf_process_skb_fields(struct iavf_ring *rx_ring,
1083 			     union iavf_rx_desc *rx_desc, struct sk_buff *skb,
1084 			     u8 rx_ptype)
1085 {
1086 	iavf_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1087 
1088 	iavf_rx_checksum(rx_ring->vsi, skb, rx_desc);
1089 
1090 	skb_record_rx_queue(skb, rx_ring->queue_index);
1091 
1092 	/* modifies the skb - consumes the enet header */
1093 	skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1094 }
1095 
1096 /**
1097  * iavf_cleanup_headers - Correct empty headers
1098  * @rx_ring: rx descriptor ring packet is being transacted on
1099  * @skb: pointer to current skb being fixed
1100  *
1101  * Also address the case where we are pulling data in on pages only
1102  * and as such no data is present in the skb header.
1103  *
1104  * In addition if skb is not at least 60 bytes we need to pad it so that
1105  * it is large enough to qualify as a valid Ethernet frame.
1106  *
1107  * Returns true if an error was encountered and skb was freed.
1108  **/
1109 static bool iavf_cleanup_headers(struct iavf_ring *rx_ring, struct sk_buff *skb)
1110 {
1111 	/* if eth_skb_pad returns an error the skb was freed */
1112 	if (eth_skb_pad(skb))
1113 		return true;
1114 
1115 	return false;
1116 }
1117 
1118 /**
1119  * iavf_reuse_rx_page - page flip buffer and store it back on the ring
1120  * @rx_ring: rx descriptor ring to store buffers on
1121  * @old_buff: donor buffer to have page reused
1122  *
1123  * Synchronizes page for reuse by the adapter
1124  **/
1125 static void iavf_reuse_rx_page(struct iavf_ring *rx_ring,
1126 			       struct iavf_rx_buffer *old_buff)
1127 {
1128 	struct iavf_rx_buffer *new_buff;
1129 	u16 nta = rx_ring->next_to_alloc;
1130 
1131 	new_buff = &rx_ring->rx_bi[nta];
1132 
1133 	/* update, and store next to alloc */
1134 	nta++;
1135 	rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1136 
1137 	/* transfer page from old buffer to new buffer */
1138 	new_buff->dma		= old_buff->dma;
1139 	new_buff->page		= old_buff->page;
1140 	new_buff->page_offset	= old_buff->page_offset;
1141 	new_buff->pagecnt_bias	= old_buff->pagecnt_bias;
1142 }
1143 
1144 /**
1145  * iavf_can_reuse_rx_page - Determine if this page can be reused by
1146  * the adapter for another receive
1147  *
1148  * @rx_buffer: buffer containing the page
1149  *
1150  * If page is reusable, rx_buffer->page_offset is adjusted to point to
1151  * an unused region in the page.
1152  *
1153  * For small pages, @truesize will be a constant value, half the size
1154  * of the memory at page.  We'll attempt to alternate between high and
1155  * low halves of the page, with one half ready for use by the hardware
1156  * and the other half being consumed by the stack.  We use the page
1157  * ref count to determine whether the stack has finished consuming the
1158  * portion of this page that was passed up with a previous packet.  If
1159  * the page ref count is >1, we'll assume the "other" half page is
1160  * still busy, and this page cannot be reused.
1161  *
1162  * For larger pages, @truesize will be the actual space used by the
1163  * received packet (adjusted upward to an even multiple of the cache
1164  * line size).  This will advance through the page by the amount
1165  * actually consumed by the received packets while there is still
1166  * space for a buffer.  Each region of larger pages will be used at
1167  * most once, after which the page will not be reused.
1168  *
1169  * In either case, if the page is reusable its refcount is increased.
1170  **/
1171 static bool iavf_can_reuse_rx_page(struct iavf_rx_buffer *rx_buffer)
1172 {
1173 	unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1174 	struct page *page = rx_buffer->page;
1175 
1176 	/* Is any reuse possible? */
1177 	if (!dev_page_is_reusable(page))
1178 		return false;
1179 
1180 #if (PAGE_SIZE < 8192)
1181 	/* if we are only owner of page we can reuse it */
1182 	if (unlikely((page_count(page) - pagecnt_bias) > 1))
1183 		return false;
1184 #else
1185 #define IAVF_LAST_OFFSET \
1186 	(SKB_WITH_OVERHEAD(PAGE_SIZE) - IAVF_RXBUFFER_2048)
1187 	if (rx_buffer->page_offset > IAVF_LAST_OFFSET)
1188 		return false;
1189 #endif
1190 
1191 	/* If we have drained the page fragment pool we need to update
1192 	 * the pagecnt_bias and page count so that we fully restock the
1193 	 * number of references the driver holds.
1194 	 */
1195 	if (unlikely(!pagecnt_bias)) {
1196 		page_ref_add(page, USHRT_MAX);
1197 		rx_buffer->pagecnt_bias = USHRT_MAX;
1198 	}
1199 
1200 	return true;
1201 }
1202 
1203 /**
1204  * iavf_add_rx_frag - Add contents of Rx buffer to sk_buff
1205  * @rx_ring: rx descriptor ring to transact packets on
1206  * @rx_buffer: buffer containing page to add
1207  * @skb: sk_buff to place the data into
1208  * @size: packet length from rx_desc
1209  *
1210  * This function will add the data contained in rx_buffer->page to the skb.
1211  * It will just attach the page as a frag to the skb.
1212  *
1213  * The function will then update the page offset.
1214  **/
1215 static void iavf_add_rx_frag(struct iavf_ring *rx_ring,
1216 			     struct iavf_rx_buffer *rx_buffer,
1217 			     struct sk_buff *skb,
1218 			     unsigned int size)
1219 {
1220 #if (PAGE_SIZE < 8192)
1221 	unsigned int truesize = iavf_rx_pg_size(rx_ring) / 2;
1222 #else
1223 	unsigned int truesize = SKB_DATA_ALIGN(size + iavf_rx_offset(rx_ring));
1224 #endif
1225 
1226 	if (!size)
1227 		return;
1228 
1229 	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1230 			rx_buffer->page_offset, size, truesize);
1231 
1232 	/* page is being used so we must update the page offset */
1233 #if (PAGE_SIZE < 8192)
1234 	rx_buffer->page_offset ^= truesize;
1235 #else
1236 	rx_buffer->page_offset += truesize;
1237 #endif
1238 }
1239 
1240 /**
1241  * iavf_get_rx_buffer - Fetch Rx buffer and synchronize data for use
1242  * @rx_ring: rx descriptor ring to transact packets on
1243  * @size: size of buffer to add to skb
1244  *
1245  * This function will pull an Rx buffer from the ring and synchronize it
1246  * for use by the CPU.
1247  */
1248 static struct iavf_rx_buffer *iavf_get_rx_buffer(struct iavf_ring *rx_ring,
1249 						 const unsigned int size)
1250 {
1251 	struct iavf_rx_buffer *rx_buffer;
1252 
1253 	if (!size)
1254 		return NULL;
1255 
1256 	rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean];
1257 	prefetchw(rx_buffer->page);
1258 
1259 	/* we are reusing so sync this buffer for CPU use */
1260 	dma_sync_single_range_for_cpu(rx_ring->dev,
1261 				      rx_buffer->dma,
1262 				      rx_buffer->page_offset,
1263 				      size,
1264 				      DMA_FROM_DEVICE);
1265 
1266 	/* We have pulled a buffer for use, so decrement pagecnt_bias */
1267 	rx_buffer->pagecnt_bias--;
1268 
1269 	return rx_buffer;
1270 }
1271 
1272 /**
1273  * iavf_construct_skb - Allocate skb and populate it
1274  * @rx_ring: rx descriptor ring to transact packets on
1275  * @rx_buffer: rx buffer to pull data from
1276  * @size: size of buffer to add to skb
1277  *
1278  * This function allocates an skb.  It then populates it with the page
1279  * data from the current receive descriptor, taking care to set up the
1280  * skb correctly.
1281  */
1282 static struct sk_buff *iavf_construct_skb(struct iavf_ring *rx_ring,
1283 					  struct iavf_rx_buffer *rx_buffer,
1284 					  unsigned int size)
1285 {
1286 	void *va;
1287 #if (PAGE_SIZE < 8192)
1288 	unsigned int truesize = iavf_rx_pg_size(rx_ring) / 2;
1289 #else
1290 	unsigned int truesize = SKB_DATA_ALIGN(size);
1291 #endif
1292 	unsigned int headlen;
1293 	struct sk_buff *skb;
1294 
1295 	if (!rx_buffer)
1296 		return NULL;
1297 	/* prefetch first cache line of first page */
1298 	va = page_address(rx_buffer->page) + rx_buffer->page_offset;
1299 	net_prefetch(va);
1300 
1301 	/* allocate a skb to store the frags */
1302 	skb = __napi_alloc_skb(&rx_ring->q_vector->napi,
1303 			       IAVF_RX_HDR_SIZE,
1304 			       GFP_ATOMIC | __GFP_NOWARN);
1305 	if (unlikely(!skb))
1306 		return NULL;
1307 
1308 	/* Determine available headroom for copy */
1309 	headlen = size;
1310 	if (headlen > IAVF_RX_HDR_SIZE)
1311 		headlen = eth_get_headlen(skb->dev, va, IAVF_RX_HDR_SIZE);
1312 
1313 	/* align pull length to size of long to optimize memcpy performance */
1314 	memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long)));
1315 
1316 	/* update all of the pointers */
1317 	size -= headlen;
1318 	if (size) {
1319 		skb_add_rx_frag(skb, 0, rx_buffer->page,
1320 				rx_buffer->page_offset + headlen,
1321 				size, truesize);
1322 
1323 		/* buffer is used by skb, update page_offset */
1324 #if (PAGE_SIZE < 8192)
1325 		rx_buffer->page_offset ^= truesize;
1326 #else
1327 		rx_buffer->page_offset += truesize;
1328 #endif
1329 	} else {
1330 		/* buffer is unused, reset bias back to rx_buffer */
1331 		rx_buffer->pagecnt_bias++;
1332 	}
1333 
1334 	return skb;
1335 }
1336 
1337 /**
1338  * iavf_build_skb - Build skb around an existing buffer
1339  * @rx_ring: Rx descriptor ring to transact packets on
1340  * @rx_buffer: Rx buffer to pull data from
1341  * @size: size of buffer to add to skb
1342  *
1343  * This function builds an skb around an existing Rx buffer, taking care
1344  * to set up the skb correctly and avoid any memcpy overhead.
1345  */
1346 static struct sk_buff *iavf_build_skb(struct iavf_ring *rx_ring,
1347 				      struct iavf_rx_buffer *rx_buffer,
1348 				      unsigned int size)
1349 {
1350 	void *va;
1351 #if (PAGE_SIZE < 8192)
1352 	unsigned int truesize = iavf_rx_pg_size(rx_ring) / 2;
1353 #else
1354 	unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1355 				SKB_DATA_ALIGN(IAVF_SKB_PAD + size);
1356 #endif
1357 	struct sk_buff *skb;
1358 
1359 	if (!rx_buffer)
1360 		return NULL;
1361 	/* prefetch first cache line of first page */
1362 	va = page_address(rx_buffer->page) + rx_buffer->page_offset;
1363 	net_prefetch(va);
1364 
1365 	/* build an skb around the page buffer */
1366 	skb = build_skb(va - IAVF_SKB_PAD, truesize);
1367 	if (unlikely(!skb))
1368 		return NULL;
1369 
1370 	/* update pointers within the skb to store the data */
1371 	skb_reserve(skb, IAVF_SKB_PAD);
1372 	__skb_put(skb, size);
1373 
1374 	/* buffer is used by skb, update page_offset */
1375 #if (PAGE_SIZE < 8192)
1376 	rx_buffer->page_offset ^= truesize;
1377 #else
1378 	rx_buffer->page_offset += truesize;
1379 #endif
1380 
1381 	return skb;
1382 }
1383 
1384 /**
1385  * iavf_put_rx_buffer - Clean up used buffer and either recycle or free
1386  * @rx_ring: rx descriptor ring to transact packets on
1387  * @rx_buffer: rx buffer to pull data from
1388  *
1389  * This function will clean up the contents of the rx_buffer.  It will
1390  * either recycle the buffer or unmap it and free the associated resources.
1391  */
1392 static void iavf_put_rx_buffer(struct iavf_ring *rx_ring,
1393 			       struct iavf_rx_buffer *rx_buffer)
1394 {
1395 	if (!rx_buffer)
1396 		return;
1397 
1398 	if (iavf_can_reuse_rx_page(rx_buffer)) {
1399 		/* hand second half of page back to the ring */
1400 		iavf_reuse_rx_page(rx_ring, rx_buffer);
1401 		rx_ring->rx_stats.page_reuse_count++;
1402 	} else {
1403 		/* we are not reusing the buffer so unmap it */
1404 		dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
1405 				     iavf_rx_pg_size(rx_ring),
1406 				     DMA_FROM_DEVICE, IAVF_RX_DMA_ATTR);
1407 		__page_frag_cache_drain(rx_buffer->page,
1408 					rx_buffer->pagecnt_bias);
1409 	}
1410 
1411 	/* clear contents of buffer_info */
1412 	rx_buffer->page = NULL;
1413 }
1414 
1415 /**
1416  * iavf_is_non_eop - process handling of non-EOP buffers
1417  * @rx_ring: Rx ring being processed
1418  * @rx_desc: Rx descriptor for current buffer
1419  * @skb: Current socket buffer containing buffer in progress
1420  *
1421  * This function updates next to clean.  If the buffer is an EOP buffer
1422  * this function exits returning false, otherwise it will place the
1423  * sk_buff in the next buffer to be chained and return true indicating
1424  * that this is in fact a non-EOP buffer.
1425  **/
1426 static bool iavf_is_non_eop(struct iavf_ring *rx_ring,
1427 			    union iavf_rx_desc *rx_desc,
1428 			    struct sk_buff *skb)
1429 {
1430 	u32 ntc = rx_ring->next_to_clean + 1;
1431 
1432 	/* fetch, update, and store next to clean */
1433 	ntc = (ntc < rx_ring->count) ? ntc : 0;
1434 	rx_ring->next_to_clean = ntc;
1435 
1436 	prefetch(IAVF_RX_DESC(rx_ring, ntc));
1437 
1438 	/* if we are the last buffer then there is nothing else to do */
1439 #define IAVF_RXD_EOF BIT(IAVF_RX_DESC_STATUS_EOF_SHIFT)
1440 	if (likely(iavf_test_staterr(rx_desc, IAVF_RXD_EOF)))
1441 		return false;
1442 
1443 	rx_ring->rx_stats.non_eop_descs++;
1444 
1445 	return true;
1446 }
1447 
1448 /**
1449  * iavf_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1450  * @rx_ring: rx descriptor ring to transact packets on
1451  * @budget: Total limit on number of packets to process
1452  *
1453  * This function provides a "bounce buffer" approach to Rx interrupt
1454  * processing.  The advantage to this is that on systems that have
1455  * expensive overhead for IOMMU access this provides a means of avoiding
1456  * it by maintaining the mapping of the page to the system.
1457  *
1458  * Returns amount of work completed
1459  **/
1460 static int iavf_clean_rx_irq(struct iavf_ring *rx_ring, int budget)
1461 {
1462 	unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1463 	struct sk_buff *skb = rx_ring->skb;
1464 	u16 cleaned_count = IAVF_DESC_UNUSED(rx_ring);
1465 	bool failure = false;
1466 
1467 	while (likely(total_rx_packets < (unsigned int)budget)) {
1468 		struct iavf_rx_buffer *rx_buffer;
1469 		union iavf_rx_desc *rx_desc;
1470 		unsigned int size;
1471 		u16 vlan_tag;
1472 		u8 rx_ptype;
1473 		u64 qword;
1474 
1475 		/* return some buffers to hardware, one at a time is too slow */
1476 		if (cleaned_count >= IAVF_RX_BUFFER_WRITE) {
1477 			failure = failure ||
1478 				  iavf_alloc_rx_buffers(rx_ring, cleaned_count);
1479 			cleaned_count = 0;
1480 		}
1481 
1482 		rx_desc = IAVF_RX_DESC(rx_ring, rx_ring->next_to_clean);
1483 
1484 		/* status_error_len will always be zero for unused descriptors
1485 		 * because it's cleared in cleanup, and overlaps with hdr_addr
1486 		 * which is always zero because packet split isn't used, if the
1487 		 * hardware wrote DD then the length will be non-zero
1488 		 */
1489 		qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1490 
1491 		/* This memory barrier is needed to keep us from reading
1492 		 * any other fields out of the rx_desc until we have
1493 		 * verified the descriptor has been written back.
1494 		 */
1495 		dma_rmb();
1496 #define IAVF_RXD_DD BIT(IAVF_RX_DESC_STATUS_DD_SHIFT)
1497 		if (!iavf_test_staterr(rx_desc, IAVF_RXD_DD))
1498 			break;
1499 
1500 		size = (qword & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1501 		       IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1502 
1503 		iavf_trace(clean_rx_irq, rx_ring, rx_desc, skb);
1504 		rx_buffer = iavf_get_rx_buffer(rx_ring, size);
1505 
1506 		/* retrieve a buffer from the ring */
1507 		if (skb)
1508 			iavf_add_rx_frag(rx_ring, rx_buffer, skb, size);
1509 		else if (ring_uses_build_skb(rx_ring))
1510 			skb = iavf_build_skb(rx_ring, rx_buffer, size);
1511 		else
1512 			skb = iavf_construct_skb(rx_ring, rx_buffer, size);
1513 
1514 		/* exit if we failed to retrieve a buffer */
1515 		if (!skb) {
1516 			rx_ring->rx_stats.alloc_buff_failed++;
1517 			if (rx_buffer)
1518 				rx_buffer->pagecnt_bias++;
1519 			break;
1520 		}
1521 
1522 		iavf_put_rx_buffer(rx_ring, rx_buffer);
1523 		cleaned_count++;
1524 
1525 		if (iavf_is_non_eop(rx_ring, rx_desc, skb))
1526 			continue;
1527 
1528 		/* ERR_MASK will only have valid bits if EOP set, and
1529 		 * what we are doing here is actually checking
1530 		 * IAVF_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1531 		 * the error field
1532 		 */
1533 		if (unlikely(iavf_test_staterr(rx_desc, BIT(IAVF_RXD_QW1_ERROR_SHIFT)))) {
1534 			dev_kfree_skb_any(skb);
1535 			skb = NULL;
1536 			continue;
1537 		}
1538 
1539 		if (iavf_cleanup_headers(rx_ring, skb)) {
1540 			skb = NULL;
1541 			continue;
1542 		}
1543 
1544 		/* probably a little skewed due to removing CRC */
1545 		total_rx_bytes += skb->len;
1546 
1547 		qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1548 		rx_ptype = (qword & IAVF_RXD_QW1_PTYPE_MASK) >>
1549 			   IAVF_RXD_QW1_PTYPE_SHIFT;
1550 
1551 		/* populate checksum, VLAN, and protocol */
1552 		iavf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);
1553 
1554 
1555 		vlan_tag = (qword & BIT(IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1556 			   le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0;
1557 
1558 		iavf_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb);
1559 		iavf_receive_skb(rx_ring, skb, vlan_tag);
1560 		skb = NULL;
1561 
1562 		/* update budget accounting */
1563 		total_rx_packets++;
1564 	}
1565 
1566 	rx_ring->skb = skb;
1567 
1568 	u64_stats_update_begin(&rx_ring->syncp);
1569 	rx_ring->stats.packets += total_rx_packets;
1570 	rx_ring->stats.bytes += total_rx_bytes;
1571 	u64_stats_update_end(&rx_ring->syncp);
1572 	rx_ring->q_vector->rx.total_packets += total_rx_packets;
1573 	rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1574 
1575 	/* guarantee a trip back through this routine if there was a failure */
1576 	return failure ? budget : (int)total_rx_packets;
1577 }
1578 
1579 static inline u32 iavf_buildreg_itr(const int type, u16 itr)
1580 {
1581 	u32 val;
1582 
1583 	/* We don't bother with setting the CLEARPBA bit as the data sheet
1584 	 * points out doing so is "meaningless since it was already
1585 	 * auto-cleared". The auto-clearing happens when the interrupt is
1586 	 * asserted.
1587 	 *
1588 	 * Hardware errata 28 for also indicates that writing to a
1589 	 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
1590 	 * an event in the PBA anyway so we need to rely on the automask
1591 	 * to hold pending events for us until the interrupt is re-enabled
1592 	 *
1593 	 * The itr value is reported in microseconds, and the register
1594 	 * value is recorded in 2 microsecond units. For this reason we
1595 	 * only need to shift by the interval shift - 1 instead of the
1596 	 * full value.
1597 	 */
1598 	itr &= IAVF_ITR_MASK;
1599 
1600 	val = IAVF_VFINT_DYN_CTLN1_INTENA_MASK |
1601 	      (type << IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1602 	      (itr << (IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT - 1));
1603 
1604 	return val;
1605 }
1606 
1607 /* a small macro to shorten up some long lines */
1608 #define INTREG IAVF_VFINT_DYN_CTLN1
1609 
1610 /* The act of updating the ITR will cause it to immediately trigger. In order
1611  * to prevent this from throwing off adaptive update statistics we defer the
1612  * update so that it can only happen so often. So after either Tx or Rx are
1613  * updated we make the adaptive scheme wait until either the ITR completely
1614  * expires via the next_update expiration or we have been through at least
1615  * 3 interrupts.
1616  */
1617 #define ITR_COUNTDOWN_START 3
1618 
1619 /**
1620  * iavf_update_enable_itr - Update itr and re-enable MSIX interrupt
1621  * @vsi: the VSI we care about
1622  * @q_vector: q_vector for which itr is being updated and interrupt enabled
1623  *
1624  **/
1625 static inline void iavf_update_enable_itr(struct iavf_vsi *vsi,
1626 					  struct iavf_q_vector *q_vector)
1627 {
1628 	struct iavf_hw *hw = &vsi->back->hw;
1629 	u32 intval;
1630 
1631 	/* These will do nothing if dynamic updates are not enabled */
1632 	iavf_update_itr(q_vector, &q_vector->tx);
1633 	iavf_update_itr(q_vector, &q_vector->rx);
1634 
1635 	/* This block of logic allows us to get away with only updating
1636 	 * one ITR value with each interrupt. The idea is to perform a
1637 	 * pseudo-lazy update with the following criteria.
1638 	 *
1639 	 * 1. Rx is given higher priority than Tx if both are in same state
1640 	 * 2. If we must reduce an ITR that is given highest priority.
1641 	 * 3. We then give priority to increasing ITR based on amount.
1642 	 */
1643 	if (q_vector->rx.target_itr < q_vector->rx.current_itr) {
1644 		/* Rx ITR needs to be reduced, this is highest priority */
1645 		intval = iavf_buildreg_itr(IAVF_RX_ITR,
1646 					   q_vector->rx.target_itr);
1647 		q_vector->rx.current_itr = q_vector->rx.target_itr;
1648 		q_vector->itr_countdown = ITR_COUNTDOWN_START;
1649 	} else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) ||
1650 		   ((q_vector->rx.target_itr - q_vector->rx.current_itr) <
1651 		    (q_vector->tx.target_itr - q_vector->tx.current_itr))) {
1652 		/* Tx ITR needs to be reduced, this is second priority
1653 		 * Tx ITR needs to be increased more than Rx, fourth priority
1654 		 */
1655 		intval = iavf_buildreg_itr(IAVF_TX_ITR,
1656 					   q_vector->tx.target_itr);
1657 		q_vector->tx.current_itr = q_vector->tx.target_itr;
1658 		q_vector->itr_countdown = ITR_COUNTDOWN_START;
1659 	} else if (q_vector->rx.current_itr != q_vector->rx.target_itr) {
1660 		/* Rx ITR needs to be increased, third priority */
1661 		intval = iavf_buildreg_itr(IAVF_RX_ITR,
1662 					   q_vector->rx.target_itr);
1663 		q_vector->rx.current_itr = q_vector->rx.target_itr;
1664 		q_vector->itr_countdown = ITR_COUNTDOWN_START;
1665 	} else {
1666 		/* No ITR update, lowest priority */
1667 		intval = iavf_buildreg_itr(IAVF_ITR_NONE, 0);
1668 		if (q_vector->itr_countdown)
1669 			q_vector->itr_countdown--;
1670 	}
1671 
1672 	if (!test_bit(__IAVF_VSI_DOWN, vsi->state))
1673 		wr32(hw, INTREG(q_vector->reg_idx), intval);
1674 }
1675 
1676 /**
1677  * iavf_napi_poll - NAPI polling Rx/Tx cleanup routine
1678  * @napi: napi struct with our devices info in it
1679  * @budget: amount of work driver is allowed to do this pass, in packets
1680  *
1681  * This function will clean all queues associated with a q_vector.
1682  *
1683  * Returns the amount of work done
1684  **/
1685 int iavf_napi_poll(struct napi_struct *napi, int budget)
1686 {
1687 	struct iavf_q_vector *q_vector =
1688 			       container_of(napi, struct iavf_q_vector, napi);
1689 	struct iavf_vsi *vsi = q_vector->vsi;
1690 	struct iavf_ring *ring;
1691 	bool clean_complete = true;
1692 	bool arm_wb = false;
1693 	int budget_per_ring;
1694 	int work_done = 0;
1695 
1696 	if (test_bit(__IAVF_VSI_DOWN, vsi->state)) {
1697 		napi_complete(napi);
1698 		return 0;
1699 	}
1700 
1701 	/* Since the actual Tx work is minimal, we can give the Tx a larger
1702 	 * budget and be more aggressive about cleaning up the Tx descriptors.
1703 	 */
1704 	iavf_for_each_ring(ring, q_vector->tx) {
1705 		if (!iavf_clean_tx_irq(vsi, ring, budget)) {
1706 			clean_complete = false;
1707 			continue;
1708 		}
1709 		arm_wb |= ring->arm_wb;
1710 		ring->arm_wb = false;
1711 	}
1712 
1713 	/* Handle case where we are called by netpoll with a budget of 0 */
1714 	if (budget <= 0)
1715 		goto tx_only;
1716 
1717 	/* We attempt to distribute budget to each Rx queue fairly, but don't
1718 	 * allow the budget to go below 1 because that would exit polling early.
1719 	 */
1720 	budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1721 
1722 	iavf_for_each_ring(ring, q_vector->rx) {
1723 		int cleaned = iavf_clean_rx_irq(ring, budget_per_ring);
1724 
1725 		work_done += cleaned;
1726 		/* if we clean as many as budgeted, we must not be done */
1727 		if (cleaned >= budget_per_ring)
1728 			clean_complete = false;
1729 	}
1730 
1731 	/* If work not completed, return budget and polling will return */
1732 	if (!clean_complete) {
1733 		int cpu_id = smp_processor_id();
1734 
1735 		/* It is possible that the interrupt affinity has changed but,
1736 		 * if the cpu is pegged at 100%, polling will never exit while
1737 		 * traffic continues and the interrupt will be stuck on this
1738 		 * cpu.  We check to make sure affinity is correct before we
1739 		 * continue to poll, otherwise we must stop polling so the
1740 		 * interrupt can move to the correct cpu.
1741 		 */
1742 		if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) {
1743 			/* Tell napi that we are done polling */
1744 			napi_complete_done(napi, work_done);
1745 
1746 			/* Force an interrupt */
1747 			iavf_force_wb(vsi, q_vector);
1748 
1749 			/* Return budget-1 so that polling stops */
1750 			return budget - 1;
1751 		}
1752 tx_only:
1753 		if (arm_wb) {
1754 			q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1755 			iavf_enable_wb_on_itr(vsi, q_vector);
1756 		}
1757 		return budget;
1758 	}
1759 
1760 	if (vsi->back->flags & IAVF_TXR_FLAGS_WB_ON_ITR)
1761 		q_vector->arm_wb_state = false;
1762 
1763 	/* Exit the polling mode, but don't re-enable interrupts if stack might
1764 	 * poll us due to busy-polling
1765 	 */
1766 	if (likely(napi_complete_done(napi, work_done)))
1767 		iavf_update_enable_itr(vsi, q_vector);
1768 
1769 	return min(work_done, budget - 1);
1770 }
1771 
1772 /**
1773  * iavf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1774  * @skb:     send buffer
1775  * @tx_ring: ring to send buffer on
1776  * @flags:   the tx flags to be set
1777  *
1778  * Checks the skb and set up correspondingly several generic transmit flags
1779  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1780  *
1781  * Returns error code indicate the frame should be dropped upon error and the
1782  * otherwise  returns 0 to indicate the flags has been set properly.
1783  **/
1784 static inline int iavf_tx_prepare_vlan_flags(struct sk_buff *skb,
1785 					     struct iavf_ring *tx_ring,
1786 					     u32 *flags)
1787 {
1788 	__be16 protocol = skb->protocol;
1789 	u32  tx_flags = 0;
1790 
1791 	if (protocol == htons(ETH_P_8021Q) &&
1792 	    !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1793 		/* When HW VLAN acceleration is turned off by the user the
1794 		 * stack sets the protocol to 8021q so that the driver
1795 		 * can take any steps required to support the SW only
1796 		 * VLAN handling.  In our case the driver doesn't need
1797 		 * to take any further steps so just set the protocol
1798 		 * to the encapsulated ethertype.
1799 		 */
1800 		skb->protocol = vlan_get_protocol(skb);
1801 		goto out;
1802 	}
1803 
1804 	/* if we have a HW VLAN tag being added, default to the HW one */
1805 	if (skb_vlan_tag_present(skb)) {
1806 		tx_flags |= skb_vlan_tag_get(skb) << IAVF_TX_FLAGS_VLAN_SHIFT;
1807 		tx_flags |= IAVF_TX_FLAGS_HW_VLAN;
1808 	/* else if it is a SW VLAN, check the next protocol and store the tag */
1809 	} else if (protocol == htons(ETH_P_8021Q)) {
1810 		struct vlan_hdr *vhdr, _vhdr;
1811 
1812 		vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1813 		if (!vhdr)
1814 			return -EINVAL;
1815 
1816 		protocol = vhdr->h_vlan_encapsulated_proto;
1817 		tx_flags |= ntohs(vhdr->h_vlan_TCI) << IAVF_TX_FLAGS_VLAN_SHIFT;
1818 		tx_flags |= IAVF_TX_FLAGS_SW_VLAN;
1819 	}
1820 
1821 out:
1822 	*flags = tx_flags;
1823 	return 0;
1824 }
1825 
1826 /**
1827  * iavf_tso - set up the tso context descriptor
1828  * @first:    pointer to first Tx buffer for xmit
1829  * @hdr_len:  ptr to the size of the packet header
1830  * @cd_type_cmd_tso_mss: Quad Word 1
1831  *
1832  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1833  **/
1834 static int iavf_tso(struct iavf_tx_buffer *first, u8 *hdr_len,
1835 		    u64 *cd_type_cmd_tso_mss)
1836 {
1837 	struct sk_buff *skb = first->skb;
1838 	u64 cd_cmd, cd_tso_len, cd_mss;
1839 	union {
1840 		struct iphdr *v4;
1841 		struct ipv6hdr *v6;
1842 		unsigned char *hdr;
1843 	} ip;
1844 	union {
1845 		struct tcphdr *tcp;
1846 		struct udphdr *udp;
1847 		unsigned char *hdr;
1848 	} l4;
1849 	u32 paylen, l4_offset;
1850 	u16 gso_segs, gso_size;
1851 	int err;
1852 
1853 	if (skb->ip_summed != CHECKSUM_PARTIAL)
1854 		return 0;
1855 
1856 	if (!skb_is_gso(skb))
1857 		return 0;
1858 
1859 	err = skb_cow_head(skb, 0);
1860 	if (err < 0)
1861 		return err;
1862 
1863 	ip.hdr = skb_network_header(skb);
1864 	l4.hdr = skb_transport_header(skb);
1865 
1866 	/* initialize outer IP header fields */
1867 	if (ip.v4->version == 4) {
1868 		ip.v4->tot_len = 0;
1869 		ip.v4->check = 0;
1870 	} else {
1871 		ip.v6->payload_len = 0;
1872 	}
1873 
1874 	if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1875 					 SKB_GSO_GRE_CSUM |
1876 					 SKB_GSO_IPXIP4 |
1877 					 SKB_GSO_IPXIP6 |
1878 					 SKB_GSO_UDP_TUNNEL |
1879 					 SKB_GSO_UDP_TUNNEL_CSUM)) {
1880 		if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
1881 		    (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
1882 			l4.udp->len = 0;
1883 
1884 			/* determine offset of outer transport header */
1885 			l4_offset = l4.hdr - skb->data;
1886 
1887 			/* remove payload length from outer checksum */
1888 			paylen = skb->len - l4_offset;
1889 			csum_replace_by_diff(&l4.udp->check,
1890 					     (__force __wsum)htonl(paylen));
1891 		}
1892 
1893 		/* reset pointers to inner headers */
1894 		ip.hdr = skb_inner_network_header(skb);
1895 		l4.hdr = skb_inner_transport_header(skb);
1896 
1897 		/* initialize inner IP header fields */
1898 		if (ip.v4->version == 4) {
1899 			ip.v4->tot_len = 0;
1900 			ip.v4->check = 0;
1901 		} else {
1902 			ip.v6->payload_len = 0;
1903 		}
1904 	}
1905 
1906 	/* determine offset of inner transport header */
1907 	l4_offset = l4.hdr - skb->data;
1908 	/* remove payload length from inner checksum */
1909 	paylen = skb->len - l4_offset;
1910 
1911 	if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1912 		csum_replace_by_diff(&l4.udp->check,
1913 				     (__force __wsum)htonl(paylen));
1914 		/* compute length of UDP segmentation header */
1915 		*hdr_len = (u8)sizeof(l4.udp) + l4_offset;
1916 	} else {
1917 		csum_replace_by_diff(&l4.tcp->check,
1918 				     (__force __wsum)htonl(paylen));
1919 		/* compute length of TCP segmentation header */
1920 		*hdr_len = (u8)((l4.tcp->doff * 4) + l4_offset);
1921 	}
1922 
1923 	/* pull values out of skb_shinfo */
1924 	gso_size = skb_shinfo(skb)->gso_size;
1925 	gso_segs = skb_shinfo(skb)->gso_segs;
1926 
1927 	/* update GSO size and bytecount with header size */
1928 	first->gso_segs = gso_segs;
1929 	first->bytecount += (first->gso_segs - 1) * *hdr_len;
1930 
1931 	/* find the field values */
1932 	cd_cmd = IAVF_TX_CTX_DESC_TSO;
1933 	cd_tso_len = skb->len - *hdr_len;
1934 	cd_mss = gso_size;
1935 	*cd_type_cmd_tso_mss |= (cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
1936 				(cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1937 				(cd_mss << IAVF_TXD_CTX_QW1_MSS_SHIFT);
1938 	return 1;
1939 }
1940 
1941 /**
1942  * iavf_tx_enable_csum - Enable Tx checksum offloads
1943  * @skb: send buffer
1944  * @tx_flags: pointer to Tx flags currently set
1945  * @td_cmd: Tx descriptor command bits to set
1946  * @td_offset: Tx descriptor header offsets to set
1947  * @tx_ring: Tx descriptor ring
1948  * @cd_tunneling: ptr to context desc bits
1949  **/
1950 static int iavf_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1951 			       u32 *td_cmd, u32 *td_offset,
1952 			       struct iavf_ring *tx_ring,
1953 			       u32 *cd_tunneling)
1954 {
1955 	union {
1956 		struct iphdr *v4;
1957 		struct ipv6hdr *v6;
1958 		unsigned char *hdr;
1959 	} ip;
1960 	union {
1961 		struct tcphdr *tcp;
1962 		struct udphdr *udp;
1963 		unsigned char *hdr;
1964 	} l4;
1965 	unsigned char *exthdr;
1966 	u32 offset, cmd = 0;
1967 	__be16 frag_off;
1968 	u8 l4_proto = 0;
1969 
1970 	if (skb->ip_summed != CHECKSUM_PARTIAL)
1971 		return 0;
1972 
1973 	ip.hdr = skb_network_header(skb);
1974 	l4.hdr = skb_transport_header(skb);
1975 
1976 	/* compute outer L2 header size */
1977 	offset = ((ip.hdr - skb->data) / 2) << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
1978 
1979 	if (skb->encapsulation) {
1980 		u32 tunnel = 0;
1981 		/* define outer network header type */
1982 		if (*tx_flags & IAVF_TX_FLAGS_IPV4) {
1983 			tunnel |= (*tx_flags & IAVF_TX_FLAGS_TSO) ?
1984 				  IAVF_TX_CTX_EXT_IP_IPV4 :
1985 				  IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1986 
1987 			l4_proto = ip.v4->protocol;
1988 		} else if (*tx_flags & IAVF_TX_FLAGS_IPV6) {
1989 			tunnel |= IAVF_TX_CTX_EXT_IP_IPV6;
1990 
1991 			exthdr = ip.hdr + sizeof(*ip.v6);
1992 			l4_proto = ip.v6->nexthdr;
1993 			if (l4.hdr != exthdr)
1994 				ipv6_skip_exthdr(skb, exthdr - skb->data,
1995 						 &l4_proto, &frag_off);
1996 		}
1997 
1998 		/* define outer transport */
1999 		switch (l4_proto) {
2000 		case IPPROTO_UDP:
2001 			tunnel |= IAVF_TXD_CTX_UDP_TUNNELING;
2002 			*tx_flags |= IAVF_TX_FLAGS_VXLAN_TUNNEL;
2003 			break;
2004 		case IPPROTO_GRE:
2005 			tunnel |= IAVF_TXD_CTX_GRE_TUNNELING;
2006 			*tx_flags |= IAVF_TX_FLAGS_VXLAN_TUNNEL;
2007 			break;
2008 		case IPPROTO_IPIP:
2009 		case IPPROTO_IPV6:
2010 			*tx_flags |= IAVF_TX_FLAGS_VXLAN_TUNNEL;
2011 			l4.hdr = skb_inner_network_header(skb);
2012 			break;
2013 		default:
2014 			if (*tx_flags & IAVF_TX_FLAGS_TSO)
2015 				return -1;
2016 
2017 			skb_checksum_help(skb);
2018 			return 0;
2019 		}
2020 
2021 		/* compute outer L3 header size */
2022 		tunnel |= ((l4.hdr - ip.hdr) / 4) <<
2023 			  IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
2024 
2025 		/* switch IP header pointer from outer to inner header */
2026 		ip.hdr = skb_inner_network_header(skb);
2027 
2028 		/* compute tunnel header size */
2029 		tunnel |= ((ip.hdr - l4.hdr) / 2) <<
2030 			  IAVF_TXD_CTX_QW0_NATLEN_SHIFT;
2031 
2032 		/* indicate if we need to offload outer UDP header */
2033 		if ((*tx_flags & IAVF_TX_FLAGS_TSO) &&
2034 		    !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
2035 		    (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
2036 			tunnel |= IAVF_TXD_CTX_QW0_L4T_CS_MASK;
2037 
2038 		/* record tunnel offload values */
2039 		*cd_tunneling |= tunnel;
2040 
2041 		/* switch L4 header pointer from outer to inner */
2042 		l4.hdr = skb_inner_transport_header(skb);
2043 		l4_proto = 0;
2044 
2045 		/* reset type as we transition from outer to inner headers */
2046 		*tx_flags &= ~(IAVF_TX_FLAGS_IPV4 | IAVF_TX_FLAGS_IPV6);
2047 		if (ip.v4->version == 4)
2048 			*tx_flags |= IAVF_TX_FLAGS_IPV4;
2049 		if (ip.v6->version == 6)
2050 			*tx_flags |= IAVF_TX_FLAGS_IPV6;
2051 	}
2052 
2053 	/* Enable IP checksum offloads */
2054 	if (*tx_flags & IAVF_TX_FLAGS_IPV4) {
2055 		l4_proto = ip.v4->protocol;
2056 		/* the stack computes the IP header already, the only time we
2057 		 * need the hardware to recompute it is in the case of TSO.
2058 		 */
2059 		cmd |= (*tx_flags & IAVF_TX_FLAGS_TSO) ?
2060 		       IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM :
2061 		       IAVF_TX_DESC_CMD_IIPT_IPV4;
2062 	} else if (*tx_flags & IAVF_TX_FLAGS_IPV6) {
2063 		cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
2064 
2065 		exthdr = ip.hdr + sizeof(*ip.v6);
2066 		l4_proto = ip.v6->nexthdr;
2067 		if (l4.hdr != exthdr)
2068 			ipv6_skip_exthdr(skb, exthdr - skb->data,
2069 					 &l4_proto, &frag_off);
2070 	}
2071 
2072 	/* compute inner L3 header size */
2073 	offset |= ((l4.hdr - ip.hdr) / 4) << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
2074 
2075 	/* Enable L4 checksum offloads */
2076 	switch (l4_proto) {
2077 	case IPPROTO_TCP:
2078 		/* enable checksum offloads */
2079 		cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
2080 		offset |= l4.tcp->doff << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2081 		break;
2082 	case IPPROTO_SCTP:
2083 		/* enable SCTP checksum offload */
2084 		cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
2085 		offset |= (sizeof(struct sctphdr) >> 2) <<
2086 			  IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2087 		break;
2088 	case IPPROTO_UDP:
2089 		/* enable UDP checksum offload */
2090 		cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
2091 		offset |= (sizeof(struct udphdr) >> 2) <<
2092 			  IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2093 		break;
2094 	default:
2095 		if (*tx_flags & IAVF_TX_FLAGS_TSO)
2096 			return -1;
2097 		skb_checksum_help(skb);
2098 		return 0;
2099 	}
2100 
2101 	*td_cmd |= cmd;
2102 	*td_offset |= offset;
2103 
2104 	return 1;
2105 }
2106 
2107 /**
2108  * iavf_create_tx_ctx - Build the Tx context descriptor
2109  * @tx_ring:  ring to create the descriptor on
2110  * @cd_type_cmd_tso_mss: Quad Word 1
2111  * @cd_tunneling: Quad Word 0 - bits 0-31
2112  * @cd_l2tag2: Quad Word 0 - bits 32-63
2113  **/
2114 static void iavf_create_tx_ctx(struct iavf_ring *tx_ring,
2115 			       const u64 cd_type_cmd_tso_mss,
2116 			       const u32 cd_tunneling, const u32 cd_l2tag2)
2117 {
2118 	struct iavf_tx_context_desc *context_desc;
2119 	int i = tx_ring->next_to_use;
2120 
2121 	if ((cd_type_cmd_tso_mss == IAVF_TX_DESC_DTYPE_CONTEXT) &&
2122 	    !cd_tunneling && !cd_l2tag2)
2123 		return;
2124 
2125 	/* grab the next descriptor */
2126 	context_desc = IAVF_TX_CTXTDESC(tx_ring, i);
2127 
2128 	i++;
2129 	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2130 
2131 	/* cpu_to_le32 and assign to struct fields */
2132 	context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
2133 	context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
2134 	context_desc->rsvd = cpu_to_le16(0);
2135 	context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
2136 }
2137 
2138 /**
2139  * __iavf_chk_linearize - Check if there are more than 8 buffers per packet
2140  * @skb:      send buffer
2141  *
2142  * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
2143  * and so we need to figure out the cases where we need to linearize the skb.
2144  *
2145  * For TSO we need to count the TSO header and segment payload separately.
2146  * As such we need to check cases where we have 7 fragments or more as we
2147  * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
2148  * the segment payload in the first descriptor, and another 7 for the
2149  * fragments.
2150  **/
2151 bool __iavf_chk_linearize(struct sk_buff *skb)
2152 {
2153 	const skb_frag_t *frag, *stale;
2154 	int nr_frags, sum;
2155 
2156 	/* no need to check if number of frags is less than 7 */
2157 	nr_frags = skb_shinfo(skb)->nr_frags;
2158 	if (nr_frags < (IAVF_MAX_BUFFER_TXD - 1))
2159 		return false;
2160 
2161 	/* We need to walk through the list and validate that each group
2162 	 * of 6 fragments totals at least gso_size.
2163 	 */
2164 	nr_frags -= IAVF_MAX_BUFFER_TXD - 2;
2165 	frag = &skb_shinfo(skb)->frags[0];
2166 
2167 	/* Initialize size to the negative value of gso_size minus 1.  We
2168 	 * use this as the worst case scenerio in which the frag ahead
2169 	 * of us only provides one byte which is why we are limited to 6
2170 	 * descriptors for a single transmit as the header and previous
2171 	 * fragment are already consuming 2 descriptors.
2172 	 */
2173 	sum = 1 - skb_shinfo(skb)->gso_size;
2174 
2175 	/* Add size of frags 0 through 4 to create our initial sum */
2176 	sum += skb_frag_size(frag++);
2177 	sum += skb_frag_size(frag++);
2178 	sum += skb_frag_size(frag++);
2179 	sum += skb_frag_size(frag++);
2180 	sum += skb_frag_size(frag++);
2181 
2182 	/* Walk through fragments adding latest fragment, testing it, and
2183 	 * then removing stale fragments from the sum.
2184 	 */
2185 	for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
2186 		int stale_size = skb_frag_size(stale);
2187 
2188 		sum += skb_frag_size(frag++);
2189 
2190 		/* The stale fragment may present us with a smaller
2191 		 * descriptor than the actual fragment size. To account
2192 		 * for that we need to remove all the data on the front and
2193 		 * figure out what the remainder would be in the last
2194 		 * descriptor associated with the fragment.
2195 		 */
2196 		if (stale_size > IAVF_MAX_DATA_PER_TXD) {
2197 			int align_pad = -(skb_frag_off(stale)) &
2198 					(IAVF_MAX_READ_REQ_SIZE - 1);
2199 
2200 			sum -= align_pad;
2201 			stale_size -= align_pad;
2202 
2203 			do {
2204 				sum -= IAVF_MAX_DATA_PER_TXD_ALIGNED;
2205 				stale_size -= IAVF_MAX_DATA_PER_TXD_ALIGNED;
2206 			} while (stale_size > IAVF_MAX_DATA_PER_TXD);
2207 		}
2208 
2209 		/* if sum is negative we failed to make sufficient progress */
2210 		if (sum < 0)
2211 			return true;
2212 
2213 		if (!nr_frags--)
2214 			break;
2215 
2216 		sum -= stale_size;
2217 	}
2218 
2219 	return false;
2220 }
2221 
2222 /**
2223  * __iavf_maybe_stop_tx - 2nd level check for tx stop conditions
2224  * @tx_ring: the ring to be checked
2225  * @size:    the size buffer we want to assure is available
2226  *
2227  * Returns -EBUSY if a stop is needed, else 0
2228  **/
2229 int __iavf_maybe_stop_tx(struct iavf_ring *tx_ring, int size)
2230 {
2231 	netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2232 	/* Memory barrier before checking head and tail */
2233 	smp_mb();
2234 
2235 	/* Check again in a case another CPU has just made room available. */
2236 	if (likely(IAVF_DESC_UNUSED(tx_ring) < size))
2237 		return -EBUSY;
2238 
2239 	/* A reprieve! - use start_queue because it doesn't call schedule */
2240 	netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
2241 	++tx_ring->tx_stats.restart_queue;
2242 	return 0;
2243 }
2244 
2245 /**
2246  * iavf_tx_map - Build the Tx descriptor
2247  * @tx_ring:  ring to send buffer on
2248  * @skb:      send buffer
2249  * @first:    first buffer info buffer to use
2250  * @tx_flags: collected send information
2251  * @hdr_len:  size of the packet header
2252  * @td_cmd:   the command field in the descriptor
2253  * @td_offset: offset for checksum or crc
2254  **/
2255 static inline void iavf_tx_map(struct iavf_ring *tx_ring, struct sk_buff *skb,
2256 			       struct iavf_tx_buffer *first, u32 tx_flags,
2257 			       const u8 hdr_len, u32 td_cmd, u32 td_offset)
2258 {
2259 	unsigned int data_len = skb->data_len;
2260 	unsigned int size = skb_headlen(skb);
2261 	skb_frag_t *frag;
2262 	struct iavf_tx_buffer *tx_bi;
2263 	struct iavf_tx_desc *tx_desc;
2264 	u16 i = tx_ring->next_to_use;
2265 	u32 td_tag = 0;
2266 	dma_addr_t dma;
2267 
2268 	if (tx_flags & IAVF_TX_FLAGS_HW_VLAN) {
2269 		td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
2270 		td_tag = (tx_flags & IAVF_TX_FLAGS_VLAN_MASK) >>
2271 			 IAVF_TX_FLAGS_VLAN_SHIFT;
2272 	}
2273 
2274 	first->tx_flags = tx_flags;
2275 
2276 	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2277 
2278 	tx_desc = IAVF_TX_DESC(tx_ring, i);
2279 	tx_bi = first;
2280 
2281 	for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
2282 		unsigned int max_data = IAVF_MAX_DATA_PER_TXD_ALIGNED;
2283 
2284 		if (dma_mapping_error(tx_ring->dev, dma))
2285 			goto dma_error;
2286 
2287 		/* record length, and DMA address */
2288 		dma_unmap_len_set(tx_bi, len, size);
2289 		dma_unmap_addr_set(tx_bi, dma, dma);
2290 
2291 		/* align size to end of page */
2292 		max_data += -dma & (IAVF_MAX_READ_REQ_SIZE - 1);
2293 		tx_desc->buffer_addr = cpu_to_le64(dma);
2294 
2295 		while (unlikely(size > IAVF_MAX_DATA_PER_TXD)) {
2296 			tx_desc->cmd_type_offset_bsz =
2297 				build_ctob(td_cmd, td_offset,
2298 					   max_data, td_tag);
2299 
2300 			tx_desc++;
2301 			i++;
2302 
2303 			if (i == tx_ring->count) {
2304 				tx_desc = IAVF_TX_DESC(tx_ring, 0);
2305 				i = 0;
2306 			}
2307 
2308 			dma += max_data;
2309 			size -= max_data;
2310 
2311 			max_data = IAVF_MAX_DATA_PER_TXD_ALIGNED;
2312 			tx_desc->buffer_addr = cpu_to_le64(dma);
2313 		}
2314 
2315 		if (likely(!data_len))
2316 			break;
2317 
2318 		tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2319 							  size, td_tag);
2320 
2321 		tx_desc++;
2322 		i++;
2323 
2324 		if (i == tx_ring->count) {
2325 			tx_desc = IAVF_TX_DESC(tx_ring, 0);
2326 			i = 0;
2327 		}
2328 
2329 		size = skb_frag_size(frag);
2330 		data_len -= size;
2331 
2332 		dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2333 				       DMA_TO_DEVICE);
2334 
2335 		tx_bi = &tx_ring->tx_bi[i];
2336 	}
2337 
2338 	netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
2339 
2340 	i++;
2341 	if (i == tx_ring->count)
2342 		i = 0;
2343 
2344 	tx_ring->next_to_use = i;
2345 
2346 	iavf_maybe_stop_tx(tx_ring, DESC_NEEDED);
2347 
2348 	/* write last descriptor with RS and EOP bits */
2349 	td_cmd |= IAVF_TXD_CMD;
2350 	tx_desc->cmd_type_offset_bsz =
2351 			build_ctob(td_cmd, td_offset, size, td_tag);
2352 
2353 	skb_tx_timestamp(skb);
2354 
2355 	/* Force memory writes to complete before letting h/w know there
2356 	 * are new descriptors to fetch.
2357 	 *
2358 	 * We also use this memory barrier to make certain all of the
2359 	 * status bits have been updated before next_to_watch is written.
2360 	 */
2361 	wmb();
2362 
2363 	/* set next_to_watch value indicating a packet is present */
2364 	first->next_to_watch = tx_desc;
2365 
2366 	/* notify HW of packet */
2367 	if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
2368 		writel(i, tx_ring->tail);
2369 	}
2370 
2371 	return;
2372 
2373 dma_error:
2374 	dev_info(tx_ring->dev, "TX DMA map failed\n");
2375 
2376 	/* clear dma mappings for failed tx_bi map */
2377 	for (;;) {
2378 		tx_bi = &tx_ring->tx_bi[i];
2379 		iavf_unmap_and_free_tx_resource(tx_ring, tx_bi);
2380 		if (tx_bi == first)
2381 			break;
2382 		if (i == 0)
2383 			i = tx_ring->count;
2384 		i--;
2385 	}
2386 
2387 	tx_ring->next_to_use = i;
2388 }
2389 
2390 /**
2391  * iavf_xmit_frame_ring - Sends buffer on Tx ring
2392  * @skb:     send buffer
2393  * @tx_ring: ring to send buffer on
2394  *
2395  * Returns NETDEV_TX_OK if sent, else an error code
2396  **/
2397 static netdev_tx_t iavf_xmit_frame_ring(struct sk_buff *skb,
2398 					struct iavf_ring *tx_ring)
2399 {
2400 	u64 cd_type_cmd_tso_mss = IAVF_TX_DESC_DTYPE_CONTEXT;
2401 	u32 cd_tunneling = 0, cd_l2tag2 = 0;
2402 	struct iavf_tx_buffer *first;
2403 	u32 td_offset = 0;
2404 	u32 tx_flags = 0;
2405 	__be16 protocol;
2406 	u32 td_cmd = 0;
2407 	u8 hdr_len = 0;
2408 	int tso, count;
2409 
2410 	/* prefetch the data, we'll need it later */
2411 	prefetch(skb->data);
2412 
2413 	iavf_trace(xmit_frame_ring, skb, tx_ring);
2414 
2415 	count = iavf_xmit_descriptor_count(skb);
2416 	if (iavf_chk_linearize(skb, count)) {
2417 		if (__skb_linearize(skb)) {
2418 			dev_kfree_skb_any(skb);
2419 			return NETDEV_TX_OK;
2420 		}
2421 		count = iavf_txd_use_count(skb->len);
2422 		tx_ring->tx_stats.tx_linearize++;
2423 	}
2424 
2425 	/* need: 1 descriptor per page * PAGE_SIZE/IAVF_MAX_DATA_PER_TXD,
2426 	 *       + 1 desc for skb_head_len/IAVF_MAX_DATA_PER_TXD,
2427 	 *       + 4 desc gap to avoid the cache line where head is,
2428 	 *       + 1 desc for context descriptor,
2429 	 * otherwise try next time
2430 	 */
2431 	if (iavf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2432 		tx_ring->tx_stats.tx_busy++;
2433 		return NETDEV_TX_BUSY;
2434 	}
2435 
2436 	/* record the location of the first descriptor for this packet */
2437 	first = &tx_ring->tx_bi[tx_ring->next_to_use];
2438 	first->skb = skb;
2439 	first->bytecount = skb->len;
2440 	first->gso_segs = 1;
2441 
2442 	/* prepare the xmit flags */
2443 	if (iavf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2444 		goto out_drop;
2445 
2446 	/* obtain protocol of skb */
2447 	protocol = vlan_get_protocol(skb);
2448 
2449 	/* setup IPv4/IPv6 offloads */
2450 	if (protocol == htons(ETH_P_IP))
2451 		tx_flags |= IAVF_TX_FLAGS_IPV4;
2452 	else if (protocol == htons(ETH_P_IPV6))
2453 		tx_flags |= IAVF_TX_FLAGS_IPV6;
2454 
2455 	tso = iavf_tso(first, &hdr_len, &cd_type_cmd_tso_mss);
2456 
2457 	if (tso < 0)
2458 		goto out_drop;
2459 	else if (tso)
2460 		tx_flags |= IAVF_TX_FLAGS_TSO;
2461 
2462 	/* Always offload the checksum, since it's in the data descriptor */
2463 	tso = iavf_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2464 				  tx_ring, &cd_tunneling);
2465 	if (tso < 0)
2466 		goto out_drop;
2467 
2468 	/* always enable CRC insertion offload */
2469 	td_cmd |= IAVF_TX_DESC_CMD_ICRC;
2470 
2471 	iavf_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2472 			   cd_tunneling, cd_l2tag2);
2473 
2474 	iavf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2475 		    td_cmd, td_offset);
2476 
2477 	return NETDEV_TX_OK;
2478 
2479 out_drop:
2480 	iavf_trace(xmit_frame_ring_drop, first->skb, tx_ring);
2481 	dev_kfree_skb_any(first->skb);
2482 	first->skb = NULL;
2483 	return NETDEV_TX_OK;
2484 }
2485 
2486 /**
2487  * iavf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2488  * @skb:    send buffer
2489  * @netdev: network interface device structure
2490  *
2491  * Returns NETDEV_TX_OK if sent, else an error code
2492  **/
2493 netdev_tx_t iavf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2494 {
2495 	struct iavf_adapter *adapter = netdev_priv(netdev);
2496 	struct iavf_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
2497 
2498 	/* hardware can't handle really short frames, hardware padding works
2499 	 * beyond this point
2500 	 */
2501 	if (unlikely(skb->len < IAVF_MIN_TX_LEN)) {
2502 		if (skb_pad(skb, IAVF_MIN_TX_LEN - skb->len))
2503 			return NETDEV_TX_OK;
2504 		skb->len = IAVF_MIN_TX_LEN;
2505 		skb_set_tail_pointer(skb, IAVF_MIN_TX_LEN);
2506 	}
2507 
2508 	return iavf_xmit_frame_ring(skb, tx_ring);
2509 }
2510