1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_TXRX_H_ 28 #define _I40E_TXRX_H_ 29 30 /* Interrupt Throttling and Rate Limiting Goodies */ 31 32 #define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */ 33 #define I40E_MIN_ITR 0x0001 /* reg uses 2 usec resolution */ 34 #define I40E_ITR_100K 0x0005 35 #define I40E_ITR_50K 0x000A 36 #define I40E_ITR_20K 0x0019 37 #define I40E_ITR_18K 0x001B 38 #define I40E_ITR_8K 0x003E 39 #define I40E_ITR_4K 0x007A 40 #define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */ 41 #define I40E_ITR_RX_DEF I40E_ITR_20K 42 #define I40E_ITR_TX_DEF I40E_ITR_20K 43 #define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ 44 #define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */ 45 #define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */ 46 #define I40E_DEFAULT_IRQ_WORK 256 47 #define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1) 48 #define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC)) 49 #define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1) 50 /* 0x40 is the enable bit for interrupt rate limiting, and must be set if 51 * the value of the rate limit is non-zero 52 */ 53 #define INTRL_ENA BIT(6) 54 #define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2) 55 /** 56 * i40e_intrl_usec_to_reg - convert interrupt rate limit to register 57 * @intrl: interrupt rate limit to convert 58 * 59 * This function converts a decimal interrupt rate limit to the appropriate 60 * register format expected by the firmware when setting interrupt rate limit. 61 */ 62 static inline u16 i40e_intrl_usec_to_reg(int intrl) 63 { 64 if (intrl >> 2) 65 return ((intrl >> 2) | INTRL_ENA); 66 else 67 return 0; 68 } 69 #define I40E_INTRL_8K 125 /* 8000 ints/sec */ 70 #define I40E_INTRL_62K 16 /* 62500 ints/sec */ 71 #define I40E_INTRL_83K 12 /* 83333 ints/sec */ 72 73 #define I40E_QUEUE_END_OF_LIST 0x7FF 74 75 /* this enum matches hardware bits and is meant to be used by DYN_CTLN 76 * registers and QINT registers or more generally anywhere in the manual 77 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 78 * register but instead is a special value meaning "don't update" ITR0/1/2. 79 */ 80 enum i40e_dyn_idx_t { 81 I40E_IDX_ITR0 = 0, 82 I40E_IDX_ITR1 = 1, 83 I40E_IDX_ITR2 = 2, 84 I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 85 }; 86 87 /* these are indexes into ITRN registers */ 88 #define I40E_RX_ITR I40E_IDX_ITR0 89 #define I40E_TX_ITR I40E_IDX_ITR1 90 #define I40E_PE_ITR I40E_IDX_ITR2 91 92 /* Supported RSS offloads */ 93 #define I40E_DEFAULT_RSS_HENA ( \ 94 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 95 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 96 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 97 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 98 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 99 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 100 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 101 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 102 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 103 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 104 BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD)) 105 106 #define I40E_DEFAULT_RSS_HENA_EXPANDED (I40E_DEFAULT_RSS_HENA | \ 107 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 108 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 109 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 110 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 111 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 112 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP)) 113 114 #define i40e_pf_get_default_rss_hena(pf) \ 115 (((pf)->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \ 116 I40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA) 117 118 /* Supported Rx Buffer Sizes (a multiple of 128) */ 119 #define I40E_RXBUFFER_256 256 120 #define I40E_RXBUFFER_1536 1536 /* 128B aligned standard Ethernet frame */ 121 #define I40E_RXBUFFER_2048 2048 122 #define I40E_RXBUFFER_3072 3072 /* Used for large frames w/ padding */ 123 #define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */ 124 125 /* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 126 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, 127 * this adds up to 512 bytes of extra data meaning the smallest allocation 128 * we could have is 1K. 129 * i.e. RXBUFFER_256 --> 960 byte skb (size-1024 slab) 130 * i.e. RXBUFFER_512 --> 1216 byte skb (size-2048 slab) 131 */ 132 #define I40E_RX_HDR_SIZE I40E_RXBUFFER_256 133 #define i40e_rx_desc i40e_32byte_rx_desc 134 135 #define I40E_RX_DMA_ATTR \ 136 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 137 138 /* Attempt to maximize the headroom available for incoming frames. We 139 * use a 2K buffer for receives and need 1536/1534 to store the data for 140 * the frame. This leaves us with 512 bytes of room. From that we need 141 * to deduct the space needed for the shared info and the padding needed 142 * to IP align the frame. 143 * 144 * Note: For cache line sizes 256 or larger this value is going to end 145 * up negative. In these cases we should fall back to the legacy 146 * receive path. 147 */ 148 #if (PAGE_SIZE < 8192) 149 #define I40E_2K_TOO_SMALL_WITH_PADDING \ 150 ((NET_SKB_PAD + I40E_RXBUFFER_1536) > SKB_WITH_OVERHEAD(I40E_RXBUFFER_2048)) 151 152 static inline int i40e_compute_pad(int rx_buf_len) 153 { 154 int page_size, pad_size; 155 156 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); 157 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; 158 159 return pad_size; 160 } 161 162 static inline int i40e_skb_pad(void) 163 { 164 int rx_buf_len; 165 166 /* If a 2K buffer cannot handle a standard Ethernet frame then 167 * optimize padding for a 3K buffer instead of a 1.5K buffer. 168 * 169 * For a 3K buffer we need to add enough padding to allow for 170 * tailroom due to NET_IP_ALIGN possibly shifting us out of 171 * cache-line alignment. 172 */ 173 if (I40E_2K_TOO_SMALL_WITH_PADDING) 174 rx_buf_len = I40E_RXBUFFER_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN); 175 else 176 rx_buf_len = I40E_RXBUFFER_1536; 177 178 /* if needed make room for NET_IP_ALIGN */ 179 rx_buf_len -= NET_IP_ALIGN; 180 181 return i40e_compute_pad(rx_buf_len); 182 } 183 184 #define I40E_SKB_PAD i40e_skb_pad() 185 #else 186 #define I40E_2K_TOO_SMALL_WITH_PADDING false 187 #define I40E_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 188 #endif 189 190 /** 191 * i40e_test_staterr - tests bits in Rx descriptor status and error fields 192 * @rx_desc: pointer to receive descriptor (in le64 format) 193 * @stat_err_bits: value to mask 194 * 195 * This function does some fast chicanery in order to return the 196 * value of the mask which is really only used for boolean tests. 197 * The status_error_len doesn't need to be shifted because it begins 198 * at offset zero. 199 */ 200 static inline bool i40e_test_staterr(union i40e_rx_desc *rx_desc, 201 const u64 stat_err_bits) 202 { 203 return !!(rx_desc->wb.qword1.status_error_len & 204 cpu_to_le64(stat_err_bits)); 205 } 206 207 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 208 #define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 209 #define I40E_RX_INCREMENT(r, i) \ 210 do { \ 211 (i)++; \ 212 if ((i) == (r)->count) \ 213 i = 0; \ 214 r->next_to_clean = i; \ 215 } while (0) 216 217 #define I40E_RX_NEXT_DESC(r, i, n) \ 218 do { \ 219 (i)++; \ 220 if ((i) == (r)->count) \ 221 i = 0; \ 222 (n) = I40E_RX_DESC((r), (i)); \ 223 } while (0) 224 225 #define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \ 226 do { \ 227 I40E_RX_NEXT_DESC((r), (i), (n)); \ 228 prefetch((n)); \ 229 } while (0) 230 231 #define I40E_MAX_BUFFER_TXD 8 232 #define I40E_MIN_TX_LEN 17 233 234 /* The size limit for a transmit buffer in a descriptor is (16K - 1). 235 * In order to align with the read requests we will align the value to 236 * the nearest 4K which represents our maximum read request size. 237 */ 238 #define I40E_MAX_READ_REQ_SIZE 4096 239 #define I40E_MAX_DATA_PER_TXD (16 * 1024 - 1) 240 #define I40E_MAX_DATA_PER_TXD_ALIGNED \ 241 (I40E_MAX_DATA_PER_TXD & ~(I40E_MAX_READ_REQ_SIZE - 1)) 242 243 /** 244 * i40e_txd_use_count - estimate the number of descriptors needed for Tx 245 * @size: transmit request size in bytes 246 * 247 * Due to hardware alignment restrictions (4K alignment), we need to 248 * assume that we can have no more than 12K of data per descriptor, even 249 * though each descriptor can take up to 16K - 1 bytes of aligned memory. 250 * Thus, we need to divide by 12K. But division is slow! Instead, 251 * we decompose the operation into shifts and one relatively cheap 252 * multiply operation. 253 * 254 * To divide by 12K, we first divide by 4K, then divide by 3: 255 * To divide by 4K, shift right by 12 bits 256 * To divide by 3, multiply by 85, then divide by 256 257 * (Divide by 256 is done by shifting right by 8 bits) 258 * Finally, we add one to round up. Because 256 isn't an exact multiple of 259 * 3, we'll underestimate near each multiple of 12K. This is actually more 260 * accurate as we have 4K - 1 of wiggle room that we can fit into the last 261 * segment. For our purposes this is accurate out to 1M which is orders of 262 * magnitude greater than our largest possible GSO size. 263 * 264 * This would then be implemented as: 265 * return (((size >> 12) * 85) >> 8) + 1; 266 * 267 * Since multiplication and division are commutative, we can reorder 268 * operations into: 269 * return ((size * 85) >> 20) + 1; 270 */ 271 static inline unsigned int i40e_txd_use_count(unsigned int size) 272 { 273 return ((size * 85) >> 20) + 1; 274 } 275 276 /* Tx Descriptors needed, worst case */ 277 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 278 #define I40E_MIN_DESC_PENDING 4 279 280 #define I40E_TX_FLAGS_HW_VLAN BIT(1) 281 #define I40E_TX_FLAGS_SW_VLAN BIT(2) 282 #define I40E_TX_FLAGS_TSO BIT(3) 283 #define I40E_TX_FLAGS_IPV4 BIT(4) 284 #define I40E_TX_FLAGS_IPV6 BIT(5) 285 #define I40E_TX_FLAGS_FCCRC BIT(6) 286 #define I40E_TX_FLAGS_FSO BIT(7) 287 #define I40E_TX_FLAGS_TSYN BIT(8) 288 #define I40E_TX_FLAGS_FD_SB BIT(9) 289 #define I40E_TX_FLAGS_UDP_TUNNEL BIT(10) 290 #define I40E_TX_FLAGS_VLAN_MASK 0xffff0000 291 #define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 292 #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29 293 #define I40E_TX_FLAGS_VLAN_SHIFT 16 294 295 struct i40e_tx_buffer { 296 struct i40e_tx_desc *next_to_watch; 297 union { 298 struct sk_buff *skb; 299 void *raw_buf; 300 }; 301 unsigned int bytecount; 302 unsigned short gso_segs; 303 304 DEFINE_DMA_UNMAP_ADDR(dma); 305 DEFINE_DMA_UNMAP_LEN(len); 306 u32 tx_flags; 307 }; 308 309 struct i40e_rx_buffer { 310 dma_addr_t dma; 311 struct page *page; 312 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 313 __u32 page_offset; 314 #else 315 __u16 page_offset; 316 #endif 317 __u16 pagecnt_bias; 318 }; 319 320 struct i40e_queue_stats { 321 u64 packets; 322 u64 bytes; 323 }; 324 325 struct i40e_tx_queue_stats { 326 u64 restart_queue; 327 u64 tx_busy; 328 u64 tx_done_old; 329 u64 tx_linearize; 330 u64 tx_force_wb; 331 }; 332 333 struct i40e_rx_queue_stats { 334 u64 non_eop_descs; 335 u64 alloc_page_failed; 336 u64 alloc_buff_failed; 337 u64 page_reuse_count; 338 u64 realloc_count; 339 }; 340 341 enum i40e_ring_state_t { 342 __I40E_TX_FDIR_INIT_DONE, 343 __I40E_TX_XPS_INIT_DONE, 344 }; 345 346 /* some useful defines for virtchannel interface, which 347 * is the only remaining user of header split 348 */ 349 #define I40E_RX_DTYPE_NO_SPLIT 0 350 #define I40E_RX_DTYPE_HEADER_SPLIT 1 351 #define I40E_RX_DTYPE_SPLIT_ALWAYS 2 352 #define I40E_RX_SPLIT_L2 0x1 353 #define I40E_RX_SPLIT_IP 0x2 354 #define I40E_RX_SPLIT_TCP_UDP 0x4 355 #define I40E_RX_SPLIT_SCTP 0x8 356 357 /* struct that defines a descriptor ring, associated with a VSI */ 358 struct i40e_ring { 359 struct i40e_ring *next; /* pointer to next ring in q_vector */ 360 void *desc; /* Descriptor ring memory */ 361 struct device *dev; /* Used for DMA mapping */ 362 struct net_device *netdev; /* netdev ring maps to */ 363 union { 364 struct i40e_tx_buffer *tx_bi; 365 struct i40e_rx_buffer *rx_bi; 366 }; 367 unsigned long state; 368 u16 queue_index; /* Queue number of ring */ 369 u8 dcb_tc; /* Traffic class of ring */ 370 u8 __iomem *tail; 371 372 /* high bit set means dynamic, use accessor routines to read/write. 373 * hardware only supports 2us resolution for the ITR registers. 374 * these values always store the USER setting, and must be converted 375 * before programming to a register. 376 */ 377 u16 rx_itr_setting; 378 u16 tx_itr_setting; 379 380 u16 count; /* Number of descriptors */ 381 u16 reg_idx; /* HW register index of the ring */ 382 u16 rx_buf_len; 383 384 /* used in interrupt processing */ 385 u16 next_to_use; 386 u16 next_to_clean; 387 388 u8 atr_sample_rate; 389 u8 atr_count; 390 391 bool ring_active; /* is ring online or not */ 392 bool arm_wb; /* do something to arm write back */ 393 u8 packet_stride; 394 395 u16 flags; 396 #define I40E_TXR_FLAGS_WB_ON_ITR BIT(0) 397 #define I40E_RXR_FLAGS_BUILD_SKB_ENABLED BIT(1) 398 399 /* stats structs */ 400 struct i40e_queue_stats stats; 401 struct u64_stats_sync syncp; 402 union { 403 struct i40e_tx_queue_stats tx_stats; 404 struct i40e_rx_queue_stats rx_stats; 405 }; 406 407 unsigned int size; /* length of descriptor ring in bytes */ 408 dma_addr_t dma; /* physical address of ring */ 409 410 struct i40e_vsi *vsi; /* Backreference to associated VSI */ 411 struct i40e_q_vector *q_vector; /* Backreference to associated vector */ 412 413 struct rcu_head rcu; /* to avoid race on free */ 414 u16 next_to_alloc; 415 struct sk_buff *skb; /* When i40e_clean_rx_ring_irq() must 416 * return before it sees the EOP for 417 * the current packet, we save that skb 418 * here and resume receiving this 419 * packet the next time 420 * i40e_clean_rx_ring_irq() is called 421 * for this ring. 422 */ 423 } ____cacheline_internodealigned_in_smp; 424 425 static inline bool ring_uses_build_skb(struct i40e_ring *ring) 426 { 427 return !!(ring->flags & I40E_RXR_FLAGS_BUILD_SKB_ENABLED); 428 } 429 430 static inline void set_ring_build_skb_enabled(struct i40e_ring *ring) 431 { 432 ring->flags |= I40E_RXR_FLAGS_BUILD_SKB_ENABLED; 433 } 434 435 static inline void clear_ring_build_skb_enabled(struct i40e_ring *ring) 436 { 437 ring->flags &= ~I40E_RXR_FLAGS_BUILD_SKB_ENABLED; 438 } 439 440 enum i40e_latency_range { 441 I40E_LOWEST_LATENCY = 0, 442 I40E_LOW_LATENCY = 1, 443 I40E_BULK_LATENCY = 2, 444 I40E_ULTRA_LATENCY = 3, 445 }; 446 447 struct i40e_ring_container { 448 /* array of pointers to rings */ 449 struct i40e_ring *ring; 450 unsigned int total_bytes; /* total bytes processed this int */ 451 unsigned int total_packets; /* total packets processed this int */ 452 u16 count; 453 enum i40e_latency_range latency_range; 454 u16 itr; 455 }; 456 457 /* iterator for handling rings in ring container */ 458 #define i40e_for_each_ring(pos, head) \ 459 for (pos = (head).ring; pos != NULL; pos = pos->next) 460 461 static inline unsigned int i40e_rx_pg_order(struct i40e_ring *ring) 462 { 463 #if (PAGE_SIZE < 8192) 464 if (ring->rx_buf_len > (PAGE_SIZE / 2)) 465 return 1; 466 #endif 467 return 0; 468 } 469 470 #define i40e_rx_pg_size(_ring) (PAGE_SIZE << i40e_rx_pg_order(_ring)) 471 472 bool i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count); 473 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 474 void i40e_clean_tx_ring(struct i40e_ring *tx_ring); 475 void i40e_clean_rx_ring(struct i40e_ring *rx_ring); 476 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring); 477 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring); 478 void i40e_free_tx_resources(struct i40e_ring *tx_ring); 479 void i40e_free_rx_resources(struct i40e_ring *rx_ring); 480 int i40e_napi_poll(struct napi_struct *napi, int budget); 481 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector); 482 u32 i40e_get_tx_pending(struct i40e_ring *ring); 483 int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size); 484 bool __i40e_chk_linearize(struct sk_buff *skb); 485 486 /** 487 * i40e_get_head - Retrieve head from head writeback 488 * @tx_ring: tx ring to fetch head of 489 * 490 * Returns value of Tx ring head based on value stored 491 * in head write-back location 492 **/ 493 static inline u32 i40e_get_head(struct i40e_ring *tx_ring) 494 { 495 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count; 496 497 return le32_to_cpu(*(volatile __le32 *)head); 498 } 499 500 /** 501 * i40e_xmit_descriptor_count - calculate number of Tx descriptors needed 502 * @skb: send buffer 503 * @tx_ring: ring to send buffer on 504 * 505 * Returns number of data descriptors needed for this skb. Returns 0 to indicate 506 * there is not enough descriptors available in this ring since we need at least 507 * one descriptor. 508 **/ 509 static inline int i40e_xmit_descriptor_count(struct sk_buff *skb) 510 { 511 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 512 unsigned int nr_frags = skb_shinfo(skb)->nr_frags; 513 int count = 0, size = skb_headlen(skb); 514 515 for (;;) { 516 count += i40e_txd_use_count(size); 517 518 if (!nr_frags--) 519 break; 520 521 size = skb_frag_size(frag++); 522 } 523 524 return count; 525 } 526 527 /** 528 * i40e_maybe_stop_tx - 1st level check for Tx stop conditions 529 * @tx_ring: the ring to be checked 530 * @size: the size buffer we want to assure is available 531 * 532 * Returns 0 if stop is not needed 533 **/ 534 static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 535 { 536 if (likely(I40E_DESC_UNUSED(tx_ring) >= size)) 537 return 0; 538 return __i40e_maybe_stop_tx(tx_ring, size); 539 } 540 541 /** 542 * i40e_chk_linearize - Check if there are more than 8 fragments per packet 543 * @skb: send buffer 544 * @count: number of buffers used 545 * 546 * Note: Our HW can't scatter-gather more than 8 fragments to build 547 * a packet on the wire and so we need to figure out the cases where we 548 * need to linearize the skb. 549 **/ 550 static inline bool i40e_chk_linearize(struct sk_buff *skb, int count) 551 { 552 /* Both TSO and single send will work if count is less than 8 */ 553 if (likely(count < I40E_MAX_BUFFER_TXD)) 554 return false; 555 556 if (skb_is_gso(skb)) 557 return __i40e_chk_linearize(skb); 558 559 /* we can support up to 8 data buffers for a single send */ 560 return count != I40E_MAX_BUFFER_TXD; 561 } 562 563 /** 564 * txring_txq - Find the netdev Tx ring based on the i40e Tx ring 565 * @ring: Tx ring to find the netdev equivalent of 566 **/ 567 static inline struct netdev_queue *txring_txq(const struct i40e_ring *ring) 568 { 569 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 570 } 571 #endif /* _I40E_TXRX_H_ */ 572