1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_TXRX_H_ 28 #define _I40E_TXRX_H_ 29 30 /* Interrupt Throttling and Rate Limiting Goodies */ 31 32 #define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */ 33 #define I40E_MIN_ITR 0x0004 /* reg uses 2 usec resolution */ 34 #define I40E_MAX_IRATE 0x03F 35 #define I40E_MIN_IRATE 0x001 36 #define I40E_IRATE_USEC_RESOLUTION 4 37 #define I40E_ITR_100K 0x0005 38 #define I40E_ITR_20K 0x0019 39 #define I40E_ITR_8K 0x003E 40 #define I40E_ITR_4K 0x007A 41 #define I40E_ITR_RX_DEF I40E_ITR_8K 42 #define I40E_ITR_TX_DEF I40E_ITR_4K 43 #define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ 44 #define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */ 45 #define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */ 46 #define I40E_DEFAULT_IRQ_WORK 256 47 #define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1) 48 #define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC)) 49 #define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1) 50 51 #define I40E_QUEUE_END_OF_LIST 0x7FF 52 53 /* this enum matches hardware bits and is meant to be used by DYN_CTLN 54 * registers and QINT registers or more generally anywhere in the manual 55 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 56 * register but instead is a special value meaning "don't update" ITR0/1/2. 57 */ 58 enum i40e_dyn_idx_t { 59 I40E_IDX_ITR0 = 0, 60 I40E_IDX_ITR1 = 1, 61 I40E_IDX_ITR2 = 2, 62 I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 63 }; 64 65 /* these are indexes into ITRN registers */ 66 #define I40E_RX_ITR I40E_IDX_ITR0 67 #define I40E_TX_ITR I40E_IDX_ITR1 68 #define I40E_PE_ITR I40E_IDX_ITR2 69 70 /* Supported RSS offloads */ 71 #define I40E_DEFAULT_RSS_HENA ( \ 72 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 73 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 74 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 75 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 76 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 77 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 78 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN) | \ 79 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 80 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 81 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 82 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 83 ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 84 85 /* Supported Rx Buffer Sizes */ 86 #define I40E_RXBUFFER_512 512 /* Used for packet split */ 87 #define I40E_RXBUFFER_2048 2048 88 #define I40E_RXBUFFER_3072 3072 /* For FCoE MTU of 2158 */ 89 #define I40E_RXBUFFER_4096 4096 90 #define I40E_RXBUFFER_8192 8192 91 #define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */ 92 93 /* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 94 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, 95 * this adds up to 512 bytes of extra data meaning the smallest allocation 96 * we could have is 1K. 97 * i.e. RXBUFFER_512 --> size-1024 slab 98 */ 99 #define I40E_RX_HDR_SIZE I40E_RXBUFFER_512 100 101 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 102 #define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 103 #define I40E_RX_NEXT_DESC(r, i, n) \ 104 do { \ 105 (i)++; \ 106 if ((i) == (r)->count) \ 107 i = 0; \ 108 (n) = I40E_RX_DESC((r), (i)); \ 109 } while (0) 110 111 #define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \ 112 do { \ 113 I40E_RX_NEXT_DESC((r), (i), (n)); \ 114 prefetch((n)); \ 115 } while (0) 116 117 #define i40e_rx_desc i40e_32byte_rx_desc 118 119 #define I40E_MIN_TX_LEN 17 120 #define I40E_MAX_DATA_PER_TXD 8192 121 122 /* Tx Descriptors needed, worst case */ 123 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD) 124 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 125 126 #define I40E_TX_FLAGS_CSUM (u32)(1) 127 #define I40E_TX_FLAGS_HW_VLAN (u32)(1 << 1) 128 #define I40E_TX_FLAGS_SW_VLAN (u32)(1 << 2) 129 #define I40E_TX_FLAGS_TSO (u32)(1 << 3) 130 #define I40E_TX_FLAGS_IPV4 (u32)(1 << 4) 131 #define I40E_TX_FLAGS_IPV6 (u32)(1 << 5) 132 #define I40E_TX_FLAGS_FCCRC (u32)(1 << 6) 133 #define I40E_TX_FLAGS_FSO (u32)(1 << 7) 134 #define I40E_TX_FLAGS_TSYN (u32)(1 << 8) 135 #define I40E_TX_FLAGS_VLAN_MASK 0xffff0000 136 #define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 137 #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29 138 #define I40E_TX_FLAGS_VLAN_SHIFT 16 139 140 struct i40e_tx_buffer { 141 struct i40e_tx_desc *next_to_watch; 142 unsigned long time_stamp; 143 struct sk_buff *skb; 144 unsigned int bytecount; 145 unsigned short gso_segs; 146 DEFINE_DMA_UNMAP_ADDR(dma); 147 DEFINE_DMA_UNMAP_LEN(len); 148 u32 tx_flags; 149 }; 150 151 struct i40e_rx_buffer { 152 struct sk_buff *skb; 153 dma_addr_t dma; 154 struct page *page; 155 dma_addr_t page_dma; 156 unsigned int page_offset; 157 }; 158 159 struct i40e_queue_stats { 160 u64 packets; 161 u64 bytes; 162 }; 163 164 struct i40e_tx_queue_stats { 165 u64 restart_queue; 166 u64 tx_busy; 167 u64 tx_done_old; 168 }; 169 170 struct i40e_rx_queue_stats { 171 u64 non_eop_descs; 172 u64 alloc_page_failed; 173 u64 alloc_buff_failed; 174 }; 175 176 enum i40e_ring_state_t { 177 __I40E_TX_FDIR_INIT_DONE, 178 __I40E_TX_XPS_INIT_DONE, 179 __I40E_TX_DETECT_HANG, 180 __I40E_HANG_CHECK_ARMED, 181 __I40E_RX_PS_ENABLED, 182 __I40E_RX_16BYTE_DESC_ENABLED, 183 }; 184 185 #define ring_is_ps_enabled(ring) \ 186 test_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 187 #define set_ring_ps_enabled(ring) \ 188 set_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 189 #define clear_ring_ps_enabled(ring) \ 190 clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 191 #define check_for_tx_hang(ring) \ 192 test_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 193 #define set_check_for_tx_hang(ring) \ 194 set_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 195 #define clear_check_for_tx_hang(ring) \ 196 clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 197 #define ring_is_16byte_desc_enabled(ring) \ 198 test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 199 #define set_ring_16byte_desc_enabled(ring) \ 200 set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 201 #define clear_ring_16byte_desc_enabled(ring) \ 202 clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 203 204 /* struct that defines a descriptor ring, associated with a VSI */ 205 struct i40e_ring { 206 struct i40e_ring *next; /* pointer to next ring in q_vector */ 207 void *desc; /* Descriptor ring memory */ 208 struct device *dev; /* Used for DMA mapping */ 209 struct net_device *netdev; /* netdev ring maps to */ 210 union { 211 struct i40e_tx_buffer *tx_bi; 212 struct i40e_rx_buffer *rx_bi; 213 }; 214 unsigned long state; 215 u16 queue_index; /* Queue number of ring */ 216 u8 dcb_tc; /* Traffic class of ring */ 217 u8 __iomem *tail; 218 219 u16 count; /* Number of descriptors */ 220 u16 reg_idx; /* HW register index of the ring */ 221 u16 rx_hdr_len; 222 u16 rx_buf_len; 223 u8 dtype; 224 #define I40E_RX_DTYPE_NO_SPLIT 0 225 #define I40E_RX_DTYPE_SPLIT_ALWAYS 1 226 #define I40E_RX_DTYPE_HEADER_SPLIT 2 227 u8 hsplit; 228 #define I40E_RX_SPLIT_L2 0x1 229 #define I40E_RX_SPLIT_IP 0x2 230 #define I40E_RX_SPLIT_TCP_UDP 0x4 231 #define I40E_RX_SPLIT_SCTP 0x8 232 233 /* used in interrupt processing */ 234 u16 next_to_use; 235 u16 next_to_clean; 236 237 u8 atr_sample_rate; 238 u8 atr_count; 239 240 unsigned long last_rx_timestamp; 241 242 bool ring_active; /* is ring online or not */ 243 244 /* stats structs */ 245 struct i40e_queue_stats stats; 246 struct u64_stats_sync syncp; 247 union { 248 struct i40e_tx_queue_stats tx_stats; 249 struct i40e_rx_queue_stats rx_stats; 250 }; 251 252 unsigned int size; /* length of descriptor ring in bytes */ 253 dma_addr_t dma; /* physical address of ring */ 254 255 struct i40e_vsi *vsi; /* Backreference to associated VSI */ 256 struct i40e_q_vector *q_vector; /* Backreference to associated vector */ 257 258 struct rcu_head rcu; /* to avoid race on free */ 259 } ____cacheline_internodealigned_in_smp; 260 261 enum i40e_latency_range { 262 I40E_LOWEST_LATENCY = 0, 263 I40E_LOW_LATENCY = 1, 264 I40E_BULK_LATENCY = 2, 265 }; 266 267 struct i40e_ring_container { 268 /* array of pointers to rings */ 269 struct i40e_ring *ring; 270 unsigned int total_bytes; /* total bytes processed this int */ 271 unsigned int total_packets; /* total packets processed this int */ 272 u16 count; 273 enum i40e_latency_range latency_range; 274 u16 itr; 275 }; 276 277 /* iterator for handling rings in ring container */ 278 #define i40e_for_each_ring(pos, head) \ 279 for (pos = (head).ring; pos != NULL; pos = pos->next) 280 281 void i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count); 282 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 283 void i40e_clean_tx_ring(struct i40e_ring *tx_ring); 284 void i40e_clean_rx_ring(struct i40e_ring *rx_ring); 285 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring); 286 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring); 287 void i40e_free_tx_resources(struct i40e_ring *tx_ring); 288 void i40e_free_rx_resources(struct i40e_ring *rx_ring); 289 int i40e_napi_poll(struct napi_struct *napi, int budget); 290 #endif /* _I40E_TXRX_H_ */ 291