1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_TXRX_H_ 28 #define _I40E_TXRX_H_ 29 30 /* Interrupt Throttling and Rate Limiting (storm control) Goodies */ 31 32 #define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */ 33 #define I40E_MIN_ITR 0x0004 /* reg uses 2 usec resolution */ 34 #define I40E_MAX_IRATE 0x03F 35 #define I40E_MIN_IRATE 0x001 36 #define I40E_IRATE_USEC_RESOLUTION 4 37 #define I40E_ITR_100K 0x0005 38 #define I40E_ITR_20K 0x0019 39 #define I40E_ITR_8K 0x003E 40 #define I40E_ITR_4K 0x007A 41 #define I40E_ITR_RX_DEF I40E_ITR_8K 42 #define I40E_ITR_TX_DEF I40E_ITR_4K 43 #define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ 44 #define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */ 45 #define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */ 46 #define I40E_DEFAULT_IRQ_WORK 256 47 #define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1) 48 #define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC)) 49 #define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1) 50 51 #define I40E_QUEUE_END_OF_LIST 0x7FF 52 53 /* this enum matches hardware bits and is meant to be used by DYN_CTLN 54 * registers and QINT registers or more generally anywhere in the manual 55 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 56 * register but instead is a special value meaning "don't update" ITR0/1/2. 57 */ 58 enum i40e_dyn_idx_t { 59 I40E_IDX_ITR0 = 0, 60 I40E_IDX_ITR1 = 1, 61 I40E_IDX_ITR2 = 2, 62 I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 63 }; 64 65 /* these are indexes into ITRN registers */ 66 #define I40E_RX_ITR I40E_IDX_ITR0 67 #define I40E_TX_ITR I40E_IDX_ITR1 68 #define I40E_PE_ITR I40E_IDX_ITR2 69 70 /* Supported RSS offloads */ 71 #define I40E_DEFAULT_RSS_HENA ( \ 72 ((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 73 ((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 74 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 75 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 76 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN) | \ 77 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 78 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 79 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 80 ((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 81 ((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 82 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 83 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN) | \ 84 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 85 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 86 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 87 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 88 ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 89 90 /* Supported Rx Buffer Sizes */ 91 #define I40E_RXBUFFER_512 512 /* Used for packet split */ 92 #define I40E_RXBUFFER_2048 2048 93 #define I40E_RXBUFFER_3072 3072 /* For FCoE MTU of 2158 */ 94 #define I40E_RXBUFFER_4096 4096 95 #define I40E_RXBUFFER_8192 8192 96 #define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */ 97 98 /* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 99 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, 100 * this adds up to 512 bytes of extra data meaning the smallest allocation 101 * we could have is 1K. 102 * i.e. RXBUFFER_512 --> size-1024 slab 103 */ 104 #define I40E_RX_HDR_SIZE I40E_RXBUFFER_512 105 106 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 107 #define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 108 #define I40E_RX_NEXT_DESC(r, i, n) \ 109 do { \ 110 (i)++; \ 111 if ((i) == (r)->count) \ 112 i = 0; \ 113 (n) = I40E_RX_DESC((r), (i)); \ 114 } while (0) 115 116 #define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \ 117 do { \ 118 I40E_RX_NEXT_DESC((r), (i), (n)); \ 119 prefetch((n)); \ 120 } while (0) 121 122 #define i40e_rx_desc i40e_32byte_rx_desc 123 124 #define I40E_MIN_TX_LEN 17 125 #define I40E_MAX_DATA_PER_TXD 16383 /* aka 16kB - 1 */ 126 127 /* Tx Descriptors needed, worst case */ 128 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD) 129 #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4) 130 131 #define I40E_TX_FLAGS_CSUM (u32)(1) 132 #define I40E_TX_FLAGS_HW_VLAN (u32)(1 << 1) 133 #define I40E_TX_FLAGS_SW_VLAN (u32)(1 << 2) 134 #define I40E_TX_FLAGS_TSO (u32)(1 << 3) 135 #define I40E_TX_FLAGS_IPV4 (u32)(1 << 4) 136 #define I40E_TX_FLAGS_IPV6 (u32)(1 << 5) 137 #define I40E_TX_FLAGS_FCCRC (u32)(1 << 6) 138 #define I40E_TX_FLAGS_FSO (u32)(1 << 7) 139 #define I40E_TX_FLAGS_TSYN (u32)(1 << 8) 140 #define I40E_TX_FLAGS_VLAN_MASK 0xffff0000 141 #define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 142 #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29 143 #define I40E_TX_FLAGS_VLAN_SHIFT 16 144 145 struct i40e_tx_buffer { 146 struct i40e_tx_desc *next_to_watch; 147 unsigned long time_stamp; 148 struct sk_buff *skb; 149 unsigned int bytecount; 150 unsigned short gso_segs; 151 DEFINE_DMA_UNMAP_ADDR(dma); 152 DEFINE_DMA_UNMAP_LEN(len); 153 u32 tx_flags; 154 }; 155 156 struct i40e_rx_buffer { 157 struct sk_buff *skb; 158 dma_addr_t dma; 159 struct page *page; 160 dma_addr_t page_dma; 161 unsigned int page_offset; 162 }; 163 164 struct i40e_queue_stats { 165 u64 packets; 166 u64 bytes; 167 }; 168 169 struct i40e_tx_queue_stats { 170 u64 restart_queue; 171 u64 tx_busy; 172 u64 tx_done_old; 173 }; 174 175 struct i40e_rx_queue_stats { 176 u64 non_eop_descs; 177 u64 alloc_page_failed; 178 u64 alloc_buff_failed; 179 }; 180 181 enum i40e_ring_state_t { 182 __I40E_TX_FDIR_INIT_DONE, 183 __I40E_TX_XPS_INIT_DONE, 184 __I40E_TX_DETECT_HANG, 185 __I40E_HANG_CHECK_ARMED, 186 __I40E_RX_PS_ENABLED, 187 __I40E_RX_LRO_ENABLED, 188 __I40E_RX_16BYTE_DESC_ENABLED, 189 }; 190 191 #define ring_is_ps_enabled(ring) \ 192 test_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 193 #define set_ring_ps_enabled(ring) \ 194 set_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 195 #define clear_ring_ps_enabled(ring) \ 196 clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 197 #define check_for_tx_hang(ring) \ 198 test_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 199 #define set_check_for_tx_hang(ring) \ 200 set_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 201 #define clear_check_for_tx_hang(ring) \ 202 clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 203 #define ring_is_lro_enabled(ring) \ 204 test_bit(__I40E_RX_LRO_ENABLED, &(ring)->state) 205 #define set_ring_lro_enabled(ring) \ 206 set_bit(__I40E_RX_LRO_ENABLED, &(ring)->state) 207 #define clear_ring_lro_enabled(ring) \ 208 clear_bit(__I40E_RX_LRO_ENABLED, &(ring)->state) 209 #define ring_is_16byte_desc_enabled(ring) \ 210 test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 211 #define set_ring_16byte_desc_enabled(ring) \ 212 set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 213 #define clear_ring_16byte_desc_enabled(ring) \ 214 clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 215 216 /* struct that defines a descriptor ring, associated with a VSI */ 217 struct i40e_ring { 218 struct i40e_ring *next; /* pointer to next ring in q_vector */ 219 void *desc; /* Descriptor ring memory */ 220 struct device *dev; /* Used for DMA mapping */ 221 struct net_device *netdev; /* netdev ring maps to */ 222 union { 223 struct i40e_tx_buffer *tx_bi; 224 struct i40e_rx_buffer *rx_bi; 225 }; 226 unsigned long state; 227 u16 queue_index; /* Queue number of ring */ 228 u8 dcb_tc; /* Traffic class of ring */ 229 u8 __iomem *tail; 230 231 u16 count; /* Number of descriptors */ 232 u16 reg_idx; /* HW register index of the ring */ 233 u16 rx_hdr_len; 234 u16 rx_buf_len; 235 u8 dtype; 236 #define I40E_RX_DTYPE_NO_SPLIT 0 237 #define I40E_RX_DTYPE_SPLIT_ALWAYS 1 238 #define I40E_RX_DTYPE_HEADER_SPLIT 2 239 u8 hsplit; 240 #define I40E_RX_SPLIT_L2 0x1 241 #define I40E_RX_SPLIT_IP 0x2 242 #define I40E_RX_SPLIT_TCP_UDP 0x4 243 #define I40E_RX_SPLIT_SCTP 0x8 244 245 /* used in interrupt processing */ 246 u16 next_to_use; 247 u16 next_to_clean; 248 249 u8 atr_sample_rate; 250 u8 atr_count; 251 252 unsigned long last_rx_timestamp; 253 254 bool ring_active; /* is ring online or not */ 255 256 /* stats structs */ 257 struct i40e_queue_stats stats; 258 struct u64_stats_sync syncp; 259 union { 260 struct i40e_tx_queue_stats tx_stats; 261 struct i40e_rx_queue_stats rx_stats; 262 }; 263 264 unsigned int size; /* length of descriptor ring in bytes */ 265 dma_addr_t dma; /* physical address of ring */ 266 267 struct i40e_vsi *vsi; /* Backreference to associated VSI */ 268 struct i40e_q_vector *q_vector; /* Backreference to associated vector */ 269 270 struct rcu_head rcu; /* to avoid race on free */ 271 } ____cacheline_internodealigned_in_smp; 272 273 enum i40e_latency_range { 274 I40E_LOWEST_LATENCY = 0, 275 I40E_LOW_LATENCY = 1, 276 I40E_BULK_LATENCY = 2, 277 }; 278 279 struct i40e_ring_container { 280 /* array of pointers to rings */ 281 struct i40e_ring *ring; 282 unsigned int total_bytes; /* total bytes processed this int */ 283 unsigned int total_packets; /* total packets processed this int */ 284 u16 count; 285 enum i40e_latency_range latency_range; 286 u16 itr; 287 }; 288 289 /* iterator for handling rings in ring container */ 290 #define i40e_for_each_ring(pos, head) \ 291 for (pos = (head).ring; pos != NULL; pos = pos->next) 292 293 void i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count); 294 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 295 void i40e_clean_tx_ring(struct i40e_ring *tx_ring); 296 void i40e_clean_rx_ring(struct i40e_ring *rx_ring); 297 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring); 298 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring); 299 void i40e_free_tx_resources(struct i40e_ring *tx_ring); 300 void i40e_free_rx_resources(struct i40e_ring *rx_ring); 301 int i40e_napi_poll(struct napi_struct *napi, int budget); 302 #endif /* _I40E_TXRX_H_ */ 303