1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_TXRX_H_ 28 #define _I40E_TXRX_H_ 29 30 #include <net/xdp.h> 31 32 /* Interrupt Throttling and Rate Limiting Goodies */ 33 #define I40E_DEFAULT_IRQ_WORK 256 34 35 /* The datasheet for the X710 and XL710 indicate that the maximum value for 36 * the ITR is 8160usec which is then called out as 0xFF0 with a 2usec 37 * resolution. 8160 is 0x1FE0 when written out in hex. So instead of storing 38 * the register value which is divided by 2 lets use the actual values and 39 * avoid an excessive amount of translation. 40 */ 41 #define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ 42 #define I40E_ITR_MASK 0x1FFE /* mask for ITR register value */ 43 #define I40E_MIN_ITR 2 /* reg uses 2 usec resolution */ 44 #define I40E_ITR_100K 10 /* all values below must be even */ 45 #define I40E_ITR_50K 20 46 #define I40E_ITR_20K 50 47 #define I40E_ITR_18K 60 48 #define I40E_ITR_8K 122 49 #define I40E_MAX_ITR 8160 /* maximum value as per datasheet */ 50 #define ITR_TO_REG(setting) ((setting) & ~I40E_ITR_DYNAMIC) 51 #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~I40E_ITR_MASK) 52 #define ITR_IS_DYNAMIC(setting) (!!((setting) & I40E_ITR_DYNAMIC)) 53 54 #define I40E_ITR_RX_DEF (I40E_ITR_20K | I40E_ITR_DYNAMIC) 55 #define I40E_ITR_TX_DEF (I40E_ITR_20K | I40E_ITR_DYNAMIC) 56 57 /* 0x40 is the enable bit for interrupt rate limiting, and must be set if 58 * the value of the rate limit is non-zero 59 */ 60 #define INTRL_ENA BIT(6) 61 #define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */ 62 #define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2) 63 64 /** 65 * i40e_intrl_usec_to_reg - convert interrupt rate limit to register 66 * @intrl: interrupt rate limit to convert 67 * 68 * This function converts a decimal interrupt rate limit to the appropriate 69 * register format expected by the firmware when setting interrupt rate limit. 70 */ 71 static inline u16 i40e_intrl_usec_to_reg(int intrl) 72 { 73 if (intrl >> 2) 74 return ((intrl >> 2) | INTRL_ENA); 75 else 76 return 0; 77 } 78 #define I40E_INTRL_8K 125 /* 8000 ints/sec */ 79 #define I40E_INTRL_62K 16 /* 62500 ints/sec */ 80 #define I40E_INTRL_83K 12 /* 83333 ints/sec */ 81 82 #define I40E_QUEUE_END_OF_LIST 0x7FF 83 84 /* this enum matches hardware bits and is meant to be used by DYN_CTLN 85 * registers and QINT registers or more generally anywhere in the manual 86 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 87 * register but instead is a special value meaning "don't update" ITR0/1/2. 88 */ 89 enum i40e_dyn_idx_t { 90 I40E_IDX_ITR0 = 0, 91 I40E_IDX_ITR1 = 1, 92 I40E_IDX_ITR2 = 2, 93 I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 94 }; 95 96 /* these are indexes into ITRN registers */ 97 #define I40E_RX_ITR I40E_IDX_ITR0 98 #define I40E_TX_ITR I40E_IDX_ITR1 99 #define I40E_PE_ITR I40E_IDX_ITR2 100 101 /* Supported RSS offloads */ 102 #define I40E_DEFAULT_RSS_HENA ( \ 103 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 104 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 105 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 106 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 107 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 108 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 109 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 110 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 111 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 112 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 113 BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD)) 114 115 #define I40E_DEFAULT_RSS_HENA_EXPANDED (I40E_DEFAULT_RSS_HENA | \ 116 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 117 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 118 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 119 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 120 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 121 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP)) 122 123 #define i40e_pf_get_default_rss_hena(pf) \ 124 (((pf)->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \ 125 I40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA) 126 127 /* Supported Rx Buffer Sizes (a multiple of 128) */ 128 #define I40E_RXBUFFER_256 256 129 #define I40E_RXBUFFER_1536 1536 /* 128B aligned standard Ethernet frame */ 130 #define I40E_RXBUFFER_2048 2048 131 #define I40E_RXBUFFER_3072 3072 /* Used for large frames w/ padding */ 132 #define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */ 133 134 /* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 135 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, 136 * this adds up to 512 bytes of extra data meaning the smallest allocation 137 * we could have is 1K. 138 * i.e. RXBUFFER_256 --> 960 byte skb (size-1024 slab) 139 * i.e. RXBUFFER_512 --> 1216 byte skb (size-2048 slab) 140 */ 141 #define I40E_RX_HDR_SIZE I40E_RXBUFFER_256 142 #define I40E_PACKET_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2)) 143 #define i40e_rx_desc i40e_32byte_rx_desc 144 145 #define I40E_RX_DMA_ATTR \ 146 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 147 148 /* Attempt to maximize the headroom available for incoming frames. We 149 * use a 2K buffer for receives and need 1536/1534 to store the data for 150 * the frame. This leaves us with 512 bytes of room. From that we need 151 * to deduct the space needed for the shared info and the padding needed 152 * to IP align the frame. 153 * 154 * Note: For cache line sizes 256 or larger this value is going to end 155 * up negative. In these cases we should fall back to the legacy 156 * receive path. 157 */ 158 #if (PAGE_SIZE < 8192) 159 #define I40E_2K_TOO_SMALL_WITH_PADDING \ 160 ((NET_SKB_PAD + I40E_RXBUFFER_1536) > SKB_WITH_OVERHEAD(I40E_RXBUFFER_2048)) 161 162 static inline int i40e_compute_pad(int rx_buf_len) 163 { 164 int page_size, pad_size; 165 166 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); 167 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; 168 169 return pad_size; 170 } 171 172 static inline int i40e_skb_pad(void) 173 { 174 int rx_buf_len; 175 176 /* If a 2K buffer cannot handle a standard Ethernet frame then 177 * optimize padding for a 3K buffer instead of a 1.5K buffer. 178 * 179 * For a 3K buffer we need to add enough padding to allow for 180 * tailroom due to NET_IP_ALIGN possibly shifting us out of 181 * cache-line alignment. 182 */ 183 if (I40E_2K_TOO_SMALL_WITH_PADDING) 184 rx_buf_len = I40E_RXBUFFER_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN); 185 else 186 rx_buf_len = I40E_RXBUFFER_1536; 187 188 /* if needed make room for NET_IP_ALIGN */ 189 rx_buf_len -= NET_IP_ALIGN; 190 191 return i40e_compute_pad(rx_buf_len); 192 } 193 194 #define I40E_SKB_PAD i40e_skb_pad() 195 #else 196 #define I40E_2K_TOO_SMALL_WITH_PADDING false 197 #define I40E_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 198 #endif 199 200 /** 201 * i40e_test_staterr - tests bits in Rx descriptor status and error fields 202 * @rx_desc: pointer to receive descriptor (in le64 format) 203 * @stat_err_bits: value to mask 204 * 205 * This function does some fast chicanery in order to return the 206 * value of the mask which is really only used for boolean tests. 207 * The status_error_len doesn't need to be shifted because it begins 208 * at offset zero. 209 */ 210 static inline bool i40e_test_staterr(union i40e_rx_desc *rx_desc, 211 const u64 stat_err_bits) 212 { 213 return !!(rx_desc->wb.qword1.status_error_len & 214 cpu_to_le64(stat_err_bits)); 215 } 216 217 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 218 #define I40E_RX_BUFFER_WRITE 32 /* Must be power of 2 */ 219 #define I40E_RX_INCREMENT(r, i) \ 220 do { \ 221 (i)++; \ 222 if ((i) == (r)->count) \ 223 i = 0; \ 224 r->next_to_clean = i; \ 225 } while (0) 226 227 #define I40E_RX_NEXT_DESC(r, i, n) \ 228 do { \ 229 (i)++; \ 230 if ((i) == (r)->count) \ 231 i = 0; \ 232 (n) = I40E_RX_DESC((r), (i)); \ 233 } while (0) 234 235 #define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \ 236 do { \ 237 I40E_RX_NEXT_DESC((r), (i), (n)); \ 238 prefetch((n)); \ 239 } while (0) 240 241 #define I40E_MAX_BUFFER_TXD 8 242 #define I40E_MIN_TX_LEN 17 243 244 /* The size limit for a transmit buffer in a descriptor is (16K - 1). 245 * In order to align with the read requests we will align the value to 246 * the nearest 4K which represents our maximum read request size. 247 */ 248 #define I40E_MAX_READ_REQ_SIZE 4096 249 #define I40E_MAX_DATA_PER_TXD (16 * 1024 - 1) 250 #define I40E_MAX_DATA_PER_TXD_ALIGNED \ 251 (I40E_MAX_DATA_PER_TXD & ~(I40E_MAX_READ_REQ_SIZE - 1)) 252 253 /** 254 * i40e_txd_use_count - estimate the number of descriptors needed for Tx 255 * @size: transmit request size in bytes 256 * 257 * Due to hardware alignment restrictions (4K alignment), we need to 258 * assume that we can have no more than 12K of data per descriptor, even 259 * though each descriptor can take up to 16K - 1 bytes of aligned memory. 260 * Thus, we need to divide by 12K. But division is slow! Instead, 261 * we decompose the operation into shifts and one relatively cheap 262 * multiply operation. 263 * 264 * To divide by 12K, we first divide by 4K, then divide by 3: 265 * To divide by 4K, shift right by 12 bits 266 * To divide by 3, multiply by 85, then divide by 256 267 * (Divide by 256 is done by shifting right by 8 bits) 268 * Finally, we add one to round up. Because 256 isn't an exact multiple of 269 * 3, we'll underestimate near each multiple of 12K. This is actually more 270 * accurate as we have 4K - 1 of wiggle room that we can fit into the last 271 * segment. For our purposes this is accurate out to 1M which is orders of 272 * magnitude greater than our largest possible GSO size. 273 * 274 * This would then be implemented as: 275 * return (((size >> 12) * 85) >> 8) + 1; 276 * 277 * Since multiplication and division are commutative, we can reorder 278 * operations into: 279 * return ((size * 85) >> 20) + 1; 280 */ 281 static inline unsigned int i40e_txd_use_count(unsigned int size) 282 { 283 return ((size * 85) >> 20) + 1; 284 } 285 286 /* Tx Descriptors needed, worst case */ 287 #define DESC_NEEDED (MAX_SKB_FRAGS + 6) 288 #define I40E_MIN_DESC_PENDING 4 289 290 #define I40E_TX_FLAGS_HW_VLAN BIT(1) 291 #define I40E_TX_FLAGS_SW_VLAN BIT(2) 292 #define I40E_TX_FLAGS_TSO BIT(3) 293 #define I40E_TX_FLAGS_IPV4 BIT(4) 294 #define I40E_TX_FLAGS_IPV6 BIT(5) 295 #define I40E_TX_FLAGS_FCCRC BIT(6) 296 #define I40E_TX_FLAGS_FSO BIT(7) 297 #define I40E_TX_FLAGS_TSYN BIT(8) 298 #define I40E_TX_FLAGS_FD_SB BIT(9) 299 #define I40E_TX_FLAGS_UDP_TUNNEL BIT(10) 300 #define I40E_TX_FLAGS_VLAN_MASK 0xffff0000 301 #define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 302 #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29 303 #define I40E_TX_FLAGS_VLAN_SHIFT 16 304 305 struct i40e_tx_buffer { 306 struct i40e_tx_desc *next_to_watch; 307 union { 308 struct sk_buff *skb; 309 void *raw_buf; 310 }; 311 unsigned int bytecount; 312 unsigned short gso_segs; 313 314 DEFINE_DMA_UNMAP_ADDR(dma); 315 DEFINE_DMA_UNMAP_LEN(len); 316 u32 tx_flags; 317 }; 318 319 struct i40e_rx_buffer { 320 dma_addr_t dma; 321 struct page *page; 322 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 323 __u32 page_offset; 324 #else 325 __u16 page_offset; 326 #endif 327 __u16 pagecnt_bias; 328 }; 329 330 struct i40e_queue_stats { 331 u64 packets; 332 u64 bytes; 333 }; 334 335 struct i40e_tx_queue_stats { 336 u64 restart_queue; 337 u64 tx_busy; 338 u64 tx_done_old; 339 u64 tx_linearize; 340 u64 tx_force_wb; 341 int prev_pkt_ctr; 342 }; 343 344 struct i40e_rx_queue_stats { 345 u64 non_eop_descs; 346 u64 alloc_page_failed; 347 u64 alloc_buff_failed; 348 u64 page_reuse_count; 349 u64 realloc_count; 350 }; 351 352 enum i40e_ring_state_t { 353 __I40E_TX_FDIR_INIT_DONE, 354 __I40E_TX_XPS_INIT_DONE, 355 __I40E_RING_STATE_NBITS /* must be last */ 356 }; 357 358 /* some useful defines for virtchannel interface, which 359 * is the only remaining user of header split 360 */ 361 #define I40E_RX_DTYPE_NO_SPLIT 0 362 #define I40E_RX_DTYPE_HEADER_SPLIT 1 363 #define I40E_RX_DTYPE_SPLIT_ALWAYS 2 364 #define I40E_RX_SPLIT_L2 0x1 365 #define I40E_RX_SPLIT_IP 0x2 366 #define I40E_RX_SPLIT_TCP_UDP 0x4 367 #define I40E_RX_SPLIT_SCTP 0x8 368 369 /* struct that defines a descriptor ring, associated with a VSI */ 370 struct i40e_ring { 371 struct i40e_ring *next; /* pointer to next ring in q_vector */ 372 void *desc; /* Descriptor ring memory */ 373 struct device *dev; /* Used for DMA mapping */ 374 struct net_device *netdev; /* netdev ring maps to */ 375 struct bpf_prog *xdp_prog; 376 union { 377 struct i40e_tx_buffer *tx_bi; 378 struct i40e_rx_buffer *rx_bi; 379 }; 380 DECLARE_BITMAP(state, __I40E_RING_STATE_NBITS); 381 u16 queue_index; /* Queue number of ring */ 382 u8 dcb_tc; /* Traffic class of ring */ 383 u8 __iomem *tail; 384 385 /* high bit set means dynamic, use accessor routines to read/write. 386 * hardware only supports 2us resolution for the ITR registers. 387 * these values always store the USER setting, and must be converted 388 * before programming to a register. 389 */ 390 u16 itr_setting; 391 392 u16 count; /* Number of descriptors */ 393 u16 reg_idx; /* HW register index of the ring */ 394 u16 rx_buf_len; 395 396 /* used in interrupt processing */ 397 u16 next_to_use; 398 u16 next_to_clean; 399 400 u8 atr_sample_rate; 401 u8 atr_count; 402 403 bool ring_active; /* is ring online or not */ 404 bool arm_wb; /* do something to arm write back */ 405 u8 packet_stride; 406 407 u16 flags; 408 #define I40E_TXR_FLAGS_WB_ON_ITR BIT(0) 409 #define I40E_RXR_FLAGS_BUILD_SKB_ENABLED BIT(1) 410 #define I40E_TXR_FLAGS_XDP BIT(2) 411 412 /* stats structs */ 413 struct i40e_queue_stats stats; 414 struct u64_stats_sync syncp; 415 union { 416 struct i40e_tx_queue_stats tx_stats; 417 struct i40e_rx_queue_stats rx_stats; 418 }; 419 420 unsigned int size; /* length of descriptor ring in bytes */ 421 dma_addr_t dma; /* physical address of ring */ 422 423 struct i40e_vsi *vsi; /* Backreference to associated VSI */ 424 struct i40e_q_vector *q_vector; /* Backreference to associated vector */ 425 426 struct rcu_head rcu; /* to avoid race on free */ 427 u16 next_to_alloc; 428 struct sk_buff *skb; /* When i40e_clean_rx_ring_irq() must 429 * return before it sees the EOP for 430 * the current packet, we save that skb 431 * here and resume receiving this 432 * packet the next time 433 * i40e_clean_rx_ring_irq() is called 434 * for this ring. 435 */ 436 437 struct i40e_channel *ch; 438 struct xdp_rxq_info xdp_rxq; 439 } ____cacheline_internodealigned_in_smp; 440 441 static inline bool ring_uses_build_skb(struct i40e_ring *ring) 442 { 443 return !!(ring->flags & I40E_RXR_FLAGS_BUILD_SKB_ENABLED); 444 } 445 446 static inline void set_ring_build_skb_enabled(struct i40e_ring *ring) 447 { 448 ring->flags |= I40E_RXR_FLAGS_BUILD_SKB_ENABLED; 449 } 450 451 static inline void clear_ring_build_skb_enabled(struct i40e_ring *ring) 452 { 453 ring->flags &= ~I40E_RXR_FLAGS_BUILD_SKB_ENABLED; 454 } 455 456 static inline bool ring_is_xdp(struct i40e_ring *ring) 457 { 458 return !!(ring->flags & I40E_TXR_FLAGS_XDP); 459 } 460 461 static inline void set_ring_xdp(struct i40e_ring *ring) 462 { 463 ring->flags |= I40E_TXR_FLAGS_XDP; 464 } 465 466 #define I40E_ITR_ADAPTIVE_MIN_INC 0x0002 467 #define I40E_ITR_ADAPTIVE_MIN_USECS 0x0002 468 #define I40E_ITR_ADAPTIVE_MAX_USECS 0x007e 469 #define I40E_ITR_ADAPTIVE_LATENCY 0x8000 470 #define I40E_ITR_ADAPTIVE_BULK 0x0000 471 #define ITR_IS_BULK(x) (!((x) & I40E_ITR_ADAPTIVE_LATENCY)) 472 473 struct i40e_ring_container { 474 struct i40e_ring *ring; /* pointer to linked list of ring(s) */ 475 unsigned long next_update; /* jiffies value of next update */ 476 unsigned int total_bytes; /* total bytes processed this int */ 477 unsigned int total_packets; /* total packets processed this int */ 478 u16 count; 479 u16 target_itr; /* target ITR setting for ring(s) */ 480 u16 current_itr; /* current ITR setting for ring(s) */ 481 }; 482 483 /* iterator for handling rings in ring container */ 484 #define i40e_for_each_ring(pos, head) \ 485 for (pos = (head).ring; pos != NULL; pos = pos->next) 486 487 static inline unsigned int i40e_rx_pg_order(struct i40e_ring *ring) 488 { 489 #if (PAGE_SIZE < 8192) 490 if (ring->rx_buf_len > (PAGE_SIZE / 2)) 491 return 1; 492 #endif 493 return 0; 494 } 495 496 #define i40e_rx_pg_size(_ring) (PAGE_SIZE << i40e_rx_pg_order(_ring)) 497 498 bool i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count); 499 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 500 void i40e_clean_tx_ring(struct i40e_ring *tx_ring); 501 void i40e_clean_rx_ring(struct i40e_ring *rx_ring); 502 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring); 503 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring); 504 void i40e_free_tx_resources(struct i40e_ring *tx_ring); 505 void i40e_free_rx_resources(struct i40e_ring *rx_ring); 506 int i40e_napi_poll(struct napi_struct *napi, int budget); 507 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector); 508 u32 i40e_get_tx_pending(struct i40e_ring *ring); 509 void i40e_detect_recover_hung(struct i40e_vsi *vsi); 510 int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size); 511 bool __i40e_chk_linearize(struct sk_buff *skb); 512 513 /** 514 * i40e_get_head - Retrieve head from head writeback 515 * @tx_ring: tx ring to fetch head of 516 * 517 * Returns value of Tx ring head based on value stored 518 * in head write-back location 519 **/ 520 static inline u32 i40e_get_head(struct i40e_ring *tx_ring) 521 { 522 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count; 523 524 return le32_to_cpu(*(volatile __le32 *)head); 525 } 526 527 /** 528 * i40e_xmit_descriptor_count - calculate number of Tx descriptors needed 529 * @skb: send buffer 530 * @tx_ring: ring to send buffer on 531 * 532 * Returns number of data descriptors needed for this skb. Returns 0 to indicate 533 * there is not enough descriptors available in this ring since we need at least 534 * one descriptor. 535 **/ 536 static inline int i40e_xmit_descriptor_count(struct sk_buff *skb) 537 { 538 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 539 unsigned int nr_frags = skb_shinfo(skb)->nr_frags; 540 int count = 0, size = skb_headlen(skb); 541 542 for (;;) { 543 count += i40e_txd_use_count(size); 544 545 if (!nr_frags--) 546 break; 547 548 size = skb_frag_size(frag++); 549 } 550 551 return count; 552 } 553 554 /** 555 * i40e_maybe_stop_tx - 1st level check for Tx stop conditions 556 * @tx_ring: the ring to be checked 557 * @size: the size buffer we want to assure is available 558 * 559 * Returns 0 if stop is not needed 560 **/ 561 static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 562 { 563 if (likely(I40E_DESC_UNUSED(tx_ring) >= size)) 564 return 0; 565 return __i40e_maybe_stop_tx(tx_ring, size); 566 } 567 568 /** 569 * i40e_chk_linearize - Check if there are more than 8 fragments per packet 570 * @skb: send buffer 571 * @count: number of buffers used 572 * 573 * Note: Our HW can't scatter-gather more than 8 fragments to build 574 * a packet on the wire and so we need to figure out the cases where we 575 * need to linearize the skb. 576 **/ 577 static inline bool i40e_chk_linearize(struct sk_buff *skb, int count) 578 { 579 /* Both TSO and single send will work if count is less than 8 */ 580 if (likely(count < I40E_MAX_BUFFER_TXD)) 581 return false; 582 583 if (skb_is_gso(skb)) 584 return __i40e_chk_linearize(skb); 585 586 /* we can support up to 8 data buffers for a single send */ 587 return count != I40E_MAX_BUFFER_TXD; 588 } 589 590 /** 591 * txring_txq - Find the netdev Tx ring based on the i40e Tx ring 592 * @ring: Tx ring to find the netdev equivalent of 593 **/ 594 static inline struct netdev_queue *txring_txq(const struct i40e_ring *ring) 595 { 596 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 597 } 598 #endif /* _I40E_TXRX_H_ */ 599