1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_TXRX_H_ 28 #define _I40E_TXRX_H_ 29 30 /* Interrupt Throttling and Rate Limiting Goodies */ 31 32 #define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */ 33 #define I40E_MIN_ITR 0x0001 /* reg uses 2 usec resolution */ 34 #define I40E_ITR_100K 0x0005 35 #define I40E_ITR_50K 0x000A 36 #define I40E_ITR_20K 0x0019 37 #define I40E_ITR_18K 0x001B 38 #define I40E_ITR_8K 0x003E 39 #define I40E_ITR_4K 0x007A 40 #define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */ 41 #define I40E_ITR_RX_DEF I40E_ITR_20K 42 #define I40E_ITR_TX_DEF I40E_ITR_20K 43 #define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ 44 #define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */ 45 #define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */ 46 #define I40E_DEFAULT_IRQ_WORK 256 47 #define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1) 48 #define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC)) 49 #define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1) 50 /* 0x40 is the enable bit for interrupt rate limiting, and must be set if 51 * the value of the rate limit is non-zero 52 */ 53 #define INTRL_ENA BIT(6) 54 #define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2) 55 /** 56 * i40e_intrl_usec_to_reg - convert interrupt rate limit to register 57 * @intrl: interrupt rate limit to convert 58 * 59 * This function converts a decimal interrupt rate limit to the appropriate 60 * register format expected by the firmware when setting interrupt rate limit. 61 */ 62 static inline u16 i40e_intrl_usec_to_reg(int intrl) 63 { 64 if (intrl >> 2) 65 return ((intrl >> 2) | INTRL_ENA); 66 else 67 return 0; 68 } 69 #define I40E_INTRL_8K 125 /* 8000 ints/sec */ 70 #define I40E_INTRL_62K 16 /* 62500 ints/sec */ 71 #define I40E_INTRL_83K 12 /* 83333 ints/sec */ 72 73 #define I40E_QUEUE_END_OF_LIST 0x7FF 74 75 /* this enum matches hardware bits and is meant to be used by DYN_CTLN 76 * registers and QINT registers or more generally anywhere in the manual 77 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 78 * register but instead is a special value meaning "don't update" ITR0/1/2. 79 */ 80 enum i40e_dyn_idx_t { 81 I40E_IDX_ITR0 = 0, 82 I40E_IDX_ITR1 = 1, 83 I40E_IDX_ITR2 = 2, 84 I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 85 }; 86 87 /* these are indexes into ITRN registers */ 88 #define I40E_RX_ITR I40E_IDX_ITR0 89 #define I40E_TX_ITR I40E_IDX_ITR1 90 #define I40E_PE_ITR I40E_IDX_ITR2 91 92 /* Supported RSS offloads */ 93 #define I40E_DEFAULT_RSS_HENA ( \ 94 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 95 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 96 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 97 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 98 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 99 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 100 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 101 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 102 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 103 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 104 BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD)) 105 106 #define I40E_DEFAULT_RSS_HENA_EXPANDED (I40E_DEFAULT_RSS_HENA | \ 107 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 108 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 109 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 110 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 111 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 112 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP)) 113 114 #define i40e_pf_get_default_rss_hena(pf) \ 115 (((pf)->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \ 116 I40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA) 117 118 /* Supported Rx Buffer Sizes (a multiple of 128) */ 119 #define I40E_RXBUFFER_256 256 120 #define I40E_RXBUFFER_1536 1536 /* 128B aligned standard Ethernet frame */ 121 #define I40E_RXBUFFER_2048 2048 122 #define I40E_RXBUFFER_3072 3072 /* Used for large frames w/ padding */ 123 #define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */ 124 125 /* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 126 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, 127 * this adds up to 512 bytes of extra data meaning the smallest allocation 128 * we could have is 1K. 129 * i.e. RXBUFFER_256 --> 960 byte skb (size-1024 slab) 130 * i.e. RXBUFFER_512 --> 1216 byte skb (size-2048 slab) 131 */ 132 #define I40E_RX_HDR_SIZE I40E_RXBUFFER_256 133 #define I40E_PACKET_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2)) 134 #define i40e_rx_desc i40e_32byte_rx_desc 135 136 #define I40E_RX_DMA_ATTR \ 137 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 138 139 /* Attempt to maximize the headroom available for incoming frames. We 140 * use a 2K buffer for receives and need 1536/1534 to store the data for 141 * the frame. This leaves us with 512 bytes of room. From that we need 142 * to deduct the space needed for the shared info and the padding needed 143 * to IP align the frame. 144 * 145 * Note: For cache line sizes 256 or larger this value is going to end 146 * up negative. In these cases we should fall back to the legacy 147 * receive path. 148 */ 149 #if (PAGE_SIZE < 8192) 150 #define I40E_2K_TOO_SMALL_WITH_PADDING \ 151 ((NET_SKB_PAD + I40E_RXBUFFER_1536) > SKB_WITH_OVERHEAD(I40E_RXBUFFER_2048)) 152 153 static inline int i40e_compute_pad(int rx_buf_len) 154 { 155 int page_size, pad_size; 156 157 page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); 158 pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; 159 160 return pad_size; 161 } 162 163 static inline int i40e_skb_pad(void) 164 { 165 int rx_buf_len; 166 167 /* If a 2K buffer cannot handle a standard Ethernet frame then 168 * optimize padding for a 3K buffer instead of a 1.5K buffer. 169 * 170 * For a 3K buffer we need to add enough padding to allow for 171 * tailroom due to NET_IP_ALIGN possibly shifting us out of 172 * cache-line alignment. 173 */ 174 if (I40E_2K_TOO_SMALL_WITH_PADDING) 175 rx_buf_len = I40E_RXBUFFER_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN); 176 else 177 rx_buf_len = I40E_RXBUFFER_1536; 178 179 /* if needed make room for NET_IP_ALIGN */ 180 rx_buf_len -= NET_IP_ALIGN; 181 182 return i40e_compute_pad(rx_buf_len); 183 } 184 185 #define I40E_SKB_PAD i40e_skb_pad() 186 #else 187 #define I40E_2K_TOO_SMALL_WITH_PADDING false 188 #define I40E_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 189 #endif 190 191 /** 192 * i40e_test_staterr - tests bits in Rx descriptor status and error fields 193 * @rx_desc: pointer to receive descriptor (in le64 format) 194 * @stat_err_bits: value to mask 195 * 196 * This function does some fast chicanery in order to return the 197 * value of the mask which is really only used for boolean tests. 198 * The status_error_len doesn't need to be shifted because it begins 199 * at offset zero. 200 */ 201 static inline bool i40e_test_staterr(union i40e_rx_desc *rx_desc, 202 const u64 stat_err_bits) 203 { 204 return !!(rx_desc->wb.qword1.status_error_len & 205 cpu_to_le64(stat_err_bits)); 206 } 207 208 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 209 #define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 210 #define I40E_RX_INCREMENT(r, i) \ 211 do { \ 212 (i)++; \ 213 if ((i) == (r)->count) \ 214 i = 0; \ 215 r->next_to_clean = i; \ 216 } while (0) 217 218 #define I40E_RX_NEXT_DESC(r, i, n) \ 219 do { \ 220 (i)++; \ 221 if ((i) == (r)->count) \ 222 i = 0; \ 223 (n) = I40E_RX_DESC((r), (i)); \ 224 } while (0) 225 226 #define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \ 227 do { \ 228 I40E_RX_NEXT_DESC((r), (i), (n)); \ 229 prefetch((n)); \ 230 } while (0) 231 232 #define I40E_MAX_BUFFER_TXD 8 233 #define I40E_MIN_TX_LEN 17 234 235 /* The size limit for a transmit buffer in a descriptor is (16K - 1). 236 * In order to align with the read requests we will align the value to 237 * the nearest 4K which represents our maximum read request size. 238 */ 239 #define I40E_MAX_READ_REQ_SIZE 4096 240 #define I40E_MAX_DATA_PER_TXD (16 * 1024 - 1) 241 #define I40E_MAX_DATA_PER_TXD_ALIGNED \ 242 (I40E_MAX_DATA_PER_TXD & ~(I40E_MAX_READ_REQ_SIZE - 1)) 243 244 /** 245 * i40e_txd_use_count - estimate the number of descriptors needed for Tx 246 * @size: transmit request size in bytes 247 * 248 * Due to hardware alignment restrictions (4K alignment), we need to 249 * assume that we can have no more than 12K of data per descriptor, even 250 * though each descriptor can take up to 16K - 1 bytes of aligned memory. 251 * Thus, we need to divide by 12K. But division is slow! Instead, 252 * we decompose the operation into shifts and one relatively cheap 253 * multiply operation. 254 * 255 * To divide by 12K, we first divide by 4K, then divide by 3: 256 * To divide by 4K, shift right by 12 bits 257 * To divide by 3, multiply by 85, then divide by 256 258 * (Divide by 256 is done by shifting right by 8 bits) 259 * Finally, we add one to round up. Because 256 isn't an exact multiple of 260 * 3, we'll underestimate near each multiple of 12K. This is actually more 261 * accurate as we have 4K - 1 of wiggle room that we can fit into the last 262 * segment. For our purposes this is accurate out to 1M which is orders of 263 * magnitude greater than our largest possible GSO size. 264 * 265 * This would then be implemented as: 266 * return (((size >> 12) * 85) >> 8) + 1; 267 * 268 * Since multiplication and division are commutative, we can reorder 269 * operations into: 270 * return ((size * 85) >> 20) + 1; 271 */ 272 static inline unsigned int i40e_txd_use_count(unsigned int size) 273 { 274 return ((size * 85) >> 20) + 1; 275 } 276 277 /* Tx Descriptors needed, worst case */ 278 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 279 #define I40E_MIN_DESC_PENDING 4 280 281 #define I40E_TX_FLAGS_HW_VLAN BIT(1) 282 #define I40E_TX_FLAGS_SW_VLAN BIT(2) 283 #define I40E_TX_FLAGS_TSO BIT(3) 284 #define I40E_TX_FLAGS_IPV4 BIT(4) 285 #define I40E_TX_FLAGS_IPV6 BIT(5) 286 #define I40E_TX_FLAGS_FCCRC BIT(6) 287 #define I40E_TX_FLAGS_FSO BIT(7) 288 #define I40E_TX_FLAGS_TSYN BIT(8) 289 #define I40E_TX_FLAGS_FD_SB BIT(9) 290 #define I40E_TX_FLAGS_UDP_TUNNEL BIT(10) 291 #define I40E_TX_FLAGS_VLAN_MASK 0xffff0000 292 #define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 293 #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29 294 #define I40E_TX_FLAGS_VLAN_SHIFT 16 295 296 struct i40e_tx_buffer { 297 struct i40e_tx_desc *next_to_watch; 298 union { 299 struct sk_buff *skb; 300 void *raw_buf; 301 }; 302 unsigned int bytecount; 303 unsigned short gso_segs; 304 305 DEFINE_DMA_UNMAP_ADDR(dma); 306 DEFINE_DMA_UNMAP_LEN(len); 307 u32 tx_flags; 308 }; 309 310 struct i40e_rx_buffer { 311 dma_addr_t dma; 312 struct page *page; 313 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 314 __u32 page_offset; 315 #else 316 __u16 page_offset; 317 #endif 318 __u16 pagecnt_bias; 319 }; 320 321 struct i40e_queue_stats { 322 u64 packets; 323 u64 bytes; 324 }; 325 326 struct i40e_tx_queue_stats { 327 u64 restart_queue; 328 u64 tx_busy; 329 u64 tx_done_old; 330 u64 tx_linearize; 331 u64 tx_force_wb; 332 }; 333 334 struct i40e_rx_queue_stats { 335 u64 non_eop_descs; 336 u64 alloc_page_failed; 337 u64 alloc_buff_failed; 338 u64 page_reuse_count; 339 u64 realloc_count; 340 }; 341 342 enum i40e_ring_state_t { 343 __I40E_TX_FDIR_INIT_DONE, 344 __I40E_TX_XPS_INIT_DONE, 345 }; 346 347 /* some useful defines for virtchannel interface, which 348 * is the only remaining user of header split 349 */ 350 #define I40E_RX_DTYPE_NO_SPLIT 0 351 #define I40E_RX_DTYPE_HEADER_SPLIT 1 352 #define I40E_RX_DTYPE_SPLIT_ALWAYS 2 353 #define I40E_RX_SPLIT_L2 0x1 354 #define I40E_RX_SPLIT_IP 0x2 355 #define I40E_RX_SPLIT_TCP_UDP 0x4 356 #define I40E_RX_SPLIT_SCTP 0x8 357 358 /* struct that defines a descriptor ring, associated with a VSI */ 359 struct i40e_ring { 360 struct i40e_ring *next; /* pointer to next ring in q_vector */ 361 void *desc; /* Descriptor ring memory */ 362 struct device *dev; /* Used for DMA mapping */ 363 struct net_device *netdev; /* netdev ring maps to */ 364 struct bpf_prog *xdp_prog; 365 union { 366 struct i40e_tx_buffer *tx_bi; 367 struct i40e_rx_buffer *rx_bi; 368 }; 369 unsigned long state; 370 u16 queue_index; /* Queue number of ring */ 371 u8 dcb_tc; /* Traffic class of ring */ 372 u8 __iomem *tail; 373 374 /* high bit set means dynamic, use accessor routines to read/write. 375 * hardware only supports 2us resolution for the ITR registers. 376 * these values always store the USER setting, and must be converted 377 * before programming to a register. 378 */ 379 u16 rx_itr_setting; 380 u16 tx_itr_setting; 381 382 u16 count; /* Number of descriptors */ 383 u16 reg_idx; /* HW register index of the ring */ 384 u16 rx_buf_len; 385 386 /* used in interrupt processing */ 387 u16 next_to_use; 388 u16 next_to_clean; 389 390 u8 atr_sample_rate; 391 u8 atr_count; 392 393 bool ring_active; /* is ring online or not */ 394 bool arm_wb; /* do something to arm write back */ 395 u8 packet_stride; 396 397 u16 flags; 398 #define I40E_TXR_FLAGS_WB_ON_ITR BIT(0) 399 #define I40E_RXR_FLAGS_BUILD_SKB_ENABLED BIT(1) 400 #define I40E_TXR_FLAGS_XDP BIT(2) 401 402 /* stats structs */ 403 struct i40e_queue_stats stats; 404 struct u64_stats_sync syncp; 405 union { 406 struct i40e_tx_queue_stats tx_stats; 407 struct i40e_rx_queue_stats rx_stats; 408 }; 409 410 unsigned int size; /* length of descriptor ring in bytes */ 411 dma_addr_t dma; /* physical address of ring */ 412 413 struct i40e_vsi *vsi; /* Backreference to associated VSI */ 414 struct i40e_q_vector *q_vector; /* Backreference to associated vector */ 415 416 struct rcu_head rcu; /* to avoid race on free */ 417 u16 next_to_alloc; 418 struct sk_buff *skb; /* When i40e_clean_rx_ring_irq() must 419 * return before it sees the EOP for 420 * the current packet, we save that skb 421 * here and resume receiving this 422 * packet the next time 423 * i40e_clean_rx_ring_irq() is called 424 * for this ring. 425 */ 426 } ____cacheline_internodealigned_in_smp; 427 428 static inline bool ring_uses_build_skb(struct i40e_ring *ring) 429 { 430 return !!(ring->flags & I40E_RXR_FLAGS_BUILD_SKB_ENABLED); 431 } 432 433 static inline void set_ring_build_skb_enabled(struct i40e_ring *ring) 434 { 435 ring->flags |= I40E_RXR_FLAGS_BUILD_SKB_ENABLED; 436 } 437 438 static inline void clear_ring_build_skb_enabled(struct i40e_ring *ring) 439 { 440 ring->flags &= ~I40E_RXR_FLAGS_BUILD_SKB_ENABLED; 441 } 442 443 static inline bool ring_is_xdp(struct i40e_ring *ring) 444 { 445 return !!(ring->flags & I40E_TXR_FLAGS_XDP); 446 } 447 448 static inline void set_ring_xdp(struct i40e_ring *ring) 449 { 450 ring->flags |= I40E_TXR_FLAGS_XDP; 451 } 452 453 enum i40e_latency_range { 454 I40E_LOWEST_LATENCY = 0, 455 I40E_LOW_LATENCY = 1, 456 I40E_BULK_LATENCY = 2, 457 }; 458 459 struct i40e_ring_container { 460 /* array of pointers to rings */ 461 struct i40e_ring *ring; 462 unsigned int total_bytes; /* total bytes processed this int */ 463 unsigned int total_packets; /* total packets processed this int */ 464 unsigned long last_itr_update; /* jiffies of last ITR update */ 465 u16 count; 466 enum i40e_latency_range latency_range; 467 u16 itr; 468 }; 469 470 /* iterator for handling rings in ring container */ 471 #define i40e_for_each_ring(pos, head) \ 472 for (pos = (head).ring; pos != NULL; pos = pos->next) 473 474 static inline unsigned int i40e_rx_pg_order(struct i40e_ring *ring) 475 { 476 #if (PAGE_SIZE < 8192) 477 if (ring->rx_buf_len > (PAGE_SIZE / 2)) 478 return 1; 479 #endif 480 return 0; 481 } 482 483 #define i40e_rx_pg_size(_ring) (PAGE_SIZE << i40e_rx_pg_order(_ring)) 484 485 bool i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count); 486 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 487 void i40e_clean_tx_ring(struct i40e_ring *tx_ring); 488 void i40e_clean_rx_ring(struct i40e_ring *rx_ring); 489 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring); 490 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring); 491 void i40e_free_tx_resources(struct i40e_ring *tx_ring); 492 void i40e_free_rx_resources(struct i40e_ring *rx_ring); 493 int i40e_napi_poll(struct napi_struct *napi, int budget); 494 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector); 495 u32 i40e_get_tx_pending(struct i40e_ring *ring); 496 int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size); 497 bool __i40e_chk_linearize(struct sk_buff *skb); 498 499 /** 500 * i40e_get_head - Retrieve head from head writeback 501 * @tx_ring: tx ring to fetch head of 502 * 503 * Returns value of Tx ring head based on value stored 504 * in head write-back location 505 **/ 506 static inline u32 i40e_get_head(struct i40e_ring *tx_ring) 507 { 508 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count; 509 510 return le32_to_cpu(*(volatile __le32 *)head); 511 } 512 513 /** 514 * i40e_xmit_descriptor_count - calculate number of Tx descriptors needed 515 * @skb: send buffer 516 * @tx_ring: ring to send buffer on 517 * 518 * Returns number of data descriptors needed for this skb. Returns 0 to indicate 519 * there is not enough descriptors available in this ring since we need at least 520 * one descriptor. 521 **/ 522 static inline int i40e_xmit_descriptor_count(struct sk_buff *skb) 523 { 524 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 525 unsigned int nr_frags = skb_shinfo(skb)->nr_frags; 526 int count = 0, size = skb_headlen(skb); 527 528 for (;;) { 529 count += i40e_txd_use_count(size); 530 531 if (!nr_frags--) 532 break; 533 534 size = skb_frag_size(frag++); 535 } 536 537 return count; 538 } 539 540 /** 541 * i40e_maybe_stop_tx - 1st level check for Tx stop conditions 542 * @tx_ring: the ring to be checked 543 * @size: the size buffer we want to assure is available 544 * 545 * Returns 0 if stop is not needed 546 **/ 547 static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 548 { 549 if (likely(I40E_DESC_UNUSED(tx_ring) >= size)) 550 return 0; 551 return __i40e_maybe_stop_tx(tx_ring, size); 552 } 553 554 /** 555 * i40e_chk_linearize - Check if there are more than 8 fragments per packet 556 * @skb: send buffer 557 * @count: number of buffers used 558 * 559 * Note: Our HW can't scatter-gather more than 8 fragments to build 560 * a packet on the wire and so we need to figure out the cases where we 561 * need to linearize the skb. 562 **/ 563 static inline bool i40e_chk_linearize(struct sk_buff *skb, int count) 564 { 565 /* Both TSO and single send will work if count is less than 8 */ 566 if (likely(count < I40E_MAX_BUFFER_TXD)) 567 return false; 568 569 if (skb_is_gso(skb)) 570 return __i40e_chk_linearize(skb); 571 572 /* we can support up to 8 data buffers for a single send */ 573 return count != I40E_MAX_BUFFER_TXD; 574 } 575 576 /** 577 * txring_txq - Find the netdev Tx ring based on the i40e Tx ring 578 * @ring: Tx ring to find the netdev equivalent of 579 **/ 580 static inline struct netdev_queue *txring_txq(const struct i40e_ring *ring) 581 { 582 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 583 } 584 #endif /* _I40E_TXRX_H_ */ 585