1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #ifndef _I40E_TXRX_H_ 28 #define _I40E_TXRX_H_ 29 30 /* Interrupt Throttling and Rate Limiting Goodies */ 31 32 #define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */ 33 #define I40E_MIN_ITR 0x0001 /* reg uses 2 usec resolution */ 34 #define I40E_ITR_100K 0x0005 35 #define I40E_ITR_50K 0x000A 36 #define I40E_ITR_20K 0x0019 37 #define I40E_ITR_18K 0x001B 38 #define I40E_ITR_8K 0x003E 39 #define I40E_ITR_4K 0x007A 40 #define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */ 41 #define I40E_ITR_RX_DEF I40E_ITR_20K 42 #define I40E_ITR_TX_DEF I40E_ITR_20K 43 #define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ 44 #define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */ 45 #define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */ 46 #define I40E_DEFAULT_IRQ_WORK 256 47 #define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1) 48 #define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC)) 49 #define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1) 50 /* 0x40 is the enable bit for interrupt rate limiting, and must be set if 51 * the value of the rate limit is non-zero 52 */ 53 #define INTRL_ENA BIT(6) 54 #define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2) 55 /** 56 * i40e_intrl_usec_to_reg - convert interrupt rate limit to register 57 * @intrl: interrupt rate limit to convert 58 * 59 * This function converts a decimal interrupt rate limit to the appropriate 60 * register format expected by the firmware when setting interrupt rate limit. 61 */ 62 static inline u16 i40e_intrl_usec_to_reg(int intrl) 63 { 64 if (intrl >> 2) 65 return ((intrl >> 2) | INTRL_ENA); 66 else 67 return 0; 68 } 69 #define I40E_INTRL_8K 125 /* 8000 ints/sec */ 70 #define I40E_INTRL_62K 16 /* 62500 ints/sec */ 71 #define I40E_INTRL_83K 12 /* 83333 ints/sec */ 72 73 #define I40E_QUEUE_END_OF_LIST 0x7FF 74 75 /* this enum matches hardware bits and is meant to be used by DYN_CTLN 76 * registers and QINT registers or more generally anywhere in the manual 77 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 78 * register but instead is a special value meaning "don't update" ITR0/1/2. 79 */ 80 enum i40e_dyn_idx_t { 81 I40E_IDX_ITR0 = 0, 82 I40E_IDX_ITR1 = 1, 83 I40E_IDX_ITR2 = 2, 84 I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 85 }; 86 87 /* these are indexes into ITRN registers */ 88 #define I40E_RX_ITR I40E_IDX_ITR0 89 #define I40E_TX_ITR I40E_IDX_ITR1 90 #define I40E_PE_ITR I40E_IDX_ITR2 91 92 /* Supported RSS offloads */ 93 #define I40E_DEFAULT_RSS_HENA ( \ 94 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 95 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 96 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 97 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 98 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 99 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 100 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 101 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 102 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 103 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 104 BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD)) 105 106 #define I40E_DEFAULT_RSS_HENA_EXPANDED (I40E_DEFAULT_RSS_HENA | \ 107 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 108 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 109 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 110 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ 111 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 112 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP)) 113 114 #define i40e_pf_get_default_rss_hena(pf) \ 115 (((pf)->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \ 116 I40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA) 117 118 /* Supported Rx Buffer Sizes (a multiple of 128) */ 119 #define I40E_RXBUFFER_256 256 120 #define I40E_RXBUFFER_1536 1536 /* 128B aligned standard Ethernet frame */ 121 #define I40E_RXBUFFER_2048 2048 122 #define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */ 123 124 /* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 125 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, 126 * this adds up to 512 bytes of extra data meaning the smallest allocation 127 * we could have is 1K. 128 * i.e. RXBUFFER_256 --> 960 byte skb (size-1024 slab) 129 * i.e. RXBUFFER_512 --> 1216 byte skb (size-2048 slab) 130 */ 131 #define I40E_RX_HDR_SIZE I40E_RXBUFFER_256 132 #define i40e_rx_desc i40e_32byte_rx_desc 133 134 #define I40E_RX_DMA_ATTR \ 135 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 136 137 /** 138 * i40e_test_staterr - tests bits in Rx descriptor status and error fields 139 * @rx_desc: pointer to receive descriptor (in le64 format) 140 * @stat_err_bits: value to mask 141 * 142 * This function does some fast chicanery in order to return the 143 * value of the mask which is really only used for boolean tests. 144 * The status_error_len doesn't need to be shifted because it begins 145 * at offset zero. 146 */ 147 static inline bool i40e_test_staterr(union i40e_rx_desc *rx_desc, 148 const u64 stat_err_bits) 149 { 150 return !!(rx_desc->wb.qword1.status_error_len & 151 cpu_to_le64(stat_err_bits)); 152 } 153 154 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 155 #define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 156 #define I40E_RX_INCREMENT(r, i) \ 157 do { \ 158 (i)++; \ 159 if ((i) == (r)->count) \ 160 i = 0; \ 161 r->next_to_clean = i; \ 162 } while (0) 163 164 #define I40E_RX_NEXT_DESC(r, i, n) \ 165 do { \ 166 (i)++; \ 167 if ((i) == (r)->count) \ 168 i = 0; \ 169 (n) = I40E_RX_DESC((r), (i)); \ 170 } while (0) 171 172 #define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \ 173 do { \ 174 I40E_RX_NEXT_DESC((r), (i), (n)); \ 175 prefetch((n)); \ 176 } while (0) 177 178 #define I40E_MAX_BUFFER_TXD 8 179 #define I40E_MIN_TX_LEN 17 180 181 /* The size limit for a transmit buffer in a descriptor is (16K - 1). 182 * In order to align with the read requests we will align the value to 183 * the nearest 4K which represents our maximum read request size. 184 */ 185 #define I40E_MAX_READ_REQ_SIZE 4096 186 #define I40E_MAX_DATA_PER_TXD (16 * 1024 - 1) 187 #define I40E_MAX_DATA_PER_TXD_ALIGNED \ 188 (I40E_MAX_DATA_PER_TXD & ~(I40E_MAX_READ_REQ_SIZE - 1)) 189 190 /** 191 * i40e_txd_use_count - estimate the number of descriptors needed for Tx 192 * @size: transmit request size in bytes 193 * 194 * Due to hardware alignment restrictions (4K alignment), we need to 195 * assume that we can have no more than 12K of data per descriptor, even 196 * though each descriptor can take up to 16K - 1 bytes of aligned memory. 197 * Thus, we need to divide by 12K. But division is slow! Instead, 198 * we decompose the operation into shifts and one relatively cheap 199 * multiply operation. 200 * 201 * To divide by 12K, we first divide by 4K, then divide by 3: 202 * To divide by 4K, shift right by 12 bits 203 * To divide by 3, multiply by 85, then divide by 256 204 * (Divide by 256 is done by shifting right by 8 bits) 205 * Finally, we add one to round up. Because 256 isn't an exact multiple of 206 * 3, we'll underestimate near each multiple of 12K. This is actually more 207 * accurate as we have 4K - 1 of wiggle room that we can fit into the last 208 * segment. For our purposes this is accurate out to 1M which is orders of 209 * magnitude greater than our largest possible GSO size. 210 * 211 * This would then be implemented as: 212 * return (((size >> 12) * 85) >> 8) + 1; 213 * 214 * Since multiplication and division are commutative, we can reorder 215 * operations into: 216 * return ((size * 85) >> 20) + 1; 217 */ 218 static inline unsigned int i40e_txd_use_count(unsigned int size) 219 { 220 return ((size * 85) >> 20) + 1; 221 } 222 223 /* Tx Descriptors needed, worst case */ 224 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 225 #define I40E_MIN_DESC_PENDING 4 226 227 #define I40E_TX_FLAGS_HW_VLAN BIT(1) 228 #define I40E_TX_FLAGS_SW_VLAN BIT(2) 229 #define I40E_TX_FLAGS_TSO BIT(3) 230 #define I40E_TX_FLAGS_IPV4 BIT(4) 231 #define I40E_TX_FLAGS_IPV6 BIT(5) 232 #define I40E_TX_FLAGS_FCCRC BIT(6) 233 #define I40E_TX_FLAGS_FSO BIT(7) 234 #define I40E_TX_FLAGS_TSYN BIT(8) 235 #define I40E_TX_FLAGS_FD_SB BIT(9) 236 #define I40E_TX_FLAGS_UDP_TUNNEL BIT(10) 237 #define I40E_TX_FLAGS_VLAN_MASK 0xffff0000 238 #define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 239 #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29 240 #define I40E_TX_FLAGS_VLAN_SHIFT 16 241 242 struct i40e_tx_buffer { 243 struct i40e_tx_desc *next_to_watch; 244 union { 245 struct sk_buff *skb; 246 void *raw_buf; 247 }; 248 unsigned int bytecount; 249 unsigned short gso_segs; 250 251 DEFINE_DMA_UNMAP_ADDR(dma); 252 DEFINE_DMA_UNMAP_LEN(len); 253 u32 tx_flags; 254 }; 255 256 struct i40e_rx_buffer { 257 dma_addr_t dma; 258 struct page *page; 259 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 260 __u32 page_offset; 261 #else 262 __u16 page_offset; 263 #endif 264 __u16 pagecnt_bias; 265 }; 266 267 struct i40e_queue_stats { 268 u64 packets; 269 u64 bytes; 270 }; 271 272 struct i40e_tx_queue_stats { 273 u64 restart_queue; 274 u64 tx_busy; 275 u64 tx_done_old; 276 u64 tx_linearize; 277 u64 tx_force_wb; 278 u64 tx_lost_interrupt; 279 }; 280 281 struct i40e_rx_queue_stats { 282 u64 non_eop_descs; 283 u64 alloc_page_failed; 284 u64 alloc_buff_failed; 285 u64 page_reuse_count; 286 u64 realloc_count; 287 }; 288 289 enum i40e_ring_state_t { 290 __I40E_TX_FDIR_INIT_DONE, 291 __I40E_TX_XPS_INIT_DONE, 292 }; 293 294 /* some useful defines for virtchannel interface, which 295 * is the only remaining user of header split 296 */ 297 #define I40E_RX_DTYPE_NO_SPLIT 0 298 #define I40E_RX_DTYPE_HEADER_SPLIT 1 299 #define I40E_RX_DTYPE_SPLIT_ALWAYS 2 300 #define I40E_RX_SPLIT_L2 0x1 301 #define I40E_RX_SPLIT_IP 0x2 302 #define I40E_RX_SPLIT_TCP_UDP 0x4 303 #define I40E_RX_SPLIT_SCTP 0x8 304 305 /* struct that defines a descriptor ring, associated with a VSI */ 306 struct i40e_ring { 307 struct i40e_ring *next; /* pointer to next ring in q_vector */ 308 void *desc; /* Descriptor ring memory */ 309 struct device *dev; /* Used for DMA mapping */ 310 struct net_device *netdev; /* netdev ring maps to */ 311 union { 312 struct i40e_tx_buffer *tx_bi; 313 struct i40e_rx_buffer *rx_bi; 314 }; 315 unsigned long state; 316 u16 queue_index; /* Queue number of ring */ 317 u8 dcb_tc; /* Traffic class of ring */ 318 u8 __iomem *tail; 319 320 /* high bit set means dynamic, use accessor routines to read/write. 321 * hardware only supports 2us resolution for the ITR registers. 322 * these values always store the USER setting, and must be converted 323 * before programming to a register. 324 */ 325 u16 rx_itr_setting; 326 u16 tx_itr_setting; 327 328 u16 count; /* Number of descriptors */ 329 u16 reg_idx; /* HW register index of the ring */ 330 u16 rx_buf_len; 331 332 /* used in interrupt processing */ 333 u16 next_to_use; 334 u16 next_to_clean; 335 336 u8 atr_sample_rate; 337 u8 atr_count; 338 339 bool ring_active; /* is ring online or not */ 340 bool arm_wb; /* do something to arm write back */ 341 u8 packet_stride; 342 343 u16 flags; 344 #define I40E_TXR_FLAGS_WB_ON_ITR BIT(0) 345 346 /* stats structs */ 347 struct i40e_queue_stats stats; 348 struct u64_stats_sync syncp; 349 union { 350 struct i40e_tx_queue_stats tx_stats; 351 struct i40e_rx_queue_stats rx_stats; 352 }; 353 354 unsigned int size; /* length of descriptor ring in bytes */ 355 dma_addr_t dma; /* physical address of ring */ 356 357 struct i40e_vsi *vsi; /* Backreference to associated VSI */ 358 struct i40e_q_vector *q_vector; /* Backreference to associated vector */ 359 360 struct rcu_head rcu; /* to avoid race on free */ 361 u16 next_to_alloc; 362 struct sk_buff *skb; /* When i40e_clean_rx_ring_irq() must 363 * return before it sees the EOP for 364 * the current packet, we save that skb 365 * here and resume receiving this 366 * packet the next time 367 * i40e_clean_rx_ring_irq() is called 368 * for this ring. 369 */ 370 } ____cacheline_internodealigned_in_smp; 371 372 enum i40e_latency_range { 373 I40E_LOWEST_LATENCY = 0, 374 I40E_LOW_LATENCY = 1, 375 I40E_BULK_LATENCY = 2, 376 I40E_ULTRA_LATENCY = 3, 377 }; 378 379 struct i40e_ring_container { 380 /* array of pointers to rings */ 381 struct i40e_ring *ring; 382 unsigned int total_bytes; /* total bytes processed this int */ 383 unsigned int total_packets; /* total packets processed this int */ 384 u16 count; 385 enum i40e_latency_range latency_range; 386 u16 itr; 387 }; 388 389 /* iterator for handling rings in ring container */ 390 #define i40e_for_each_ring(pos, head) \ 391 for (pos = (head).ring; pos != NULL; pos = pos->next) 392 393 bool i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count); 394 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 395 void i40e_clean_tx_ring(struct i40e_ring *tx_ring); 396 void i40e_clean_rx_ring(struct i40e_ring *rx_ring); 397 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring); 398 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring); 399 void i40e_free_tx_resources(struct i40e_ring *tx_ring); 400 void i40e_free_rx_resources(struct i40e_ring *rx_ring); 401 int i40e_napi_poll(struct napi_struct *napi, int budget); 402 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector); 403 u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw); 404 int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size); 405 bool __i40e_chk_linearize(struct sk_buff *skb); 406 407 /** 408 * i40e_get_head - Retrieve head from head writeback 409 * @tx_ring: tx ring to fetch head of 410 * 411 * Returns value of Tx ring head based on value stored 412 * in head write-back location 413 **/ 414 static inline u32 i40e_get_head(struct i40e_ring *tx_ring) 415 { 416 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count; 417 418 return le32_to_cpu(*(volatile __le32 *)head); 419 } 420 421 /** 422 * i40e_xmit_descriptor_count - calculate number of Tx descriptors needed 423 * @skb: send buffer 424 * @tx_ring: ring to send buffer on 425 * 426 * Returns number of data descriptors needed for this skb. Returns 0 to indicate 427 * there is not enough descriptors available in this ring since we need at least 428 * one descriptor. 429 **/ 430 static inline int i40e_xmit_descriptor_count(struct sk_buff *skb) 431 { 432 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 433 unsigned int nr_frags = skb_shinfo(skb)->nr_frags; 434 int count = 0, size = skb_headlen(skb); 435 436 for (;;) { 437 count += i40e_txd_use_count(size); 438 439 if (!nr_frags--) 440 break; 441 442 size = skb_frag_size(frag++); 443 } 444 445 return count; 446 } 447 448 /** 449 * i40e_maybe_stop_tx - 1st level check for Tx stop conditions 450 * @tx_ring: the ring to be checked 451 * @size: the size buffer we want to assure is available 452 * 453 * Returns 0 if stop is not needed 454 **/ 455 static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 456 { 457 if (likely(I40E_DESC_UNUSED(tx_ring) >= size)) 458 return 0; 459 return __i40e_maybe_stop_tx(tx_ring, size); 460 } 461 462 /** 463 * i40e_chk_linearize - Check if there are more than 8 fragments per packet 464 * @skb: send buffer 465 * @count: number of buffers used 466 * 467 * Note: Our HW can't scatter-gather more than 8 fragments to build 468 * a packet on the wire and so we need to figure out the cases where we 469 * need to linearize the skb. 470 **/ 471 static inline bool i40e_chk_linearize(struct sk_buff *skb, int count) 472 { 473 /* Both TSO and single send will work if count is less than 8 */ 474 if (likely(count < I40E_MAX_BUFFER_TXD)) 475 return false; 476 477 if (skb_is_gso(skb)) 478 return __i40e_chk_linearize(skb); 479 480 /* we can support up to 8 data buffers for a single send */ 481 return count != I40E_MAX_BUFFER_TXD; 482 } 483 484 /** 485 * txring_txq - Find the netdev Tx ring based on the i40e Tx ring 486 * @ring: Tx ring to find the netdev equivalent of 487 **/ 488 static inline struct netdev_queue *txring_txq(const struct i40e_ring *ring) 489 { 490 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 491 } 492 #endif /* _I40E_TXRX_H_ */ 493