1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include <linux/prefetch.h> 28 #include <net/busy_poll.h> 29 #include "i40e.h" 30 #include "i40e_trace.h" 31 #include "i40e_prototype.h" 32 33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, 34 u32 td_tag) 35 { 36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | 37 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | 38 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | 39 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | 40 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); 41 } 42 43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) 44 /** 45 * i40e_fdir - Generate a Flow Director descriptor based on fdata 46 * @tx_ring: Tx ring to send buffer on 47 * @fdata: Flow director filter data 48 * @add: Indicate if we are adding a rule or deleting one 49 * 50 **/ 51 static void i40e_fdir(struct i40e_ring *tx_ring, 52 struct i40e_fdir_filter *fdata, bool add) 53 { 54 struct i40e_filter_program_desc *fdir_desc; 55 struct i40e_pf *pf = tx_ring->vsi->back; 56 u32 flex_ptype, dtype_cmd; 57 u16 i; 58 59 /* grab the next descriptor */ 60 i = tx_ring->next_to_use; 61 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 62 63 i++; 64 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 65 66 flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK & 67 (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT); 68 69 flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK & 70 (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT); 71 72 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK & 73 (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 74 75 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK & 76 (fdata->flex_offset << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT); 77 78 /* Use LAN VSI Id if not programmed by user */ 79 flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK & 80 ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) << 81 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT); 82 83 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 84 85 dtype_cmd |= add ? 86 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 87 I40E_TXD_FLTR_QW1_PCMD_SHIFT : 88 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 89 I40E_TXD_FLTR_QW1_PCMD_SHIFT; 90 91 dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK & 92 (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT); 93 94 dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK & 95 (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT); 96 97 if (fdata->cnt_index) { 98 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 99 dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK & 100 ((u32)fdata->cnt_index << 101 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT); 102 } 103 104 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); 105 fdir_desc->rsvd = cpu_to_le32(0); 106 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); 107 fdir_desc->fd_id = cpu_to_le32(fdata->fd_id); 108 } 109 110 #define I40E_FD_CLEAN_DELAY 10 111 /** 112 * i40e_program_fdir_filter - Program a Flow Director filter 113 * @fdir_data: Packet data that will be filter parameters 114 * @raw_packet: the pre-allocated packet buffer for FDir 115 * @pf: The PF pointer 116 * @add: True for add/update, False for remove 117 **/ 118 static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, 119 u8 *raw_packet, struct i40e_pf *pf, 120 bool add) 121 { 122 struct i40e_tx_buffer *tx_buf, *first; 123 struct i40e_tx_desc *tx_desc; 124 struct i40e_ring *tx_ring; 125 struct i40e_vsi *vsi; 126 struct device *dev; 127 dma_addr_t dma; 128 u32 td_cmd = 0; 129 u16 i; 130 131 /* find existing FDIR VSI */ 132 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); 133 if (!vsi) 134 return -ENOENT; 135 136 tx_ring = vsi->tx_rings[0]; 137 dev = tx_ring->dev; 138 139 /* we need two descriptors to add/del a filter and we can wait */ 140 for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) { 141 if (!i) 142 return -EAGAIN; 143 msleep_interruptible(1); 144 } 145 146 dma = dma_map_single(dev, raw_packet, 147 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); 148 if (dma_mapping_error(dev, dma)) 149 goto dma_fail; 150 151 /* grab the next descriptor */ 152 i = tx_ring->next_to_use; 153 first = &tx_ring->tx_bi[i]; 154 i40e_fdir(tx_ring, fdir_data, add); 155 156 /* Now program a dummy descriptor */ 157 i = tx_ring->next_to_use; 158 tx_desc = I40E_TX_DESC(tx_ring, i); 159 tx_buf = &tx_ring->tx_bi[i]; 160 161 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; 162 163 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); 164 165 /* record length, and DMA address */ 166 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); 167 dma_unmap_addr_set(tx_buf, dma, dma); 168 169 tx_desc->buffer_addr = cpu_to_le64(dma); 170 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; 171 172 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; 173 tx_buf->raw_buf = (void *)raw_packet; 174 175 tx_desc->cmd_type_offset_bsz = 176 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); 177 178 /* Force memory writes to complete before letting h/w 179 * know there are new descriptors to fetch. 180 */ 181 wmb(); 182 183 /* Mark the data descriptor to be watched */ 184 first->next_to_watch = tx_desc; 185 186 writel(tx_ring->next_to_use, tx_ring->tail); 187 return 0; 188 189 dma_fail: 190 return -1; 191 } 192 193 #define IP_HEADER_OFFSET 14 194 #define I40E_UDPIP_DUMMY_PACKET_LEN 42 195 /** 196 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters 197 * @vsi: pointer to the targeted VSI 198 * @fd_data: the flow director data required for the FDir descriptor 199 * @add: true adds a filter, false removes it 200 * 201 * Returns 0 if the filters were successfully added or removed 202 **/ 203 static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi, 204 struct i40e_fdir_filter *fd_data, 205 bool add) 206 { 207 struct i40e_pf *pf = vsi->back; 208 struct udphdr *udp; 209 struct iphdr *ip; 210 u8 *raw_packet; 211 int ret; 212 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 213 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0, 214 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 215 216 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 217 if (!raw_packet) 218 return -ENOMEM; 219 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN); 220 221 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 222 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET 223 + sizeof(struct iphdr)); 224 225 ip->daddr = fd_data->dst_ip; 226 udp->dest = fd_data->dst_port; 227 ip->saddr = fd_data->src_ip; 228 udp->source = fd_data->src_port; 229 230 if (fd_data->flex_filter) { 231 u8 *payload = raw_packet + I40E_UDPIP_DUMMY_PACKET_LEN; 232 __be16 pattern = fd_data->flex_word; 233 u16 off = fd_data->flex_offset; 234 235 *((__force __be16 *)(payload + off)) = pattern; 236 } 237 238 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; 239 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 240 if (ret) { 241 dev_info(&pf->pdev->dev, 242 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 243 fd_data->pctype, fd_data->fd_id, ret); 244 /* Free the packet buffer since it wasn't added to the ring */ 245 kfree(raw_packet); 246 return -EOPNOTSUPP; 247 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 248 if (add) 249 dev_info(&pf->pdev->dev, 250 "Filter OK for PCTYPE %d loc = %d\n", 251 fd_data->pctype, fd_data->fd_id); 252 else 253 dev_info(&pf->pdev->dev, 254 "Filter deleted for PCTYPE %d loc = %d\n", 255 fd_data->pctype, fd_data->fd_id); 256 } 257 258 if (add) 259 pf->fd_udp4_filter_cnt++; 260 else 261 pf->fd_udp4_filter_cnt--; 262 263 return 0; 264 } 265 266 #define I40E_TCPIP_DUMMY_PACKET_LEN 54 267 /** 268 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters 269 * @vsi: pointer to the targeted VSI 270 * @fd_data: the flow director data required for the FDir descriptor 271 * @add: true adds a filter, false removes it 272 * 273 * Returns 0 if the filters were successfully added or removed 274 **/ 275 static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi, 276 struct i40e_fdir_filter *fd_data, 277 bool add) 278 { 279 struct i40e_pf *pf = vsi->back; 280 struct tcphdr *tcp; 281 struct iphdr *ip; 282 u8 *raw_packet; 283 int ret; 284 /* Dummy packet */ 285 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 286 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0, 287 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11, 288 0x0, 0x72, 0, 0, 0, 0}; 289 290 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 291 if (!raw_packet) 292 return -ENOMEM; 293 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN); 294 295 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 296 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET 297 + sizeof(struct iphdr)); 298 299 ip->daddr = fd_data->dst_ip; 300 tcp->dest = fd_data->dst_port; 301 ip->saddr = fd_data->src_ip; 302 tcp->source = fd_data->src_port; 303 304 if (fd_data->flex_filter) { 305 u8 *payload = raw_packet + I40E_TCPIP_DUMMY_PACKET_LEN; 306 __be16 pattern = fd_data->flex_word; 307 u16 off = fd_data->flex_offset; 308 309 *((__force __be16 *)(payload + off)) = pattern; 310 } 311 312 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP; 313 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 314 if (ret) { 315 dev_info(&pf->pdev->dev, 316 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 317 fd_data->pctype, fd_data->fd_id, ret); 318 /* Free the packet buffer since it wasn't added to the ring */ 319 kfree(raw_packet); 320 return -EOPNOTSUPP; 321 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 322 if (add) 323 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n", 324 fd_data->pctype, fd_data->fd_id); 325 else 326 dev_info(&pf->pdev->dev, 327 "Filter deleted for PCTYPE %d loc = %d\n", 328 fd_data->pctype, fd_data->fd_id); 329 } 330 331 if (add) { 332 pf->fd_tcp4_filter_cnt++; 333 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && 334 I40E_DEBUG_FD & pf->hw.debug_mask) 335 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); 336 pf->flags |= I40E_FLAG_FD_ATR_AUTO_DISABLED; 337 } else { 338 pf->fd_tcp4_filter_cnt--; 339 } 340 341 return 0; 342 } 343 344 #define I40E_SCTPIP_DUMMY_PACKET_LEN 46 345 /** 346 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for 347 * a specific flow spec 348 * @vsi: pointer to the targeted VSI 349 * @fd_data: the flow director data required for the FDir descriptor 350 * @add: true adds a filter, false removes it 351 * 352 * Returns 0 if the filters were successfully added or removed 353 **/ 354 static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi, 355 struct i40e_fdir_filter *fd_data, 356 bool add) 357 { 358 struct i40e_pf *pf = vsi->back; 359 struct sctphdr *sctp; 360 struct iphdr *ip; 361 u8 *raw_packet; 362 int ret; 363 /* Dummy packet */ 364 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 365 0x45, 0, 0, 0x20, 0, 0, 0x40, 0, 0x40, 0x84, 0, 0, 0, 0, 0, 0, 366 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 367 368 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 369 if (!raw_packet) 370 return -ENOMEM; 371 memcpy(raw_packet, packet, I40E_SCTPIP_DUMMY_PACKET_LEN); 372 373 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 374 sctp = (struct sctphdr *)(raw_packet + IP_HEADER_OFFSET 375 + sizeof(struct iphdr)); 376 377 ip->daddr = fd_data->dst_ip; 378 sctp->dest = fd_data->dst_port; 379 ip->saddr = fd_data->src_ip; 380 sctp->source = fd_data->src_port; 381 382 if (fd_data->flex_filter) { 383 u8 *payload = raw_packet + I40E_SCTPIP_DUMMY_PACKET_LEN; 384 __be16 pattern = fd_data->flex_word; 385 u16 off = fd_data->flex_offset; 386 387 *((__force __be16 *)(payload + off)) = pattern; 388 } 389 390 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP; 391 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 392 if (ret) { 393 dev_info(&pf->pdev->dev, 394 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 395 fd_data->pctype, fd_data->fd_id, ret); 396 /* Free the packet buffer since it wasn't added to the ring */ 397 kfree(raw_packet); 398 return -EOPNOTSUPP; 399 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 400 if (add) 401 dev_info(&pf->pdev->dev, 402 "Filter OK for PCTYPE %d loc = %d\n", 403 fd_data->pctype, fd_data->fd_id); 404 else 405 dev_info(&pf->pdev->dev, 406 "Filter deleted for PCTYPE %d loc = %d\n", 407 fd_data->pctype, fd_data->fd_id); 408 } 409 410 if (add) 411 pf->fd_sctp4_filter_cnt++; 412 else 413 pf->fd_sctp4_filter_cnt--; 414 415 return 0; 416 } 417 418 #define I40E_IP_DUMMY_PACKET_LEN 34 419 /** 420 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for 421 * a specific flow spec 422 * @vsi: pointer to the targeted VSI 423 * @fd_data: the flow director data required for the FDir descriptor 424 * @add: true adds a filter, false removes it 425 * 426 * Returns 0 if the filters were successfully added or removed 427 **/ 428 static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi, 429 struct i40e_fdir_filter *fd_data, 430 bool add) 431 { 432 struct i40e_pf *pf = vsi->back; 433 struct iphdr *ip; 434 u8 *raw_packet; 435 int ret; 436 int i; 437 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 438 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0, 439 0, 0, 0, 0}; 440 441 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; 442 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) { 443 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 444 if (!raw_packet) 445 return -ENOMEM; 446 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN); 447 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 448 449 ip->saddr = fd_data->src_ip; 450 ip->daddr = fd_data->dst_ip; 451 ip->protocol = 0; 452 453 if (fd_data->flex_filter) { 454 u8 *payload = raw_packet + I40E_IP_DUMMY_PACKET_LEN; 455 __be16 pattern = fd_data->flex_word; 456 u16 off = fd_data->flex_offset; 457 458 *((__force __be16 *)(payload + off)) = pattern; 459 } 460 461 fd_data->pctype = i; 462 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 463 if (ret) { 464 dev_info(&pf->pdev->dev, 465 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 466 fd_data->pctype, fd_data->fd_id, ret); 467 /* The packet buffer wasn't added to the ring so we 468 * need to free it now. 469 */ 470 kfree(raw_packet); 471 return -EOPNOTSUPP; 472 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 473 if (add) 474 dev_info(&pf->pdev->dev, 475 "Filter OK for PCTYPE %d loc = %d\n", 476 fd_data->pctype, fd_data->fd_id); 477 else 478 dev_info(&pf->pdev->dev, 479 "Filter deleted for PCTYPE %d loc = %d\n", 480 fd_data->pctype, fd_data->fd_id); 481 } 482 } 483 484 if (add) 485 pf->fd_ip4_filter_cnt++; 486 else 487 pf->fd_ip4_filter_cnt--; 488 489 return 0; 490 } 491 492 /** 493 * i40e_add_del_fdir - Build raw packets to add/del fdir filter 494 * @vsi: pointer to the targeted VSI 495 * @cmd: command to get or set RX flow classification rules 496 * @add: true adds a filter, false removes it 497 * 498 **/ 499 int i40e_add_del_fdir(struct i40e_vsi *vsi, 500 struct i40e_fdir_filter *input, bool add) 501 { 502 struct i40e_pf *pf = vsi->back; 503 int ret; 504 505 switch (input->flow_type & ~FLOW_EXT) { 506 case TCP_V4_FLOW: 507 ret = i40e_add_del_fdir_tcpv4(vsi, input, add); 508 break; 509 case UDP_V4_FLOW: 510 ret = i40e_add_del_fdir_udpv4(vsi, input, add); 511 break; 512 case SCTP_V4_FLOW: 513 ret = i40e_add_del_fdir_sctpv4(vsi, input, add); 514 break; 515 case IP_USER_FLOW: 516 switch (input->ip4_proto) { 517 case IPPROTO_TCP: 518 ret = i40e_add_del_fdir_tcpv4(vsi, input, add); 519 break; 520 case IPPROTO_UDP: 521 ret = i40e_add_del_fdir_udpv4(vsi, input, add); 522 break; 523 case IPPROTO_SCTP: 524 ret = i40e_add_del_fdir_sctpv4(vsi, input, add); 525 break; 526 case IPPROTO_IP: 527 ret = i40e_add_del_fdir_ipv4(vsi, input, add); 528 break; 529 default: 530 /* We cannot support masking based on protocol */ 531 dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n", 532 input->ip4_proto); 533 return -EINVAL; 534 } 535 break; 536 default: 537 dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n", 538 input->flow_type); 539 return -EINVAL; 540 } 541 542 /* The buffer allocated here will be normally be freed by 543 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit 544 * completion. In the event of an error adding the buffer to the FDIR 545 * ring, it will immediately be freed. It may also be freed by 546 * i40e_clean_tx_ring() when closing the VSI. 547 */ 548 return ret; 549 } 550 551 /** 552 * i40e_fd_handle_status - check the Programming Status for FD 553 * @rx_ring: the Rx ring for this descriptor 554 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor. 555 * @prog_id: the id originally used for programming 556 * 557 * This is used to verify if the FD programming or invalidation 558 * requested by SW to the HW is successful or not and take actions accordingly. 559 **/ 560 static void i40e_fd_handle_status(struct i40e_ring *rx_ring, 561 union i40e_rx_desc *rx_desc, u8 prog_id) 562 { 563 struct i40e_pf *pf = rx_ring->vsi->back; 564 struct pci_dev *pdev = pf->pdev; 565 u32 fcnt_prog, fcnt_avail; 566 u32 error; 567 u64 qw; 568 569 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 570 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >> 571 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT; 572 573 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { 574 pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id); 575 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) || 576 (I40E_DEBUG_FD & pf->hw.debug_mask)) 577 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", 578 pf->fd_inv); 579 580 /* Check if the programming error is for ATR. 581 * If so, auto disable ATR and set a state for 582 * flush in progress. Next time we come here if flush is in 583 * progress do nothing, once flush is complete the state will 584 * be cleared. 585 */ 586 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) 587 return; 588 589 pf->fd_add_err++; 590 /* store the current atr filter count */ 591 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); 592 593 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) && 594 pf->flags & I40E_FLAG_FD_SB_AUTO_DISABLED) { 595 pf->flags |= I40E_FLAG_FD_ATR_AUTO_DISABLED; 596 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state); 597 } 598 599 /* filter programming failed most likely due to table full */ 600 fcnt_prog = i40e_get_global_fd_count(pf); 601 fcnt_avail = pf->fdir_pf_filter_count; 602 /* If ATR is running fcnt_prog can quickly change, 603 * if we are very close to full, it makes sense to disable 604 * FD ATR/SB and then re-enable it when there is room. 605 */ 606 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { 607 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && 608 !(pf->flags & I40E_FLAG_FD_SB_AUTO_DISABLED)) { 609 pf->flags |= I40E_FLAG_FD_SB_AUTO_DISABLED; 610 if (I40E_DEBUG_FD & pf->hw.debug_mask) 611 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); 612 } 613 } 614 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { 615 if (I40E_DEBUG_FD & pf->hw.debug_mask) 616 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", 617 rx_desc->wb.qword0.hi_dword.fd_id); 618 } 619 } 620 621 /** 622 * i40e_unmap_and_free_tx_resource - Release a Tx buffer 623 * @ring: the ring that owns the buffer 624 * @tx_buffer: the buffer to free 625 **/ 626 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, 627 struct i40e_tx_buffer *tx_buffer) 628 { 629 if (tx_buffer->skb) { 630 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) 631 kfree(tx_buffer->raw_buf); 632 else 633 dev_kfree_skb_any(tx_buffer->skb); 634 if (dma_unmap_len(tx_buffer, len)) 635 dma_unmap_single(ring->dev, 636 dma_unmap_addr(tx_buffer, dma), 637 dma_unmap_len(tx_buffer, len), 638 DMA_TO_DEVICE); 639 } else if (dma_unmap_len(tx_buffer, len)) { 640 dma_unmap_page(ring->dev, 641 dma_unmap_addr(tx_buffer, dma), 642 dma_unmap_len(tx_buffer, len), 643 DMA_TO_DEVICE); 644 } 645 646 tx_buffer->next_to_watch = NULL; 647 tx_buffer->skb = NULL; 648 dma_unmap_len_set(tx_buffer, len, 0); 649 /* tx_buffer must be completely set up in the transmit path */ 650 } 651 652 /** 653 * i40e_clean_tx_ring - Free any empty Tx buffers 654 * @tx_ring: ring to be cleaned 655 **/ 656 void i40e_clean_tx_ring(struct i40e_ring *tx_ring) 657 { 658 unsigned long bi_size; 659 u16 i; 660 661 /* ring already cleared, nothing to do */ 662 if (!tx_ring->tx_bi) 663 return; 664 665 /* Free all the Tx ring sk_buffs */ 666 for (i = 0; i < tx_ring->count; i++) 667 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); 668 669 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 670 memset(tx_ring->tx_bi, 0, bi_size); 671 672 /* Zero out the descriptor ring */ 673 memset(tx_ring->desc, 0, tx_ring->size); 674 675 tx_ring->next_to_use = 0; 676 tx_ring->next_to_clean = 0; 677 678 if (!tx_ring->netdev) 679 return; 680 681 /* cleanup Tx queue statistics */ 682 netdev_tx_reset_queue(txring_txq(tx_ring)); 683 } 684 685 /** 686 * i40e_free_tx_resources - Free Tx resources per queue 687 * @tx_ring: Tx descriptor ring for a specific queue 688 * 689 * Free all transmit software resources 690 **/ 691 void i40e_free_tx_resources(struct i40e_ring *tx_ring) 692 { 693 i40e_clean_tx_ring(tx_ring); 694 kfree(tx_ring->tx_bi); 695 tx_ring->tx_bi = NULL; 696 697 if (tx_ring->desc) { 698 dma_free_coherent(tx_ring->dev, tx_ring->size, 699 tx_ring->desc, tx_ring->dma); 700 tx_ring->desc = NULL; 701 } 702 } 703 704 /** 705 * i40e_get_tx_pending - how many tx descriptors not processed 706 * @tx_ring: the ring of descriptors 707 * 708 * Since there is no access to the ring head register 709 * in XL710, we need to use our local copies 710 **/ 711 u32 i40e_get_tx_pending(struct i40e_ring *ring) 712 { 713 u32 head, tail; 714 715 head = i40e_get_head(ring); 716 tail = readl(ring->tail); 717 718 if (head != tail) 719 return (head < tail) ? 720 tail - head : (tail + ring->count - head); 721 722 return 0; 723 } 724 725 #define WB_STRIDE 4 726 727 /** 728 * i40e_clean_tx_irq - Reclaim resources after transmit completes 729 * @vsi: the VSI we care about 730 * @tx_ring: Tx ring to clean 731 * @napi_budget: Used to determine if we are in netpoll 732 * 733 * Returns true if there's any budget left (e.g. the clean is finished) 734 **/ 735 static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, 736 struct i40e_ring *tx_ring, int napi_budget) 737 { 738 u16 i = tx_ring->next_to_clean; 739 struct i40e_tx_buffer *tx_buf; 740 struct i40e_tx_desc *tx_head; 741 struct i40e_tx_desc *tx_desc; 742 unsigned int total_bytes = 0, total_packets = 0; 743 unsigned int budget = vsi->work_limit; 744 745 tx_buf = &tx_ring->tx_bi[i]; 746 tx_desc = I40E_TX_DESC(tx_ring, i); 747 i -= tx_ring->count; 748 749 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); 750 751 do { 752 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; 753 754 /* if next_to_watch is not set then there is no work pending */ 755 if (!eop_desc) 756 break; 757 758 /* prevent any other reads prior to eop_desc */ 759 read_barrier_depends(); 760 761 i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf); 762 /* we have caught up to head, no work left to do */ 763 if (tx_head == tx_desc) 764 break; 765 766 /* clear next_to_watch to prevent false hangs */ 767 tx_buf->next_to_watch = NULL; 768 769 /* update the statistics for this packet */ 770 total_bytes += tx_buf->bytecount; 771 total_packets += tx_buf->gso_segs; 772 773 /* free the skb */ 774 napi_consume_skb(tx_buf->skb, napi_budget); 775 776 /* unmap skb header data */ 777 dma_unmap_single(tx_ring->dev, 778 dma_unmap_addr(tx_buf, dma), 779 dma_unmap_len(tx_buf, len), 780 DMA_TO_DEVICE); 781 782 /* clear tx_buffer data */ 783 tx_buf->skb = NULL; 784 dma_unmap_len_set(tx_buf, len, 0); 785 786 /* unmap remaining buffers */ 787 while (tx_desc != eop_desc) { 788 i40e_trace(clean_tx_irq_unmap, 789 tx_ring, tx_desc, tx_buf); 790 791 tx_buf++; 792 tx_desc++; 793 i++; 794 if (unlikely(!i)) { 795 i -= tx_ring->count; 796 tx_buf = tx_ring->tx_bi; 797 tx_desc = I40E_TX_DESC(tx_ring, 0); 798 } 799 800 /* unmap any remaining paged data */ 801 if (dma_unmap_len(tx_buf, len)) { 802 dma_unmap_page(tx_ring->dev, 803 dma_unmap_addr(tx_buf, dma), 804 dma_unmap_len(tx_buf, len), 805 DMA_TO_DEVICE); 806 dma_unmap_len_set(tx_buf, len, 0); 807 } 808 } 809 810 /* move us one more past the eop_desc for start of next pkt */ 811 tx_buf++; 812 tx_desc++; 813 i++; 814 if (unlikely(!i)) { 815 i -= tx_ring->count; 816 tx_buf = tx_ring->tx_bi; 817 tx_desc = I40E_TX_DESC(tx_ring, 0); 818 } 819 820 prefetch(tx_desc); 821 822 /* update budget accounting */ 823 budget--; 824 } while (likely(budget)); 825 826 i += tx_ring->count; 827 tx_ring->next_to_clean = i; 828 u64_stats_update_begin(&tx_ring->syncp); 829 tx_ring->stats.bytes += total_bytes; 830 tx_ring->stats.packets += total_packets; 831 u64_stats_update_end(&tx_ring->syncp); 832 tx_ring->q_vector->tx.total_bytes += total_bytes; 833 tx_ring->q_vector->tx.total_packets += total_packets; 834 835 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) { 836 /* check to see if there are < 4 descriptors 837 * waiting to be written back, then kick the hardware to force 838 * them to be written back in case we stay in NAPI. 839 * In this mode on X722 we do not enable Interrupt. 840 */ 841 unsigned int j = i40e_get_tx_pending(tx_ring); 842 843 if (budget && 844 ((j / WB_STRIDE) == 0) && (j > 0) && 845 !test_bit(__I40E_VSI_DOWN, vsi->state) && 846 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) 847 tx_ring->arm_wb = true; 848 } 849 850 /* notify netdev of completed buffers */ 851 netdev_tx_completed_queue(txring_txq(tx_ring), 852 total_packets, total_bytes); 853 854 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 855 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 856 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { 857 /* Make sure that anybody stopping the queue after this 858 * sees the new next_to_clean. 859 */ 860 smp_mb(); 861 if (__netif_subqueue_stopped(tx_ring->netdev, 862 tx_ring->queue_index) && 863 !test_bit(__I40E_VSI_DOWN, vsi->state)) { 864 netif_wake_subqueue(tx_ring->netdev, 865 tx_ring->queue_index); 866 ++tx_ring->tx_stats.restart_queue; 867 } 868 } 869 870 return !!budget; 871 } 872 873 /** 874 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled 875 * @vsi: the VSI we care about 876 * @q_vector: the vector on which to enable writeback 877 * 878 **/ 879 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, 880 struct i40e_q_vector *q_vector) 881 { 882 u16 flags = q_vector->tx.ring[0].flags; 883 u32 val; 884 885 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) 886 return; 887 888 if (q_vector->arm_wb_state) 889 return; 890 891 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { 892 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK | 893 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */ 894 895 wr32(&vsi->back->hw, 896 I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1), 897 val); 898 } else { 899 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK | 900 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */ 901 902 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); 903 } 904 q_vector->arm_wb_state = true; 905 } 906 907 /** 908 * i40e_force_wb - Issue SW Interrupt so HW does a wb 909 * @vsi: the VSI we care about 910 * @q_vector: the vector on which to force writeback 911 * 912 **/ 913 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) 914 { 915 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { 916 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 917 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */ 918 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | 919 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; 920 /* allow 00 to be written to the index */ 921 922 wr32(&vsi->back->hw, 923 I40E_PFINT_DYN_CTLN(q_vector->v_idx + 924 vsi->base_vector - 1), val); 925 } else { 926 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK | 927 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */ 928 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK | 929 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK; 930 /* allow 00 to be written to the index */ 931 932 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val); 933 } 934 } 935 936 /** 937 * i40e_set_new_dynamic_itr - Find new ITR level 938 * @rc: structure containing ring performance data 939 * 940 * Returns true if ITR changed, false if not 941 * 942 * Stores a new ITR value based on packets and byte counts during 943 * the last interrupt. The advantage of per interrupt computation 944 * is faster updates and more accurate ITR for the current traffic 945 * pattern. Constants in this function were computed based on 946 * theoretical maximum wire speed and thresholds were set based on 947 * testing data as well as attempting to minimize response time 948 * while increasing bulk throughput. 949 **/ 950 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) 951 { 952 enum i40e_latency_range new_latency_range = rc->latency_range; 953 struct i40e_q_vector *qv = rc->ring->q_vector; 954 u32 new_itr = rc->itr; 955 int bytes_per_int; 956 int usecs; 957 958 if (rc->total_packets == 0 || !rc->itr) 959 return false; 960 961 /* simple throttlerate management 962 * 0-10MB/s lowest (50000 ints/s) 963 * 10-20MB/s low (20000 ints/s) 964 * 20-1249MB/s bulk (18000 ints/s) 965 * > 40000 Rx packets per second (8000 ints/s) 966 * 967 * The math works out because the divisor is in 10^(-6) which 968 * turns the bytes/us input value into MB/s values, but 969 * make sure to use usecs, as the register values written 970 * are in 2 usec increments in the ITR registers, and make sure 971 * to use the smoothed values that the countdown timer gives us. 972 */ 973 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START; 974 bytes_per_int = rc->total_bytes / usecs; 975 976 switch (new_latency_range) { 977 case I40E_LOWEST_LATENCY: 978 if (bytes_per_int > 10) 979 new_latency_range = I40E_LOW_LATENCY; 980 break; 981 case I40E_LOW_LATENCY: 982 if (bytes_per_int > 20) 983 new_latency_range = I40E_BULK_LATENCY; 984 else if (bytes_per_int <= 10) 985 new_latency_range = I40E_LOWEST_LATENCY; 986 break; 987 case I40E_BULK_LATENCY: 988 case I40E_ULTRA_LATENCY: 989 default: 990 if (bytes_per_int <= 20) 991 new_latency_range = I40E_LOW_LATENCY; 992 break; 993 } 994 995 /* this is to adjust RX more aggressively when streaming small 996 * packets. The value of 40000 was picked as it is just beyond 997 * what the hardware can receive per second if in low latency 998 * mode. 999 */ 1000 #define RX_ULTRA_PACKET_RATE 40000 1001 1002 if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) && 1003 (&qv->rx == rc)) 1004 new_latency_range = I40E_ULTRA_LATENCY; 1005 1006 rc->latency_range = new_latency_range; 1007 1008 switch (new_latency_range) { 1009 case I40E_LOWEST_LATENCY: 1010 new_itr = I40E_ITR_50K; 1011 break; 1012 case I40E_LOW_LATENCY: 1013 new_itr = I40E_ITR_20K; 1014 break; 1015 case I40E_BULK_LATENCY: 1016 new_itr = I40E_ITR_18K; 1017 break; 1018 case I40E_ULTRA_LATENCY: 1019 new_itr = I40E_ITR_8K; 1020 break; 1021 default: 1022 break; 1023 } 1024 1025 rc->total_bytes = 0; 1026 rc->total_packets = 0; 1027 1028 if (new_itr != rc->itr) { 1029 rc->itr = new_itr; 1030 return true; 1031 } 1032 1033 return false; 1034 } 1035 1036 /** 1037 * i40e_rx_is_programming_status - check for programming status descriptor 1038 * @qw: qword representing status_error_len in CPU ordering 1039 * 1040 * The value of in the descriptor length field indicate if this 1041 * is a programming status descriptor for flow director or FCoE 1042 * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise 1043 * it is a packet descriptor. 1044 **/ 1045 static inline bool i40e_rx_is_programming_status(u64 qw) 1046 { 1047 /* The Rx filter programming status and SPH bit occupy the same 1048 * spot in the descriptor. Since we don't support packet split we 1049 * can just reuse the bit as an indication that this is a 1050 * programming status descriptor. 1051 */ 1052 return qw & I40E_RXD_QW1_LENGTH_SPH_MASK; 1053 } 1054 1055 /** 1056 * i40e_clean_programming_status - clean the programming status descriptor 1057 * @rx_ring: the rx ring that has this descriptor 1058 * @rx_desc: the rx descriptor written back by HW 1059 * @qw: qword representing status_error_len in CPU ordering 1060 * 1061 * Flow director should handle FD_FILTER_STATUS to check its filter programming 1062 * status being successful or not and take actions accordingly. FCoE should 1063 * handle its context/filter programming/invalidation status and take actions. 1064 * 1065 **/ 1066 static void i40e_clean_programming_status(struct i40e_ring *rx_ring, 1067 union i40e_rx_desc *rx_desc, 1068 u64 qw) 1069 { 1070 u32 ntc = rx_ring->next_to_clean + 1; 1071 u8 id; 1072 1073 /* fetch, update, and store next to clean */ 1074 ntc = (ntc < rx_ring->count) ? ntc : 0; 1075 rx_ring->next_to_clean = ntc; 1076 1077 prefetch(I40E_RX_DESC(rx_ring, ntc)); 1078 1079 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >> 1080 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT; 1081 1082 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) 1083 i40e_fd_handle_status(rx_ring, rx_desc, id); 1084 } 1085 1086 /** 1087 * i40e_setup_tx_descriptors - Allocate the Tx descriptors 1088 * @tx_ring: the tx ring to set up 1089 * 1090 * Return 0 on success, negative on error 1091 **/ 1092 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) 1093 { 1094 struct device *dev = tx_ring->dev; 1095 int bi_size; 1096 1097 if (!dev) 1098 return -ENOMEM; 1099 1100 /* warn if we are about to overwrite the pointer */ 1101 WARN_ON(tx_ring->tx_bi); 1102 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 1103 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); 1104 if (!tx_ring->tx_bi) 1105 goto err; 1106 1107 /* round up to nearest 4K */ 1108 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); 1109 /* add u32 for head writeback, align after this takes care of 1110 * guaranteeing this is at least one cache line in size 1111 */ 1112 tx_ring->size += sizeof(u32); 1113 tx_ring->size = ALIGN(tx_ring->size, 4096); 1114 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 1115 &tx_ring->dma, GFP_KERNEL); 1116 if (!tx_ring->desc) { 1117 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", 1118 tx_ring->size); 1119 goto err; 1120 } 1121 1122 tx_ring->next_to_use = 0; 1123 tx_ring->next_to_clean = 0; 1124 return 0; 1125 1126 err: 1127 kfree(tx_ring->tx_bi); 1128 tx_ring->tx_bi = NULL; 1129 return -ENOMEM; 1130 } 1131 1132 /** 1133 * i40e_clean_rx_ring - Free Rx buffers 1134 * @rx_ring: ring to be cleaned 1135 **/ 1136 void i40e_clean_rx_ring(struct i40e_ring *rx_ring) 1137 { 1138 unsigned long bi_size; 1139 u16 i; 1140 1141 /* ring already cleared, nothing to do */ 1142 if (!rx_ring->rx_bi) 1143 return; 1144 1145 if (rx_ring->skb) { 1146 dev_kfree_skb(rx_ring->skb); 1147 rx_ring->skb = NULL; 1148 } 1149 1150 /* Free all the Rx ring sk_buffs */ 1151 for (i = 0; i < rx_ring->count; i++) { 1152 struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i]; 1153 1154 if (!rx_bi->page) 1155 continue; 1156 1157 /* Invalidate cache lines that may have been written to by 1158 * device so that we avoid corrupting memory. 1159 */ 1160 dma_sync_single_range_for_cpu(rx_ring->dev, 1161 rx_bi->dma, 1162 rx_bi->page_offset, 1163 rx_ring->rx_buf_len, 1164 DMA_FROM_DEVICE); 1165 1166 /* free resources associated with mapping */ 1167 dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma, 1168 i40e_rx_pg_size(rx_ring), 1169 DMA_FROM_DEVICE, 1170 I40E_RX_DMA_ATTR); 1171 1172 __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias); 1173 1174 rx_bi->page = NULL; 1175 rx_bi->page_offset = 0; 1176 } 1177 1178 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; 1179 memset(rx_ring->rx_bi, 0, bi_size); 1180 1181 /* Zero out the descriptor ring */ 1182 memset(rx_ring->desc, 0, rx_ring->size); 1183 1184 rx_ring->next_to_alloc = 0; 1185 rx_ring->next_to_clean = 0; 1186 rx_ring->next_to_use = 0; 1187 } 1188 1189 /** 1190 * i40e_free_rx_resources - Free Rx resources 1191 * @rx_ring: ring to clean the resources from 1192 * 1193 * Free all receive software resources 1194 **/ 1195 void i40e_free_rx_resources(struct i40e_ring *rx_ring) 1196 { 1197 i40e_clean_rx_ring(rx_ring); 1198 kfree(rx_ring->rx_bi); 1199 rx_ring->rx_bi = NULL; 1200 1201 if (rx_ring->desc) { 1202 dma_free_coherent(rx_ring->dev, rx_ring->size, 1203 rx_ring->desc, rx_ring->dma); 1204 rx_ring->desc = NULL; 1205 } 1206 } 1207 1208 /** 1209 * i40e_setup_rx_descriptors - Allocate Rx descriptors 1210 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 1211 * 1212 * Returns 0 on success, negative on failure 1213 **/ 1214 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) 1215 { 1216 struct device *dev = rx_ring->dev; 1217 int bi_size; 1218 1219 /* warn if we are about to overwrite the pointer */ 1220 WARN_ON(rx_ring->rx_bi); 1221 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; 1222 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); 1223 if (!rx_ring->rx_bi) 1224 goto err; 1225 1226 u64_stats_init(&rx_ring->syncp); 1227 1228 /* Round up to nearest 4K */ 1229 rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc); 1230 rx_ring->size = ALIGN(rx_ring->size, 4096); 1231 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 1232 &rx_ring->dma, GFP_KERNEL); 1233 1234 if (!rx_ring->desc) { 1235 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", 1236 rx_ring->size); 1237 goto err; 1238 } 1239 1240 rx_ring->next_to_alloc = 0; 1241 rx_ring->next_to_clean = 0; 1242 rx_ring->next_to_use = 0; 1243 1244 return 0; 1245 err: 1246 kfree(rx_ring->rx_bi); 1247 rx_ring->rx_bi = NULL; 1248 return -ENOMEM; 1249 } 1250 1251 /** 1252 * i40e_release_rx_desc - Store the new tail and head values 1253 * @rx_ring: ring to bump 1254 * @val: new head index 1255 **/ 1256 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) 1257 { 1258 rx_ring->next_to_use = val; 1259 1260 /* update next to alloc since we have filled the ring */ 1261 rx_ring->next_to_alloc = val; 1262 1263 /* Force memory writes to complete before letting h/w 1264 * know there are new descriptors to fetch. (Only 1265 * applicable for weak-ordered memory model archs, 1266 * such as IA-64). 1267 */ 1268 wmb(); 1269 writel(val, rx_ring->tail); 1270 } 1271 1272 /** 1273 * i40e_rx_offset - Return expected offset into page to access data 1274 * @rx_ring: Ring we are requesting offset of 1275 * 1276 * Returns the offset value for ring into the data buffer. 1277 */ 1278 static inline unsigned int i40e_rx_offset(struct i40e_ring *rx_ring) 1279 { 1280 return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0; 1281 } 1282 1283 /** 1284 * i40e_alloc_mapped_page - recycle or make a new page 1285 * @rx_ring: ring to use 1286 * @bi: rx_buffer struct to modify 1287 * 1288 * Returns true if the page was successfully allocated or 1289 * reused. 1290 **/ 1291 static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, 1292 struct i40e_rx_buffer *bi) 1293 { 1294 struct page *page = bi->page; 1295 dma_addr_t dma; 1296 1297 /* since we are recycling buffers we should seldom need to alloc */ 1298 if (likely(page)) { 1299 rx_ring->rx_stats.page_reuse_count++; 1300 return true; 1301 } 1302 1303 /* alloc new page for storage */ 1304 page = dev_alloc_pages(i40e_rx_pg_order(rx_ring)); 1305 if (unlikely(!page)) { 1306 rx_ring->rx_stats.alloc_page_failed++; 1307 return false; 1308 } 1309 1310 /* map page for use */ 1311 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1312 i40e_rx_pg_size(rx_ring), 1313 DMA_FROM_DEVICE, 1314 I40E_RX_DMA_ATTR); 1315 1316 /* if mapping failed free memory back to system since 1317 * there isn't much point in holding memory we can't use 1318 */ 1319 if (dma_mapping_error(rx_ring->dev, dma)) { 1320 __free_pages(page, i40e_rx_pg_order(rx_ring)); 1321 rx_ring->rx_stats.alloc_page_failed++; 1322 return false; 1323 } 1324 1325 bi->dma = dma; 1326 bi->page = page; 1327 bi->page_offset = i40e_rx_offset(rx_ring); 1328 1329 /* initialize pagecnt_bias to 1 representing we fully own page */ 1330 bi->pagecnt_bias = 1; 1331 1332 return true; 1333 } 1334 1335 /** 1336 * i40e_receive_skb - Send a completed packet up the stack 1337 * @rx_ring: rx ring in play 1338 * @skb: packet to send up 1339 * @vlan_tag: vlan tag for packet 1340 **/ 1341 static void i40e_receive_skb(struct i40e_ring *rx_ring, 1342 struct sk_buff *skb, u16 vlan_tag) 1343 { 1344 struct i40e_q_vector *q_vector = rx_ring->q_vector; 1345 1346 if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1347 (vlan_tag & VLAN_VID_MASK)) 1348 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 1349 1350 napi_gro_receive(&q_vector->napi, skb); 1351 } 1352 1353 /** 1354 * i40e_alloc_rx_buffers - Replace used receive buffers 1355 * @rx_ring: ring to place buffers on 1356 * @cleaned_count: number of buffers to replace 1357 * 1358 * Returns false if all allocations were successful, true if any fail 1359 **/ 1360 bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) 1361 { 1362 u16 ntu = rx_ring->next_to_use; 1363 union i40e_rx_desc *rx_desc; 1364 struct i40e_rx_buffer *bi; 1365 1366 /* do nothing if no valid netdev defined */ 1367 if (!rx_ring->netdev || !cleaned_count) 1368 return false; 1369 1370 rx_desc = I40E_RX_DESC(rx_ring, ntu); 1371 bi = &rx_ring->rx_bi[ntu]; 1372 1373 do { 1374 if (!i40e_alloc_mapped_page(rx_ring, bi)) 1375 goto no_buffers; 1376 1377 /* sync the buffer for use by the device */ 1378 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1379 bi->page_offset, 1380 rx_ring->rx_buf_len, 1381 DMA_FROM_DEVICE); 1382 1383 /* Refresh the desc even if buffer_addrs didn't change 1384 * because each write-back erases this info. 1385 */ 1386 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1387 1388 rx_desc++; 1389 bi++; 1390 ntu++; 1391 if (unlikely(ntu == rx_ring->count)) { 1392 rx_desc = I40E_RX_DESC(rx_ring, 0); 1393 bi = rx_ring->rx_bi; 1394 ntu = 0; 1395 } 1396 1397 /* clear the status bits for the next_to_use descriptor */ 1398 rx_desc->wb.qword1.status_error_len = 0; 1399 1400 cleaned_count--; 1401 } while (cleaned_count); 1402 1403 if (rx_ring->next_to_use != ntu) 1404 i40e_release_rx_desc(rx_ring, ntu); 1405 1406 return false; 1407 1408 no_buffers: 1409 if (rx_ring->next_to_use != ntu) 1410 i40e_release_rx_desc(rx_ring, ntu); 1411 1412 /* make sure to come back via polling to try again after 1413 * allocation failure 1414 */ 1415 return true; 1416 } 1417 1418 /** 1419 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum 1420 * @vsi: the VSI we care about 1421 * @skb: skb currently being received and modified 1422 * @rx_desc: the receive descriptor 1423 **/ 1424 static inline void i40e_rx_checksum(struct i40e_vsi *vsi, 1425 struct sk_buff *skb, 1426 union i40e_rx_desc *rx_desc) 1427 { 1428 struct i40e_rx_ptype_decoded decoded; 1429 u32 rx_error, rx_status; 1430 bool ipv4, ipv6; 1431 u8 ptype; 1432 u64 qword; 1433 1434 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1435 ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT; 1436 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> 1437 I40E_RXD_QW1_ERROR_SHIFT; 1438 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1439 I40E_RXD_QW1_STATUS_SHIFT; 1440 decoded = decode_rx_desc_ptype(ptype); 1441 1442 skb->ip_summed = CHECKSUM_NONE; 1443 1444 skb_checksum_none_assert(skb); 1445 1446 /* Rx csum enabled and ip headers found? */ 1447 if (!(vsi->netdev->features & NETIF_F_RXCSUM)) 1448 return; 1449 1450 /* did the hardware decode the packet and checksum? */ 1451 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) 1452 return; 1453 1454 /* both known and outer_ip must be set for the below code to work */ 1455 if (!(decoded.known && decoded.outer_ip)) 1456 return; 1457 1458 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && 1459 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4); 1460 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && 1461 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6); 1462 1463 if (ipv4 && 1464 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | 1465 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) 1466 goto checksum_fail; 1467 1468 /* likely incorrect csum if alternate IP extension headers found */ 1469 if (ipv6 && 1470 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) 1471 /* don't increment checksum err here, non-fatal err */ 1472 return; 1473 1474 /* there was some L4 error, count error and punt packet to the stack */ 1475 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) 1476 goto checksum_fail; 1477 1478 /* handle packets that were not able to be checksummed due 1479 * to arrival speed, in this case the stack can compute 1480 * the csum. 1481 */ 1482 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) 1483 return; 1484 1485 /* If there is an outer header present that might contain a checksum 1486 * we need to bump the checksum level by 1 to reflect the fact that 1487 * we are indicating we validated the inner checksum. 1488 */ 1489 if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT) 1490 skb->csum_level = 1; 1491 1492 /* Only report checksum unnecessary for TCP, UDP, or SCTP */ 1493 switch (decoded.inner_prot) { 1494 case I40E_RX_PTYPE_INNER_PROT_TCP: 1495 case I40E_RX_PTYPE_INNER_PROT_UDP: 1496 case I40E_RX_PTYPE_INNER_PROT_SCTP: 1497 skb->ip_summed = CHECKSUM_UNNECESSARY; 1498 /* fall though */ 1499 default: 1500 break; 1501 } 1502 1503 return; 1504 1505 checksum_fail: 1506 vsi->back->hw_csum_rx_error++; 1507 } 1508 1509 /** 1510 * i40e_ptype_to_htype - get a hash type 1511 * @ptype: the ptype value from the descriptor 1512 * 1513 * Returns a hash type to be used by skb_set_hash 1514 **/ 1515 static inline int i40e_ptype_to_htype(u8 ptype) 1516 { 1517 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); 1518 1519 if (!decoded.known) 1520 return PKT_HASH_TYPE_NONE; 1521 1522 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1523 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) 1524 return PKT_HASH_TYPE_L4; 1525 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1526 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) 1527 return PKT_HASH_TYPE_L3; 1528 else 1529 return PKT_HASH_TYPE_L2; 1530 } 1531 1532 /** 1533 * i40e_rx_hash - set the hash value in the skb 1534 * @ring: descriptor ring 1535 * @rx_desc: specific descriptor 1536 **/ 1537 static inline void i40e_rx_hash(struct i40e_ring *ring, 1538 union i40e_rx_desc *rx_desc, 1539 struct sk_buff *skb, 1540 u8 rx_ptype) 1541 { 1542 u32 hash; 1543 const __le64 rss_mask = 1544 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << 1545 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); 1546 1547 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1548 return; 1549 1550 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { 1551 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); 1552 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype)); 1553 } 1554 } 1555 1556 /** 1557 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor 1558 * @rx_ring: rx descriptor ring packet is being transacted on 1559 * @rx_desc: pointer to the EOP Rx descriptor 1560 * @skb: pointer to current skb being populated 1561 * @rx_ptype: the packet type decoded by hardware 1562 * 1563 * This function checks the ring, descriptor, and packet information in 1564 * order to populate the hash, checksum, VLAN, protocol, and 1565 * other fields within the skb. 1566 **/ 1567 static inline 1568 void i40e_process_skb_fields(struct i40e_ring *rx_ring, 1569 union i40e_rx_desc *rx_desc, struct sk_buff *skb, 1570 u8 rx_ptype) 1571 { 1572 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1573 u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1574 I40E_RXD_QW1_STATUS_SHIFT; 1575 u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK; 1576 u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> 1577 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT; 1578 1579 if (unlikely(tsynvalid)) 1580 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn); 1581 1582 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); 1583 1584 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); 1585 1586 skb_record_rx_queue(skb, rx_ring->queue_index); 1587 1588 /* modifies the skb - consumes the enet header */ 1589 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1590 } 1591 1592 /** 1593 * i40e_cleanup_headers - Correct empty headers 1594 * @rx_ring: rx descriptor ring packet is being transacted on 1595 * @skb: pointer to current skb being fixed 1596 * 1597 * Also address the case where we are pulling data in on pages only 1598 * and as such no data is present in the skb header. 1599 * 1600 * In addition if skb is not at least 60 bytes we need to pad it so that 1601 * it is large enough to qualify as a valid Ethernet frame. 1602 * 1603 * Returns true if an error was encountered and skb was freed. 1604 **/ 1605 static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb) 1606 { 1607 /* if eth_skb_pad returns an error the skb was freed */ 1608 if (eth_skb_pad(skb)) 1609 return true; 1610 1611 return false; 1612 } 1613 1614 /** 1615 * i40e_reuse_rx_page - page flip buffer and store it back on the ring 1616 * @rx_ring: rx descriptor ring to store buffers on 1617 * @old_buff: donor buffer to have page reused 1618 * 1619 * Synchronizes page for reuse by the adapter 1620 **/ 1621 static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, 1622 struct i40e_rx_buffer *old_buff) 1623 { 1624 struct i40e_rx_buffer *new_buff; 1625 u16 nta = rx_ring->next_to_alloc; 1626 1627 new_buff = &rx_ring->rx_bi[nta]; 1628 1629 /* update, and store next to alloc */ 1630 nta++; 1631 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 1632 1633 /* transfer page from old buffer to new buffer */ 1634 new_buff->dma = old_buff->dma; 1635 new_buff->page = old_buff->page; 1636 new_buff->page_offset = old_buff->page_offset; 1637 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 1638 } 1639 1640 /** 1641 * i40e_page_is_reusable - check if any reuse is possible 1642 * @page: page struct to check 1643 * 1644 * A page is not reusable if it was allocated under low memory 1645 * conditions, or it's not in the same NUMA node as this CPU. 1646 */ 1647 static inline bool i40e_page_is_reusable(struct page *page) 1648 { 1649 return (page_to_nid(page) == numa_mem_id()) && 1650 !page_is_pfmemalloc(page); 1651 } 1652 1653 /** 1654 * i40e_can_reuse_rx_page - Determine if this page can be reused by 1655 * the adapter for another receive 1656 * 1657 * @rx_buffer: buffer containing the page 1658 * 1659 * If page is reusable, rx_buffer->page_offset is adjusted to point to 1660 * an unused region in the page. 1661 * 1662 * For small pages, @truesize will be a constant value, half the size 1663 * of the memory at page. We'll attempt to alternate between high and 1664 * low halves of the page, with one half ready for use by the hardware 1665 * and the other half being consumed by the stack. We use the page 1666 * ref count to determine whether the stack has finished consuming the 1667 * portion of this page that was passed up with a previous packet. If 1668 * the page ref count is >1, we'll assume the "other" half page is 1669 * still busy, and this page cannot be reused. 1670 * 1671 * For larger pages, @truesize will be the actual space used by the 1672 * received packet (adjusted upward to an even multiple of the cache 1673 * line size). This will advance through the page by the amount 1674 * actually consumed by the received packets while there is still 1675 * space for a buffer. Each region of larger pages will be used at 1676 * most once, after which the page will not be reused. 1677 * 1678 * In either case, if the page is reusable its refcount is increased. 1679 **/ 1680 static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer) 1681 { 1682 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 1683 struct page *page = rx_buffer->page; 1684 1685 /* Is any reuse possible? */ 1686 if (unlikely(!i40e_page_is_reusable(page))) 1687 return false; 1688 1689 #if (PAGE_SIZE < 8192) 1690 /* if we are only owner of page we can reuse it */ 1691 if (unlikely((page_count(page) - pagecnt_bias) > 1)) 1692 return false; 1693 #else 1694 #define I40E_LAST_OFFSET \ 1695 (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048) 1696 if (rx_buffer->page_offset > I40E_LAST_OFFSET) 1697 return false; 1698 #endif 1699 1700 /* If we have drained the page fragment pool we need to update 1701 * the pagecnt_bias and page count so that we fully restock the 1702 * number of references the driver holds. 1703 */ 1704 if (unlikely(!pagecnt_bias)) { 1705 page_ref_add(page, USHRT_MAX); 1706 rx_buffer->pagecnt_bias = USHRT_MAX; 1707 } 1708 1709 return true; 1710 } 1711 1712 /** 1713 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff 1714 * @rx_ring: rx descriptor ring to transact packets on 1715 * @rx_buffer: buffer containing page to add 1716 * @skb: sk_buff to place the data into 1717 * @size: packet length from rx_desc 1718 * 1719 * This function will add the data contained in rx_buffer->page to the skb. 1720 * It will just attach the page as a frag to the skb. 1721 * 1722 * The function will then update the page offset. 1723 **/ 1724 static void i40e_add_rx_frag(struct i40e_ring *rx_ring, 1725 struct i40e_rx_buffer *rx_buffer, 1726 struct sk_buff *skb, 1727 unsigned int size) 1728 { 1729 #if (PAGE_SIZE < 8192) 1730 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; 1731 #else 1732 unsigned int truesize = SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring)); 1733 #endif 1734 1735 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 1736 rx_buffer->page_offset, size, truesize); 1737 1738 /* page is being used so we must update the page offset */ 1739 #if (PAGE_SIZE < 8192) 1740 rx_buffer->page_offset ^= truesize; 1741 #else 1742 rx_buffer->page_offset += truesize; 1743 #endif 1744 } 1745 1746 /** 1747 * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use 1748 * @rx_ring: rx descriptor ring to transact packets on 1749 * @size: size of buffer to add to skb 1750 * 1751 * This function will pull an Rx buffer from the ring and synchronize it 1752 * for use by the CPU. 1753 */ 1754 static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring, 1755 const unsigned int size) 1756 { 1757 struct i40e_rx_buffer *rx_buffer; 1758 1759 rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean]; 1760 prefetchw(rx_buffer->page); 1761 1762 /* we are reusing so sync this buffer for CPU use */ 1763 dma_sync_single_range_for_cpu(rx_ring->dev, 1764 rx_buffer->dma, 1765 rx_buffer->page_offset, 1766 size, 1767 DMA_FROM_DEVICE); 1768 1769 /* We have pulled a buffer for use, so decrement pagecnt_bias */ 1770 rx_buffer->pagecnt_bias--; 1771 1772 return rx_buffer; 1773 } 1774 1775 /** 1776 * i40e_construct_skb - Allocate skb and populate it 1777 * @rx_ring: rx descriptor ring to transact packets on 1778 * @rx_buffer: rx buffer to pull data from 1779 * @size: size of buffer to add to skb 1780 * 1781 * This function allocates an skb. It then populates it with the page 1782 * data from the current receive descriptor, taking care to set up the 1783 * skb correctly. 1784 */ 1785 static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring, 1786 struct i40e_rx_buffer *rx_buffer, 1787 unsigned int size) 1788 { 1789 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 1790 #if (PAGE_SIZE < 8192) 1791 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; 1792 #else 1793 unsigned int truesize = SKB_DATA_ALIGN(size); 1794 #endif 1795 unsigned int headlen; 1796 struct sk_buff *skb; 1797 1798 /* prefetch first cache line of first page */ 1799 prefetch(va); 1800 #if L1_CACHE_BYTES < 128 1801 prefetch(va + L1_CACHE_BYTES); 1802 #endif 1803 1804 /* allocate a skb to store the frags */ 1805 skb = __napi_alloc_skb(&rx_ring->q_vector->napi, 1806 I40E_RX_HDR_SIZE, 1807 GFP_ATOMIC | __GFP_NOWARN); 1808 if (unlikely(!skb)) 1809 return NULL; 1810 1811 /* Determine available headroom for copy */ 1812 headlen = size; 1813 if (headlen > I40E_RX_HDR_SIZE) 1814 headlen = eth_get_headlen(va, I40E_RX_HDR_SIZE); 1815 1816 /* align pull length to size of long to optimize memcpy performance */ 1817 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); 1818 1819 /* update all of the pointers */ 1820 size -= headlen; 1821 if (size) { 1822 skb_add_rx_frag(skb, 0, rx_buffer->page, 1823 rx_buffer->page_offset + headlen, 1824 size, truesize); 1825 1826 /* buffer is used by skb, update page_offset */ 1827 #if (PAGE_SIZE < 8192) 1828 rx_buffer->page_offset ^= truesize; 1829 #else 1830 rx_buffer->page_offset += truesize; 1831 #endif 1832 } else { 1833 /* buffer is unused, reset bias back to rx_buffer */ 1834 rx_buffer->pagecnt_bias++; 1835 } 1836 1837 return skb; 1838 } 1839 1840 /** 1841 * i40e_build_skb - Build skb around an existing buffer 1842 * @rx_ring: Rx descriptor ring to transact packets on 1843 * @rx_buffer: Rx buffer to pull data from 1844 * @size: size of buffer to add to skb 1845 * 1846 * This function builds an skb around an existing Rx buffer, taking care 1847 * to set up the skb correctly and avoid any memcpy overhead. 1848 */ 1849 static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring, 1850 struct i40e_rx_buffer *rx_buffer, 1851 unsigned int size) 1852 { 1853 void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; 1854 #if (PAGE_SIZE < 8192) 1855 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2; 1856 #else 1857 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1858 SKB_DATA_ALIGN(I40E_SKB_PAD + size); 1859 #endif 1860 struct sk_buff *skb; 1861 1862 /* prefetch first cache line of first page */ 1863 prefetch(va); 1864 #if L1_CACHE_BYTES < 128 1865 prefetch(va + L1_CACHE_BYTES); 1866 #endif 1867 /* build an skb around the page buffer */ 1868 skb = build_skb(va - I40E_SKB_PAD, truesize); 1869 if (unlikely(!skb)) 1870 return NULL; 1871 1872 /* update pointers within the skb to store the data */ 1873 skb_reserve(skb, I40E_SKB_PAD); 1874 __skb_put(skb, size); 1875 1876 /* buffer is used by skb, update page_offset */ 1877 #if (PAGE_SIZE < 8192) 1878 rx_buffer->page_offset ^= truesize; 1879 #else 1880 rx_buffer->page_offset += truesize; 1881 #endif 1882 1883 return skb; 1884 } 1885 1886 /** 1887 * i40e_put_rx_buffer - Clean up used buffer and either recycle or free 1888 * @rx_ring: rx descriptor ring to transact packets on 1889 * @rx_buffer: rx buffer to pull data from 1890 * 1891 * This function will clean up the contents of the rx_buffer. It will 1892 * either recycle the bufer or unmap it and free the associated resources. 1893 */ 1894 static void i40e_put_rx_buffer(struct i40e_ring *rx_ring, 1895 struct i40e_rx_buffer *rx_buffer) 1896 { 1897 if (i40e_can_reuse_rx_page(rx_buffer)) { 1898 /* hand second half of page back to the ring */ 1899 i40e_reuse_rx_page(rx_ring, rx_buffer); 1900 rx_ring->rx_stats.page_reuse_count++; 1901 } else { 1902 /* we are not reusing the buffer so unmap it */ 1903 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 1904 i40e_rx_pg_size(rx_ring), 1905 DMA_FROM_DEVICE, I40E_RX_DMA_ATTR); 1906 __page_frag_cache_drain(rx_buffer->page, 1907 rx_buffer->pagecnt_bias); 1908 } 1909 1910 /* clear contents of buffer_info */ 1911 rx_buffer->page = NULL; 1912 } 1913 1914 /** 1915 * i40e_is_non_eop - process handling of non-EOP buffers 1916 * @rx_ring: Rx ring being processed 1917 * @rx_desc: Rx descriptor for current buffer 1918 * @skb: Current socket buffer containing buffer in progress 1919 * 1920 * This function updates next to clean. If the buffer is an EOP buffer 1921 * this function exits returning false, otherwise it will place the 1922 * sk_buff in the next buffer to be chained and return true indicating 1923 * that this is in fact a non-EOP buffer. 1924 **/ 1925 static bool i40e_is_non_eop(struct i40e_ring *rx_ring, 1926 union i40e_rx_desc *rx_desc, 1927 struct sk_buff *skb) 1928 { 1929 u32 ntc = rx_ring->next_to_clean + 1; 1930 1931 /* fetch, update, and store next to clean */ 1932 ntc = (ntc < rx_ring->count) ? ntc : 0; 1933 rx_ring->next_to_clean = ntc; 1934 1935 prefetch(I40E_RX_DESC(rx_ring, ntc)); 1936 1937 /* if we are the last buffer then there is nothing else to do */ 1938 #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) 1939 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) 1940 return false; 1941 1942 rx_ring->rx_stats.non_eop_descs++; 1943 1944 return true; 1945 } 1946 1947 /** 1948 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 1949 * @rx_ring: rx descriptor ring to transact packets on 1950 * @budget: Total limit on number of packets to process 1951 * 1952 * This function provides a "bounce buffer" approach to Rx interrupt 1953 * processing. The advantage to this is that on systems that have 1954 * expensive overhead for IOMMU access this provides a means of avoiding 1955 * it by maintaining the mapping of the page to the system. 1956 * 1957 * Returns amount of work completed 1958 **/ 1959 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) 1960 { 1961 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1962 struct sk_buff *skb = rx_ring->skb; 1963 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); 1964 bool failure = false; 1965 1966 while (likely(total_rx_packets < budget)) { 1967 struct i40e_rx_buffer *rx_buffer; 1968 union i40e_rx_desc *rx_desc; 1969 unsigned int size; 1970 u16 vlan_tag; 1971 u8 rx_ptype; 1972 u64 qword; 1973 1974 /* return some buffers to hardware, one at a time is too slow */ 1975 if (cleaned_count >= I40E_RX_BUFFER_WRITE) { 1976 failure = failure || 1977 i40e_alloc_rx_buffers(rx_ring, cleaned_count); 1978 cleaned_count = 0; 1979 } 1980 1981 rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean); 1982 1983 /* status_error_len will always be zero for unused descriptors 1984 * because it's cleared in cleanup, and overlaps with hdr_addr 1985 * which is always zero because packet split isn't used, if the 1986 * hardware wrote DD then the length will be non-zero 1987 */ 1988 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1989 1990 /* This memory barrier is needed to keep us from reading 1991 * any other fields out of the rx_desc until we have 1992 * verified the descriptor has been written back. 1993 */ 1994 dma_rmb(); 1995 1996 if (unlikely(i40e_rx_is_programming_status(qword))) { 1997 i40e_clean_programming_status(rx_ring, rx_desc, qword); 1998 continue; 1999 } 2000 size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> 2001 I40E_RXD_QW1_LENGTH_PBUF_SHIFT; 2002 if (!size) 2003 break; 2004 2005 i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb); 2006 rx_buffer = i40e_get_rx_buffer(rx_ring, size); 2007 2008 /* retrieve a buffer from the ring */ 2009 if (skb) 2010 i40e_add_rx_frag(rx_ring, rx_buffer, skb, size); 2011 else if (ring_uses_build_skb(rx_ring)) 2012 skb = i40e_build_skb(rx_ring, rx_buffer, size); 2013 else 2014 skb = i40e_construct_skb(rx_ring, rx_buffer, size); 2015 2016 /* exit if we failed to retrieve a buffer */ 2017 if (!skb) { 2018 rx_ring->rx_stats.alloc_buff_failed++; 2019 rx_buffer->pagecnt_bias++; 2020 break; 2021 } 2022 2023 i40e_put_rx_buffer(rx_ring, rx_buffer); 2024 cleaned_count++; 2025 2026 if (i40e_is_non_eop(rx_ring, rx_desc, skb)) 2027 continue; 2028 2029 /* ERR_MASK will only have valid bits if EOP set, and 2030 * what we are doing here is actually checking 2031 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in 2032 * the error field 2033 */ 2034 if (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { 2035 dev_kfree_skb_any(skb); 2036 skb = NULL; 2037 continue; 2038 } 2039 2040 if (i40e_cleanup_headers(rx_ring, skb)) { 2041 skb = NULL; 2042 continue; 2043 } 2044 2045 /* probably a little skewed due to removing CRC */ 2046 total_rx_bytes += skb->len; 2047 2048 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 2049 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> 2050 I40E_RXD_QW1_PTYPE_SHIFT; 2051 2052 /* populate checksum, VLAN, and protocol */ 2053 i40e_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype); 2054 2055 vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ? 2056 le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0; 2057 2058 i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb); 2059 i40e_receive_skb(rx_ring, skb, vlan_tag); 2060 skb = NULL; 2061 2062 /* update budget accounting */ 2063 total_rx_packets++; 2064 } 2065 2066 rx_ring->skb = skb; 2067 2068 u64_stats_update_begin(&rx_ring->syncp); 2069 rx_ring->stats.packets += total_rx_packets; 2070 rx_ring->stats.bytes += total_rx_bytes; 2071 u64_stats_update_end(&rx_ring->syncp); 2072 rx_ring->q_vector->rx.total_packets += total_rx_packets; 2073 rx_ring->q_vector->rx.total_bytes += total_rx_bytes; 2074 2075 /* guarantee a trip back through this routine if there was a failure */ 2076 return failure ? budget : total_rx_packets; 2077 } 2078 2079 static u32 i40e_buildreg_itr(const int type, const u16 itr) 2080 { 2081 u32 val; 2082 2083 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 2084 /* Don't clear PBA because that can cause lost interrupts that 2085 * came in while we were cleaning/polling 2086 */ 2087 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | 2088 (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT); 2089 2090 return val; 2091 } 2092 2093 /* a small macro to shorten up some long lines */ 2094 #define INTREG I40E_PFINT_DYN_CTLN 2095 static inline int get_rx_itr(struct i40e_vsi *vsi, int idx) 2096 { 2097 return vsi->rx_rings[idx]->rx_itr_setting; 2098 } 2099 2100 static inline int get_tx_itr(struct i40e_vsi *vsi, int idx) 2101 { 2102 return vsi->tx_rings[idx]->tx_itr_setting; 2103 } 2104 2105 /** 2106 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt 2107 * @vsi: the VSI we care about 2108 * @q_vector: q_vector for which itr is being updated and interrupt enabled 2109 * 2110 **/ 2111 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, 2112 struct i40e_q_vector *q_vector) 2113 { 2114 struct i40e_hw *hw = &vsi->back->hw; 2115 bool rx = false, tx = false; 2116 u32 rxval, txval; 2117 int vector; 2118 int idx = q_vector->v_idx; 2119 int rx_itr_setting, tx_itr_setting; 2120 2121 vector = (q_vector->v_idx + vsi->base_vector); 2122 2123 /* avoid dynamic calculation if in countdown mode OR if 2124 * all dynamic is disabled 2125 */ 2126 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0); 2127 2128 rx_itr_setting = get_rx_itr(vsi, idx); 2129 tx_itr_setting = get_tx_itr(vsi, idx); 2130 2131 if (q_vector->itr_countdown > 0 || 2132 (!ITR_IS_DYNAMIC(rx_itr_setting) && 2133 !ITR_IS_DYNAMIC(tx_itr_setting))) { 2134 goto enable_int; 2135 } 2136 2137 if (ITR_IS_DYNAMIC(tx_itr_setting)) { 2138 rx = i40e_set_new_dynamic_itr(&q_vector->rx); 2139 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr); 2140 } 2141 2142 if (ITR_IS_DYNAMIC(tx_itr_setting)) { 2143 tx = i40e_set_new_dynamic_itr(&q_vector->tx); 2144 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr); 2145 } 2146 2147 if (rx || tx) { 2148 /* get the higher of the two ITR adjustments and 2149 * use the same value for both ITR registers 2150 * when in adaptive mode (Rx and/or Tx) 2151 */ 2152 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr); 2153 2154 q_vector->tx.itr = q_vector->rx.itr = itr; 2155 txval = i40e_buildreg_itr(I40E_TX_ITR, itr); 2156 tx = true; 2157 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr); 2158 rx = true; 2159 } 2160 2161 /* only need to enable the interrupt once, but need 2162 * to possibly update both ITR values 2163 */ 2164 if (rx) { 2165 /* set the INTENA_MSK_MASK so that this first write 2166 * won't actually enable the interrupt, instead just 2167 * updating the ITR (it's bit 31 PF and VF) 2168 */ 2169 rxval |= BIT(31); 2170 /* don't check _DOWN because interrupt isn't being enabled */ 2171 wr32(hw, INTREG(vector - 1), rxval); 2172 } 2173 2174 enable_int: 2175 if (!test_bit(__I40E_VSI_DOWN, vsi->state)) 2176 wr32(hw, INTREG(vector - 1), txval); 2177 2178 if (q_vector->itr_countdown) 2179 q_vector->itr_countdown--; 2180 else 2181 q_vector->itr_countdown = ITR_COUNTDOWN_START; 2182 } 2183 2184 /** 2185 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine 2186 * @napi: napi struct with our devices info in it 2187 * @budget: amount of work driver is allowed to do this pass, in packets 2188 * 2189 * This function will clean all queues associated with a q_vector. 2190 * 2191 * Returns the amount of work done 2192 **/ 2193 int i40e_napi_poll(struct napi_struct *napi, int budget) 2194 { 2195 struct i40e_q_vector *q_vector = 2196 container_of(napi, struct i40e_q_vector, napi); 2197 struct i40e_vsi *vsi = q_vector->vsi; 2198 struct i40e_ring *ring; 2199 bool clean_complete = true; 2200 bool arm_wb = false; 2201 int budget_per_ring; 2202 int work_done = 0; 2203 2204 if (test_bit(__I40E_VSI_DOWN, vsi->state)) { 2205 napi_complete(napi); 2206 return 0; 2207 } 2208 2209 /* Since the actual Tx work is minimal, we can give the Tx a larger 2210 * budget and be more aggressive about cleaning up the Tx descriptors. 2211 */ 2212 i40e_for_each_ring(ring, q_vector->tx) { 2213 if (!i40e_clean_tx_irq(vsi, ring, budget)) { 2214 clean_complete = false; 2215 continue; 2216 } 2217 arm_wb |= ring->arm_wb; 2218 ring->arm_wb = false; 2219 } 2220 2221 /* Handle case where we are called by netpoll with a budget of 0 */ 2222 if (budget <= 0) 2223 goto tx_only; 2224 2225 /* We attempt to distribute budget to each Rx queue fairly, but don't 2226 * allow the budget to go below 1 because that would exit polling early. 2227 */ 2228 budget_per_ring = max(budget/q_vector->num_ringpairs, 1); 2229 2230 i40e_for_each_ring(ring, q_vector->rx) { 2231 int cleaned = i40e_clean_rx_irq(ring, budget_per_ring); 2232 2233 work_done += cleaned; 2234 /* if we clean as many as budgeted, we must not be done */ 2235 if (cleaned >= budget_per_ring) 2236 clean_complete = false; 2237 } 2238 2239 /* If work not completed, return budget and polling will return */ 2240 if (!clean_complete) { 2241 const cpumask_t *aff_mask = &q_vector->affinity_mask; 2242 int cpu_id = smp_processor_id(); 2243 2244 /* It is possible that the interrupt affinity has changed but, 2245 * if the cpu is pegged at 100%, polling will never exit while 2246 * traffic continues and the interrupt will be stuck on this 2247 * cpu. We check to make sure affinity is correct before we 2248 * continue to poll, otherwise we must stop polling so the 2249 * interrupt can move to the correct cpu. 2250 */ 2251 if (likely(cpumask_test_cpu(cpu_id, aff_mask) || 2252 !(vsi->back->flags & I40E_FLAG_MSIX_ENABLED))) { 2253 tx_only: 2254 if (arm_wb) { 2255 q_vector->tx.ring[0].tx_stats.tx_force_wb++; 2256 i40e_enable_wb_on_itr(vsi, q_vector); 2257 } 2258 return budget; 2259 } 2260 } 2261 2262 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) 2263 q_vector->arm_wb_state = false; 2264 2265 /* Work is done so exit the polling mode and re-enable the interrupt */ 2266 napi_complete_done(napi, work_done); 2267 2268 /* If we're prematurely stopping polling to fix the interrupt 2269 * affinity we want to make sure polling starts back up so we 2270 * issue a call to i40e_force_wb which triggers a SW interrupt. 2271 */ 2272 if (!clean_complete) 2273 i40e_force_wb(vsi, q_vector); 2274 else if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) 2275 i40e_irq_dynamic_enable_icr0(vsi->back, false); 2276 else 2277 i40e_update_enable_itr(vsi, q_vector); 2278 2279 return min(work_done, budget - 1); 2280 } 2281 2282 /** 2283 * i40e_atr - Add a Flow Director ATR filter 2284 * @tx_ring: ring to add programming descriptor to 2285 * @skb: send buffer 2286 * @tx_flags: send tx flags 2287 **/ 2288 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, 2289 u32 tx_flags) 2290 { 2291 struct i40e_filter_program_desc *fdir_desc; 2292 struct i40e_pf *pf = tx_ring->vsi->back; 2293 union { 2294 unsigned char *network; 2295 struct iphdr *ipv4; 2296 struct ipv6hdr *ipv6; 2297 } hdr; 2298 struct tcphdr *th; 2299 unsigned int hlen; 2300 u32 flex_ptype, dtype_cmd; 2301 int l4_proto; 2302 u16 i; 2303 2304 /* make sure ATR is enabled */ 2305 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED)) 2306 return; 2307 2308 if (pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED) 2309 return; 2310 2311 /* if sampling is disabled do nothing */ 2312 if (!tx_ring->atr_sample_rate) 2313 return; 2314 2315 /* Currently only IPv4/IPv6 with TCP is supported */ 2316 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6))) 2317 return; 2318 2319 /* snag network header to get L4 type and address */ 2320 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ? 2321 skb_inner_network_header(skb) : skb_network_header(skb); 2322 2323 /* Note: tx_flags gets modified to reflect inner protocols in 2324 * tx_enable_csum function if encap is enabled. 2325 */ 2326 if (tx_flags & I40E_TX_FLAGS_IPV4) { 2327 /* access ihl as u8 to avoid unaligned access on ia64 */ 2328 hlen = (hdr.network[0] & 0x0F) << 2; 2329 l4_proto = hdr.ipv4->protocol; 2330 } else { 2331 hlen = hdr.network - skb->data; 2332 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 2333 hlen -= hdr.network - skb->data; 2334 } 2335 2336 if (l4_proto != IPPROTO_TCP) 2337 return; 2338 2339 th = (struct tcphdr *)(hdr.network + hlen); 2340 2341 /* Due to lack of space, no more new filters can be programmed */ 2342 if (th->syn && (pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED)) 2343 return; 2344 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) { 2345 /* HW ATR eviction will take care of removing filters on FIN 2346 * and RST packets. 2347 */ 2348 if (th->fin || th->rst) 2349 return; 2350 } 2351 2352 tx_ring->atr_count++; 2353 2354 /* sample on all syn/fin/rst packets or once every atr sample rate */ 2355 if (!th->fin && 2356 !th->syn && 2357 !th->rst && 2358 (tx_ring->atr_count < tx_ring->atr_sample_rate)) 2359 return; 2360 2361 tx_ring->atr_count = 0; 2362 2363 /* grab the next descriptor */ 2364 i = tx_ring->next_to_use; 2365 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 2366 2367 i++; 2368 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2369 2370 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 2371 I40E_TXD_FLTR_QW0_QINDEX_MASK; 2372 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ? 2373 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << 2374 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : 2375 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << 2376 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 2377 2378 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 2379 2380 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 2381 2382 dtype_cmd |= (th->fin || th->rst) ? 2383 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 2384 I40E_TXD_FLTR_QW1_PCMD_SHIFT) : 2385 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 2386 I40E_TXD_FLTR_QW1_PCMD_SHIFT); 2387 2388 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << 2389 I40E_TXD_FLTR_QW1_DEST_SHIFT; 2390 2391 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << 2392 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; 2393 2394 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 2395 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL)) 2396 dtype_cmd |= 2397 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) << 2398 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 2399 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 2400 else 2401 dtype_cmd |= 2402 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) << 2403 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 2404 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 2405 2406 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) 2407 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK; 2408 2409 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); 2410 fdir_desc->rsvd = cpu_to_le32(0); 2411 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); 2412 fdir_desc->fd_id = cpu_to_le32(0); 2413 } 2414 2415 /** 2416 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW 2417 * @skb: send buffer 2418 * @tx_ring: ring to send buffer on 2419 * @flags: the tx flags to be set 2420 * 2421 * Checks the skb and set up correspondingly several generic transmit flags 2422 * related to VLAN tagging for the HW, such as VLAN, DCB, etc. 2423 * 2424 * Returns error code indicate the frame should be dropped upon error and the 2425 * otherwise returns 0 to indicate the flags has been set properly. 2426 **/ 2427 static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 2428 struct i40e_ring *tx_ring, 2429 u32 *flags) 2430 { 2431 __be16 protocol = skb->protocol; 2432 u32 tx_flags = 0; 2433 2434 if (protocol == htons(ETH_P_8021Q) && 2435 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 2436 /* When HW VLAN acceleration is turned off by the user the 2437 * stack sets the protocol to 8021q so that the driver 2438 * can take any steps required to support the SW only 2439 * VLAN handling. In our case the driver doesn't need 2440 * to take any further steps so just set the protocol 2441 * to the encapsulated ethertype. 2442 */ 2443 skb->protocol = vlan_get_protocol(skb); 2444 goto out; 2445 } 2446 2447 /* if we have a HW VLAN tag being added, default to the HW one */ 2448 if (skb_vlan_tag_present(skb)) { 2449 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; 2450 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 2451 /* else if it is a SW VLAN, check the next protocol and store the tag */ 2452 } else if (protocol == htons(ETH_P_8021Q)) { 2453 struct vlan_hdr *vhdr, _vhdr; 2454 2455 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 2456 if (!vhdr) 2457 return -EINVAL; 2458 2459 protocol = vhdr->h_vlan_encapsulated_proto; 2460 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; 2461 tx_flags |= I40E_TX_FLAGS_SW_VLAN; 2462 } 2463 2464 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED)) 2465 goto out; 2466 2467 /* Insert 802.1p priority into VLAN header */ 2468 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || 2469 (skb->priority != TC_PRIO_CONTROL)) { 2470 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; 2471 tx_flags |= (skb->priority & 0x7) << 2472 I40E_TX_FLAGS_VLAN_PRIO_SHIFT; 2473 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { 2474 struct vlan_ethhdr *vhdr; 2475 int rc; 2476 2477 rc = skb_cow_head(skb, 0); 2478 if (rc < 0) 2479 return rc; 2480 vhdr = (struct vlan_ethhdr *)skb->data; 2481 vhdr->h_vlan_TCI = htons(tx_flags >> 2482 I40E_TX_FLAGS_VLAN_SHIFT); 2483 } else { 2484 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 2485 } 2486 } 2487 2488 out: 2489 *flags = tx_flags; 2490 return 0; 2491 } 2492 2493 /** 2494 * i40e_tso - set up the tso context descriptor 2495 * @first: pointer to first Tx buffer for xmit 2496 * @hdr_len: ptr to the size of the packet header 2497 * @cd_type_cmd_tso_mss: Quad Word 1 2498 * 2499 * Returns 0 if no TSO can happen, 1 if tso is going, or error 2500 **/ 2501 static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len, 2502 u64 *cd_type_cmd_tso_mss) 2503 { 2504 struct sk_buff *skb = first->skb; 2505 u64 cd_cmd, cd_tso_len, cd_mss; 2506 union { 2507 struct iphdr *v4; 2508 struct ipv6hdr *v6; 2509 unsigned char *hdr; 2510 } ip; 2511 union { 2512 struct tcphdr *tcp; 2513 struct udphdr *udp; 2514 unsigned char *hdr; 2515 } l4; 2516 u32 paylen, l4_offset; 2517 u16 gso_segs, gso_size; 2518 int err; 2519 2520 if (skb->ip_summed != CHECKSUM_PARTIAL) 2521 return 0; 2522 2523 if (!skb_is_gso(skb)) 2524 return 0; 2525 2526 err = skb_cow_head(skb, 0); 2527 if (err < 0) 2528 return err; 2529 2530 ip.hdr = skb_network_header(skb); 2531 l4.hdr = skb_transport_header(skb); 2532 2533 /* initialize outer IP header fields */ 2534 if (ip.v4->version == 4) { 2535 ip.v4->tot_len = 0; 2536 ip.v4->check = 0; 2537 } else { 2538 ip.v6->payload_len = 0; 2539 } 2540 2541 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 2542 SKB_GSO_GRE_CSUM | 2543 SKB_GSO_IPXIP4 | 2544 SKB_GSO_IPXIP6 | 2545 SKB_GSO_UDP_TUNNEL | 2546 SKB_GSO_UDP_TUNNEL_CSUM)) { 2547 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 2548 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { 2549 l4.udp->len = 0; 2550 2551 /* determine offset of outer transport header */ 2552 l4_offset = l4.hdr - skb->data; 2553 2554 /* remove payload length from outer checksum */ 2555 paylen = skb->len - l4_offset; 2556 csum_replace_by_diff(&l4.udp->check, 2557 (__force __wsum)htonl(paylen)); 2558 } 2559 2560 /* reset pointers to inner headers */ 2561 ip.hdr = skb_inner_network_header(skb); 2562 l4.hdr = skb_inner_transport_header(skb); 2563 2564 /* initialize inner IP header fields */ 2565 if (ip.v4->version == 4) { 2566 ip.v4->tot_len = 0; 2567 ip.v4->check = 0; 2568 } else { 2569 ip.v6->payload_len = 0; 2570 } 2571 } 2572 2573 /* determine offset of inner transport header */ 2574 l4_offset = l4.hdr - skb->data; 2575 2576 /* remove payload length from inner checksum */ 2577 paylen = skb->len - l4_offset; 2578 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); 2579 2580 /* compute length of segmentation header */ 2581 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 2582 2583 /* pull values out of skb_shinfo */ 2584 gso_size = skb_shinfo(skb)->gso_size; 2585 gso_segs = skb_shinfo(skb)->gso_segs; 2586 2587 /* update GSO size and bytecount with header size */ 2588 first->gso_segs = gso_segs; 2589 first->bytecount += (first->gso_segs - 1) * *hdr_len; 2590 2591 /* find the field values */ 2592 cd_cmd = I40E_TX_CTX_DESC_TSO; 2593 cd_tso_len = skb->len - *hdr_len; 2594 cd_mss = gso_size; 2595 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | 2596 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | 2597 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); 2598 return 1; 2599 } 2600 2601 /** 2602 * i40e_tsyn - set up the tsyn context descriptor 2603 * @tx_ring: ptr to the ring to send 2604 * @skb: ptr to the skb we're sending 2605 * @tx_flags: the collected send information 2606 * @cd_type_cmd_tso_mss: Quad Word 1 2607 * 2608 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen 2609 **/ 2610 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, 2611 u32 tx_flags, u64 *cd_type_cmd_tso_mss) 2612 { 2613 struct i40e_pf *pf; 2614 2615 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) 2616 return 0; 2617 2618 /* Tx timestamps cannot be sampled when doing TSO */ 2619 if (tx_flags & I40E_TX_FLAGS_TSO) 2620 return 0; 2621 2622 /* only timestamp the outbound packet if the user has requested it and 2623 * we are not already transmitting a packet to be timestamped 2624 */ 2625 pf = i40e_netdev_to_pf(tx_ring->netdev); 2626 if (!(pf->flags & I40E_FLAG_PTP)) 2627 return 0; 2628 2629 if (pf->ptp_tx && 2630 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) { 2631 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2632 pf->ptp_tx_skb = skb_get(skb); 2633 } else { 2634 return 0; 2635 } 2636 2637 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << 2638 I40E_TXD_CTX_QW1_CMD_SHIFT; 2639 2640 return 1; 2641 } 2642 2643 /** 2644 * i40e_tx_enable_csum - Enable Tx checksum offloads 2645 * @skb: send buffer 2646 * @tx_flags: pointer to Tx flags currently set 2647 * @td_cmd: Tx descriptor command bits to set 2648 * @td_offset: Tx descriptor header offsets to set 2649 * @tx_ring: Tx descriptor ring 2650 * @cd_tunneling: ptr to context desc bits 2651 **/ 2652 static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, 2653 u32 *td_cmd, u32 *td_offset, 2654 struct i40e_ring *tx_ring, 2655 u32 *cd_tunneling) 2656 { 2657 union { 2658 struct iphdr *v4; 2659 struct ipv6hdr *v6; 2660 unsigned char *hdr; 2661 } ip; 2662 union { 2663 struct tcphdr *tcp; 2664 struct udphdr *udp; 2665 unsigned char *hdr; 2666 } l4; 2667 unsigned char *exthdr; 2668 u32 offset, cmd = 0; 2669 __be16 frag_off; 2670 u8 l4_proto = 0; 2671 2672 if (skb->ip_summed != CHECKSUM_PARTIAL) 2673 return 0; 2674 2675 ip.hdr = skb_network_header(skb); 2676 l4.hdr = skb_transport_header(skb); 2677 2678 /* compute outer L2 header size */ 2679 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; 2680 2681 if (skb->encapsulation) { 2682 u32 tunnel = 0; 2683 /* define outer network header type */ 2684 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 2685 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? 2686 I40E_TX_CTX_EXT_IP_IPV4 : 2687 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; 2688 2689 l4_proto = ip.v4->protocol; 2690 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 2691 tunnel |= I40E_TX_CTX_EXT_IP_IPV6; 2692 2693 exthdr = ip.hdr + sizeof(*ip.v6); 2694 l4_proto = ip.v6->nexthdr; 2695 if (l4.hdr != exthdr) 2696 ipv6_skip_exthdr(skb, exthdr - skb->data, 2697 &l4_proto, &frag_off); 2698 } 2699 2700 /* define outer transport */ 2701 switch (l4_proto) { 2702 case IPPROTO_UDP: 2703 tunnel |= I40E_TXD_CTX_UDP_TUNNELING; 2704 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 2705 break; 2706 case IPPROTO_GRE: 2707 tunnel |= I40E_TXD_CTX_GRE_TUNNELING; 2708 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 2709 break; 2710 case IPPROTO_IPIP: 2711 case IPPROTO_IPV6: 2712 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL; 2713 l4.hdr = skb_inner_network_header(skb); 2714 break; 2715 default: 2716 if (*tx_flags & I40E_TX_FLAGS_TSO) 2717 return -1; 2718 2719 skb_checksum_help(skb); 2720 return 0; 2721 } 2722 2723 /* compute outer L3 header size */ 2724 tunnel |= ((l4.hdr - ip.hdr) / 4) << 2725 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; 2726 2727 /* switch IP header pointer from outer to inner header */ 2728 ip.hdr = skb_inner_network_header(skb); 2729 2730 /* compute tunnel header size */ 2731 tunnel |= ((ip.hdr - l4.hdr) / 2) << 2732 I40E_TXD_CTX_QW0_NATLEN_SHIFT; 2733 2734 /* indicate if we need to offload outer UDP header */ 2735 if ((*tx_flags & I40E_TX_FLAGS_TSO) && 2736 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 2737 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) 2738 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; 2739 2740 /* record tunnel offload values */ 2741 *cd_tunneling |= tunnel; 2742 2743 /* switch L4 header pointer from outer to inner */ 2744 l4.hdr = skb_inner_transport_header(skb); 2745 l4_proto = 0; 2746 2747 /* reset type as we transition from outer to inner headers */ 2748 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); 2749 if (ip.v4->version == 4) 2750 *tx_flags |= I40E_TX_FLAGS_IPV4; 2751 if (ip.v6->version == 6) 2752 *tx_flags |= I40E_TX_FLAGS_IPV6; 2753 } 2754 2755 /* Enable IP checksum offloads */ 2756 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 2757 l4_proto = ip.v4->protocol; 2758 /* the stack computes the IP header already, the only time we 2759 * need the hardware to recompute it is in the case of TSO. 2760 */ 2761 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? 2762 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : 2763 I40E_TX_DESC_CMD_IIPT_IPV4; 2764 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 2765 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; 2766 2767 exthdr = ip.hdr + sizeof(*ip.v6); 2768 l4_proto = ip.v6->nexthdr; 2769 if (l4.hdr != exthdr) 2770 ipv6_skip_exthdr(skb, exthdr - skb->data, 2771 &l4_proto, &frag_off); 2772 } 2773 2774 /* compute inner L3 header size */ 2775 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; 2776 2777 /* Enable L4 checksum offloads */ 2778 switch (l4_proto) { 2779 case IPPROTO_TCP: 2780 /* enable checksum offloads */ 2781 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; 2782 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2783 break; 2784 case IPPROTO_SCTP: 2785 /* enable SCTP checksum offload */ 2786 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; 2787 offset |= (sizeof(struct sctphdr) >> 2) << 2788 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2789 break; 2790 case IPPROTO_UDP: 2791 /* enable UDP checksum offload */ 2792 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; 2793 offset |= (sizeof(struct udphdr) >> 2) << 2794 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2795 break; 2796 default: 2797 if (*tx_flags & I40E_TX_FLAGS_TSO) 2798 return -1; 2799 skb_checksum_help(skb); 2800 return 0; 2801 } 2802 2803 *td_cmd |= cmd; 2804 *td_offset |= offset; 2805 2806 return 1; 2807 } 2808 2809 /** 2810 * i40e_create_tx_ctx Build the Tx context descriptor 2811 * @tx_ring: ring to create the descriptor on 2812 * @cd_type_cmd_tso_mss: Quad Word 1 2813 * @cd_tunneling: Quad Word 0 - bits 0-31 2814 * @cd_l2tag2: Quad Word 0 - bits 32-63 2815 **/ 2816 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, 2817 const u64 cd_type_cmd_tso_mss, 2818 const u32 cd_tunneling, const u32 cd_l2tag2) 2819 { 2820 struct i40e_tx_context_desc *context_desc; 2821 int i = tx_ring->next_to_use; 2822 2823 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && 2824 !cd_tunneling && !cd_l2tag2) 2825 return; 2826 2827 /* grab the next descriptor */ 2828 context_desc = I40E_TX_CTXTDESC(tx_ring, i); 2829 2830 i++; 2831 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2832 2833 /* cpu_to_le32 and assign to struct fields */ 2834 context_desc->tunneling_params = cpu_to_le32(cd_tunneling); 2835 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); 2836 context_desc->rsvd = cpu_to_le16(0); 2837 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); 2838 } 2839 2840 /** 2841 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions 2842 * @tx_ring: the ring to be checked 2843 * @size: the size buffer we want to assure is available 2844 * 2845 * Returns -EBUSY if a stop is needed, else 0 2846 **/ 2847 int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 2848 { 2849 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 2850 /* Memory barrier before checking head and tail */ 2851 smp_mb(); 2852 2853 /* Check again in a case another CPU has just made room available. */ 2854 if (likely(I40E_DESC_UNUSED(tx_ring) < size)) 2855 return -EBUSY; 2856 2857 /* A reprieve! - use start_queue because it doesn't call schedule */ 2858 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 2859 ++tx_ring->tx_stats.restart_queue; 2860 return 0; 2861 } 2862 2863 /** 2864 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet 2865 * @skb: send buffer 2866 * 2867 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire 2868 * and so we need to figure out the cases where we need to linearize the skb. 2869 * 2870 * For TSO we need to count the TSO header and segment payload separately. 2871 * As such we need to check cases where we have 7 fragments or more as we 2872 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for 2873 * the segment payload in the first descriptor, and another 7 for the 2874 * fragments. 2875 **/ 2876 bool __i40e_chk_linearize(struct sk_buff *skb) 2877 { 2878 const struct skb_frag_struct *frag, *stale; 2879 int nr_frags, sum; 2880 2881 /* no need to check if number of frags is less than 7 */ 2882 nr_frags = skb_shinfo(skb)->nr_frags; 2883 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) 2884 return false; 2885 2886 /* We need to walk through the list and validate that each group 2887 * of 6 fragments totals at least gso_size. 2888 */ 2889 nr_frags -= I40E_MAX_BUFFER_TXD - 2; 2890 frag = &skb_shinfo(skb)->frags[0]; 2891 2892 /* Initialize size to the negative value of gso_size minus 1. We 2893 * use this as the worst case scenerio in which the frag ahead 2894 * of us only provides one byte which is why we are limited to 6 2895 * descriptors for a single transmit as the header and previous 2896 * fragment are already consuming 2 descriptors. 2897 */ 2898 sum = 1 - skb_shinfo(skb)->gso_size; 2899 2900 /* Add size of frags 0 through 4 to create our initial sum */ 2901 sum += skb_frag_size(frag++); 2902 sum += skb_frag_size(frag++); 2903 sum += skb_frag_size(frag++); 2904 sum += skb_frag_size(frag++); 2905 sum += skb_frag_size(frag++); 2906 2907 /* Walk through fragments adding latest fragment, testing it, and 2908 * then removing stale fragments from the sum. 2909 */ 2910 stale = &skb_shinfo(skb)->frags[0]; 2911 for (;;) { 2912 sum += skb_frag_size(frag++); 2913 2914 /* if sum is negative we failed to make sufficient progress */ 2915 if (sum < 0) 2916 return true; 2917 2918 if (!nr_frags--) 2919 break; 2920 2921 sum -= skb_frag_size(stale++); 2922 } 2923 2924 return false; 2925 } 2926 2927 /** 2928 * i40e_tx_map - Build the Tx descriptor 2929 * @tx_ring: ring to send buffer on 2930 * @skb: send buffer 2931 * @first: first buffer info buffer to use 2932 * @tx_flags: collected send information 2933 * @hdr_len: size of the packet header 2934 * @td_cmd: the command field in the descriptor 2935 * @td_offset: offset for checksum or crc 2936 **/ 2937 static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 2938 struct i40e_tx_buffer *first, u32 tx_flags, 2939 const u8 hdr_len, u32 td_cmd, u32 td_offset) 2940 { 2941 unsigned int data_len = skb->data_len; 2942 unsigned int size = skb_headlen(skb); 2943 struct skb_frag_struct *frag; 2944 struct i40e_tx_buffer *tx_bi; 2945 struct i40e_tx_desc *tx_desc; 2946 u16 i = tx_ring->next_to_use; 2947 u32 td_tag = 0; 2948 dma_addr_t dma; 2949 u16 desc_count = 1; 2950 2951 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { 2952 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; 2953 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> 2954 I40E_TX_FLAGS_VLAN_SHIFT; 2955 } 2956 2957 first->tx_flags = tx_flags; 2958 2959 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 2960 2961 tx_desc = I40E_TX_DESC(tx_ring, i); 2962 tx_bi = first; 2963 2964 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 2965 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; 2966 2967 if (dma_mapping_error(tx_ring->dev, dma)) 2968 goto dma_error; 2969 2970 /* record length, and DMA address */ 2971 dma_unmap_len_set(tx_bi, len, size); 2972 dma_unmap_addr_set(tx_bi, dma, dma); 2973 2974 /* align size to end of page */ 2975 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); 2976 tx_desc->buffer_addr = cpu_to_le64(dma); 2977 2978 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { 2979 tx_desc->cmd_type_offset_bsz = 2980 build_ctob(td_cmd, td_offset, 2981 max_data, td_tag); 2982 2983 tx_desc++; 2984 i++; 2985 desc_count++; 2986 2987 if (i == tx_ring->count) { 2988 tx_desc = I40E_TX_DESC(tx_ring, 0); 2989 i = 0; 2990 } 2991 2992 dma += max_data; 2993 size -= max_data; 2994 2995 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; 2996 tx_desc->buffer_addr = cpu_to_le64(dma); 2997 } 2998 2999 if (likely(!data_len)) 3000 break; 3001 3002 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, 3003 size, td_tag); 3004 3005 tx_desc++; 3006 i++; 3007 desc_count++; 3008 3009 if (i == tx_ring->count) { 3010 tx_desc = I40E_TX_DESC(tx_ring, 0); 3011 i = 0; 3012 } 3013 3014 size = skb_frag_size(frag); 3015 data_len -= size; 3016 3017 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 3018 DMA_TO_DEVICE); 3019 3020 tx_bi = &tx_ring->tx_bi[i]; 3021 } 3022 3023 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 3024 3025 i++; 3026 if (i == tx_ring->count) 3027 i = 0; 3028 3029 tx_ring->next_to_use = i; 3030 3031 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); 3032 3033 /* write last descriptor with EOP bit */ 3034 td_cmd |= I40E_TX_DESC_CMD_EOP; 3035 3036 /* We can OR these values together as they both are checked against 3037 * 4 below and at this point desc_count will be used as a boolean value 3038 * after this if/else block. 3039 */ 3040 desc_count |= ++tx_ring->packet_stride; 3041 3042 /* Algorithm to optimize tail and RS bit setting: 3043 * if queue is stopped 3044 * mark RS bit 3045 * reset packet counter 3046 * else if xmit_more is supported and is true 3047 * advance packet counter to 4 3048 * reset desc_count to 0 3049 * 3050 * if desc_count >= 4 3051 * mark RS bit 3052 * reset packet counter 3053 * if desc_count > 0 3054 * update tail 3055 * 3056 * Note: If there are less than 4 descriptors 3057 * pending and interrupts were disabled the service task will 3058 * trigger a force WB. 3059 */ 3060 if (netif_xmit_stopped(txring_txq(tx_ring))) { 3061 goto do_rs; 3062 } else if (skb->xmit_more) { 3063 /* set stride to arm on next packet and reset desc_count */ 3064 tx_ring->packet_stride = WB_STRIDE; 3065 desc_count = 0; 3066 } else if (desc_count >= WB_STRIDE) { 3067 do_rs: 3068 /* write last descriptor with RS bit set */ 3069 td_cmd |= I40E_TX_DESC_CMD_RS; 3070 tx_ring->packet_stride = 0; 3071 } 3072 3073 tx_desc->cmd_type_offset_bsz = 3074 build_ctob(td_cmd, td_offset, size, td_tag); 3075 3076 /* Force memory writes to complete before letting h/w know there 3077 * are new descriptors to fetch. 3078 * 3079 * We also use this memory barrier to make certain all of the 3080 * status bits have been updated before next_to_watch is written. 3081 */ 3082 wmb(); 3083 3084 /* set next_to_watch value indicating a packet is present */ 3085 first->next_to_watch = tx_desc; 3086 3087 /* notify HW of packet */ 3088 if (desc_count) { 3089 writel(i, tx_ring->tail); 3090 3091 /* we need this if more than one processor can write to our tail 3092 * at a time, it synchronizes IO on IA64/Altix systems 3093 */ 3094 mmiowb(); 3095 } 3096 3097 return; 3098 3099 dma_error: 3100 dev_info(tx_ring->dev, "TX DMA map failed\n"); 3101 3102 /* clear dma mappings for failed tx_bi map */ 3103 for (;;) { 3104 tx_bi = &tx_ring->tx_bi[i]; 3105 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); 3106 if (tx_bi == first) 3107 break; 3108 if (i == 0) 3109 i = tx_ring->count; 3110 i--; 3111 } 3112 3113 tx_ring->next_to_use = i; 3114 } 3115 3116 /** 3117 * i40e_xmit_frame_ring - Sends buffer on Tx ring 3118 * @skb: send buffer 3119 * @tx_ring: ring to send buffer on 3120 * 3121 * Returns NETDEV_TX_OK if sent, else an error code 3122 **/ 3123 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, 3124 struct i40e_ring *tx_ring) 3125 { 3126 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; 3127 u32 cd_tunneling = 0, cd_l2tag2 = 0; 3128 struct i40e_tx_buffer *first; 3129 u32 td_offset = 0; 3130 u32 tx_flags = 0; 3131 __be16 protocol; 3132 u32 td_cmd = 0; 3133 u8 hdr_len = 0; 3134 int tso, count; 3135 int tsyn; 3136 3137 /* prefetch the data, we'll need it later */ 3138 prefetch(skb->data); 3139 3140 i40e_trace(xmit_frame_ring, skb, tx_ring); 3141 3142 count = i40e_xmit_descriptor_count(skb); 3143 if (i40e_chk_linearize(skb, count)) { 3144 if (__skb_linearize(skb)) { 3145 dev_kfree_skb_any(skb); 3146 return NETDEV_TX_OK; 3147 } 3148 count = i40e_txd_use_count(skb->len); 3149 tx_ring->tx_stats.tx_linearize++; 3150 } 3151 3152 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, 3153 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, 3154 * + 4 desc gap to avoid the cache line where head is, 3155 * + 1 desc for context descriptor, 3156 * otherwise try next time 3157 */ 3158 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { 3159 tx_ring->tx_stats.tx_busy++; 3160 return NETDEV_TX_BUSY; 3161 } 3162 3163 /* record the location of the first descriptor for this packet */ 3164 first = &tx_ring->tx_bi[tx_ring->next_to_use]; 3165 first->skb = skb; 3166 first->bytecount = skb->len; 3167 first->gso_segs = 1; 3168 3169 /* prepare the xmit flags */ 3170 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) 3171 goto out_drop; 3172 3173 /* obtain protocol of skb */ 3174 protocol = vlan_get_protocol(skb); 3175 3176 /* setup IPv4/IPv6 offloads */ 3177 if (protocol == htons(ETH_P_IP)) 3178 tx_flags |= I40E_TX_FLAGS_IPV4; 3179 else if (protocol == htons(ETH_P_IPV6)) 3180 tx_flags |= I40E_TX_FLAGS_IPV6; 3181 3182 tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss); 3183 3184 if (tso < 0) 3185 goto out_drop; 3186 else if (tso) 3187 tx_flags |= I40E_TX_FLAGS_TSO; 3188 3189 /* Always offload the checksum, since it's in the data descriptor */ 3190 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, 3191 tx_ring, &cd_tunneling); 3192 if (tso < 0) 3193 goto out_drop; 3194 3195 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); 3196 3197 if (tsyn) 3198 tx_flags |= I40E_TX_FLAGS_TSYN; 3199 3200 skb_tx_timestamp(skb); 3201 3202 /* always enable CRC insertion offload */ 3203 td_cmd |= I40E_TX_DESC_CMD_ICRC; 3204 3205 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, 3206 cd_tunneling, cd_l2tag2); 3207 3208 /* Add Flow Director ATR if it's enabled. 3209 * 3210 * NOTE: this must always be directly before the data descriptor. 3211 */ 3212 i40e_atr(tx_ring, skb, tx_flags); 3213 3214 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, 3215 td_cmd, td_offset); 3216 3217 return NETDEV_TX_OK; 3218 3219 out_drop: 3220 i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring); 3221 dev_kfree_skb_any(first->skb); 3222 first->skb = NULL; 3223 return NETDEV_TX_OK; 3224 } 3225 3226 /** 3227 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer 3228 * @skb: send buffer 3229 * @netdev: network interface device structure 3230 * 3231 * Returns NETDEV_TX_OK if sent, else an error code 3232 **/ 3233 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 3234 { 3235 struct i40e_netdev_priv *np = netdev_priv(netdev); 3236 struct i40e_vsi *vsi = np->vsi; 3237 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; 3238 3239 /* hardware can't handle really short frames, hardware padding works 3240 * beyond this point 3241 */ 3242 if (skb_put_padto(skb, I40E_MIN_TX_LEN)) 3243 return NETDEV_TX_OK; 3244 3245 return i40e_xmit_frame_ring(skb, tx_ring); 3246 } 3247