1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include <linux/prefetch.h> 28 #include "i40e.h" 29 #include "i40e_prototype.h" 30 31 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, 32 u32 td_tag) 33 { 34 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | 35 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | 36 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | 37 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | 38 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); 39 } 40 41 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) 42 #define I40E_FD_CLEAN_DELAY 10 43 /** 44 * i40e_program_fdir_filter - Program a Flow Director filter 45 * @fdir_data: Packet data that will be filter parameters 46 * @raw_packet: the pre-allocated packet buffer for FDir 47 * @pf: The pf pointer 48 * @add: True for add/update, False for remove 49 **/ 50 int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet, 51 struct i40e_pf *pf, bool add) 52 { 53 struct i40e_filter_program_desc *fdir_desc; 54 struct i40e_tx_buffer *tx_buf, *first; 55 struct i40e_tx_desc *tx_desc; 56 struct i40e_ring *tx_ring; 57 unsigned int fpt, dcc; 58 struct i40e_vsi *vsi; 59 struct device *dev; 60 dma_addr_t dma; 61 u32 td_cmd = 0; 62 u16 delay = 0; 63 u16 i; 64 65 /* find existing FDIR VSI */ 66 vsi = NULL; 67 for (i = 0; i < pf->num_alloc_vsi; i++) 68 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) 69 vsi = pf->vsi[i]; 70 if (!vsi) 71 return -ENOENT; 72 73 tx_ring = vsi->tx_rings[0]; 74 dev = tx_ring->dev; 75 76 /* we need two descriptors to add/del a filter and we can wait */ 77 do { 78 if (I40E_DESC_UNUSED(tx_ring) > 1) 79 break; 80 msleep_interruptible(1); 81 delay++; 82 } while (delay < I40E_FD_CLEAN_DELAY); 83 84 if (!(I40E_DESC_UNUSED(tx_ring) > 1)) 85 return -EAGAIN; 86 87 dma = dma_map_single(dev, raw_packet, 88 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); 89 if (dma_mapping_error(dev, dma)) 90 goto dma_fail; 91 92 /* grab the next descriptor */ 93 i = tx_ring->next_to_use; 94 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 95 first = &tx_ring->tx_bi[i]; 96 memset(first, 0, sizeof(struct i40e_tx_buffer)); 97 98 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; 99 100 fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 101 I40E_TXD_FLTR_QW0_QINDEX_MASK; 102 103 fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) & 104 I40E_TXD_FLTR_QW0_FLEXOFF_MASK; 105 106 fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) & 107 I40E_TXD_FLTR_QW0_PCTYPE_MASK; 108 109 /* Use LAN VSI Id if not programmed by user */ 110 if (fdir_data->dest_vsi == 0) 111 fpt |= (pf->vsi[pf->lan_vsi]->id) << 112 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 113 else 114 fpt |= ((u32)fdir_data->dest_vsi << 115 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) & 116 I40E_TXD_FLTR_QW0_DEST_VSI_MASK; 117 118 dcc = I40E_TX_DESC_DTYPE_FILTER_PROG; 119 120 if (add) 121 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 122 I40E_TXD_FLTR_QW1_PCMD_SHIFT; 123 else 124 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 125 I40E_TXD_FLTR_QW1_PCMD_SHIFT; 126 127 dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) & 128 I40E_TXD_FLTR_QW1_DEST_MASK; 129 130 dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) & 131 I40E_TXD_FLTR_QW1_FD_STATUS_MASK; 132 133 if (fdir_data->cnt_index != 0) { 134 dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 135 dcc |= ((u32)fdir_data->cnt_index << 136 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 137 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 138 } 139 140 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt); 141 fdir_desc->rsvd = cpu_to_le32(0); 142 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc); 143 fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id); 144 145 /* Now program a dummy descriptor */ 146 i = tx_ring->next_to_use; 147 tx_desc = I40E_TX_DESC(tx_ring, i); 148 tx_buf = &tx_ring->tx_bi[i]; 149 150 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; 151 152 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); 153 154 /* record length, and DMA address */ 155 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); 156 dma_unmap_addr_set(tx_buf, dma, dma); 157 158 tx_desc->buffer_addr = cpu_to_le64(dma); 159 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; 160 161 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; 162 tx_buf->raw_buf = (void *)raw_packet; 163 164 tx_desc->cmd_type_offset_bsz = 165 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); 166 167 /* set the timestamp */ 168 tx_buf->time_stamp = jiffies; 169 170 /* Force memory writes to complete before letting h/w 171 * know there are new descriptors to fetch. 172 */ 173 wmb(); 174 175 /* Mark the data descriptor to be watched */ 176 first->next_to_watch = tx_desc; 177 178 writel(tx_ring->next_to_use, tx_ring->tail); 179 return 0; 180 181 dma_fail: 182 return -1; 183 } 184 185 #define IP_HEADER_OFFSET 14 186 #define I40E_UDPIP_DUMMY_PACKET_LEN 42 187 /** 188 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters 189 * @vsi: pointer to the targeted VSI 190 * @fd_data: the flow director data required for the FDir descriptor 191 * @add: true adds a filter, false removes it 192 * 193 * Returns 0 if the filters were successfully added or removed 194 **/ 195 static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi, 196 struct i40e_fdir_filter *fd_data, 197 bool add) 198 { 199 struct i40e_pf *pf = vsi->back; 200 struct udphdr *udp; 201 struct iphdr *ip; 202 bool err = false; 203 u8 *raw_packet; 204 int ret; 205 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 206 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0, 207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 208 209 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 210 if (!raw_packet) 211 return -ENOMEM; 212 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN); 213 214 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 215 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET 216 + sizeof(struct iphdr)); 217 218 ip->daddr = fd_data->dst_ip[0]; 219 udp->dest = fd_data->dst_port; 220 ip->saddr = fd_data->src_ip[0]; 221 udp->source = fd_data->src_port; 222 223 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; 224 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 225 if (ret) { 226 dev_info(&pf->pdev->dev, 227 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 228 fd_data->pctype, fd_data->fd_id, ret); 229 err = true; 230 } else { 231 if (add) 232 dev_info(&pf->pdev->dev, 233 "Filter OK for PCTYPE %d loc = %d\n", 234 fd_data->pctype, fd_data->fd_id); 235 else 236 dev_info(&pf->pdev->dev, 237 "Filter deleted for PCTYPE %d loc = %d\n", 238 fd_data->pctype, fd_data->fd_id); 239 } 240 return err ? -EOPNOTSUPP : 0; 241 } 242 243 #define I40E_TCPIP_DUMMY_PACKET_LEN 54 244 /** 245 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters 246 * @vsi: pointer to the targeted VSI 247 * @fd_data: the flow director data required for the FDir descriptor 248 * @add: true adds a filter, false removes it 249 * 250 * Returns 0 if the filters were successfully added or removed 251 **/ 252 static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi, 253 struct i40e_fdir_filter *fd_data, 254 bool add) 255 { 256 struct i40e_pf *pf = vsi->back; 257 struct tcphdr *tcp; 258 struct iphdr *ip; 259 bool err = false; 260 u8 *raw_packet; 261 int ret; 262 /* Dummy packet */ 263 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 264 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0, 265 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11, 266 0x0, 0x72, 0, 0, 0, 0}; 267 268 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 269 if (!raw_packet) 270 return -ENOMEM; 271 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN); 272 273 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 274 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET 275 + sizeof(struct iphdr)); 276 277 ip->daddr = fd_data->dst_ip[0]; 278 tcp->dest = fd_data->dst_port; 279 ip->saddr = fd_data->src_ip[0]; 280 tcp->source = fd_data->src_port; 281 282 if (add) { 283 pf->fd_tcp_rule++; 284 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) { 285 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); 286 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED; 287 } 288 } else { 289 pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ? 290 (pf->fd_tcp_rule - 1) : 0; 291 if (pf->fd_tcp_rule == 0) { 292 pf->flags |= I40E_FLAG_FD_ATR_ENABLED; 293 dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n"); 294 } 295 } 296 297 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP; 298 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 299 300 if (ret) { 301 dev_info(&pf->pdev->dev, 302 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 303 fd_data->pctype, fd_data->fd_id, ret); 304 err = true; 305 } else { 306 if (add) 307 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n", 308 fd_data->pctype, fd_data->fd_id); 309 else 310 dev_info(&pf->pdev->dev, 311 "Filter deleted for PCTYPE %d loc = %d\n", 312 fd_data->pctype, fd_data->fd_id); 313 } 314 315 return err ? -EOPNOTSUPP : 0; 316 } 317 318 /** 319 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for 320 * a specific flow spec 321 * @vsi: pointer to the targeted VSI 322 * @fd_data: the flow director data required for the FDir descriptor 323 * @add: true adds a filter, false removes it 324 * 325 * Always returns -EOPNOTSUPP 326 **/ 327 static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi, 328 struct i40e_fdir_filter *fd_data, 329 bool add) 330 { 331 return -EOPNOTSUPP; 332 } 333 334 #define I40E_IP_DUMMY_PACKET_LEN 34 335 /** 336 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for 337 * a specific flow spec 338 * @vsi: pointer to the targeted VSI 339 * @fd_data: the flow director data required for the FDir descriptor 340 * @add: true adds a filter, false removes it 341 * 342 * Returns 0 if the filters were successfully added or removed 343 **/ 344 static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi, 345 struct i40e_fdir_filter *fd_data, 346 bool add) 347 { 348 struct i40e_pf *pf = vsi->back; 349 struct iphdr *ip; 350 bool err = false; 351 u8 *raw_packet; 352 int ret; 353 int i; 354 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 355 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0, 356 0, 0, 0, 0}; 357 358 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; 359 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) { 360 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 361 if (!raw_packet) 362 return -ENOMEM; 363 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN); 364 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 365 366 ip->saddr = fd_data->src_ip[0]; 367 ip->daddr = fd_data->dst_ip[0]; 368 ip->protocol = 0; 369 370 fd_data->pctype = i; 371 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 372 373 if (ret) { 374 dev_info(&pf->pdev->dev, 375 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 376 fd_data->pctype, fd_data->fd_id, ret); 377 err = true; 378 } else { 379 if (add) 380 dev_info(&pf->pdev->dev, 381 "Filter OK for PCTYPE %d loc = %d\n", 382 fd_data->pctype, fd_data->fd_id); 383 else 384 dev_info(&pf->pdev->dev, 385 "Filter deleted for PCTYPE %d loc = %d\n", 386 fd_data->pctype, fd_data->fd_id); 387 } 388 } 389 390 return err ? -EOPNOTSUPP : 0; 391 } 392 393 /** 394 * i40e_add_del_fdir - Build raw packets to add/del fdir filter 395 * @vsi: pointer to the targeted VSI 396 * @cmd: command to get or set RX flow classification rules 397 * @add: true adds a filter, false removes it 398 * 399 **/ 400 int i40e_add_del_fdir(struct i40e_vsi *vsi, 401 struct i40e_fdir_filter *input, bool add) 402 { 403 struct i40e_pf *pf = vsi->back; 404 int ret; 405 406 switch (input->flow_type & ~FLOW_EXT) { 407 case TCP_V4_FLOW: 408 ret = i40e_add_del_fdir_tcpv4(vsi, input, add); 409 break; 410 case UDP_V4_FLOW: 411 ret = i40e_add_del_fdir_udpv4(vsi, input, add); 412 break; 413 case SCTP_V4_FLOW: 414 ret = i40e_add_del_fdir_sctpv4(vsi, input, add); 415 break; 416 case IPV4_FLOW: 417 ret = i40e_add_del_fdir_ipv4(vsi, input, add); 418 break; 419 case IP_USER_FLOW: 420 switch (input->ip4_proto) { 421 case IPPROTO_TCP: 422 ret = i40e_add_del_fdir_tcpv4(vsi, input, add); 423 break; 424 case IPPROTO_UDP: 425 ret = i40e_add_del_fdir_udpv4(vsi, input, add); 426 break; 427 case IPPROTO_SCTP: 428 ret = i40e_add_del_fdir_sctpv4(vsi, input, add); 429 break; 430 default: 431 ret = i40e_add_del_fdir_ipv4(vsi, input, add); 432 break; 433 } 434 break; 435 default: 436 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n", 437 input->flow_type); 438 ret = -EINVAL; 439 } 440 441 /* The buffer allocated here is freed by the i40e_clean_tx_ring() */ 442 return ret; 443 } 444 445 /** 446 * i40e_fd_handle_status - check the Programming Status for FD 447 * @rx_ring: the Rx ring for this descriptor 448 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor. 449 * @prog_id: the id originally used for programming 450 * 451 * This is used to verify if the FD programming or invalidation 452 * requested by SW to the HW is successful or not and take actions accordingly. 453 **/ 454 static void i40e_fd_handle_status(struct i40e_ring *rx_ring, 455 union i40e_rx_desc *rx_desc, u8 prog_id) 456 { 457 struct i40e_pf *pf = rx_ring->vsi->back; 458 struct pci_dev *pdev = pf->pdev; 459 u32 fcnt_prog, fcnt_avail; 460 u32 error; 461 u64 qw; 462 463 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 464 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >> 465 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT; 466 467 if (error == (0x1 << I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { 468 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) || 469 (I40E_DEBUG_FD & pf->hw.debug_mask)) 470 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", 471 rx_desc->wb.qword0.hi_dword.fd_id); 472 473 pf->fd_add_err++; 474 /* store the current atr filter count */ 475 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); 476 477 /* filter programming failed most likely due to table full */ 478 fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf); 479 fcnt_avail = pf->fdir_pf_filter_count; 480 /* If ATR is running fcnt_prog can quickly change, 481 * if we are very close to full, it makes sense to disable 482 * FD ATR/SB and then re-enable it when there is room. 483 */ 484 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { 485 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && 486 !(pf->auto_disable_flags & 487 I40E_FLAG_FD_SB_ENABLED)) { 488 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); 489 pf->auto_disable_flags |= 490 I40E_FLAG_FD_SB_ENABLED; 491 } 492 } else { 493 dev_info(&pdev->dev, 494 "FD filter programming failed due to incorrect filter parameters\n"); 495 } 496 } else if (error == 497 (0x1 << I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { 498 if (I40E_DEBUG_FD & pf->hw.debug_mask) 499 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", 500 rx_desc->wb.qword0.hi_dword.fd_id); 501 } 502 } 503 504 /** 505 * i40e_unmap_and_free_tx_resource - Release a Tx buffer 506 * @ring: the ring that owns the buffer 507 * @tx_buffer: the buffer to free 508 **/ 509 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, 510 struct i40e_tx_buffer *tx_buffer) 511 { 512 if (tx_buffer->skb) { 513 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) 514 kfree(tx_buffer->raw_buf); 515 else 516 dev_kfree_skb_any(tx_buffer->skb); 517 518 if (dma_unmap_len(tx_buffer, len)) 519 dma_unmap_single(ring->dev, 520 dma_unmap_addr(tx_buffer, dma), 521 dma_unmap_len(tx_buffer, len), 522 DMA_TO_DEVICE); 523 } else if (dma_unmap_len(tx_buffer, len)) { 524 dma_unmap_page(ring->dev, 525 dma_unmap_addr(tx_buffer, dma), 526 dma_unmap_len(tx_buffer, len), 527 DMA_TO_DEVICE); 528 } 529 tx_buffer->next_to_watch = NULL; 530 tx_buffer->skb = NULL; 531 dma_unmap_len_set(tx_buffer, len, 0); 532 /* tx_buffer must be completely set up in the transmit path */ 533 } 534 535 /** 536 * i40e_clean_tx_ring - Free any empty Tx buffers 537 * @tx_ring: ring to be cleaned 538 **/ 539 void i40e_clean_tx_ring(struct i40e_ring *tx_ring) 540 { 541 unsigned long bi_size; 542 u16 i; 543 544 /* ring already cleared, nothing to do */ 545 if (!tx_ring->tx_bi) 546 return; 547 548 /* Free all the Tx ring sk_buffs */ 549 for (i = 0; i < tx_ring->count; i++) 550 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); 551 552 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 553 memset(tx_ring->tx_bi, 0, bi_size); 554 555 /* Zero out the descriptor ring */ 556 memset(tx_ring->desc, 0, tx_ring->size); 557 558 tx_ring->next_to_use = 0; 559 tx_ring->next_to_clean = 0; 560 561 if (!tx_ring->netdev) 562 return; 563 564 /* cleanup Tx queue statistics */ 565 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev, 566 tx_ring->queue_index)); 567 } 568 569 /** 570 * i40e_free_tx_resources - Free Tx resources per queue 571 * @tx_ring: Tx descriptor ring for a specific queue 572 * 573 * Free all transmit software resources 574 **/ 575 void i40e_free_tx_resources(struct i40e_ring *tx_ring) 576 { 577 i40e_clean_tx_ring(tx_ring); 578 kfree(tx_ring->tx_bi); 579 tx_ring->tx_bi = NULL; 580 581 if (tx_ring->desc) { 582 dma_free_coherent(tx_ring->dev, tx_ring->size, 583 tx_ring->desc, tx_ring->dma); 584 tx_ring->desc = NULL; 585 } 586 } 587 588 /** 589 * i40e_get_tx_pending - how many tx descriptors not processed 590 * @tx_ring: the ring of descriptors 591 * 592 * Since there is no access to the ring head register 593 * in XL710, we need to use our local copies 594 **/ 595 static u32 i40e_get_tx_pending(struct i40e_ring *ring) 596 { 597 u32 ntu = ((ring->next_to_clean <= ring->next_to_use) 598 ? ring->next_to_use 599 : ring->next_to_use + ring->count); 600 return ntu - ring->next_to_clean; 601 } 602 603 /** 604 * i40e_check_tx_hang - Is there a hang in the Tx queue 605 * @tx_ring: the ring of descriptors 606 **/ 607 static bool i40e_check_tx_hang(struct i40e_ring *tx_ring) 608 { 609 u32 tx_pending = i40e_get_tx_pending(tx_ring); 610 struct i40e_pf *pf = tx_ring->vsi->back; 611 bool ret = false; 612 613 clear_check_for_tx_hang(tx_ring); 614 615 /* Check for a hung queue, but be thorough. This verifies 616 * that a transmit has been completed since the previous 617 * check AND there is at least one packet pending. The 618 * ARMED bit is set to indicate a potential hang. The 619 * bit is cleared if a pause frame is received to remove 620 * false hang detection due to PFC or 802.3x frames. By 621 * requiring this to fail twice we avoid races with 622 * PFC clearing the ARMED bit and conditions where we 623 * run the check_tx_hang logic with a transmit completion 624 * pending but without time to complete it yet. 625 */ 626 if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) && 627 (tx_pending >= I40E_MIN_DESC_PENDING)) { 628 /* make sure it is true for two checks in a row */ 629 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED, 630 &tx_ring->state); 631 } else if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) && 632 (tx_pending < I40E_MIN_DESC_PENDING) && 633 (tx_pending > 0)) { 634 if (I40E_DEBUG_FLOW & pf->hw.debug_mask) 635 dev_info(tx_ring->dev, "HW needs some more descs to do a cacheline flush. tx_pending %d, queue %d", 636 tx_pending, tx_ring->queue_index); 637 pf->tx_sluggish_count++; 638 } else { 639 /* update completed stats and disarm the hang check */ 640 tx_ring->tx_stats.tx_done_old = tx_ring->stats.packets; 641 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state); 642 } 643 644 return ret; 645 } 646 647 /** 648 * i40e_get_head - Retrieve head from head writeback 649 * @tx_ring: tx ring to fetch head of 650 * 651 * Returns value of Tx ring head based on value stored 652 * in head write-back location 653 **/ 654 static inline u32 i40e_get_head(struct i40e_ring *tx_ring) 655 { 656 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count; 657 658 return le32_to_cpu(*(volatile __le32 *)head); 659 } 660 661 #define WB_STRIDE 0x3 662 663 /** 664 * i40e_clean_tx_irq - Reclaim resources after transmit completes 665 * @tx_ring: tx ring to clean 666 * @budget: how many cleans we're allowed 667 * 668 * Returns true if there's any budget left (e.g. the clean is finished) 669 **/ 670 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget) 671 { 672 u16 i = tx_ring->next_to_clean; 673 struct i40e_tx_buffer *tx_buf; 674 struct i40e_tx_desc *tx_head; 675 struct i40e_tx_desc *tx_desc; 676 unsigned int total_packets = 0; 677 unsigned int total_bytes = 0; 678 679 tx_buf = &tx_ring->tx_bi[i]; 680 tx_desc = I40E_TX_DESC(tx_ring, i); 681 i -= tx_ring->count; 682 683 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); 684 685 do { 686 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; 687 688 /* if next_to_watch is not set then there is no work pending */ 689 if (!eop_desc) 690 break; 691 692 /* prevent any other reads prior to eop_desc */ 693 read_barrier_depends(); 694 695 /* we have caught up to head, no work left to do */ 696 if (tx_head == tx_desc) 697 break; 698 699 /* clear next_to_watch to prevent false hangs */ 700 tx_buf->next_to_watch = NULL; 701 702 /* update the statistics for this packet */ 703 total_bytes += tx_buf->bytecount; 704 total_packets += tx_buf->gso_segs; 705 706 /* free the skb */ 707 dev_consume_skb_any(tx_buf->skb); 708 709 /* unmap skb header data */ 710 dma_unmap_single(tx_ring->dev, 711 dma_unmap_addr(tx_buf, dma), 712 dma_unmap_len(tx_buf, len), 713 DMA_TO_DEVICE); 714 715 /* clear tx_buffer data */ 716 tx_buf->skb = NULL; 717 dma_unmap_len_set(tx_buf, len, 0); 718 719 /* unmap remaining buffers */ 720 while (tx_desc != eop_desc) { 721 722 tx_buf++; 723 tx_desc++; 724 i++; 725 if (unlikely(!i)) { 726 i -= tx_ring->count; 727 tx_buf = tx_ring->tx_bi; 728 tx_desc = I40E_TX_DESC(tx_ring, 0); 729 } 730 731 /* unmap any remaining paged data */ 732 if (dma_unmap_len(tx_buf, len)) { 733 dma_unmap_page(tx_ring->dev, 734 dma_unmap_addr(tx_buf, dma), 735 dma_unmap_len(tx_buf, len), 736 DMA_TO_DEVICE); 737 dma_unmap_len_set(tx_buf, len, 0); 738 } 739 } 740 741 /* move us one more past the eop_desc for start of next pkt */ 742 tx_buf++; 743 tx_desc++; 744 i++; 745 if (unlikely(!i)) { 746 i -= tx_ring->count; 747 tx_buf = tx_ring->tx_bi; 748 tx_desc = I40E_TX_DESC(tx_ring, 0); 749 } 750 751 /* update budget accounting */ 752 budget--; 753 } while (likely(budget)); 754 755 i += tx_ring->count; 756 tx_ring->next_to_clean = i; 757 u64_stats_update_begin(&tx_ring->syncp); 758 tx_ring->stats.bytes += total_bytes; 759 tx_ring->stats.packets += total_packets; 760 u64_stats_update_end(&tx_ring->syncp); 761 tx_ring->q_vector->tx.total_bytes += total_bytes; 762 tx_ring->q_vector->tx.total_packets += total_packets; 763 764 /* check to see if there are any non-cache aligned descriptors 765 * waiting to be written back, and kick the hardware to force 766 * them to be written back in case of napi polling 767 */ 768 if (budget && 769 !((i & WB_STRIDE) == WB_STRIDE) && 770 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) && 771 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) 772 tx_ring->arm_wb = true; 773 else 774 tx_ring->arm_wb = false; 775 776 if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) { 777 /* schedule immediate reset if we believe we hung */ 778 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n" 779 " VSI <%d>\n" 780 " Tx Queue <%d>\n" 781 " next_to_use <%x>\n" 782 " next_to_clean <%x>\n", 783 tx_ring->vsi->seid, 784 tx_ring->queue_index, 785 tx_ring->next_to_use, i); 786 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n" 787 " time_stamp <%lx>\n" 788 " jiffies <%lx>\n", 789 tx_ring->tx_bi[i].time_stamp, jiffies); 790 791 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 792 793 dev_info(tx_ring->dev, 794 "tx hang detected on queue %d, reset requested\n", 795 tx_ring->queue_index); 796 797 /* do not fire the reset immediately, wait for the stack to 798 * decide we are truly stuck, also prevents every queue from 799 * simultaneously requesting a reset 800 */ 801 802 /* the adapter is about to reset, no point in enabling polling */ 803 budget = 1; 804 } 805 806 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev, 807 tx_ring->queue_index), 808 total_packets, total_bytes); 809 810 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 811 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 812 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { 813 /* Make sure that anybody stopping the queue after this 814 * sees the new next_to_clean. 815 */ 816 smp_mb(); 817 if (__netif_subqueue_stopped(tx_ring->netdev, 818 tx_ring->queue_index) && 819 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) { 820 netif_wake_subqueue(tx_ring->netdev, 821 tx_ring->queue_index); 822 ++tx_ring->tx_stats.restart_queue; 823 } 824 } 825 826 return !!budget; 827 } 828 829 /** 830 * i40e_force_wb - Arm hardware to do a wb on noncache aligned descriptors 831 * @vsi: the VSI we care about 832 * @q_vector: the vector on which to force writeback 833 * 834 **/ 835 static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) 836 { 837 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 838 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | 839 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK 840 /* allow 00 to be written to the index */; 841 842 wr32(&vsi->back->hw, 843 I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1), 844 val); 845 } 846 847 /** 848 * i40e_set_new_dynamic_itr - Find new ITR level 849 * @rc: structure containing ring performance data 850 * 851 * Stores a new ITR value based on packets and byte counts during 852 * the last interrupt. The advantage of per interrupt computation 853 * is faster updates and more accurate ITR for the current traffic 854 * pattern. Constants in this function were computed based on 855 * theoretical maximum wire speed and thresholds were set based on 856 * testing data as well as attempting to minimize response time 857 * while increasing bulk throughput. 858 **/ 859 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) 860 { 861 enum i40e_latency_range new_latency_range = rc->latency_range; 862 u32 new_itr = rc->itr; 863 int bytes_per_int; 864 865 if (rc->total_packets == 0 || !rc->itr) 866 return; 867 868 /* simple throttlerate management 869 * 0-10MB/s lowest (100000 ints/s) 870 * 10-20MB/s low (20000 ints/s) 871 * 20-1249MB/s bulk (8000 ints/s) 872 */ 873 bytes_per_int = rc->total_bytes / rc->itr; 874 switch (rc->itr) { 875 case I40E_LOWEST_LATENCY: 876 if (bytes_per_int > 10) 877 new_latency_range = I40E_LOW_LATENCY; 878 break; 879 case I40E_LOW_LATENCY: 880 if (bytes_per_int > 20) 881 new_latency_range = I40E_BULK_LATENCY; 882 else if (bytes_per_int <= 10) 883 new_latency_range = I40E_LOWEST_LATENCY; 884 break; 885 case I40E_BULK_LATENCY: 886 if (bytes_per_int <= 20) 887 rc->latency_range = I40E_LOW_LATENCY; 888 break; 889 } 890 891 switch (new_latency_range) { 892 case I40E_LOWEST_LATENCY: 893 new_itr = I40E_ITR_100K; 894 break; 895 case I40E_LOW_LATENCY: 896 new_itr = I40E_ITR_20K; 897 break; 898 case I40E_BULK_LATENCY: 899 new_itr = I40E_ITR_8K; 900 break; 901 default: 902 break; 903 } 904 905 if (new_itr != rc->itr) { 906 /* do an exponential smoothing */ 907 new_itr = (10 * new_itr * rc->itr) / 908 ((9 * new_itr) + rc->itr); 909 rc->itr = new_itr & I40E_MAX_ITR; 910 } 911 912 rc->total_bytes = 0; 913 rc->total_packets = 0; 914 } 915 916 /** 917 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int 918 * @q_vector: the vector to adjust 919 **/ 920 static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector) 921 { 922 u16 vector = q_vector->vsi->base_vector + q_vector->v_idx; 923 struct i40e_hw *hw = &q_vector->vsi->back->hw; 924 u32 reg_addr; 925 u16 old_itr; 926 927 reg_addr = I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1); 928 old_itr = q_vector->rx.itr; 929 i40e_set_new_dynamic_itr(&q_vector->rx); 930 if (old_itr != q_vector->rx.itr) 931 wr32(hw, reg_addr, q_vector->rx.itr); 932 933 reg_addr = I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1); 934 old_itr = q_vector->tx.itr; 935 i40e_set_new_dynamic_itr(&q_vector->tx); 936 if (old_itr != q_vector->tx.itr) 937 wr32(hw, reg_addr, q_vector->tx.itr); 938 } 939 940 /** 941 * i40e_clean_programming_status - clean the programming status descriptor 942 * @rx_ring: the rx ring that has this descriptor 943 * @rx_desc: the rx descriptor written back by HW 944 * 945 * Flow director should handle FD_FILTER_STATUS to check its filter programming 946 * status being successful or not and take actions accordingly. FCoE should 947 * handle its context/filter programming/invalidation status and take actions. 948 * 949 **/ 950 static void i40e_clean_programming_status(struct i40e_ring *rx_ring, 951 union i40e_rx_desc *rx_desc) 952 { 953 u64 qw; 954 u8 id; 955 956 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 957 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >> 958 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT; 959 960 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) 961 i40e_fd_handle_status(rx_ring, rx_desc, id); 962 #ifdef I40E_FCOE 963 else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) || 964 (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS)) 965 i40e_fcoe_handle_status(rx_ring, rx_desc, id); 966 #endif 967 } 968 969 /** 970 * i40e_setup_tx_descriptors - Allocate the Tx descriptors 971 * @tx_ring: the tx ring to set up 972 * 973 * Return 0 on success, negative on error 974 **/ 975 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) 976 { 977 struct device *dev = tx_ring->dev; 978 int bi_size; 979 980 if (!dev) 981 return -ENOMEM; 982 983 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 984 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); 985 if (!tx_ring->tx_bi) 986 goto err; 987 988 /* round up to nearest 4K */ 989 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); 990 /* add u32 for head writeback, align after this takes care of 991 * guaranteeing this is at least one cache line in size 992 */ 993 tx_ring->size += sizeof(u32); 994 tx_ring->size = ALIGN(tx_ring->size, 4096); 995 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 996 &tx_ring->dma, GFP_KERNEL); 997 if (!tx_ring->desc) { 998 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", 999 tx_ring->size); 1000 goto err; 1001 } 1002 1003 tx_ring->next_to_use = 0; 1004 tx_ring->next_to_clean = 0; 1005 return 0; 1006 1007 err: 1008 kfree(tx_ring->tx_bi); 1009 tx_ring->tx_bi = NULL; 1010 return -ENOMEM; 1011 } 1012 1013 /** 1014 * i40e_clean_rx_ring - Free Rx buffers 1015 * @rx_ring: ring to be cleaned 1016 **/ 1017 void i40e_clean_rx_ring(struct i40e_ring *rx_ring) 1018 { 1019 struct device *dev = rx_ring->dev; 1020 struct i40e_rx_buffer *rx_bi; 1021 unsigned long bi_size; 1022 u16 i; 1023 1024 /* ring already cleared, nothing to do */ 1025 if (!rx_ring->rx_bi) 1026 return; 1027 1028 /* Free all the Rx ring sk_buffs */ 1029 for (i = 0; i < rx_ring->count; i++) { 1030 rx_bi = &rx_ring->rx_bi[i]; 1031 if (rx_bi->dma) { 1032 dma_unmap_single(dev, 1033 rx_bi->dma, 1034 rx_ring->rx_buf_len, 1035 DMA_FROM_DEVICE); 1036 rx_bi->dma = 0; 1037 } 1038 if (rx_bi->skb) { 1039 dev_kfree_skb(rx_bi->skb); 1040 rx_bi->skb = NULL; 1041 } 1042 if (rx_bi->page) { 1043 if (rx_bi->page_dma) { 1044 dma_unmap_page(dev, 1045 rx_bi->page_dma, 1046 PAGE_SIZE / 2, 1047 DMA_FROM_DEVICE); 1048 rx_bi->page_dma = 0; 1049 } 1050 __free_page(rx_bi->page); 1051 rx_bi->page = NULL; 1052 rx_bi->page_offset = 0; 1053 } 1054 } 1055 1056 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; 1057 memset(rx_ring->rx_bi, 0, bi_size); 1058 1059 /* Zero out the descriptor ring */ 1060 memset(rx_ring->desc, 0, rx_ring->size); 1061 1062 rx_ring->next_to_clean = 0; 1063 rx_ring->next_to_use = 0; 1064 } 1065 1066 /** 1067 * i40e_free_rx_resources - Free Rx resources 1068 * @rx_ring: ring to clean the resources from 1069 * 1070 * Free all receive software resources 1071 **/ 1072 void i40e_free_rx_resources(struct i40e_ring *rx_ring) 1073 { 1074 i40e_clean_rx_ring(rx_ring); 1075 kfree(rx_ring->rx_bi); 1076 rx_ring->rx_bi = NULL; 1077 1078 if (rx_ring->desc) { 1079 dma_free_coherent(rx_ring->dev, rx_ring->size, 1080 rx_ring->desc, rx_ring->dma); 1081 rx_ring->desc = NULL; 1082 } 1083 } 1084 1085 /** 1086 * i40e_setup_rx_descriptors - Allocate Rx descriptors 1087 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 1088 * 1089 * Returns 0 on success, negative on failure 1090 **/ 1091 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) 1092 { 1093 struct device *dev = rx_ring->dev; 1094 int bi_size; 1095 1096 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; 1097 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); 1098 if (!rx_ring->rx_bi) 1099 goto err; 1100 1101 /* Round up to nearest 4K */ 1102 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring) 1103 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc) 1104 : rx_ring->count * sizeof(union i40e_32byte_rx_desc); 1105 rx_ring->size = ALIGN(rx_ring->size, 4096); 1106 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 1107 &rx_ring->dma, GFP_KERNEL); 1108 1109 if (!rx_ring->desc) { 1110 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", 1111 rx_ring->size); 1112 goto err; 1113 } 1114 1115 rx_ring->next_to_clean = 0; 1116 rx_ring->next_to_use = 0; 1117 1118 return 0; 1119 err: 1120 kfree(rx_ring->rx_bi); 1121 rx_ring->rx_bi = NULL; 1122 return -ENOMEM; 1123 } 1124 1125 /** 1126 * i40e_release_rx_desc - Store the new tail and head values 1127 * @rx_ring: ring to bump 1128 * @val: new head index 1129 **/ 1130 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) 1131 { 1132 rx_ring->next_to_use = val; 1133 /* Force memory writes to complete before letting h/w 1134 * know there are new descriptors to fetch. (Only 1135 * applicable for weak-ordered memory model archs, 1136 * such as IA-64). 1137 */ 1138 wmb(); 1139 writel(val, rx_ring->tail); 1140 } 1141 1142 /** 1143 * i40e_alloc_rx_buffers - Replace used receive buffers; packet split 1144 * @rx_ring: ring to place buffers on 1145 * @cleaned_count: number of buffers to replace 1146 **/ 1147 void i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) 1148 { 1149 u16 i = rx_ring->next_to_use; 1150 union i40e_rx_desc *rx_desc; 1151 struct i40e_rx_buffer *bi; 1152 struct sk_buff *skb; 1153 1154 /* do nothing if no valid netdev defined */ 1155 if (!rx_ring->netdev || !cleaned_count) 1156 return; 1157 1158 while (cleaned_count--) { 1159 rx_desc = I40E_RX_DESC(rx_ring, i); 1160 bi = &rx_ring->rx_bi[i]; 1161 skb = bi->skb; 1162 1163 if (!skb) { 1164 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 1165 rx_ring->rx_buf_len); 1166 if (!skb) { 1167 rx_ring->rx_stats.alloc_buff_failed++; 1168 goto no_buffers; 1169 } 1170 /* initialize queue mapping */ 1171 skb_record_rx_queue(skb, rx_ring->queue_index); 1172 bi->skb = skb; 1173 } 1174 1175 if (!bi->dma) { 1176 bi->dma = dma_map_single(rx_ring->dev, 1177 skb->data, 1178 rx_ring->rx_buf_len, 1179 DMA_FROM_DEVICE); 1180 if (dma_mapping_error(rx_ring->dev, bi->dma)) { 1181 rx_ring->rx_stats.alloc_buff_failed++; 1182 bi->dma = 0; 1183 goto no_buffers; 1184 } 1185 } 1186 1187 if (ring_is_ps_enabled(rx_ring)) { 1188 if (!bi->page) { 1189 bi->page = alloc_page(GFP_ATOMIC); 1190 if (!bi->page) { 1191 rx_ring->rx_stats.alloc_page_failed++; 1192 goto no_buffers; 1193 } 1194 } 1195 1196 if (!bi->page_dma) { 1197 /* use a half page if we're re-using */ 1198 bi->page_offset ^= PAGE_SIZE / 2; 1199 bi->page_dma = dma_map_page(rx_ring->dev, 1200 bi->page, 1201 bi->page_offset, 1202 PAGE_SIZE / 2, 1203 DMA_FROM_DEVICE); 1204 if (dma_mapping_error(rx_ring->dev, 1205 bi->page_dma)) { 1206 rx_ring->rx_stats.alloc_page_failed++; 1207 bi->page_dma = 0; 1208 goto no_buffers; 1209 } 1210 } 1211 1212 /* Refresh the desc even if buffer_addrs didn't change 1213 * because each write-back erases this info. 1214 */ 1215 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); 1216 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); 1217 } else { 1218 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); 1219 rx_desc->read.hdr_addr = 0; 1220 } 1221 i++; 1222 if (i == rx_ring->count) 1223 i = 0; 1224 } 1225 1226 no_buffers: 1227 if (rx_ring->next_to_use != i) 1228 i40e_release_rx_desc(rx_ring, i); 1229 } 1230 1231 /** 1232 * i40e_receive_skb - Send a completed packet up the stack 1233 * @rx_ring: rx ring in play 1234 * @skb: packet to send up 1235 * @vlan_tag: vlan tag for packet 1236 **/ 1237 static void i40e_receive_skb(struct i40e_ring *rx_ring, 1238 struct sk_buff *skb, u16 vlan_tag) 1239 { 1240 struct i40e_q_vector *q_vector = rx_ring->q_vector; 1241 struct i40e_vsi *vsi = rx_ring->vsi; 1242 u64 flags = vsi->back->flags; 1243 1244 if (vlan_tag & VLAN_VID_MASK) 1245 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 1246 1247 if (flags & I40E_FLAG_IN_NETPOLL) 1248 netif_rx(skb); 1249 else 1250 napi_gro_receive(&q_vector->napi, skb); 1251 } 1252 1253 /** 1254 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum 1255 * @vsi: the VSI we care about 1256 * @skb: skb currently being received and modified 1257 * @rx_status: status value of last descriptor in packet 1258 * @rx_error: error value of last descriptor in packet 1259 * @rx_ptype: ptype value of last descriptor in packet 1260 **/ 1261 static inline void i40e_rx_checksum(struct i40e_vsi *vsi, 1262 struct sk_buff *skb, 1263 u32 rx_status, 1264 u32 rx_error, 1265 u16 rx_ptype) 1266 { 1267 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype); 1268 bool ipv4 = false, ipv6 = false; 1269 bool ipv4_tunnel, ipv6_tunnel; 1270 __wsum rx_udp_csum; 1271 struct iphdr *iph; 1272 __sum16 csum; 1273 1274 ipv4_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT4_MAC_PAY3) && 1275 (rx_ptype < I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4); 1276 ipv6_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT6_MAC_PAY3) && 1277 (rx_ptype < I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4); 1278 1279 skb->ip_summed = CHECKSUM_NONE; 1280 1281 /* Rx csum enabled and ip headers found? */ 1282 if (!(vsi->netdev->features & NETIF_F_RXCSUM)) 1283 return; 1284 1285 /* did the hardware decode the packet and checksum? */ 1286 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT))) 1287 return; 1288 1289 /* both known and outer_ip must be set for the below code to work */ 1290 if (!(decoded.known && decoded.outer_ip)) 1291 return; 1292 1293 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1294 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4) 1295 ipv4 = true; 1296 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1297 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6) 1298 ipv6 = true; 1299 1300 if (ipv4 && 1301 (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) | 1302 (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))) 1303 goto checksum_fail; 1304 1305 /* likely incorrect csum if alternate IP extension headers found */ 1306 if (ipv6 && 1307 rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) 1308 /* don't increment checksum err here, non-fatal err */ 1309 return; 1310 1311 /* there was some L4 error, count error and punt packet to the stack */ 1312 if (rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)) 1313 goto checksum_fail; 1314 1315 /* handle packets that were not able to be checksummed due 1316 * to arrival speed, in this case the stack can compute 1317 * the csum. 1318 */ 1319 if (rx_error & (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT)) 1320 return; 1321 1322 /* If VXLAN traffic has an outer UDPv4 checksum we need to check 1323 * it in the driver, hardware does not do it for us. 1324 * Since L3L4P bit was set we assume a valid IHL value (>=5) 1325 * so the total length of IPv4 header is IHL*4 bytes 1326 * The UDP_0 bit *may* bet set if the *inner* header is UDP 1327 */ 1328 if (ipv4_tunnel) { 1329 skb->transport_header = skb->mac_header + 1330 sizeof(struct ethhdr) + 1331 (ip_hdr(skb)->ihl * 4); 1332 1333 /* Add 4 bytes for VLAN tagged packets */ 1334 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) || 1335 skb->protocol == htons(ETH_P_8021AD)) 1336 ? VLAN_HLEN : 0; 1337 1338 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) && 1339 (udp_hdr(skb)->check != 0)) { 1340 rx_udp_csum = udp_csum(skb); 1341 iph = ip_hdr(skb); 1342 csum = csum_tcpudp_magic( 1343 iph->saddr, iph->daddr, 1344 (skb->len - skb_transport_offset(skb)), 1345 IPPROTO_UDP, rx_udp_csum); 1346 1347 if (udp_hdr(skb)->check != csum) 1348 goto checksum_fail; 1349 1350 } /* else its GRE and so no outer UDP header */ 1351 } 1352 1353 skb->ip_summed = CHECKSUM_UNNECESSARY; 1354 skb->csum_level = ipv4_tunnel || ipv6_tunnel; 1355 1356 return; 1357 1358 checksum_fail: 1359 vsi->back->hw_csum_rx_error++; 1360 } 1361 1362 /** 1363 * i40e_rx_hash - returns the hash value from the Rx descriptor 1364 * @ring: descriptor ring 1365 * @rx_desc: specific descriptor 1366 **/ 1367 static inline u32 i40e_rx_hash(struct i40e_ring *ring, 1368 union i40e_rx_desc *rx_desc) 1369 { 1370 const __le64 rss_mask = 1371 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << 1372 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); 1373 1374 if ((ring->netdev->features & NETIF_F_RXHASH) && 1375 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) 1376 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); 1377 else 1378 return 0; 1379 } 1380 1381 /** 1382 * i40e_ptype_to_hash - get a hash type 1383 * @ptype: the ptype value from the descriptor 1384 * 1385 * Returns a hash type to be used by skb_set_hash 1386 **/ 1387 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype) 1388 { 1389 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); 1390 1391 if (!decoded.known) 1392 return PKT_HASH_TYPE_NONE; 1393 1394 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1395 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) 1396 return PKT_HASH_TYPE_L4; 1397 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1398 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) 1399 return PKT_HASH_TYPE_L3; 1400 else 1401 return PKT_HASH_TYPE_L2; 1402 } 1403 1404 /** 1405 * i40e_clean_rx_irq - Reclaim resources after receive completes 1406 * @rx_ring: rx ring to clean 1407 * @budget: how many cleans we're allowed 1408 * 1409 * Returns true if there's any budget left (e.g. the clean is finished) 1410 **/ 1411 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) 1412 { 1413 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1414 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo; 1415 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); 1416 const int current_node = numa_node_id(); 1417 struct i40e_vsi *vsi = rx_ring->vsi; 1418 u16 i = rx_ring->next_to_clean; 1419 union i40e_rx_desc *rx_desc; 1420 u32 rx_error, rx_status; 1421 u8 rx_ptype; 1422 u64 qword; 1423 1424 if (budget <= 0) 1425 return 0; 1426 1427 rx_desc = I40E_RX_DESC(rx_ring, i); 1428 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1429 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1430 I40E_RXD_QW1_STATUS_SHIFT; 1431 1432 while (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) { 1433 union i40e_rx_desc *next_rxd; 1434 struct i40e_rx_buffer *rx_bi; 1435 struct sk_buff *skb; 1436 u16 vlan_tag; 1437 if (i40e_rx_is_programming_status(qword)) { 1438 i40e_clean_programming_status(rx_ring, rx_desc); 1439 I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd); 1440 goto next_desc; 1441 } 1442 rx_bi = &rx_ring->rx_bi[i]; 1443 skb = rx_bi->skb; 1444 prefetch(skb->data); 1445 1446 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> 1447 I40E_RXD_QW1_LENGTH_PBUF_SHIFT; 1448 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >> 1449 I40E_RXD_QW1_LENGTH_HBUF_SHIFT; 1450 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >> 1451 I40E_RXD_QW1_LENGTH_SPH_SHIFT; 1452 1453 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> 1454 I40E_RXD_QW1_ERROR_SHIFT; 1455 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT); 1456 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT); 1457 1458 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> 1459 I40E_RXD_QW1_PTYPE_SHIFT; 1460 rx_bi->skb = NULL; 1461 1462 /* This memory barrier is needed to keep us from reading 1463 * any other fields out of the rx_desc until we know the 1464 * STATUS_DD bit is set 1465 */ 1466 rmb(); 1467 1468 /* Get the header and possibly the whole packet 1469 * If this is an skb from previous receive dma will be 0 1470 */ 1471 if (rx_bi->dma) { 1472 u16 len; 1473 1474 if (rx_hbo) 1475 len = I40E_RX_HDR_SIZE; 1476 else if (rx_sph) 1477 len = rx_header_len; 1478 else if (rx_packet_len) 1479 len = rx_packet_len; /* 1buf/no split found */ 1480 else 1481 len = rx_header_len; /* split always mode */ 1482 1483 skb_put(skb, len); 1484 dma_unmap_single(rx_ring->dev, 1485 rx_bi->dma, 1486 rx_ring->rx_buf_len, 1487 DMA_FROM_DEVICE); 1488 rx_bi->dma = 0; 1489 } 1490 1491 /* Get the rest of the data if this was a header split */ 1492 if (ring_is_ps_enabled(rx_ring) && rx_packet_len) { 1493 1494 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, 1495 rx_bi->page, 1496 rx_bi->page_offset, 1497 rx_packet_len); 1498 1499 skb->len += rx_packet_len; 1500 skb->data_len += rx_packet_len; 1501 skb->truesize += rx_packet_len; 1502 1503 if ((page_count(rx_bi->page) == 1) && 1504 (page_to_nid(rx_bi->page) == current_node)) 1505 get_page(rx_bi->page); 1506 else 1507 rx_bi->page = NULL; 1508 1509 dma_unmap_page(rx_ring->dev, 1510 rx_bi->page_dma, 1511 PAGE_SIZE / 2, 1512 DMA_FROM_DEVICE); 1513 rx_bi->page_dma = 0; 1514 } 1515 I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd); 1516 1517 if (unlikely( 1518 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) { 1519 struct i40e_rx_buffer *next_buffer; 1520 1521 next_buffer = &rx_ring->rx_bi[i]; 1522 1523 if (ring_is_ps_enabled(rx_ring)) { 1524 rx_bi->skb = next_buffer->skb; 1525 rx_bi->dma = next_buffer->dma; 1526 next_buffer->skb = skb; 1527 next_buffer->dma = 0; 1528 } 1529 rx_ring->rx_stats.non_eop_descs++; 1530 goto next_desc; 1531 } 1532 1533 /* ERR_MASK will only have valid bits if EOP set */ 1534 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) { 1535 dev_kfree_skb_any(skb); 1536 /* TODO: shouldn't we increment a counter indicating the 1537 * drop? 1538 */ 1539 goto next_desc; 1540 } 1541 1542 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc), 1543 i40e_ptype_to_hash(rx_ptype)); 1544 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) { 1545 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status & 1546 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> 1547 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT); 1548 rx_ring->last_rx_timestamp = jiffies; 1549 } 1550 1551 /* probably a little skewed due to removing CRC */ 1552 total_rx_bytes += skb->len; 1553 total_rx_packets++; 1554 1555 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1556 1557 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype); 1558 1559 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) 1560 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) 1561 : 0; 1562 #ifdef I40E_FCOE 1563 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) { 1564 dev_kfree_skb_any(skb); 1565 goto next_desc; 1566 } 1567 #endif 1568 i40e_receive_skb(rx_ring, skb, vlan_tag); 1569 1570 rx_ring->netdev->last_rx = jiffies; 1571 budget--; 1572 next_desc: 1573 rx_desc->wb.qword1.status_error_len = 0; 1574 if (!budget) 1575 break; 1576 1577 cleaned_count++; 1578 /* return some buffers to hardware, one at a time is too slow */ 1579 if (cleaned_count >= I40E_RX_BUFFER_WRITE) { 1580 i40e_alloc_rx_buffers(rx_ring, cleaned_count); 1581 cleaned_count = 0; 1582 } 1583 1584 /* use prefetched values */ 1585 rx_desc = next_rxd; 1586 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1587 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1588 I40E_RXD_QW1_STATUS_SHIFT; 1589 } 1590 1591 rx_ring->next_to_clean = i; 1592 u64_stats_update_begin(&rx_ring->syncp); 1593 rx_ring->stats.packets += total_rx_packets; 1594 rx_ring->stats.bytes += total_rx_bytes; 1595 u64_stats_update_end(&rx_ring->syncp); 1596 rx_ring->q_vector->rx.total_packets += total_rx_packets; 1597 rx_ring->q_vector->rx.total_bytes += total_rx_bytes; 1598 1599 if (cleaned_count) 1600 i40e_alloc_rx_buffers(rx_ring, cleaned_count); 1601 1602 return budget > 0; 1603 } 1604 1605 /** 1606 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine 1607 * @napi: napi struct with our devices info in it 1608 * @budget: amount of work driver is allowed to do this pass, in packets 1609 * 1610 * This function will clean all queues associated with a q_vector. 1611 * 1612 * Returns the amount of work done 1613 **/ 1614 int i40e_napi_poll(struct napi_struct *napi, int budget) 1615 { 1616 struct i40e_q_vector *q_vector = 1617 container_of(napi, struct i40e_q_vector, napi); 1618 struct i40e_vsi *vsi = q_vector->vsi; 1619 struct i40e_ring *ring; 1620 bool clean_complete = true; 1621 bool arm_wb = false; 1622 int budget_per_ring; 1623 1624 if (test_bit(__I40E_DOWN, &vsi->state)) { 1625 napi_complete(napi); 1626 return 0; 1627 } 1628 1629 /* Since the actual Tx work is minimal, we can give the Tx a larger 1630 * budget and be more aggressive about cleaning up the Tx descriptors. 1631 */ 1632 i40e_for_each_ring(ring, q_vector->tx) { 1633 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit); 1634 arm_wb |= ring->arm_wb; 1635 } 1636 1637 /* We attempt to distribute budget to each Rx queue fairly, but don't 1638 * allow the budget to go below 1 because that would exit polling early. 1639 */ 1640 budget_per_ring = max(budget/q_vector->num_ringpairs, 1); 1641 1642 i40e_for_each_ring(ring, q_vector->rx) 1643 clean_complete &= i40e_clean_rx_irq(ring, budget_per_ring); 1644 1645 /* If work not completed, return budget and polling will return */ 1646 if (!clean_complete) { 1647 if (arm_wb) 1648 i40e_force_wb(vsi, q_vector); 1649 return budget; 1650 } 1651 1652 /* Work is done so exit the polling mode and re-enable the interrupt */ 1653 napi_complete(napi); 1654 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) || 1655 ITR_IS_DYNAMIC(vsi->tx_itr_setting)) 1656 i40e_update_dynamic_itr(q_vector); 1657 1658 if (!test_bit(__I40E_DOWN, &vsi->state)) { 1659 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { 1660 i40e_irq_dynamic_enable(vsi, 1661 q_vector->v_idx + vsi->base_vector); 1662 } else { 1663 struct i40e_hw *hw = &vsi->back->hw; 1664 /* We re-enable the queue 0 cause, but 1665 * don't worry about dynamic_enable 1666 * because we left it on for the other 1667 * possible interrupts during napi 1668 */ 1669 u32 qval = rd32(hw, I40E_QINT_RQCTL(0)); 1670 qval |= I40E_QINT_RQCTL_CAUSE_ENA_MASK; 1671 wr32(hw, I40E_QINT_RQCTL(0), qval); 1672 1673 qval = rd32(hw, I40E_QINT_TQCTL(0)); 1674 qval |= I40E_QINT_TQCTL_CAUSE_ENA_MASK; 1675 wr32(hw, I40E_QINT_TQCTL(0), qval); 1676 1677 i40e_irq_dynamic_enable_icr0(vsi->back); 1678 } 1679 } 1680 1681 return 0; 1682 } 1683 1684 /** 1685 * i40e_atr - Add a Flow Director ATR filter 1686 * @tx_ring: ring to add programming descriptor to 1687 * @skb: send buffer 1688 * @flags: send flags 1689 * @protocol: wire protocol 1690 **/ 1691 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, 1692 u32 flags, __be16 protocol) 1693 { 1694 struct i40e_filter_program_desc *fdir_desc; 1695 struct i40e_pf *pf = tx_ring->vsi->back; 1696 union { 1697 unsigned char *network; 1698 struct iphdr *ipv4; 1699 struct ipv6hdr *ipv6; 1700 } hdr; 1701 struct tcphdr *th; 1702 unsigned int hlen; 1703 u32 flex_ptype, dtype_cmd; 1704 u16 i; 1705 1706 /* make sure ATR is enabled */ 1707 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED)) 1708 return; 1709 1710 /* if sampling is disabled do nothing */ 1711 if (!tx_ring->atr_sample_rate) 1712 return; 1713 1714 /* snag network header to get L4 type and address */ 1715 hdr.network = skb_network_header(skb); 1716 1717 /* Currently only IPv4/IPv6 with TCP is supported */ 1718 if (protocol == htons(ETH_P_IP)) { 1719 if (hdr.ipv4->protocol != IPPROTO_TCP) 1720 return; 1721 1722 /* access ihl as a u8 to avoid unaligned access on ia64 */ 1723 hlen = (hdr.network[0] & 0x0F) << 2; 1724 } else if (protocol == htons(ETH_P_IPV6)) { 1725 if (hdr.ipv6->nexthdr != IPPROTO_TCP) 1726 return; 1727 1728 hlen = sizeof(struct ipv6hdr); 1729 } else { 1730 return; 1731 } 1732 1733 th = (struct tcphdr *)(hdr.network + hlen); 1734 1735 /* Due to lack of space, no more new filters can be programmed */ 1736 if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) 1737 return; 1738 1739 tx_ring->atr_count++; 1740 1741 /* sample on all syn/fin/rst packets or once every atr sample rate */ 1742 if (!th->fin && 1743 !th->syn && 1744 !th->rst && 1745 (tx_ring->atr_count < tx_ring->atr_sample_rate)) 1746 return; 1747 1748 tx_ring->atr_count = 0; 1749 1750 /* grab the next descriptor */ 1751 i = tx_ring->next_to_use; 1752 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 1753 1754 i++; 1755 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 1756 1757 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 1758 I40E_TXD_FLTR_QW0_QINDEX_MASK; 1759 flex_ptype |= (protocol == htons(ETH_P_IP)) ? 1760 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << 1761 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : 1762 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << 1763 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 1764 1765 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 1766 1767 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 1768 1769 dtype_cmd |= (th->fin || th->rst) ? 1770 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 1771 I40E_TXD_FLTR_QW1_PCMD_SHIFT) : 1772 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 1773 I40E_TXD_FLTR_QW1_PCMD_SHIFT); 1774 1775 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << 1776 I40E_TXD_FLTR_QW1_DEST_SHIFT; 1777 1778 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << 1779 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; 1780 1781 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 1782 dtype_cmd |= 1783 ((u32)pf->fd_atr_cnt_idx << I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 1784 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 1785 1786 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); 1787 fdir_desc->rsvd = cpu_to_le32(0); 1788 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); 1789 fdir_desc->fd_id = cpu_to_le32(0); 1790 } 1791 1792 /** 1793 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW 1794 * @skb: send buffer 1795 * @tx_ring: ring to send buffer on 1796 * @flags: the tx flags to be set 1797 * 1798 * Checks the skb and set up correspondingly several generic transmit flags 1799 * related to VLAN tagging for the HW, such as VLAN, DCB, etc. 1800 * 1801 * Returns error code indicate the frame should be dropped upon error and the 1802 * otherwise returns 0 to indicate the flags has been set properly. 1803 **/ 1804 #ifdef I40E_FCOE 1805 int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 1806 struct i40e_ring *tx_ring, 1807 u32 *flags) 1808 #else 1809 static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 1810 struct i40e_ring *tx_ring, 1811 u32 *flags) 1812 #endif 1813 { 1814 __be16 protocol = skb->protocol; 1815 u32 tx_flags = 0; 1816 1817 /* if we have a HW VLAN tag being added, default to the HW one */ 1818 if (vlan_tx_tag_present(skb)) { 1819 tx_flags |= vlan_tx_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; 1820 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 1821 /* else if it is a SW VLAN, check the next protocol and store the tag */ 1822 } else if (protocol == htons(ETH_P_8021Q)) { 1823 struct vlan_hdr *vhdr, _vhdr; 1824 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 1825 if (!vhdr) 1826 return -EINVAL; 1827 1828 protocol = vhdr->h_vlan_encapsulated_proto; 1829 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; 1830 tx_flags |= I40E_TX_FLAGS_SW_VLAN; 1831 } 1832 1833 /* Insert 802.1p priority into VLAN header */ 1834 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || 1835 (skb->priority != TC_PRIO_CONTROL)) { 1836 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; 1837 tx_flags |= (skb->priority & 0x7) << 1838 I40E_TX_FLAGS_VLAN_PRIO_SHIFT; 1839 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { 1840 struct vlan_ethhdr *vhdr; 1841 int rc; 1842 1843 rc = skb_cow_head(skb, 0); 1844 if (rc < 0) 1845 return rc; 1846 vhdr = (struct vlan_ethhdr *)skb->data; 1847 vhdr->h_vlan_TCI = htons(tx_flags >> 1848 I40E_TX_FLAGS_VLAN_SHIFT); 1849 } else { 1850 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 1851 } 1852 } 1853 *flags = tx_flags; 1854 return 0; 1855 } 1856 1857 /** 1858 * i40e_tso - set up the tso context descriptor 1859 * @tx_ring: ptr to the ring to send 1860 * @skb: ptr to the skb we're sending 1861 * @tx_flags: the collected send information 1862 * @protocol: the send protocol 1863 * @hdr_len: ptr to the size of the packet header 1864 * @cd_tunneling: ptr to context descriptor bits 1865 * 1866 * Returns 0 if no TSO can happen, 1 if tso is going, or error 1867 **/ 1868 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb, 1869 u32 tx_flags, __be16 protocol, u8 *hdr_len, 1870 u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling) 1871 { 1872 u32 cd_cmd, cd_tso_len, cd_mss; 1873 struct ipv6hdr *ipv6h; 1874 struct tcphdr *tcph; 1875 struct iphdr *iph; 1876 u32 l4len; 1877 int err; 1878 1879 if (!skb_is_gso(skb)) 1880 return 0; 1881 1882 err = skb_cow_head(skb, 0); 1883 if (err < 0) 1884 return err; 1885 1886 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb); 1887 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb); 1888 1889 if (iph->version == 4) { 1890 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1891 iph->tot_len = 0; 1892 iph->check = 0; 1893 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 1894 0, IPPROTO_TCP, 0); 1895 } else if (ipv6h->version == 6) { 1896 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1897 ipv6h->payload_len = 0; 1898 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 1899 0, IPPROTO_TCP, 0); 1900 } 1901 1902 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb); 1903 *hdr_len = (skb->encapsulation 1904 ? (skb_inner_transport_header(skb) - skb->data) 1905 : skb_transport_offset(skb)) + l4len; 1906 1907 /* find the field values */ 1908 cd_cmd = I40E_TX_CTX_DESC_TSO; 1909 cd_tso_len = skb->len - *hdr_len; 1910 cd_mss = skb_shinfo(skb)->gso_size; 1911 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | 1912 ((u64)cd_tso_len << 1913 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | 1914 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); 1915 return 1; 1916 } 1917 1918 /** 1919 * i40e_tsyn - set up the tsyn context descriptor 1920 * @tx_ring: ptr to the ring to send 1921 * @skb: ptr to the skb we're sending 1922 * @tx_flags: the collected send information 1923 * 1924 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen 1925 **/ 1926 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, 1927 u32 tx_flags, u64 *cd_type_cmd_tso_mss) 1928 { 1929 struct i40e_pf *pf; 1930 1931 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) 1932 return 0; 1933 1934 /* Tx timestamps cannot be sampled when doing TSO */ 1935 if (tx_flags & I40E_TX_FLAGS_TSO) 1936 return 0; 1937 1938 /* only timestamp the outbound packet if the user has requested it and 1939 * we are not already transmitting a packet to be timestamped 1940 */ 1941 pf = i40e_netdev_to_pf(tx_ring->netdev); 1942 if (pf->ptp_tx && 1943 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) { 1944 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1945 pf->ptp_tx_skb = skb_get(skb); 1946 } else { 1947 return 0; 1948 } 1949 1950 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << 1951 I40E_TXD_CTX_QW1_CMD_SHIFT; 1952 1953 return 1; 1954 } 1955 1956 /** 1957 * i40e_tx_enable_csum - Enable Tx checksum offloads 1958 * @skb: send buffer 1959 * @tx_flags: Tx flags currently set 1960 * @td_cmd: Tx descriptor command bits to set 1961 * @td_offset: Tx descriptor header offsets to set 1962 * @cd_tunneling: ptr to context desc bits 1963 **/ 1964 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags, 1965 u32 *td_cmd, u32 *td_offset, 1966 struct i40e_ring *tx_ring, 1967 u32 *cd_tunneling) 1968 { 1969 struct ipv6hdr *this_ipv6_hdr; 1970 unsigned int this_tcp_hdrlen; 1971 struct iphdr *this_ip_hdr; 1972 u32 network_hdr_len; 1973 u8 l4_hdr = 0; 1974 1975 if (skb->encapsulation) { 1976 network_hdr_len = skb_inner_network_header_len(skb); 1977 this_ip_hdr = inner_ip_hdr(skb); 1978 this_ipv6_hdr = inner_ipv6_hdr(skb); 1979 this_tcp_hdrlen = inner_tcp_hdrlen(skb); 1980 1981 if (tx_flags & I40E_TX_FLAGS_IPV4) { 1982 1983 if (tx_flags & I40E_TX_FLAGS_TSO) { 1984 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4; 1985 ip_hdr(skb)->check = 0; 1986 } else { 1987 *cd_tunneling |= 1988 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; 1989 } 1990 } else if (tx_flags & I40E_TX_FLAGS_IPV6) { 1991 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6; 1992 if (tx_flags & I40E_TX_FLAGS_TSO) 1993 ip_hdr(skb)->check = 0; 1994 } 1995 1996 /* Now set the ctx descriptor fields */ 1997 *cd_tunneling |= (skb_network_header_len(skb) >> 2) << 1998 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT | 1999 I40E_TXD_CTX_UDP_TUNNELING | 2000 ((skb_inner_network_offset(skb) - 2001 skb_transport_offset(skb)) >> 1) << 2002 I40E_TXD_CTX_QW0_NATLEN_SHIFT; 2003 if (this_ip_hdr->version == 6) { 2004 tx_flags &= ~I40E_TX_FLAGS_IPV4; 2005 tx_flags |= I40E_TX_FLAGS_IPV6; 2006 } 2007 } else { 2008 network_hdr_len = skb_network_header_len(skb); 2009 this_ip_hdr = ip_hdr(skb); 2010 this_ipv6_hdr = ipv6_hdr(skb); 2011 this_tcp_hdrlen = tcp_hdrlen(skb); 2012 } 2013 2014 /* Enable IP checksum offloads */ 2015 if (tx_flags & I40E_TX_FLAGS_IPV4) { 2016 l4_hdr = this_ip_hdr->protocol; 2017 /* the stack computes the IP header already, the only time we 2018 * need the hardware to recompute it is in the case of TSO. 2019 */ 2020 if (tx_flags & I40E_TX_FLAGS_TSO) { 2021 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM; 2022 this_ip_hdr->check = 0; 2023 } else { 2024 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4; 2025 } 2026 /* Now set the td_offset for IP header length */ 2027 *td_offset = (network_hdr_len >> 2) << 2028 I40E_TX_DESC_LENGTH_IPLEN_SHIFT; 2029 } else if (tx_flags & I40E_TX_FLAGS_IPV6) { 2030 l4_hdr = this_ipv6_hdr->nexthdr; 2031 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; 2032 /* Now set the td_offset for IP header length */ 2033 *td_offset = (network_hdr_len >> 2) << 2034 I40E_TX_DESC_LENGTH_IPLEN_SHIFT; 2035 } 2036 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */ 2037 *td_offset |= (skb_network_offset(skb) >> 1) << 2038 I40E_TX_DESC_LENGTH_MACLEN_SHIFT; 2039 2040 /* Enable L4 checksum offloads */ 2041 switch (l4_hdr) { 2042 case IPPROTO_TCP: 2043 /* enable checksum offloads */ 2044 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; 2045 *td_offset |= (this_tcp_hdrlen >> 2) << 2046 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2047 break; 2048 case IPPROTO_SCTP: 2049 /* enable SCTP checksum offload */ 2050 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; 2051 *td_offset |= (sizeof(struct sctphdr) >> 2) << 2052 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2053 break; 2054 case IPPROTO_UDP: 2055 /* enable UDP checksum offload */ 2056 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; 2057 *td_offset |= (sizeof(struct udphdr) >> 2) << 2058 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2059 break; 2060 default: 2061 break; 2062 } 2063 } 2064 2065 /** 2066 * i40e_create_tx_ctx Build the Tx context descriptor 2067 * @tx_ring: ring to create the descriptor on 2068 * @cd_type_cmd_tso_mss: Quad Word 1 2069 * @cd_tunneling: Quad Word 0 - bits 0-31 2070 * @cd_l2tag2: Quad Word 0 - bits 32-63 2071 **/ 2072 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, 2073 const u64 cd_type_cmd_tso_mss, 2074 const u32 cd_tunneling, const u32 cd_l2tag2) 2075 { 2076 struct i40e_tx_context_desc *context_desc; 2077 int i = tx_ring->next_to_use; 2078 2079 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && 2080 !cd_tunneling && !cd_l2tag2) 2081 return; 2082 2083 /* grab the next descriptor */ 2084 context_desc = I40E_TX_CTXTDESC(tx_ring, i); 2085 2086 i++; 2087 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2088 2089 /* cpu_to_le32 and assign to struct fields */ 2090 context_desc->tunneling_params = cpu_to_le32(cd_tunneling); 2091 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); 2092 context_desc->rsvd = cpu_to_le16(0); 2093 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); 2094 } 2095 2096 /** 2097 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions 2098 * @tx_ring: the ring to be checked 2099 * @size: the size buffer we want to assure is available 2100 * 2101 * Returns -EBUSY if a stop is needed, else 0 2102 **/ 2103 static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 2104 { 2105 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 2106 /* Memory barrier before checking head and tail */ 2107 smp_mb(); 2108 2109 /* Check again in a case another CPU has just made room available. */ 2110 if (likely(I40E_DESC_UNUSED(tx_ring) < size)) 2111 return -EBUSY; 2112 2113 /* A reprieve! - use start_queue because it doesn't call schedule */ 2114 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 2115 ++tx_ring->tx_stats.restart_queue; 2116 return 0; 2117 } 2118 2119 /** 2120 * i40e_maybe_stop_tx - 1st level check for tx stop conditions 2121 * @tx_ring: the ring to be checked 2122 * @size: the size buffer we want to assure is available 2123 * 2124 * Returns 0 if stop is not needed 2125 **/ 2126 #ifdef I40E_FCOE 2127 int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 2128 #else 2129 static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 2130 #endif 2131 { 2132 if (likely(I40E_DESC_UNUSED(tx_ring) >= size)) 2133 return 0; 2134 return __i40e_maybe_stop_tx(tx_ring, size); 2135 } 2136 2137 /** 2138 * i40e_tx_map - Build the Tx descriptor 2139 * @tx_ring: ring to send buffer on 2140 * @skb: send buffer 2141 * @first: first buffer info buffer to use 2142 * @tx_flags: collected send information 2143 * @hdr_len: size of the packet header 2144 * @td_cmd: the command field in the descriptor 2145 * @td_offset: offset for checksum or crc 2146 **/ 2147 #ifdef I40E_FCOE 2148 void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 2149 struct i40e_tx_buffer *first, u32 tx_flags, 2150 const u8 hdr_len, u32 td_cmd, u32 td_offset) 2151 #else 2152 static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 2153 struct i40e_tx_buffer *first, u32 tx_flags, 2154 const u8 hdr_len, u32 td_cmd, u32 td_offset) 2155 #endif 2156 { 2157 unsigned int data_len = skb->data_len; 2158 unsigned int size = skb_headlen(skb); 2159 struct skb_frag_struct *frag; 2160 struct i40e_tx_buffer *tx_bi; 2161 struct i40e_tx_desc *tx_desc; 2162 u16 i = tx_ring->next_to_use; 2163 u32 td_tag = 0; 2164 dma_addr_t dma; 2165 u16 gso_segs; 2166 2167 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { 2168 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; 2169 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> 2170 I40E_TX_FLAGS_VLAN_SHIFT; 2171 } 2172 2173 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) 2174 gso_segs = skb_shinfo(skb)->gso_segs; 2175 else 2176 gso_segs = 1; 2177 2178 /* multiply data chunks by size of headers */ 2179 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len); 2180 first->gso_segs = gso_segs; 2181 first->skb = skb; 2182 first->tx_flags = tx_flags; 2183 2184 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 2185 2186 tx_desc = I40E_TX_DESC(tx_ring, i); 2187 tx_bi = first; 2188 2189 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 2190 if (dma_mapping_error(tx_ring->dev, dma)) 2191 goto dma_error; 2192 2193 /* record length, and DMA address */ 2194 dma_unmap_len_set(tx_bi, len, size); 2195 dma_unmap_addr_set(tx_bi, dma, dma); 2196 2197 tx_desc->buffer_addr = cpu_to_le64(dma); 2198 2199 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { 2200 tx_desc->cmd_type_offset_bsz = 2201 build_ctob(td_cmd, td_offset, 2202 I40E_MAX_DATA_PER_TXD, td_tag); 2203 2204 tx_desc++; 2205 i++; 2206 if (i == tx_ring->count) { 2207 tx_desc = I40E_TX_DESC(tx_ring, 0); 2208 i = 0; 2209 } 2210 2211 dma += I40E_MAX_DATA_PER_TXD; 2212 size -= I40E_MAX_DATA_PER_TXD; 2213 2214 tx_desc->buffer_addr = cpu_to_le64(dma); 2215 } 2216 2217 if (likely(!data_len)) 2218 break; 2219 2220 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, 2221 size, td_tag); 2222 2223 tx_desc++; 2224 i++; 2225 if (i == tx_ring->count) { 2226 tx_desc = I40E_TX_DESC(tx_ring, 0); 2227 i = 0; 2228 } 2229 2230 size = skb_frag_size(frag); 2231 data_len -= size; 2232 2233 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 2234 DMA_TO_DEVICE); 2235 2236 tx_bi = &tx_ring->tx_bi[i]; 2237 } 2238 2239 /* Place RS bit on last descriptor of any packet that spans across the 2240 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline. 2241 */ 2242 if (((i & WB_STRIDE) != WB_STRIDE) && 2243 (first <= &tx_ring->tx_bi[i]) && 2244 (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) { 2245 tx_desc->cmd_type_offset_bsz = 2246 build_ctob(td_cmd, td_offset, size, td_tag) | 2247 cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP << 2248 I40E_TXD_QW1_CMD_SHIFT); 2249 } else { 2250 tx_desc->cmd_type_offset_bsz = 2251 build_ctob(td_cmd, td_offset, size, td_tag) | 2252 cpu_to_le64((u64)I40E_TXD_CMD << 2253 I40E_TXD_QW1_CMD_SHIFT); 2254 } 2255 2256 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev, 2257 tx_ring->queue_index), 2258 first->bytecount); 2259 2260 /* set the timestamp */ 2261 first->time_stamp = jiffies; 2262 2263 /* Force memory writes to complete before letting h/w 2264 * know there are new descriptors to fetch. (Only 2265 * applicable for weak-ordered memory model archs, 2266 * such as IA-64). 2267 */ 2268 wmb(); 2269 2270 /* set next_to_watch value indicating a packet is present */ 2271 first->next_to_watch = tx_desc; 2272 2273 i++; 2274 if (i == tx_ring->count) 2275 i = 0; 2276 2277 tx_ring->next_to_use = i; 2278 2279 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); 2280 /* notify HW of packet */ 2281 if (!skb->xmit_more || 2282 netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev, 2283 tx_ring->queue_index))) 2284 writel(i, tx_ring->tail); 2285 2286 return; 2287 2288 dma_error: 2289 dev_info(tx_ring->dev, "TX DMA map failed\n"); 2290 2291 /* clear dma mappings for failed tx_bi map */ 2292 for (;;) { 2293 tx_bi = &tx_ring->tx_bi[i]; 2294 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); 2295 if (tx_bi == first) 2296 break; 2297 if (i == 0) 2298 i = tx_ring->count; 2299 i--; 2300 } 2301 2302 tx_ring->next_to_use = i; 2303 } 2304 2305 /** 2306 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed 2307 * @skb: send buffer 2308 * @tx_ring: ring to send buffer on 2309 * 2310 * Returns number of data descriptors needed for this skb. Returns 0 to indicate 2311 * there is not enough descriptors available in this ring since we need at least 2312 * one descriptor. 2313 **/ 2314 #ifdef I40E_FCOE 2315 int i40e_xmit_descriptor_count(struct sk_buff *skb, 2316 struct i40e_ring *tx_ring) 2317 #else 2318 static int i40e_xmit_descriptor_count(struct sk_buff *skb, 2319 struct i40e_ring *tx_ring) 2320 #endif 2321 { 2322 unsigned int f; 2323 int count = 0; 2324 2325 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, 2326 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, 2327 * + 4 desc gap to avoid the cache line where head is, 2328 * + 1 desc for context descriptor, 2329 * otherwise try next time 2330 */ 2331 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 2332 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 2333 2334 count += TXD_USE_COUNT(skb_headlen(skb)); 2335 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { 2336 tx_ring->tx_stats.tx_busy++; 2337 return 0; 2338 } 2339 return count; 2340 } 2341 2342 /** 2343 * i40e_xmit_frame_ring - Sends buffer on Tx ring 2344 * @skb: send buffer 2345 * @tx_ring: ring to send buffer on 2346 * 2347 * Returns NETDEV_TX_OK if sent, else an error code 2348 **/ 2349 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, 2350 struct i40e_ring *tx_ring) 2351 { 2352 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; 2353 u32 cd_tunneling = 0, cd_l2tag2 = 0; 2354 struct i40e_tx_buffer *first; 2355 u32 td_offset = 0; 2356 u32 tx_flags = 0; 2357 __be16 protocol; 2358 u32 td_cmd = 0; 2359 u8 hdr_len = 0; 2360 int tsyn; 2361 int tso; 2362 if (0 == i40e_xmit_descriptor_count(skb, tx_ring)) 2363 return NETDEV_TX_BUSY; 2364 2365 /* prepare the xmit flags */ 2366 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) 2367 goto out_drop; 2368 2369 /* obtain protocol of skb */ 2370 protocol = vlan_get_protocol(skb); 2371 2372 /* record the location of the first descriptor for this packet */ 2373 first = &tx_ring->tx_bi[tx_ring->next_to_use]; 2374 2375 /* setup IPv4/IPv6 offloads */ 2376 if (protocol == htons(ETH_P_IP)) 2377 tx_flags |= I40E_TX_FLAGS_IPV4; 2378 else if (protocol == htons(ETH_P_IPV6)) 2379 tx_flags |= I40E_TX_FLAGS_IPV6; 2380 2381 tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len, 2382 &cd_type_cmd_tso_mss, &cd_tunneling); 2383 2384 if (tso < 0) 2385 goto out_drop; 2386 else if (tso) 2387 tx_flags |= I40E_TX_FLAGS_TSO; 2388 2389 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); 2390 2391 if (tsyn) 2392 tx_flags |= I40E_TX_FLAGS_TSYN; 2393 2394 skb_tx_timestamp(skb); 2395 2396 /* always enable CRC insertion offload */ 2397 td_cmd |= I40E_TX_DESC_CMD_ICRC; 2398 2399 /* Always offload the checksum, since it's in the data descriptor */ 2400 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2401 tx_flags |= I40E_TX_FLAGS_CSUM; 2402 2403 i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset, 2404 tx_ring, &cd_tunneling); 2405 } 2406 2407 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, 2408 cd_tunneling, cd_l2tag2); 2409 2410 /* Add Flow Director ATR if it's enabled. 2411 * 2412 * NOTE: this must always be directly before the data descriptor. 2413 */ 2414 i40e_atr(tx_ring, skb, tx_flags, protocol); 2415 2416 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, 2417 td_cmd, td_offset); 2418 2419 return NETDEV_TX_OK; 2420 2421 out_drop: 2422 dev_kfree_skb_any(skb); 2423 return NETDEV_TX_OK; 2424 } 2425 2426 /** 2427 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer 2428 * @skb: send buffer 2429 * @netdev: network interface device structure 2430 * 2431 * Returns NETDEV_TX_OK if sent, else an error code 2432 **/ 2433 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 2434 { 2435 struct i40e_netdev_priv *np = netdev_priv(netdev); 2436 struct i40e_vsi *vsi = np->vsi; 2437 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; 2438 2439 /* hardware can't handle really short frames, hardware padding works 2440 * beyond this point 2441 */ 2442 if (skb_put_padto(skb, I40E_MIN_TX_LEN)) 2443 return NETDEV_TX_OK; 2444 2445 return i40e_xmit_frame_ring(skb, tx_ring); 2446 } 2447