1 /******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27 #include <linux/prefetch.h> 28 #include <net/busy_poll.h> 29 #include "i40e.h" 30 #include "i40e_prototype.h" 31 32 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, 33 u32 td_tag) 34 { 35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | 36 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | 37 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | 38 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | 39 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); 40 } 41 42 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) 43 #define I40E_FD_CLEAN_DELAY 10 44 /** 45 * i40e_program_fdir_filter - Program a Flow Director filter 46 * @fdir_data: Packet data that will be filter parameters 47 * @raw_packet: the pre-allocated packet buffer for FDir 48 * @pf: The PF pointer 49 * @add: True for add/update, False for remove 50 **/ 51 int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet, 52 struct i40e_pf *pf, bool add) 53 { 54 struct i40e_filter_program_desc *fdir_desc; 55 struct i40e_tx_buffer *tx_buf, *first; 56 struct i40e_tx_desc *tx_desc; 57 struct i40e_ring *tx_ring; 58 unsigned int fpt, dcc; 59 struct i40e_vsi *vsi; 60 struct device *dev; 61 dma_addr_t dma; 62 u32 td_cmd = 0; 63 u16 delay = 0; 64 u16 i; 65 66 /* find existing FDIR VSI */ 67 vsi = NULL; 68 for (i = 0; i < pf->num_alloc_vsi; i++) 69 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) 70 vsi = pf->vsi[i]; 71 if (!vsi) 72 return -ENOENT; 73 74 tx_ring = vsi->tx_rings[0]; 75 dev = tx_ring->dev; 76 77 /* we need two descriptors to add/del a filter and we can wait */ 78 do { 79 if (I40E_DESC_UNUSED(tx_ring) > 1) 80 break; 81 msleep_interruptible(1); 82 delay++; 83 } while (delay < I40E_FD_CLEAN_DELAY); 84 85 if (!(I40E_DESC_UNUSED(tx_ring) > 1)) 86 return -EAGAIN; 87 88 dma = dma_map_single(dev, raw_packet, 89 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE); 90 if (dma_mapping_error(dev, dma)) 91 goto dma_fail; 92 93 /* grab the next descriptor */ 94 i = tx_ring->next_to_use; 95 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 96 first = &tx_ring->tx_bi[i]; 97 memset(first, 0, sizeof(struct i40e_tx_buffer)); 98 99 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; 100 101 fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 102 I40E_TXD_FLTR_QW0_QINDEX_MASK; 103 104 fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) & 105 I40E_TXD_FLTR_QW0_FLEXOFF_MASK; 106 107 fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) & 108 I40E_TXD_FLTR_QW0_PCTYPE_MASK; 109 110 /* Use LAN VSI Id if not programmed by user */ 111 if (fdir_data->dest_vsi == 0) 112 fpt |= (pf->vsi[pf->lan_vsi]->id) << 113 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 114 else 115 fpt |= ((u32)fdir_data->dest_vsi << 116 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) & 117 I40E_TXD_FLTR_QW0_DEST_VSI_MASK; 118 119 dcc = I40E_TX_DESC_DTYPE_FILTER_PROG; 120 121 if (add) 122 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 123 I40E_TXD_FLTR_QW1_PCMD_SHIFT; 124 else 125 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 126 I40E_TXD_FLTR_QW1_PCMD_SHIFT; 127 128 dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) & 129 I40E_TXD_FLTR_QW1_DEST_MASK; 130 131 dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) & 132 I40E_TXD_FLTR_QW1_FD_STATUS_MASK; 133 134 if (fdir_data->cnt_index != 0) { 135 dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 136 dcc |= ((u32)fdir_data->cnt_index << 137 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 138 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 139 } 140 141 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt); 142 fdir_desc->rsvd = cpu_to_le32(0); 143 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc); 144 fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id); 145 146 /* Now program a dummy descriptor */ 147 i = tx_ring->next_to_use; 148 tx_desc = I40E_TX_DESC(tx_ring, i); 149 tx_buf = &tx_ring->tx_bi[i]; 150 151 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0; 152 153 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer)); 154 155 /* record length, and DMA address */ 156 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE); 157 dma_unmap_addr_set(tx_buf, dma, dma); 158 159 tx_desc->buffer_addr = cpu_to_le64(dma); 160 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY; 161 162 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB; 163 tx_buf->raw_buf = (void *)raw_packet; 164 165 tx_desc->cmd_type_offset_bsz = 166 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0); 167 168 /* Force memory writes to complete before letting h/w 169 * know there are new descriptors to fetch. 170 */ 171 wmb(); 172 173 /* Mark the data descriptor to be watched */ 174 first->next_to_watch = tx_desc; 175 176 writel(tx_ring->next_to_use, tx_ring->tail); 177 return 0; 178 179 dma_fail: 180 return -1; 181 } 182 183 #define IP_HEADER_OFFSET 14 184 #define I40E_UDPIP_DUMMY_PACKET_LEN 42 185 /** 186 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters 187 * @vsi: pointer to the targeted VSI 188 * @fd_data: the flow director data required for the FDir descriptor 189 * @add: true adds a filter, false removes it 190 * 191 * Returns 0 if the filters were successfully added or removed 192 **/ 193 static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi, 194 struct i40e_fdir_filter *fd_data, 195 bool add) 196 { 197 struct i40e_pf *pf = vsi->back; 198 struct udphdr *udp; 199 struct iphdr *ip; 200 bool err = false; 201 u8 *raw_packet; 202 int ret; 203 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 204 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0, 205 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; 206 207 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 208 if (!raw_packet) 209 return -ENOMEM; 210 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN); 211 212 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 213 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET 214 + sizeof(struct iphdr)); 215 216 ip->daddr = fd_data->dst_ip[0]; 217 udp->dest = fd_data->dst_port; 218 ip->saddr = fd_data->src_ip[0]; 219 udp->source = fd_data->src_port; 220 221 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP; 222 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 223 if (ret) { 224 dev_info(&pf->pdev->dev, 225 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 226 fd_data->pctype, fd_data->fd_id, ret); 227 err = true; 228 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 229 if (add) 230 dev_info(&pf->pdev->dev, 231 "Filter OK for PCTYPE %d loc = %d\n", 232 fd_data->pctype, fd_data->fd_id); 233 else 234 dev_info(&pf->pdev->dev, 235 "Filter deleted for PCTYPE %d loc = %d\n", 236 fd_data->pctype, fd_data->fd_id); 237 } 238 return err ? -EOPNOTSUPP : 0; 239 } 240 241 #define I40E_TCPIP_DUMMY_PACKET_LEN 54 242 /** 243 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters 244 * @vsi: pointer to the targeted VSI 245 * @fd_data: the flow director data required for the FDir descriptor 246 * @add: true adds a filter, false removes it 247 * 248 * Returns 0 if the filters were successfully added or removed 249 **/ 250 static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi, 251 struct i40e_fdir_filter *fd_data, 252 bool add) 253 { 254 struct i40e_pf *pf = vsi->back; 255 struct tcphdr *tcp; 256 struct iphdr *ip; 257 bool err = false; 258 u8 *raw_packet; 259 int ret; 260 /* Dummy packet */ 261 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 262 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0, 263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11, 264 0x0, 0x72, 0, 0, 0, 0}; 265 266 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 267 if (!raw_packet) 268 return -ENOMEM; 269 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN); 270 271 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 272 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET 273 + sizeof(struct iphdr)); 274 275 ip->daddr = fd_data->dst_ip[0]; 276 tcp->dest = fd_data->dst_port; 277 ip->saddr = fd_data->src_ip[0]; 278 tcp->source = fd_data->src_port; 279 280 if (add) { 281 pf->fd_tcp_rule++; 282 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) { 283 if (I40E_DEBUG_FD & pf->hw.debug_mask) 284 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n"); 285 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED; 286 } 287 } else { 288 pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ? 289 (pf->fd_tcp_rule - 1) : 0; 290 if (pf->fd_tcp_rule == 0) { 291 pf->flags |= I40E_FLAG_FD_ATR_ENABLED; 292 if (I40E_DEBUG_FD & pf->hw.debug_mask) 293 dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n"); 294 } 295 } 296 297 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP; 298 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 299 300 if (ret) { 301 dev_info(&pf->pdev->dev, 302 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 303 fd_data->pctype, fd_data->fd_id, ret); 304 err = true; 305 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 306 if (add) 307 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n", 308 fd_data->pctype, fd_data->fd_id); 309 else 310 dev_info(&pf->pdev->dev, 311 "Filter deleted for PCTYPE %d loc = %d\n", 312 fd_data->pctype, fd_data->fd_id); 313 } 314 315 return err ? -EOPNOTSUPP : 0; 316 } 317 318 /** 319 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for 320 * a specific flow spec 321 * @vsi: pointer to the targeted VSI 322 * @fd_data: the flow director data required for the FDir descriptor 323 * @add: true adds a filter, false removes it 324 * 325 * Always returns -EOPNOTSUPP 326 **/ 327 static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi, 328 struct i40e_fdir_filter *fd_data, 329 bool add) 330 { 331 return -EOPNOTSUPP; 332 } 333 334 #define I40E_IP_DUMMY_PACKET_LEN 34 335 /** 336 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for 337 * a specific flow spec 338 * @vsi: pointer to the targeted VSI 339 * @fd_data: the flow director data required for the FDir descriptor 340 * @add: true adds a filter, false removes it 341 * 342 * Returns 0 if the filters were successfully added or removed 343 **/ 344 static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi, 345 struct i40e_fdir_filter *fd_data, 346 bool add) 347 { 348 struct i40e_pf *pf = vsi->back; 349 struct iphdr *ip; 350 bool err = false; 351 u8 *raw_packet; 352 int ret; 353 int i; 354 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, 355 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0, 356 0, 0, 0, 0}; 357 358 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; 359 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) { 360 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL); 361 if (!raw_packet) 362 return -ENOMEM; 363 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN); 364 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET); 365 366 ip->saddr = fd_data->src_ip[0]; 367 ip->daddr = fd_data->dst_ip[0]; 368 ip->protocol = 0; 369 370 fd_data->pctype = i; 371 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); 372 373 if (ret) { 374 dev_info(&pf->pdev->dev, 375 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n", 376 fd_data->pctype, fd_data->fd_id, ret); 377 err = true; 378 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) { 379 if (add) 380 dev_info(&pf->pdev->dev, 381 "Filter OK for PCTYPE %d loc = %d\n", 382 fd_data->pctype, fd_data->fd_id); 383 else 384 dev_info(&pf->pdev->dev, 385 "Filter deleted for PCTYPE %d loc = %d\n", 386 fd_data->pctype, fd_data->fd_id); 387 } 388 } 389 390 return err ? -EOPNOTSUPP : 0; 391 } 392 393 /** 394 * i40e_add_del_fdir - Build raw packets to add/del fdir filter 395 * @vsi: pointer to the targeted VSI 396 * @cmd: command to get or set RX flow classification rules 397 * @add: true adds a filter, false removes it 398 * 399 **/ 400 int i40e_add_del_fdir(struct i40e_vsi *vsi, 401 struct i40e_fdir_filter *input, bool add) 402 { 403 struct i40e_pf *pf = vsi->back; 404 int ret; 405 406 switch (input->flow_type & ~FLOW_EXT) { 407 case TCP_V4_FLOW: 408 ret = i40e_add_del_fdir_tcpv4(vsi, input, add); 409 break; 410 case UDP_V4_FLOW: 411 ret = i40e_add_del_fdir_udpv4(vsi, input, add); 412 break; 413 case SCTP_V4_FLOW: 414 ret = i40e_add_del_fdir_sctpv4(vsi, input, add); 415 break; 416 case IPV4_FLOW: 417 ret = i40e_add_del_fdir_ipv4(vsi, input, add); 418 break; 419 case IP_USER_FLOW: 420 switch (input->ip4_proto) { 421 case IPPROTO_TCP: 422 ret = i40e_add_del_fdir_tcpv4(vsi, input, add); 423 break; 424 case IPPROTO_UDP: 425 ret = i40e_add_del_fdir_udpv4(vsi, input, add); 426 break; 427 case IPPROTO_SCTP: 428 ret = i40e_add_del_fdir_sctpv4(vsi, input, add); 429 break; 430 default: 431 ret = i40e_add_del_fdir_ipv4(vsi, input, add); 432 break; 433 } 434 break; 435 default: 436 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n", 437 input->flow_type); 438 ret = -EINVAL; 439 } 440 441 /* The buffer allocated here is freed by the i40e_clean_tx_ring() */ 442 return ret; 443 } 444 445 /** 446 * i40e_fd_handle_status - check the Programming Status for FD 447 * @rx_ring: the Rx ring for this descriptor 448 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor. 449 * @prog_id: the id originally used for programming 450 * 451 * This is used to verify if the FD programming or invalidation 452 * requested by SW to the HW is successful or not and take actions accordingly. 453 **/ 454 static void i40e_fd_handle_status(struct i40e_ring *rx_ring, 455 union i40e_rx_desc *rx_desc, u8 prog_id) 456 { 457 struct i40e_pf *pf = rx_ring->vsi->back; 458 struct pci_dev *pdev = pf->pdev; 459 u32 fcnt_prog, fcnt_avail; 460 u32 error; 461 u64 qw; 462 463 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 464 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >> 465 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT; 466 467 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) { 468 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) || 469 (I40E_DEBUG_FD & pf->hw.debug_mask)) 470 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n", 471 rx_desc->wb.qword0.hi_dword.fd_id); 472 473 /* Check if the programming error is for ATR. 474 * If so, auto disable ATR and set a state for 475 * flush in progress. Next time we come here if flush is in 476 * progress do nothing, once flush is complete the state will 477 * be cleared. 478 */ 479 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state)) 480 return; 481 482 pf->fd_add_err++; 483 /* store the current atr filter count */ 484 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf); 485 486 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) && 487 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) { 488 pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED; 489 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state); 490 } 491 492 /* filter programming failed most likely due to table full */ 493 fcnt_prog = i40e_get_global_fd_count(pf); 494 fcnt_avail = pf->fdir_pf_filter_count; 495 /* If ATR is running fcnt_prog can quickly change, 496 * if we are very close to full, it makes sense to disable 497 * FD ATR/SB and then re-enable it when there is room. 498 */ 499 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) { 500 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && 501 !(pf->auto_disable_flags & 502 I40E_FLAG_FD_SB_ENABLED)) { 503 if (I40E_DEBUG_FD & pf->hw.debug_mask) 504 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n"); 505 pf->auto_disable_flags |= 506 I40E_FLAG_FD_SB_ENABLED; 507 } 508 } else { 509 dev_info(&pdev->dev, 510 "FD filter programming failed due to incorrect filter parameters\n"); 511 } 512 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) { 513 if (I40E_DEBUG_FD & pf->hw.debug_mask) 514 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n", 515 rx_desc->wb.qword0.hi_dword.fd_id); 516 } 517 } 518 519 /** 520 * i40e_unmap_and_free_tx_resource - Release a Tx buffer 521 * @ring: the ring that owns the buffer 522 * @tx_buffer: the buffer to free 523 **/ 524 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, 525 struct i40e_tx_buffer *tx_buffer) 526 { 527 if (tx_buffer->skb) { 528 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) 529 kfree(tx_buffer->raw_buf); 530 else 531 dev_kfree_skb_any(tx_buffer->skb); 532 533 if (dma_unmap_len(tx_buffer, len)) 534 dma_unmap_single(ring->dev, 535 dma_unmap_addr(tx_buffer, dma), 536 dma_unmap_len(tx_buffer, len), 537 DMA_TO_DEVICE); 538 } else if (dma_unmap_len(tx_buffer, len)) { 539 dma_unmap_page(ring->dev, 540 dma_unmap_addr(tx_buffer, dma), 541 dma_unmap_len(tx_buffer, len), 542 DMA_TO_DEVICE); 543 } 544 tx_buffer->next_to_watch = NULL; 545 tx_buffer->skb = NULL; 546 dma_unmap_len_set(tx_buffer, len, 0); 547 /* tx_buffer must be completely set up in the transmit path */ 548 } 549 550 /** 551 * i40e_clean_tx_ring - Free any empty Tx buffers 552 * @tx_ring: ring to be cleaned 553 **/ 554 void i40e_clean_tx_ring(struct i40e_ring *tx_ring) 555 { 556 unsigned long bi_size; 557 u16 i; 558 559 /* ring already cleared, nothing to do */ 560 if (!tx_ring->tx_bi) 561 return; 562 563 /* Free all the Tx ring sk_buffs */ 564 for (i = 0; i < tx_ring->count; i++) 565 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); 566 567 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 568 memset(tx_ring->tx_bi, 0, bi_size); 569 570 /* Zero out the descriptor ring */ 571 memset(tx_ring->desc, 0, tx_ring->size); 572 573 tx_ring->next_to_use = 0; 574 tx_ring->next_to_clean = 0; 575 576 if (!tx_ring->netdev) 577 return; 578 579 /* cleanup Tx queue statistics */ 580 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev, 581 tx_ring->queue_index)); 582 } 583 584 /** 585 * i40e_free_tx_resources - Free Tx resources per queue 586 * @tx_ring: Tx descriptor ring for a specific queue 587 * 588 * Free all transmit software resources 589 **/ 590 void i40e_free_tx_resources(struct i40e_ring *tx_ring) 591 { 592 i40e_clean_tx_ring(tx_ring); 593 kfree(tx_ring->tx_bi); 594 tx_ring->tx_bi = NULL; 595 596 if (tx_ring->desc) { 597 dma_free_coherent(tx_ring->dev, tx_ring->size, 598 tx_ring->desc, tx_ring->dma); 599 tx_ring->desc = NULL; 600 } 601 } 602 603 /** 604 * i40e_get_head - Retrieve head from head writeback 605 * @tx_ring: tx ring to fetch head of 606 * 607 * Returns value of Tx ring head based on value stored 608 * in head write-back location 609 **/ 610 static inline u32 i40e_get_head(struct i40e_ring *tx_ring) 611 { 612 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count; 613 614 return le32_to_cpu(*(volatile __le32 *)head); 615 } 616 617 /** 618 * i40e_get_tx_pending - how many tx descriptors not processed 619 * @tx_ring: the ring of descriptors 620 * 621 * Since there is no access to the ring head register 622 * in XL710, we need to use our local copies 623 **/ 624 static u32 i40e_get_tx_pending(struct i40e_ring *ring) 625 { 626 u32 head, tail; 627 628 head = i40e_get_head(ring); 629 tail = readl(ring->tail); 630 631 if (head != tail) 632 return (head < tail) ? 633 tail - head : (tail + ring->count - head); 634 635 return 0; 636 } 637 638 /** 639 * i40e_check_tx_hang - Is there a hang in the Tx queue 640 * @tx_ring: the ring of descriptors 641 **/ 642 static bool i40e_check_tx_hang(struct i40e_ring *tx_ring) 643 { 644 u32 tx_done = tx_ring->stats.packets; 645 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 646 u32 tx_pending = i40e_get_tx_pending(tx_ring); 647 struct i40e_pf *pf = tx_ring->vsi->back; 648 bool ret = false; 649 650 clear_check_for_tx_hang(tx_ring); 651 652 /* Check for a hung queue, but be thorough. This verifies 653 * that a transmit has been completed since the previous 654 * check AND there is at least one packet pending. The 655 * ARMED bit is set to indicate a potential hang. The 656 * bit is cleared if a pause frame is received to remove 657 * false hang detection due to PFC or 802.3x frames. By 658 * requiring this to fail twice we avoid races with 659 * PFC clearing the ARMED bit and conditions where we 660 * run the check_tx_hang logic with a transmit completion 661 * pending but without time to complete it yet. 662 */ 663 if ((tx_done_old == tx_done) && tx_pending) { 664 /* make sure it is true for two checks in a row */ 665 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED, 666 &tx_ring->state); 667 } else if (tx_done_old == tx_done && 668 (tx_pending < I40E_MIN_DESC_PENDING) && (tx_pending > 0)) { 669 if (I40E_DEBUG_FLOW & pf->hw.debug_mask) 670 dev_info(tx_ring->dev, "HW needs some more descs to do a cacheline flush. tx_pending %d, queue %d", 671 tx_pending, tx_ring->queue_index); 672 pf->tx_sluggish_count++; 673 } else { 674 /* update completed stats and disarm the hang check */ 675 tx_ring->tx_stats.tx_done_old = tx_done; 676 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state); 677 } 678 679 return ret; 680 } 681 682 #define WB_STRIDE 0x3 683 684 /** 685 * i40e_clean_tx_irq - Reclaim resources after transmit completes 686 * @tx_ring: tx ring to clean 687 * @budget: how many cleans we're allowed 688 * 689 * Returns true if there's any budget left (e.g. the clean is finished) 690 **/ 691 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget) 692 { 693 u16 i = tx_ring->next_to_clean; 694 struct i40e_tx_buffer *tx_buf; 695 struct i40e_tx_desc *tx_head; 696 struct i40e_tx_desc *tx_desc; 697 unsigned int total_packets = 0; 698 unsigned int total_bytes = 0; 699 700 tx_buf = &tx_ring->tx_bi[i]; 701 tx_desc = I40E_TX_DESC(tx_ring, i); 702 i -= tx_ring->count; 703 704 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring)); 705 706 do { 707 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; 708 709 /* if next_to_watch is not set then there is no work pending */ 710 if (!eop_desc) 711 break; 712 713 /* prevent any other reads prior to eop_desc */ 714 read_barrier_depends(); 715 716 /* we have caught up to head, no work left to do */ 717 if (tx_head == tx_desc) 718 break; 719 720 /* clear next_to_watch to prevent false hangs */ 721 tx_buf->next_to_watch = NULL; 722 723 /* update the statistics for this packet */ 724 total_bytes += tx_buf->bytecount; 725 total_packets += tx_buf->gso_segs; 726 727 /* free the skb */ 728 dev_consume_skb_any(tx_buf->skb); 729 730 /* unmap skb header data */ 731 dma_unmap_single(tx_ring->dev, 732 dma_unmap_addr(tx_buf, dma), 733 dma_unmap_len(tx_buf, len), 734 DMA_TO_DEVICE); 735 736 /* clear tx_buffer data */ 737 tx_buf->skb = NULL; 738 dma_unmap_len_set(tx_buf, len, 0); 739 740 /* unmap remaining buffers */ 741 while (tx_desc != eop_desc) { 742 743 tx_buf++; 744 tx_desc++; 745 i++; 746 if (unlikely(!i)) { 747 i -= tx_ring->count; 748 tx_buf = tx_ring->tx_bi; 749 tx_desc = I40E_TX_DESC(tx_ring, 0); 750 } 751 752 /* unmap any remaining paged data */ 753 if (dma_unmap_len(tx_buf, len)) { 754 dma_unmap_page(tx_ring->dev, 755 dma_unmap_addr(tx_buf, dma), 756 dma_unmap_len(tx_buf, len), 757 DMA_TO_DEVICE); 758 dma_unmap_len_set(tx_buf, len, 0); 759 } 760 } 761 762 /* move us one more past the eop_desc for start of next pkt */ 763 tx_buf++; 764 tx_desc++; 765 i++; 766 if (unlikely(!i)) { 767 i -= tx_ring->count; 768 tx_buf = tx_ring->tx_bi; 769 tx_desc = I40E_TX_DESC(tx_ring, 0); 770 } 771 772 prefetch(tx_desc); 773 774 /* update budget accounting */ 775 budget--; 776 } while (likely(budget)); 777 778 i += tx_ring->count; 779 tx_ring->next_to_clean = i; 780 u64_stats_update_begin(&tx_ring->syncp); 781 tx_ring->stats.bytes += total_bytes; 782 tx_ring->stats.packets += total_packets; 783 u64_stats_update_end(&tx_ring->syncp); 784 tx_ring->q_vector->tx.total_bytes += total_bytes; 785 tx_ring->q_vector->tx.total_packets += total_packets; 786 787 /* check to see if there are any non-cache aligned descriptors 788 * waiting to be written back, and kick the hardware to force 789 * them to be written back in case of napi polling 790 */ 791 if (budget && 792 !((i & WB_STRIDE) == WB_STRIDE) && 793 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) && 794 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) 795 tx_ring->arm_wb = true; 796 else 797 tx_ring->arm_wb = false; 798 799 if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) { 800 /* schedule immediate reset if we believe we hung */ 801 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n" 802 " VSI <%d>\n" 803 " Tx Queue <%d>\n" 804 " next_to_use <%x>\n" 805 " next_to_clean <%x>\n", 806 tx_ring->vsi->seid, 807 tx_ring->queue_index, 808 tx_ring->next_to_use, i); 809 810 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 811 812 dev_info(tx_ring->dev, 813 "tx hang detected on queue %d, reset requested\n", 814 tx_ring->queue_index); 815 816 /* do not fire the reset immediately, wait for the stack to 817 * decide we are truly stuck, also prevents every queue from 818 * simultaneously requesting a reset 819 */ 820 821 /* the adapter is about to reset, no point in enabling polling */ 822 budget = 1; 823 } 824 825 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev, 826 tx_ring->queue_index), 827 total_packets, total_bytes); 828 829 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 830 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 831 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { 832 /* Make sure that anybody stopping the queue after this 833 * sees the new next_to_clean. 834 */ 835 smp_mb(); 836 if (__netif_subqueue_stopped(tx_ring->netdev, 837 tx_ring->queue_index) && 838 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) { 839 netif_wake_subqueue(tx_ring->netdev, 840 tx_ring->queue_index); 841 ++tx_ring->tx_stats.restart_queue; 842 } 843 } 844 845 return !!budget; 846 } 847 848 /** 849 * i40e_force_wb - Arm hardware to do a wb on noncache aligned descriptors 850 * @vsi: the VSI we care about 851 * @q_vector: the vector on which to force writeback 852 * 853 **/ 854 static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) 855 { 856 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 857 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */ 858 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK | 859 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK; 860 /* allow 00 to be written to the index */ 861 862 wr32(&vsi->back->hw, 863 I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1), 864 val); 865 } 866 867 /** 868 * i40e_set_new_dynamic_itr - Find new ITR level 869 * @rc: structure containing ring performance data 870 * 871 * Stores a new ITR value based on packets and byte counts during 872 * the last interrupt. The advantage of per interrupt computation 873 * is faster updates and more accurate ITR for the current traffic 874 * pattern. Constants in this function were computed based on 875 * theoretical maximum wire speed and thresholds were set based on 876 * testing data as well as attempting to minimize response time 877 * while increasing bulk throughput. 878 **/ 879 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) 880 { 881 enum i40e_latency_range new_latency_range = rc->latency_range; 882 u32 new_itr = rc->itr; 883 int bytes_per_int; 884 885 if (rc->total_packets == 0 || !rc->itr) 886 return; 887 888 /* simple throttlerate management 889 * 0-10MB/s lowest (100000 ints/s) 890 * 10-20MB/s low (20000 ints/s) 891 * 20-1249MB/s bulk (8000 ints/s) 892 */ 893 bytes_per_int = rc->total_bytes / rc->itr; 894 switch (new_latency_range) { 895 case I40E_LOWEST_LATENCY: 896 if (bytes_per_int > 10) 897 new_latency_range = I40E_LOW_LATENCY; 898 break; 899 case I40E_LOW_LATENCY: 900 if (bytes_per_int > 20) 901 new_latency_range = I40E_BULK_LATENCY; 902 else if (bytes_per_int <= 10) 903 new_latency_range = I40E_LOWEST_LATENCY; 904 break; 905 case I40E_BULK_LATENCY: 906 if (bytes_per_int <= 20) 907 new_latency_range = I40E_LOW_LATENCY; 908 break; 909 default: 910 if (bytes_per_int <= 20) 911 new_latency_range = I40E_LOW_LATENCY; 912 break; 913 } 914 rc->latency_range = new_latency_range; 915 916 switch (new_latency_range) { 917 case I40E_LOWEST_LATENCY: 918 new_itr = I40E_ITR_100K; 919 break; 920 case I40E_LOW_LATENCY: 921 new_itr = I40E_ITR_20K; 922 break; 923 case I40E_BULK_LATENCY: 924 new_itr = I40E_ITR_8K; 925 break; 926 default: 927 break; 928 } 929 930 if (new_itr != rc->itr) 931 rc->itr = new_itr; 932 933 rc->total_bytes = 0; 934 rc->total_packets = 0; 935 } 936 937 /** 938 * i40e_clean_programming_status - clean the programming status descriptor 939 * @rx_ring: the rx ring that has this descriptor 940 * @rx_desc: the rx descriptor written back by HW 941 * 942 * Flow director should handle FD_FILTER_STATUS to check its filter programming 943 * status being successful or not and take actions accordingly. FCoE should 944 * handle its context/filter programming/invalidation status and take actions. 945 * 946 **/ 947 static void i40e_clean_programming_status(struct i40e_ring *rx_ring, 948 union i40e_rx_desc *rx_desc) 949 { 950 u64 qw; 951 u8 id; 952 953 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 954 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >> 955 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT; 956 957 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) 958 i40e_fd_handle_status(rx_ring, rx_desc, id); 959 #ifdef I40E_FCOE 960 else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) || 961 (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS)) 962 i40e_fcoe_handle_status(rx_ring, rx_desc, id); 963 #endif 964 } 965 966 /** 967 * i40e_setup_tx_descriptors - Allocate the Tx descriptors 968 * @tx_ring: the tx ring to set up 969 * 970 * Return 0 on success, negative on error 971 **/ 972 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring) 973 { 974 struct device *dev = tx_ring->dev; 975 int bi_size; 976 977 if (!dev) 978 return -ENOMEM; 979 980 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; 981 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); 982 if (!tx_ring->tx_bi) 983 goto err; 984 985 /* round up to nearest 4K */ 986 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); 987 /* add u32 for head writeback, align after this takes care of 988 * guaranteeing this is at least one cache line in size 989 */ 990 tx_ring->size += sizeof(u32); 991 tx_ring->size = ALIGN(tx_ring->size, 4096); 992 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 993 &tx_ring->dma, GFP_KERNEL); 994 if (!tx_ring->desc) { 995 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", 996 tx_ring->size); 997 goto err; 998 } 999 1000 tx_ring->next_to_use = 0; 1001 tx_ring->next_to_clean = 0; 1002 return 0; 1003 1004 err: 1005 kfree(tx_ring->tx_bi); 1006 tx_ring->tx_bi = NULL; 1007 return -ENOMEM; 1008 } 1009 1010 /** 1011 * i40e_clean_rx_ring - Free Rx buffers 1012 * @rx_ring: ring to be cleaned 1013 **/ 1014 void i40e_clean_rx_ring(struct i40e_ring *rx_ring) 1015 { 1016 struct device *dev = rx_ring->dev; 1017 struct i40e_rx_buffer *rx_bi; 1018 unsigned long bi_size; 1019 u16 i; 1020 1021 /* ring already cleared, nothing to do */ 1022 if (!rx_ring->rx_bi) 1023 return; 1024 1025 if (ring_is_ps_enabled(rx_ring)) { 1026 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count; 1027 1028 rx_bi = &rx_ring->rx_bi[0]; 1029 if (rx_bi->hdr_buf) { 1030 dma_free_coherent(dev, 1031 bufsz, 1032 rx_bi->hdr_buf, 1033 rx_bi->dma); 1034 for (i = 0; i < rx_ring->count; i++) { 1035 rx_bi = &rx_ring->rx_bi[i]; 1036 rx_bi->dma = 0; 1037 rx_bi->hdr_buf = NULL; 1038 } 1039 } 1040 } 1041 /* Free all the Rx ring sk_buffs */ 1042 for (i = 0; i < rx_ring->count; i++) { 1043 rx_bi = &rx_ring->rx_bi[i]; 1044 if (rx_bi->dma) { 1045 dma_unmap_single(dev, 1046 rx_bi->dma, 1047 rx_ring->rx_buf_len, 1048 DMA_FROM_DEVICE); 1049 rx_bi->dma = 0; 1050 } 1051 if (rx_bi->skb) { 1052 dev_kfree_skb(rx_bi->skb); 1053 rx_bi->skb = NULL; 1054 } 1055 if (rx_bi->page) { 1056 if (rx_bi->page_dma) { 1057 dma_unmap_page(dev, 1058 rx_bi->page_dma, 1059 PAGE_SIZE / 2, 1060 DMA_FROM_DEVICE); 1061 rx_bi->page_dma = 0; 1062 } 1063 __free_page(rx_bi->page); 1064 rx_bi->page = NULL; 1065 rx_bi->page_offset = 0; 1066 } 1067 } 1068 1069 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; 1070 memset(rx_ring->rx_bi, 0, bi_size); 1071 1072 /* Zero out the descriptor ring */ 1073 memset(rx_ring->desc, 0, rx_ring->size); 1074 1075 rx_ring->next_to_clean = 0; 1076 rx_ring->next_to_use = 0; 1077 } 1078 1079 /** 1080 * i40e_free_rx_resources - Free Rx resources 1081 * @rx_ring: ring to clean the resources from 1082 * 1083 * Free all receive software resources 1084 **/ 1085 void i40e_free_rx_resources(struct i40e_ring *rx_ring) 1086 { 1087 i40e_clean_rx_ring(rx_ring); 1088 kfree(rx_ring->rx_bi); 1089 rx_ring->rx_bi = NULL; 1090 1091 if (rx_ring->desc) { 1092 dma_free_coherent(rx_ring->dev, rx_ring->size, 1093 rx_ring->desc, rx_ring->dma); 1094 rx_ring->desc = NULL; 1095 } 1096 } 1097 1098 /** 1099 * i40e_alloc_rx_headers - allocate rx header buffers 1100 * @rx_ring: ring to alloc buffers 1101 * 1102 * Allocate rx header buffers for the entire ring. As these are static, 1103 * this is only called when setting up a new ring. 1104 **/ 1105 void i40e_alloc_rx_headers(struct i40e_ring *rx_ring) 1106 { 1107 struct device *dev = rx_ring->dev; 1108 struct i40e_rx_buffer *rx_bi; 1109 dma_addr_t dma; 1110 void *buffer; 1111 int buf_size; 1112 int i; 1113 1114 if (rx_ring->rx_bi[0].hdr_buf) 1115 return; 1116 /* Make sure the buffers don't cross cache line boundaries. */ 1117 buf_size = ALIGN(rx_ring->rx_hdr_len, 256); 1118 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count, 1119 &dma, GFP_KERNEL); 1120 if (!buffer) 1121 return; 1122 for (i = 0; i < rx_ring->count; i++) { 1123 rx_bi = &rx_ring->rx_bi[i]; 1124 rx_bi->dma = dma + (i * buf_size); 1125 rx_bi->hdr_buf = buffer + (i * buf_size); 1126 } 1127 } 1128 1129 /** 1130 * i40e_setup_rx_descriptors - Allocate Rx descriptors 1131 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 1132 * 1133 * Returns 0 on success, negative on failure 1134 **/ 1135 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring) 1136 { 1137 struct device *dev = rx_ring->dev; 1138 int bi_size; 1139 1140 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; 1141 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); 1142 if (!rx_ring->rx_bi) 1143 goto err; 1144 1145 u64_stats_init(&rx_ring->syncp); 1146 1147 /* Round up to nearest 4K */ 1148 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring) 1149 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc) 1150 : rx_ring->count * sizeof(union i40e_32byte_rx_desc); 1151 rx_ring->size = ALIGN(rx_ring->size, 4096); 1152 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 1153 &rx_ring->dma, GFP_KERNEL); 1154 1155 if (!rx_ring->desc) { 1156 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", 1157 rx_ring->size); 1158 goto err; 1159 } 1160 1161 rx_ring->next_to_clean = 0; 1162 rx_ring->next_to_use = 0; 1163 1164 return 0; 1165 err: 1166 kfree(rx_ring->rx_bi); 1167 rx_ring->rx_bi = NULL; 1168 return -ENOMEM; 1169 } 1170 1171 /** 1172 * i40e_release_rx_desc - Store the new tail and head values 1173 * @rx_ring: ring to bump 1174 * @val: new head index 1175 **/ 1176 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) 1177 { 1178 rx_ring->next_to_use = val; 1179 /* Force memory writes to complete before letting h/w 1180 * know there are new descriptors to fetch. (Only 1181 * applicable for weak-ordered memory model archs, 1182 * such as IA-64). 1183 */ 1184 wmb(); 1185 writel(val, rx_ring->tail); 1186 } 1187 1188 /** 1189 * i40e_alloc_rx_buffers_ps - Replace used receive buffers; packet split 1190 * @rx_ring: ring to place buffers on 1191 * @cleaned_count: number of buffers to replace 1192 **/ 1193 void i40e_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count) 1194 { 1195 u16 i = rx_ring->next_to_use; 1196 union i40e_rx_desc *rx_desc; 1197 struct i40e_rx_buffer *bi; 1198 1199 /* do nothing if no valid netdev defined */ 1200 if (!rx_ring->netdev || !cleaned_count) 1201 return; 1202 1203 while (cleaned_count--) { 1204 rx_desc = I40E_RX_DESC(rx_ring, i); 1205 bi = &rx_ring->rx_bi[i]; 1206 1207 if (bi->skb) /* desc is in use */ 1208 goto no_buffers; 1209 if (!bi->page) { 1210 bi->page = alloc_page(GFP_ATOMIC); 1211 if (!bi->page) { 1212 rx_ring->rx_stats.alloc_page_failed++; 1213 goto no_buffers; 1214 } 1215 } 1216 1217 if (!bi->page_dma) { 1218 /* use a half page if we're re-using */ 1219 bi->page_offset ^= PAGE_SIZE / 2; 1220 bi->page_dma = dma_map_page(rx_ring->dev, 1221 bi->page, 1222 bi->page_offset, 1223 PAGE_SIZE / 2, 1224 DMA_FROM_DEVICE); 1225 if (dma_mapping_error(rx_ring->dev, 1226 bi->page_dma)) { 1227 rx_ring->rx_stats.alloc_page_failed++; 1228 bi->page_dma = 0; 1229 goto no_buffers; 1230 } 1231 } 1232 1233 dma_sync_single_range_for_device(rx_ring->dev, 1234 bi->dma, 1235 0, 1236 rx_ring->rx_hdr_len, 1237 DMA_FROM_DEVICE); 1238 /* Refresh the desc even if buffer_addrs didn't change 1239 * because each write-back erases this info. 1240 */ 1241 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); 1242 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); 1243 i++; 1244 if (i == rx_ring->count) 1245 i = 0; 1246 } 1247 1248 no_buffers: 1249 if (rx_ring->next_to_use != i) 1250 i40e_release_rx_desc(rx_ring, i); 1251 } 1252 1253 /** 1254 * i40e_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer 1255 * @rx_ring: ring to place buffers on 1256 * @cleaned_count: number of buffers to replace 1257 **/ 1258 void i40e_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count) 1259 { 1260 u16 i = rx_ring->next_to_use; 1261 union i40e_rx_desc *rx_desc; 1262 struct i40e_rx_buffer *bi; 1263 struct sk_buff *skb; 1264 1265 /* do nothing if no valid netdev defined */ 1266 if (!rx_ring->netdev || !cleaned_count) 1267 return; 1268 1269 while (cleaned_count--) { 1270 rx_desc = I40E_RX_DESC(rx_ring, i); 1271 bi = &rx_ring->rx_bi[i]; 1272 skb = bi->skb; 1273 1274 if (!skb) { 1275 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 1276 rx_ring->rx_buf_len); 1277 if (!skb) { 1278 rx_ring->rx_stats.alloc_buff_failed++; 1279 goto no_buffers; 1280 } 1281 /* initialize queue mapping */ 1282 skb_record_rx_queue(skb, rx_ring->queue_index); 1283 bi->skb = skb; 1284 } 1285 1286 if (!bi->dma) { 1287 bi->dma = dma_map_single(rx_ring->dev, 1288 skb->data, 1289 rx_ring->rx_buf_len, 1290 DMA_FROM_DEVICE); 1291 if (dma_mapping_error(rx_ring->dev, bi->dma)) { 1292 rx_ring->rx_stats.alloc_buff_failed++; 1293 bi->dma = 0; 1294 goto no_buffers; 1295 } 1296 } 1297 1298 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); 1299 rx_desc->read.hdr_addr = 0; 1300 i++; 1301 if (i == rx_ring->count) 1302 i = 0; 1303 } 1304 1305 no_buffers: 1306 if (rx_ring->next_to_use != i) 1307 i40e_release_rx_desc(rx_ring, i); 1308 } 1309 1310 /** 1311 * i40e_receive_skb - Send a completed packet up the stack 1312 * @rx_ring: rx ring in play 1313 * @skb: packet to send up 1314 * @vlan_tag: vlan tag for packet 1315 **/ 1316 static void i40e_receive_skb(struct i40e_ring *rx_ring, 1317 struct sk_buff *skb, u16 vlan_tag) 1318 { 1319 struct i40e_q_vector *q_vector = rx_ring->q_vector; 1320 struct i40e_vsi *vsi = rx_ring->vsi; 1321 u64 flags = vsi->back->flags; 1322 1323 if (vlan_tag & VLAN_VID_MASK) 1324 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); 1325 1326 if (flags & I40E_FLAG_IN_NETPOLL) 1327 netif_rx(skb); 1328 else 1329 napi_gro_receive(&q_vector->napi, skb); 1330 } 1331 1332 /** 1333 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum 1334 * @vsi: the VSI we care about 1335 * @skb: skb currently being received and modified 1336 * @rx_status: status value of last descriptor in packet 1337 * @rx_error: error value of last descriptor in packet 1338 * @rx_ptype: ptype value of last descriptor in packet 1339 **/ 1340 static inline void i40e_rx_checksum(struct i40e_vsi *vsi, 1341 struct sk_buff *skb, 1342 u32 rx_status, 1343 u32 rx_error, 1344 u16 rx_ptype) 1345 { 1346 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype); 1347 bool ipv4 = false, ipv6 = false; 1348 bool ipv4_tunnel, ipv6_tunnel; 1349 __wsum rx_udp_csum; 1350 struct iphdr *iph; 1351 __sum16 csum; 1352 1353 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) && 1354 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4); 1355 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) && 1356 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4); 1357 1358 skb->ip_summed = CHECKSUM_NONE; 1359 1360 /* Rx csum enabled and ip headers found? */ 1361 if (!(vsi->netdev->features & NETIF_F_RXCSUM)) 1362 return; 1363 1364 /* did the hardware decode the packet and checksum? */ 1365 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) 1366 return; 1367 1368 /* both known and outer_ip must be set for the below code to work */ 1369 if (!(decoded.known && decoded.outer_ip)) 1370 return; 1371 1372 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1373 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4) 1374 ipv4 = true; 1375 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1376 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6) 1377 ipv6 = true; 1378 1379 if (ipv4 && 1380 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | 1381 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) 1382 goto checksum_fail; 1383 1384 /* likely incorrect csum if alternate IP extension headers found */ 1385 if (ipv6 && 1386 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) 1387 /* don't increment checksum err here, non-fatal err */ 1388 return; 1389 1390 /* there was some L4 error, count error and punt packet to the stack */ 1391 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) 1392 goto checksum_fail; 1393 1394 /* handle packets that were not able to be checksummed due 1395 * to arrival speed, in this case the stack can compute 1396 * the csum. 1397 */ 1398 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) 1399 return; 1400 1401 /* If VXLAN traffic has an outer UDPv4 checksum we need to check 1402 * it in the driver, hardware does not do it for us. 1403 * Since L3L4P bit was set we assume a valid IHL value (>=5) 1404 * so the total length of IPv4 header is IHL*4 bytes 1405 * The UDP_0 bit *may* bet set if the *inner* header is UDP 1406 */ 1407 if (ipv4_tunnel) { 1408 skb->transport_header = skb->mac_header + 1409 sizeof(struct ethhdr) + 1410 (ip_hdr(skb)->ihl * 4); 1411 1412 /* Add 4 bytes for VLAN tagged packets */ 1413 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) || 1414 skb->protocol == htons(ETH_P_8021AD)) 1415 ? VLAN_HLEN : 0; 1416 1417 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) && 1418 (udp_hdr(skb)->check != 0)) { 1419 rx_udp_csum = udp_csum(skb); 1420 iph = ip_hdr(skb); 1421 csum = csum_tcpudp_magic( 1422 iph->saddr, iph->daddr, 1423 (skb->len - skb_transport_offset(skb)), 1424 IPPROTO_UDP, rx_udp_csum); 1425 1426 if (udp_hdr(skb)->check != csum) 1427 goto checksum_fail; 1428 1429 } /* else its GRE and so no outer UDP header */ 1430 } 1431 1432 skb->ip_summed = CHECKSUM_UNNECESSARY; 1433 skb->csum_level = ipv4_tunnel || ipv6_tunnel; 1434 1435 return; 1436 1437 checksum_fail: 1438 vsi->back->hw_csum_rx_error++; 1439 } 1440 1441 /** 1442 * i40e_rx_hash - returns the hash value from the Rx descriptor 1443 * @ring: descriptor ring 1444 * @rx_desc: specific descriptor 1445 **/ 1446 static inline u32 i40e_rx_hash(struct i40e_ring *ring, 1447 union i40e_rx_desc *rx_desc) 1448 { 1449 const __le64 rss_mask = 1450 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << 1451 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); 1452 1453 if ((ring->netdev->features & NETIF_F_RXHASH) && 1454 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) 1455 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); 1456 else 1457 return 0; 1458 } 1459 1460 /** 1461 * i40e_ptype_to_hash - get a hash type 1462 * @ptype: the ptype value from the descriptor 1463 * 1464 * Returns a hash type to be used by skb_set_hash 1465 **/ 1466 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype) 1467 { 1468 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); 1469 1470 if (!decoded.known) 1471 return PKT_HASH_TYPE_NONE; 1472 1473 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1474 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) 1475 return PKT_HASH_TYPE_L4; 1476 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && 1477 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) 1478 return PKT_HASH_TYPE_L3; 1479 else 1480 return PKT_HASH_TYPE_L2; 1481 } 1482 1483 /** 1484 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split 1485 * @rx_ring: rx ring to clean 1486 * @budget: how many cleans we're allowed 1487 * 1488 * Returns true if there's any budget left (e.g. the clean is finished) 1489 **/ 1490 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget) 1491 { 1492 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1493 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo; 1494 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); 1495 const int current_node = numa_node_id(); 1496 struct i40e_vsi *vsi = rx_ring->vsi; 1497 u16 i = rx_ring->next_to_clean; 1498 union i40e_rx_desc *rx_desc; 1499 u32 rx_error, rx_status; 1500 u8 rx_ptype; 1501 u64 qword; 1502 1503 if (budget <= 0) 1504 return 0; 1505 1506 do { 1507 struct i40e_rx_buffer *rx_bi; 1508 struct sk_buff *skb; 1509 u16 vlan_tag; 1510 /* return some buffers to hardware, one at a time is too slow */ 1511 if (cleaned_count >= I40E_RX_BUFFER_WRITE) { 1512 i40e_alloc_rx_buffers_ps(rx_ring, cleaned_count); 1513 cleaned_count = 0; 1514 } 1515 1516 i = rx_ring->next_to_clean; 1517 rx_desc = I40E_RX_DESC(rx_ring, i); 1518 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1519 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1520 I40E_RXD_QW1_STATUS_SHIFT; 1521 1522 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT))) 1523 break; 1524 1525 /* This memory barrier is needed to keep us from reading 1526 * any other fields out of the rx_desc until we know the 1527 * DD bit is set. 1528 */ 1529 dma_rmb(); 1530 if (i40e_rx_is_programming_status(qword)) { 1531 i40e_clean_programming_status(rx_ring, rx_desc); 1532 I40E_RX_INCREMENT(rx_ring, i); 1533 continue; 1534 } 1535 rx_bi = &rx_ring->rx_bi[i]; 1536 skb = rx_bi->skb; 1537 if (likely(!skb)) { 1538 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 1539 rx_ring->rx_hdr_len); 1540 if (!skb) { 1541 rx_ring->rx_stats.alloc_buff_failed++; 1542 break; 1543 } 1544 1545 /* initialize queue mapping */ 1546 skb_record_rx_queue(skb, rx_ring->queue_index); 1547 /* we are reusing so sync this buffer for CPU use */ 1548 dma_sync_single_range_for_cpu(rx_ring->dev, 1549 rx_bi->dma, 1550 0, 1551 rx_ring->rx_hdr_len, 1552 DMA_FROM_DEVICE); 1553 } 1554 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> 1555 I40E_RXD_QW1_LENGTH_PBUF_SHIFT; 1556 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >> 1557 I40E_RXD_QW1_LENGTH_HBUF_SHIFT; 1558 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >> 1559 I40E_RXD_QW1_LENGTH_SPH_SHIFT; 1560 1561 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> 1562 I40E_RXD_QW1_ERROR_SHIFT; 1563 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT); 1564 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT); 1565 1566 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> 1567 I40E_RXD_QW1_PTYPE_SHIFT; 1568 prefetch(rx_bi->page); 1569 rx_bi->skb = NULL; 1570 cleaned_count++; 1571 if (rx_hbo || rx_sph) { 1572 int len; 1573 if (rx_hbo) 1574 len = I40E_RX_HDR_SIZE; 1575 else 1576 len = rx_header_len; 1577 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len); 1578 } else if (skb->len == 0) { 1579 int len; 1580 1581 len = (rx_packet_len > skb_headlen(skb) ? 1582 skb_headlen(skb) : rx_packet_len); 1583 memcpy(__skb_put(skb, len), 1584 rx_bi->page + rx_bi->page_offset, 1585 len); 1586 rx_bi->page_offset += len; 1587 rx_packet_len -= len; 1588 } 1589 1590 /* Get the rest of the data if this was a header split */ 1591 if (rx_packet_len) { 1592 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, 1593 rx_bi->page, 1594 rx_bi->page_offset, 1595 rx_packet_len); 1596 1597 skb->len += rx_packet_len; 1598 skb->data_len += rx_packet_len; 1599 skb->truesize += rx_packet_len; 1600 1601 if ((page_count(rx_bi->page) == 1) && 1602 (page_to_nid(rx_bi->page) == current_node)) 1603 get_page(rx_bi->page); 1604 else 1605 rx_bi->page = NULL; 1606 1607 dma_unmap_page(rx_ring->dev, 1608 rx_bi->page_dma, 1609 PAGE_SIZE / 2, 1610 DMA_FROM_DEVICE); 1611 rx_bi->page_dma = 0; 1612 } 1613 I40E_RX_INCREMENT(rx_ring, i); 1614 1615 if (unlikely( 1616 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) { 1617 struct i40e_rx_buffer *next_buffer; 1618 1619 next_buffer = &rx_ring->rx_bi[i]; 1620 next_buffer->skb = skb; 1621 rx_ring->rx_stats.non_eop_descs++; 1622 continue; 1623 } 1624 1625 /* ERR_MASK will only have valid bits if EOP set */ 1626 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) { 1627 dev_kfree_skb_any(skb); 1628 continue; 1629 } 1630 1631 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc), 1632 i40e_ptype_to_hash(rx_ptype)); 1633 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) { 1634 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status & 1635 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> 1636 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT); 1637 rx_ring->last_rx_timestamp = jiffies; 1638 } 1639 1640 /* probably a little skewed due to removing CRC */ 1641 total_rx_bytes += skb->len; 1642 total_rx_packets++; 1643 1644 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1645 1646 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype); 1647 1648 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) 1649 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) 1650 : 0; 1651 #ifdef I40E_FCOE 1652 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) { 1653 dev_kfree_skb_any(skb); 1654 continue; 1655 } 1656 #endif 1657 skb_mark_napi_id(skb, &rx_ring->q_vector->napi); 1658 i40e_receive_skb(rx_ring, skb, vlan_tag); 1659 1660 rx_desc->wb.qword1.status_error_len = 0; 1661 1662 } while (likely(total_rx_packets < budget)); 1663 1664 u64_stats_update_begin(&rx_ring->syncp); 1665 rx_ring->stats.packets += total_rx_packets; 1666 rx_ring->stats.bytes += total_rx_bytes; 1667 u64_stats_update_end(&rx_ring->syncp); 1668 rx_ring->q_vector->rx.total_packets += total_rx_packets; 1669 rx_ring->q_vector->rx.total_bytes += total_rx_bytes; 1670 1671 return total_rx_packets; 1672 } 1673 1674 /** 1675 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer 1676 * @rx_ring: rx ring to clean 1677 * @budget: how many cleans we're allowed 1678 * 1679 * Returns number of packets cleaned 1680 **/ 1681 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget) 1682 { 1683 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 1684 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); 1685 struct i40e_vsi *vsi = rx_ring->vsi; 1686 union i40e_rx_desc *rx_desc; 1687 u32 rx_error, rx_status; 1688 u16 rx_packet_len; 1689 u8 rx_ptype; 1690 u64 qword; 1691 u16 i; 1692 1693 do { 1694 struct i40e_rx_buffer *rx_bi; 1695 struct sk_buff *skb; 1696 u16 vlan_tag; 1697 /* return some buffers to hardware, one at a time is too slow */ 1698 if (cleaned_count >= I40E_RX_BUFFER_WRITE) { 1699 i40e_alloc_rx_buffers_1buf(rx_ring, cleaned_count); 1700 cleaned_count = 0; 1701 } 1702 1703 i = rx_ring->next_to_clean; 1704 rx_desc = I40E_RX_DESC(rx_ring, i); 1705 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); 1706 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> 1707 I40E_RXD_QW1_STATUS_SHIFT; 1708 1709 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT))) 1710 break; 1711 1712 /* This memory barrier is needed to keep us from reading 1713 * any other fields out of the rx_desc until we know the 1714 * DD bit is set. 1715 */ 1716 dma_rmb(); 1717 1718 if (i40e_rx_is_programming_status(qword)) { 1719 i40e_clean_programming_status(rx_ring, rx_desc); 1720 I40E_RX_INCREMENT(rx_ring, i); 1721 continue; 1722 } 1723 rx_bi = &rx_ring->rx_bi[i]; 1724 skb = rx_bi->skb; 1725 prefetch(skb->data); 1726 1727 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> 1728 I40E_RXD_QW1_LENGTH_PBUF_SHIFT; 1729 1730 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> 1731 I40E_RXD_QW1_ERROR_SHIFT; 1732 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT); 1733 1734 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> 1735 I40E_RXD_QW1_PTYPE_SHIFT; 1736 rx_bi->skb = NULL; 1737 cleaned_count++; 1738 1739 /* Get the header and possibly the whole packet 1740 * If this is an skb from previous receive dma will be 0 1741 */ 1742 skb_put(skb, rx_packet_len); 1743 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len, 1744 DMA_FROM_DEVICE); 1745 rx_bi->dma = 0; 1746 1747 I40E_RX_INCREMENT(rx_ring, i); 1748 1749 if (unlikely( 1750 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) { 1751 rx_ring->rx_stats.non_eop_descs++; 1752 continue; 1753 } 1754 1755 /* ERR_MASK will only have valid bits if EOP set */ 1756 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) { 1757 dev_kfree_skb_any(skb); 1758 /* TODO: shouldn't we increment a counter indicating the 1759 * drop? 1760 */ 1761 continue; 1762 } 1763 1764 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc), 1765 i40e_ptype_to_hash(rx_ptype)); 1766 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) { 1767 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status & 1768 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >> 1769 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT); 1770 rx_ring->last_rx_timestamp = jiffies; 1771 } 1772 1773 /* probably a little skewed due to removing CRC */ 1774 total_rx_bytes += skb->len; 1775 total_rx_packets++; 1776 1777 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 1778 1779 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype); 1780 1781 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) 1782 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) 1783 : 0; 1784 #ifdef I40E_FCOE 1785 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) { 1786 dev_kfree_skb_any(skb); 1787 continue; 1788 } 1789 #endif 1790 i40e_receive_skb(rx_ring, skb, vlan_tag); 1791 1792 rx_desc->wb.qword1.status_error_len = 0; 1793 } while (likely(total_rx_packets < budget)); 1794 1795 u64_stats_update_begin(&rx_ring->syncp); 1796 rx_ring->stats.packets += total_rx_packets; 1797 rx_ring->stats.bytes += total_rx_bytes; 1798 u64_stats_update_end(&rx_ring->syncp); 1799 rx_ring->q_vector->rx.total_packets += total_rx_packets; 1800 rx_ring->q_vector->rx.total_bytes += total_rx_bytes; 1801 1802 return total_rx_packets; 1803 } 1804 1805 /** 1806 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt 1807 * @vsi: the VSI we care about 1808 * @q_vector: q_vector for which itr is being updated and interrupt enabled 1809 * 1810 **/ 1811 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, 1812 struct i40e_q_vector *q_vector) 1813 { 1814 struct i40e_hw *hw = &vsi->back->hw; 1815 u16 old_itr; 1816 int vector; 1817 u32 val; 1818 1819 vector = (q_vector->v_idx + vsi->base_vector); 1820 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) { 1821 old_itr = q_vector->rx.itr; 1822 i40e_set_new_dynamic_itr(&q_vector->rx); 1823 if (old_itr != q_vector->rx.itr) { 1824 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1825 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1826 (I40E_RX_ITR << 1827 I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | 1828 (q_vector->rx.itr << 1829 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT); 1830 } else { 1831 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1832 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1833 (I40E_ITR_NONE << 1834 I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1835 } 1836 if (!test_bit(__I40E_DOWN, &vsi->state)) 1837 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val); 1838 } else { 1839 i40e_irq_dynamic_enable(vsi, 1840 q_vector->v_idx + vsi->base_vector); 1841 } 1842 if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) { 1843 old_itr = q_vector->tx.itr; 1844 i40e_set_new_dynamic_itr(&q_vector->tx); 1845 if (old_itr != q_vector->tx.itr) { 1846 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1847 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1848 (I40E_TX_ITR << 1849 I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | 1850 (q_vector->tx.itr << 1851 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT); 1852 } else { 1853 val = I40E_PFINT_DYN_CTLN_INTENA_MASK | 1854 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1855 (I40E_ITR_NONE << 1856 I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); 1857 } 1858 if (!test_bit(__I40E_DOWN, &vsi->state)) 1859 wr32(hw, I40E_PFINT_DYN_CTLN(q_vector->v_idx + 1860 vsi->base_vector - 1), val); 1861 } else { 1862 i40e_irq_dynamic_enable(vsi, 1863 q_vector->v_idx + vsi->base_vector); 1864 } 1865 } 1866 1867 /** 1868 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine 1869 * @napi: napi struct with our devices info in it 1870 * @budget: amount of work driver is allowed to do this pass, in packets 1871 * 1872 * This function will clean all queues associated with a q_vector. 1873 * 1874 * Returns the amount of work done 1875 **/ 1876 int i40e_napi_poll(struct napi_struct *napi, int budget) 1877 { 1878 struct i40e_q_vector *q_vector = 1879 container_of(napi, struct i40e_q_vector, napi); 1880 struct i40e_vsi *vsi = q_vector->vsi; 1881 struct i40e_ring *ring; 1882 bool clean_complete = true; 1883 bool arm_wb = false; 1884 int budget_per_ring; 1885 int cleaned; 1886 1887 if (test_bit(__I40E_DOWN, &vsi->state)) { 1888 napi_complete(napi); 1889 return 0; 1890 } 1891 1892 /* Since the actual Tx work is minimal, we can give the Tx a larger 1893 * budget and be more aggressive about cleaning up the Tx descriptors. 1894 */ 1895 i40e_for_each_ring(ring, q_vector->tx) { 1896 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit); 1897 arm_wb |= ring->arm_wb; 1898 } 1899 1900 /* We attempt to distribute budget to each Rx queue fairly, but don't 1901 * allow the budget to go below 1 because that would exit polling early. 1902 */ 1903 budget_per_ring = max(budget/q_vector->num_ringpairs, 1); 1904 1905 i40e_for_each_ring(ring, q_vector->rx) { 1906 if (ring_is_ps_enabled(ring)) 1907 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring); 1908 else 1909 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring); 1910 /* if we didn't clean as many as budgeted, we must be done */ 1911 clean_complete &= (budget_per_ring != cleaned); 1912 } 1913 1914 /* If work not completed, return budget and polling will return */ 1915 if (!clean_complete) { 1916 if (arm_wb) 1917 i40e_force_wb(vsi, q_vector); 1918 return budget; 1919 } 1920 1921 /* Work is done so exit the polling mode and re-enable the interrupt */ 1922 napi_complete(napi); 1923 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { 1924 i40e_update_enable_itr(vsi, q_vector); 1925 } else { /* Legacy mode */ 1926 struct i40e_hw *hw = &vsi->back->hw; 1927 /* We re-enable the queue 0 cause, but 1928 * don't worry about dynamic_enable 1929 * because we left it on for the other 1930 * possible interrupts during napi 1931 */ 1932 u32 qval = rd32(hw, I40E_QINT_RQCTL(0)) | 1933 I40E_QINT_RQCTL_CAUSE_ENA_MASK; 1934 1935 wr32(hw, I40E_QINT_RQCTL(0), qval); 1936 qval = rd32(hw, I40E_QINT_TQCTL(0)) | 1937 I40E_QINT_TQCTL_CAUSE_ENA_MASK; 1938 wr32(hw, I40E_QINT_TQCTL(0), qval); 1939 i40e_irq_dynamic_enable_icr0(vsi->back); 1940 } 1941 return 0; 1942 } 1943 1944 /** 1945 * i40e_atr - Add a Flow Director ATR filter 1946 * @tx_ring: ring to add programming descriptor to 1947 * @skb: send buffer 1948 * @tx_flags: send tx flags 1949 * @protocol: wire protocol 1950 **/ 1951 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb, 1952 u32 tx_flags, __be16 protocol) 1953 { 1954 struct i40e_filter_program_desc *fdir_desc; 1955 struct i40e_pf *pf = tx_ring->vsi->back; 1956 union { 1957 unsigned char *network; 1958 struct iphdr *ipv4; 1959 struct ipv6hdr *ipv6; 1960 } hdr; 1961 struct tcphdr *th; 1962 unsigned int hlen; 1963 u32 flex_ptype, dtype_cmd; 1964 u16 i; 1965 1966 /* make sure ATR is enabled */ 1967 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED)) 1968 return; 1969 1970 if ((pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) 1971 return; 1972 1973 /* if sampling is disabled do nothing */ 1974 if (!tx_ring->atr_sample_rate) 1975 return; 1976 1977 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6))) 1978 return; 1979 1980 if (!(tx_flags & I40E_TX_FLAGS_VXLAN_TUNNEL)) { 1981 /* snag network header to get L4 type and address */ 1982 hdr.network = skb_network_header(skb); 1983 1984 /* Currently only IPv4/IPv6 with TCP is supported 1985 * access ihl as u8 to avoid unaligned access on ia64 1986 */ 1987 if (tx_flags & I40E_TX_FLAGS_IPV4) 1988 hlen = (hdr.network[0] & 0x0F) << 2; 1989 else if (protocol == htons(ETH_P_IPV6)) 1990 hlen = sizeof(struct ipv6hdr); 1991 else 1992 return; 1993 } else { 1994 hdr.network = skb_inner_network_header(skb); 1995 hlen = skb_inner_network_header_len(skb); 1996 } 1997 1998 /* Currently only IPv4/IPv6 with TCP is supported 1999 * Note: tx_flags gets modified to reflect inner protocols in 2000 * tx_enable_csum function if encap is enabled. 2001 */ 2002 if ((tx_flags & I40E_TX_FLAGS_IPV4) && 2003 (hdr.ipv4->protocol != IPPROTO_TCP)) 2004 return; 2005 else if ((tx_flags & I40E_TX_FLAGS_IPV6) && 2006 (hdr.ipv6->nexthdr != IPPROTO_TCP)) 2007 return; 2008 2009 th = (struct tcphdr *)(hdr.network + hlen); 2010 2011 /* Due to lack of space, no more new filters can be programmed */ 2012 if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) 2013 return; 2014 2015 tx_ring->atr_count++; 2016 2017 /* sample on all syn/fin/rst packets or once every atr sample rate */ 2018 if (!th->fin && 2019 !th->syn && 2020 !th->rst && 2021 (tx_ring->atr_count < tx_ring->atr_sample_rate)) 2022 return; 2023 2024 tx_ring->atr_count = 0; 2025 2026 /* grab the next descriptor */ 2027 i = tx_ring->next_to_use; 2028 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i); 2029 2030 i++; 2031 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2032 2033 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) & 2034 I40E_TXD_FLTR_QW0_QINDEX_MASK; 2035 flex_ptype |= (protocol == htons(ETH_P_IP)) ? 2036 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP << 2037 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) : 2038 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP << 2039 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT); 2040 2041 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT; 2042 2043 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG; 2044 2045 dtype_cmd |= (th->fin || th->rst) ? 2046 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE << 2047 I40E_TXD_FLTR_QW1_PCMD_SHIFT) : 2048 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE << 2049 I40E_TXD_FLTR_QW1_PCMD_SHIFT); 2050 2051 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX << 2052 I40E_TXD_FLTR_QW1_DEST_SHIFT; 2053 2054 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID << 2055 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT; 2056 2057 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK; 2058 if (!(tx_flags & I40E_TX_FLAGS_VXLAN_TUNNEL)) 2059 dtype_cmd |= 2060 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) << 2061 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 2062 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 2063 else 2064 dtype_cmd |= 2065 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) << 2066 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) & 2067 I40E_TXD_FLTR_QW1_CNTINDEX_MASK; 2068 2069 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype); 2070 fdir_desc->rsvd = cpu_to_le32(0); 2071 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd); 2072 fdir_desc->fd_id = cpu_to_le32(0); 2073 } 2074 2075 /** 2076 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW 2077 * @skb: send buffer 2078 * @tx_ring: ring to send buffer on 2079 * @flags: the tx flags to be set 2080 * 2081 * Checks the skb and set up correspondingly several generic transmit flags 2082 * related to VLAN tagging for the HW, such as VLAN, DCB, etc. 2083 * 2084 * Returns error code indicate the frame should be dropped upon error and the 2085 * otherwise returns 0 to indicate the flags has been set properly. 2086 **/ 2087 #ifdef I40E_FCOE 2088 inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 2089 struct i40e_ring *tx_ring, 2090 u32 *flags) 2091 #else 2092 static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb, 2093 struct i40e_ring *tx_ring, 2094 u32 *flags) 2095 #endif 2096 { 2097 __be16 protocol = skb->protocol; 2098 u32 tx_flags = 0; 2099 2100 if (protocol == htons(ETH_P_8021Q) && 2101 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 2102 /* When HW VLAN acceleration is turned off by the user the 2103 * stack sets the protocol to 8021q so that the driver 2104 * can take any steps required to support the SW only 2105 * VLAN handling. In our case the driver doesn't need 2106 * to take any further steps so just set the protocol 2107 * to the encapsulated ethertype. 2108 */ 2109 skb->protocol = vlan_get_protocol(skb); 2110 goto out; 2111 } 2112 2113 /* if we have a HW VLAN tag being added, default to the HW one */ 2114 if (skb_vlan_tag_present(skb)) { 2115 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; 2116 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 2117 /* else if it is a SW VLAN, check the next protocol and store the tag */ 2118 } else if (protocol == htons(ETH_P_8021Q)) { 2119 struct vlan_hdr *vhdr, _vhdr; 2120 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 2121 if (!vhdr) 2122 return -EINVAL; 2123 2124 protocol = vhdr->h_vlan_encapsulated_proto; 2125 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; 2126 tx_flags |= I40E_TX_FLAGS_SW_VLAN; 2127 } 2128 2129 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED)) 2130 goto out; 2131 2132 /* Insert 802.1p priority into VLAN header */ 2133 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) || 2134 (skb->priority != TC_PRIO_CONTROL)) { 2135 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK; 2136 tx_flags |= (skb->priority & 0x7) << 2137 I40E_TX_FLAGS_VLAN_PRIO_SHIFT; 2138 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) { 2139 struct vlan_ethhdr *vhdr; 2140 int rc; 2141 2142 rc = skb_cow_head(skb, 0); 2143 if (rc < 0) 2144 return rc; 2145 vhdr = (struct vlan_ethhdr *)skb->data; 2146 vhdr->h_vlan_TCI = htons(tx_flags >> 2147 I40E_TX_FLAGS_VLAN_SHIFT); 2148 } else { 2149 tx_flags |= I40E_TX_FLAGS_HW_VLAN; 2150 } 2151 } 2152 2153 out: 2154 *flags = tx_flags; 2155 return 0; 2156 } 2157 2158 /** 2159 * i40e_tso - set up the tso context descriptor 2160 * @tx_ring: ptr to the ring to send 2161 * @skb: ptr to the skb we're sending 2162 * @hdr_len: ptr to the size of the packet header 2163 * @cd_tunneling: ptr to context descriptor bits 2164 * 2165 * Returns 0 if no TSO can happen, 1 if tso is going, or error 2166 **/ 2167 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb, 2168 u8 *hdr_len, u64 *cd_type_cmd_tso_mss, 2169 u32 *cd_tunneling) 2170 { 2171 u32 cd_cmd, cd_tso_len, cd_mss; 2172 struct ipv6hdr *ipv6h; 2173 struct tcphdr *tcph; 2174 struct iphdr *iph; 2175 u32 l4len; 2176 int err; 2177 2178 if (!skb_is_gso(skb)) 2179 return 0; 2180 2181 err = skb_cow_head(skb, 0); 2182 if (err < 0) 2183 return err; 2184 2185 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb); 2186 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb); 2187 2188 if (iph->version == 4) { 2189 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb); 2190 iph->tot_len = 0; 2191 iph->check = 0; 2192 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 2193 0, IPPROTO_TCP, 0); 2194 } else if (ipv6h->version == 6) { 2195 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb); 2196 ipv6h->payload_len = 0; 2197 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 2198 0, IPPROTO_TCP, 0); 2199 } 2200 2201 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb); 2202 *hdr_len = (skb->encapsulation 2203 ? (skb_inner_transport_header(skb) - skb->data) 2204 : skb_transport_offset(skb)) + l4len; 2205 2206 /* find the field values */ 2207 cd_cmd = I40E_TX_CTX_DESC_TSO; 2208 cd_tso_len = skb->len - *hdr_len; 2209 cd_mss = skb_shinfo(skb)->gso_size; 2210 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | 2211 ((u64)cd_tso_len << 2212 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | 2213 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); 2214 return 1; 2215 } 2216 2217 /** 2218 * i40e_tsyn - set up the tsyn context descriptor 2219 * @tx_ring: ptr to the ring to send 2220 * @skb: ptr to the skb we're sending 2221 * @tx_flags: the collected send information 2222 * 2223 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen 2224 **/ 2225 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb, 2226 u32 tx_flags, u64 *cd_type_cmd_tso_mss) 2227 { 2228 struct i40e_pf *pf; 2229 2230 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) 2231 return 0; 2232 2233 /* Tx timestamps cannot be sampled when doing TSO */ 2234 if (tx_flags & I40E_TX_FLAGS_TSO) 2235 return 0; 2236 2237 /* only timestamp the outbound packet if the user has requested it and 2238 * we are not already transmitting a packet to be timestamped 2239 */ 2240 pf = i40e_netdev_to_pf(tx_ring->netdev); 2241 if (!(pf->flags & I40E_FLAG_PTP)) 2242 return 0; 2243 2244 if (pf->ptp_tx && 2245 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) { 2246 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2247 pf->ptp_tx_skb = skb_get(skb); 2248 } else { 2249 return 0; 2250 } 2251 2252 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN << 2253 I40E_TXD_CTX_QW1_CMD_SHIFT; 2254 2255 return 1; 2256 } 2257 2258 /** 2259 * i40e_tx_enable_csum - Enable Tx checksum offloads 2260 * @skb: send buffer 2261 * @tx_flags: pointer to Tx flags currently set 2262 * @td_cmd: Tx descriptor command bits to set 2263 * @td_offset: Tx descriptor header offsets to set 2264 * @cd_tunneling: ptr to context desc bits 2265 **/ 2266 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, 2267 u32 *td_cmd, u32 *td_offset, 2268 struct i40e_ring *tx_ring, 2269 u32 *cd_tunneling) 2270 { 2271 struct ipv6hdr *this_ipv6_hdr; 2272 unsigned int this_tcp_hdrlen; 2273 struct iphdr *this_ip_hdr; 2274 u32 network_hdr_len; 2275 u8 l4_hdr = 0; 2276 u32 l4_tunnel = 0; 2277 2278 if (skb->encapsulation) { 2279 switch (ip_hdr(skb)->protocol) { 2280 case IPPROTO_UDP: 2281 l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING; 2282 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL; 2283 break; 2284 default: 2285 return; 2286 } 2287 network_hdr_len = skb_inner_network_header_len(skb); 2288 this_ip_hdr = inner_ip_hdr(skb); 2289 this_ipv6_hdr = inner_ipv6_hdr(skb); 2290 this_tcp_hdrlen = inner_tcp_hdrlen(skb); 2291 2292 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 2293 if (*tx_flags & I40E_TX_FLAGS_TSO) { 2294 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4; 2295 ip_hdr(skb)->check = 0; 2296 } else { 2297 *cd_tunneling |= 2298 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; 2299 } 2300 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 2301 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6; 2302 if (*tx_flags & I40E_TX_FLAGS_TSO) 2303 ip_hdr(skb)->check = 0; 2304 } 2305 2306 /* Now set the ctx descriptor fields */ 2307 *cd_tunneling |= (skb_network_header_len(skb) >> 2) << 2308 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT | 2309 l4_tunnel | 2310 ((skb_inner_network_offset(skb) - 2311 skb_transport_offset(skb)) >> 1) << 2312 I40E_TXD_CTX_QW0_NATLEN_SHIFT; 2313 if (this_ip_hdr->version == 6) { 2314 *tx_flags &= ~I40E_TX_FLAGS_IPV4; 2315 *tx_flags |= I40E_TX_FLAGS_IPV6; 2316 } 2317 } else { 2318 network_hdr_len = skb_network_header_len(skb); 2319 this_ip_hdr = ip_hdr(skb); 2320 this_ipv6_hdr = ipv6_hdr(skb); 2321 this_tcp_hdrlen = tcp_hdrlen(skb); 2322 } 2323 2324 /* Enable IP checksum offloads */ 2325 if (*tx_flags & I40E_TX_FLAGS_IPV4) { 2326 l4_hdr = this_ip_hdr->protocol; 2327 /* the stack computes the IP header already, the only time we 2328 * need the hardware to recompute it is in the case of TSO. 2329 */ 2330 if (*tx_flags & I40E_TX_FLAGS_TSO) { 2331 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM; 2332 this_ip_hdr->check = 0; 2333 } else { 2334 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4; 2335 } 2336 /* Now set the td_offset for IP header length */ 2337 *td_offset = (network_hdr_len >> 2) << 2338 I40E_TX_DESC_LENGTH_IPLEN_SHIFT; 2339 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { 2340 l4_hdr = this_ipv6_hdr->nexthdr; 2341 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; 2342 /* Now set the td_offset for IP header length */ 2343 *td_offset = (network_hdr_len >> 2) << 2344 I40E_TX_DESC_LENGTH_IPLEN_SHIFT; 2345 } 2346 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */ 2347 *td_offset |= (skb_network_offset(skb) >> 1) << 2348 I40E_TX_DESC_LENGTH_MACLEN_SHIFT; 2349 2350 /* Enable L4 checksum offloads */ 2351 switch (l4_hdr) { 2352 case IPPROTO_TCP: 2353 /* enable checksum offloads */ 2354 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; 2355 *td_offset |= (this_tcp_hdrlen >> 2) << 2356 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2357 break; 2358 case IPPROTO_SCTP: 2359 /* enable SCTP checksum offload */ 2360 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; 2361 *td_offset |= (sizeof(struct sctphdr) >> 2) << 2362 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2363 break; 2364 case IPPROTO_UDP: 2365 /* enable UDP checksum offload */ 2366 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; 2367 *td_offset |= (sizeof(struct udphdr) >> 2) << 2368 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; 2369 break; 2370 default: 2371 break; 2372 } 2373 } 2374 2375 /** 2376 * i40e_create_tx_ctx Build the Tx context descriptor 2377 * @tx_ring: ring to create the descriptor on 2378 * @cd_type_cmd_tso_mss: Quad Word 1 2379 * @cd_tunneling: Quad Word 0 - bits 0-31 2380 * @cd_l2tag2: Quad Word 0 - bits 32-63 2381 **/ 2382 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, 2383 const u64 cd_type_cmd_tso_mss, 2384 const u32 cd_tunneling, const u32 cd_l2tag2) 2385 { 2386 struct i40e_tx_context_desc *context_desc; 2387 int i = tx_ring->next_to_use; 2388 2389 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && 2390 !cd_tunneling && !cd_l2tag2) 2391 return; 2392 2393 /* grab the next descriptor */ 2394 context_desc = I40E_TX_CTXTDESC(tx_ring, i); 2395 2396 i++; 2397 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2398 2399 /* cpu_to_le32 and assign to struct fields */ 2400 context_desc->tunneling_params = cpu_to_le32(cd_tunneling); 2401 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); 2402 context_desc->rsvd = cpu_to_le16(0); 2403 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); 2404 } 2405 2406 /** 2407 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions 2408 * @tx_ring: the ring to be checked 2409 * @size: the size buffer we want to assure is available 2410 * 2411 * Returns -EBUSY if a stop is needed, else 0 2412 **/ 2413 static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 2414 { 2415 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 2416 /* Memory barrier before checking head and tail */ 2417 smp_mb(); 2418 2419 /* Check again in a case another CPU has just made room available. */ 2420 if (likely(I40E_DESC_UNUSED(tx_ring) < size)) 2421 return -EBUSY; 2422 2423 /* A reprieve! - use start_queue because it doesn't call schedule */ 2424 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 2425 ++tx_ring->tx_stats.restart_queue; 2426 return 0; 2427 } 2428 2429 /** 2430 * i40e_maybe_stop_tx - 1st level check for tx stop conditions 2431 * @tx_ring: the ring to be checked 2432 * @size: the size buffer we want to assure is available 2433 * 2434 * Returns 0 if stop is not needed 2435 **/ 2436 #ifdef I40E_FCOE 2437 inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 2438 #else 2439 static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) 2440 #endif 2441 { 2442 if (likely(I40E_DESC_UNUSED(tx_ring) >= size)) 2443 return 0; 2444 return __i40e_maybe_stop_tx(tx_ring, size); 2445 } 2446 2447 /** 2448 * i40e_chk_linearize - Check if there are more than 8 fragments per packet 2449 * @skb: send buffer 2450 * @tx_flags: collected send information 2451 * 2452 * Note: Our HW can't scatter-gather more than 8 fragments to build 2453 * a packet on the wire and so we need to figure out the cases where we 2454 * need to linearize the skb. 2455 **/ 2456 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags) 2457 { 2458 struct skb_frag_struct *frag; 2459 bool linearize = false; 2460 unsigned int size = 0; 2461 u16 num_frags; 2462 u16 gso_segs; 2463 2464 num_frags = skb_shinfo(skb)->nr_frags; 2465 gso_segs = skb_shinfo(skb)->gso_segs; 2466 2467 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) { 2468 u16 j = 0; 2469 2470 if (num_frags < (I40E_MAX_BUFFER_TXD)) 2471 goto linearize_chk_done; 2472 /* try the simple math, if we have too many frags per segment */ 2473 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) > 2474 I40E_MAX_BUFFER_TXD) { 2475 linearize = true; 2476 goto linearize_chk_done; 2477 } 2478 frag = &skb_shinfo(skb)->frags[0]; 2479 /* we might still have more fragments per segment */ 2480 do { 2481 size += skb_frag_size(frag); 2482 frag++; j++; 2483 if ((size >= skb_shinfo(skb)->gso_size) && 2484 (j < I40E_MAX_BUFFER_TXD)) { 2485 size = (size % skb_shinfo(skb)->gso_size); 2486 j = (size) ? 1 : 0; 2487 } 2488 if (j == I40E_MAX_BUFFER_TXD) { 2489 linearize = true; 2490 break; 2491 } 2492 num_frags--; 2493 } while (num_frags); 2494 } else { 2495 if (num_frags >= I40E_MAX_BUFFER_TXD) 2496 linearize = true; 2497 } 2498 2499 linearize_chk_done: 2500 return linearize; 2501 } 2502 2503 /** 2504 * i40e_tx_map - Build the Tx descriptor 2505 * @tx_ring: ring to send buffer on 2506 * @skb: send buffer 2507 * @first: first buffer info buffer to use 2508 * @tx_flags: collected send information 2509 * @hdr_len: size of the packet header 2510 * @td_cmd: the command field in the descriptor 2511 * @td_offset: offset for checksum or crc 2512 **/ 2513 #ifdef I40E_FCOE 2514 inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 2515 struct i40e_tx_buffer *first, u32 tx_flags, 2516 const u8 hdr_len, u32 td_cmd, u32 td_offset) 2517 #else 2518 static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, 2519 struct i40e_tx_buffer *first, u32 tx_flags, 2520 const u8 hdr_len, u32 td_cmd, u32 td_offset) 2521 #endif 2522 { 2523 unsigned int data_len = skb->data_len; 2524 unsigned int size = skb_headlen(skb); 2525 struct skb_frag_struct *frag; 2526 struct i40e_tx_buffer *tx_bi; 2527 struct i40e_tx_desc *tx_desc; 2528 u16 i = tx_ring->next_to_use; 2529 u32 td_tag = 0; 2530 dma_addr_t dma; 2531 u16 gso_segs; 2532 2533 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { 2534 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; 2535 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> 2536 I40E_TX_FLAGS_VLAN_SHIFT; 2537 } 2538 2539 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) 2540 gso_segs = skb_shinfo(skb)->gso_segs; 2541 else 2542 gso_segs = 1; 2543 2544 /* multiply data chunks by size of headers */ 2545 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len); 2546 first->gso_segs = gso_segs; 2547 first->skb = skb; 2548 first->tx_flags = tx_flags; 2549 2550 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 2551 2552 tx_desc = I40E_TX_DESC(tx_ring, i); 2553 tx_bi = first; 2554 2555 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 2556 if (dma_mapping_error(tx_ring->dev, dma)) 2557 goto dma_error; 2558 2559 /* record length, and DMA address */ 2560 dma_unmap_len_set(tx_bi, len, size); 2561 dma_unmap_addr_set(tx_bi, dma, dma); 2562 2563 tx_desc->buffer_addr = cpu_to_le64(dma); 2564 2565 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { 2566 tx_desc->cmd_type_offset_bsz = 2567 build_ctob(td_cmd, td_offset, 2568 I40E_MAX_DATA_PER_TXD, td_tag); 2569 2570 tx_desc++; 2571 i++; 2572 if (i == tx_ring->count) { 2573 tx_desc = I40E_TX_DESC(tx_ring, 0); 2574 i = 0; 2575 } 2576 2577 dma += I40E_MAX_DATA_PER_TXD; 2578 size -= I40E_MAX_DATA_PER_TXD; 2579 2580 tx_desc->buffer_addr = cpu_to_le64(dma); 2581 } 2582 2583 if (likely(!data_len)) 2584 break; 2585 2586 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, 2587 size, td_tag); 2588 2589 tx_desc++; 2590 i++; 2591 if (i == tx_ring->count) { 2592 tx_desc = I40E_TX_DESC(tx_ring, 0); 2593 i = 0; 2594 } 2595 2596 size = skb_frag_size(frag); 2597 data_len -= size; 2598 2599 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 2600 DMA_TO_DEVICE); 2601 2602 tx_bi = &tx_ring->tx_bi[i]; 2603 } 2604 2605 /* Place RS bit on last descriptor of any packet that spans across the 2606 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline. 2607 */ 2608 if (((i & WB_STRIDE) != WB_STRIDE) && 2609 (first <= &tx_ring->tx_bi[i]) && 2610 (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) { 2611 tx_desc->cmd_type_offset_bsz = 2612 build_ctob(td_cmd, td_offset, size, td_tag) | 2613 cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP << 2614 I40E_TXD_QW1_CMD_SHIFT); 2615 } else { 2616 tx_desc->cmd_type_offset_bsz = 2617 build_ctob(td_cmd, td_offset, size, td_tag) | 2618 cpu_to_le64((u64)I40E_TXD_CMD << 2619 I40E_TXD_QW1_CMD_SHIFT); 2620 } 2621 2622 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev, 2623 tx_ring->queue_index), 2624 first->bytecount); 2625 2626 /* Force memory writes to complete before letting h/w 2627 * know there are new descriptors to fetch. (Only 2628 * applicable for weak-ordered memory model archs, 2629 * such as IA-64). 2630 */ 2631 wmb(); 2632 2633 /* set next_to_watch value indicating a packet is present */ 2634 first->next_to_watch = tx_desc; 2635 2636 i++; 2637 if (i == tx_ring->count) 2638 i = 0; 2639 2640 tx_ring->next_to_use = i; 2641 2642 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); 2643 /* notify HW of packet */ 2644 if (!skb->xmit_more || 2645 netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev, 2646 tx_ring->queue_index))) 2647 writel(i, tx_ring->tail); 2648 else 2649 prefetchw(tx_desc + 1); 2650 2651 return; 2652 2653 dma_error: 2654 dev_info(tx_ring->dev, "TX DMA map failed\n"); 2655 2656 /* clear dma mappings for failed tx_bi map */ 2657 for (;;) { 2658 tx_bi = &tx_ring->tx_bi[i]; 2659 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); 2660 if (tx_bi == first) 2661 break; 2662 if (i == 0) 2663 i = tx_ring->count; 2664 i--; 2665 } 2666 2667 tx_ring->next_to_use = i; 2668 } 2669 2670 /** 2671 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed 2672 * @skb: send buffer 2673 * @tx_ring: ring to send buffer on 2674 * 2675 * Returns number of data descriptors needed for this skb. Returns 0 to indicate 2676 * there is not enough descriptors available in this ring since we need at least 2677 * one descriptor. 2678 **/ 2679 #ifdef I40E_FCOE 2680 inline int i40e_xmit_descriptor_count(struct sk_buff *skb, 2681 struct i40e_ring *tx_ring) 2682 #else 2683 static inline int i40e_xmit_descriptor_count(struct sk_buff *skb, 2684 struct i40e_ring *tx_ring) 2685 #endif 2686 { 2687 unsigned int f; 2688 int count = 0; 2689 2690 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, 2691 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, 2692 * + 4 desc gap to avoid the cache line where head is, 2693 * + 1 desc for context descriptor, 2694 * otherwise try next time 2695 */ 2696 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 2697 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 2698 2699 count += TXD_USE_COUNT(skb_headlen(skb)); 2700 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { 2701 tx_ring->tx_stats.tx_busy++; 2702 return 0; 2703 } 2704 return count; 2705 } 2706 2707 /** 2708 * i40e_xmit_frame_ring - Sends buffer on Tx ring 2709 * @skb: send buffer 2710 * @tx_ring: ring to send buffer on 2711 * 2712 * Returns NETDEV_TX_OK if sent, else an error code 2713 **/ 2714 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, 2715 struct i40e_ring *tx_ring) 2716 { 2717 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; 2718 u32 cd_tunneling = 0, cd_l2tag2 = 0; 2719 struct i40e_tx_buffer *first; 2720 u32 td_offset = 0; 2721 u32 tx_flags = 0; 2722 __be16 protocol; 2723 u32 td_cmd = 0; 2724 u8 hdr_len = 0; 2725 int tsyn; 2726 int tso; 2727 if (0 == i40e_xmit_descriptor_count(skb, tx_ring)) 2728 return NETDEV_TX_BUSY; 2729 2730 /* prepare the xmit flags */ 2731 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) 2732 goto out_drop; 2733 2734 /* obtain protocol of skb */ 2735 protocol = vlan_get_protocol(skb); 2736 2737 /* record the location of the first descriptor for this packet */ 2738 first = &tx_ring->tx_bi[tx_ring->next_to_use]; 2739 2740 /* setup IPv4/IPv6 offloads */ 2741 if (protocol == htons(ETH_P_IP)) 2742 tx_flags |= I40E_TX_FLAGS_IPV4; 2743 else if (protocol == htons(ETH_P_IPV6)) 2744 tx_flags |= I40E_TX_FLAGS_IPV6; 2745 2746 tso = i40e_tso(tx_ring, skb, &hdr_len, 2747 &cd_type_cmd_tso_mss, &cd_tunneling); 2748 2749 if (tso < 0) 2750 goto out_drop; 2751 else if (tso) 2752 tx_flags |= I40E_TX_FLAGS_TSO; 2753 2754 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss); 2755 2756 if (tsyn) 2757 tx_flags |= I40E_TX_FLAGS_TSYN; 2758 2759 if (i40e_chk_linearize(skb, tx_flags)) 2760 if (skb_linearize(skb)) 2761 goto out_drop; 2762 2763 skb_tx_timestamp(skb); 2764 2765 /* always enable CRC insertion offload */ 2766 td_cmd |= I40E_TX_DESC_CMD_ICRC; 2767 2768 /* Always offload the checksum, since it's in the data descriptor */ 2769 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2770 tx_flags |= I40E_TX_FLAGS_CSUM; 2771 2772 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, 2773 tx_ring, &cd_tunneling); 2774 } 2775 2776 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, 2777 cd_tunneling, cd_l2tag2); 2778 2779 /* Add Flow Director ATR if it's enabled. 2780 * 2781 * NOTE: this must always be directly before the data descriptor. 2782 */ 2783 i40e_atr(tx_ring, skb, tx_flags, protocol); 2784 2785 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len, 2786 td_cmd, td_offset); 2787 2788 return NETDEV_TX_OK; 2789 2790 out_drop: 2791 dev_kfree_skb_any(skb); 2792 return NETDEV_TX_OK; 2793 } 2794 2795 /** 2796 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer 2797 * @skb: send buffer 2798 * @netdev: network interface device structure 2799 * 2800 * Returns NETDEV_TX_OK if sent, else an error code 2801 **/ 2802 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 2803 { 2804 struct i40e_netdev_priv *np = netdev_priv(netdev); 2805 struct i40e_vsi *vsi = np->vsi; 2806 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping]; 2807 2808 /* hardware can't handle really short frames, hardware padding works 2809 * beyond this point 2810 */ 2811 if (skb_put_padto(skb, I40E_MIN_TX_LEN)) 2812 return NETDEV_TX_OK; 2813 2814 return i40e_xmit_frame_ring(skb, tx_ring); 2815 } 2816